IPC-7095B Design and Assembly Process Implementation for BGAs March 2008
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IPC-7095B ®
Design and Assembly Process Implementation for BGAs
Developed by the Device Manufacturers Interface Committee of IPC
Supersedes: IPC-7095A - October 2004 IPC-7095 - August 2000
Users of this publication are encouraged to participate in the development of future revisions. Contact: IPC 3000 Lakeside Drive, Suite 309S Bannockburn, Illinois 60015-1249 Tel 847 615.7100 Fax 847 615.7105
This Page Intentionally Left Blank
March 2008
IPC-7095B
Acknowledgment Any document involving a complex technology draws material from a vast number of sources. While the principal members of the IPC Ball Grid Array Task Group (5-21f) of the Assembly & Joining Processes Committee (5-20) are shown below, it is not possible to include all of those who assisted in the evolution of this standard. To each of them, the members of the IPC extend their gratitude. Assembly & Joining Processes Committee
Ball Grid Array Task Group
Technical Liaisons of the IPC Board of Directors
Chair Leo P. Lambert EPTAC Corporation
Chair Ray Prasad Ray Prasad Consultancy Group
Peter Bigelow IMI Inc.
Vice Chair Renee J. Michalkiewicz Trace Laboratories - East
Sammy Yi Flextronics International
Ball Grid Array Task Group
David Adams, Rockwell Collins
Robert Rowland, RadiSys
Syed Ahmad, NDSU
Constantin Hudon, Varitron Technologies
Dudi Amir, Intel Corporation
Greg Hurst, BAE Systems
Waleed Rusheidat, Jabil Circuit
Raiyomand Aspandiar, Intel Corporation
Glen Leinbach, Agilent Technologies Paul Lotosky, Cookson Electronics
Marty Scionti, Raytheon Missile Systems
David Brown, Lockheed Martin Aeronautics
Helen Lowe, Celestica
Gregory Servis, Lockheed Martin
Robert Mazium, Phoenix/X-Ray
Lyle Burhenn, BAE Systems Scott Buttars, Intel Corporation
Karen McConnell, Lockheed Martin EPICenter
Vern Solberg, Solberg Technical Consulting
Beverley Christian, Research in Motion Ltd.
George Milad, Uyemura In’l Corporation
Geoffrey Dick, Lockheed Martin Allen Donaldson, Intel Corporation
Jim Moffit, Moffit Consulting Services
Don Dupriest, Lockheed Martin Missiles and Fire Control
Barry Morris, Advanced Rework Technology
Werner Engelmaier, Engelmaier Associates
George Oxx, Flextronics Technology Inc.
Gary Ferrari, FTG Circuits
Deepak Pai, General Dynamics Adv Info Sys
Joe Fjelstad, SiliconPipe Inc. Lionel Fullwood, WKK Distribution Mahendra Gandhi, Northrop Grumman Space Technology Hue Green, Lockheed Martin Space Systems Mike Green, Lockheed Martin Space Systems
Jim Rudig, Intel Corporation
Kerry Spencer, Lockheed Martin Missle & Fire Control Dung Tiet, Lockheed Martin Space Systems Neil Trelford, Nortel Kris Troxel, Hewlett Packard Dave Vanacek, Lockheed Martin Aeronautics Sharon Ventress, U.S. Army Aviation & Missile Rob Walls, PIEK
Mel Parrish, Soldering Technology International
Dewey Whittaker, Honeywell Aerospace
Sam Polk, Lockheed Martin Missiles and Fire Control
Linda Woody, Lockheed Martin
Ray Prasad, Ray Prasad Consultancy Group Guy Ramsey, R&D Assembly
Fonda Wu, Raytheon Electronics Systems Michael Yuen, Microsoft Corp. Gil Zweig, Glenbrook Technologies
Teresa Rowe, AAI Corporation
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A special note of thanks goes to the following individuals for their dedication to bringing this project to fruition. We would like to highlight those individuals who made major contributions to the development of this standard.
Dudi Amir, Intel Corporation
Mike Green, Lockheed Martin Space Systems
Raiyomand Aspandiar, Intel Corporation
Helen Lowe, Celestica
Scott Buttars, Intel Corporation Werner Engelmaier, Engelmaier Associates
Karen McConnell, Lockheed Martin EPICenter
Robert Rowland, RadiSys Vern Solberg, Solberg Technical Consulting Kris Troxel, Hewlett Packard
Ray Prasad, Ray Prasad Consultancy Group
Front and back cover photos courtesy of RadiSys Corporation
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Table of Contents 1
1.1 1.2
4.3.1
Industry Standards for BGA .............................. 16
Purpose ................................................................. 1 Intent .................................................................... 1
4.3.2 4.3.3 4.3.4 4.3.5 4.4
Ball Pitch ........................................................... BGA Package Outline ....................................... Ball Size Relationships ...................................... Coplanarity ......................................................... Component Packaging Style Considerations ....
4.4.1 4.4.2
Solder Ball Alloy ............................................... 20 Ball Attach Process ............................................ 20
4.4.3 4.4.4
Ceramic Ball Grid Array ................................... 21 Ceramic Column Grid Arrays ........................... 21
4.4.5 4.4.6 4.4.7 4.4.8 4.4.9
Tape Ball Grid Arrays ....................................... Multiple Die Packaging ..................................... System-in-Package (SiP) ................................... 3D Folded Package Technology ........................ Ball Stack, Package-on-Package .......................
APPLICABLE DOCUMENTS .................................... 1
2
2.1 2.2 3
SCOPE ...................................................................... 1
IPC ....................................................................... 1 JEDEC .................................................................. 1 SELECTION CRITERIA AND MANAGING BGA IMPLEMENTATION .......................................... 2
3.1 3.1.1 3.1.2 3.1.3
Description of Infrastructure ............................... Land Patterns and Circuit Board Considerations ...................................................... Technology Comparison ...................................... Assembly Equipment Impact ..............................
3.1.4 3.1.5 3.1.6
Stencil Requirements ........................................... 7 Inspection Requirements ..................................... 8 Test ....................................................................... 8
3.2 3.3 3.4 3.5 3.5.1
Time-to-Market Readiness .................................. Methodology ........................................................ Process Step Analysis .......................................... BGA Limitations and Issues ............................... Visual Inspection .................................................
3.5.2 3.5.3
Moisture Sensitivity ............................................. 9 Thermally Unbalanced BGA Design ................ 10
3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9
Rework ............................................................... 10 Cost .................................................................... 11 Availability ......................................................... 12 Voids in BGA ..................................................... 12 Standardization Issues ....................................... 12 Reliability Concerns .......................................... 12
4
3 3 5 7
8 9 9 9 9
17 18 19 19 19
22 22 23 23 23
4.4.10 Folded and Stacked Packaging Combination ... 24 4.4.11 4.5 4.5.1 4.5.2
Benefits of Multiple Die Packaging .................. BGA Connectors ................................................ Material Considerations for BGA Connectors .. Attachment Considerations for BGA Connectors ................................................
24 24 24
4.6 4.6.1 4.6.2 4.7 4.7.1
BGA Construction Materials ............................. Types of Substrate Materials ............................. Properties of Substrate Materials ...................... BGA Package Design Considerations ............... Power and Ground Planes .................................
25 25 26 27 27
4.7.2 4.7.3
Signal Integrity .................................................. 28 Heat Spreader Incorporation Inside the Package ........................................................ 28 BGA Package Acceptance Criteria and Shipping Format ................................................ 28
4.8
COMPONENT CONSIDERATIONS ........................ 12
25
4.8.1
Missing Balls ..................................................... 28
4.8.2
Voids in Solder Balls ......................................... 28
4.1.1 4.1.2
Component Packaging Comparisons and Drivers ......................................................... 12 Package Feature Comparisons ........................... 12 BGA Package Drivers ....................................... 13
4.8.3
Solder Ball Attach Integrity .............................. 29
4.8.4
Package Coplanarity .......................................... 29
4.1.3 4.1.4
Cost Issues ......................................................... 13 Component Handling ......................................... 13
4.8.5
Moisture Sensitivity (Baking, Storage, Handling, Rebaking) .......................................... 30
4.1.5
Thermal Performance ........................................ 13
4.8.6
4.1.6
Real Estate ......................................................... 13
Shipping Medium (Tape and Reel, Trays, Tubes) ..................................................... 30
4.1.7
Electrical Performance ....................................... 14
4.8.7
Solder Ball Alloy ............................................... 31
4.2
Die Mounting in the BGA Package .................. 14
5
4.2.1
Wire Bond .......................................................... 14
5.1
Types of Mounting Structures ........................... 31
4.2.2
Flip Chip ............................................................ 15
5.1.1
Organic Resin Systems ...................................... 31
Standardization ................................................... 16
5.1.2
Inorganic Structures ........................................... 31
4.1
4.3
PCBS AND OTHER MOUNTING STRUCTURES .. 31
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5.1.3 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.3 5.3.1 5.3.2
Layering (Multilayer, Sequential or Build-Up) ....................................................... Properties of Mounting Structures .................... Resin Systems .................................................... Reinforcements .................................................. Laminate Material Properties ............................ Reliability Concerns with High Lead-Free Soldering Temperatures ..................................... Thermal Expansion ............................................ Glass Transition Temperature ............................ Moisture Absorption .......................................... Surface Finishes ................................................. Hot Air Solder Leveling (HASL) .....................
March 2008
31 31 31 33 33 33 33 33 34 34 34
5.3.3
Organic Surface Protection (Organic Solderability Preservative) OSP Coatings ........ 37 Noble Platings/Coatings .................................... 37
5.4 5.4.1 5.4.2
Solder Mask ....................................................... 40 Wet and Dry Film Solder Masks ...................... 41 Photoimageable Solder Masks .......................... 41
5.4.3 5.4.4
Registration ........................................................ 42 Via Protection .................................................... 42
5.5
Thermal Spreader Structure Incorporation (e.g., Metal Core Boards) .................................. 44
5.5.1
Lamination Sequences ....................................... 44
5.5.2
Heat Transfer Pathway ...................................... 44
6
PRINTED CIRCUIT ASSEMBLY DESIGN CONSIDERATION .................................... 46
6.4
Impact of Wave Solder on Top Side BGAs ..... 57
6.4.1 6.4.2
Top Side Reflow ................................................ 57 Impact of Top Side Reflow ............................... 57
6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.6
Methods of Avoiding Top Side Reflow ............ Top Side Reflow for Lead-Free Boards ............ Testability and Test Point Access ...................... Component Testing ............................................ Damage to the Solder Balls During Test and Burn-In ........................................................ Bare Board Testing ............................................ Assembly Testing ............................................... Other Design for Manufacturability Issues .......
60 61 61 64
6.6.1 6.6.2 6.7 6.7.1 6.7.2 6.7.3 6.7.4
Panel/Subpanel Design ...................................... In-Process/End Product Test Coupons .............. Thermal Management ........................................ Conduction ......................................................... Radiation ............................................................ Convection ......................................................... Thermal Interface Materials ..............................
64 64 65 65 66 67 67
6.7.5 6.8
Heat Sink Attachment Methods for BGAs ....... 67 Documentation and Electronic Data Transfer ... 69
6.8.1 6.8.2 6.8.3
Drawing Requirements ...................................... 69 Equipment Messaging Protocols ....................... 70 Specifications ..................................................... 71
7
58 59 59 59
ASSEMBLY OF BGAS ON PRINTED CIRCUIT BOARDS .................................................. 71
6.1
Component Placement and Clearances ............. 46
7.1
SMT Assembly Processes .................................. 71
6.1.1
Pick and Place Requirements ............................ 46
7.1.1
Solder Paste and Its Application ....................... 71
6.1.2
Repair/Rework Requirements ............................ 46
7.1.2
Component Placement Impact ........................... 73
6.1.3
Global Placement ............................................... 47
7.1.3
Vision Systems for Placement ........................... 73
6.1.4
Alignment Legends (Silkscreen, Copper Features, Pin 1 Identifier) .................................. 47
7.1.4
Reflow Soldering and Profiling ......................... 74
7.1.5
Material Issues ................................................... 78
6.2
Attachment Sites (Land Patterns and Vias) ...... 48
7.1.6
Vapor Phase ....................................................... 78
6.2.1
Big vs. Small Land and Impact on Routing ..... 48
7.1.7
Cleaning vs. No-Clean ...................................... 79
6.2.2
Solder Mask vs. Metal Defined Land Design .. 48
7.1.8
Package Standoff ............................................... 79
6.2.3
Conductor Width ................................................ 50
7.2
Post-SMT Processes .......................................... 80
6.2.4
Via Size and Location ....................................... 50
7.2.1
Conformal Coatings ........................................... 80
6.3
Escape and Conductor Routing Strategies ........ 51
7.2.2
Use of Underfills and Adhesives ....................... 81
6.3.1
Escape Strategies ............................................... 53
7.2.3
Depaneling of Boards and Modules ................. 84
6.3.2
Surface Conductor Details ................................. 54
7.3
Inspection Techniques ........................................ 84
6.3.3
Dog Bone Through Via Details ........................ 54
7.3.1
X-Ray Usage ...................................................... 84
6.3.4
Design for Mechanical Strain ........................... 54
7.3.2
X-Ray Image Acquisition .................................. 85
6.3.5
Uncapped Via-in-Pad and Impact on Reliability Issues ................................................ 55
7.3.3
Definition and Discussion of X-Ray System Terminology .......................................... 86
6.3.6
Fine Pitch BGA Microvia in Pad Strategies ..... 56
7.3.4
Analysis of the X-Ray Image ........................... 88
Power and Ground Connectivity ....................... 57
7.3.5
Scanning Acoustic Microscopy ......................... 90
6.3.7 vi
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7.3.6 7.3.7 7.3.8 7.4 7.4.1
BGA Standoff Measurement ............................. Optical Inspection .............................................. Destructive Analysis Methods ........................... Testing and Product Verification ....................... Electrical Testing ...............................................
90 90 92 93 93
8.5.4 8.5.5 8.6 8.7
Reliability of Solder Attachments of Ceramic Grid Array .................................... Lead-Free Soldering of BGAs ........................ Design for Reliability (DfR) Process .............. Validation and Qualification Tests ..................
7.4.2 7.4.3 7.4.4 7.5
8.8 8.8.1 8.8.2
Screening Procedures ....................................... 128 Solder Joint Defects ......................................... 128 Screening Recommendations ........................... 128
7.5.1 7.5.2 7.5.3 7.5.4
Test Coverage .................................................... 94 Burn-In Testing .................................................. 94 Product Screening Tests .................................... 94 Assembly Process Control Criteria for Plastic BGAs ...................................................... 94 Voids ................................................................... 95 Solder Bridging ................................................ 106 Opens ............................................................... 106 Cold Solder ...................................................... 106
7.5.5 7.5.6
Defect Correlation/Process Improvement ....... 106 Insufficient/Uneven Heating ............................ 107
7.5.7
Component Defects ......................................... 107
7.6
Repair Processes .............................................. 108
7.6.1
Rework/Repair Philosophy .............................. 108
7.6.2
Removal of BGA ............................................. 108
7.6.3
Replacement ..................................................... 109
8
RELIABILITY ......................................................... 111
9
121 121 127 128
DEFECT AND FAILURE ANALYSIS CASE STUDIES .................................................... 129
9.1 9.1.1
Solder Mask Defined BGA Conditions ........... 129 Solder Mask Defined and Nondefined Lands . 129
9.1.2
Solder Mask Defined Land on Product Board .................................................. 129 Solder Mask Defined BGA Failures ............... 130
9.1.3 9.2 9.2.1 9.2.2 9.2.3
Over-Collapse BGA Solder Ball Conditions .. BGA Ball Shape without Heat Slug 500 µm Standoff Height ................................................ BGA Ball Shape with Heat Slug 375 µm Standoff Height ................................................ BGA Ball Shape with Heat Slug 300 µm Standoff Height ................................................
130 130 130 131
9.2.4 9.2.5 9.2.6
Critical Solder Paste Conditions ..................... 131 Thicker Paste Deposit ...................................... 131 Void Determination Through X-Ray and Cross-Section ................................................... 131
9.2.7 9.2.8 9.3 9.3.1
Voids and Uneven Solder Balls ...................... Eggshell Void ................................................... BGA Interposer Bow and Twist ...................... BGA Interposer Warp ......................................
9.3.2 9.4 9.4.1
Solder Joint Opens Due to Interposer Warp ... 133 Solder Joint Conditions ................................... 133 Target Solder Condition .................................. 134
9.4.2 9.4.3 9.4.4 9.4.5 9.4.6
Solder Balls With Excessive Oxide ................ Evidence of Dewetting .................................... Mottled Condition ............................................ Tin/lead Solder Ball Evaluation ......................
SAC Alloy ........................................................ 135
9.4.7
Cold Solder Joint ............................................. 135
9.4.8
Incomplete Joining Due to Land Contamination .................................................. 135 Deformed Solder Ball Contamination ............. 136
8.1
Accelerated Reliability Testing ........................ 111
8.2
Damage Mechanisms and Failure of Solder Attachments .......................................... 112
8.2.1
Comparison of Thermal Fatigue Crack Growth Mechanism in SAC vs. Tin/ Lead BGA Solder Joints .................................. 113
8.2.2
Mixed Alloy Soldering .................................... 113
8.3
Solder Joints and Attachment Types ............... 115
8.3.1
Global Expansion Mismatch ........................... 116
8.3.2
Local Expansion Mismatch ............................. 116
8.3.3
Internal Expansion Mismatch .......................... 116
8.4
Solder Attachment Failure ............................... 116
8.4.1
Solder Attachment Failure Classification ........ 116
8.4.2
Failure Signature-1: Cold Solder .................... 117
8.4.3
Failure Signature-2: Land, Nonsolderable ..... 117
8.4.4
Failure Signature-3: Ball Drop ....................... 117
8.4.5
Failure Signature-4: Missing Ball .................. 118
8.4.6
Failure Signature-5: Package Warpage ........... 118
9.4.9
8.4.7
Failure Signature-6: Mechanical Failure ........ 118
9.4.10 Deformed Solder Ball ...................................... 136
8.4.8
Failure Signature-7: Insufficient Reflow ......... 119
8.5
Critical Factors to Impact Reliability .............. 119
9.4.11 Insufficient Solder and Flux for Proper Joint Formation ................................................ 136
8.5.1
Package Technology ........................................ 119
9.4.12 Reduced Termination Contact Area ................ 136
8.5.2
Stand-off Height ............................................... 120
9.4.13 Excessive Solder Bridging .............................. 137
8.5.3
PCB Design Considerations ............................ 121
9.4.14 Incomplete Solder Reflow ............................... 137
132 132 132 133
134 134 134 135
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9.4.15 Disturbed Solder Joint ..................................... 137 9.4.16 Missing Solder ................................................. 137
Figure 4-18
BGA connector ............................................... 25
Figure 4-19
Example of missing balls on a BGA component ...................................................... 28
10
GLOSSARY AND ACRONYMS .......................... 138
Figure 4-20
11
BIBLIOGRAPHY AND REFERENCES ............... 139
Example of voids in eutectic solder balls at incoming inspection ........................................ 29
Figure 4-21
Examples of solder ball/land surface conditions ........................................................ 29
Figure 4-22
Establishing BGA coplanarity requirement ..... 30 Ball contact positional tolerance ..................... 30
Figures Figure 3-1
BGA package manufacturing process .............. 2
Figure 4-23
Figure 3-2
Area array I/O position comparisons ................ 4
Figure 5-1
Examples of different build-up constructions . 32
Figure 3-3
Area array I/O position patterns ....................... 5
Figure 5-2
Expansion rate above Tg ................................ 34
Figure 3-4
MCM type 2S-L-WB ......................................... 5
Figure 5-3
Figure 3-5
Conductor width to pitch relationship ............... 7
Hot air solder level (HASL) surface topology comparison ..................................................... 36
Figure 3-6
Plastic ball grid array, chip wire bonded .......... 8
Figure 5-4
Black pad related fracture showing crack between Nickel & Ni-Sn intermetallic layer .... 38
Figure 3-7
Ball grid array, flip chip bonded ........................ 8
Figure 5-5
Figure 3-8
BGA warpage .................................................. 11
Figure 4-1
Partial area under the die is used to provide ground for the die. The rest of the area has been used for signal routing but has been covered with solder mask to isolate it from the conductive adhesive under the die. ......... 14
Crack location for a) black pad related failure and (b) interfacial fracture when using ENIG surface finish .................................................. 38
Figure 5-6
Typical mud crack appearance of black pad Surface ........................................................... 39
Figure 5-7
A large region of severe black pad with corrosion spikes protruding into nickel rich layer through phosphorus rich layer underneath immersion gold surface ............... 39
Figure 5-8
Graphic depiction of electroless nickel, electroless palladium/immersion gold ............ 40
Figure 5-9
Graphic depiction of directed immersion gold ................................................................. 40
Figure 5-10
Work and turn panel layout ............................ 43
Figure 5-11
Distance from tented land clearance ............. 43
Figure 5-12
Via plug methods ............................................ 45
Figure 5-13
Solder filled and tented via blow-out .............. 46
Figure 5-14
Metal core board construction examples ....... 46
Figure 6-1
BGA alignment marks ..................................... 47
Figure 6-2
Solder lands for BGA components ................. 49
Figure 6-3
Metal defined land attachment profile ............ 49
Figure 6-4
Solder mask stress concentration .................. 49
Figure 6-5
Solder joint geometry contrast ....................... 49 Good/bad solder mask design ....................... 50
Figure 4-2
Use of glass die to optimize the adhesive dispensing process for void-free controlled fill and squeeze-out. The picture on the top shows the adhesive dispense pattern on the die site. The picture on the bottom shows the placed glass die to view voids and filling characteristics. The adhesive provides full die coverage for attachment but partial coverage to ground through a smaller than die ground pad, allowing a larger portion of the area under the die for signal routing saving valuable real estate and making the resulting package smaller. .............................. 15
Figure 4-3
BOC BGA construction ................................... 15
Figure 4-4
Top of molded BOC type BGA ....................... 16
Figure 4-5
Flip-chip (bumped die) on BGA substrate ...... 16
Figure 4-6
Plastic ball grid array (BGA) package ............ 21
Figure 4-7
Cross-section of a ceramic ball grid array (CBGA) package ............................................ 21
Figure 4-8
Ceramic ball grid array (CBGA) package ...... 21
Figure 6-6
Figure 4-9
Cross-section of a ceramic column grid array (CCGA) package ................................... 21
Figure 6-7
Examples of metal-defined land ..................... 50
Figure 6-8
Quadrant dog bone BGA pattern ................... 51
Polyimide film based lead-bond µBGA package substrate furnishes close coupling between die pad and ball contact .................. 22
Figure 6-9
Square array ................................................... 52
Figure 6-10
Rectangular array ........................................... 52
Comparing in-package circuit routing capability of the single metal layer tape substrate to two metal layer tape substrate ... 22
Figure 6-11
Depopulated array .......................................... 52
Figure 6-12
Square array with missing balls ..................... 52
Figure 6-13
Interspersed array .......................................... 53
Figure 4-12
Single package die-stack BGA ....................... 23
Figure 6-14
Conductor routing strategy ............................. 53
Figure 4-13
Custom eight die (flip-chip and wire-bond) SiP assembly .................................................. 23
Figure 6-15
BGA dogbone land pattern preferred direction for conductor routing ........................ 55
Figure 4-14
Folded multiple-die BGA package .................. 23
Figure 6-16
Preferred screw and support placement ........ 55
Figure 4-15
Package-on-package FBGA ........................... 24
Figure 6-17
Connector screw support placement .............. 55
Figure 4-16
SO-DIMM memory card assembly ................. 24
Figure 6-18
Figure 4-17
Folded and stacked multiple die BGA package .................................................. 24
Cross section of 0.75 mm ball with via-inpad structure (Indent to the upper left of the ball is anartifact.) ...................................... 55
Figure 4-10
Figure 4-11
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Figure 6-19
Cross section of via-in-pad design showing via cap and solder ball ................................... 55
Figure 6-20
Via-in-pad process descriptions ..................... 56
Figure 6-21
Microvia example ............................................ 56
Figure 6-22
Microvia in pad voiding ................................... 57
Figure 6-23 Figure 6-24
Figure 7-12
Examples of underfill voids - small, medium and large; upper left, lower left and left of solder balls, respectively ................................ 82
Figure 7-13
Example of partial underfill - package was pulled from the PCB and dark underfill can be seen in the corners ................................... 82
Ground or power BGA connection ................. 57
Figure 7-14
Corner applied adhesive ................................ 83
Example of top side reflow joints ................... 57
Figure 7-15
Figure 6-25
Example of wave solder temperature profile of top-aide of mixed component assembly .... 58
Critical dimension for application of prereflow corner glue ...................................... 83
Figure 7-16
Figure 6-26
Heat pathways to BGA solder joint during wave soldering ................................................ 58
Figure 6-27
Methods of avoiding BGA topside solder joint reflow ...................................................... 59
Typical corner glue failure mode in shock if glue area is too low - Solder mask rips off board and does not protect the solder joints ............................................................... 83
Figure 7-17
Fundamentals of X-ray technology ................ 85
Figure 7-18
X-ray example of missing solder balls ........... 85
Figure 7-19
X-ray example of voiding in solder ball contacts .......................................................... 85
Figure 7-20
Manual X-ray system image quality ............... 86
Figure 7-21
Example of X-ray pin cushion distortion and voltage blooming ..................................... 86
Figure 6-28
An example of a side contact made with a tweezers type contact ..................................... 60
Figure 6-29
Pogo-pin type electrical contact impressions on the bottom of a solder ball ........................ 60
Figure 6-30
Area array land pattern testing ....................... 62
Figure 6-31
Board panelization .......................................... 65
Figure 6-32
Comb pattern examples ................................. 66
Figure 7-22
Transmission image (2D) ............................... 86
Figure 6-33
Heat sink attached to a BGA with an adhesive .................................................... 68
Figure 7-23
Tomosynthesis image (3D) ............................. 87
Figure 6-34
Heat sink attached to a BGA with a clip that hooks onto the component substrate ...... 68
Figure 7-24
Laminographic cross-section image (3D) ....... 87
Figure 7-25
Transmission example .................................... 87
Figure 7-26
Oblique viewing board tilt ............................... 88
Figure 7-27
Oblique viewing detector tilt ........................... 88
Figure 7-28
Top down view of FBGA solder joints ............ 88
Figure 7-29
Oblique view of FBGA solder joints ............... 88
Figure 7-30
Tomosynthesis ................................................ 89
Heat sink attached to a BGA by wave soldering its pins in a through-hole in the printed circuit board .................................. 69
Figure 7-31
Scanned beam X-ray laminography ............... 89
Figure 7-32
Scanning acoustic microscopy ....................... 91
Figure 7-1
Aspect and area ratios for complete paste release ............................................................ 72
Figure 7-33
Endoscope example ....................................... 91
Figure 7-34
Figure 7-2
High lead and eutectic solder ball and joint comparison ..................................................... 73
Lead-free 1.27 mm pitch BGA reflowed in nitrogen and washed between SMT passes ............................................................ 91
Figure 7-3
Example of peak reflow temperatures at various locations at or near a BGA ................ 74
Figure 7-35
Lead-free BGA reflowed in air and washed between SMT passes ..................................... 92
Figure 7-4
Schematic of reflow profile for tin/lead assemblies ...................................................... 75
Figure 7-36
Engineering crack evaluation technique ........ 93
Figure 7-37
A solder ball cross sectioned through a void in the solder ball ..................................... 93
Figure 7-38
Cross-section of a crack initiation at the ball/pad interface ............................................ 93
Figure 7-39
No dye penetration under the ball .................. 94
Figure 7-40
Corner balls have 80-100% dye penetration which indicate a crack .................................... 94
Figure 7-41
Locations of thermocouples on a board with large and small components ................... 77
Small voids clustered in mass at the ball-toland interface .................................................. 96
Figure 7-42
Recommended locations of thermocouples on a BGA ........................................................ 77
X-ray image of solder balls with voids at 50 kV (a) and 60 kV (b) ................................. 97
Figure 7-43
Effect of having solder mask relief around the BGA lands of the board ............................ 80
Typical size and location of various types of voids in a BGA solder joint ......................... 98
Figure 7-44
Flow of underfill between two parallel surfaces .......................................................... 82
Example of voided area at land and board Interface .......................................................... 98
Figure 7-45
Typical flow diagram for void assessment ... 100
Figure 6-35
Figure 6-36
Figure 6-37
Heat sink attached to a BGA with a clip that hooks into a through-hole on the printed circuit board ........................................ 68 Heat sink attached to a BGA with a clip that hooks onto a stake soldered in the printed circuit board .................................................... 69
Figure 7-5
An example of tin/lead profile with multiple thermocouples ................................................ 76
Figure 7-6
Schematic of reflow profile for lead-free assemblies ...................................................... 76
Figure 7-7
Examples of lead-free profiles with soak (top) and ramp to peak (bottom) with multiple thermocouples. The profiles with soak tend to reduce voids in BGAs. ....... 76
Figure 7-8 Figure 7-9 Figure 7-10 Figure 7-11
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Figure 7-46
Voids in BGAs with crack started at corner lead .................................................... 104
Figure 7-47
Examples of suggested void protocols ........ 104
Figure 7-48
Void diameter related to land size ................ 105
Figure 7-49
X-ray image showing uneven heating .......... 107
Figure 7-50
X-ray image at 45° showing insufficient heating in one corner of the BGA ................ 107
Figure 7-51
X-ray image of popcorning ........................... 108
Figure 7-52
X-ray image showing warpage in a BGA ..... 108
Figure 7-53
BGA/assembly shielding examples .............. 109
Figure 8-1
BGA solder joint of eutectic tin/lead solder composition exhibiting lead rich (dark) phase and tin rich (light) phase grains ......... 113
Figure 8-2
Figure 8-3
Socket BGA solder joints of SnAgCu composition, showing the solder joint comprised of 6 grains (top photo) and a single grain (bottom photo). ....................... 113 Thermal-fatigue crack propagation in eutectic tin/lead solder joints in a CBGA module .......................................................... 114
Figure 8-21
Micrograph of a cross-section of a BGA SnAgCu solder ball, assembled onto a board with tin/lead solder paste using the standard tin/lead reflow soldering profile. The SnAgCu solder ball does not melt; black/grey interconnecting fingers are lead-rich grain boundaries; rod shape particles are Ag3Sn IMCs; grey particles are Cu6Sn5 IMCs. ...... 126
Figure 8-22
Micrograph of a cross-section of a BGA SnAgCu solder ball, assembled onto a board with tin/lead solder paste using a backward compatibility reflows soldering profile. The SnAgCu solder ball has melted. ................... 127
Tables Table 3-1
Multichip module definitions ................................ 5
Table 3-2
Number of escapes vs. array size on two layers of circuitry ................................................. 6
Table 3-3
Potential plating or component termination material properties ............................................ 10
Table 3-4
Semiconductor cost predictions ........................ 11 JEDEC Standard JEP95-1/5 allowable ball diameter variations for FBGA ............................ 17
Figure 8-4
Thermal-fatigue crack propagation in Sn-3.8Ag-0.7Cu joints in a CBGA module [3] ..................................................... 114
Table 4-1 Table 4-2
Ball diameter sizes for PBGAs ......................... 18
Figure 8-5
Incomplete solder joint formation for 1% Ag ball alloy assembled at low end of typical process window ................................. 115
Table 4-3
Future ball size diameters for PBGAs .............. 18
Table 4-4
Land size approximation ................................... 18
Solder joint failure due to silicon and board CTE mismatch .................................... 116
Table 4-5
Future land size approximation ......................... 18
Table 4-6
Land-to-ball calculations for current and future BGA packages (mm) .............................. 19
Table 4-7
Examples of JEDEC registered BGA outlines .............................................................. 19
Table 4-8
IPC-4101B FR-4 property summaries specification sheets projected to better withstand lead-free assembly ........................... 26 Typical properties of common dielectric materials for BGA package substrates ............. 27
Figure 8-6 Figure 8-7
Grainy appearing solder joint ........................ 117
Figure 8-8
Nonsolderable land (black pad) .................... 117
Figure 8-9
Land contamination (solder mask residue) .. 117
Figure 8-10
Solder ball down ........................................... 117
Figure 8-11
Missing solder ball ........................................ 118
Figure 8-12
Deformed solder joint due to BGA warping .. 118
Table 4-9
Figure 8-13
Two examples of pad cratering (located at corner of BGA) .............................................. 118
Table 4-10 Moisture classification level and floor life ......... 30
Pad crater under 1.0 mm pitch lead-free solder ball. Crack in metal trace connected to the land is clear; however, the pad crater is difficult to see in bright field microscopy. .. 119
Table 5-1
Environmental properties of common dielectric materials ............................................ 32
Table 5-2
Key attributes for various board surface finishes .............................................................. 35
Figure 8-15A Insufficient reflow temperature ...................... 119
Table 5-3
Figure 8-15B Cross-section photographs illustrating insufficient melting of solder joints during reflow soldering. These solder joints are located below the cam of a socket. ............. 120
Via filling/encroachment to surface finish process evaluation ............................................ 44
Table 5-4
Via fill options .................................................... 46
Table 6-1
Number of conductors between solder lands for 1.27 mm pitch BGAs ................................... 48
Table 6-2
Number of conductors between solder lands for 1.0 mm pitch BGAs ..................................... 48
Table 6-3
Maximum solder land to pitch relationship ....... 48
Table 6-4
Escape strategies for full arrays ....................... 53
Table 6-5
Conductor routing - 1.27 mm Pitch ................... 54
Table 6-6
Conductor routing - 1.0 mm Pitch ..................... 54
Table 6-7
Conductor routing - 0.8 mm Pitch ..................... 54
Table 6-8
Conductor routing - 1.27 mm Pitch ................... 54
Table 6-9
Conductor routing - 1.0 mm Pitch ..................... 54
Figure 8-14
Figure 8-16
Solder mask influence .................................. 121
Figure 8-17
Reliability test failure due to very large void ...................................................... 121
Figure 8-18
Comparison of a lead-free (SnAgCu) and tin/lead (SnPb) BGA reflow soldering profiles .......................................................... 125
Figure 8-19 Figure 8-20
x
Endoscope photo of a SnAgCu BGA solder ball ..................................................... 125 Comparison of reflow soldering profiles for tin/lead, backward compatibility and total lead-free board assemblies .......................... 126
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Table 6-10 Conductor routing - 0.8 mm Pitch ..................... 54 Table 6-11 Effects of material type on conduction ............. 66 Table 6-12 Emissivity ratings for certain materials ............. 66 Table 7-1
Particle size comparisons ................................. 72
Table 7-2
Solder paste volume requirements for ceramic array packages .................................... 73
Table 7-3
Profile comparison between SnPb and SAC alloys ......................................................... 75
Table 7-10 Ball-to-void size image - comparison for various ball diameters ..................................... 104 Table 7-11 C=0 sampling plan (sample size for specific index value*) ................................................... 106 Table 7-12 Repair process temperature profiles for tin lead assembly .................................................. 111 Table 7-13 Repair process temperature profiles for lead-free assemblies ........................................ 111 Table 8-1
Accelerated testing for end use environments ................................................... 112
Table 8-2
Tin/lead component compatibility with leadfree reflow soldering ........................................ 114 Typical stand-off heights for tin/lead balls (in mm) ................................................... 120
Table 7-4
Inspection usage application recommendations .............................................. 84
Table 7-5
Field of view for inspection ............................... 90
Table 7-6
Void classification .............................................. 97
Table 7-7
Corrective action indicator for lands used with 1.5, 1.27 or 1.0 mm pitch ........................ 101
Table 8-4
Common solders, their melting points, advantages and drawbacks ............................ 123
Table 7-8
Corrective action indicator for lands used with 0.8, 0.65 or 0.5 mm pitch ........................ 102
Table 8-5
Table 7-9
Corrective action indicator for microvia in pad lands used with 0.5, 0.4 or 0.3 mm pitch ................................................................. 103
Comparison of lead-free solder alloy compositions in the Sn-Ag-Cu family selection by various consortia ......................... 123
Table 8-6
Types of lead-free assemblies possible .......... 125
Table 8-3
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Design and Assembly Process Implementation for BGAs 1 SCOPE
This document describes the design and assembly challenges for implementing Ball Grid Array (BGA) and Fine Pitch BGA (FBGA) technology. The effect of BGA and FBGA on current technology and component types are addressed, as is the move to lead-free assembly processes. The focus on the information contained herein is on critical inspection, repair, and reliability issues associated with BGAs. Throughout this document the word ‘‘BGA’’ can mean all types and forms of ball/column grid array packages. 1.1 Purpose The target audiences for this document are managers, design and process engineers, and operators and technicians who deal with the electronic assembly, inspection, and repair processes. The intent is to provide useful and practical information to those who are using BGAs, those who are considering BGA implementation and companies who are in the process of transition from the standard tin/lead reflow processes to those that use lead-free materials in the assembly of BGA type components. 1.2 Intent The new challenge in implementing BGA assembly processes, along with other types of components, is the need to meet the legislative directives that declare certain materials as hazardous to the environment. The requirements to eliminate these materials from electronic components have caused component manufacturers to rethink the materials used for encapsulation, the plating finishes on the components and the metal alloys used in the assembly attachment process.
This document, although not a complete recipe, identifies many of the characteristics that influence the successful implementation of a robust assembly process. In many applications, the variation between assembly methods and materials is reviewed with the intent to highlight significant differences that relate to the quality and reliability of the final product. The accept/reject criteria for BGA assemblies, used in contractual agreements, is established by J-STD-001 and IPC-A-610.
J-STD-020 Handling Requirements for Moisture Sensitive Components J-STD-033 Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices IPC-T-50 Terms and Definitions for Printed Boards and Printed Board Assemblies
Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies
IPC-D-279
Documentation Requirements for Printed
IPC-D-325
Boards IPC-D-350
Printed Board Description in Digital Form
Bare Substrate Electrical Test Information in Digital Form
IPC-D-356
IPC-SM-785 Guidelines for Accelerated Reliability Testing of Surface Mount Attachments IPC-2221
Generic Standard on Printed Board Design
Generic Requirements for Implementation of Product Manufacturing Description Data and Transfer
IPC-2511
IPC-2581 Generic Requirements for Printed Board Assembly Products Manufacturing Description Data and Transfer Methodology IPC-7094 Design and Assembly Process Implementation for Flip Chip and Die Size Components IPC-7351 Generic Requirements for Surface Mount Design and Land Pattern Standard IPC-7525
Stencil Design Guidelines
IPC-7711/7721 Rework, Modification and Repair of Electronic Assemblies IPC-9701 Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments IPC/JEDEC-9704
2 APPLICABLE DOCUMENTS
Guideline
2.1 IPC1
2.2 JEDEC2
J-STD-001 Requirements for Soldered Electrical and Electronic Assemblies
Package (FBGA)
Printed Wiring Board Strain Gage Test
JEP95 Section 4.5
Fine Pitch (Square) Ball Grid Array
1. www.ipc.org 2. www.jedec.org
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Fine Pitch (Rectangular) Ball Grid Array Package (FRBGA)
3 SELECTION CRITERIA AND MANAGING BGA IMPLEMENTATION
Die-Size Ball Grid Array Package
Every electronic system consists of various parts: interfaces, electronic storage media, and the printed board assembly. Typically, the complexity of these systems is reflected in both the type of components used and their interconnecting structure. The more complex the components, as judged by the amount of input/output terminals they possess, the more complex is the interconnecting substrate. Cost and performance drivers have resulted in increased component density, and a greater number of components attached to a single assembly, while the available mounting real estate has shrunk. In addition, the number of functions per device has increased and this is accommodated by using increased I/O count and reduced contact pitch. Reduced contact pitch represents challenges for both assemblers and bare board manufacturers. Assemblers encounter handling, coplanarity and alignment problems.
JEP95 Section 4.6
JEP95 Section 4.7
(DSBGA) JEP95 Section 4.9 Generic Matrix Tray for Handling and Shipping (Low Stacking Profile for BGA Packages) JEP95 Section 4.10
Generic Matrix Tray for Handling and
Shipping JEP95 Section 4.14
Ball Grid Array Package (BGA)
JEP95 Section 4.17 Ball Grid Array (BGA) Package Measurement and Methodology JEP95 Section 4.22 Fine Pitch Square Ball Grid Array Package (FBGA) Package on Package (PoP) JESD22-A102
Unbiased Autoclave Test Method
JESD22-A103
High Temperature Storage Test Method
JESD22-A104
Thermal Shock Test Method
JESD22-A118
Accelerated Moisture Resistance-Unbiased
HAST JESD22-B103 JESD22-B110
Board-Level Vibration Test Method Subassembly Mechanical Shock Test
Method JESD22-B111
Start
Board-Level Drop Test Method
Known Good Die
Die Attach
Component packaging in general, microprocessor and memory packages in particular, drive the rest of the electronic assembly packaging issues. Figure 3-1 shows an example of the package manufacturing process. The driving forces for component packaging are thermal and electrical performance, real estate constraints and cost. Peripheral devices with 1.27 mm pitch have become commonplace in the industry. However, this package cannot accommodate higher than 84 pins. Larger peripheral pin count devices require lead pitches of 0.65 mm, 0.5 mm or 0.3 mm.
Wire Bond
Chip Attach using Flip Chip Process
Print Flux or Paste on GBA Substrate Lands
Perform Electrical Test
Place Balls on BGA Substrate Lands
Inspect
Mold Package Underfill Die
Ball Attach Reflow Balls on BGA Substrate Lands
Pack
Ship IPC-7095B-3-1
Figure 3-1
2
BGA package manufacturing process
March 2008
Although pitches below 1.27 mm are useful for reducing package size, the increased density presents many problems for most manufacturers. At these fine-pitches, leads are very fragile and susceptible to damage such as lead coplanarity, lead bending and sweep. To place these packages, a pick-and-place machine with vision system and waffle pack handlers is necessary. These two features, however, can add substantial capital equipment costs. Design guidelines must change to allow added interpackage spacing between the fine-pitch devices and neighboring conventional packages. With the exception of no-clean fluxes, cleaning problems arise with fine-pitch devices which sit almost flush (0 to 250 µm) to the board. For proper cleaning, a 0.4 mm to 0.5 mm standoff is recommended, with the need to meet this requirement based on the size of the BGA package, since smaller profiles allow easier penetration of the cleaning solutions. Using a temporary solder mask over the vias under a package avoids flux entrapment problems. However, this extra process step increases production cost. Since BGAs use solder bump interconnections instead of leads, problems associated with lead damage and coplanarity are eliminated. BGA pitches from 1.27 mm to 1.5 mm, have well over 250 µm of standoff height, so problems with paste printing, placement, reflow and cleaning are significantly reduced. BGAs also provide much shorter signal paths compared to fine-pitch devices. Shorter signal paths can be very critical in high-speed applications. 3.1 Description of Infrastructure The use of BGAs in the design through assembly processes has become common place in the last few years. Nevertheless, incorporating these parts into electronic assemblies requires dedicated engineering resources to develop, implement and integrate the processes into the assembly operation. Even though BGAs can leverage existing SMT infrastructure, there are many technical considerations that must be addressed in order to be successful in implementing BGA components into existing product configurations. 3.1.1 Land Patterns and Circuit Board Considerations
Components are soldered to the printed board on the surface mount lands. Lands are areas of copper approximately the shape and size of the lead or termination footprint. The land pattern design is critical for manufacturability, because it affects the solder defect rate, cleanability, testability, repair/rework and the solder joint’s reliability. In the past, component tolerances were too liberal (some still are) for effectively designing land patterns. Additionally, since surface mount packages were not standardized, land pattern design could not be standardized. As a result, users had to develop in-house land pattern dimensions and qualify a limited number of suppliers who met those specifications. Reducing the number of suppliers reduced the
IPC-7095B
range of sizes and associated tolerances required of land pattern design. Land pattern design issues for BGA need to be understood. This is essential to assure proper solder joint formation and prevent defects such as bridging, opens and to achieve optimal reliability. In addition to land design, one should also keep in mind that the inner rows of BGA pins require additional layers for interconnection. Increasing the number of pins (vias) drives layer count due to the reduction of routing channels. Higher layer count means higher cost of the bare board. BGA lands can be solder mask defined (solder mask overlaps the land) or copper defined (solder mask stays away from the land). There are pros and cons of each approach but the copper defined lands are more reliable. The board manufacturers must deal with land size issues, compatible surface finishes, solder mask resolution and electrical test problems. The assembler must deal with the assembly process parameters and make a decision as to the solder paste properties, wave solder materials and the process profiles for attachment of a variety of component and board finishes. Based on industry predictions one would believe that all component packages have over 200 I/Os and are increasing in I/O count. Actually, components with the highest usage have I/O counts in the 16 to 64 I/O range. Over 50% of all components fall into this category, while only 5% of all components used have over 208 I/Os, which may be the threshold for determining the cross-over point between peripheral leaded component style packages and array type formats. Many peripherally leaded, lower I/O count devices, such as memory and logic devices, are being converted to area array packaging formats as either BGAs or fine pitch BGAs. Although the percentage of high I/O components used on an electronic assembly is small, they play a big part in driving the industry infrastructure for both bare board and assembly manufacturing. These high I/O components determine the process for bare board imaging, etching, testing and surface finishing. They determine the materials used for fabrication and drive assembly process improvements in a similar manner. The electronics industry has evolved from using through hole assembly technology in which the component leads went into the printed board substrate and were either soldered to the bottom side of the board or into a platedthrough hole. Surface mounting technology (SMT) has advanced to a stage where the majority of electronic components manufactured today are only available in SMT form. Manufacturing products with SMT in any significant volume requires automation. For low volume, a manually 3
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operated machine or a single placement machine may be sufficient. High volume SMT manufacturing requires special solder paste deposition systems, multiple and various placement machines, in-line solder reflow systems and cleaning systems. The heart of surface mount manufacturing is the machine that places the components onto the printed board land areas prior to soldering. Unlike through-hole (TH) insertion machines, surface mount placement machines are usually capable of placing many different component types. As design densities have increased, new SMT package styles have evolved. Examples are fine pitch technology (FPT), ultra fine pitch technology (UFPT), and array surface mount (ASM). This latter category consists of the many families of ball or column grid arrays, chip scale packages (CSP), fine pitch BGAs (FBGA), and flip chip (FC) applications. These parts are all capable of being placed by machines provided that the equipment has the required positioning accuracy. Increased device complexity has been a primary driving factor for SMT. In order to minimize the component package size, component lead spacing has decreased (e.g., 1.27 mm to 0.65 mm). Further increases in semiconductor integration requiring more than 196 I/Os can drive packages to even closer perimeter lead spacing, such as 0.5, 0.4, 0.3, and 0.25 mm. However, the array package format has become the favorite for high I/O count devices. Area array component package styles have a pitch that originally was much larger than the equivalent peripherally leaded device, however that lead format is now also seeing reductions in pitch configurations. Ball and column grid arrays were standardized in 1992 with 1.5, 1.27 and 1.0 mm pitch. Fine pitch BGA array
Figure 3-2
4
Area array I/O position comparisons
packages standards have established pitches of 1.0, 0.8, 0.75, 0.65, and 0.5 mm. There are some implementations of FBGAs where the pitch has been reduced to 0.4 mm, and future components are being evaluated with 0.3 and 0.25 mm pitch configurations. Although standard configurations for BGAs and their associated land patterns exist, as described in IPC-7351, some component manufacturers have modified the standard configurations in order to improve the interconnection capability in the component substrate. The tailoring of the standard geometries makes it important to check the manufacturer’s data sheet to determine the exact characteristics of the pitch, ball size and depopulation (removed balls). There is a question as to how many lead pitches are required between 1.0 mm and 0.5 mm. Some indicate that a 60% rule is of value where the ball diameter is 60% of the pitch. This results in a 0.5 mm ball diameter for a 0.8 mm pitch. FBGAs would use a 0.4 mm ball diameter for a 0.65 mm pitch. On the other hand, some feel that it would be better to standardize a 0.3 mm diameter ball for all FBGA packages. Standardization of a single ball size would facilitate many characteristics. The motive is to accommodate conductor routing on the interconnecting substrate and help standardize socket pin contact design. Area array packaging has the intrinsic value of being able to make coherent designs. This is exemplified on the right side of Figure 3-2, where a single pitch might be depopulated to meet the requirements of the design. The trend illustrated on the left side of Figure 3-2 forces the creation of many different test sockets. Interconnection of the part IOs is affected both by ball pitch and ball diameter. The standard ball diameter as specified by the US JEDEC JC11 Committee alleviates pressure on the substrate design.
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also be used to connect several chips together. This technique is referred to as a multichip module-laminate (MCM-L) or a multichip package (MCP) or the new name assigned to complex module assemblies known as multi device subassembly (MDS). In all the variations that are being developed the one governing condition is the use of the area array format. Thus, ball size and pitch will continue to be the process governing factor for individual components or those that encompass more than one semiconductor die. Table 3-1 shows some examples of an attempt to establish a definition for Multichip modules housing more than one die. Figure 3-4 is an example of one such product using the area array concepts for interconnection.
The selection process for an electronic assembly should attempt to minimize the variation in component package types and the I/O pitch condition. The large I/O count devices and problems with assembly of finer pitch peripheral packages has caused rethinking of the packaging style vs. the assembly complexity relationship, and the printed board interconnection and surface characteristics. The concern in using these very complex parts relates to board design and assembly issues. Assembly is concerned about attaching all the leads to the mounting structure without bridging (shorts) or missing solder joints (opens). Design is concerned with interconnecting all the leads and having sufficient room for routing conductors. Array packages permit a variety of ball configurations, i.e., staggered positions or partially populated parts, to provide the room required for adequate conductor routing. With a common base array pitch significant advantages can be gained in terms of providing a coherent standard for all of the elements of the electronic manufacturing infrastructure for components, sockets, substrates and test systems (see Figure 3-3).
IPC-7095b-3-4
Figure 3-4
MCM type 2S-L-WB
3.1.2 Technology Comparison The principles used to mount a single chip into an organic carrier package can
26
PIN #1 CORNER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
24 25
22 23
20 21
18 19
16 17
14 15
12 13
10 11
8 9
B C D E F G H J K L M N O P
P
2 3
PIN #1 CORNER
1
P
P
Figure 3-3
4 5
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
A
P
6 7
IPC-7095b-3-3
Area array I/O position patterns Table 3-1 MCM
Multichip module definitions
Technology Description
Attributes
Type 1
Common Technology Package
Multiple same type chips, in plane.
Type 1S
Common Technology Package
Multiple same type chips, stacked.
Type 1F
Common Technology Package
Multiple same type chips, folded.
Type 2
Mixed Technology Package
Mixed IC technology package, in plane.
Type 2S
Mixed Technology Package
Mixed IC technology package, stacked.
Type 2F
Mixed Technology Package
Mixed IC technology package, folded.
Type 3
System in Package
Mixed ICs and discrete devices, in plane.
Type 3S
System in Package
Mixed ICs and discrete devices, stacked.
Type 4
Optoelectronic System Package
Mixed technology for optoelectronics.
5
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Possible other descriptive attributes include substrate technology (e.g., -C for ceramic, -L for laminate, -D for deposited, -W for wafer, -S for silicon) & interconnection technology (e.g., -WB for wire bond, -FC for flip chip, -MX for mixed). Microprocessors typically have between 40-60% of their I/O dedicated to power and ground. As an example, a package might have a total of 1300-1400 I/O where the signal count is between 600 and 700 I/O. Applications Specific ICs (ASICs) may differ in that I/O apportionment. The signal I/O escape wiring, and their interconnection to other high I/O packages, will also require very high density printed boards (HDBs). As the number of I/O on a chip increases further, the body size of the single chip package may become unacceptably large, and could require reassessment of the overall package solution, including considering multichip module packaging or application specific module packaging (ASMP) as an alternative. The signal I/O count for high performance BGAs is about 2.5X that commonly required for BGAs used in hand held products. The interconnection density requirement is linearly proportional to the number of signal I/O per package, and inversely proportional to the center-to-center pitch between adjacent packages. A 2.5X increase in signal I/O from 500 to 1300 pins per package at the same package-to-package pitch will require a printed board with a 2.5X increase in its wiring density, and a proportional increase in the density of the interlevel vias or Plated-Through Holes (PTHs). This may require a reduction in the PTH/via pitch, and an increase in the number of signal layers in the printed board. With more of the circuit customization going into silicon and with the component package size increasing, the printed board design will need to change. The higher I/O demand will require multilayer or high-density interconnection (microvia) designs to support the required wiring and to provide escape routing from the internal connections of array component patterns to the printed board. Both sides of the printed board may be required to place all the components required by the design. There will also be an increased demand on the printed board to handle the required power dissipation. Using high I/O components like BGAs and fine pitch BGAs creates the challenge of routing all the required signal, power, and ground I/O balls to the printed board without increasing board complexity and, therefore, cost. Thoughtful package pin assignments and the package configuration considerations (pitch, ball size, ball count, and depopulation) can go a long way in making the board routing easier. Two interconnection signal layers can be sufficient for BGA package escape, even when the BGA has very high ball counts, providing the pin assignments are properly planned and the escape routing is carefully designed. Table 6
March 2008
3-2 indicates the number of ‘‘escapes’’ possible on two layers of circuitry vs. the array size and the number of conductors between lands/vias. It should be noted that, as the number of I/O increases, the ability to escape diminishes and thus more layers may be required. At first glance, Table 3-2 might appear to indicate that two routing layers are insufficient to escape any array greater than 16 x 16 (256 balls). In reality, a significant number of the balls will be used for power and ground connections and therefore do not need ‘‘escape’’ routing. They can be directly connected to the appropriate plane through the dogbone via attached to the land. That being said, poor placement of the signal or power/ground balls can ‘‘waste’’ available routing channels and significantly reduce the total number of signal I/Os that can be routed out in a given number of layers. Table 3-2 Number of escapes vs. array size on two layers of circuitry Number of Conductors Between Vias (•|•) 1
2
3
Array Size
Total Leads
•|•
•||•
•|||•
14 X 14
196
192
196
196
16 X 16
256
236
256
256
19 X 19
361
272
316
352
21 X 21
441
304
356
400
25 X 25
625
368
436
496
31 X 31
961
464
556
640
35 X 35
1225
528
638
736
Placing signal pin assignments on the outer rows of an array package, and using the inner balls for power and ground will facilitate escape routing. However, the corner balls of large array packages are more susceptible to mechanical failure, and therefore it may be better to use these for redundant ground connections. The number of rows of signal I/O that can be routed out will depend on the desired number of conductor routing layers in the printed board and the number of conductors that can be routed between lands and vias. Figure 3-5 shows examples of conductor and space widths that will fit between adjacent lands with various pitches and land diameters. Note that as the ball pitch decreases, the conductor width and spacing for a given number of conductors per channel also decreases, and it becomes more difficult and costly to produce the board. Using 150 µm conductors and spaces is quite cost effective, but printed board cost begins to increase significantly for 100 µm conductors and spaces. Using an organic interconnecting substrate to mount the bare die within a plastic BGA requires that the mounting lands on the substrate match the bonding lands on the die. The bonding lands are typically positioned for wire bonding, since this is the most popular technique. Thermally
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IPC-7095B
0.25 mm Pitch
0.5 mm Pitch
0.75 mm Pitch
1.0 mm Pitch
1.27 mm Pitch
Conventional FR-4 125 µm Line 125 µm Space 700 µm Land
Conventional FR-4 125 µm Line 125 µm Space 600 µm Land
High Density FR-4 100 µm Line 100 µm Space 600 µm Land
Next Gen FR-4 60 µm Line 50 µm Space 300 µm Land
Typical Microvia 75 µm Line 100 µm Space 200 µm Land
Next Gen Microvia 50 µm Line 50 µm Space 50 µm Land
Figure 3-5
Conductor width to pitch relationship
conductive adhesive is one of the methods used to attach the back of the die to the substrate. Depending on the number of I/O and the lead pitch, multilayer substrate fabrication techniques may be used to translate a peripheral bonding land die, to an area array matrix of bumps, balls, or columns (see Figure 3-6). The transition of chip bonding lands that are in an array format permits the mounting of the die in flip chip configurations. In this instance, the die is mounted opposite to that which is wire-bonded and the bumps of the die come into direct contact with the substrate being used to convert the die pattern to the BGA pattern. This creates new challenges for the routing requirements for the organic high-density microcircuit board manufacturer. In addition, underfill is usually required to maintain some consistency between the coefficient of thermal expansion (CTE) of the chip and the CTE of the organic multilayer board (see Figure 3-7). Getting into BGA technology also requires some new assembly capability. 3.1.3 Assembly Equipment Impact
Depending upon the type of pick and place systems, a change in package carrier mechanism may also be required to transfer packages from matrix tray to the pick position. Fiducials may also be helpful in helping the vision systems recognize the exact location of the land pattern for the BGA, similar to what is used for fine-pitch peripheral leaded parts. Large BGA parts on tape-and-reel will require 44 mm and 56 mm feeders depending on the body size. Use of a forced air convection oven is preferred. Repair and inspection of BGAs are rather difficult. Rework machines with paste deposition, preheat, and vision capability may not be required, but are very helpful. X-ray and optical inspection (endoscope) capability for process development is a benefit. 3.1.4 Stencil Requirements The stencil thickness may need to be reduced when using finer pitch BGA parts. Stencil thickness and land size will determine paste volume, which is very critical for ceramic BGAs. It is helpful to have trapezoidal stencil apertures (slightly larger opening
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Overmolded Epoxy
Wire Bonds
Silicon Die
BT Substrate
Die Attach Solder Balls (Sn63Pb37) IPC-7095b-3-6
Figure 3-6
Plastic ball grid array, chip wire bonded
Underfill Epoxy
Plated Copper Conductor
IC
Signal and Ground Via
Soldermask
97/3 or 95/5 Sn/Pb Solder or Z-Axis Interconnect
BT Epoxy PCB
Thermal Via
Eutectic Solder Ball IPC-7095b-3-7
Figure 3-7
Ball grid array, flip chip bonded
on the bottom than on the top) for better paste release. Generally, on larger BGA components with 1.25 mm and 1.00 mm pitch, the aperture is large enough that stencil clogging, print registration and definition are less of a problem than with quad flat pack (QFP) components. Matching solder paste stencil openings to the requirements of fine-pitch BGAs requires an understanding of the relationship between the stencil aperture and the size of the particles in the paste. IPC-7525 provides good descriptions to help make the appropriate relationship decisions as the land patterns for attachment becomes smaller and are closer to one another. 3.1.5 Inspection Requirements As with any surface mount part, BGAs should not be moved after component placement because this may smear the paste and cause solder bridges. The outline of the component can be included in the silk screen to show gross alignment problems, but the parts will self align during reflow if not more than 50% off the land. If a BGA has a gross misalignment problem it
8
should be removed before reflow and reworked later. Though it may not be practical for high volume production, using X-ray or optical inspection (endoscope) to inspect failures before removing the part may be desirable. 3.1.6 Test Test strategies need to be developed before using BGAs. The solder joints cannot be probed and test points are required. It may be difficult to incorporate enough test points to adequately test all solder joints. Some alternative test strategies may be needed. Some BGA components may have boundary scan designed into them for increased test capability. Some BGA components have test points designed right on the top of the package. This is not a good practice, since it puts pressure on the BGA components and the joints. 3.2 Time-to-Market Readiness In some cases each designer will have an option to use or not to use BGAs. The alternative may be using a high pin count QFP. However, if a company is new to BGAs, it may take some time
March 2008
for the user and the suppliers of printed boards and assembly services to address the technical and business issues in order to implement BGAs into products. It is very likely that time to market will be adversely impacted if both products and the technology are developed simultaneously. It is a good idea first to develop and validate the technology before implementing it on a real product. Otherwise, if any problem develops in the product or technology, the deadline for product shipment will be missed. To assure time-to-market readiness, BGA implementation methodology and process steps should be analyzed. The designer faces a broad task. He or she must consider form, fit, function, cost, reliability, and time-to-market before choosing a particular course. In general, product design is cost, size, and/or performance driven. But in addition to the design and assembly challenges discussed above, the product must also be able to provide requisite performance in its stated environment (including temperature, vibration, and moisture). Reliability must be such that the product functions as intended in the working environment over the predicted life span of the equipment. Package selection may be driven by environment and reliability requirements. 3.3 Methodology
IPC-7095B
9. Design the remaining candidate products. With the major emphasis on using parts that meet both customer requirements and conform to new global regulations, many customers are requiring that their suppliers, both component and assembly service providers, indicate the materials that are a part of the component or have been intentionally added in order to provide a reliable assembly. The requirement to establish a formal declaration system has been in place since the automotive industry was challenged by the ‘‘End-of-Life’’ European directives. To show an example of the breadth of the variation in material properties that may occur in products, Table 3-3 shows a list of materials that might be used as a surface finish or a material that was added to the assembly as the second level interconnection. Since BGA technology has moved into the mainstream there are still some decisions that need to be considered. These are business and technical issues that must be resolved. The areas of special concern are: 3.5 BGA Limitations and Issues
• Visual Inspection • Moisture Sensitivity
There are several available paths to utilizing BGAs effectively. The length of each path depends on what design and assembly facilities a company presently has, and how quickly they can be made ready for production. The following is an example of one approach.
• Rework
1. Select a list of candidate products for BGAs.
• Reliability Concerns
2. Develop an equipment list based on the projected volume needs. If sufficient in-house expertise does not exist, it may be desirable to use a reputable training center or consultant to save cost and time.
BGA issues are not insurmountable, however they require dedicated engineering resources to develop and implement the process.
3.4 Process Step Analysis
3. Organize a team representing design, production, test, quality, and purchasing. This team is responsible for component and equipment selections and review. 4. Develop a comprehensive BGA design guide that stresses manufacturability. Use existing standards where possible. 5. Design the candidate products starting with the conversions of existing products using fine pitch components. 6. Determine the need for lead-free products including the alloy used on the part as well as the surface finish needed on the mounting substrate. 7. Conduct rigorous assembly and test reviews. Carefully monitor component purchasing to assure that components have the specified package, shipping method, metallization, solderability, and orientation in the shipping containers. 8. Develop comprehensive workmanship standards and a process control system that is statistically sound.
• Cost • Availability • Voids in BGA • Standards and their adoption
3.5.1 Visual Inspection BGA is not a package suitable for companies that assure quality by inspection and repair. BGA solder joints cannot be inspected unless X-ray or optical inspection techniques are used. To reap the benefits that BGA offers, robust process control must be maintained. Due to limited time and training, many companies find implementing such tight process control to be a difficult endeavor.
There are some visual inspections that would show good flow on an un-collapsed ball with ceramic BGAs, and also be able to show collapsed balls on plastic BGAs. Visual inspections of BGAs can identify problems with solder joints. Visual inspection of the outer rows serves as an indicator of some of these problems. Examples are BGA alignment with the lands on the outer rows or how the BGA is sitting on the board, level or skewed. The plastic BGA packages are very moisture sensitive. This makes them susceptible to 3.5.2 Moisture Sensitivity
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March 2008 Table 3-3
Potential plating or component termination material properties
Aluminum (Al) - anodized Bright Tin (Sn) Bright Tin (Sn) - annealed Bright Tin (Sn) - fused Bright Tin (Sn) - reflowed Bright Tin (Sn) - reflowed over Nickel (Ni) barrier Bright Tin (Sn) - with Nickel (Ni) barrier Bright Tin (Sn) - with Silver (Ag) barrier Chromium (Cr) Chromium (Cr) - hexavalent Chromium (Cr) - trivalent Gold (Au) Gold (Au) - electroplated Gold (Au) - hard Indium (In) Matte Tin/Copper (Sn/Cu) Matte Tin (Sn) Matte Tin (Sn) - annealed Matte Tin (Sn) - fused Matte Tin (Sn) - reflowed Matte Tin (Sn) - reflowed over Nickel (Ni) barrier Matte Tin (Sn) - with Nickel (Ni) barrier Matte Tin (Sn) - with Silver (Ag) barrier Nickel (Ni) Nickel/Gold (Ni/Au) Nickel/Gold (Ni/Au) - electrolytic Nickel/Gold (Ni/Au) - ENIG Nickel/Palladium (Ni/Pd) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) - ENEPIG Organic Solderability Preservative (OSP) Organic Solderability Preservative (OSP-HT) Palladium (Pd)
Platinum/Palladium/Silver (Pt/Pd/Ag) Semimatte Tin (Sn) Silver (Ag) Silver (Ag) - electroplated Silver (Ag) - immersion Silver (Ag) - with Nickel (Ni) barrier Silver/Palladium (Ag/Pd) Silver/Palladium (Ag/Pd) - Ni barrier Tin (Sn) Tin (Sn) - hot dipped Tin (Sn) - immersion Tin (Sn) - reflowed Tin/Bismuth (SnBi) Tin/Bismuth (SnBi) - <5% Bi Tin/Bismuth/Gold (Sn/Bi/Au) Tin/Copper (Sn/Cu) Tin/Copper (Sn/Cu) - annealed Tin/Copper (Sn/Cu) - HASL Tin/Copper (Sn/Cu) - hot dipped Tin/Lead (Sn10Pb90) Tin/Lead (Sn63Pb37) Tin/Lead/Silver (Sn/Pb/Ag) Tin/Silver (Sn/Ag) Tin/Silver (Sn/Ag) - hot dipped Tin/Silver (Sn/Ag) - plated Tin/Silver/Bismuth (Sn/Ag/Bi) Tin/Silver/Bismuth/Copper (Sn/Ag/Bi/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) - hot dipped Tin/Zinc (Sn/Zn) Tin/Zinc/Aluminum (Sn/Zn/Al) Tin/Zinc/Nickel (Sn/Zn/Ni) Zinc (Zn)
warpage, swelling, popcorning, or cracking if the packages are not properly baked and kept dry prior to package assembly. Component storage and handling procedures are critical for any moisture sensitive component including leaded surface mounted devices, but it is critical for BGAs/ FBGAs.
thus such terms as ‘‘frowning’’ or ‘‘smiling’’ BGAs have been used to identify these conditions. Package warpage is of real concern in flux only applications during rework. Large die sizes can cause CTE mismatch between the PCB and the package laminate material, which can create package warpage (see Figure 3-8).
Component moisture sensitivity is tested using J-STD-020. The moisture sensitivity level must be determined for each BGA package type. It is critical to know at which of the three temperatures, 220°C, 235°C, or 250°C, the BGA package was classified. The classification of the package type may drop several levels if the higher temperature is used.
Thermally unbalanced package designs, particularly those with heat spreaders on the top, will warp according to the classic bi-metal effect.
Due to improvements in molding compounds and laminate systems, most laminate-based BGAs can be mounted and qualified for temperatures above 220°C. The hermetic ceramic BGAs are not moisture sensitive and therefore can be mounted using either of the higher temperatures. Because of the forced switch to lead-free solders, the industry needs to be testing at a higher temperature such as 260°C, which will create major issues with not only BGAs but also all surface mounted devices. The plastic BGA package is also susceptible to warpage during which the package edges lift up which could result in no connections on the outer rows. The edges may also bend down, 3.5.3 Thermally Unbalanced BGA Design
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Although BGAs do not require nearly as much rework as fine pitch lead-frame devices, many assemblers are apprehensive about using a component package that is difficult to be reworked. While BGA rework is difficult, it is by no means impossible. Tools and techniques for rework are currently available that range from manual to automated techniques to reball the BGA or redress the land pattern. Several factors must be addressed during the rework operation. These are:
3.5.4 Rework
• Number of heat cycles. • Ball collapsed during reballing. • No damage to pads on BGA interposer. • Proper land redressing and no damage to lands on the product board. • Appropriate reflow temperature for reattachment based on alloy used.
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IPC-7095B
IPC-7095b-3-8
Figure 3-8
BGA warpage
• Electrical enhancements.
• Proper cleaning to remove flux residue unless no-clean flux is used.
• Very fine external pitches. • High temperature reflow requirements.
The BGA still has a slight cost differential compared to fine pitch peripheral packages that it replaces. However, competitive pressures keep bringing costs lower to meet new targets. Further costs accrue with the increased board layer counts that BGAs require, however there are many advantages to the interconnecting concepts and the performance characteristics resulting from BGA implementation. 3.5.5 Cost
• Thin profile heights. All of these have been addressed in the last few years and great progress has been made. In general, it has been difficult to create standard pin count BGA designs because every die has different requirements. Each package/die combination is unique, therefore economies of scale that manufacturers can achieve with perimeter leaded packages are not necessarily seen with the area array devices.
Following are some of the key reasons for higher BGA package cost: • Higher cost substrate (fine line/space).
Table 3-4 shows the expectations of the semiconductor industry as to what they expect to pay on a cost per pin relationship for the different technologies over the next
• High Tg BT (bismaleimide-triazine) resin. • Thermal enhancements. Table 3-4 Year Roadmap Input
2008
Semiconductor cost predictions
2009
2010
2011
2012
2015
2018
2020
Cost per Pin Minimum for Contract Assembly [1,2] (Cents/Pin) Low-cost, hand held and memory
0.24-0.47
0.23-0.46
0.22-0.45
0.21-0.43
0.20-0.42
0.19-0.38
0.18-0.35
0.17-0.34
Cost-Performance
0.63-1.00
0.62-0.96
0.61-0.94
0.60-0.92
0.58-0.90
0.55-0.85
0.52-0.80
0.50-0.79
High-Performance
1.68
1.64
1.61
1.58
1.55
1.45
1.37
1.32
0.23-2.00
0.22-1.90
0.22-1.54
0.21-1.46
0.20-1.38
0.19-1.17
0.18-1.00
0.17-0.89
Harsh White - Solutions exist
Yellow - Solutions being pursued
Red - No known solutions
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IPC-7095B
several years. The shaded sections indicate a challenge and degree of difficulty in achieving the predicted goals. Table 3-4 is taken from the ITRS 2005 Roadmap and the costs are very aggressive. The lower range of costs reflect peripheral leaded packages and the higher ranges reflect array style packages like BGAs/FBGAs. The opinion of many resource experts is that the prices in the future years may not be able to be achieved with profitability because of the low costs forecasted. 3.5.6 Availability The 1.5, 1.27, and 1.0 mm are available in high volumes in many locations in the world. The 0.80 mm to 0.50 mm pitch packages are also available and used in many advanced portable electronic applications. Unfortunately, some of the component manufacturers are developing their own version of the BGA package. Part of this has to do with making it more difficult to copy the design; another part has to do with maintaining market share. The concept is one that prevents second source entry and locks the designer that chooses a particular nonstandard component product into a single component supplier.
Many companies use X-ray, in-circuit test and automatic optical inspection in combination to improve their process control for BGA solder joints. Some look for voids through X-ray to determine accept/ reject criteria. Some level of voiding in any kind of solder joint is inevitable. 3.5.7 Voids in BGA
There is still some debate as to what is an excessive void. The proponents of voids argue that it is not the void that is bad, but its location. For example, if a very large void is between the ball and the board, you essentially have nonwetting, which is unacceptable. Most process voids in BGA are in the ball, well above the board, and hence the analogy of nonwetting or dewetting are not issues. 3.5.8 Standardization Issues Many of the BGAs are using conventional printed board (interposer) materials, but are being tested to the standard component reliability tests. Standardization efforts are being undertaken by both JEDEC and IPC to test these new packages to the requirement limits of the bulk of the applications. The majority of these packages are going into office equipment, laptop computers and portable electronic applications that do not require the life cycle performance requirements needed by other applications.
Application specific qualification standards are needed to relate the test conditions to the environment in which the product will be used. Many of the industry technology roadmaps have identified these environments as being low cost benign, hand held, high function hand held, cost performance, high performance and harsh environments. The latter environments, such as those for Aerospace or Automotive (under-the-hood) electronics, many times require 12
March 2008
additional testing such as highly accelerated stress testing (HAST) in order to verify reliability in those harsh environments. 3.5.9 Reliability Concerns Reliability concerns relate to the BGA components themselves and to the reliability of the BGA solder attachment to the interconnecting substrate, usually an organic printed board.
Component reliability issues are mitigated through proper mounting of the die to the interposer. Wire bonding techniques have been used for many years. The processes are well known, oftentimes quite refined, and can afford high yields. Another popular technique is to mount the bare die face down onto the interposer in a flip chip configuration. Using flip chip processes requires a tighter control of the land positions on the interposer so that the lands line up properly with the bonding sites on the bare die. In addition, if the interposer is made of organic materials the attachment process also requires underfill to minimize the fatigue damage caused by a CTE mismatch between the silicon die and interposer. Solder joint fatigue at the assembly level is mitigated when CTE mismatch is minimized and stand-off height is increased. The reliability of the solder attachment can be optimized by developing a thorough understanding of the product’s operational use environment and by following the guidance outline in the design for reliability (DfR) procedure suggested in IPC-D-279. Risk of tin whiskers and gold embrittlement should be considered when selecting surface finishes. Thick gold (more than 0.25 µm) as a surface finish should be avoided to mitigate the risk of gold embrittlement of the solder. 4 COMPONENT CONSIDERATIONS 4.1 Component Packaging Comparisons and Drivers 4.1.1 Package Feature Comparisons There are many types of package formats for ICs but only four types of terminal shapes; in-line pin (both single and dual), pin grid array, J lead, and gull-wing lead. The most common lead configurations for surface mountable plastic packaged ICs are the J lead and gull-wing lead. Of these two, the gullwing lead form is the most commonly used lead type for plastic packaged ICs. One of the biggest problems with higher pin count, fine-pitch gull wing leads is their fragility and, consequently, susceptibility to lead damage such as coplanarity, lead bending and sweep.
Lead damage is one of the leading causes of defects in fine-pitch gull wing leaded packages. Although gull wing devices are the most commonly used lead form for low and high pin count packages, ball grid array packaged devices have achieved broad acceptance due to their physical robustness, (pin-for-pin) size reduction and enhanced electrical performance.
March 2008
In regard to performance, the BGA signal paths can be much shorter than those of fine-pitch gull wing lead packages, advantageous in high-speed applications. BGA packaged ICs have exhibited very high board level assembly process yields due to their ability to self-center during reflow soldering. Because the array format can accommodate high I/O within a small form factor, BGAs have proven to be a practical solution to the high pin count packaging trend as well. 4.1.2 BGA Package Drivers The emphasis on faster, smaller and lighter electronics systems is making component, board and system packaging more complex. The increase in assembly complexity is due in part to the wide use of small outline surface mountable packages, the key to miniaturization of electronics products. The device contact pitch plays a critical role in the complexity of manufacturing processes as well. For example, with the adoption of finer and finer contact pitches, greater precision is demanded for each process in the assembly sequence: pickand-place, solder paste printing, and solder reflow. Inspection, rework and repair need to become more precise as well.
Key issues to be addressed when selecting BGA component packaging are thermal and electrical performance, real estate constraint and cost. The component packaging requirement varies for different types of systems. For example, the high-end microprocessors run at higher frequencies and require thermally and electrically enhanced packages. Examples of thermal enhancements are heat slugs, heat spreaders, heat sink and fin-fan (fan mounted on heat sink) etc. And examples of electrical enhancements are multilayer and higher pin-count packages and in-package capacitance. Hermetic ceramic packages are generally used for the in-package capacitance application. For mid-range systems, performance is important as well, but so is cost (not that cost is not important for high end systems). Lead-frame packaged ICs have traditionally maintained a relatively low manufacturing cost. This is due to the very high volume of products being offered in a limited package configuration. This allows the manufacturer to utilize common tooling and molding processes for a diverse number of customer applications. The array package format, on the other hand, is more often designed and engineered for a specific product application. The initial cost for packaging BGA devices with a pin count of less than 200 will most likely be greater than lead-frame packaging. This is due in part to the unique single application substrate design and additional package assembly process steps. Cost parity between lead frame packaged ICs and the BGA package is generally reached when the device requires 200 or more I/O.
4.1.3 Cost Issues
IPC-7095B 4.1.4 Component Handling BGAs can be furnished in a carrier tray format or tape-and-reel. The EIA standard embossed tape-and-reel format is often specified when the IC components are relatively small and/or required for very high-volume applications. The JEDEC registered carrier trays are furnished to meet industry developed design guidelines (see JEDEC publication 95, Section 4.9 and Section 4.10) with a fixed length, width, and thickness. The plastic packaged ICs, including the BGA, are susceptible to moisture retention that can damage the package during reflow solder processing. To protect the devices from undue physical contact and exposure to humidity, the loaded carrier trays are shipped in a sealed ESD and vacuum purged moisture resistant envelope (and should remain sealed until ready for board level assembly, see 4.8.5).
It is recommended that the user specify that plastic encased BGAs be furnished in the tray format rather than the tapeand-reel format. The tray carrier will accommodate the potential need to bake-out devices that are prone to moisture absorption. For example, if the plastic BGA packages are exposed to ambient conditions beyond their floor life, they will likely require baking before assembly. The plastic tray carriers developed for bake-out are rated to withstand 125°C temperature. The tape-and-reel materials, on the other-hand, cannot be exposed to temperatures above 50°C without damaging the carrier tape. So baking a moisturesensitive BGA in the tape format could take many days. 4.1.5 Thermal Performance Thermal enhancements have become essential with introduction of faster and faster microprocessors. With introduction of new generations of microprocessors, power dissipation has continually moved upward. As the device clocking speed increases, the power goes up. The problem of higher power is mitigated, fortunately, with ‘‘die shrink’’ made possible by the reduction of transistor feature sizes in contemporary semiconductor processes and the associated trend towards lower power supply voltages. (As device geometry shrinks, the field intensities increase, promoting a reduction in supply voltages to avoid destructive effects.) The ceramic BGA is commonly used for higher wattage packages, as it has greater thermal conductivity than plastic packages. Plastic packages, however, are also evolving, and thermally enhanced plastic packages are already in wide use by the industry. Thermally enhanced plastic packages used to be limited to 6 to 8 watts, however, by incorporating integral metal heat spreaders, plastic packages can accommodate up to 30 watts. 4.1.6 Real Estate Real estate constraint is one of the important driving forces in reducing component package size. This has contributed to the widespread usage of surface mount devices, which are not only smaller in size, but enable component mounting on both sides of the board. As
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IPC-7095B
pin counts increase, however, even with surface mount, the conductor-to-conductor pitch must decrease to keep the size of the package within a practical range for manufacturing. As the pitch of the BGA package decreases, the opportunity for placing more components in a given area increases. Although the board real estate can now support more functions per unit area, components such as the fine pitch BGA (FBGA) are more difficult to interconnect. This fact may increase the number of conductive layers required for the total circuit. Thus, surface real estate is optimized at the expense of more conductor routing layers. 4.1.7 Electrical Performance Electrical performance drivers include signal fidelity, operating frequency, power, and pin-count. With increasing frequency, the need for improved impedance control and minimal package insertion loss are a concern. When impedance control requirements are imposed, one must consider the need for terminations to prevent or dampen reflections. These terminations, if performed in parallel to source and/or load points on critical signals, will increase power consumption. High frequency operation itself, all other things being equal, drives power consumption upward with the square of frequency. As such, low power semiconductor research is increasing, in an attempt to reduce the average power consumption of complex digital ICs. Fortunately, as IC processes mature, the power per logic operation decreases by virtue of smaller device feature sizes. In the case of ceramic packages, even with increase in bond lands for high-speed devices, the pin count growth required for power and ground distribution is kept to a minimum by exploiting the intrinsically high package capacitance and employing package-mounted bypass capacitors. 4.2 Die Mounting in the BGA Package There are many
ways a die is mounted in a BGA. The three main variations can be differentiated by the medium of signal transmission from the die to the solder ball array. In the basic three designs, the signal is carried by wire, conductive material (flip chip) or conductive ribbon-lead. The substrate can be ceramic or organic. The package properties will depend on the properties of the substrate material and its dimensional parameters. The following descriptions represent the more common methodology for die-to-package assembly. 4.2.1 Wire Bond There are two main forms of the wire bonded BGA. They are chip-on-board (COB) with the active surface of the die facing away from the substrate and board-on-chip (BOC) types with the active surface of the die facing the substrate. In the COB structure, the bond pads on the die are generally furnished at its periphery and the wire bonds are made from the die periphery to the lands on the substrate surrounding the die. Wire bonds in the case of COB design can be made from the substrate/PCB to the
14
March 2008
die (known as reverse bonding) to reduce the package height or, in some cases, when another die is going to be stacked on top. The die can be attached to the substrate using conductive or nonconductive adhesive. Use of electrically conductive adhesive is specified when the die backside requires an electrical connection. The drawback is that some or all of the substrate area under the die cannot be accessed for in-package circuit routing. The size of the ground pad under the die will depend on the die requirements. If a partial grounding is sufficient then the rest of the area under the die can be used for signal routing but will need to be protected with solder mask from the conductive adhesive. If the die does not require a backside electrical connection, then a nonconductive adhesive can be used to place the die on the substrate. In this case, the area under the die can be used for signal routing. See Figures 4-1 and 4-2.
Figure 4-1 Partial area under the die is used to provide ground for the die. The rest of the area has been used for signal routing but has been covered with solder mask to isolate it from the conductive adhesive under the die.
The adhesive selected for die attach must not adversely affect the mechanical integrity of the traces or the integrity of the electrical signal. Following die attach and adhesive curing process the die is ready for electrical interface to the substrate base. The bond pads on the die are connected electrically to the bond pads on the substrate using gold wire or aluminum wire where feasible. The traces on the substrate route the signals from wire bond pads to the ball grid array on the bottom of the substrate through plated via holes. Following the wire-bond process, the die and bond area is typically protected by encapsulation, conformal coating or plastic over-mold. The encapsulation can be applied in the form of glob top or it can be molded in a press. An alternative to encapsulation is the post-assembly attachment of a premolded cover.
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IPC-7095B
IPC-7095b-4-3
Figure 4-3
Figure 4-2 Use of glass die to optimize the adhesive dispensing process for void-free controlled fill and squeezeout. The picture on the top shows the adhesive dispense pattern on the die site. The picture on the bottom shows the placed glass die to view voids and filling characteristics. The adhesive provides full die coverage for attachment but partial coverage to ground through a smaller than die ground pad, allowing a larger portion of the area under the die for signal routing saving valuable real estate and making the resulting package smaller.
In the case of long wires, it may be necessary to lock wires by using glob-top type of material to alleviate wire sweep. In the BOC or die face-down structure, the bond pads on the die can be located at the die periphery or in a row or rows at the center of the die. The substrate is designed with a narrow slot to accommodate the row or rows of bond pads on the die. The die-to-substrate adhesive is placed to the right and left of the bond pads. The adhesive can be applied in the form of a paste or a film. The active or circuit side of the die is attached face-down onto the substrate with the substrate slot exposing the bond pads on the die typical of that shown in Figure 4-3.
BOC BGA construction
Following die attachment and adhesive cure, the bond pads on the die are wire-bonded to the corresponding pads surrounding the slot on the substrate. Following wire-bond, the wires and exposed die surface are encapsulated for protection. Note that one or more grid array rows will need to be depopulated to allow the slot in the substrate for wire bond to the die. Also note that the wire bonding is accomplished at the center of the die and does not require additional peripheral area around it for die-to-substrate interface. Figure 4-4 illustrates the top and bottom of a moldencapsulated BGA package. 4.2.2 Flip Chip The flip chip (or direct-chip-attach) design eliminates the need for wires and die attach. In this design, the prebumped die is flipped circuit side down and the lands on the circuit side of the die are brought into contact with corresponding lands on a substrate using solder or conductive adhesive. The die bond pads, however, are not immediately compatible with either solder or conductive adhesive attachment processes. Solder bumping with a solder compatible alloy composition before the die wafer is sawed is one of the most common procedures. The solder material and the bumped-pad structure materials are chosen to optimize electrical and mechanical connection typical of that shown in Figure 4-5.
Conductive adhesive or polymer attachment can be adapted as well, however, the die bump contact may require a ‘‘noble’’ alloy that is compatible with the conductive alloy particles in the adhesive. This alloy bump or ball can be applied to the die bond pads by plating or ball bonding processes. If a solder or an isotropically conductive adhesive is used, the gap between the die and the substrate may 15
IPC-7095B
March 2008
array (CGA) is a square or rectangular 1.50, 1.27, and 1.00 mm pitch package with an array of metallic balls or columns on the underside of the package. The main body of the package has a metallized circuit pattern applied to a dielectric structure. To this package body, the semiconductor die(s) is attached to either the top or bottom surface. On the underside of the dielectric is an array pattern of metallized balls/columns which form the mechanical and electrical connection from the package body to a mating feature such as a printed circuit board. The surface that contains the die may be encapsulated by various techniques to protect the semiconductor.
Top
Bottom IPC-7095b-4-4
Figure 4-4
Top of molded BOC type BGA Heat Spreader Thermal Paste Die Underfill Flip Chip Solder Balls Package Substrate BGA Solder Balls Circuit Board IPC-7095b-4-5
Figure 4-5
Flip-chip (bumped die) on BGA substrate
require an under-die-filling with epoxy to ensure mechanical integrity of the die-to-substrate interface. Use of an anisotropically conductive material eliminates the need for added underfill. After attaching the die to the substrate, it is typically encapsulated, coated or over-molded for protection 4.3 Standardization Standardization of BGA packaging has considered a number of physical variables including the diameter of the individual ball, the positional accuracy of the ball in relationship to a true position within the component outline. 4.3.1 Industry Standards for BGA For more detail regarding package variation, mechanical feature dimensions and allowable physical tolerances, refer to the following JEDEC developed guidelines for BGA packaging. 4.3.1.1 BGA Package JEDEC Publication JEP95, Section 4.14, defines a ball and column grid array package family. A ball grid array (BGA) package or column grid
16
4.3.1.2 Fine Pitch BGA Package JEDEC Publication JEP95, Section 4.5, defines an FBGA package as a reduced-pitch (<1.00 mm) version of a BGA package. The carrier body of the package has a metallized circuit pattern applied to a dielectric structure. One or more semiconductor devices are attached to either the top or the bottom surface of this dielectric carrier. On the underside of the dielectric carrier is an array pattern of metallized balls, which form the mechanical and electrical connection from the package body to a mating feature such as a printed circuit board. The surface that contains the die may be encapsulated by various techniques to protect the semiconductor. The requirements for a square FBGA package family allows three optional contact pitch variations: 0.50, 0.65, and 0.80 mm and defines four device profile (height) variations as well. Additionally, a 0.75 mm contact pitch has been included on the Die Size BGA (DSBGA) package guideline, thus providing four pitch variations for the die size device family.
The total profile height of the FBGA as measured from the seating plane to the top of the component, is >1.70 mm. The low-profile fine-pitch ball grid array (LFBGA) is a reduced-height version of an FBGA. The total profile height of the LFBGA as measured from the seating plane to the top of the component, is no greater than 1.20 mm. Thin profile fine pitch ball grid array (TFBGA) is a reduced-height version of an FBGA with a total profile height as measured from the seating plane to the top of the component that does not exceed 1.00 mm and the very thin profile fine pitch ball grid array (VFBGA) is a reducedheight version of an FBGA with a total profile height as measured from the seating plane to the top of the component that is at or below 0.80 mm. The JEDEC design guide for FBGA allows the manufacturer the option to increase ball diameter as the spacing or pitch between ball contact centers increase as compared in Table 4-1. As of this release, the JEDEC FBGA and FRBGA design guide does not support the 0.75 mm pitch; however, the industry has registered some nonconforming parts with that pitch.
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IPC-7095B
Table 4-1 JEDEC Standard JEP95-1/5 allowable ball diameter variations for FBGA Ball Diameter/mm Ball Pitch
Min.
Nom.
Max.
0.50
0.25
0.30
0.35
0.65
0.25
0.30
0.35
0.65
0.35
0.40
0.45
0.80
0.25
0.30
0.35
0.80
0.35
0.40
0.45
0.80
0.45
0.50
0.55
The larger ball diameter option has been allowed to accommodate packages using rigid interposer structures. The larger diameter ball may compensate to a degree, for the wide mismatch of the coefficient of thermal expansion (CTE) between the silicon die and the rigid PCB structure. JEDEC Publication JEP95, Section 4.22, defines an FBGA Package-on-Package (PoP) configuration that consists of at least two microelectronic packages assembled in a vertical stack. Although package stacking can be done with a variety of package styles, this design guide focuses only on utilizing Fine-pitch Ball Grid Array (FBGA) packages to create the stack. The lower package of the stack includes a pattern of metallized lands on the top surface of the package through which mechanical and electrical attachment is made with the upper package. The ball pattern of the upper package is designed to facilitate the connection between the packages. This guideline focuses on land and ball patterns needed to facilitate the stacking. Wherever possible, dimensions are common to that defined in JEP95, Section 4.6. JEDEC Publication JEP95, Section 4.6, defines a fine-pitch, rectangular ball grid array (FRBGA) as having an array of metallic balls on the underside of the package. The substrate or carrier of the package has a rectangular shape with a metallized circuit pattern applied to either or both sides of a dielectric structure. Generally described with the same general terms noted in the JEP95, Section 4.5, the body size for an FRBGA is defined by the D and E dimensions. Dimension D is the size of the body when measured parallel to the major axis of the package, and dimension E is the size measured parallel to the minor axis. Thus, for rectangular packages D will have a larger value than E. 4.3.1.3 Fine Pitch Rectangular BGA Package
4.3.1.4 Die Size BGA Package JEDEC Publication JEP95, Section 4.7, defines a die-size ball grid array (DSBGA) package. A Die-size Ball Grid Array has an array of metallic balls on the underside of the package. The substrate or carrier of the package may have a square or rectangular shape with a metallized circuit pattern applied to either or both sides of a dielectric structure. The semiconductor die is attached to the top surface of this dielectric
carrier. On the underside of the dielectric the array pattern of metallized balls provides the mechanical and electrical connection from the package body to the next level component such as a printed circuit board. The surface to which the die is attached may be encapsulated by various techniques to protect the semiconductor. The size of the substrate or carrier is as close to the die size as practically possible. A ‘‘die-size’’ ball grid array (DSBGA) is a type of BGA package where the body size is defined to coincide as closely as possible with a specific die size. This package is sometimes called a ‘‘real chip-size’’ BGA or CSP. The dimensions of the package body accommodate assembly only of a die with a specific size, and these body dimensions will change as a result of future changes in die size. The outline of the package may be square or rectangular, but this aspect ratio may also change as a given package is redesigned to conform to a new die size. The aspect ratio will likely differ for devices of the same functionality from multiple suppliers. The controlling factor for the standardization of DSBGA packages is the size and aspect ratio of the ball array. The D and E dimensions define the body size for a DSBGA package. For packages with a rectangular ball matrix, the matrix determines the orientation of the dimensions. Dimension D is the body size measured parallel to the major axis of the ball matrix, and dimension E is the body size measured parallel to the minor axis of the ball matrix. Thus, for rectangular packages D will not necessarily have a larger value than E as would be the case for an FRBGA package per JEDEC JEP95, Section 4.6. A DSBGA package with a square ball matrix should follow the usual JEDEC convention where D is greater than E. The maximum values for both D and E are defined in JEDEC Publication 95 using 0.50 mm increments. The values are determined by rounding the actual DSBGA body size upward to the next 0.50 mm boundary. Thus, D and E values have the form y.00 or y.50 following this procedure. The array pitch for a DSBGA package will not necessarily be equal for the D and E matrix dimensions. When the pitches are not equal, ball dimensions and tolerances for the smaller of the two pitches will govern the definition of related package dimensions and tolerances. The controlling pitch of the array of balls on a DSBGA package is always less than 1.0 mm. The contact pitch variations for the DSBGA described in JEP95, Section 4.7, are 0.80, 0.75, 0.65 and 0.50 mm. 4.3.2 Ball Pitch Ball Grid Arrays are divided up into two groups of pitches. The first group includes both plastic and ceramic package outlines allowing 1.50, 1.27, and 1.00 mm contact pitch variations. The second group is designated as a fine-pitch and die size BGA package family allowing ball contact pitch variations of 0.80, 0.75, 0.65, 0.50, and
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IPC-7095B
March 2008
0.75 mm for the die size BGA. Few component manufacturers are currently providing parts with 1.5 mm pitch, as the pressure is on form factor in order to keep BGAs as small as possible and although ball pitch of 0.40 mm and less are allowed, the applications may be limited for conventional surface mount assembly due to difficulty in processing. Pitch plays a large role in the determination of what ball diameters can be used in various combinations. Table 4-2 shows the characteristics of those balls that are used with pitches of 0.5 mm through 1.5 mm. Table 4-2
Ball diameter sizes for PBGAs
Nominal Ball Diameter (mm)
Tolerance Variation (mm)
Pitch (mm)
0.75
0.90 - 0.65
1.5, 1.27
0.60
0.70 - 0.50
1.0
0.50
0.55 - 0.45
1.0, 0.8
0.45
0.50 - 0.40
1.0, 0.8, 0.75
0.40
0.45 - 0.35
0.80, 0.75, 0.65
0.30
0.35 - 0.25
0.80, 0.75, 0.65, 0.50
Although not mandatory, nonsymmetrical ball patterns have the added advantage of enabling automated orientation detection during assembly. One example is to omit one of the corner balls in an otherwise symmetrical array. Although not required for the BGAs shown in Table 4-2, future ball sizes contemplated are shown in Table 4-3. 4.3.2.1 Future Ball Contact Size Conditions
Table 4-3
Future ball size diameters for PBGAs
Nominal Ball Diameter (mm)
Tolerance Variation (mm)
Pitch (mm)
0.25
0.28 - 0.22
0.40
0.20
0.22 - 0.18
0.30
0.15
0.17 - 0.13
0.25
The land pattern of the component substrate (where the ball is attached) and the land pattern of the mounting structure (printed board) should be as similar in diameter as possible. Component manufacturers have determined that the printed board land pattern or the pad on the component should be slightly less than the ball diameter. The amount of reduction is based on the original ball size, which is used to determine the average land. In determining the relationship between nominal characteristics, a manufacturing allowance for land size has been determined to be 0.1 mm between the maximum material condition (MMC) and least material condition (LMC). 4.3.2.2 Land Pattern Approximation
The information shown in Table 4-4 provides data on land patterns and their variation to accommodate six common ball diameters. Many component manufacturers use solder mask defined lands (see 6.2.2). When this technique is employed, the nominal land diameter should be increased by the amount 18
Table 4-4
Land size approximation
Nominal Ball Diameter (mm) Reduction
Nominal Land Diameter (mm)
Land Variation (mm)
0.75
25%
0.55
0.60 - 0.50
0.60
25%
0.45
0.50 - 0.40
0.50
20%
0.40
0.45 - 0.35
0.45
20%
0.35
0.40 - 0.30
0.40
20%
0.30
0.35 - 0.25
0.30
20%
0.25
0.25 - 0.20
of solder mask encroachment on the land (usually about 0.1 mm). The opening in the solder mask window then represents the diameter to which the ball will become attached, while the actual land is slightly larger to accommodate the solder mask defined land concepts. It should be noted that routing density is decreased, since the land is larger. Table 4-5 shows future land size approximations. These indications are for ball sizes from 0.25 mm to 0.15 mm. The same relationships for a solder mask defined land applies as stated for Table 4-4. Table 4-5
Future land size approximation
Nominal Ball Sizes (mm)
Reduction
Nominal Land Size (mm)
Land Variation (mm)
0.25
20%
0.20
0.20 - 0.17
0.20
20%
0.15
0.15 - 0.12
0.15
20%
0.10
0.10 - 0.08
The trend toward higher pin-count ICs and smaller package outlines has enabled companies to improve both product functionality and performance. Table 4-6 will assist the user in calculating variations in land pattern geometry for a wide range of BGA applications. 4.3.3 BGA Package Outline Body sizes for ball grid arrays are divided up into the following two outline groups: square and rectangular. The square outline package family size ranges from as small as 4 mm x 4 mm and as large as 50 mm x 50 mm. In the fine pitch variations you will see the package sizes increase in 1.0 mm increments. In the ranges above 21 mm x 21 mm you will see the body size increase in increments of 2.0 mm to 2.5 mm and the pitches are in the regular range. Rarely will any of the fine pitch parts be found in sizes larger than 21 mm x 21 mm. The rectangular BGA family has the same size ranges from 4.0 mm to 50 mm but varies by each application. This group can have many more variations than the square group. Rectangular sizes typically are found to follow no fixed incremental progression. This group is normally driven by the memory applications and closely follows the die sizes. Rectangular sizes are normally standardized in small application specific families. The fine pitch BGA components, equal to or less than 0.8 mm, rarely exceed 21 mm in body size.
March 2008
IPC-7095B Table 4-6 Land Size
Land-to-ball calculations for current and future BGA packages (mm) Ball Size
RLP
MMC
LMC
Location Allowance
Ball Variation
Nominal
MMC
LMC
% Reduction From Nom.
Variation Allowance
050
0.60
0.50
0.10
0.25
0.75
0.90
0.65
25%
0.25
051
0.50
0.40
0.10
0.20
0.60
0.70
0.50
25%
0.20
052
0.45
0.35
0.10
0.10
0.50
0.55
0.45
20%
0.17
053
0.40
0.30
0.10
0.10
0.45
0.50
0.40
20%
0.17
054
0.35
0.25
0.10
0.10
0.40
0.45
0.35
20%
0.17
055
0.25
0.20
0.05
0.10
0.30
0.35
0.25
20%
0.15
056
0.20
0.17
0.05
0.06
0.25
0.28
0.22
20%
0.08
057
0.15
0.12
0.05
0.04
0.20
0.22
0.18
20%
0.07
058
0.10
0.08
0.05
0.04
0.15
0.17
0.13
20%
0.07
Fine pitch ball grid arrays (FBGA) is a 0.50 to 0.80 mm pitch solder balled array package that has fixed package dimensions ‘‘D (Length)’’ and ‘‘E (Width).’’ The FBGA is more like the plastic and ceramic BGA families described above having fixed body dimensions. Although the FBGA outline is typically only 20% larger than the die, it will not change shape with every die shrink. The die-size ball grid array package (DSBGA) is a 0.50 to 0.80 mm pitch solder balled array package that has variable package dimensions ‘‘D (Length)’’ and ‘‘E (Width).’’ The DSBGA package takes the shape of the die which normally makes it a rectangular outline and is presently widely used in Flash and DRAM Memory devices. The rectangular die size (RDS) outline will likely change ‘‘D’’ and ‘‘E’’ dimensions with every die shrink. 4.3.4 Ball Size Relationships The total variation of the system considers three major issues: positioning, ball tolerance, and substrate tolerance. All three attributes added together result in a worst case analysis, however as with other land patterns in the standard, a statistical average is determined by using the RMS (root mean, square) value. Table 4-6 shows the total variation in the system for each of the nine ball sizes identified in the standards. As noted, the standard nominal dimension for ball contact diameters are 0.15, 0.20, 0.25, 0.30, 0.40, 0.45, 0.50, 0.60, and 0.75 mm. Ball contact size for array packages are influenced by the limit established for overall package height, ball contact pitch and the desire to maximize solder joint reliability.
A critical issue in surface mount packages is the limits for coplanarity of the contacts. The coplanarity requirements in BGA are very different from other lead-frame packaged surface mount components. Coplanarity for BGA is the distance of component contact surface above a common seating plane. Thus, noncoplanarity, a simplified term, is the maximum distance between the lowest and the highest pin when the package rests on a perfectly flat surface. This definition represents a package sitting on a PC board on at least three leads. 4.3.5 Coplanarity
Coplanarity tolerance defines the distance from the seating plane to the highest point of the package. This dimension includes the standoff height, package body thickness and (if present) lid thickness. The measurement criteria do not include attached features such as heat sinks or other components. An integral heat-slug, however, is not considered an attached feature. If the package happens to be laminate substrate based BGA, additional coplanarity issues can be expected due to problems associated with adapting larger substrates and maintaining flatness within the tolerances. This, in part, is the reason why the plastic BGA (PBGA) package coplanarity requirement is established at 150 µm. Most suppliers would like the allowable BGA coplanarity limit to be around 200 µm but the users would prefer the maximum to be no greater than 100 µm (see 4.6.2.6 and 4.8.4). There are different coplanarity requirements for different types of BGAs. Table 4-7 shows a sampling of JEDEC registered BGA package outlines. Table 4-7
Examples of JEDEC registered BGA outlines
Registered Outline
Package Type
Coplanarity
MO-151
Plastic BGA
0.20 mm
MO-156/MO-157
Ceramic BGA
0.15 mm
MO-195
Fine Pitch BGA
0.08 mm
The coplanarity values may vary from JEDEC outline-tooutline because of the ball metallurgy. In low temperature, eutectic (183°C melting point) solder balls, the balls collapse during the assembly operation, therefore the coplanarity requirement is not as tight as a high temperature (302°C melting point) solder balls in which the balls do not collapse during the assembly operation. 4.4 Component Packaging Style Considerations The JEDEC Design Guidelines for BGA do not define specific materials or method of assembly. The base material will vary from one supplier to another depending on application. The base structure is most likely a reinforced organic laminate, a nonreinforced polyimide film or ceramic. Ceramic based BGA package is often supplied with noncollapsing solder balls made of high temperature solder (90% lead, 10% tin) with melting point of 302°C. The ball
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IPC-7095B
size will vary with the pitch and package size. Larger packages will usually have larger ball sizes to improve reliability. Since the ceramic package is relatively very flat, and the tolerances in ball diameters are very narrow, the coplanarity requirements can be relatively narrow as well. The supplier of the ceramic-based package will generally furnish recommendations for selecting a suitable solder paste composition for board level assembly. Laminate and polyimide film-based BGAs are very different, however. The laminate based package is essentially made of circuit board material with a high temperature (Tg) rating. A high Tg rated resin system adopted by several companies for BGA package applications is bismaleimide triazine (BT). Reinforced polyimides and polyimide films have an even higher temperature rating and are also in wide use for both BGAs and FBGAs. 4.4.1 Solder Ball Alloy Solder ball composition is defined by the overall PCA technology, i.e., tin/lead or lead-free, and the package type, i.e., ceramic or laminate substrate. The alloy composition selected for ball contacts on reinforced laminate and polyimide film based BGA packages can vary a great deal. Many are furnished with a tin/lead eutectic solder having a melting (liquidus) point of 183°C (or 179°C for eutectic solder with 2% silver). The ball contacts are commonly applied to the package substrate using only flux and a reflow soldering temperature of 215-220°C to complete the joining process. 4.4.1.1 Tin/Lead Technology Alloys A common alloy used in tin/lead technology BGAs is eutectic Sn63Pb37, with a melting point of 183°C. The eutectic silver containing alloy, Sn62Pn36Ag2, has a melting point of 179°C and is an acceptable alternative to eutectic Sn63Pb37. Ceramic BGAs, when used in the tin/lead technology, typically require the use of the high-lead alloy of Sn10Pb90 to provide the required solder joint reliability. This alloy does not melt during the tin/lead reflow process but when attached to the PCB with eutectic Sn63Pb37 provides a reliable interconnect. 4.4.1.2 Lead Free Technology Alloys For applications requiring a lead-free alloy composition, tin, silver or tin, silver, copper alloys are combined for both solder ball contacts and solder paste. These solders have liquidus temperatures in the range of 210-227°C and require peak reflow temperatures in excess of 240°C; corresponding maximum package temperatures may be as high as 260°C. BGA packages may be supplied with ball contacts that use an alloy composition that is not designed to reach a liquidus stage, thus, noncollapsing. In this application, the noncollapsing ball contact is attached to the package with solder paste composition typical of that used for board level assembly.
Lead-free solder alloys used for BGA balls typically contain Sn, Cu, and Ag. The initial lead-free alloy composi20
March 2008
tions selected for the ball alloys typically matched the assembly process alloys of Sn96.5Ag3.0Cu0.5 (SAC305), Sn95.5Ag3.8Cu0.7 (SAC387) or Sn95.5Ag4.0Cu0.5 (SAC405). To reduce defects related to ball-to-package retention and susceptibility to mechanical strain, some BGA suppliers may adopt additional alloy compositions for the balls. For some packages, the change involves moving from silver (Ag) content in a SAC solder of 3-4% down to 0.3%. The addition of other alloying elements has also been suggested however these additions can affect solder under-cooling, the formation of various intermetallics, unusual matrix properties and changes in solder microstructure. Depending on the specific alloy the melting point of the solder ball can increase by as much as 10°C. This can have a significant impact on the PCA assembly process. Great care must to be taken when introducing new alloys into BGAs and new alloyed BGAs into the assembly process. 4.4.2 Ball Attach Process The package substrate is typically fabricated in a strip format containing multiple packages (see Figure 4-6). Ball contact placement is performed after they have gone through wire bonding and plastic molding or encapsulation process steps. Both automated and semiautomated ball placement is being utilized for volume BGA assembly. Alloy spheres of the desired size (as shown in Table 4-1) are attached either by gang placement machines or dispensed in mass with a stencil-like fixture. For companies doing development or for low-volume placement, simple template fixtures can be provided for precise ball positioning. The overall ball attachment process, however, is the same. To begin, liquid or paste flux is dispensed or printed onto the contact pattern. The flux holds the balls in place during reflow soldering. Reflow soldering of the ball to the substrate is often performed in a nitrogen gas environment. The nitrogen gas environment helps provide consistent ball quality and keeps the surface from oxidizing during reflow. However, nitrogen gas may not be necessary for reflow attachment of the package to the PCB. The eutectic solder balls provide a ‘‘controlled collapse’’ that, during reflow soldering, promotes selfalignment (compensating for some misplacement during assembly).
There are some issues to consider when using plastic BGA packages; these are moisture sensitivity and rework following removal. The plastic cased BGA will require specialized tooling and skills to reball after the package is detached from the board assembly. This may not be the case with the high melting point noncollapsing balls used on ceramic based BGA because they do not melt during rework. The plastic BGA package is also susceptible to warpage when exposed to temperatures required for solder attachment. The edges of the package tend to lift up or curve down during reflow soldering and can severely disturb or
March 2008
IPC-7095B
Chip Encapsulant Bonding Wire
Wire Bond Die
Package Substrate
Package Substrate
Ceramic Substrate (Double Side)
Solder Ball (Lead Free)
IPC-7095b-4-8 IPC-7095B-4-6
Figure 4-6
Plastic ball grid array (BGA) package
interrupt the electrical interface between package and board assembly. The larger packages are even more susceptible to warpage than the smaller packages. The package warpage is caused by CTE mismatch between the substrate structure, the mold compound and the silicon die inside. This problem may become more acute when the die is large, or when the BGA has a heat spreader. 4.4.3 Ceramic Ball Grid Array The internal connections in the ceramic-based package can be either wire-bond or flip-chip. Figure 4-7 shows flip-chip bonding inside the package. The package can be furnished with the die mounted on the top surface of the substrate (cavity up) or with the die mounted to the substrate’s lower surface (cavity down). The solder balls generally used for ceramic package typical of that illustrated in Figure 4-8 are a high temperature alloy composition (90% lead and 10% tin) with a melting point of 302°C. The ball attachment alloy, however, may be a eutectic solder (Sn63Pb37).
Underfill
Solder Balls (Sn3Pb97)
Figure 4-8
Ceramic ball grid array (CBGA) package
reballing for reuse. The disadvantage of the ceramic-based BGA is that its high thermal mass will be much different than the plastic packaged ICs and can make solder reflow profile development more difficult. Because of the CTE mismatch between the ceramic-based package and the host circuit board, users typically apply an epoxy type underfill to stabilize and restrict movement in the component mounting area in order to meet reliability expectations. 4.4.4 Ceramic Column Grid Arrays Solder column contacts typical of that illustrated in Figure 4-9 are used for larger ceramic-based packages (32 mm to 45 mm). The package resembles the earlier pin-grid-array but with closer contact pitch and more fragile leads (columns). The column contact diameter is approximately 0.5 mm with its length varying from 1.25 mm to 2.0 mm. The columns are attached to the package either by eutectic (Sn63Pb37) solder or they are cast in place using 90% lead and 10% tin. The longer columns typically increase solder joint reliability by absorbing a great deal of the thermal expansion mismatch created by the CTE mismatch between the ceramic package and the board.
Sealing Adhesive
Solder Balls (Sn5Pb95)
Underfil
Sealing Adhesive Solder (Sn63Pb37)
Solder Balls (Sn10Pb90) IPC-7095b-4-7
Figure 4-7 Cross-section of a ceramic ball grid array (CBGA) package
Although plastic encapsulation or over-molding is widely used to encase the die area, some ceramic based BGA packaged devices are hermetic (do not absorb moisture). As noted, because the solder balls furnished on the ceramic-based BGAs typically have a high melting point, they do not collapse during rework and may not require
Solder Columns (Sn10Pb90) IPC-7095b-4-9
Figure 4-9 Cross-section of a ceramic column grid array (CCGA) package
Longer columns, on the other-hand, may reduce electrical performance and will increase the overall package height 21
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profile. The columns are not as rugged as ball contacts and are susceptible to handling damage. 4.4.5 Tape Ball Grid Arrays A tape (polyimide film) based ball grid array, illustrated in Figure 4-10, can furnish a lower overall profile package. The low dielectric polyimide film can be furnished with one or two metal layers for high density in-package circuit routing.
Single Metal Tape
Two Metal Tape
IPC-7095b-4-11
Figure 4-11 Comparing in-package circuit routing capability of the single metal layer tape substrate to two metal layer tape substrate
Circuit routing of the single metal material is limited to the narrow gap of dielectric between ball contact attachment sites. As the contact pitch reduces down to 0.50 mm, the space between contact features is reduced to 75 µm, providing the possibility of routing only a single circuit trace. This factor limits the use of single metal layer to a narrow band of low I/O package applications.
IPC-7095b-4-10
Figure 4-10 Polyimide film based lead-bond µBGA package substrate furnishes close coupling between die pad and ball contact
For polyimide-based BGAs, typical of that illustrated, the CTE mismatch is not an issue since the die attach adhesive and substrate flexibility will take up strains within the package structure. Tape-based BGAs can adapt flip-chip, wire-bond or lead-bond to achieve die-to-substrate interconnection. The single metal layer tape substrate is typically used for low cost and low lead count package applications and the two metal layer tape for higher lead count or performance driven applications. An additional layer of copper, for example, can provide an efficient ground return, significantly lowering inductance and reducing the effects of switching noise. The ground plane effect impacts noise level reduction as well but the number of current sinks within the ground plane will also influence inductance levels. The two metal layer substrate compared in Figure 4-11 not only furnishes better electrical performance, it also provides a significant improvement in in-package circuit routability. 22
4.4.6 Multiple Die Packaging Portable and wireless electronics represent the most aggressive growth area for high-density package technology. In both circuit board fabrication and IC packaging, the technology for compressing even the most sophisticated electronic functions into a smaller and lighter finished product continues to evolve.
Portable or hand-held electronics are a natural target. Digital cameras and camcorders, for example, must consider ease of use, lighter weight and performance. Cellular phones, pagers, personal communicators, palm top computers, industrial and automotive electronics, personal GPS, medical and diagnostic products, are all viable candidates for more efficient device miniaturization. Memory devices such as Flash, SRAM and SDRAM are the first commodity type products in the market to adapt FBGA and CSP in high volume. However, digital signal processors, controllers, CPUs and any number of application specific IC devices are also prime candidates for multiple die packaging. Many of the multiple die packages adapt a simple wire-bond process for die-to-substrate interface. The die and wire bond area is then encapsulated or over-molded to furnish the single package outline. Wirebond solutions are capable of furnishing a two or more die stack, but package height increases significantly with each added die layer.
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Two or more ICs encased in a single package outline is more efficient in both size-to-function ratio and may enhance performance. Multiple die packaging potentially increases component density and improves component-tocomponent circuit routing efficiency on the printed wiring board. Some of the multiple die package methodologies attach one die on top of the other on a single substrate as illustrated in Figure 4-12.
Figure 4-13 assembly
IPC-7095b-4-12
Figure 4-12
Custom eight die (flip-chip and wire-bond) SiP
two functions is substantially different and will further compromise the level of confidence the user will have in its use.
Single package die-stack BGA
Die stacking different size die in a pyramid fashion is common but, when the die are the same size, a spacer must be added between each active die to clear the wire-bond loop. 4.4.7 System-in-Package (SiP) To provide space for the additional functions companies are combining a number of related functions into a single package outline. Although some companies choose to develop a multiple function die (system-on-chip), this option may not be practical for many others. Because of the length of time to develop a custom die with mixed function capability, most companies have found that combining (stacking) already proven die within a single package structure more practical (see the die-stack example in Figure 4-13).
The eight die configuration shown above includes two 1Gb NAND Flash die, two 256Mb SDRAM, two 256Mb NOR Flash die, one 128Mb UtRAM and one 64UtRAM die. This is a very impressive application for die stacking and the company, as the supplier of most or all die in the package, is meeting satisfactory yields of the finished package. However, due to the variation in manufacturing processes and differing yield potential of die level product from multiple sources, meeting overall package level cost goals for some are not always attainable. To ensure uncased bare die quality and reliability, some sort of electrical testing must be provided on the bare die prior to package level assembly. ASIC, simple logic circuits, some processors and linear circuits, at some point, tend to stabilize but testing is the only way to guarantee quality and reliability. Combining logic and memory within a single package, for example, poses a very real problem. The testing of these
4.4.8 3D Folded Package Technology Memory die, such as Flash and SRAM, have relatively high fabrication yields. Damage can take place during assembly processing and handling but, overall, the memory packaging process and testing has a very high pass ratio. Flexible substrate material enables the folding of several die into a single FBGA package outline that is only slightly greater than the largest die of the set. Figure 4-14 is a typical folded-flex package application, combining three single memory function die into a single package outline.
IPC-7095b-4-14
Figure 4-14
Folded multiple-die BGA package
4.4.9 Ball Stack, Package-on-Package Although not limited to memory packaging, a key application is the stacking of DDR-SDRAM chips, which enables OEMs and memory module manufacturers to increase the density of their memory boards by up to eight times the current density available today. The stacking of pretested FBGA packaged die is an ideal application for memory. Testing, sorting and grading of memory before joining will ensure that
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the final component configuration furnishes its full performance potential. Figure 4-15 shows an illustration of several ball stack packages as one entire assembly.
IPC-7095b-4-17
Figure 4-17
Figure 4-15
Package-on-package FBGA
Sequentially stacking one pretested FBGA package allows the dramatic increase in component density and functionality. As a practical example of a current application, consider the dynamics and potential for memory capacity on the standard single sided SO-DIMM shown in Figure 4-16.
Folded and stacked multiple die BGA package
tion. Through a process of folding and surface mount attachment, the two pretested sections become a single, high yielding multiple-function component. Furthermore, by providing a universal array pattern interface on the topside of the ASIC package, several variations of memory functions can be soldered directly onto the base package. 4.4.11 Benefits of Multiple Die Packaging The primary benefit in multiple die packaging is the dramatic increase in component density. The size and weight of the product is likely to be reduced and functionality enhanced. The functional enhancement is achieved through the integration of several device types. Other benefits include decreased circuit board complexity, improved product quality through higher reliability and reduced risk in getting the product to market. With multiple sourcing of already proven and mature die, time to market and cost of ownership can be minimized. The task of developing a multiple-die product is not without some obstacles. Some of the key issues are:
• Managing multiple vendors • Known good die test and burn-in methods • Die and wafer availability • Combining high and low yield devices • Overall product quality and reliability IPC-7095b-4-16
Figure 4-16
SO-DIMM memory card assembly
4.4.10 Folded and Stacked Packaging Combination Be-
cause processor and ASIC wafer fabrication yield is not as predictable as memory or less complex functions, pretesting of the individual die before package assembly is a must. In addition, combining two very different yielding products into the same finished package can be very risky. To minimize risk, the idea of building up the multiple-die package sequentially becomes highly attractive. With the ultimate goal of combining several functions in a single package footprint still achievable, assembling and testing individual devices prior to final integration appears ideal. The issues associated with compound yield and test can be easily addressed by stacking separate packages. One example would be to package and test the ASIC separately from the memory functions in a two-section format typical of that illustrated in Figure 4-17. The lower and upper package assemblies with memory are processed and tested prior to the folding and joining opera24
4.5 BGA Connectors 4.5.1 Material Considerations for BGA Connectors The BGA connector shown in Figure 4-18 is designed to provide a relatively low profile horizontal or parallel interface between two circuit assemblies. The material engineered for this application has been developed to withstand the reflow soldering temperatures associated with surface mount assembly and furnish a reliable interconnect in the varying environmental conditions typical of the product’s end use.
It is important to understand the material properties of the connector system. During the life of the product, the circuit board assembly will undergo many varying thermal cycles. These thermal cycles will cause material expansion/ contraction to the assembly components, including the BGA connector. Therefore, material selection for BGA connectors is significant due to the thermal interaction of the connector to the PCB substrate. Specifically, the BGA connector material’s coefficient of thermal expansion (CTE) must be matched to the CTE of the PCB substrate material.
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ments, etc. The material choice is also dependent on the processes used in the manufacture of the BGA and the complexity of the design required to redistribute the chip I/O to area array format. Base materials are selected not only by their electrical characteristics, but also their mechanical properties. Most component manufacturers require that the material used to redistribute the I/Os meet a stress test identified in the JEDEC standard, JESD22, Test Method A102B. The test consists of an exposure in a pressure vessel for 168 hours. This severe accelerated stress test permits the use of only the most robust materials for the substrate interposer.
Figure 4-18
BGA connector
If there is a significant CTE mismatch between the BGA connector (typically a LCP material) and the PCB substrate (typically FR-4), the resulting thermal stresses on the solder joints could cause cracking and ultimately solder joint failure. 4.5.2 Attachment Considerations for BGA Connectors
Several items need to be addressed concerning the placement and soldering of BGA connectors to a PCB substrate. Some BGA connector designs do not lend themselves to a vacuum pick-up using standard SMT nozzles. In this case, two options are available: 1. Mechanical chuck pick-up using a custom nozzle. 2. Design the BGA connector with a cap or other temporary surface so a standard vacuum nozzle can be used. Both options can be successful in production, and the best option is highly dependent on the connector design. Depending on the connector material, reflow profiles have to be examined and compared to the Tg temperature of the connector material. When the temperature of the connector increases beyond the Tg point, the connector will tend to either bow toward the board (‘‘flatten out’’) or bow away from the board (‘‘warp’’). The actual behavior is a function of the connector geometry, connector material, and the surface tension of the connector balls to the substrate. Also included in this analysis are the connector coplanarity requirements for successful soldering. The material properties behavior during reflow and the overall connector size will dictate the connector ball coplanarity requirements. Typically, BGA connectors’ coplanarity requirements are stricter than standard BGA packaged IC components due to their increased size. 4.6 BGA Construction Materials 4.6.1 Types of Substrate Materials A number of different materials are used in the construction of BGAs. The material choice is predicated on a number of different factors including cost, use environment, reliability require-
4.6.1.1 Bismaleimide Triazine-Glass (BT) Bismaleimide triazine resins used in combination with glass fabric reinforcements are a common choice for the fabrication of substrates used in BGA packages. The material is available from a number of sources and provides good thermal performance (based on a relatively high glass transition temperature). In addition, the electrical properties of BT resin (IPC-4101/30 with a Tg range of 170-220°C) are suitable for a great number of IC package applications. 4.6.1.2 Epoxy-Glass (FR-4) A fire retardant epoxy-glass composite can be used for BGA package applications but the material is most commonly used in the manufacture of printed circuits. High Tg FR-4 laminates (tetrafunctional, multi-functional) have been predominantly used in manufacturing multilayer circuit boards, but the material may be suitable for BGA packaging as well. Recent advances in the epoxy-resin material formulation have resulted in greatly improved high temperature performance and rivals BT in terms of glass transition temperature. Another advantage of using FR-4 resin systems for BGA construction is that they are more closely matched in CTE to the circuit board onto which they are mounted. IPC-4101 has undergone extensive expansion to meet RoHS compliance and the requirements of lead-free soldering. The compositions have been formulated to minimize both the rate of decomposition and excessive Z axis expansion during soldering processes (processes that may exceed 260°C). Because manufacturers use widely varying compositions to manufacture epoxy-glass base material, a single slash sheet specification is not possible. Six specifications that are RoHS compliant are IPC-4101/99, /101, /121, /124, /126 and /129. There are only slight differences in composition elements with a Tg range between 110°C and 170°C and a decomposition (Td) range between 310°C and 340°C. All have a UL flammability rating of V-O (see Table 4-8). 4.6.1.3 Fire Retardants for FR-4 In regard to the fireretardant used in manufacturing FR-4 composites, the RoHS directive forbids the use of some bromine compounds, but it does not ban brominated materials used currently as a flame retardant for glass reinforced base materials used for substrate fabrication. Bromine-containing
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March 2008 Table 4-8 IPC-4101B FR-4 property summaries - specification sheets projected to better withstand lead-free assembly IPC-4101B Specification Sheets Property
Tg min (°C)
/99
/101
/121
/124
/126
/129
150
110
110
150
170
170
Tg max (°C)
N/A
N/A
N/A
N/A
N/A
N/A
Td min (°C)
325
310
310
325
340
340
Fillers Flame Retardant Flammability
yes
yes
no
no
yes
no
RoHS BR
RoHS BR
RoHS BR
RoHS BR
RoHS BR
RoHS BR
V-0
V-0
V-0
V-0
V-0
V-0
Max Z-Axis CTE - alpha 1
60
60
60
60
60
60
Max Z-Axis CTE - alpha 2
300
300
300
300
300
300
Max Z-Axis CTE (50-260°C)
3.5
4.0
4.0
3.5
3.0
3.5
T-260 (minutes)
30
30
30
30
30
30 15
T-288 (minutes)
5
5
5
5
15
T-300 (minutes)
AABUS
AABUS
AABUS
AABUS
2
2
UL Max. Operating Temp (°C)
AABUS
AABUS
AABUS
AABUS
130
130
compounds that are outlawed by RoHS are those that remain as independent molecules within the polymeric matrix. These include polybrominated diphenyl ether (PBDE) or polybrominated biphenyl oxide (PBBO) and polybrominated biphenyls (PBB). Bromine-containing compounds that are compliant with RoHS include those that react to become a chemical part of the polymeric matrix, for example, tetrabromobisphenol A (TBBPA). Being RoHS compliant does not mean the base material must be halogen free. Certain brominated flame retardants including the most popular brominated flame retardant for FR-4, TBBPA, are accepted by RoHS and decabromodiphenyl ether (DBDPE) has been given an exemption by RoHS. 4.6.1.4 Ceramic Ceramic is the term used for a general class of substrate based on alumina or aluminum oxide. The material is one of the first used for area array packaging in the form of pin grid arrays and was also the material first used in the construction of its earliest BGA packages. Ceramic substrates have higher thermal conductivity and, using a cavity and lid format, can provide hermetic packaging capability. Ceramic substrate material does, however, have a number of detractors. For example, it is normally more expensive, more brittle, has a higher dielectric constant (which retards signal propagation speed) and has a coefficient of thermal expansion much lower than the typical circuit board structure onto which it is normally mounted. This last point is a major concern and can limit the overall package size and the need to maximize the ball contact size in order to achieve acceptable solder joint reliability of the assembled package. 4.6.1.5 Flexible (Nonreinforced) Base Films Flexible base films are an increasingly common choice for BGA construction. The most common base film for such con-
26
structions is polyimide. Polyimide has a number of attractive attributes, which make it a strong choice for BGA substrates. Among the positive attributes offered by polyimide films are very high temperature limits (~250°C) and relatively low dielectric constant (~3.5 versus ~4.5 for FR-4 and ~10.0 for ceramic). In addition, it is very thin and is much easier to produce the fine line circuit features more commonly required for high-density area array packages. On the negative side, the main concern with nonreinforced or flexible materials has been their dimensional stability. The reinforcement provides the physical characteristics that enhance CTE properties in the X-Y axis. The X and Y axes are the particular segments of the interconnecting product that affect the stress on the solder joints of the package when mounted onto the interconnecting product. In addition, polyimide film is generally more expensive than some of the other reinforced organic base materials and it is relatively hydroscopic. On the other hand, because polyimide films are more flexible, the material will absorb rather than transfer physical stress. 4.6.2 Properties of Substrate Materials While there are numerous properties that are specified and measured, relative to substrate materials, only a few properties are considered key to the performance of the final BGA product.
The coefficient of thermal expansion is a very important physical attribute of a BGA substrate. The CTE defines the rate of expansion of the material with increase in temperature. The importance is magnified when there are large differences in CTE between the BGA package and the circuit board structure to which it is mounted. When the CTE difference is large, excessive strain can be placed on the solder ball connections resulting in lower reliability of the assembled package. 4.6.2.1 Coefficient of Thermal Expansion (CTE)
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4.6.2.2 Glass Transition Temperature (Tg) The glass transition temperature is the temperature at which the resin element of the laminate begins to soften and lose strength. It is also the point at which the resin begins to expand at a much higher rate (i.e., the material’s CTE increases) primarily in the z-axis as the glass fabric controls the in-plane CTE. 4.6.2.3 Flexural Modulus Flexural modulus is important as a measure of the stiffness or rigidity of the substrate. The impact on the BGA is most commonly manifested in the degree of warpage. This in turn can significantly impact board assembly yield if warpage is excessive. 4.6.2.4 Dielectric Properties There are several metrics that are embraced under the general heading of dielectric properties. Dielectric constant, dissipation factor, dielectric withstanding voltage and surface insulation resistance are examples of such properties. These properties are important; moreover, as computers and modules obtain processing speeds towards the 400 MHz level, signal speed and integrity become paramount. The high speed is mainly for the microprocessor. The interconnecting bus speed requirements are somewhat less; in the neighborhood of 100 MHz.
The need for greater performance capability will be apparent as systems designed to be run above 200-300 MHz, continue to use FR-4. As processing speeds continue to increase, it is necessary to lower the dielectric constant and also lower the dissipation factor of the material. The more advanced substrate material systems can provide robust solutions. For example, cyanate-ester provides signal transmission speeds of 114 cm/nsec compared to 100 cm/nsec for common FR-4 epoxy material. Lower dielectric constant (Dk) and lower dissipation factor (Df) must be considered when selecting advanced material technologies. Lower dielectric constant (Dk) benefits include: • Faster conductor signal speed. • Thinner interconnects for the same conductor geometries. Lower dissipation factor (Df) benefits include: • Improved signal integrity with high frequencies.
Table 4-9 shows the different characteristics for some of the materials used to fabricate substrates for BGA applications. Moisture absorption of materials used for BGA construction is something of great concern. The ideal material will not retain any moisture. From a packaging perspective, the concern is predicated on the fact that moisture can be trapped in the laminate base. Entrapped moisture can expand and outgas explosively during assembly causing local delamination, degrading the reliability of the package. 4.6.2.5 Moisture Absorption
4.6.2.6 Flatness Requirements Flatness requirements for BGA substrates must be maintained to assure that the components will not be excessively warped or bowed after package assembly. Such conditions could make testing and the assembly to the next level difficult. The package assembly process will likely improve some of the negative effects once the die is attached, especially if the die is of substantial size relative to the package outline. The recommended flatness criteria for BGA packaging should not exceed 0.3%. 4.7 BGA Package Design Considerations In addition to the die design rules, the substrate designer must understand both thermal and electrical performance issues. BGA package designers must consider manufacturability issues as well: substrate fabrication, first and second level assembly yield and finished package reliability. 4.7.1 Power and Ground Planes In-package power and ground distribution must be planned in advance. For some high-speed applications, entire circuit layers are required for power and ground distribution. Ground and voltage planes are also used when controlled impedance transmission lines are required. In addition, a quiet ground needs to be separated from a noisy ground where all the switching activity takes place. Some applications require several power supplies with different voltages for each part of the chip. These planes should be distributed evenly on the BGA package substrate to minimize component warpage.
For applications requiring a solid power or ground plane, a minimum of a four-layer substrate is required. The four
• Less signal loss at high frequencies.
Table 4-9 Typical properties of common dielectric materials for BGA package substrates Material Property
Dielectric Constant (Neat Resin)
High Performance Epoxy
Bismaleimide Triazine/ Epoxy
Polyimide
Cyanate Ester
3.4
2.9
3.5 - 3.7
2.8
70.9 [1.8]
47.2 [1.2]
70.9 [1.8]
65.0 [1.65]
Volume Resistivity (x 106 D-cm)
4.9
4.0
2.1
1.0
Water Absorption (wt%)
0.3
1.3
1.3
0.8
0.012
0.015
0.01
0.004
Electric Strength (x 103 V/mm) [x 106 V/in]
Dissipation Factor Note: Also see Table 5-1
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layer substrates will also exhibit lower thermal resistance and higher power dissipation compared to two-layer packages. In thermally enhanced BGAs where a copper heat sink is incorporated inside the package, the heat sink is commonly used as a ground plane. By connecting ground lines through vias to the heatsink, the heatsink becomes an active current-carrying ground plane. There are three major BGA package design considerations that affect signal integrity. 4.7.2 Signal Integrity
1. Reflections due to discontinuation in the characteristic impedance lines. 2. Cross-talk between adjacent lines generated from the coupled noise between an active line and the quiet line. 3. Switching noise generated from multiple outputs switching simultaneously, which is commonly known as ΔΙ noise or SSO noise. Multiple simultaneously switching outputs (SSOs) require the power and supply lines to have a lower effective inductance (Leff): ΔI Noise = Leff
• Solder ball attach integrity (4.8.3) • Ball coplanarity (4.8.4 Package Coplanarity) • Moisture sensitivity (4.8.5) • Shipping medium (4.8.6) • Solder ball alloy (lead vs. lead-free) (4.8.7) • Ball size and shape • Module flatness/package bow. • Presence of contamination. • CSAM (C-mode scanning acoustic microscopy) for delamination. 4.8.1 Missing Balls Missing or damaged ball contacts are not acceptable on incoming BGA components. Figure 4-19 provides an illustration of balls missing from the BGA package.
di in millivolts dt
The effective inductance in a BGA package depends on the number and placement of power and ground pins in relation to the power and ground pads on the die. By proper pin assignments for power and ground pins and commercially available signal integrity tools, Leff as well as the ΔΙ noise can be minimized. 4.7.3 Heat Spreader Incorporation Inside the Package
A heat spreader may be incorporated inside the package when the chip power exceeds the maximum power dissipation that can be supported by the package substrate. Due to lower functional conductivity of some laminate material, most of the heat generated by the IC is carried through the copper conductors, plated through-hole vias, and the solder balls. By furnishing a copper plane or section under the die mounting area, a heat spreader is incorporated into the package. It is important that the package design is as thermally balanced as possible to avoid excessive warpage during temperature changes. In ceramic-based BGA the heat spreading can be achieved by replacing the low conductivity alumina-based ceramic material by high conductivity copper-tungsten materials having a thermal expansion coefficient matched to alumina substrate materials. 4.8 BGA Package Acceptance Criteria and Shipping Format There are several issues related to the acceptance
criteria for BGA packages. These include having a process control strategy during qualification and production where sampling plans are used to define the level of nonconformance. The major issues are: • Missing balls (4.8.1) • Voids in solder balls (4.8.2) 28
Figure 4-19 component
Example of missing balls on a BGA
Voids in solder balls should be based on incoming acceptance criteria or post-assembly solder joint acceptance criteria. There is a fundamental difference in whether voids are present in solder balls prior to assembly or afterwards. 4.8.2 Voids in Solder Balls
Voids typical of that shown in Figure 4-20 may or may not dissipate during board level assembly processing. Voids found in solder balls at incoming inspection indicate reduced solder volumes in the solder balls. This will translate to smaller collapsed solder ball stand-off heights and thus may reduce reliability. For voids found during post-assembly inspection, reliability of the solder joint may be compromised if a void is excessive due to the reduction of solder cross-section and/or surface bonding area both at the interposer and the product board. It will be necessary to establish an acceptable level of voiding so that the product can meet customer expectations, has a useful working life and meets product
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reliability requirements. See 7.5.1 for post assembly process control criteria for solder ball voids.
Flattened bottom of a solder ball
Figure 4-21 conditions
Pad on an FBGA where it was supposed to be attached
Examples of solder ball/land surface
4.8.4 Package Coplanarity Package Coplanarity is the result of all of the following factors: Figure 4-20 Example of voids in eutectic solder balls at incoming inspection
1. Package thickness, pitch, and thermal requirements. 2. Substrate design, material, and manufacturing processes. 3. Number of devices (silicon) - size and thickness.
One of the factors the success of the BGA package depends upon is reliable solder ball attachment. The solder balls need to be attached within acceptable dimensional tolerances. Their height and width after attach need to be within specified and/or acceptable limits. Most important of all they need to form a proper metallurgical bond with the lands on the substrate. All the solder balls need to see a temperature profile which ensures wetting necessary for optimum connection. If the joint does not wet (that is, it makes a cold solder joint) then the solder ball is not properly attached for necessary mechanical and electrical interconnect. Such balls may fall off during shipping, transportation and handling or may fail or act intermittently during electrical testing. Figure 4-21 shows the surfaces of the solder ball and the land, which did not wet to form a metallurgical bond. The first picture shows the flattened bottom of a solder ball and the second picture shows the pad on an FBGA where it was supposed to be attached. Attach temperature did not reach high enough for the tin in the solder to dissolve some of the base metal and to form an intermetallic compound (IMC) to form a good metallurgical bond. Only a small amount of force dislodged the solder ball from the pad since it was held in place only by mechanical adhesion. 4.8.3 Solder Ball Attach Integrity
Solder ball attach integrity can be evaluated through solder ball shear. Manual and automated shearing and shear force recording instruments are available for that purpose. For shear tests it is not the magnitude of the shear forces that is important, but the failure mode. Brittle interfacial failure is a clear sign of inadequate wetting. Failures at the solder interface, indicated by ripping soldering pads out of the resin matrix of the BGA or the lands of the PCB, are positive indications of good wetting. For a good attach, there should be no unwetted areas.
4. Number of passives - size and thickness. 5. Assembly materials and manufacturing processes. Coplanarity that is currently specified at room temperature is not always ensuring that the component will have a proper joint formation at SMT. The package behavior during reflow (dynamic warpage) could result in good or bad contact with the solder during reflow regardless of room temperature coplanarity. The dynamic warpage of the package depends on the package CTE (package size, die size, package material). The dynamic warpage signature could be characterized by Shadow Moiré technique and should be meeting the warpage reflow specification. The final package coplanarity is a very complex combination of these factors. A large percentage (~70%) of the package coplanarity is controlled by factors 1 and 2. The type of solder ball used will determine how much overall package coplanarity can be tolerated during the final package to board assembly. The reason why collapsing eutectic solder and tin-alloy based balls are the most popular is because they can compensate for larger package coplanarity values. The JEDEC design guidelines currently define the ball contact diameter (b) at its maximum diameter, as measured in a plane parallel to the seating plane, Datum C. The detail illustrated in Figure 4-22 defines the profile tolerance zone controlling coplanarity (ccc) and the limits for parallelism between the package top surface (bbb) and the seating plane (Datum C). Package height is measured from top surface of the package to the seating plane (where the ball meets the mounting surface of the host printed circuit board). It is important that the top surface of the package remains parallel to the seating plane, accommodating component handling in test, inspection and assembly. The bilateral tolerance zone 29
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Components are segregated into eight levels as shown in Table 4-10. These classes define how long a component can be left out on the production floor once removed from its sealed shipping bag. Parts exposed to ambient air for longer than the specified time must be rebaked prior to use, to drive out excess absorbed moisture.
bbb C nX ccc C
C Figure 4-22
Table 4-10
A1
Establishing BGA coplanarity requirement
(bbb) for parallelism references the top surface of the package with respect to Datum C, the seating plane. Tolerance limits for coplanarity varies slightly with the increase in ball diameter. The following shows the Controlled Coplanarity (ccc) per ball size: 4.8.4.1 Example for FBGA Coplanarity
0.30 mm ball = 0.08 mm (ccc) 0.40 mm ball = 0.10 mm (ccc) 0.50 mm ball = 0.12 mm (ccc) The unilateral profile tolerance zone (ccc) extends upward from the seating plane. The lowest point of the ball contact must be within the tolerance zone. Each ball has a tolerance zone associated with diameter ‘b’ that is located on true position with respect to Datums A and B and is perpendicular to Datum C. The center of each ball must lie within the tolerance zone. The positional tolerance for the ball contact is defined with relationship to package outline Datums A, B and C, as illustrated in Figure 4-23.
b nX ddd M C A B eee M C IPC-7095b-4-23
Figure 4-23
Ball contact positional tolerance
The array of tolerance zones associated with the ball diameter (b), spaced on a basic pitch (e), controls the location of the balls. The design guideline allows the array to float with respect to the tolerance zone ‘ddd;’ however, the centers of the balls must simultaneously lie within both tolerance zones. For more detail in measuring the BGA package see JEDEC JEP95, Section 4.17 (BGA Package Measuring and Methodology). 4.8.5 Moisture Sensitivity (Baking, Storage, Handling, Rebaking) Moisture sensitivity requirements are defined
by J-STD-020 and J-STD-033. The J-STD-033 provides information on handling moisture sensitive components. 30
Moisture classification level and floor life
IPC-7095b-4-22
Floor life (out of bag) at factory ambient ≤30°C/60% RH or as stated
Level
1
Unlimited at ≤30°C/85% RH
2
1 year
2a
4 weeks
3
168 hours
4
72 hours
5
48 hours
5a
24 hours
6
Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label
Many BGA components are moisture sensitive; particular attention should be paid to tape ball grid array (TBGA) and flip chip PBGA components. Ceramic BGA/CGA components are generally not moisture sensitive. It is recommended that BGAs meet at least Level 3 specifications. Level 5 and 6 parts are particularly undesirable from a manufacturing handling perspective, because they drive additional shop floor and component handling controls. In the case of Level 6 parts, bake-out ovens will be required. Bake-out may take between four hours and 48 hours at 125°C or five days to 68 days at 40°C depending on package thickness and size. In order to remove moisture from BGA components a recommended bake cycle should be established. It should be noted that the higher reflow temperatures required for lead-free solders may require a more rigorous moisture removal bake cycle. However, the J-STD-020 requires a shorter time in which the package is permitted to absorb the moisture. 4.8.6 Shipping Medium (Tape and Reel, Trays, Tubes)
As with all SMT components, BGA parts should be packaged in ESD (electrostatic discharge) packaging which meets the requirements of the appropriate standards or specifications. BGA components should be available in JEDEC approved matrix trays able to withstand multiple bake cycles, as many BGAs are moisture sensitive. See 4.8.5 for required bake temperatures and times for the different classes of moisture sensitive components. It may be preferable to procure high volume parts, e.g., SRAM or DRAM devices, in tape and reel for faster assembly cycle times. Component size and moisture sensitivity may dictate that tape and reel is not applicable for some BGAs. Tape widths up to 56 mm are available, and a tape ‘‘leader’’ of at least 200 mm should be provided. Caution must be used when baking parts in tape-and-reel, as
March 2008
IPC-7095B
this type of packaging is usually restricted to lower bake temperatures than matrix trays. 4.8.7 Solder Ball Alloy Component manufacturers should establish a method to clearly identify the metallurgy of the solder alloy used for the BGA balls, accompanied by a part number change. The J-STD-609 provides a convenient method to identify the BGA ball alloy. Users may want to verify the BGA alloy using screening methods such as XRF. 5 PCBS AND OTHER MOUNTING STRUCTURES
PCBs and other similar types of interconnection platforms serve the mounting structures for BGAs and other components. There are a variety of alternative mounting structures available which serve BGA needs as interconnection substrates for electronic assemblies. These structures employ a wide range of materials, both organic and inorganic and, not surprisingly, have a wide range of physical properties. Materials choice is normally made based on cost/ performance needs of the finished product. 5.1 Types of Mounting Structures Following is an examination of some of the more commonly used mounting structure substrates.
Organic substrates are the most commonly used in the construction of electronic interconnection structures. There is a well-established worldwide manufacturing base for this type of product. As a result of the large manufacturing base, this type of interconnection structure has the lowest cost among the competing technologies. Organic materials have intrinsic beneficial electrical properties. Most notable is a relatively low dielectric constant on average which can be made much lower by the proper choice of resin and reinforcement. Organic substrates are commonly reinforced using an appropriate material such as woven glass cloth; however, flexible circuit materials are not commonly reinforced. 5.1.1 Organic Resin Systems
5.1.2 Inorganic Structures Inorganic substrates are an alternative to the organic substrates. They are commonly refractory materials comprised of sintered metal oxides. While they are typically brittle, they have some significant benefits not easily obtained with organic substrates.
Chief among the advantages are excellent thermal properties. Like organic structures there are a number of possible choices available: ceramic, silicon, and enameled metals. The dielectric properties of these materials tend to be higher than organic based materials and, because they are brittle, they are generally more prone to breakage. Because of the more limited vendor base for inorganic substrates, these structures are normally more expensive. 5.1.3 Layering
(Multilayer,
Sequential
or
Build-Up)
While single and two metal layer circuits are still common,
multilayer interconnection structures are commonly required to support the interconnection of BGAs in today’s high performance electronics. There are several approaches to creating multilayer circuit product. The traditional multilayer is created by printing and etching thin layers of copper clad substrates and laminating them into a monolithic structure which can be drilled and plated so as to make connection between the layers where required. More recently, however, alternative structures have been developed to address the higher density and routing difficulties associated with BGAs. These newer structures employ a variety of different approaches to create suitable multilayer structures. The new structures are variously referred to as build-up multilayers, sequential multilayers and co-laminated multilayers. A key feature of these structures is their use of very small vias. The term microvias has been applied to describe these miniscule interconnections. A typical microvia is less than 150 µm in diameter and has a capture land (where the via starts) and a smaller target land (where the via ends). Figure 5-1 shows several examples of different high density interconnect (HDI) printed boards (see IPC-2226). 5.2 Properties of Mounting Structures 5.2.1 Resin Systems There are a number of different resins systems suitable for use in organic laminate construction. There is a long and well understood history and years of faithful service among the traditional resins systems. However, to support the move to meet legislated lead free requirements by the EU, many new resins are being developed to meet the higher temperature assembly reflow requirements. Test methods have been developed, i.e., Td (Temperature of decomposition) and T260, T288, T300 (Time to Delaminate), to quantify material properties for conformance to the new EU requirements. Some of the new resin systems are classified to new material slash sheets such as IPC-4101 /99, /101, /121, /124, /126 and /129.
There are a number of different resin systems that can be used to create a printed wiring substrate. Epoxy is among the organic resins with the longest history and it is one of the most commonly used resin systems for PCBs. It offers a good blend of physical, electrical and processing properties at reasonable cost. The general properties are provided in Table 5-1. Higher temperature capability epoxy resin systems have been developed for leadfree applications and are available at a cost premium.
5.2.1.1 Epoxy
5.2.1.2 Polyimide Polyimide offers the highest operating temperature among resin systems in use today. It has been a favorite for military applications where the potential for board rework and repair in the field with uncontrolled soldering tools is anticipated. Because of its high glass transition temperature, polyimide provides a safety margin and
31
IPC-7095B
March 2008
A
B
C
D
IPC-7095b-5-01a,b,c,d
Figure 5-1 A. B. C. D.
Examples of different build-up constructions
Piercing post co-laminated structure - Type IV HDI Construction Sequentially built-up multilayer - Type II HDI Construction Passive substrate with external microvia layers interposer - Type IV HDI Construction Filled via sequentially co-laminated substrate - Coreless Type V HDI Construction
Table 5-1
Environmental properties of common dielectric materials Material FR-4 (Epoxy E-glass)
MultiFunctional Epoxy
High Performance Epoxy
Bismaleimide Triazine/ Epoxy
Polyimide
Cyanate Ester
Coefficient of Thermal Expansion, xy-plane, CTE(xy) (ppm/°C)
16 - 19
14 - 18
14 - 18
~15
8 - 18
~15
Coefficient of Thermal Expansion, z-axis below Tg1, CTE(z,
50 - 85
44 - 80
~44
~70
35 - 70
~81
Coefficient of Thermal Expansion z-axis above Tg1, CTE(z,>Tg) (ppm/°C)
240 - 390
240 - 390
240 - 390
TBD
TBD
TBD
Thermal Expansion z-axis, TE(50-260°C) (%)
3.0 - 4.5
2.5 - 4.0
2.0 - 3.5
TBD
TBD
TBD
Glass Transition Temperature , Tg (°C)
110 - 140
130 - 160
165 - 190
175 - 200
220 - 280
180 - 260
Decomposition Temperature3, Td (5%) (°C)
310 - 330
320 - 350
330 - 400
~334
~376
~376
Soldering Temperature Impact Index4, STII
170 - 205
200 - 220
215 - 260
TBD
TBD
TBD
Fill5 Warp6
18.6 12.0
18.6 20.7
19.3 22.0
20.7 24.1
26.9 28.9
20.7 22.0
Fill5 Warp6
413 482
413 448
413 524
393 427
482 551
345 413
0.5
0.1
0.3
1.3
1.3
0.8
Environmental Property
2
Flexural Modulus (GPa)
Tensile Strength (MPa)
Water Absorption (wt%)
1. CTE (z,
Tg) as Alpha 2. Contact supplier for specific values of the other materials. 2. The glass transition temperature can be measured by three different methods (TMA, DSC, DMA). Of these the values obtained by TMA are the most pertinent for the purpose of assessing reliability issues. A very rough relationship between the results of these three methods is Tg(TMA) ≈Tg(DSC) -10°C ≈Tg(DMA) -20°C. Contact supplier for specific values of other materials. 3. The decomposition temperature can be measured to two different values of weight loss, Td (2%) and Td (5%). Td (5%) is more commonly used, but Td (2%) is becoming popular because of its greater usefulness. Contact supplier for specific values of other materials. 4. Soldering Temperature Impact Index, STII, which is defined as STII = Tg/2 + Td/2 — (TE%(50 to 260°C) x 10). 5. Fill - yarns that are woven in a crosswise direction of the fabric. 6. Warp (cloth) - yarns that are woven in a lengthwise direction of the fabric.
32
March 2008
potential to reduce damage to the board when uncontrolled soldering irons are used to remove or replace a component. The general properties are provided in Table 5-1. 5.2.1.3 Bismaleimide Triazine Bismaleimide triazine or BT resin is the most popular choice for the construction of BGA packages because of its combined advantages of high temperature capability at reasonable cost. The general properties are provided in Table 5-1. 5.2.2 Reinforcements Reinforcements provide the dimensional stability and the bulk of the mechanical properties of the organic substrate laminate. Following are some of the more commonly used reinforcements. 5.2.2.1 Glass Cloth Glass cloths are the most commonly used reinforcement for printed board substrates. They are widely available and are processed with relative ease. The cloths are available in a number of different thicknesses and weaves. The chemical make-up of the glass can vary and can affect the electrical properties. Presently, E type glass is the most commonly used glass cloth for printed circuit substrates.
Glass felt or nonwoven glass mat has been commonly used as a reinforcement material for fluoroplastic resins and is commonly used in low loss, RF or microwave applications. It has seen some application in formable laminates as well but the technology was not widespread. 5.2.2.2 Glass Felt
5.2.2.3 Aramid Cloth Aramid cloth has been used to reinforce certain laminates. It is unusual in that it has a negative CTE in the X and Y direction, which helps to offset the in-plane CTE of the resin. Because of the counteracting expansion and contraction, laminate materials of this combination can match approximately the CTE of ceramic. However, a drawback of the material is that the aramid has Z axis CTE much higher than glass and, in thermal excursions, can fracture nearby resin, leaving microcracks along the surface of the fibers. 5.2.2.4 Aramid Paper The supply of nonwoven aramid paper has diminished due to a lack of manufacturing sources. Aramid papers have been effectively used in a number of multilayer applications. They have most of the benefits of the aramid cloth with more process latitude. They are often used for thin core layers at or near the surfaces of the printed boards to better control CTE. Because the aramid is organic, it has the added advantage of being more easily processed by laser ablation and and can also be processed using plasma etching for making holes. The organic nature of the material also helps to keep the dielectric constant low. 5.2.3 Laminate Material Properties There are a number of different material properties that are important in the selection of a laminate for BGA substrate manufacture.
IPC-7095B 5.2.4 Reliability Concerns with High Lead-Free Soldering Temperatures The higher temperatures required for
soldering lead-free solders creates reliability concerns for the survivability of the PCB resins as well as the integrity of the PCB interconnect structures, such as plated-through holes and vias. The properties that are most important in this respect are the thermal expansion, the glass transition temperature and the decomposition temperature. The thermal expansion from 50-260°C, TE(50-260°C) is a composite of the thermal expansions below and above the glass transition temperature. The glass transition temperature (Tg) locates a temperature range within which resins change molecular structure from a glassy to an amorphous state; these different molecular structures result in very different physical properties. The decomposition temperature (Td) measures the temperature at which the resin decomposes irreversibly, and thereby loses weight; typically the temperature to a weight loss of 2% or 5% is measured. The impact of these three properties is captured with the Soldering Temperature Impact Index, STII, which is defined as STII = Tg/2 + Td/2 — (TE%(50-260°C) x 10). 5.2.5 Thermal Expansion Thermal expansion is usually characterized in terms of changes to the x-y plane, which is controlled primarily by the reinforcement of the material. The x-y expansion will have the greatest effect on surface mounted components and their reliability. Thermal expansion also occurs in the z-axis at a rate significantly larger than in the x-y plane, particularly at temperatures above the Tg. The z-axis expansion will have its greatest effect on plated-through hole and via reliability.
Table 5-1 shows the conditions for various reinforced resin types. All thermal expansion is measured in parts/million/ change in temperature (°C). 5.2.6 Glass Transition Temperature Glass transition temperature is that property of the material where the reinforcement and the resin systems transition from a linear coefficient of thermal expansion and begin to soften and expand at a much higher rate. This usually occurs when the resin system exceeds its cured polymer state. It is usually an expansion in the z-axis of the material and the temperature stated expands at a faster rate, although still linear (mm/mm of thickness). Table 5-1 shows some of the characteristics of the conditions for glass transition temperature of various material types. Figure 5-2 illustrates the concept graphically and shows how different resins might perform.
Laminates of different resins often have different Glass Transition Temperatures resulting in different capabilities in high temperature applications. Lead free with its high temperature processing will require higher performance laminates. These normally are a higher cost. The glass transition temperature can be measured by three different methods (TMA, DSC, DMA). Of these the values 33
IPC-7095B
March 2008
Resin laminate system 2
Expansion
Resin laminate system 1
Tg-2
Tg-1
Temperature IPC-7095B-5-2
Figure 5-2
Expansion rate above Tg
obtained by TMA are the most pertinent for the purpose of assessing reliability issues. A very rough relationship between the results of these three methods is Tg(TMA) ≈Tg(DSC) -10°C ≈Tg(DMA) -20°C. 5.2.7 Moisture Absorption Most organic materials are hygroscopic to some degree and soak up moisture at different rates, some do so relatively rapidly. This moisture absorption changes the electrical properties of the material such as loss tangent and as well the processing characteristics of the material as outgassing can result in blisters. It can also impact physical dimensions and the laminate’s weight. Thus a simple way to determine that the material has absorbed moisture is to note the increase in weight under defined moisture exposure conditions. Table 5-1 shows the water absorption rate by weight for the various materials highlighted in this section. 5.3 Surface Finishes PCB surface finishes serve several functions, these include: solderability provision and protection, reliable contact surface for contacts/switches, wire bondable surface, and solder joint interface. Although BGAs are the focus of this document, the other components and assembly operations of the PCB must be taken into consideration when choosing the most appropriate surface finish. There is no single surface finish that will be best for all applications.
While no surface finish is ideal for all applications, the search continues for improved surface finish solutions. Although early results look good for some of the immersing surface finishes, immersion silver in particular, more testing and industry experience is required before conclu34
sions can be drawn regarding BGA solder joint reliability and new surface finishes. Some of the application features that must be considered in selection of a suitable surface finish are given in Table 5-2. 5.3.1 Hot Air Solder Leveling (HASL) The current surface finish of long standing is hot air solder leveling (HASL). In this process, the finished circuit board is dipped either vertically or horizontally into a molten solder bath at about 260°C and the excess solder is blown away and leveled with hot air, giving the process its name. The HASL process is the first soldering stress that the printed board experiences. Some material combinations may be prone to delamination during the multiple excess temperature exposure. 5.3.1.1 Tin Lead HASL Although the tin lead surface finish was the main solution for printed boards, one concern with the HASL process is the coating thickness uniformity. Often in the process, the solder thickness varies widely from 0.75 µm to 35 µm. It is generally held that the lower thickness is not acceptable because the very thin layer of solder is completely transformed into copper-tin intermetallic, which has very poor solderability. However, studies on the solderability evaluation of printed circuit boards with HASL and other protective coatings indicate that soldering performance as indicated by visual examination showed absolutely no correlation to the solder thickness or solder coverage on the lands observed in cross-sections. As a result, acceptance criteria for the solderability of printed circuit boards should include or be entirely based on functional testing of sample boards.
March 2008
IPC-7095B Table 5-2
Key attributes for various board surface finishes
HASL SnPb/SnCu*
OSP
Electroless NI/ Immersion AU
Electrolytic Ni/ Electroplated AU
Immersion Silver**
Immersion Tin
Shelf Life proper Handling
1 Year
6 Months
>1 Year
>1 Year
6 Months
6 Months
Handling
Normal
Avoid physical contact
Normal
Normal
Avoid physical contact
Avoid physical contact
Domed/Flatter
Flat
Flat
Flat
Flat
Flat
Good, although intermetallics increase/need robust laminate
Fair, better with thick coatings; may see bare copper if reflowed with lead-free solder paste
Good
Good
Good
Good
No Concerns
May require more aggressive fluxes/and Nitrogen Atmosphere
No concerns
No concerns
Possible flux residue incompatibility
Possible flux residue incompatibility
Use on thick PCBs
Barrels difficult to fill and clear
PTH fill concerns
Improved barrel reliability
Improved barrel reliability
PTH fill concern
PTH fill concern
Use in thin PCBs
No, prone to warping/Avoid
Yes
Yes
Yes
Yes
Yes
Gold embrittlement concerns
Planar microvoid concerns
Good
SMT land Surface topology
Multiple assembly reflow cycles
Soldering Fluxes and Atmospheres
Solder joint reliability
Good
Good
BGA ‘‘black pad’’ concerns
Card edge contacts
Additional plating operation
Additional plating operation
Additional plating operation
No additional plating
Additional plating operation
Additional plating operation
No
No
No
Yes
Yes
Yes
Test point probing
Good
Poor, unless solder applied during assembly
Good
Good
Good
Good
Exposed Copper after Assembly
No
Yes
No
No
No
No
Switches/Contacts
No
No
Yes
Yes
Yes
No
Waste Treatment and Safety in PCB Fabrication
Poor/Fair
Good
Fair
Fair
Poor
Good
Process Control
Thickness control concerns
Fair
Phosphorus content concerns
Gold thickness control concerns
Microetch and plating concerns
Tin whisker concerns
Coating thickness/µm
0.8 - 0.38
0.2 - 0.5
3-7/0.05 - 0.10
0.8 - 2.5
0.07 - 0.10
1.0 - 1.3
General Cost Comparison
1
0.4 - 0.6
2.0 - 3.0
1.2 - 1.5
1.1 - 1.6
~0.8
Sporadic brittle fracture
Wire bonding
* Tin copper alloy is the preferred alloy for lead-free HASL ** For reflow operation >1 year if sealed in Moisture Membrane Bag (MMB)
35
IPC-7095B
The wide variation seen in solder thickness in HASL affects the coplanarity of solder termination on the PCB and hence the components. Moreover, the uneven surface makes more difficult the paste-printing task, because it makes it more difficult to achieve good sealing of the stencil while printing. Lack of a good seal or ‘‘gasketing’’ will result in leakage of solder paste beneath the stencil. The result is that the manufacturer must either increase the frequency of cleaning (thus lowering throughput) or risk increased potential for bridging (thus lowering yield). The increase in the use of thin PCBs (<0.5 mm in thickness) in many applications such as PCMCIA (personal computer memory card international association) cards, may preclude the use of HASL because of warping of the PCBs during processing. 5.3.1.2 Lead-Free HASL The lead-free hot air solder leveling process has proven to provide both quality and reliability of the surface finish in providing long shelf life solderability. Like most of lead-free technology, the process for lead-free HASL is still in the early stages of implementation.
The HASL finish provides a virtual guarantee of solderability in that the process creates one half of the soldered joint by fully wetting the copper substrate. The quality of the product regarding solderability can be confirmed easily through a simple dip test, conditioned by an aging process or by simple visual inspection. Any evidence of nonwetting or dewetting is immediately apparent as the board exits the process. A surface finish of using solder provides long solderable shelf life. Solderability is lost only when the intermetallic has grown through the surface. Thus, a properly applied coating can last more than a year if stored correctly. In addition, the coating’s solderability properties will survive several cycles of adhesive cure or paste reflow. The most likely candidates for lead-free HASL are Sn-Cu eutectic (227°C melting point), or Sn-Ag-Cu eutectic (217°C melting point). The Sn-Ag-Cu alloy appears to offer an advantage due to its lower melting point, but there are advantages of the tin-copper system since the raw materials are readily available, and represent the lowest cost. The Sn-Cu solder pool is easy to manage and recycle since there are only two constituents. The solder bath is not too aggressive, has low copper pick up characteristics, and is relatively tolerant of common impurities. The melting point is low enough for most current equipment and components and, with some of the newer laminate properties, is compatible with the printed board fabrication sequence and processing. In order to fine tune the process, solder alloy bath suppliers have added a proprietary stabilizing constituent—HASL, which is identified as Sn-0.7Cu. A typical alloy developed for lead-free soldering 36
March 2008
is the SnCuNi with a melting temperature of 227°C and a processing temperature for soldering at 250°C to 260°C (482°F to 500°F). Copper dissolution can be a problem if the bath exceeds 0.85% copper which will likely increase in the incidence of bridges, icicles, and other defects. The Sn-0.7Cu+Ni is 227-265°C (38°C variation) vs. Sn63Pb37 183-250°C (67°C variation). All high tin alloys are more expensive than the tin/lead alloy they replace because a low cost material (lead) is replaced by high cost tin and silver. There is some cost compensation to the extent that because of their lower density, the high tin alloys provide a 12% greater volume for the same weight. Also, the stabilized Sn-0.7Cu has the advantage of not containing very high cost silver and has a low dross rate compared with other lead-free alternatives and tin/lead. The copper content of the Sn-0.7Cu can be managed without the need to scrap all or part of the solder bath. The Sn-0.7Cu+stabilizer HASL is a reasonable alternative for those applications that need lead-free processing. The process can be carried out with a thermal excursion that the new laminates, resists and other coatings (e.g., carbon paste) can tolerate without significant degradation, and without unacceptable warpage (bow and twist). Very thin boards are still problematic and require special fixtures, which is the same for any of the HASL processes. The finish has good solderability which is retained through thermal excursions and storage. The finish is smooth and bright and less domed than the tin/lead it is replacing (see Figure 5-3). The solder bath composition can be held stable by the use of a low copper top-up alloy, and dross losses are low. Most important is that the alloy is not aggressive towards solder bath materials.
Figure 5-3 Hot air solder level (HASL) surface topology comparison
In situations where large boards (>250 x 250 mm) are used with large BGAs (>25 x 25 mm), it may be a good idea to increase PWB thickness to at least 2 mm to minimize board bending and flexing. This will reduce or eliminate interfacial failures due to mechanical stress that is caused by bending and flexing of the PWB. However, with the conversion to lead free, thicker boards will require a greater time at temperature exposure making reliability a greater concern.
March 2008 5.3.2 Organic Surface Protection (Organic Solderability Preservative) OSP Coatings With wide spread use of ball
grid array (BGA) and more fine pitch devices, the need for increased control of PCB flatness is more critical. As an alternative to HASL, which can cause warping, the popularity of alternative surface finishes in general, and organic solderability preservative (OSP) in particular, is increasing. An OSP is an anti-tarnish coating of an organic compound (such as a benzimidazole-based compound) which is applied over exposed copper surfaces to prevent oxidation. An OSP is commonly a water-based organic compound that selectively bonds with copper to provide an organometallic layer that protects the copper, preserving its solderability. Various chemistries of OSPs are available. Some common ones are benzotriazol, imidazol and benzimidazol. These coatings keep the copper surface solderable by preventing it from oxidation or tarnish. The coating is commonly applied either by dipping the board in an OSP bath or by spray. As long as the process is controlled to achieve uniform OSP coating, either method will work. The coating thickness can range from very thin (0.01 µm) to relatively thick 0.2 to 0.5 µm (note: 25 µm equals 0.001 inches). The thicker coatings are preferred over the thinner coatings, especially if there is need for multiple reflow cycles and/or a long wait (e.g., days) between soldering of each side. It should be noted that all OSPs are not alike since there are specially developed OSPs to withstand the higher reflow profiles associated with lead free.
IPC-7095B
edges and corners of surface mount lands). It is thus important for flux to get into the PTH during wave soldering to achieve topside fillet. Similarly, in the SMT process, the paste must cover the entire land surface to avoid dewetted appearance at the land edges. While such defects are cosmetic only and the joints are acceptable (in some studies the pull strength of OSP joints have been found to be higher than ENIG joints); it is desirable to process properly to avoid any questions if possible. There are other issues to consider with OSP. For example, there may be potential incompatibility between no-clean fluxes and terpene-based solvents. There is also the potential of solderability concerns when the assembly is subjected to multiple thermal cycles during reflow, wave, and hand soldering. Bed-of-nail testing may pierce the coating and reduce long term solderability at test point sites. In addition, in-circuit test probing may be negatively impacted because it is difficult to probe bare copper, thus test lands should be pasted to provide a solder bead which will greatly increase contact probability. Handling of the PCBs is also critical as salts from the hands can damage the OSP coating. OSP boards should be handled only by their edges, gloves can be useful as well. It is recommended to cover test lands with solder paste for lower contact resistance. To limit oxidation of the copper and thus maximize process soldering yields, the processing window of all stages e.g., reflow, wave, and hand soldering should be optimized i.e., <24 hours.
The OSP surface has many advantages. Most important of all, it avoids the key problem of the tin/lead HASL by keeping the board surface flat. It is also lead free and will meet with EU legislative requirements. An OSP may also improve gasketing, thereby reducing solder paste printing related defects and thus provides better overall yield.
Historically, the most widely used surface finishes have been HASL and OSP. While no finish is ideal for all applications, the selection of a specific coating should be based on the specific application and familiarity with the technical and business issues related to that technology.
Since the OSP coated surface has another benefit because the terminations maintain their copper appearance (OSP coating is transparent), any solder paste misprint is more easily spotted due to increased color contrast. Alcohol or other solvents, if used for washing off the misprinted paste, will also wash off coatings, and therefore will increase the risk of oxidation of the copper which impacts solderability. However, such boards can be recoated if necessary. Washing and wiping the board is not recommended, but should instead be processed in accordance with IPC-7526 which recommends stencil and misprinted board application data. Process engineers should work with chemical cleaning suppliers to establish the correct cleaning process that will remove the wet paste and minimize removal of the OSP surface.
5.3.3 Noble Platings/Coatings With the EU’s mandated legislation to remove lead from electronic solder, noble metal coatings are seeing increased use as PCB surface finishes even though gold is approaching the historically high levels of the late 1970s. There has also been an increase in more expensive noble metal coatings such as gold and palladium, which are used on occasion. Two other noble metal surface finishes are recently gaining popularity, especially for use on BGA substrates. These are electroless nickel/electroless palladium/immersion gold (ENEPIG) and direct immersion gold (DIG). These are also sometimes called universal surface finishes since they can be soldered to, wire bonded to, and are also suitable as contactable surface finishes. ENEPIG, in particular, is immune to solder joint brittleness problems occasionally seen with ENIG when used with SAC lead-free solder balls for BGAs.
There are some potential process incompatibilities with OSPs. For example, if paste or flux does not cover all land surfaces during soldering, there may be some negative effects such as: insufficient hole filling in wave soldering and/or dewetted appearance after reflow soldering (on the
5.3.3.1 Electroless Nickel/Immersion Gold (ENIG) Both electroless nickel/immersion gold (ENIG) and electrolytic nickel/electroplated gold finishes provide very good shelf life, a flat soldering surface for SMT, and a good electrical
37
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probe surface for in-circuit-test (ICT). Both finishes provide solderable surfaces which can survive through multiple reflow operations and they are less prone to handling related problems. The presence of nickel plating strengthens the through-hole barrels during multiple reflow cycles and rework of through-hole components. Noble plating finishes typically cost more than OSP finishes, and are either comparable or more expensive than HASL, depending on the complexity of the PCB. If it is desired to mix multiple board finishes on a single board, for example Ni/Au in some areas and OSP in others, this can be difficult and expensive to achieve in manufacturing. Application of electroless nickel/immersion gold can be performed using a variety of chemistries, which may lead to different finished results depending on the chemistry used. Also, the chemistry and process may be incompatible with some solder masks.
Crack Interface
Solder Ni-Sn IMC Ni-P Ni
Cu
(a) Crack Interface
Solder Ni-Sn IMC Ni-P
The reducing agents used in the electroless nickel process contain either phosphorous or boron. In the reduction of the nickel in the electroless nickel deposition, either phosphorous or boron is incorporated into the nickel deposit. The level of these co-deposited elements should be controlled within the specified process limit. Variation of phosphorous or boron level, outside the specified process limits, may have adverse effects on the solderability of the finish and possibly the reliability of the solder joints. Many companies have used electroless nickel/immersion gold as a surface finish successfully. However, when BGAs are used with the electroless nickel/immersion gold finish the results, at times, can be unpredictable. Two failure modes have occurred in recent years. The first failure mode is a nonwetting or dewetting condition referred to as ‘‘black pad.’’ Figure 5-4 shows the location of crack constituting a black pad related failure. The failure is between nickel and Ni-Sn intermetallic (not between the ball and Ni-Sn intermetallic).
Crack Cu
Ni-Sn IMC
BGA Solder Ball
Ni IPC-7095b-5-4
Figure 5-4 Black pad related fracture showing crack between Nickel & Ni-Sn intermetallic layer
The second failure mode is an interfacial fracture that is associated with mechanical stress and the failure will occur between the BGA ball and Ni-Sn intermetallic. Figure 5-5 shows an illustration to highlight the differences between the two failure modes and the location of their occurrence. 38
Ni
Cu
(b)
IPC-7095b-5-5
Figure 5-5 Crack location for a) black pad related failure and (b) interfacial fracture when using ENIG surface finish
Results from industry consortia and studies by individual companies suggest that ‘‘black pad’’ is caused by an aggressive attack (hyperactive corrosion) of the electroless Ni plating during the immersion Au plating process. The gold ions from the plating solution attract electrons from the metallic nickel surface as they plate out as the gold metal; in return a nickel ion is released to the bath. Due to certain microstructure features, such as grain boundaries and the electrochemistry involved, the exchange does not always occur locally, i.e., the gold can be deposited to one feature or area and the nickel ion released from a different feature or area. The possible consequence of this process is that selected nickel features become attacked leaving behind a rough and phosphorous rich layer that forms a weak bond with solder. The affected solder joints do not form a robust mechanical bond with the PWB and, as a result, the solder joints fail with a relatively small applied force; revealing lands with little or no solder left on them. The exposed nickel surface on the land is smooth with an appearance varying from grey to black in color, which is where the term ‘‘black pad’’ comes from (see Figures 5-6 and 5-7). SEM analysis shows a distinctive nickel nodular structure similar to ‘‘mud cracks.’’ EDX indicates high amounts of phosphorous and nickel and low amounts of tin. Corrosion marks and a phosphorous rich layer are observed from a polished cross-section.
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Occurrence of the ‘‘black pad’’ condition does not appear to be sufficiently common to advise against use of electroless nickel/immersion gold as a surface finish. Assemblers using PWBs with this finish should be aware of the potential problem, learn to recognize it, and take corrective action. Recent analysis indicates that the interfacial fracture of the solder joint happens between the nickel-tin intermetallic layer and the BGA ball or under a high level of both applied strain and strain rate even if hyperactive corrosion does not take place. Failures have occurred under a variety of laboratory testing conditions including bending, mechanical shock, and thermal cycling. Data indicates that increasing the strain rate shifts the failure mode to an interfacial fracture of the solder joint. Therefore interfacial failure may occur under a reduced strain if the strain rate is high enough. Currently there is no industry specification that quantitatively assesses the mechanical strength of assembled BGA components on any surface finish. Another version of a nickel/gold combination is the electrolytic nickel/electroplated gold surface finish. This plating is similar, however it results in a different grain structure from electroless nickel/immersion gold, and does not exhibit the ’black pad’ joint cracking phenomenon. 5.3.3.2 Electrolytic Nickel/Electroplated Gold
Figure 5-6 Surface
Typical mud crack appearance of black pad
Electrolytic nickel/electroplated gold is applied after pattern plating and most often before solder mask, and therefore carries some risk of surface contamination. Solder mask applied over electrolytic nickel/electroplated gold exhibits lower solder mask adhesion than other surface finishes. This can create problems during assembly of BGAs, and especially during rework. If the solder mask dams covering the traces between BGA lands and vias peel off, solder will flow from the BGA lands into the vias and cause insufficient or open solder joints. Another concern is that it can be difficult to control the gold thickness across the board. The gold may be too thin (for example in areas with dense circuitry) or the gold may be too thick (for example in isolated circuits). This latter situation may lead to gold embrittlement due to excessive gold (>3%) in the solder joints. 5.3.3.3 Electroless Nickel/Electroless Palladium/ Immersion Gold (ENEPIG) In order to address some of
Figure 5-7 A large region of severe black pad with corrosion spikes protruding into nickel rich layer through phosphorus rich layer underneath immersion gold surface
the problems with the electroless nickel/electroless palladium/immersion gold (ENIG) process, another combination of electroless and immersion plating processes have been developed. The switch to lead-free solder has raised many issues on the manufacture, processing, and reliability of lead-free electronic products. Some of the evaluations included a Ni-7%P/Pd/Au (ENEPIG) (5 µm/0.06 µm/0.03 µm) process as illustrated in Figure 5-8. These studies evaluated solder joints formed on the surface finish ENEPIG with SAC 305 LF alloy. The results showed 39
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• The IMC layer of Cu3Sn thickness continues to grow as the heating time increases. • As with tin/lead solder, Cu3Sn is clearly apparent when Sn/Ag/Cu solder is used. DIG is a finishing process that can directly deposit gold onto the copper surface by utilizing an electroless plating process. A graphic representation is shown in Figure 5-9. It is possible to directly deposit gold on the copper surface with excellent coverage, and it should be noted that the main gold depositing reaction is an auto-catalytic and not a displacement one. Copper Surface Cleaned and Microetched Electroless Ni 5 µm (200 microinches) Electroless Pd 0.06 µm (2.4 microinches) Immersion Au 0.03 µm (1.2 microinches) IPC-7095b-5-8
Copper Surface Cleaned and Microetched
Figure 5-8 Graphic depiction of electroless nickel, electroless palladium/immersion gold
a very high degree of reliability under the conditions of testing. It was also noted that the same finish ENEPIG does not produce the most reliable solder joint with tin/lead eutectic solders. Pd cannot form an alloy with lead. The nonalloyed lead disrupts the IMC formation. As Pd is introduced into the Ni3Sn4 layer, it aggregates into distinctive clusters (away from lead) creating a nonuniform IMC layer. The excessive growth and lack of uniformity of the IMC leads to poor reliability when ENEPIG is used with eutectic solder. 5.3.3.4 Direct Immersion Gold (DIG) Direct immersion gold (DIG), is introduced as a viable surface finish that is able to deposit a fine and uniform gold layer directly on the copper surfaces. By examining the deposition reaction of the flash gold plating bath, it can be confirmed that copper does not co-deposit with gold and also that the main driving force for deposition is an auto-catalytic reaction. The copper surface roughness affects solder spread-ability, and the solder joint characteristics are excellent when the film thickness is within the range of 30 to 80 nm. In addition, good wire bonding characteristics can also be derived from deposits plated by a neutral pH, auto-catalytic type heavy electroless gold plating bath, atop the flash gold.
Lead-free solder results are usually inferior (spread less) as compared to tin/lead eutectic solder with a DIG finish. It is necessary to understand this characteristic when lead-free solder is utilized, in that the IMC layer changes at 150°C degrees with time and shows: • A small difference between Sn/Ag/Cu solder and tin/lead solder IMC layer thickness at 0 hours. • After 100 hours of exposure the IMC thickness is usually equal. 40
Immersion Gold 0.06 µm (2 microinches) IPC-7095b-5-9
Figure 5-9
Graphic depiction of directed immersion gold
5.3.3.5 Immersion Silver The industry continues to search for alternative surface finishes that can overcome the disadvantages associated with the HASL, OSP, and ENIG finishes. Some of the most promising alternative surface finishes are immersion silver and immersion tin. Immersion tin has a relatively long history but its use has been limited due to earlier concerns about intermetallic formation and reduced solderability. These concerns seem to be getting addressed in more recent processes.
Both immersion silver and immersion tin are deposited on the board surface using the immersion method of metal deposition. Immersion Silver is a metallic solderability preservative. It can be permanent, becoming an integral part of the assembled board, or sacrificial, preventing copper oxidation and preserving solderability through the assembly process. Immersion silver is also a good surface for contact probe testing. 5.3.3.6 Immersion Tin Immersion tin is a metallic solderability preservative that is sacrificial, preventing copper oxidation and preserving solderability through the assembly process. Due to the higher contact resistance of tin it is not as good as immersion silver for contact probe testing. 5.4 Solder Mask The solder mask is a polymer coating which serves to mask all surfaces which are not to be soldered. Unlike the laminate, which is a composite, solder mask is commonly a homogeneous material. Again, as the name suggests, this solder mask is used to mask off the outer areas of the board where solder is not required to
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prevent bridging between conductors. Because of process changes for lead-free soldering, evaluating solder mask performance takes on a whole new meaning. In the past not all boards required a solder mask because the conductors and lands were spaced quite far apart. The solder bridges between adjacent conductors during wave soldering were not critical. But with the advent of fine lines and spaces, the use of a solder mask has become almost mandatory for boards that are going to be wave soldered. On a full SMT board where no wave soldering is required, tenting or plugging of via holes is done to assist drawing a vacuum on some ICT testers. Also, the application of solder mask to block or plug a via allows closer spacing between a via and the adjacent conductor lines. 5.4.1 Wet and Dry Film Solder Masks Permanent solder masks come in dry film and wet film. Dry film masks can have an aqueous or a solvent base. In both cases, the mask starts out as a polymer film, which is applied to the board by vacuum lamination. Wet film solder masks, as the name implies, are liquid or paste-like. They include photoimageable and wet screenable solder masks. The latter are differentiated by the method of cure. Some wet screenable solder masks can be cured by UV light and some can be cured thermally in convection or IR ovens. UV masks do not provide as good adhesion as thermal masks but require only seconds to cure as opposed to 30-60 minutes for thermal cure.
Each of the liquid solder masks has advantages and disadvantages. They are inexpensive and highly durable. Being liquid, they flow between conductors and prevent the formation of air pockets. There is no trim waste, and the thickness of the mask can be controlled for each design. Since the wet film solder masks are screened on (a mechanical process), they are difficult to register and have a tendency to skip over conductors, especially on fine line boards. They also tend to bleed onto the lands and surface mount lands during cure. Wet screenable masks are difficult to use on boards with fine lines and spaces (<200 µm), and they are also vulnerable to voids, bubbles and pin holes. The use of screenable mask has been on decline as photoimageable solder masks have gained in popularity. The wet film solder mask cannot successfully tent via holes. Generally these materials fill one side of the vias partially, which can prevent bridging but is ineffective in sealing holes to prevent vacuum leakage during testing. The degree of fill needs some control in order to develop a plug that prevents chemistry from going through the via. Partially filled vias trap process chemicals and are difficult to clean. Dry film solder masks have some advantages over their wet screen counterparts. The former provide very accurate registration, which is critical in preventing solder bridging or bleeding on fine line boards, as well as sharper resolution. Tenting of via holes is also superior with dry
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film solder masks because they are never in a liquid state and do not drip into the via during vacuum lamination. However some problems may arise when trying to laminate a semisolid dry film over an uneven board surface with conductors and lands. Any warping and twisting of the board will compound the problem, possibly causing air pockets underneath the dry film near conductors. The curing of a dry film solder mask is critical for achieving a reliable coating. Insufficient cure can cause cleaning problems because of diminished resistance to chemical attack by fluxes or cleaning solutions. Overcure results in a brittle mask, which can crack easily under thermal stress. Most dry film solder masks are not resistant to thermal shock. Cracks develop in the cured masks within 100 cycles of thermal shock cycling from -40 to +100°C; this can be a problem especially in solder mask over bare copper (SMOBC) boards because of exposed copper conductors. However, there are some commercially-available solder masks that resist cracking during thermal shock. Dry film masks are more costly than the wet film variety, and the vendor base is limited. Moreover, the application process for dry film solder masks is very difficult to control. Not many film thicknesses are commercially available, and this can limit flexibility and increase cost. Typically, most dry film solder masks are quite thick, 75 µm -100 µm. Trim waste also adds to cost. Nonwetting of surface mount boards containing wave soldered chip components sometimes occurs because of the greatest thickness. In addition, the thicker mask surrounding the small vias may prevent them from filling with solder during wave soldering (crater effect). The thicker masks can cause problems in reflow soldering as well. For example, a dry film mask applied between the lands of passive surface mount devices can cause tombstoning (standing up on edge) during reflow soldering because of the rocking effect of the mask. For this reason dry film solder mask should not be used between the lands of chip resistors and capacitors or in assemblies that have components glued to the bottom side for wave soldering. 5.4.2 Photoimageable Solder Masks Photoimageable solder masks combine the advantages of dry film and wet solder masks. Dry film is also a photoimageable mask. In this section, however, our discussion is focused on wet film photoimageable masks, which provide accurate registration, are easy to apply, encapsulate the circuit lines totally, have excellent durability, and are cheaper than dry film.
Photoimageable masks can be either screened on or applied by a process called curtain-coating, in which the board is passed at high speed through a curtain or waterfall of solder mask. The photoimageable mask may contain solvent along with photopolymer liquid. If the solvent is added in the mask, 41
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the liquid mask is screened on, solvent is dried off in an oven, and then the mask is exposed to UV light by offcontact or on-contact methods. (If no solvents are used, the liquid is 100% reactive to UV light.) The off-contact method requires a collimated light system to minimize diffraction and scatter in liquid. This makes the system very expensive. The on-contact approach needs no collimated UV light source, and the system is relatively cheaper. Photoimageable solder masks can tent only very small via holes. Most photoimageable wet film masks will not reliably tent 0.35 mm via holes because it is difficult to cure polymer in via holes. If tenting is required, dry film is needed because only dry film can tent via holes effectively. Registration between individual boards within a multi board panel becomes critical for any surface mount application. This is especially true when the board is made in a panel array format to assist the assembly process and throughput characteristics. Board manufacturers inherently build printed boards in a manufacturing panel format; assemblers also want to take advantage of the multiple board array format when they complete their assembly. 5.4.3 Registration
The positioning and orientation of individual boards on any panel is usually at the discretion of the board manufacturer. The manufacturer optimizes the use of the material in the panel and the tolerance conditions that can be achieved with the material used to build a particular board. It is a well known fact that organic materials are prone to movement (i.e., growth and/or shrinkage) thus the board manufacturer, based on their knowledge of materials and their predicted dimensional change movement, will commonly adjust the photo tool to compensate for material stretch or shrinkage depending on the circuit, the board size and the particular properties of the selected material. It is important to understand that assembly companies frequently build their stencils based on a process of ‘‘step and repeat’’ where elements of an individual board are repeated to match the arrangement of the boards on the subpanel. It is vital that the exact layout used by the board manufacturer is understood to accurately provide the relationships of a land pattern for a BGA on one board with all other land patterns of sister boards in the same panel. Inconsistent arrangement of the assembly array can result in misprints when stenciling solder paste onto the panel for surface mount assembly. It is sometimes a common practice to rotate some boards on a panel in order to maximize use of the material. This practice requires caution because some ‘‘work-and-turn’’ layouts may effectively create panels with different shrinkage factors than others. Figure 5-10 shows an example where two array panels were laid out on the manufacturing panel in a horizontal position, and one laid out in a vertical position to accommodate material usage. The shrink factor 42
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on the horizontal version of the material based on the glass cloth reinforcement would be relatively different than that of the array panel position in a vertical plane. Manufacturers are advised to communicate effectively the complex issues related to using the work-and-turn process before proceeding into the manufacturing steps. 5.4.4 Via Protection 5.4.4.1 Encroached Vias The encroached via concept is one that permits solder mask being on the land without filling the via plated-through hole. Encroachment vias take the primary solder mask opening and adjust it so that it is slightly larger than the via hole size.
This concept will permit any outgassing or cleaning of the via plated-through hole, provide more surface coverage and increase adhesion between the solder mask and copper of the annular ring. It will also provide a larger web between the land and the via, and thus should minimize solder mask removal during BGA removal for rework. 5.4.4.2 Via Filling Via filling, capping, flooding tenting and plugging (conductive or nonconductive) are some of the process names applied to those techniques used to cover or fill via holes with solder mask. These processes serve different purposes. Via filling is normally performed on boards that use both reflow soldering and wave soldering. Via filling is also recommended under certain specified conditions, such as for boards where exposed vias under BGAs are exposed to a wave solder. The concern is based on the fact that, when a board with BGAs on the first side is processed through wave soldering, a large amount of heat can transfer from the vias. This can be very significant because BGAs can have very high via densities beneath them. The BGA’s joints can potentially reflow again in the wave and a second reflow without flux could result in cold solder joints or open joint conditions.
Via plugging may also be useful on wave solder boards that are directly connected to BGA lands or directly connected by trace to BGA lands. Vias may be located outside the BGA perimeter or under the BGA, thus for BGAs it is recommended to cap or tent all vias that are less than 1.0 mm from the BGA lands (see Figure 5-11). Via capping is the preferred method since tenting reliability is dependent on the finished hole size. The following definitions apply to the various via filling operations. There are four basic concepts which include: • Tented Via – A via covered with dry film solder mask; the via has no fill. When tenting from both sides there may be issues with air entrapment and expansion during mass soldering. When tenting on one side there may be issues with chemical entrapment during the assembly process, especially when using aggressive flux.
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IPC-7095b-5-10
Figure 5-10
Work and turn panel layout
• Flooded Via – A via that is flooded with LPI solder mask; the via is partially filled or the walls are coated with solder mask. This process could possibly be improved by using a vacuum assist table. • Capped Via – A secondary operation that applies solder mask on one or both sides of the via; the via is partially filled, usually with a space between the two caps. When capping from both sides there may be issues with air entrapment and expansion during mass soldering. • Plugged Via – An additional operation which is done prior to solder mask application; the via is filled with a conductive or nonconductive material. Via plugging is frequently used in conjunction with BGA vias to prevent solder flow to the BGA solder joints when wave soldering is used. Table 5-3 shows the relationship between via filling and the surface finish conditions.
1.0 mm IPC-7095b-5-11
Figure 5-11
Distance from tented land clearance
As a general rule, via flooding and capping processing should be performed after a surface finish has been applied. For OSP and ImAg (immersion silver) finishes, via capping must be done after the surface finish is applied because the harsh chemicals that are used to clean the copper surface can become trapped around the via cap. These trapped 43
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Via filling/encroachment to surface finish process evaluation
Surface Finish
Tenting
Flooding
HASL
Okay
Okay
Okay
Okay
Okay
OSP
Okay
Not Recommended
Okay
Okay
Okay
ENIG
Okay
Okay
Okay
Okay
Okay
ImAg
Okay
Not Recommended
Okay
Okay
Okay
ImSn
Okay
Not Recommended
Okay
Okay
Okay
chemicals can damage the via wall resulting in open vias. Applying the via caps after the surface finish has been applied can degrade some surface finishes (e.g., OSP, ImAg, ImSn) due to the thermal exposure that is necessary to cure the via cap material. There are presently eight different methods of via plugging/ capping identified in IPC standardization. These are shown in Figure 5-12. It is important to realize that the choice of tented, plugged and filled vias for via protection can have direct impacts on the subsequent assembly processes. Besides identifying the eight identified methods, Table 5-4 also provides the pros and cons of the commonly available options offered by board fabricators. The preference of the plugging method among the options presented will depend on the capabilities of both the fabricators and the assemblers. To avoid complication during assembly, it is imperative that all involved in the manufacturing process understand the trade-offs among the options. For printed boards with HASL finish, the solder coating will effectively prevent most surface degradation due to chemical exposure. HASL finishes also increase overall wall thickness of the via barrel. Note, however, that for vias that are solder coated before plugging, the solder coating will melt during second side reflow. As a result, the plugging material can become loose. In some cases, when there is excessive solder coating thickness or solder entrapped within via during fabrication, solder can potentially outgass and spatter or drain to the remaining openings (see Figure 5-13). This is especially problematic when plugging is applied only to the bottom side of the BGA. 5.5 Thermal Spreader Structure Incorporation (e.g., Metal Core Boards) When structural, thermal, or electri-
cal requirements dictate, a conductive constraining core or metal core can be added to the organic substrate to make the new structure. It is recommended that the board circuit layer configuration be made symmetrical about the center of the core. It is possible to create structures that are asymmetrical (i.e., having a different number of layers to either side of the core), however plated-through holes going through the entire stack may be less reliable due to the differences in expansion on either side of the metal or constraining core (see Figure 5-14). There are also, however, some advantages in an asymmetrical design in that the electrical properties and function are 44
Capping
Plugging
Encroaching
separated from the mechanical, or heat dissipation, function. However among the drawbacks are the fact that, due to the differences in coefficient of thermal expansion of the board and the core material, the completed board may distort during assembly soldering/reflow operations, or while in system use due to operating temperature changes. Some compensation can be achieved by having additional copper planes added to the back of the interconnection product. The extra copper plane may increase the expansion coefficient slightly and make soldering more difficult due to the need to put more energy into the board to assure proper solder joint formation; however, a positive effect is that it enhances thermal conductivity. 5.5.1 Lamination Sequences As previously noted, more desirable constructions are those where circuit layers are symmetrical about the core chosen to serve at the center of the board. By so doing, individual multilayer circuits can be produced separately, each with their own laminating sequence. For example, a four layer board might be manufactured having vias through the entire four layers and this can be duplicated for use on either side of the core.
To achieve mechanical constraint within a chosen and useful range, the total thickness of the core in the multilayer should be approximately 25% of the board’s total thickness. Constraining core board is more often used because the core layers may be imaged, etched, and connected to the plated-through hole. The thicker center core must be machined. Better thermal cycle survival has been shown in some studies for structure having two constraining cores in the board rather than one. Another configuration is to have a special constraining core board made by bonding a multilayer board to each side of a thick metal core after each of the boards has been completed. The composite board is then sequentially drilled, plated, and etched to form plated-through hole connections between the two boards. Coupons should be provided to test the integrity of the composite structure. 5.5.2 Heat Transfer Pathway Metal core boards add significantly to the thermal mass of the assembly. This may force the preheating soldering process to be operated at abnormally high limits. These designs should be thoroughly evaluated under production conditions prior to release. Laminate ruptures and discoloration and grainier textured solder are typical effects that have been observed.
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Via, Tented (Type 1 Via) A via with a mask material (typically dry film) applied bridging over the via wherein no additional materials are in the hole. It may be applied to one side or both.
Via, Tented and Covered (Type II Via) A Type I via with a secondary covering of mask material applied over the tented via.
Via, Plugged (Type III Via) A via with material applied allowing partial penetration into the via. It may be applied from either one side or both sides. Via, Plugged and Covered (Type IV Via) A Type III via with a secondary covering of material applied over the via. The secondary covering may be applied from either one side or both sides.
Via, Filled (Type V Via) A via with material applied into the via targeting a full penetration and encapsulation of the hole.
Via, Filled and Covered (Type VI Via) A Type V via with a secondary covering of material (liquid or dry film solder mask) applied over the via. It may be applied from either one side or both sides.
Via, Filled and Capped (Type VII Via) A Type V via with a secondary metallized coating covering the via. The metallization is on both sides.
Figure 5-12
Via plug methods
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March 2008 Table 5-4
Via fill options
Top
Bottom
Top & bottom
No plug
Pros Increase rework robustness
Yes
Yes
Yes
No
Reduce secondary reflow risk at wave
Yes
Yes
Yes
No
Prevent solder drain
Yes
Yes
Yes
No
Cons Secondary Fab process
Yes
Yes
Yes
No
Component side height profile restriction
less than 50 µm above solder mask
No
less than 50 µm above solder mask
No
Contaminant concern
Yes – (if exposed to wave solder directly, there is a potential of flux entrapment)
No
Yes – (Contaminants entrapped within the via can be difficult to detect)
No
Plug integrity concern
Yes
Yes
Yes
No
The heat transfer path between components and the planes are usually accomplished through either direct contact with the plane or through thermal vias positioned under the component and connected to the thermal core or plane in its position.
BGA Package
6 PRINTED CIRCUIT ASSEMBLY DESIGN CONSIDERATION
Z
Circuit Board
Solder Filled and Mask Tented Via
Solder Blow-Out on Top Surface Caused by Elevated Heat During Reflow or Wave Solder Processing
6.1 Component Placement and Clearances It is recommended that sufficient clearance (3 to 5 mm) be provided around BGAs to facilitate rework. The high-end clearances are recommended, especially for CBGA when using a step stencil to deposit solder paste and using hot air for rework. However, if using diode laser systems for rework the spacing can be reduced to 0.5 mm to 1.00 mm since laser rework does not impact adjacent components.
IPC-7095b-5-13
Figure 5-13
Solder filled and tented via blow-out
IPC-7095b-5-14
Figure 5-14
Metal core board construction examples
6.1.1 Pick and Place Requirements An advantage of BGA packages over other advanced, high-pin count packages (fine pitch, TAB, PGA, etc.) is the ability to be placed using existing surface mount placement equipment. BGAs are more forgiving in the pick and place process because they self align. 6.1.2 Repair/Rework Requirements Repair/rework of BGA components is a major driver for component spacing requirements. A typical BGA rework method requires five steps: 1) heating the solder joints to reflow temperatures for package removal; 2) removal and clean-up of solder on the BGA land pattern; 3) application of new solder paste or flux; 4) placement of the new BGA package; and 5) heating the solder joints to reflow temperatures for assembly of the BGA component to the circuit board.
A keepout area may be needed for each of these steps. Rework equipment manufacturers can provide specific details regarding necessary keepout areas. General rules are 46
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outlined below. Nearly all hot air methods use a nozzle system that fits down over and/or around the BGA package to heat the solder joints for removal and reflow. A component keepout area of 2.5 mm away from the outer edge of the oven nozzle is suggested. Including the nozzle size results in a 3.8 mm clearance from the component body. This spacing around the BGA provides room for the nozzle and reduces the risk of heating solder joints of adjacent components above the reflow temperature. When using laser for rework, the keepout area can be reduced to under 1 mm. After a BGA package has been removed from the board during repair, the solder lands must be cleaned and new solder paste or flux applied before a new component can be placed. If the solder paste or flux is dispensed using manual methods or, if solder paste is applied using an automated dispensing system, then there are no special component keepout areas required. However, many repair systems use a miniaturized stencil and squeegee to manually apply solder paste. In general, a minimum of 3 mm component keepout (i.e., the nominal distance between the body of the component and the body of the neighboring component) is needed so that both the nozzle clearance requirement and the mini-stencil requirement can be met. The existence of a high profile neighboring component may require the minimum distance to be much larger than the stated minimum value. 6.1.3 Global Placement There are no special global placement requirements for BGA packages. However, it is recommended that they not be placed near the board centerlines. This reduces the potential of coplanarity problems associated with the board warping during reflow. In addition, BGA packages should not be placed next to large through-hole components, as these can stiffen the board and significantly increase localized BGA corner joint stresses. In some cases, one might want to take advantage of certain features that might actually help protect the BGA if the induced strain relative to the BGA corners are reduced by the stiffness caused by nearby through-hole or other components. Finally, BGA packages should not be placed with their diagonals in line with mounting stand-off, bosses, and screws that support or secure the printed board assembly, since this can induce levels of stress on the corner balls, which are more susceptible to damage. 6.1.4 Alignment Legends (Silkscreen, Copper Features, Pin 1 Identifier) Alignment features printed on the circuit
board are recommended for BGA packages to verify component alignment before and after reflow. BGA packages, especially PBGA, will self-align during reflow, even when placed up to 50% off the lands. As a result, any misalignments are generally one land diameter length or more off. Alignment features will help verify that the component placement is sufficiently accurate with visual inspection.
IPC-7095B
Silkscreen and copper are the two main materials used for alignment legends. Silkscreen is the most visible material, but requires the additional process step during board manufacturing. Copper alignment legends are created at the same time all other copper features are created and, therefore, leads to more accurate placement. Higher speed circuitry may be affected by the ungrounded copper in this solution. Unconnected copper conductors can collect a capacitance which will dissipate uncontrollably. In many instances, legend is used by equipment or individuals to evaluate the alignment of the BGA during the placement operation. For peripheral leaded components, the fiducial has been standardized so that placement equipment can adjust the movement of the placement head accordingly and improve the final component positioning. Fiducials are normally put at opposite corners to allow adjustment for the theta angle. This technique has been incorporated into many placement tools and equipments. The use of fiducials may not provide the most obvious condition for human inspection, however most inspectors can approximate that the package is properly centered between two fiducials that are known as local fiducials in order to accommodate their position. In some instances, companies have used angle brackets in place of the fiducials to assist the human eye in making this judgment; however, the camera for placement equipment is not familiar with that configuration, thus the practice is not the most conducive for automatic assembly (see Figure 6-1).
IPC-7095b-6-1
Figure 6-1
BGA alignment marks
Using silkscreen, the entire package can be outlined for easy visual alignment. Another alignment pattern commonly used is to mark just the corners of the BGA package. Corner marks should only be 0.8 mm long on each side. Copper can be used for corner marks, since it won’t interfere with routing runs, as long as it does not affect circuitry performance such as unwanted capacitance. All alignment legends should be offset 0.25 mm away from the outer edge of the BGA package. This gives sufficient clearance to view the features all around the BGA package. Pin 1 identifiers are required on BGA land patterns. This identifier can be a caret, dot, or other easily visible shape. The Pin 1 identifier can be either silkscreen or copper and 47
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P - D ≥ (2n + 1)x
should be distinct enough so as not to be confused with any other markings around the land pattern.
A general rule is to design the solder land on the circuit board with the same diameter as the solder land on the plastic BGA substrate.
6.2 Attachment Sites (Land Patterns and Vias) 6.2.1 Big vs. Small Land and Impact on Routing The diameter of the solder land can affect both the reliability of the solder joints and also the routing of conductors. The land diameter is usually smaller than the ball diameter of the BGA. The land size reduction of 20 to 25% has been determined to provide reliable attachment criteria. The larger the lands the less room for routing between lands. For example, a 1.27 mm pitch BGA package with 0.63 mm diameter solder lands will be able to fit two conductors between the lands using 125/125 µm conductors and spacing. If a 0.8 mm diameter solder land is used, only one conductor can fit between the solder lands using 125/ 125 µm conductors and spaces.
Table 6-3 shows another view that takes the maximum land size possible for a particular number of conductors instead of number of conductors for each land size and has additional pitches. Information is also provided on interstitial via. Solder land sizes for a CBGA should be designed such that the noncollapsing ball or column has sufficient platform availability of the land in order to obtain the solder attachment to the column or ball of the CBGA. This makes the land somewhat larger in order to establish this minimum requirement and is necessary to ensure reliability of solder joint which usually comes from the melted solder paste deposit.
Tables 6-1 and 6-2 show the number of conductors that can be routed between lands for various land diameters and conductor/space widths.
6.2.2 Solder Mask vs. Metal Defined Land Design
There are two basic types of solder lands used for BGA packages. These are metal defined (MD) and solder mask defined (SMD). MD lands are etch-defined and there is solder mask clearance around the lands, similar to most
The following equation can be used to determine the number of conductors that can be routed between lands depending on package pitch (P), solder land diameter (D), number of conductors between lands (n) and conductor/space width (x). Table 6-1
Number of conductors between solder lands for 1.27 mm pitch BGAs
Solder Land Diameter (micron)
Conductor Spacing Width (micron)
750
700
625
500
400
350
200
N/A
N/A
1
1
1
1
150
1
1
1
2
2
2
125
1
1
2
2
2
3
100
2
2
2
3
3
4
75
2
3
3
4
5
5
Table 6-2 Solder Land Diameter
Conductor Spacing Width (micron)
Number of conductors between solder lands for 1.0 mm pitch BGAs 625
500
400
350
300
250
200
200
N/A
N/A
1
1
1
1
1
150
N/A
1
1
1
1
2
2
125
1
1
1
2
2
2
2
100
1
2
2
2
2
3
3
75
2
2
3
3
4
4
4
Table 6-3
Maximum solder land to pitch relationship Maximum Land Size
BGA Pitch
Ball Size
Standard Pad
Via
One Track
Two Track
1.27
0.75
0.50
0.95
0.90
0.65
1.0
0.60
0.45
0.45
0.65
0.40
0.8
0.50
0.40
0.30
0.45
0.7
0.40
0.35
0.20
0.35
Assumption: 125/125 µm conductors and spaces via land for 1.25 mm and 1.0 mm pitch BGA is 0.63 mm via land for 0.8 mm and 0.7 mm pitch BGA is 0.5 mm All values rounded down to 0.5 mm
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surface mount lands. SMD lands have solder mask overlapping the copper land (see Figure 6-2). Both land types have advantages and disadvantages. 6.2.2.1 Metal Defined Lands Metal-defined (MD) lands require a smaller diameter copper land and, therefore, have more metal-to-metal spacing for routing and vias. Copper dimensions can also be controlled better than solder mask dimensions, giving a more uniform surface finish, especially for HASL boards. The absence of solder mask around the solder land allows the solder to flow around the edges of the land, eliminating any areas of stress concentration.
IPC-7095b-6-3
Figure 6-3
Metal defined land attachment profile
Metal defined lands gives the solder joint a much better geometry (see Figure 6-3), potentially giving it longer fatigue life, but lowers the stand-off height. Because of the overlapped solder mask, SMD lands require a larger diameter metal land to achieve the same sized land diameter as MD. The solder joint is defined by the solder mask creating a stress concentration (see Figure 6-4), but will have a higher standoff. The effect is illustrated in Figure 6-5, which shows the contrast in joint geometry resulting from solder mask defined lands (left side) and a metal defined condition (right side). The stress concentration on the solder mask defined land results in possible crack initiation at the mounting surface. The SMD lands adhere to the board more because of the larger surface area of copper and the overlapping solder mask. The major disadvantage to SMD lands is that this approach is less reliable, decreasing the fatigue life by up to 70 percent when compared to nonsolder mask defined (NSMD) lands. An area of high stress is created at the solder mask opening. The major advantage is that this approach may be used to prevent the land from pulling off of the board. Land lifting, also known as cratering, usually occurs at the corner balls. Because corner balls have a higher strain rate and are more 6.2.2.2 Solder Mask Defined (SMD) Lands
Cross Sectional Area of Solder Ball Reduced
Solder Mask Concentrates Stress Thermal Expansion in “Z” Axis is Greater for Solder Mask than the Solder Ball IPC-7095b-6-4
Figure 6-4
Solder mask stress concentration
SMD geometry with stressconcentration
Figure 6-5
MD geometry without stressconcentration
Solder joint geometry contrast
Copper Pad Copper Pad Solder mask away from pad Solder mask on pad
Via covered with solder mask for interconnection
Figure 6-2
IPC-7095b-6-2
Solder lands for BGA components
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likely to fail, many times component manufacturers make these noncritical to function (CTF). In the case of no CTF corner balls, it may be desirable to have SMD lands in these locations. The conductor width can affect the routing of the BGA package. The wider the conductor, the less room between lands for placing runs. There is no maximum conductor width recommendation for SMD solder lands; however, the maximum conductor width connecting NSMD solder lands is 0.2 mm. Anything wider will have the effect of changing the solder land to an SMD type land at the location. For the same reasons, only one run should be joined to any NSMD solder land. To eliminate sharp corners, a fillet should be used where the conductor connects to the solder land. 6.2.3 Conductor Width
6.2.4 Via Size and Location Vias can be placed between BGA solder lands on the land pattern. Via lands should be kept small enough to provide clearance between it and adjoining solder lands. The maximum via size that can be used depends upon the size and type (SMD vs. MD) of solder land used. However, it is recommended that the smallest standard via land/drill size be utilized for the board thickness. Vias with 0.6 mm lands and 0.35 mm drilled holes are common for 1.5 mm and 1.27 mm pitch BGAs, while 0.5 mm lands/0.25 mm drilled holes are used for 1.0 mm and 0.75 mm pitch packages.
To minimize the risk of solder bridging between standard sized vias and solder lands, vias can be either tented or have solder mask encroaching (overlapping) the via land. Covering the via lands will also reduce the risk of narrow solder mask dams peeling off during BGA rework. See Figure 6-6 for examples of covered vias and narrow solder mask dams. Tented vias may not be reliable with some combinations of solder mask and surface finish. The solder mask opening on an encroached via should be just large enough to allow flux and other contaminants to escape during processing. Consult your board fabricator for capabilities when planning to tent or use encroached solder mask on vias. Also see Figure 6-7.
Figure 6-7
Examples of metal-defined land
Other options for vias on BGA land patterns include blind vias and microvias. Blind vias can be created using a standard drill process, laser ablation, or photo defined through
BGA Trace and Solder Mask Design
Solder has has been been Solder sucked into into via via sucked due to to improper improper due trace and and solder solder trace mask design. design. mask Showing Solder Joint Impact Figure 6-6
50
Good/bad solder mask design
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wet or dry (plasma) chemistry. The outer and inner layers are sequentially built and are then laminated together. Because the via penetrates only the outer layers, a smaller sized drill can be utilized. However, this option is generally a large cost addition. Blind vias can be placed between solder lands but, because of their smaller via lands, centering the via between the solder lands is not as critical. Microvias are created in a secondary operation and penetrate the outer layers only. A standard microvia connects layers 1 and 2 and/or n-1 and n. A typical microvia can have a 0.3 mm land with a 0.1 mm hole size. Because of this small size, the via can actually be placed in the center of the solder land with the only noticeable effect being a small dimple. The dimple can be avoided by using a Type VII via protection concept in the design that fills and caps the via. By placing vias directly in the land, the space between BGA solder lands on the outer layers can be used exclusively for routing. One should establish a liaison with a board manufacturer for options and rules before designing BGA land patterns with blind or microvias. Unlike peripherally leaded packages, BGA solder joints are not all easily accessible on the top board layer. This is especially true for BGA packages with large, full grid arrays. Additional layers may be required to route the signals out from underneath the middle of these packages. 6.3 Escape and Conductor Routing Strategies
For example, a 1.27 mm pitch, 357-pin PBGA has a 19x19 full grid array without the corner solder balls. If 0.63 mm solder lands are used, this leaves only 0.63 mm between lands for routing conductors. This would permit only one 0.2 mm conductor between the lands, meaning that only the outer two rows (136 pins total) of the package could be routed out on the top layer. All other pins (221 total) would need to join to vias and then be routed out through other signal layers. If 125 µm conductors/spacing is used, two conductors could be placed between lands so that the outer three rows of pins (192 pins total) could be routed out on the top layer, leaving the remaining pins (165 total) to be routed using vias. The via pattern for the board requires much tighter feature control as the pitch for BGA, FBGA and CSP becomes smaller. Fanout patterns should show a distinctive cross for power. There have been instances that power isolation has occurred when the cross pattern was not used in BGA fanout due to power clearances, creating wall around the internal power pins. The cross pattern also allows for an area for internal or cross BGA nets to route (see Figure 6-8). Successful BGA fanout involves: • Adherence to a placement grid in alignment with the fanout grid whenever possible
Figure 6-8
Quadrant dog bone BGA pattern
• Protecting BGA fanout vias during routing • Proper via and land sizes An alternate method for BGA fanout is to not fanout the perimeter pins in the outer two rows and columns of the BGA. For the outer two rows, allow the router to drop the ‘‘fanout’’ via with a relaxed set of distance rules. The outer two rows of relaxed fanouts create a dip-like pattern around the BGA for the auto-router to complete. The space between this dip pattern and the BGA pattern allow for non-BGA nets to cross the area of the BGA without needing to navigate the internal BGA fanout pattern. This method can be tried when one is having problems routing a board with BGAs. To ease routing, power and ground pins can be placed in the center of the array pattern so that they can be connected directly to vias and not interfere with routing around the outer edges of the package. Ball grid arrays can be square or can be rectangular. In a square array, the number of rows is equal to the number of columns. A 4x4 square array is shown in Figure 6-9. In a rectangular array, the number of rows is not equal to the number of columns. A 4x5 rectangular array is shown in Figure 6-10. The arrays may be completely filled or certain portions of the array may be unfilled. A 4x5 rectangular array is shown in Figure 6-11 which has one central column unused, blank, or depopulated. The 4x4 square array shown in Figure 6-12 has some balls missing, blank or depopulated. It is relatively trivial to fan out the conductors from the outlying balls to the periphery for interconnection to the 51
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IPC-7095b-6-9
Figure 6-9
Square array
IPC-7095b-6-12
Figure 6-12
Square array with missing balls
the conductors. This information will help to model the signal integrity to assure the success of their application. The number of conductors per outlet, C, for a simple r x c array can be determined by substituting r and c in the following relationship with the number of rows and columns of the given array, and by substituting d with the number of depopulated sites in the array. C
IPC-7095b-6-10
Figure 6-10
Rectangular array
[(r−2)(c−2)]−d 2(r+c−2)
In case the above equation provides a whole number for C, every array outlet between adjacent solder balls will need to accommodate C conductors. If C is a fractional number then some outlets will have to accommodate a number of conductors obtained by rounding down the value of C, and others will have to accommodate a number of conductors obtained by rounding up the value of C. The fraction is the proportion of the lower and higher number of conductors per outlet. The balls in an array can also be interspersed, as in a diagonal array. An example of a 5x5 interspersed array is shown in Figure 6-13. The following relationship can be used to determine the number of conductors per outlet for an interspersed array.
IPC-7095b-6-11
Figure 6-11
Depopulated array
outside world. But the solder balls inside the array have to be routed in between the outlying solder balls. As the size of the array increases, more and more traces from the solder balls inside the array have to be routed in between the solder balls to connect to the outside world. It is important for the substrate designers to know how many conductors they may expect to accommodate in the spacing between the adjacent solder balls so that they may determine the widths of the conductors and the spacing between 52
C =
[(r−2)(c−2)+(r−1)(c−1)]−d 2(r+c−2)
If C turns out to be a fraction, then rounding it down will give the lower number of conductors to be accommodated between some adjacent balls, and rounding it up will provide the number of maximum conductors needed to be accommodated between other adjacent balls. The fraction gives the proportion of the two numbers. The sizes of the solder land and via land also affect the routing ability of BGA packages. A 0.8 mm solder land on a 1.27 mm pitch leaves only 0.5 mm between solder lands for routing. In order to get two conductors between the
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IPC-7095B
interlevel vias or PTHs. It may be necessary to have one or more interconnecting lines between two adjacent bonding lands on the topside of the BGA substrate. This is done in order to access multiple rows of the interior I/O lands for connection to the vias or PTHs for eventual connection to the solder balls on the bottom side. Very aggressive layout rules must be used, even when designing with surface redistribution layers (see Figure 6-14).
IPC-7095b-6-13
Figure 6-13
Interspersed array
solder lands, 100/100 µm conductors/spacing would need to be used. However, if a 0.6 mm solder land is used, two conductors can be routed between lands using 125/125 µm conductors/spacing. Because of the small space between solder lands on finer pitch BGA (1.00 mm and less), smaller via lands and drill sizes are required. As the drill sizes get smaller, the maximum allowable board thickness also decreases. This may force board designers to use fewer layers or to decrease the dielectric thickness between layers. If microvias are used, this may force the outer two layers of the PCB to be signal layers. 6.3.1 Escape Strategies
Table 6-4 shows some escape
strategies for full arrays. To accommodate a flip chip with area array I/O lands at 0.25 mm pitch, the BGA package substrate will need bonding lands at 0.25 mm pitch on the top side, and solder balls at 1.27 or 1.00 mm pitch on the bottom side. These opposing sets of lands must be connected by the BGA package substrate (high-density microcircuit board) wiring and Table 6-4
IPC-7095b-6-14
Figure 6-14
Conductor routing strategy
Escape strategies for full arrays Full array parts
Nominal ball diameter (mm)
Surface traces
Dog bone through vias
Dog bone microvias
Microvia in pad
1.27
0.75
Y
Y
Y
Y
1.0
0.45 - 0.6
Y
Y
Y
Y
Pitch (mm)
0.8
0.3 - 0.5
Y
Y
Y
Y
0.75
0.3 - 0.45
N
H, S
Y
Y
0.65
0.3 - 0.4
N
N
Y
Y
0.5
0.3
N
N
N
Y
Notes: See Table 6-5 to 6-7 for details on routing channel widths See Tables 6-8 to 6-10 via drill and land size assumptions used Y = yes, with ‘standard’ board fabrication capability and standard land size
H = high capability board fabrication required S = shrink land size required N = not practical with industry standard design & process
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For high performance chips with 1700 pin requirements, a BGA with very dense wiring layers is required. The body size of such a BGA would be 50 mm. In all probability, there would be depopulated solder balls in the middle of the BGA. Regarding pitch, such a BGA substrate would require a 1.00 mm via and solder ball pitch, which would accommodate a ball density of 100 I/O per square centimeter.
Table 6-9
Conductor routing - 1.0 mm pitch
Nominal Ball Diameter (mm)
0.6
0.5
0.45
Typical Solder Land Diameter (mm)
Drill Diameter
Tables 6-5 through 6-7 shows various conductor routing characteristics for different BGA pitches. 6.3.2 Surface Conductor Details
Table 6-5
Nominal Ball Diameter (mm)
0.75
Typical Solder Land Diameter (mm)
Conductor Spacing Width (µm)
Table 6-6
0.55
150
2
125
2
100
3
75
4
0.5
0.45
Typical Solder Land Diameter (mm)
0.45
0.40
0.35
150
1
1
1
125
1
1
2
100
2
2
2
75
3
3
3
Conductor Spacing Width (µm)
Nominal Ball Diameter (mm)
0.45
0.4
0.3
Typical Solder Land Diameter (mm)
0.35
0.3
0.25
150
1
1
1
125
1
1
1
100
1
2
2
75
1
2
3
Tables 6-8 through 6-10 provide the details for conductor routing using the dogbone via concept. The tables also are organized per via pitch. 6.3.3 Dog Bone Through Via Details
Table 6-8
Conductor routing - 1.27 mm pitch
Nominal Ball Diameter (mm)
0.75
Typical Solder Land Diameter (mm)
0.55
Drill Diameter
0.35 mm [0.0135 in]
Y
0.3 mm [0.012 in]
Y
Y
0.3 mm [0.012 in]
N
Y
Y
0.25 mm [0.010 in]
Y
Y
Y
0.2 mm [0.008 in]
Y
Y
Y
Nominal Ball Diameter (mm)
0.45
0.4
0.3
0.35
0.3
0.25
0.35 mm [0.0135 in]
N
N
N
0.3 mm [0.012 in]
N
N
N
0.25 mm [0.010 in]
N
Y
Y
0.2 mm [0.008 in]
Y
Y
Y
6.3.4 Design for Mechanical Strain Mechanical strain and board flexure are major causes of PCB and BGA joint damage. Several BGA layout strategies have been developed that can help reduce the impact of mechanical strain on the BGA. PCB:
Conductor routing - 0.8 mm pitch
Conductor Spacing Width (µm)
0.35
N
Typical Solder Land Diameter (mm)
Conductor routing - 1.0 mm pitch 0.6
0.40
N
Conductor routing - 0.8 mm pitch
Drill Diameter
Nominal Ball Diameter (mm)
Table 6-7
Table 6-10
Conductor routing - 1.27 mm pitch
0.45
0.35 mm [0.0135 in]
• Divide each BGA into four equal quadrants with lines parallel to the sides. From each quadrant route conductors and dogbones to escape vias from the BGA lands so that they go out radially from the BGA at 45 degree angles (see Figure 6-15). This increases the amount of strain that corner lands can withstand before damage. • Enlarge or teardrop the dogbones or routes to BGA corner lands. PCA and Enclosures:
• Do not place screws near BGA corners in line with the package diagonals (see Figure 6-16, red locations). • Preferably place screws and bosses on the normal to the midpoint of the BGA sides (see Figure 6-16, green locations). • Use header connectors with a stiff body and provide PCA support at both ends, especially for connectors with high insertion and release forces (see Figure 6-17). • Use washers under screw heads not larger than the boss Outer Diameter to minimize torsional deformation of the PCB.
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IPC-7095B
CONNECTOR SCREW SUPPORT
D Di o g b re o n cti e on
D D og ire b ct on io e n
PROVIDE END CONNECTOR SUPPORT ON PCB
BGA
IPC-7095b-6-17
Figure 6-17
D D og ire b ct o n io e n
D D og ire b ct on io e n
Connector screw support placement
size with respect to joint reliability. An illustration of the problem is shown in Figures 6-18 and 6-19.
IPC-7095b-6-15
Figure 6-15 BGA dogbone land pattern preferred direction for conductor routing
SCREW AND SUPPORT PLACEMENT
Figure 6-18 Cross section of 0.75 mm ball with via-inpad structure (Indent to the upper left of the ball is an artifact.)
BGA
AVOID PREFERRED CORNER PLACEMENT PLACEMENT IPC-7095b-6-16
Figure 6-16
Preferred screw and support placement
6.3.5 Uncapped Via-in-Pad and Impact on Reliability Issues Via-in-pad (through-hole via, capped on bottom of
the board) for BGA lands can cause voids in the BGA solder joints, which may impact reliability. Current data indicate that, for the standard 25-35 mm package with 0.75 mm balls, there is no reliability risk from voids. Accelerated aging tests have been performed and the failure rate was statistically equivalent to standard dogbone designs. It appears that void consistency is more important than void
IPC-7095b-6-19
Figure 6-19 Cross section of via-in-pad design showing via cap and solder ball
Vias capped on one side can pose a variety of reliability issues. Each issue should be evaluated for relevancy to the specific environmental design criteria: • the hole may be partially filled creating uneven stresses • the void may utilize a sizable part of the connection area reducing the structural support • the void may reduce the thermal path When using via-in-pad technology, a void will occur in the joint as shown in Figure 6-19, unless the via is capped on 55
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the component placement side of the board. Most experts agree that these void conditions, created due to entrapped air, are acceptable and have no impact on the reliability of the joint. There is no doubt that the conditions depend not only on the process, but the size of the BGA land and the diameter of the hole. In addition, there is a difference as to whether the hole is a through-hole, blind via, or microvia. Figure 6-20 shows the characteristics of the three hole configurations and what takes place at incoming after the solder paste has been printed and the BGA has been placed; the conditions of the ball and hole during reflow soldering; and, finally, the characteristics of the resulting solder joint. One of the major reasons for the occurrence of the void conditions is the entrapped gas that exists under the solder paste during the original paste printing and BGA placement. During the reflow operation, the entrapped gas and the solder paste volatiles need to escape, and this creates the minor occurrences of absence of solder at the center part of the ball as shown in the illustration. 6.3.6 Fine Pitch BGA Microvia in Pad Strategies When the pitch is less than 0.8 mm there is not enough room to place a via using current mechanical drill technology for full array BGA components. For finer pitch BGAs or, in order to achieve increased routing area, putting a microvia-
in-pad may be necessary. These are blind vias that connect to the first or second internal layer of the printed board. They are typically laser drilled but in some cases a mechanical drilling process is used (see Figure 6-21).
PCB pad Cu layer
Cross-section IPC-7095b-6-21
Figure 6-21
Microvia example
Unless the via is filled or plated shut then air is likely to remain under the solder paste forming a void in the solder ball when reflowed. For MD lands with microvias crack, propagation will start from the void associated with the via and move towards the outside of the ball (see Figure 6-22). These voids have been shown to decrease the amount of stress that the solder joint can withstand when compared to a comparable MD land without via in pad. For this reason
BGA
Incoming - Before Assembly Process
After Solder Paste Printing & BGA Placement
During Reflow Soldering
Post Reflow Soldering
Figure 6-20
56
Via-in-pad process descriptions
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IPC-7095B
then wave soldering the through-hole packages (inserted from the top side) as well as the surface mount components on the bottom side. During the wave soldering process step, however, the reflow soldered surface mount components on the top side of the board are also heated. This heating can cause the solder joints of these components to melt if the temperature increases close to the liquidus point of the solder alloy. Hence, care needs to be taken to avoid the solder joints of these components from reaching the liquidus temperature.
Figure 6-22
Microvia in pad voiding
it is not recommended to use via in pad for high stress solder balls such as the corner balls or those directly under the edges the die. 6.3.7 Power and Ground Connectivity When lands are required within a ground or power plane, it is a common practice to leave an opening in the solder mask covering the plane to provide access to the land. When increased fatigue life is needed for these locations or for thermal isolation, an MD land can be created within the plane etching crescent-shaped relief pattern around the land (see Figure 6-23). The segment tie bar, no matter whether 2,3, or 4 spokes, should point towards the corner of the BGA to provide maximum fatigue strength.
MD Segment
Figure 6-23
Figure 6-24 depicts examples of ball deformation and de-wetting for a BGA component located on the top side of a motherboard. The solder joints of the BGA reached a peak temperature of 180°C during wave solder. BGAs are more prone to such defects than leaded surface mount solder joints since there is less strain relief.
SMD Segment
Solder Mask
Crescent Opening Etched Into Plane
6.4.2 Impact of Top Side Reflow BGA solder joints need particular attention in this regard since the solder joints are under stress during the wave soldering operation. If these solder joints reach the solidus temperature (183°C for the eutectic tin/lead solder composition; 217°C for SAC alloy) then there is a potential to de-wet or be pulled away from the board or the package substrate due to the thermomechanical strains induced in them at the elevated temperatures. Since solder is extremely soft even at temperatures approaching the solidus temperature, the potential for cold solder, de-wetting or ball deformation exists when their temperatures do not reach solidus.
Copper Plane IPC-7095b-6-23
Ground or power BGA connection
6.4 Impact of Wave Solder on Top Side BGAs 6.4.1 Top Side Reflow Mixed Technology printed circuit boards are typically assembled by first reflow soldering the surface mount packages on the top side of the board and
Figure 6-24
Example of top side reflow joints
To avoid problems in BGA solder joints on the top side of the board, their temperatures should not exceed 150°C during tin/lead wave soldering and 190°C for lead-free alloy wave soldering. This is less than the maximum temperature allowed for the fine pitch leaded components such as plastic QFPs. Figure 6-25 is an example of an acceptable temperature profile for the solder joints on a mixed technology board during the wave solder process. To determine the various ways of keeping the temperature below 150°C (or 190°C for lead free), it is best to first 57
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Zone # 1
Zone # 2
Zone # 3
Chip
Contour
183°C 160°C
Maximum peak temperature for Fine Pitch is 160°C
150°C
100°C
Maximum peak temperature for BGA is 150°C
80°C 60°C 40°C
IPC-7095b-6-25
Figure 6-25
Example of wave solder temperature profile of top-aide of mixed component assembly
identify the various ways in which the BGA solder joints are heated during the wave solder process. Figure 6-26 illustrated three pathways. Pathway A is by conduction through the thickness of the board from bottom to top. Pathway B is by conduction through the barrel of the via, along a trace connecting the via to the BGA solder joint land. Pathway C is by convection and radiation from the Preheaters on the top in the wave solder machine.
6.4.3 Methods of Avoiding Top Side Reflow The methods of avoiding top side reflow aim to reduce the heat transfer to the BGA solder joints by one or more of the three pathways described above. Figure 6-27 illustrates these methods. A heat shield can be placed over the BGA packages to avoid direct heating from the preheaters in the wave solder machine. These shields can be mechanically attached to the wave solder pallets.
Heat Pathways to the BGA Solder Joint During Wave Soldering Heat Source
C
BGA B Printed Circuit Board
A
Wave IPC-7095b-6-26
Figure 6-26
58
Heat pathways to BGA solder joint during wave soldering
March 2008
IPC-7095B
Methods of Avoiding Topside BGA Solder Joint Reflow During Wave Soldering Heat Source
Heat Shield (Attached to Pallet)
BGA Printed Circuit Board
Nonmetallic Wave Shield (Attached to Pallet)
Via Capping
Wave IPC-7095ba-6-27
Figure 6-27
Methods of avoiding BGA topside solder joint reflow
Secondly, vias can be capped by solder mask on the bottom side of the board. This via-capping process is very commonly employed in the industry, for a variety of reasons. Via capping rules should be built into the design for manufacturability (DfM) process, during board design. Vias that certainly need to be capped are those that are connected to the BGA land with a short trace length or those that are connected to a plane in the board. Thirdly, a nonmetallic wave shield can be placed immediately below the BGA package locations on the bottom side of the board to avoid the wave from touching these board locations. The wave shield can also be attached to the wave pallet by nonmetallic fingers. Selective wave pallets can utilize solid material under the BGAs to prevent solder contact with the bottom of the board and heat transfer up the vias to the lands. This will prevent secondary reflow of the BGA joints. The efficacy of each of these methods should be confirmed by measuring the temperature profile of the BGA solder joints during the wave solder process and ensuring that they stay below 150°C. 6.4.4 Top Side Reflow for Lead-Free Boards Most leadfree solders targeted for use, including the popular solders in the SnAgCu system, have melting points higher than that for eutectic tin/lead solder. Hence, the potential for top
side reflow when wave soldering boards with surface mount lead-free components already reflow soldered on the top side of the board is significantly reduced. For SnAgCu solders, the maximum top side solder joint reflow temperature can reach 190°C without any impact on the BGA solder joints. The differences in contact design have differing effects on the quality and reliability of the contact, contactability, and later solderability. The effects are negligible and insignificant when the contact is minimal. 6.5 Testability and Test Point Access
6.5.1 Component Testing As the BGA pitches and solder ball size decrease, socket manufacturers face increasing challenges in the design of sockets to adequately test BGA packages. There are a myriad of tip designs socket manufacturers are working with to meet the needs of sub-mm pitch BGAs.
One challenge is to be able to make contact to all BGA individual balls. While attaching to a PCB, the solder balls melt and self align to attach to the corresponding lands on the PCB. Therefore, wider variations in the placements of solder balls are tolerable with respect to BGA attach to the PCB. But these variations need to be tightened in the case of test and burn-in and thus there is no self-alignment of solder balls to socket contacts. 59
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The design of socket probes needs to take into account the solder ball height variation. A larger variation in solder ball height would require a wider reach range for socket probes, and also when testing, the solder balls will be more vulnerable. Burn-in of BGAs is conducted at an elevated temperature. The burn-in time/temperature combination will soften the solder balls to an extent dependent upon the solder ball material. Under test probe pressure, the softened solder ball will deform heavily and may affect the contact quality during burn-in. The socket manufacturers need to assure that the probes do not stick to softened solder balls and the solder balls are not pulled away. The socket test probe design is also critical in that the probe does not gouge the solder ball in such a way or to such an extent that the deformation becomes a quality or reliability concern during or after BGA attach to the PCB. Some contacts touch the solder ball on their sides, and some on the tip of the solder balls. In some designs, the individual pins are spring-loaded, in others all contact probes are in the same rigid plane.
Figure 6-28 An example of a side contact made with a tweezers type contact
6.5.2 Damage to the Solder Balls During Test and Burn-In In their pristine form, eutectic solder balls on a
BGA are shiny and quite round. Their attach, handling, and subsequent BGA processing steps may induce deformation, damage, pokes and dents. The solder ball deformation during test and burn-in is an expected phenomenon and, as such, is an acceptable anomaly as long as it does not affect the usefulness of the product. Many contact designs exist, each vying for a better share of the market. Each contact will impart its unique imprint on the solder ball. These probes contact the solder ball at differing locations and impart unique imprints characteristic of the contact design to the solder ball during test and burn-in. Solder balls have been known to come off in certain situations. Rather than trying to catch the problem by using vision systems to detect the presence or absence of solder balls or the damage to solder balls during testing, it is prudent to optimize the solder attachment and to choose a test socket which is benign to the device under test. Some contacts disturb only the sides of the solder ball and not the bottom. The bottom of the solder ball is untouched during contact. One such example is shown in Figure 6-28. Other contacts impact the bottom of the solder ball. Figure 6-29 shows a solder ball which has been contacted at the bottom of the solder ball. The concern is that, during reflow, flux may get entrapped in the depressions formed by the contact and may explode under reflow heat, splattering solder around, causing shorts, etc. Some contacts are designed not to allow the entrapment of flux. Contact probes may contact the bottom of a solder ball to create a pattern which provides a path for the flux to escape and will not entrap flux during reflow. 60
Figure 6-29 Pogo-pin type electrical contact impressions on the bottom of a solder ball
Other contact impressions allow the entrapment of flux. If the impressions cause a hole at the bottom of the solder ball then there is a greater chance of flux entrapment. Such entrapment may be quite benign for shallow depressions. To be damaging, the depressions have to be larger than anticipated with current designs to entrap enough flux to cause problems. Some contacts are designed with individual force mechanisms for each contact pin. Other contacts come with common force mechanism applied to all contacts simultaneously. All different kinds of contacting mechanisms will leave some imprint on the solder balls. Contact size should be matched with the solder ball size to be tested to minimize the solder ball deformation. Therefore, the size of the contact needs to decrease with decreasing solder ball sizes and decreasing array pitches. Too large of a contact size may short and may subject the solder ball to undesired levels of deformation. The force mechanism to assure contact needs to match the solder ball hardness, which is dependent upon the solder constituents. Too much force will impart unnecessary
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deformation. The force mechanism needs to provide enough force to contact the smallest balls in an array. The solder balls soften when subjected or exposed to elevated temperatures and time durations. Force mechanism design needs to take this change in consideration for their use at varying temperatures. Even at ambient, continuous testing of parts may increase the temperature at the contact site. For all practical purposes, the solder ball needs to be solderable with acceptable contact strength, contact area and solder column shape after it has endured the rigors of testing and burn-in. To assess the impact of processing through test and burn-in, the items to look at should include solderability, coplanarity, and general cosmetic shape of the solder ball. The solder ball should not lose so much solder to the test and burn-in process that enough solder is not left for optimum connection. The ball should be able to respond to the reflow process to produce an acceptable contact. Ball corrosion and foreign material picked up during test and burn-in should not adversely affect the quality and long-term reliability of the solder ball. After the test and burn-in cycle, especially for no-melt balls, meeting the coplanarity expectations will be an essential requirement for proper BGA attachment to substrate. Various technologies contact different parts of the solder ball. In fact, most of the contact designs touch the bottom of the solder ball to make a contact. In view of these options, it would be impossible to declare certain parts of the solder ball untouchable during its processing. To keep a certain area of the solder ball untouchable is neither practical nor necessary if it has no effect on solderability, coplanarity, solder volume, quality and reliability of the end product. 6.5.3 Bare Board Testing There are a number of issues that arise when considering the test inspection and measurement of increasingly complex substrate interconnections, especially when involved with the electrical evaluation of the substrate. In order for the manufacturer to be able to reduce cost, while adequately assuring the electrical function of the substrate interconnection, the customer will have to provide definitive test data, with the preference being 100% net list testing. Compatibility of the data is currently an issue as well. It is hoped that industry standardization efforts will help to solve this issue in the foreseeable future. One item which could prove key to achieving this is likely to be acceptance of a standard base grid pitch, which would allow test equipment and socket manufacturers to examine and focus on creation of a universal solution.
The use of fixtures and bed of nails testing for opens and shorts testing is quickly losing the ability to meet test requirements as feature size decreases, coupled with increased densities. Double density, or 1.77 mm pitch, test beds seem to be adequate for 400 µm pitch and up. As the
IPC-7095B
density of the substrate increases beyond 400 µm pitch, alternative techniques must be considered. Quad density fixturing is a possibility, with 62 test probes per square centimeter, but concern increases about potential feature damage due to the contact by the probes. In addition, the cost of double and quad density fixtures, as well as the cost of test equipment, make it difficult to justify total test coverage within cost expectations based on current understanding of electrical testing and a linear projection of present testing concepts. Regarding the I/O density of 200 to 1000 at various grid segmentation, it becomes apparent that double and quad density is capable for bare board continuity testing the average I/O requirements. However, if components are stacked ‘‘edge-to-edge’’ the testing becomes impossible with this test approach. This is because a BGA on 1.0 mm pitch contains 96 lands per cm2, and the quad density test fixture is only able to accommodate 62 probes per cm2. Spreading components on the mounting structure relieves some of that complexity but also consumes more space and reduces performance. It should also be noted that, using presently available testing concepts, maximum component I/O creates a condition that drives testing cost of the bare board dramatically higher due to multi-pass or dual fixture testing in order to have full test coverage. Figure 6-30 shows the relationship of part land requirements compared to fixture capability. Flying probe testing eliminates the need for costly fixtures and, depending on the volume of substrates being manufactured, can provide a cost-effective alternative to bed-ofnails testing. Unfortunately, the test is relatively slow, depending on the equipment used, and the equipment can be expensive. The problem is compounded by the increased density requirements and the need for additional net testing. Most of this equipment/test technique has evolved from the semiconductor industry and has experienced some difficulty in scaling to meet the mechanical challenges associated with larger panel sizes. In addition, the small feature size in some instances defeats the detection system due to the difficulties in charging the feature with the probe. Additional equipment development will have to take place if technologies such as this are going to be useful for the complex substrates of the future. As via size continues to decrease, the limits of conventional evaluation with metallographic microsection will become less viable. 150 µm vias seem to be the practical limit for microsection labs of average competence. An alternative test method will be required if companies want to know more about the plating in the via than just continuity. An electrical Interconnect Stress Test (IST) is presently being used by some companies to determining hole integrity and reliability. 6.5.4 Assembly Testing Design of a printed board assembly for testability normally involves system level testability issues. In most applications, there are system
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Z Single Density
P 100 TP/sq. in.
0.10 in
15.5 TP/sq. cm.
Double Density 200 TP/sq. in. 31 TP/sq. cm.
Quad Density
P, mm.
Z,cm
I/O
TP/sq. cm
ET
1.5
2.53
300
46.9
QD
1.27
2.06
300
70.6
>QD
1.0
1.76
300
96.8
>QD
400 TP/sq. in 62 TP/sq. cm.
Note: Fixture density assumes that components are minimum distance from each other and ET pins from outside the package outline cannot be used. When components are not brickwalled then pins can be gathered from outside the device land pattern. IPC-7095b-6-30
Figure 6-30
Area array land pattern testing
level fault isolation and recovery requirements such as mean time to repair, percent up time, time to operate through single faults, and maximum time to repair. To meet the contractual requirements, the system design may include testability features, and many times these same features can be used to increase testability at the printed board assembly level. The printed board assembly testability philosophy also needs to be compatible with the overall integrations, testing and maintenance plans for the contract. The factory testers to be used, how integration and test is planned, when printed board assemblies are conformal coated, the depot and field test equipment capabilities and personnel skill level are all factors that must be considered when developing the printed board assembly test strategy. The test philosophy may be different for different phases of the program. For example, the first unit debug philosophy may be much different than the test philosophy for spares when all the systems have already been shipped. Before the PWB design starts, requirements for the system testability functions should be presented at the conceptual design review. These requirements and any derived requirements should be partitioned down to the various printed board assemblies and documented. The system and program level test criteria and how they are partitioned down to the 62
printed board assembly requirements are beyond the scope of this document. The two basic types of printed board assembly test are functional test and in-circuit test. Functional testing is used to test the electrical design functionality. Functional testers access the board under test through the connector, test points, or bed-of-nails. The board is functionally tested by applying predetermined stimuli (vectors) at the printed board assembly’s inputs while monitoring the printed board assembly outputs to ensure that the design responds properly. In-circuit testing is used to find manufacturing defects in printed board assemblies. In-circuit testers access the board under test through the use of a bed-of-nails fixture which makes contact with each node on the printed board assembly. The printed board assembly is tested by exercising all the parts on the board individually. In-circuit testing places fewer restrictions on the design. Conformal coated printed board assemblies and many Surface Mount Technology (SMT) and mixed technology printed board assemblies present bed-of-nails physical access problems which may prohibit the use of in-circuit testing. Primary concerns for in-circuit test are that the lands or pins (1) must be on grid (for compatibility with the use of bed-of-nails fixture), and (2) should be accessible from the bottom side (a.k.a. noncomponent or
March 2008
solder side of through-hole technology boards) of the printed board assembly. Manufacturing Defects Analyzer (MDA) provides a low cost alternative to the traditional in-circuit tester. Like the in-circuit tester, the MDA examines the construction of the printed board assembly for defects. It performs a subset of the types of tests, mainly only tests for shorts and open faults without power applied to the printed board assembly. For high volume production with highly controlled manufacturing processes (i.e., Statistical Process Control techniques), the MDA may have application as a viable part of a printed board assembly test strategy. Vectorless Test is another low cost alternative to in-circuit testing. Vectorless Test performs testing for finding manufacturing processrelated pin faults for SMT boards and does not require programming of test vectors. It is a powered-off measurement technique consisting of three basic types of tests: 1. Analog Junction Test – DC current measurement test on unique pin pairs of the printed board assembly using the ESD protection diodes present on most digital and mixed signal device pins. 2. RF Induction Test – Magnetic induction is used to test for device faults utilizing the printed board assemblies device protection diodes. This technique uses chip’s power and ground pins to make measurements for finding solder opens on device signal paths, broken bond wires, and devices damaged by ESD. Parts incorrectly oriented can also be detected. Fixturing containing magnetic inducers are required for this type of test. 3. Capacitive Coupling Test – This technique uses capacitive coupling to test for pin opens and does not rely on internal device circuitry, but instead relies on the presence of the metallic lead frame of the device to test the pins. Connectors and sockets, lead frames and correct polarity of capacitors can be tested using the technique. 6.5.4.1 Board Flexure During Testing Since lead-free joints can be stiffer and less ductile than tin/lead joints, in-circuit/functional test fixtures can damage solder joints if their design and manufacturing results in excessive board flexing during use. This board flex induced damage is typically caused by improper location of board supports and hold-downs, especially around areas with high concentrations of test probes. Excessive board flexure may also be caused by improper planar alignment of supports and holddowns, high probe forces, as well as by excessive or insufficient vacuum or improper distribution of springs between top plate and probe plate. In addition, Improperly designed tooling and fixtures can easily lead to improper flexure of the PCB, leading to damage.
In order to insure that a test fixture does not cause damage to printed circuit assemblies (PCAs), strain and strain-rate must be measured on PCAs during use of the test fixture. Measurements must be done at the corners of BGAs using
IPC-7095B
three element rectangular rosettes placed according to the recommended gauge placement in IPC/JEDEC-9704. Strains and strain-rates should be specified in a ‘‘strain limit specification’’ defining actuation, test or release requirements of the unit under test (UUT). The strain measurement system must simultaneously sample all elements in each rosette (e1, e2, e3) in order to properly measure and calculate all strain components. The generally accepted strain limits for tin/lead PCAs is 600 µε, either principal or diagonal. The generally accepted strain limits for lead-free PCAs is 450 µε, either principal or diagonal. The generally accepted Maximum Strain Rate is 30,000 µε/sec, either principal or diagonal. Typical Damage Acceptance Criteria is: No damage to BGA solder joints detected using cross-section FA method. 6.5.4.2 In-Circuit Test Concerns In-circuit testing is used to find shorts, opens, wrong parts, reversed parts, bad devices, incorrect assembly of printed board assemblies and other manufacturing defects. In-circuit testing is neither meant to find marginal parts nor to verify critical timing parameters or other electrical design functions.
In-circuit testing of digital printed board assemblies can involve a process that is known as back driving (see IPCT-50). Back driving can also cause devices to oscillate and the tester can have insufficient drive to bring a device out of saturation. Back driving can be performed only for controlled periods of time, or the junction of the device (with the overdriven output) will overheat. The two main concerns for designing the printed board and printed board assembly for in-circuit testability are design for compatibility with in-circuit test fixturing and electrical design considerations. 6.5.4.3 Functional Testing Concerns There are several concerns for designing the printed board assembly for functional testability. The use of test connectors, problems with initialization and synchronization, long counter chains, self diagnostics, and physical testing are topics which are discussed in detail in the following subsections and are not meant to be tutorials on testability but rather ideas of how to overcome typical functional testing problems. Fault isolation on conformal coated boards or most SMT and mixed technology designs can be very difficult because of the lack of access to the circuitry on the board. If strategic signals are brought out to a test connector or an area on the printed board where the signals can be probed (test points), fault isolation may be much improved. This lowers the cost of detection, isolation and correction. It is also possible to design the circuit so that a test connector can be used to stimulate the circuit (such as taking over a data bus via the test connector) or disable functions on the
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printed board assembly (such as disabling a free running oscillator and adding single step capability via the test connector). 6.6 Other Design for Manufacturability Issues The layout generation process should include a formal design review of layout details by as many affected disciplines within the company as possible, including fabrication, assembly and testing. The approval of the layout by representatives of the affected disciplines will ensure that these production-related factors have been considered in the design. The success or failure of an interconnecting structure design depends on many interrelated considerations. From an end-product usage standpoint, the impact on the design by the following typical parameters should be considered. Other design for manufacturability issues include:
• Equipment environmental conditions, such as ambient temperature, heat generated by the components, ventilation, shock and vibration • If an assembly is to be maintainable and repairable, consideration must be given to component/circuit density, the selection of board/conformal coating materials, and component placement for accessibility. • Installation interface that may affect the size and location of mounting holes, connector locations, lead protrusion limitations, part placement, and the placement of brackets and other hardware • Testing/fault location requirements that might affect component placement, conductor routing, connector contact assignments, etc. • Process allowances such as etch factor compensation for conductor widths, spacings, land fabrication, etc. • Manufacturing limitations such as minimum etched features, minimum plating thickness, board shape and size, etc. • Coating and marking requirements • Assembly technology used, such as surface mount • Through-hole, and mixed • Board performance class • Materials selection • Producibility of the printed board assembly as it pertains to manufacturing equipment limitations – Flexibility (Flexural) Requirements – Electrical/Electronic – Performance Requirements • ESD sensitivity considerations 6.6.1 Panel/Subpanel Design Panelization of parts is a standard process for both test and assembly. A datum system is required for the panel, as well as each individual board in the panel. To reduce tolerance buildup, it is important to relate each individual board datum to the panel datum (see Figure 6-31).
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Most assembly companies want to build the assembly in array format, similar to that shown in Figure 6-31. The board manufacturer of these subpanels would position the subpanels on the standard manufacturing panel, which is usually 460 x 610 mm. Designers are encouraged to work with their manufacturing suppliers in order to optimize the material movement, and the manner in which the panels/ boards are removed from their respective position and how they are tested. Coupons have been used by the industry for many years in an effort to evaluate the product being built. These coupons represented the features of the board or the features of the assembly. They are incorporated into the borders of the panels either used for board manufacturing or the subpanels provided to the assembly company. Known as quality conformance coupons, they were many times evaluated once the product had been completely manufactured. This technique is no longer valid in that the concepts of inspecting the quality into the product have not borne fruit. Most manufacturers and assemblers have their processes in control, nevertheless, coupons are of value to make certain through various physical evaluations that the process and the recipe used to make the part stay in the control that is necessary to meet requirements. This concept is essential for BGAs since one cannot see the lands or the solder joints once the assembly has taken place. Test coupons or specimens should reflect the specific board or panel characteristics. The data derived from panels should be used to establish the requirements for vias and lands, conductors, spaces, etc. When specimens are used to establish process control parameters, they shall consistently use single hole size or land configuration which reflects the process. Process characteristics and general board characteristics should be matched. 6.6.2 In-Process/End Product Test Coupons
IPC-2221 provides excellent coupons that are used to evaluate those board and assembly characterizations. They include: • Hole Solderability • Solder Resist Tenting • Thermal Stress Plating • Thickness and Bond Strength • Plating Adhesion • Surface Solderability • Solder Resist • Surface Mount Solderability • Surface Bond Strength • Surface Insulation Resistance • Moisture Insulation Resistance • Registration • Interconnect Resistance
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IPC-7095B
PANEL TOOLING HOLE (3 PLACES)
INDIVIDUAL BOARD TOOLING HOLES (3 PLACES PER BOARD)
X.XXX
X.XX X.XXX
X.XXX
DATUM
DATUM X.XXX
X.XX X.XXX
X.XX X.XX
8 BOARD PANELIZATION IPC-7095b-6-31
Figure 6-31
Board panelization
Figure 6-32 shows alternate coupons that can be used to evaluate the cleanliness of a board after ball attachment has been completed. These comb patterns are used on the board in order to make certain that flux or flux residue does not impair the electrical properties of the product. 6.7 Thermal Management The primary objective of thermal management is to ensure that all circuit components, especially the BGAs, are maintained within both functional and maximum allowable limits. The functional temperature limits provide the ambient or component package (case) temperature range within which the electronic circuits can be allowed to properly perform.
The cooling technique to be used in the printed board assembly applications must be known in order to ensure the proper printed board assembly design. For commercial applications, direct-air cooling (i.e., where cooling air contacts the printed board assembly), is usually used. For rugged and hostile usage, indirect cooling must be used to cool the printed board assembly. In this application, the assembly is mounted to the cooling structure that is air or
liquid cooled and the board components are cooled by the conduction through a heat exchange surface. These designs must use appropriate metal heatsinks on the printed board assembly. Appropriate component mounting and bonding may be required. To ensure adequate design, thermal dissipation maps must be provided to aid analysis and thermal design of the printed board assembly. The dissipation of heat generated within electronic equipment results from the interaction of the three basic modes of heat transfer: conduction, radiation, and convection. These heat transfer modes can, and often do, act simultaneously. Thus, any thermal management approach should attempt to maximize their natural interaction. 6.7.1 Conduction Conduction takes place to a varying degree through all materials. The conduction of heat through a material is directly proportional to the thermal conductivity constant (K) of the material, the cross sectional area of the conductive path and the temperature difference across the material. Conduction is inversely proportional to the length of the path and the thickness of the material (see Table 6-11).
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IPC-7095b-6-32
Figure 6-32
Comb pattern examples Table 6-11
Effects of material type on conduction Thermal Conductivity (K)
Watts/inch °C
Watts/m °C
Gram-calorie/cm °C • s
Still Air
Materials
0.0007
0.0276
0.000066
Epoxy
0.005
0.200
0.00047
Thermally Conductive Epoxy
0.02
0.787
0.0019
Aluminum Alloy 1100
5.63
222
0.530
Aluminum Alloy 3003
4.88
192
0.459
Aluminum Alloy 5052
3.52
139
0.331
Aluminum Alloy 6061
4.36
172
0.410
Aluminum Alloy 6063
4.88
192
0.459
Copper
4.93
194
0.464
Steel Low Carbon
1.19
46.9
0.112
Thermal radiation is the transfer of heat by electromagnetic radiation, primarily in the infrared (IR) wavelengths. It is the only means of heat transfer between bodies that are separated by a vacuum, as in space environments.
Table 6-12
6.7.2 Radiation
Heat transfer by radiation is a function of the surface of the ‘‘hot’’ body with respect to its emissivity, its effective surface area and the differential to the fourth power of the absolute temperatures involved. The emissivity is a derating factor for surfaces that are not ‘‘black bodies.’’ It is defined as the ratio of emissive power of a given body to that of a black body, for which emissivity is unity (1.0). The optical color of a body has little to do with it being a ‘‘thermal black body.’’ The emissivity of anodized aluminum is the same if it is black, red or blue. However, surface finish is important. A matte or dull surface will be more radiant than a bright or glossy surface (see Table 6-12). 66
Emissivity ratings for certain materials
Material and Finish
Emissivity
Aluminum Sheet - Polished
0.040
Aluminum Sheet - Rough
0.055
Anodized Aluminum - any color
0.80
Brass - Commercial
0.040
Copper - Commercial
0.030
Copper - Machined
0.072
Steel - Rolled Sheet
0.55
Steel - Oxided
0.667
Nickel Plate - Dull Finish Silver Tin
0.11 0.022 0.043
Oil Paints - Any Color
0.92-0.96
Lacquer - Any Color
0.80-0.95
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Devices, components, etc. close to one another will absorb each others’ radiant energy. If radiation is to be the principle means of heat transfer, ‘‘hot’’ spots must be kept clear of each other. 6.7.3 Convection The convection heat transfer mode is the most complex. It involves the transfer of heat by the mixing of fluids, usually air.
The rate of heat flow by convection from a body to a fluid is a function of the surface area of the body, the temperature differential, the velocity of the fluid and certain properties of the fluid. The contact of any fluid with a hotter surface reduces the density of the fluid and causes it to rise. The circulation resulting from this phenomenon is known as ‘‘free’’ or ‘‘natural’’ convection. The air flow can be induced in this manner or by some external artificial device, such as a fan or blower. Heat transfer by forced convection can be as much as ten times more effective than natural convection. 6.7.4 Thermal Interface Materials Attachment of heat sinks to BGAs is the most common technique today in cooling the silicon devices packaged within the BGAs. These heat sinks require a thermal interface material to be sandwiched between the heat sink and the BGA in order to conduct the heat from the top of the package surface and into the bottom of the heat sink surface.
When selecting a thermal interface material, keep in mind the surface flatness of the BGA body and the heatsink. Warpage of the BGA package during reflow and large tolerances on the heatsink contact surface can result in large gaps that are difficult to fill reliably with some interface materials. This in turn can cause poor thermal conductivity and/or a weak heatsink attachment bond. There are various types of thermal interface materials (TIM). These are described below. Adhesives: Metal filled epoxies and silicone adhesives were commonly used as TIMs initially. They play a dual part of being a TIM as well as a mechanical attachment method since when cured they become highly cross-linked and attain high cohesive strength. Hence, unlike the other TIMs, supplementary mechanical attachment methods are not necessary when using adhesive. Disadvantages of adhesives include a thermal cure step being necessary after the BGA is soldered on the board and the potential for severe delamination at the interfaces that the adhesive bonds to due to coefficient of thermal expansion mismatches between the heat sink and the package. Another subclass of adhesives are the Pressure Sensitive Adhesives (PSAs), which do not require a cure to generate the interfacial bond, but instead require a certain amount of pressure, typically in the 20 to 30 psi range. Their use for BGAs is therefore limited since this pressure, if not properly controlled, may adversely impact the BGA solder joints.
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Greases: Thermal greases are metal filled polymers that have the inherent advantage of being ‘liquidy’ and conforming to the macroscopic and microscopic irregularities in the surfaces of the heat sink and the BGA component. They have excellent thermal performance and unlike adhesives do not require a cure. A major disadvantage of thermal greases is that they tend to migrate out from between the heat sink and package interfaces over time. This phenomenon is known as ‘pump out‘ and is caused by the thermo-mechanical stresses exerted at the interfaces during temperature cycling. Phase change materials (PCM): Phase change materials are in a solid state at room temperature but become liquid at the higher temperatures at which they are required to conduct heat away from the BGA surface. Hence, they offer ease of handling and dispensing because they typically are in a film form and do not need to be cured. However, their thermal conduction properties are inferior to greases, adhesives and the other TIM alternatives so they are only suitable for use with low wattage devices. Gels: Gels are comprised of a lightly cross-linked silicone polymer filled with metal or ceramic particles that impart the thermal conductivity necessary for this TIM. Gels combine the beneficial properties of greases and cured adhesives, do not pump-out and do not require a post application cure step. Their modulus is low enough to relieve thermo-mechanical stresses and avoid interfacial delaminations. They have high bulk thermal conductivities and have been used in cooling BGA components containing high wattage CPU devices. Thermal conductive pressure sensitive tape: Thermal conductive pressure sensitive tape may occasionally be used to impart the thermal conductivity necessary to remove heat from the BGA. This thermal interface material is becoming more widely used due to the ease of handling and applying to the surfaces that are used for cooling BGA components. 6.7.5 Heat Sink Attachment Methods for BGAs There are quite a few techniques for attaching heat sinks to BGAs. These are depicted in the following illustrations.
Figure 6-33 shows a heat sink attached to the top of a BGA package with a thermally conductive adhesive. The adhesive acts as both a thermal conduction medium as well as a mechanical attachment medium. As mentioned above, however, this technique requires a post solder thermal cure step to cross-link the adhesive and harden it. Figure 6-34 illustrates a heat sink attached to the top of a BGA package with clips that hook on to a BGA substrate, however there is danger of damage to the solder joints while attaching the clips. The thermal interface material in this case is a grease, or PCM or gel, i.e., one that does not provide a strong mechanical bond between the heat sink and the top of the BGA package. This method has one 67
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Heat Sink
Adhesive BGA Board IPC-7095b-6-33
Figure 6-33
Heat sink attached to a BGA with an adhesive
clip
Heat Sink BGA
Grease/ Gel/PCM Board IPC-7095b-6-34
Figure 6-34
Heat sink attached to a BGA with a clip that hooks onto the component substrate
drawback. The weight of the heat sink is supported by the package and, during mechanical shock and vibration, the solder balls of the BGA have to bear the mechanical stresses generated by the additional mass of the heat sink.
method of attachment transfers even less stress on the BGA solder balls during mechanical shock and vibration than the previous case. However, the solder joints of the stakes will bear most of this stress.
Figure 6-35 depicts the case of a heat sink attached to the BGA with clips that hook into holes in the printed circuit board. These holes do not have to be plated. Unlike the previous case, the printed circuit board supports the weight of the heat sink when the clips are actuated, but some stress can still be transferred on to the BGA solder balls during mechanical shock and vibration. In addition, the heat sink may create a cantilevered load on the solder joint when the assembly is in a vertical orientation. This load may lead to premature solder joint failure.
Figure 6-37 illustrates the attachment of the heat sink to a BGA by directly soldering the heat sink into the board during the wave soldering process step. The heat sink design has four or more pins that insert into holes in the board prior to the wave solder process. As opposed to the previous cases above, this method does not need any post assembly processing to attach the heat sink.
Figure 6-36 shows the case of a heat sink attached to a BGA package with clips that hook on stakes that are wave soldered into holes in the printed circuit board. This
The three methods in Figures 6-30, 6-31 and 6-32 have one drawback not present in the first two. These methods require holes in the printed circuit to be designed in. These holes may reduce the trace routing real estate on all the board layers. For highly dense board designs, this could impact the final layer count of the board.
clip
Heat Sink BGA
Grease/ Gel/PCM Board IPC-7095b-6-35
Figure 6-35
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Heat sink attached to a BGA with a clip that hooks into a through-hole on the printed circuit board
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Clip Heat Sink
Grease/ Gel/PCM
BGA
Board IPC-7095b-6-36
Figure 6-36
Heat sink attached to a BGA with a clip that hooks onto a stake soldered in the printed circuit board
Heat Sink Pin
BGA
Grease/ Gel/PCM Board IPC-7095a-6-25
Figure 6-37
Heat sink attached to a BGA by wave soldering its pins in a through-hole in the printed circuit board
The documentation package for describing BGA components usually consists of a master drawing, master pattern drawing, copies of artwork (film or paper), mounting structure assembly drawing, parts list, and schematic/logic diagram. The documentation package may be provided in either hard copy or electronic data. All information about documentation is also appropriate for electronic data transmission. Since many CAD systems have their own native database, everyone is promoting some form of unique format that has a neutral concept, thus avoiding sending the native database to the suppliers. 6.8 Documentation and Electronic Data Transfer
Unfortunately, the lowest common denominator for years has been a machine language. This is trying to be circumvented by such formats as the IPC-D-350, IPC-D-356, IPC2511 or IPC-2581. Archiving electronic data should be in accordance with these documents. Delivery of computer generated data as a part of the documentation package should meet the requirements stated in those packages. With automated techniques, the database shall detail all information that will be needed to produce the printed board or mounting structure for the bare die. This includes all notes, plating requirements, board thickness, etc. The test plots should be employed to verify that the data matches the requirements.
Other documentation may include numerical control data for drilling, routing, libraries, tests, artwork, and special tooling. There are design and documentation features/ requirements that apply to the basic layout, the production master (artwork), the mounting structure itself, and the end item component or printed board assembly. All must be taken into consideration during the design of the mounting structures for the bare die, or the mounting structure for the BGA. Documentation shall meet the requirements of IPCD-325. In order to provide the best documentation package possible, it is important to review IPC-D-325 and identify all the criteria that are affected by the design process. 6.8.1 Drawing Requirements During the formal design review prior to layout, special tools that can be generated by the design area in the form of artwork or numerical control data shall be considered. This tooling may be needed by fabrication, assembly, or testing. Examples of such tooling are artwork overlays, artwork solder resist stripping, numerical data for automatic attachment, solder paste stencil, or plots of numerical data to be used as check films.
When viewing the documentation, it is always viewed from the primary side. All phototool generation is viewed from that same direction. The definition of layers of the product shall be viewed looking through the particular part from the primary side. 69
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Accuracy and skill must be sufficient to eliminate inaccuracies from the layout as being interpreted during the artwork generation process. This requirement can be minimized by strictly adhering to grid systems, which define all features on the board or on the bare die. Layout notes should be as complete as possible with the addition of appropriate notations. Marking requirements and revision status level definition is key to maintaining configuration management conditions. It is especially important for the engineering review cycle, a quoting effort, and when the document is used by someone other than the originator. 6.8.2 Equipment Messaging Protocols Throughout the electronics industry manufacturing consists of numerous steps, each of which often centers around one supplier’s equipment. Although the steps are generally wellautomated within themselves, they only peripherally connected to one another. Proprietary data formats and communications protocols prevent the islands of automation from talking to one another. This condition also prevents factory managers from monitoring, understanding, and possibly correcting the manufacturing process to improve throughput and product quality.
In the last few years, building on an International Electronics Manufacturing Initiative (iNEMI) funded project, the IPC has standardized data syntax and semantics in electronics assembly, establishing rules for data exchange both on a single factory floor and between that floor and the rest of a manufacturing organization. The results have been published as the IPC CAMX (computer-aided manufacturing using the extensible markup language [XML]) standards: The standards are: • IPC-2541 ‘‘Generic Requirements for ElectronicsManufacturing Shop-Floor Equipment Communication’’ • IPC-2546 ‘‘Sectional Requirements for Shop-Floor Equipment Communication Messages (CAMX) for Printed Circuit Board Assembly’’ • IPC-2547 ‘‘Sectional Requirements for Shop Floor Equipment Communication Messages (CAMX) for Printed Circuit Board Test, Inspection and Rework’’ At the heart of the standard is a framework with an intermediary. This is the ‘‘message broker’’ that handles information exchange and complies with the IPC-2501 Standard (‘‘Definition for Web-based Exchange of XML Data’’). The message broker can be thought of as a post office or a mail server. Messages are sent to the server and, when the information is needed, it is asked for by the equipment or the manager who wants the data. In a factory, several lines of equipment and several applications may connect to the message broker at the same time. Individual elements need not know any details about the nature, configuration, or format of the others. They 70
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communicate directly only with the broker. When people and equipment need specific information, the broker provides it in the correct format. 6.8.2.1 Implementation It is relatively easy to set up the infrastructure and Web-based tools to monitor several sets of manufacturing equipment, including in-circuit testers, and several suppliers’ pick-and-place machines. The setup can be used to gathered performance and functional feedback data on the message broker. The message broker can usually be up and running in two days, being able to connect reasonably easily with both legacy equipment and any XML-ready equipment using an infrastructure that is in place at the manufacturing site. In a careful installation, it is also possible to avoid compromising network security requirements.
Using internet standards like HTTP and XML ensures the interoperability between different platforms. Although an application has never been run against a running message broker before, it can be adapted to the existing communication framework on site. One important goal of the IPC CAMX standards is to lower the technological barrier to ease the integration of sophisticated equipment like pickand-place machines and test equipment, as well as simpler equipment like printed board handlers. The CAMX standards provide data about the products under manufacture, the processes, and the shop-floor equipment. Applications receiving messages from the equipment include: • Work-in-process (WIP). • Tracking, capacity, and throughput monitors. • Equipment utilization and line-balancing monitors. • Product quality monitors that incorporated data from test and inspection. Linking all parts of a manufacturing operation through a single hub has been the goal for many years. The CAMX message-broker approach provides an extraordinary array of tools to accomplish that task. The message broker can connect any number of clients together. Clients can be factory equipment, a host computer, or the data hub at the engineering manager’s desk. The system provides visual representation of whatever the manager wants to know. The manager can communicate with someone in Singapore, and check the status of their work-in-process using a snapshot of the data in any of a number of preset formats. He can pick the format and instruct the software as to how frequently the updates are required, and the broker does the rest. 6.8.2.2 Information Exchange Benefits Major equipment manufacturers have involved themselves in this effort from the beginning, thus they support the CAMX effort to extract information from their machines in the standard format. Critical to the success of this new tool is its ‘‘plugand-play’’ construction. Any piece of equipment on the
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floor can connect to the supporting architecture and datagathering software. Using XML as the standard ensures that no one will misinterpret what the data means. Process correction and product improvement require traceability of faults, regardless of where a fault is identified. Knowing where the fault came from and its root cause are critical.
should be provided in this same manner in which the original package is provided (hard copy or electronic). Conformance test circuitry shall be provided, thus the part can be tested through destructive techniques. As a minimum, conformance test circuitry shall include:
In addition, increasing product quality and reducing costs require understanding the actual fault spectrum. Historically, the same fault may be called by several names at different process points. Applying the CAMX standard, fault names can be consistent from step to step within the manufacturing operation, thereby improving the overall level of communication.
• Traceability identification
For electronics manufacturing service (EMS) providers, the CAMX standards permit manufacturing flexibility without sacrificing data coherence and comprehensive data analysis, regardless of the process under evaluation. The software is more streamlined and less complex than systems that were developed for the semiconductor industry because all of the equipment now conforms to the single standard. The result is equipment that is both easier to use and easier to support.
7 ASSEMBLY OF BGAS ON PRINTED CIRCUIT BOARDS
Standardization will open up opportunities to perform more elaborate data analysis because the standards will reduce the effort required to gather information. IPC-2501, as implemented in the CAMX message broker, provides the simplified web-based XML messaging activity for the other IPC standard vocabularies. Equipment suppliers who need a particular piece of information will merely ‘‘subscribe’’ to an application or system using the existing Web-based and universal XML messaging SOAP protocol, regardless of the architecture of the other interfaces, and download responses in real time. SOAP is an XML messaging standard supported by all major computing and software vendors. It forms the foundation of their Web-services infrastructures. The XML message type of machine communication was less necessary when OEMs did their own manufacturing. However, with the amount of outsourcing that kind of vertical integration has become more the exception than the rule. The new standards will make it possible for the OEM customer to regain a measure of the insight into manufacturing activity that was lost due to outsourcing the work. The use of a universal data format will also provide the ability of suppliers to monitor inventory of their products to prevent disruptions of the manufacturing line. Component suppliers can monitor usage of their components on the factory floor, scheduling purchases and taking over similar functions that otherwise fall to the EMS company or to the OEM. In many instances, documentation references other specifications. These should be clear and 6.8.3 Specifications
• Board part number/revision letter • Date code • Manufacturer’s identification, e.g., commercial and government entity (CAGE), logo, etc. • Special coding systems may be used provided they are identified on the master drawing
7.1 SMT Assembly Processes The assembly processes for attaching BGA components are more forgiving than the processes for attaching fine pitch peripheral components. Process defect rates can be greatly reduced, however good process control is a necessity.
The surface mount assembly process uses solder paste to connect the BGA balls to the lands on the board. Solder paste can be applied to the lands using three methods: screening, stenciling, and dispensing. BGAs are typically printed using stenciling where solder paste is applied on the BGA lands through the apertures on the stencil of similar size or smaller to the BGA lands. 7.1.1 Solder Paste and Its Application
Stencil thickness and aperture size will determine paste volume, which is very critical for ceramic BGAs. Also, the type of squeegee is an important factor in determining paste volume when printing the solder paste by squeegees. The stencil thickness may need to be reduced when using finer pitch BGA components. It is helpful to have trapezoidal stencil apertures (slightly larger opening on the bottom than on the top) for better paste release. Generally, on larger BGA components with 1.25 mm and 1.00 mm pitch, the aperture is large enough that stencil clogging, print registration and definition are less of a problem than with QFP components. Solder paste consists of a homogeneous mixture of metal powder particles and flux. The metal content (typically 90% by weight) in the solder paste determines the amount of solder in the solder joint. The most common solder paste alloy is the eutectic Sn63Pb37, and SAC 305 for lead free (Sn96.5Ag3.0Cu0.5). Metal powder particles are generally spherical in shape. A uniform shape aids the printing or dispensing process and it decreases the surface area, which minimizes oxidation. Flux makes up the majority of the remaining substances in the solder paste. The activators in the flux remove oxides from the solder particles, the land, and the BGA balls. They 71
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promote good solderability during reflow process. Solder balls, which form for a variety of reasons during reflow, are a reliability concern, especially when fine pitch devices are involved. The solvents have an important role in controlling the tackiness of the paste and affecting the rheological properties. The formation of voids in the BGA solder joint may be related to solvents in the solder paste. Solvents with low boiling points and/or improper reflow parameters can increase the incidence of voids in BGA solder joints. For successful fine pitch BGA printing, the solder paste must pass through very small apertures in the stencil. The solder paste needs to remain printable and tacky for an extended period of time, and it must maintain print definition prior to and during reflow. Solder paste viscosity, particle size and stencil life are critical parameters for solder paste application.
It is very important to design a stencil aperture that will provide good paste release. In order to ensure good paste release, an aspect ratio of 1.5 is recommended. Aspect ratio is the ratio between stencil aperture width and stencil thickness. Another commonly used ratio is called area ratio. An area ratio of greater than 0.66 is recommended. The formula to calculate area aspect ratio is the area of the stencil aperture divided by the area of the stencil walls (see Figure 7-1).
Stencil Stencil Thickness: T
Aperture Width: W
Aperture Length: L
7.1.1.1 Particle Size and Paste Selection Many solder pastes are available and one should be selected based on (among other things) the print characteristics, flux type, and fine pitch particle size. Print characteristics includes that the solder paste print well, providing good print definition without exhibiting solder paste slump. The flux in the paste should be active enough to exhibit good wetting and reflow characteristics, yet it should be compatible with the cleaning process or surface resistivity requirements if a no-clean flux is used. The diameter of the particle size should not exceed the aperture width divided by 4.2. This was determined through empirical experimentation. When this rule is violated, the paste release and print definitions are affected.
The solder particle size is classified by J-STD-005 (see Table 7-1). Table 7-1
Particle size comparisons
Solder paste type
Mesh
Maximum particle size [µm]
Type 2
-200/+325
75
Type 3
-325/+500
53
Type 4
-400/+500
38
Type 5
-500
25
Particle size distribution affects the solder paste viscosity and printability. Type 3 paste is the most commonly used, and it is adequate for most printing applications. Ultra fine pitch CSP application may require Type 4 paste. 7.1.1.2 Stencil Thickness and Aperture Design As is the case for all components, as the pitch of the part decreases it becomes necessary to decrease the stencil thickness. For BGA components in the pitch range of 1.5 mm to 1.0 mm, a stencil can range from 0.15 mm to 0.18 mm thick. For chip scale packages (CSP) or fine pitch BGAs with a pitch ≤0.80 mm, a stencil thickness range of 0.1 mm to 0.15 mm is recommended.
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Figure 7-1 release
Aspect and area ratios for complete paste
Area land contact/area stencil wall equals aperture/area of aperture walls) = L*W/2*(L+W)*T >0.66. LxW x T 2(L+W) Note: Aspect ratio is more common than area ratio in aperture design since aspect ratio is one dimensional simplification of the area ratio when land length is much greater than width, i.e., a square aperture with a dimension of 0.35 mm with a stencil thickness of 0.125 mm gives the resulting aspect ratio: 0.35x0.35 0.1225 = = 0.70 2(0.35+0.35)x0.125 0.175 Using an overprint or an aperture larger than the land may be necessary to achieve this ratio, and is desirable to provide a larger target for placement. This feature also provides for greater adhesion of the component to the land on the mounting structure prior to reflow. An overprint of 50 µm to 75 µm larger than the land for fine pitch BGAs is recommended. A square aperture with rounded corners will also provide better paste release and volume deposition. 7.1.1.3 Importance of Paste Volume For plastic BGAs much of their solder volume is supplied by the solder ball on the part itself and the paste volume is not all that critical. For plastic BGAs (in both SnPb and lead-free configurations) above 0.80 mm pitch, stencil thickness will be dictated by the other component types used on the printed board assembly. Solder volume and stencil thickness become more critical for ceramic and fine-pitch BGA such as CSP. The solder balls used on ceramic BGAs in SnPb assembly are not tin/lead eutectic and do not collapse during the normal reflow process (see Figure 7-2).
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CBGA Substrate
a)
b)
PBGA Substrate 90/10 Pb/Sn Ball
Eutectic Sn/Pb 62Sn/36Pb/2Ag PWB
PWB IPC-7095b-7-2
Figure 7-2
High lead and eutectic solder ball and joint comparison
For CBGA or other BGA components where thicker solder volume is required, a stepped stencil may be used. The step is typically 0.04 mm to 0.08 mm, and it can put two different paste thicknesses on the board surface. A metal squeegee can be used successfully when the step is 0.04 mm. If a stepped stencil is used, the step line should be at least 3.75 mm away from any print aperture. Because the high lead content ball does not collapse, having sufficient solder paste is critical. The fillet between the land and ball depend upon the solder paste volume. Ceramic BGAs and CGAs require a minimum volume of solder pastes to make a reliable solder joint. There are various suppliers of this type of technology who can provide the specific solder paste volume for their package. Table 7-2 contains the solder paste volume requirements for some of the ceramic packages for tin/lead and lead-free product in ceramic packages. Table 7-2 Solder paste volume requirements for ceramic array packages Volume in µm3 Component
Pitch (mm)
Alloy
Low (min)
High (max)
CBGA
1.27
Tin/Lead
4800
10000
CBGA
1.27
Lead Free
1500
3000
CBGA
1.00
Tin/Lead
2500
4600
CBGA
1.00
Lead Free
1500
2500
CCGA
1.27
Tin Lead
3000
7600
CCGA
1.00
Tin Lead
2000
5000
CuCGA
1.27
Lead Free
3700
4700
CuCGA
1.00
Lead Free
3700
4500
In order to achieve the correct solder volume of solder paste for your ceramic package, it may be necessary to overprint the land with a larger aperture or use a thicker stencil. For other components on a circuit board with CBGAs, the aperture size may need to be adjusted to compensate for the thicker stencil or it may be necessary to step the stencil. Getting into BGA technology also requires some new assembly capability. Depending upon the type of pick and place system, a 7.1.2 Component Placement Impact
change in package carrier mechanism may also be required to transfer packages from matrix tray to the pick position. Fiducials may also be helpful in helping the vision systems recognize the exact location of the land pattern for the BGA, similar to what is used for fine-pitch peripheral leaded parts. Large BGA parts on tape-and-reel will require 44 mm and 56 mm feeders depending on the body size. 7.1.3 Vision Systems for Placement Placement accuracy is a very critical part of the BGA process. It is strongly recommended to not move a BGA after machine placement to correct placement problems as this may cause solder bridging in adjacent solder joints, since the connections cannot be seen visually. The placement machine’s accuracy is largely dependent on the vision system and the ability of the nozzle to hold the component. Matching the vision system to the application is also important. The vision system determines the X, Y and theta offset of each component prior to placement. In addition to determining the component offset, the vision system can also inspect the component for dimensional integrity and missing solder balls. CCD (charge-coupled device) camera-based systems employ two lighting methods, referred to as binary and gray scale. Both methods can be sensitive to contrast and lighting changes.
Gray scale systems use front lighting, which illuminates the component from below. Surface features are reflected into the CCD camera for processing. Binary systems use back lighting, which illuminates the component from above. The outline of the component is projected into the CCD camera for processing. Binary imaging, which is the older of the two methods, locates a feature using the contrast between black and white images. Gray scale systems can usually interpret 256 levels of contrast. Both systems use an algorithm to determine the center of the component. Binary imaging requires less computing capability than gray scale imaging. Gray scale imaging places BGA components based on ball location while binary imaging places BGA components based on the component outline. In some cases the tolerance between the BGA outline and the balls is significant. 73
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Gray scale imaging is more desirable for placing BGA components because it eliminates placement error due to variations in the component outline. Placement machine nozzle designs vary from supplier to supplier. It is important that the correct nozzle is chosen which will have sufficient surface area to hold the part without any shifting during the placement process. The nozzle must gasket against the part, not allowing vacuum leakage. Tactile sensing, which helps control the Z axis (vertical) stroke of the spindle, is desirable because it prevents a component from being crushed between the vacuum nozzle and the substrate. 7.1.4 Reflow Soldering and Profiling Reflow soldering is a complex process with many variables. All mass reflow systems incorporate convective, conductive and radiant means of heat transfer, to what degree depends on the design of the reflow system. All designs strive to achieve the same fundamental results. Five different phases take place during reflow. The five phases are: (1) evaporate solvents from the solder paste, (2) activate the flux and allow fluxing action to occur, (3) preheat the components and printed circuit board, (4) melt the solder and allow proper wetting to occur, and (5) cool the soldered assembly.
It needs to be understood that, regardless of the basic reflow heat transfer concept used, the solder balls underneath a BGA component are primarily heated by conductive heating through the interconnect substrate. The reason for this is illustrated in Figure 7-3. 240ºC 245ºC 220ºC 225ºC
260ºC 230ºC
for LF-solders for Sn/Pb
205ºC 230ºC
217ºC 235ºC IPC-7095b-7-3
Figure 7-3 Example of peak reflow temperatures at various locations at or near a BGA
Over the years, reflow equipment has changed frequently. Four design concepts have been used: vapor phase, lamp infrared (IR), panel IR, and forced gas convection. Vapor phase reflow technology evolved first and was popular for a few years. Eventually, IR became the preferred approach. Today, forced gas convection with I/R assist technology is the method of choice with some applications requiring an inert oven atmosphere. 7.1.4.1 Forced Gas Convection Convection heat is today’s method of choice. Heat is transferred to the printed circuit assembly (PCA) by low velocity heated gas. Forced
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gas convection is a noncontact heating method, with some heating accomplished by radiation. The rate at which heat is transferred to the object is directly proportional to the difference in temperature between the heated gas and the PCA. Inline forced gas convection systems have three main sections: (1) preheat, (2) reflow and (3) cooling. Each section contains a number of top and bottom zones. The number of zones has a direct effect on the transport speed and the user’s ability to fine tune the profile. Adding more zones allows the user to run a faster transport speed and it permits more accurate profiling. Low volume reflow systems have three or four zone sections (a zone section includes top and bottom heaters). Medium volume reflow systems have five or six zone sections, while the higher volume systems use seven or more. Typically, a six zone system will satisfy most reflow requirements, including very large PCAs and reasonably high transport speeds (up to 60 cm per minute). Profile changes are accomplished by adjusting the transport speed and top and bottom temperature settings. 7.1.4.2 Reflow Atmosphere The atmosphere of the reflow furnace will affect solder wetting. Reflowing in a nitrogen environment will result in improved wetting of the solder joint. This will sometimes allow compensation for marginally wettable surfaces on the boards as well as oxidized solder balls. In order to obtain the maximum benefit of the solder paste in a nitrogen environment, it is recommended to monitor the oxygen content and control it within the limits you have established for your process.
With the migration of products into lead-free technology, the wetting of the lead-free solder pastes is not as uniform as with tin lead. It is also possible to use up the activators in the solder paste to clean the oxides off the paste, land, and balls prior to reflow. This would result in a nonuniform shaped solder joint and possibly nonwetting of the land. Some solder paste formulations may also be affected by reflow atmosphere in the formation of voids. When using lead-free processes with OSP surface finishes, it is recommended to reflow the product using nitrogen, and to use an OSP designed for high reflow temperatures seen during lead-free soldering. Reflowing OSP in nitrogen may also preserve the wettability of the lands for downstream processes as well as minimize oxidation of the test points or vias which may have an impact at in-circuit test (ICT). 7.1.4.3 Time/Temperature Profiles The solder profile, also known as thermal profile, is one of the key variables in the manufacturing process that significantly impacts product yield. Conveyor speed and panel temperatures are two variables in solder profile development. The solder profile is not only product specific, it is also flux dependent. Different pastes require different profiles for optimum
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performance, so it is important to consult the paste manufacturer before developing the solder profile. For developing the profile, the loaded board is needed for which the profile is being developed. Start with a given belt speed and monitor the top-side board temperature using thermocouples. Most new reflow ovens have built-in thermocouples and software packages to record the thermal profile. Also, commercial hardware and software packages, such as MOLE, data pack and many others are available to make thermal profile development an easy task. Use of such profilers has been important in tin/lead assemblies. Now it is not only important, but critical, that such profilers be used on each product to achieve good yield without exceeding the temperature constraints imposed by different types of components. Table 7-3 provides key reflow profiles for both tin/lead and lead-free assemblies. Table 7-3 Profile comparison between SnPb and SAC alloys SnPb Alloy
Pb-Free Alloy (SAC)
183°C
217-220°C
210-220°C
235-245°C
Minimum peak reflow temperature**
205°C
230°C
Component ramp up rate
2-4°C/second*
2-4°C/second*
Component ramp down rate
2-6°C/second*
2-6°C/second*
100-180°C*
140-220°C*
Soak or preheat activation time
60-120 seconds*
60-150 seconds*
Dwell time above liquidus
60-90 seconds
60-90 seconds
20 seconds max.
20 seconds max.
Profile Topic
Alloy Solidus temperature Alloy soldering temperature range
Soak or preheat activation temperature
Dwell time at peak temperature
trolytic capacitors, put restrictions on maximum temperature and duration above 230°C to which they can be subjected. Additional constraints will be dictated by low cost laminates, plastic connectors and moisture sensitive components if used. To accommodate such constraints, the peak temperature in lead-free assemblies should be maintained between 230245°C, a variation of only 15°C—a tight process window indeed. This is about a 60% drop from 35°C variation within tin/lead assemblies as mentioned earlier. The difficulty of achieving a reflow profile to meet the defined process window is further increased if large components with high thermal mass are used on the same board with smaller, temperature sensitive components. The reasons are simple. The large components with high thermal mass require a larger heat input to meet the process window requirements for Peak Temperature and time above liquidus. However, this large heat input may result in the smaller, temperature sensitive components falling outside the process window requirements. To resolve this issue, very tight process control and narrow temperature bandwidth across the board is necessary. Many assembly houses may have a hard time meeting such requirements, especially on complex boards without concerted time and effort in developing reflow profiles. The problem can be further compounded by backward compatibility issues where some lead-free components are used on a primarily tin/lead board. In such cases, the profile must accommodate both tin/lead and lead-free package requirements. Figures 7-4 to 7-7 show schematic and actual profiles for tin/lead, lead free, and assemblies with tin/lead and leadfree components.
* Verify with the supplier ** Coolest temperature on the board
With tin/lead, there has been general consensus in the industry about the composition of solder to be used: eutectic solder with 63% tin and 37% lead composition with melting point of 183°C. With this composition, there was a big difference between the melting point (183°C) and peak temperature (220°C). Even though it has been the recommended practice to maintain the temperature all across the board between 210-220°C, one could easily get away by maintaining temperature between 190-225°C, a variation of almost 35°C and still achieve good reflow soldering results. This is about to change. In lead-free assembly, the commonly used SAC (Sn, Ag, and Cu) solders contain 3 to 4% silver, 0.5 to 0.7% copper and the rest tin. These alloys have the melting point around 220°C. A few components, such as some aluminum elec-
Ramp to Peak Profile with no Soak
60-90 SEC
210 to 220°C
183°C Cool Down 4-8°C/Second
100-180°C
90-120 SEC
REFLOW
MAX SLOPE OF 5°C/SEC
SOAK
30-60 SEC for cooling to room temp
PREHEAT COOLING 60-90 SEC
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Figure 7-4 blies
Schematic of reflow profile for tin/lead assem-
In preheat zone the temperature is 30-175°C and component suppliers generally recommend 7.1.4.4 Preheat Zone
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Figure 7-5 An example of tin/lead profile with multiple thermocouples
Ramp to Peak Profile with no Soak
60-90 SEC
235 to 245°C
Figure 7-7 Examples of lead-free profiles with soak (top) and ramp to peak (bottom) with multiple thermocouples. The profiles with soak tend to reduce voids in BGAs.
217°C Cool Down 4-8°C/Second
140-220°C
racy, thermocouple junctions must be welded. No twisting, crimping or soldering should be used.
90-120 SEC MAX SLOPE OF 5°C/SEC
REFLOW SOAK
30-60 SEC for cooling to room temp
PREHEAT COOLING 60-90 SEC
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Figure 7-6 blies
Schematic of reflow profile for lead-free assem-
2-3°C /second ramp rate to avoid thermal shock to sensitive components. Such guidelines are considered conservative since some capacitors are wave soldered where they go from preheat temperature of about 120°C to wave pot temperature of 260°C. The fast ramp rate does increase the potential for solder balls and hence should be kept as low as feasible but it is safe to use 5°C/second ramp rate; however, consideration should be given to the acceptable ramp rate of the most sensitive component on the assembly. 7.1.4.5 Thermocouple Attachment Figure 7-8 shows recommended locations of thermocouples on a board. It is important that thermocouples be attached onto small and large components at the solder joints. For BGAs, it is also important to attach a thermocouple at the top of the package.
In developing any profile, it is very important to use the right thermocouple. Type k thermocouples with wire gauge of 36 AWG should be used. Thicker thermocouple wires add too much heat sink. Thermocouple wire length should not exceed three feet for good accuracy. To ensure accu76
Care should be exercised when using high temperature tapes such as polyimide (kapton) or aluminum tapes. Tapes tend to come loose during reflow and the system measures the temperature of the air in the oven and not the temperature of the solder joints. It is important to make sure that there is good contact of the tape, otherwise, a high temperature solder or thermally conductive adhesive should be used to attach thermocouples to the solder joints. One benefit with using tape is that the thermocouples can be reused repeatedly without damaging them. In the case of BGAs, drill holes in the center and corner balls of the BGA from the bottom of the board and push the thermocouples to the top to correctly measure the temperature of BGA balls. It is important that the difference in temperature of the center and corner balls of the same BGA are within 2°C of each other. There are also some thermocouples that can be inserted under the BGA, eliminating the hole drilling process; however, in this instance, the thermocouples may only be measuring the temperature under the device. Four to six thermocouples should be attached at various component locations to represent the lowest to highest thermal mass areas including at least two thermocouples for BGAs. Figure 7-9 shows locations of thermocouples on a BGA. 7.1.4.6 Soak Zone The soak zone is intended to bring the temperature of the entire board up to a uniform temperature. The ramp rate in this zone is very slow, almost
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Figure 7-8 Locations of thermocouples on a board with large and small components
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Figure 7-9 a BGA
Recommended locations of thermocouples on
flat when raising the temperature from 75-220°C. The soak zone also acts as the flux activation zone for solder paste. The consequences of having too high a temperature in the soak zone are solder balls, solder splatter due to excessive oxidation of paste, and spent flux activation capability. The purpose of long soak zone is to minimize voids, especially in BGAs. It is also common practice not to use soak zone but to steadily ramp the temperature from preheat zone to peak reflow. However, the likelihood of voids may be increased when ramping steadily to peak reflow temperature. 7.1.4.7 Reflow Zone The peak temperature in the reflow zone should be high enough for adequate flux action to obtain good wetting, and create a strong metallurgical bond. However, it should not be so high as to cause component or board damage or discoloration or, in worst case, charring of the board. If the temperature is too low, cold and grainy solder joints, nonmelted solder, or poor intermetallic bonding may result. The peak temperature in this zone should be maintained between 230-245°C for lead free. The time above liquidus (TAL) should be 60 to 90 seconds. Extended duration above the solder melting point or TAL will damage temperature sensitive components. It also results in excessive intermetallic growth which makes the solder joint brittle and reduces solder joint fatigue resistance. 7.1.4.8 Cooling Zone The cooling rate of the solder joint after reflow is also important. The faster the cooling rate, the smaller the grain size of the solder and, therefore, the higher the fatigue resistance of the solder joint. So the cooling rate should be as fast as possible. However, from a practical standpoint, there is not too much control on the
cooling rate other than making sure that the cooling fans at the end of the oven are operational. It is possible to control cooling to some extent by varying fan speeds and adding chillers in the cooling zone. If the fans are nonoperational, the cooling rate will be slow. This will increase grain size causing relatively weaker solder joints. There are some who believe that reducing cooling rate helps in making solder joints less susceptible to pad cratering when dealing with lead free. However, pad cratering is a function of laminate material and the comparatively harder nature of most lead-free solder alloys due to absence of softer lead. Achieving the desired time and temperature and uniformity of temperature across the board in all four zones within 5-10°C should be the two key objectives in developing a reflow profile. Keep adjusting the panel settings and belt speed until these twin objectives are met even if it takes you half a day. The right profile with tight bandwidth is like using a good design for manufacturing (DfM)—they are key to achieving good yield and you have to do them only once. 7.1.4.9 Thermal Profile for Backward Compatibility
Developing a reflow profile is made difficult when dealing with backward compatibility issues where some lead-free components are used on a primarily tin/lead board. Backward compatibility is a scenario where some components are available only with lead-free surface finishes. Such a scenario arises since it may not be economical for many component suppliers to supply both tin/lead and lead-free versions of the same component. It is not an issue when using leaded components such as small outline integrated circuit (SOIC), plastic leaded chip carrier (PLCC) or fine pitch with lead-free surface finishes. Most tin/lead components primarily have 85% tin surface finish with about 15% lead. When component manufacturers eliminated the lead from parts they plated pure tin; however, the solderability suffered. To correct this condition, up to 5% bismuth was added to the plating alloy to improve the wetting or solderability to the part. The real problem arises when using lead-free BGAs on a primarily tin/lead board. If the tin/lead profile with maximum peak temperature of 220°C is used, the lead-free BGA balls will not reflow at all or will partially reflow, creating a serious solder joint reliability problem. If tin/lead components are soldered along with some leadfree BGAs in the same oven (since tin/lead versions were not available), a peak temperature must be used that is not damaging to all the tin/lead components, but is also sufficient to reflow the lead-free BGAs. Using tin/lead solder paste is appropriate, since most of the components on the board are tin/lead. So a peak temperature of 210-220°C will be fine for tin/lead but inadequate for lead-free BGA balls with a melting point of 217-221°C. But a peak temperature of 228-232°C with 45 to 60 seconds time above 77
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liquidus or TAL will be sufficient to reflow lead-free BGAs without seriously damaging all the tin/lead components on the same board. If the tight reflow temperature band of 228-232°C is difficult to achieve in order to solder both tin lead and lead-free BGAs in backward compatibility scenario consider selective laser soldering to solder lead-free BGAs after other tin lead components have been soldered in a convection reflow oven or find an alternative source for BGAs with tin/lead balls. 7.1.4.10 Unique Profile for Each Printed Board Assembly There is some misunderstanding by some people that
one convection oven profile will work for all boards and hence there is no need for developing unique profiles for each board. This is simply not true because each board has a different thermal mass and one may have different loading patterns (distance between boards as they are loaded in the oven). Even the same double sided board, depending upon component placement and distribution of copper planes on each side, may require a different profile for each side. And there is also a misconception that if you do need to change a profile, simply change the belt speed. Having to change only the belt speed is certainly easy, but it may not be the right approach. Changing the belt speed changes the temperature of the board in every zone. Once the desired profile is achieved, run an actual production board with solder paste and components for reflow. After reflow, inspect the quality of the solder joints. A random problem only in a certain section of the board may be related to solderability but a consistent problem in a given section may be related to the solder profile due to nonuniform heating (wide band width). Note too that consistent problems may also be related to paste quality and land pattern design. Once the profile is found to give the desired results (assuming design and other material variables have been optimized), document the profile. After this point, no changes should be allowed in the profile. 7.1.5 Material Issues Flux has two key attributes. First it must remove contamination and, second, it must protect the solderable surfaces after contamination removal. A common mistake is to use a time/temperature profile that consumes the flux before the solder melts. Ideally, the flux would be consumed just as the solder begins to melt. Activation time should range from 90 to 120 seconds. Flux usually becomes active at around 130°C for tin lead solder pastes. Typically, solder paste activation for lead-free solder will be higher, in the 150°C range; however, it is recommended to work with your solder paste supplier for recommendation on that specific solder paste.
Components can be damaged by the incorrect application of heat. All components have a heat exposure limit. Most 78
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tin/lead surface mount components should tolerate a peak temperature of 220°C for up to 60 seconds. Lead-free BGAs will be rated to a higher temperature which is approximately 240-260°C. Thermal shock, caused by the rapid application of heat, can crack certain components. However, since the peak temperature of reflow ovens varies, the intent is to heat the solder in a controlled established profile to a solder joint temperature of 210-220°C for tin lead products and for 235-245°C for lead-free products. Component lead finish will affect solderability. There are a number of lead finishes being used today, including tin/ lead, gold, tin and palladium. It is important to select a flux and solder alloy that works well with the lead finish being used. 7.1.6 Vapor Phase Vapor phase reflow can be operated as a single fluid system or a two fluid system, utilizing a primary and a secondary fluid. The process was developed using the two fluid approach in batch equipment; but modern in-line systems are normally operated with only one fluid. Whichever system is used, the maximum temperature reached by assemblies in vapor phase (VP) reflow depends on the choice of the primary fluid. Primary fluids are available in a number of temperature ranges, with 218-222°C being common with tin lead products and 235-245°C for lead-free products. While all the primary fluids can be classed as perfluorocarbons, the basic structure (amine, cyclic or ether) will determine the key properties of in-use stability, solder paste chemicals solubility and overall process economics. The choice of a fluid is normally based on the melting point of the solder alloy to be reflowed.
For the range cited, the lower temperatures are suitable for the typical tin/lead or tin/lead-silver alloys used for standard attachment processes. The upper end of the range will permit reflow of high lead alloys, which are used to attach pins to PGA packages. Users faced with reflow of a specialty alloy have been successful in mixing two primary fluids to tailor a vapor phase system for a specific stable boiling point. Higher temperatures will permit shorter times, which may be advantageous with some solder pastes. The primary vapor phase should be inert and not introduce contaminants that must be removed later. Solder paste chemicals that dissolve in the fluid are carried in the high boiling vapor then deposited on the surface of the boards. Such residues tend to be difficult to remove. Minimizing solder paste residue in the primary fluid will maximize the lifetime of the fluid, prevent boiling point elevation due to dissolved paste ingredients, and simplify cleaning. The secondary vapor blanket was originally CFC-113, a lower boiling fluorinated material, which formed a low cost sacrificial ‘‘lid’’ over the more costly primary fluid. The constant exposure to the high boiling primary fluid at the
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interface of the two fluids could cause the secondary fluid to undergo thermal decomposition at the interface, generating HCl (hydrochloric) and HF (hydrofluoric) acid vapors. These corrosive vapors often attacked the soldering equipment over time. While in theory the vapors could be absorbed in flux residues and cause problems for high reliability products, this was rare in comparison to the attack on the equipment. With the phase out of CFC-113, a low boiling perfluorocarbon was introduced to replace it. This second generation secondary blanket fluid was more stable than CFC-113 for prolonged exposure to the high boiling vapor phase fluids. As surface mount technology grew, most users converted to the higher throughput in-line machines, which used the single fluid approach. Defluxing after vapor phase reflow should be done with either a bipolar solvent formulation or include an aqueous cleaning formulation that can ensure removal of all the solder paste residues, with the choice of cleaning process based on the composition of the solder paste. Secondary factors influencing the decision would be compatibility, and the component to PWB surface spacing. In addition, most companies gave serious thought to considering the potential chemical loss from using this type of equipment since many perfluoro compounds are very longlived global warming compounds. The selection of the solder paste/flux technology has many implications. The two basic types are materials where the residues require cleaning or can be left on the PCA without causing damage. 7.1.7 Cleaning vs. No-Clean
7.1.7.1 Flux Residues that Require Cleaning (Clean)
Those residues that require cleaning can be separated by the chemicals necessary to remove the residue, typically either solvent/surfactant, basic water, or deionized water cleanable. Selection of a cleaning solvent should follow a careful evaluation of technical, economic, and environmental considerations. In general, cleaning under BGAs is difficult because the tight gap between the board and components may entrap flux which may be difficult to remove during cleaning. Entrapped flux residues that require cleaning are typically highly corrosive so this situation can lead to serious reliability concerns. However, if proper care is taken in selecting the cleaning processes and equipment, and if the soldering and cleaning processes are properly controlled, cleaning under BGAs can be successful. In addition, if no-clean pastes are used, the stencils are required to be cleaned to ensure good printing. It does need to be emphasized, however, that good washer process control is essential when using aggressive water-soluble fluxes. When establishing a cleaning process for water-cleanable solder pastes, it is necessary to verify cleanliness specifically with low profile BGAs or CSPs, and BGA connec-
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tors. It is common to utilize a method such as surface insulation resistance (SIR) to verify that flux residues are completely removed between the BGA balls and to establish your cleanliness process settings. Other methods such as ion chromatography or ionography are recommended to be used to monitor the process after qualification. 7.1.7.2 Flux Residues that Do Not Require Cleaning (NoClean) The use of no-clean fluxes has increased due to
the environmental concerns of using fluxes that require cleaning, the disposal of used solvents and the cost of the cleaning equipment. However, no-clean is not a drop-in process. No-clean fluxes are generally not as active as other types of flux and hence the soldering results may be less than desired unless adequate steps are taken. Some no-clean fluxes require nitrogen reflow environments to produce acceptable results, however most currently available no-clean fluxes can be reflowed in air. No-clean flux residues must be sufficiently inert so that they will not damage the PCB or components. These residues are often mildly ionic and/or acidic and can potentially cause product failure. The possible failure modes caused by those residues include: 1. Corrosion of the PC board. 2. Shorting between metal traces due to dendritic growth. 3. Functional degradation of the ICs due to ionic contamination diffusing into the active junctions of the die. The first two failure modes are surface phenomena. The effects can be detected on the board surface, and the incubation time is relatively short. These failure mechanisms are detected with the surface insulation resistance (SIR) test or the electrochemical migration test (ECM). The third failure mode depends on how long it takes for the external ions, if any, to diffuse through the package encapsulation into the die area. Once these foreign ions reach the silicon die, they may impact its function. The diffusion time is usually on the order of years in a normal operating environment. Typically, some form of acceleration testing, such as SIR or ECM, is required in order to measure this effect within a reasonable test period. In addition, all no-clean fluxes used on a PCA such as solder paste, wave solder flux and even rework fluxes can all remain on the PCA and can become mixed. It is recommended that these fluxes be tested in combination, as well as individually, to understand the complete cleanliness picture. 7.1.8 Package Standoff The package standoff is one of the prime parameters determining the reliability of the BGA solder joints. Package standoff for a BGA is defined as the distance between the land on the bottom of the package substrate and the land on the top of the board surface. This distance varies depending on the type of solder ball: the high lead ball type stays a fairly consistent size; the eutectic solder ball reduces the package standoff height.
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This is also known as ball collapse height. When the BGA is soldered on the board, the balls ‘‘collapse’’ during reflow and reduce the package standoff by 0.25 mm to 0.30 mm from the prereflowed value. The high lead and copper balls do not collapse because they do not melt. The standoff height on lead-free BGAs should be verified during the set up of your process. It is recommended to establish the process to reproduce the standoff height for specific components. Factors that determine the post-reflow BGA package standoff from the board include the BGA package weight, the ball size, the ball material, the land size and land configuration (solder mask defined or nonsolder mask defined). Standoff height decreases with increased package weight. However, for packages with a large ball count, the package weight may have less effect on the standoff height. One study on the relationship between these two parameters discovered that increasing the package weight by 5X decreased the standoff height by only about 0.05 mm for a 615 ball, 1.27 mm ball pitch BGA package. Larger ball sizes will lead to larger package standoff heights due to the larger volume of solder in each ball. Standoff heights are inversely proportional to the land diameters. For nonsolder mask defined (NSMD) lands, a solder mask relief around the land may reduce the standoff height, because the solder will wet out along the conductors as well as along the edges of the land. This is shown in Figure 7-10. Solder Mask Relief Around Land
7.2 Post-SMT Processes 7.2.1 Conformal Coatings Conformal coatings are used to protect the parts from surface moisture and thus corrosion. Conformal coatings should be specified to meet the requirements of IPC-CC-830 and should be specified on the master assembly drawing. When UL requirements are imposed, the coatings shall be approved by UL for use by the printed board manufacturer.
The designer should be cognizant of compatibility issues. Conformal coating is an electrical insulation material which conforms to the shape of the circuit board and its components. It is applied for the purpose of improving surface dielectric properties and protecting them from the effects of a severe environment. Conformal coatings are not required on surfaces or in areas that have no electrical conductors. See IPC-2221, Section 4.5.2. Conformal coatings may be any of five types. The thickness of the conformal coatings shall be as follows for the type specified: • AR – acrylic resin, 0.03 to 0.13 mm • ER – epoxy resin, 0.03 to 0.13 mm • UR – urethane resin, 0.03 to 0.13 mm • SR – silicon resin, 0.05 to 0.21 mm • XY – paraxylylene resin, 0.01 to 0.05 mm There are three primary chemical categories in use for conformal coatings. These are: silicon elastometers, parylene,
~0 mm
0.75 mm
Top view of land illustrating increase of effective land diameter due to trace connections
Cross-sectional view of land with solder ball joint illustrating the solder wetting down the edge of the land when there is solder mask relief away from the land edge
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Figure 7-10
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Effect of having solder mask relief around the BGA lands of the board
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and other organics. All conformal coating types provide various levels of protection from solvents, moisture, corrosion, arcing and other environmental factors that can jeopardize the circuit operation. Conformal coatings may also be used in greater thicknesses as shock and vibration dampening agents. This type of application brings with it the risk of mechanical stress to glass and ceramic-sealed parts during cold temperature excursions. Using this material may require the use of buffer materials. Caution should be taken to prevent underfilling BGAs with coating materials. Testing has shown that complete underfill of coating materials (other than paraxylylene) resulted in early solder joint fatigue failures during thermal cycle testing due to ‘‘Z’’ axis expansion. Conformal coating should not be confused with encapsulants. Encapsulants are used primarily to protect the bare die as a part of the chip component package. Plastic encapsulants provide the protection of the plastic BGA from external sources. The compatibility issues of encapsulants and thermal coatings are very similar. 7.2.2 Use of Underfills and Adhesives BGAs may require the use of adhesives to further strengthen the package to PCB interconnection. In recent years the implementation of lead-free solders and the reduction in pitches has created more fragile package constructions, particularly in the areas of shock and bend. Electronic devices are getting smaller and smaller. Smaller devices tend to be carried more and dropped more which leads to more demanding shock and drop specifications. These factors are driving underfills and structural adhesives to be commonplace with electronics packaging.
Polymeric reinforcement of BGA packages is rapidly moving into many electronics applications. Early adopters of these methods include the markets such as cell phones, MP3 players, PDAs, cameras, medical electronics, avionics and military applications. More recent markets that are using underfills and other epoxies include laptop motherboards and ultra mobile PCs. Desktop motherboards and server boards have resisted implementation of polymeric BGA reinforcement. However, as BGA packages get more fragile, this approach is also a possibility in these markets. Three polymeric approaches for strengthening the BGA to PCB interconnection are popular in the marketplace. These include full capillary flow underfill, partial capillary flow underfill, and corner applied adhesive. No flow underfill technologies are being developed, but High Volume Manufacturing (HVM) adoption of this approach has not yet occurred. Some studies have shown that roughly a 100 to 200% improvement in package performance can be seen in representative packages in shock and bend performance versus packages with no polymeric reinforcement. Polymeric reinforcement of BGA is better than many other
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approaches that have been tried. (larger land sizes, metal defined lands, alternate land shapes, etc). There are no current guidelines as to which BGA packages would require underfill or adhesive reinforcement. The owner of the product design must determine if the product design needs additional mechanical protection for BGA packages to meet marketplace specific reliability requirements (e.g., shock, bend, vibration, drop, temperature cycling, etc.) As would be expected, high performance with these polymeric reinforcement strategies can only be obtained by choosing the right material for the specific application using experimentation. Underfill users should be aware that choosing an underfill chemistry with cured mechanical properties that match the use environment is critical. Underfill chemistries generally increase mechanical performance of packages (shock, bend, vibration, and drop) but if they are not selected properly they can degrade the temperature cycling performance at the same time. 7.2.2.1 Full Underfill and Partial Underfill Full underfill is usually done by applying uncured liquid polymer to the board at the edge of the BGA package and allowing the underfill to flow underneath the BGA package via capillary action. Care must be taken when designing the underfill dispense process to avoid the capture of a large air bubble (void) in the interior of the BGA package. Dispense patterns such as an ‘‘I’’ shaped dispense down one side of the package are much less likely to entrap bubbles than the faster to flow ‘‘L’’ or ‘‘U’’ shaped patterns (down two sides or three sides respectively).
Underfill can be dispensed around packages on boards either with automated equipment (jet dispense or auger pumps or others) or with manual equipment (pneumatic dispense through a syringe and needle). To increase the flow rate of the underfill and the production rate of the manufacturing line, assembled boards are often preheated to between 50°-110°C. Underfill vendors recognize that flow rate drives production rate. More recent generations of underfills are being formulated with lower viscosities and better wetting characteristics that significantly increase flow rates. Newer generation underfills that flow well without preheating of PCBs are also being introduced. Capillary underfill flow time when dispensed using an ‘‘I’’ pattern can be approximated with the following equation: See Figure 7-11. T = (3µL2)/(hγ cos Θ) where, T = for underfill to flow across the package in seconds µ = underfill viscosity L = distance for underfill to flow h = gap between parallel surfaces Θ = wetting angle of fluid to surfaces γ = surface tension of underfill. 81
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approach. Batch ovens may also be used. Underfill vendors have been introducing new formulations that cure at lower temperatures over less time.
L µ,γ
θ
h IPC-7095b-7-11
Figure 7-11 faces
Flow of underfill between two parallel sur-
Voids in underfill are common, especially at the intersection of the solder ball and the PCB and the solder ball and the package substrate. General consensus is that small voids in the bulk underfill have no significant effect on performance in shock, bend, or temperature cycling. There is no industry standard for allowable voids in underfill. However, most underfill users recognize that any voids in the underfill that connect adjacent solder are risky. (Solder has been shown to creep through voids and short adjacent solder balls in temperature cycling.) Moderate sized voids (i.e., getting larger than half of the diameter of a solder ball) are a grey area in terms of industry acceptance. Anecdotal evidence says that these moderate sized voids do not have significant adverse effects but some underfill users would like to eliminate them from occurring in their process. Figure 7-12 shows examples of small halo voids, medium sized voids and large voids, respectively.
Historically, underfill epoxies have not been practically reworkable in an HVM environment. This was more acceptable initially in devices such as early generation cell phones where the cost of each board was relatively low and scrapping a few boards was not a significant cost penalty. However, underfill is penetrating more and more high value markets. As a result, underfill vendors are developing chemistries that are more reworkable in HVM. Partial or corner only underfill is done by dispensing underfill in dot or ‘‘L’’ shaped patterns near the corner of BGA packages. The underfill flows into a roughly arc shaped pattern and envelops several solder balls deep at each corner (see Figure 7-13).
Proper fillet height is desirable for maximum underfill performance. The presence of a fillet that extends between 25% and 100% of the way up the side of the package near its midpoint is considered acceptable in most applications. Keepout zones for other devices and open vias are required around the periphery of the BGA being underfilled. A conservative rule for keep outs is 1.5X the height of the top of the substrate of the BGA package from the PCB surface on the nondispense sides of the package and 6.0 mm on the dispense side of the BGA package. Underfills packages are cured in ovens. One desirable method for curing these boards is using a single pass through a standard SMT oven run at a lower than reflow temperature. Many underfill chemistries can be cured in 5-20 minutes at 120-165°C which may be conducive to this
Figure 7-12
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Figure 7-13 Example of partial underfill - package was pulled from the PCB and dark underfill can be seen in the corners
This method has the advantage over full underfill in that much less underfill material can be used, and also that underfill flow time can be greatly reduced which can help increase the production rate associated with the dispense step. As expected partial or corner only underfill does not have quite the strength improvement of fully underfilled packages; however, in many situations the performance improvement gained with partial underfill is more than
Examples of underfill voids - small, medium and large; upper left, lower left and left of solder balls, respectively
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enough to meet the market requirements for the package/ board being protected. (An experimental case showed a 1.5X increase in shock level where the onset of mechanical damage was sustained for a partial corner underfill BGA versus the same nonfilled BGA. This is very significant.) Some manufacturers of mobile PC motherboards have used partial underfill to increase the strength of the BGAs on their boards. 7.2.2.2 Corner Applied Adhesive Corner applied adhesive (sometime called corner glue, corner bond or corner tack) is a method for applying glue only to the corner and/or outer edges of a BGA package. The theory is that by reenforcing the area of the package that is under the most stress, the solder balls farthest from the center of the package, package performance can be improved. Corner applied adhesives do not improve package performance as much as conventional full capillary flow underfill but often the advantage gained is significant and enough to meet market requirements. The corner glue approach has been widely adopted by markets that require high mechanical requirements (shock, vibration, and bend) on large BGA packages (20 x 20 mm to 45 x 45 mm). The mobile PC motherboard market matches this description.
A photograph of a BGA package mounted with corner glue is shown in Figure 7-14.
Figure 7-14
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Figure 7-15 Critical dimension for application of prereflow corner glue
The effectiveness of corner glue post assembly and reflow methods depends on the type of glue chosen and the total surface area contacted at each corner. Dispensed amounts vary from essentially single glue dots at each corner to ‘‘L’’ shaped brackets of glue that extend down the side of the package by up to six solder balls on each side of the corner. Studies show that the longer ‘‘L’’ shaped dispensed brackets can significantly improve mechanical reliability (i.e., one study showed an improvement in shock performance where the acceleration level caused the onset of mechanical damage to occur, increasing from 180 G to 300 G). A good starting point for the amount of glue that should be applied at each corner is that each leg of the ‘‘L’’ shaped bracket should extend somewhere between 3 and 6 solder balls deep. One pitfall of corner glue is using too little glue in terms of the surface covered. Testing has shown that a single dot of glue that covers no more that the width of one solder ball down the side of the substrate does not significantly increase the shock or bend performance of a BGA. This is because typically the strength of the solder mask to underlying FR-4 or the strength of the BGA substrate is low and these constructions crack very easily if the surface area of the corner glue is too low (see Figure 7-16).
Corner applied adhesive
Corner glue can be applied either directly to the PCB prior to BGA package placement and reflow or to the assembled BGA package after reflow. Corner glue prior to reflow requires that the BGA package have sufficient substrate available outside of the edge of the last solder ball in the outermost rows (see Figure 7-15). The minimum width of available substrate where corner glue can be applied is approximately 0.7 mm. With packages with less than this amount of substrate available this process is not controllable in HVM. Current trends are that package substrate sizes are shrinking and the use of prereflow applied corner glue is expected to drop off.
Figure 7-16 Typical corner glue failure mode in shock if glue area is too low - Solder mask rips off board and does not protect the solder joints
Other guidelines are that the glue should wet on average at least 50% up the vertical side of the substrate throughout the entire dispense line and that the epoxy material should 83
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be forced to flow to some degree underneath the BGA package, even if the epoxy flows in deeply enough to contact some of the solder balls. Typical dispense equipment for post-reflow corner glue includes a pneumatic source that supplies air to a syringe and needle set up. This equipment is low cost and conducive to being set up in manufacturing environments where labor rates are fairly low compared to available capital. Corner glues are epoxies similar to underfills. Typical cure cycles include 5-60 minutes at 60-180°C. Some UV light curable versions of these materials are also being introduced. 7.2.3 Depaneling of Boards and Modules The method for depanelization can be achieved using a number of different techniques. These include simple scoring, a combination of routing and scoring, and a combination of routing plus breakaway tabs. See IPC-2222.
Scoring is the machining of a shallow, precise V-groove into the top and bottom surfaces of the laminate. As scoring allows the removal of rails and individual parts from a pallet, positional accuracy is critical. Routing defines the final assembly periphery. The routing channels are produced using router bits of different diameters, leaving breakaway tabs to hold the board in place during assembly. Extreme care should be taken when break away tabs are removed. Avoid bending the board, especially near BGA components. Bending may cause BGA solder joints to crack, typically starting with the corner balls. Custom tools should be fabricated, or machines designed for break away tab removal should be purchased. These tools or machines should reduce or eliminate stress near BGA components during break away tab removal. 7.3 Inspection Techniques The following paragraphs are inspection techniques that may be applied at different Table 7-4
times during the development of the BGA assembly process or as an auditing mechanism during production. Table 7-4 provides some recommendations as to applicability of the inspection method. 7.3.1 X-Ray Usage X-ray inspection is generally used when there is a high proportion of hidden solder joints that are not visually accessible, and when there are a significant number of untestable solder joints. Examples of untestable solder joints are redundant connections, and back-to-back BGAs where the fanout vias are inaccessible and space does not allow for additional test points. X-ray methods can complement the test process chosen, and can provide faster feedback to the manufacturing line. Depending on the capability of the X-ray system being used, X-ray is capable of detecting solder related defects such as bridging, open solder joints, insufficient solder, and excessive solder volume. Other defect types such as missing balls, misregistration, and package popcorning can also be identified. In addition to defect detection, X-ray can be used to provide trend analysis for solder volume and solder joint shape. X-ray is the only nondestructive method of finding voids in BGA joints.
Figure 7-17 shows the principles of X-ray equipment being used with the X-ray to be above the sample; some equipments have the tube below or at an angle to the specimen. The general characteristics provided in the figure apply to most X-ray systems. X-ray inspection has become a generally accepted tool for solder joint evaluation and analysis, and as a monitor for the reflow process. X-ray inspection techniques can be employed most effectively through the understanding of principles of X-ray image acquisition. X-ray can be effective in confirming solder bond integrity of BGAs and as a monitor for the reflow process. X-ray inspection techniques can be employed most effectively through the understanding of:
Inspection usage application recommendations NPI or Low Volume Production
Process Development
In-Line Production
Failure Analysis
Process Auditing
Optical Inspection
Excellent
Good
Excellent
Good
Good
Manual X-ray
Excellent
Good
Excellent
Good
Excellent
Automated Transmission X-Ray
Excellent
Excellent
Good
Good
Good
Automated Cross Section X-Ray
Excellent
Excellent
Excellent
Good
Good
Scanning Acoustic Microscopy
Excellent
Fair
Good
Good
Fair
Fair
Fair
Good
Good
Fair
Solder paste volume
Part identification, solder paste volume
Not Applicable
Part identification, solder paste volume
Part identification, solder paste volume
Good
Poor
Excellent
Fair
Fair
Method
Stand Off Measurement Automatic Optical Inspection Destructive Analysis
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Figure 7-17
Fundamentals of X-ray technology
• Principles of X-ray image acquisition • Analysis of the X-ray image (in the light of the reflow process) Use of X-ray requires some caution regarding overexposure on vulnerable materials or components. Figures 7-18 and 7-19 show the characteristics of X-ray images for both voids at the interface, or missing solder balls in the BGA attachment.
Figure 7-19 tacts
X-ray example of voiding in solder ball con-
can then be viewed on video film viewers for high magnification examination of details. The process is slow but can yield X-ray images of great detail and tonal accuracy.
Figure 7-18
X-ray example of missing solder balls
7.3.2 X-Ray Image Acquisition
Film Based X-Ray Inspection – Film based X-ray inspection systems employ an industrial X-ray cabinet and X-ray film packets to record the X-ray image on film. The film
Real Time X-Ray Systems – Real Time X-ray inspection systems utilize an X-ray source and a detector system which converts the invisible X-ray image into a video display signal. These systems provide immediate imaging results of samples. The images produced from these systems should not be distorted or include false artifacts induced by the X-ray system itself. Figure 7-20 illustrates a comparable level of image quality that should be expected from a manual X-ray inspection system. Figure 7-21 illustrates examples of pin-cushion distortion and 85
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voltage blooming. Real time systems are available in a broad range of sizes from small desktop systems to large console floor models. They are also available with a broad range of X-ray source voltages. There is not a specific voltage needed to inspect BGAs. The voltage required will, in part, depend on the sensitivity of the particular X-ray system employed, as well as the structure and characteristics of the BGA under inspection. BGAs with copper heat sinks for example, will require higher penetrating voltage settings than PBGAs or CBGAs. BGAs with aluminum heat sinks, on the other hand, do not require the higher voltages since aluminum is a less dense material and is therefore much more transparent to X-rays than copper.
Figure 7-21 Example of X-ray pin cushion distortion and voltage blooming
The following definitions for Transmission, Cross-section and Combo Automatic X-ray Inspection apply:
Figure 7-20
Manual X-ray system image quality
Transmission X-ray automatically generates images of all features of the sample between the X-ray source and the detector. Figures 7-22 through 7-24 show examples of transmission, tomosynthesis, and laminographic X-ray images.
7.3.3 Definition and Discussion of X-Ray System Terminology X-ray inspection systems are available in both
manual (MXI) and automated (AXI) configurations. MXI systems can have varying degrees of automation which can include automatic BGA analysis, automatic image processing functions, automated manipulation and board handling. Another feature available with transmission target X-ray systems is high magnification using an oblique view (see 7.3.3.2). What generally distinguishes AXI systems from MXI systems is that AXI systems are in-line capable and do not require an operator to make pass/fail decisions. MXI equipment is almost exclusively transmission X-ray technology, whereas AXI equipment can be transmission, cross-section and combination. AXI equipment is generally available in three forms: • Transmission AX – commonly referred to as 2D X-ray • Cross-Section AX – commonly referred to as 3D X-ray • Combination 2D/3D AXI 86
Figure 7-22
Transmission image (2D)
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technique captures specific slice information, these techniques have both unique & common capabilities to detect some types of solder defects. All of transmission, crosssection and combo X-ray techniques are capable of detecting PCB assembly defects that cause changes in the solder joint profile. These types of assembly defects include but are not limited to: solder shorts, solder opens, insufficient solder joints, missing devices, skewed devices, and solder voids.
Figure 7-23
Tomosynthesis image (3D)
7.3.3.1 Transmission X-Ray Technology In transmission X-ray, the X-ray source and detector can be fixed or movable in a variety of motions for variations in magnification and angle of view. Generally, all features in the vertical ‘‘line of sight’’ are viewed concurrently without distinguishing depth.
Differences in material thickness or density will result in different transmitted X-ray attenuation at the detector resulting in brighter or darker intensities within the image display. For a single material type, such as eutectic solder, the attenuation of the X-ray photons received at the detector is proportional to the material thickness. A gray scale image is created which can be interpreted to determine whether or not solder joints are acceptable. Figure 7-25 shows a transmission inspection illustration.
Figure 7-24
Laminographic cross-section image (3D)
Cross-section AXI automatically generates images of one slice of the board at a time. Laminography and tomosynthesis are the most common forms of cross-section AXI. Combo AXI equipment uses a combination of transmission and cross-section techniques concurrently during the inspection of a PCB. Combo systems automatically apply each technique where it is best suited and allow users the ability to prefer one technique to another if desired. On assemblies with components on both sides (Type 2), some subset of the solder joints will be inaccessible to the standard transmission X-ray technique due to overlap, unless an oblique viewing method is utilized.
X-Ray Technology There are two basic methods of oblique viewing of objects with transmission X-ray systems. One method consists of tilting the sample in order to get the oblique angle as illustrated in Figure 7-26. Although this method enables the oblique view, the technique may not allow for the highest achievable level of magnification to be realized.
The cross-section technique on the other hand, will have greater test access where oblique viewing is not utilized. Since the transmission X-ray technique captures information from the entire solder volume, and the cross-section
Another method of oblique viewing utilizes a wide angle transmission X-ray source as illustrated in Figure 7-27. In this method, the detector rotates around the center axis of the X-ray source, utilizing the peripheral portion of the
Figure 7-25
Transmission example
7.3.3.2 Oblique Viewing Inspections with Transmission
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Oblique Viewing with Board Tilt
FBGA Solder Joints
1
2
3
4
5
6
Top Down View
Tilted View
Board with FBGA
High magnification is required, but loss of magnification occurs through object tilt. (Due to longer source to object distance.)
Detector
Top down view of FBGA solder joints
FBGA Solder Joints IPC-7095b-7-28
Figure 7-26
Figure 7-28
1
2
3
4
5
6
Oblique View
Oblique viewing board tilt
cone of radiation to produce an oblique view with the highest achievable magnification.
Oblique View without Compromising Available Magnification
Three solder joints are clearly open (No. 2,3,4). The void (No.1) is located near the component pad. The solder joint above right (No.6) is in contact to the board but with insufficient wetting (no meniscus).
Oblique View Figure 7-29
High magnification is required and maintained by rotating the detector through the cone of radiation while keeping it perpendicular to the center of the x-ray source. (Due to shorter source to object distance.)
Board with FBGA
Detector IPC-7095b-7-27
Figure 7-27
Oblique viewing detector tilt
Figures 7-28 and 7-29 illustrate the benefits of oblique viewing at high magnification with actual images of a FBGA comparing a top down transmission view with an oblique view. The images in Figure 7-29 will be slightly different in texture and darkness for a lead-free application. The tube intensity and/or power may need to be slightly reduced in order to avoid overexposure. 7.3.3.3 Cross-Sectional X-Ray Technologies On double sided boards, some subset of the solder joints will be inaccessible to the transmission X-ray technique due to overlap, whereas the cross-section technique will have greater
88
Oblique view of FBGA solder joints
test access. Because the transmission X-ray technique captures information from the entire solder volume and the cross-section technique captures specific ‘‘slice’’ information, these techniques have both unique and common capabilities to detect some types of solder defects. For more detailed information, contact the manufacturers of AXI systems who can provide information about the capabilities of their techniques and systems. Both tomosynthesis, Figure 7-30, and laminography, Figure 7-31, are radiographic techniques that provide image ‘‘slices’’ of the device that can be viewed. With laminography, the X-ray source and the X-ray image plane are moved in a coordinated way with respect to the electronic device being inspected. A clear image of only one layer or ‘‘slice’’ of the device appears; all other layers in the image plane are blurred out. Tomosynthesis collects several transmission X-ray images from different angles during the inspection and combines the digital data of those images mathematically. This enables virtual slices to be created at the desired plane for analysis. 7.3.4 Analysis of the X-Ray Image An understanding of the construction of the particular BGA device and of the reflow process will aid in the interpretation and analysis of
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Figure 7-30
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Tomosynthesis
Rotating X-ray Beam A
Focal Plane
A
Rotating X-ray Detector
A
A
A
A
Result
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Figure 7-31
Scanned beam X-ray laminography
the X-ray image of the ball bonds. The concurrent factors that should be considered for X-ray image analysis might include: • Determine if the balls are collapsible (eutectic) or noncollapsible (noneutectic). • Define if noncollapsible balls have been placed in the corners to retain coplanarity. • Was reflow temperature maintained sufficiently to permit full alignment and collapse? • Does BGA package appear to have physically deformed in some way during reflow? These factors will add further insight into the interpretation and analysis of the X-ray image. 7.3.4.1 Field of View In determining the criteria for inspections it is also important to determine how much can be seen of the BGA at any one time. As the pitch of the BGA gets smaller, the ball size is also reduced. Several magnification levels can be applied to the evaluation. Table 7-5 provides the different pitch and ball size characteristics applicable to any field of view. The magnification range
varies, however should be between 30X and 50X. Depending on the ball size, the field of view can be determined by simply dividing the number 15 by the ball size. Thus, 15 divided by 0.75 (for the 0.75 mm ball) results in being able to see 20 balls of that size for evaluation. As the ball size decreases, a greater number of ball images are viewed for quality evaluations. The display of the field of view from a real-time x-ray system depends on the number of pixels available from the x-ray detector and how this is displayed on the operator screen. This can vary from 640 x 480 pixels to 1600 x 1200 pixels, or more, in commercially available x-ray systems. As one of the quality measurements that is used in this document is voiding, unless a minimum number of pixels is suggested for the diameter of the solder balls when under inspection, then the precision of any subsequent measurements will be severely compromised. For example, assume a 4 x 4 array of 0.75 mm diameter balls (pitch 1.5 mm) and a 7 x 7 array of 0.30 mm diameter balls (pitch 0.5 mm) are shown fully on screen (similar to that shown in the table). On an X-ray system with a 640 x 480 pixel detector 89
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Field of view for inspection Magnification Recommendation
Nominal Ball Diameter (mm)
Pitch (mm)
0.75
1.5, 1.27
15/0.75 = 20 Balls
0.60
1.0
15/0.60 = 25 Balls
0.50
1.0, 0.8
0.45
1.0, 0.8, 0.75
15/0.50 = 30 Balls 15/0.45 = 34 Balls
0.40
0.80, 0.75, 0.65
15/0.40 = 38 Balls
0.30
0.8, 0.75, 0.65, 0.50
15/0.30 = 50 Balls
(assuming 1:1 presentation on the display), then for the shortest screen axis, each type of BGA ball will be 68 and 44 pixels in diameter respectively. With an error of linear measurement of 2 pixels (one at either edge), for example, each BGA has an error of 2/68 and 2/44, or 3% and 4.5% respectively. Should these values then be used to calculate the area of the balls for the crucial void percentage calculation, then the error in the area will be 9% and 20% respectively. In contrast, the values for an x-ray system with a 1600 x 1200 detector would be 171 and 109 pixels with a linear error of 1.2% and 1.8% and an area error of 1.5% and 3.25% respectively. For Class 3 products, a maximum of 4% voiding by area is proposed. In the worst case above (but as devices continue to shrink then the lower spec X-ray systems will progressively worsen) the minimum action level through system measurement will have to be nearer 3%, and this is before any other errors in X-ray measurement are taken into account (from grayscale sensitivity variation, geometric magnification effects, etc.) and lowers the action level still further. 7.3.5 Scanning Acoustic Microscopy Scanning acoustic microscopy (SAM), also called scanning acoustic tomography (SAT), is a nondestructive failure analysis tool. It uses sound waves to scan the internal layers of an assembly. It is commonly used in the semiconductor packaging field to detect delamination or voids located inside an electronic assembly. It can locate delamination or voids inside a BGA package. It can also locate similar anomalies in underfill after the BGA has been attached to the substrate.
The resolution of delamination or void detection depends on the acoustic frequency used for analysis. Resolution increases with increasing frequency. A 230 MHz transducer can bring detection resolution down to around a 25 µm gap. A single point observation is called a SAM, a line scan is called a b-SAM, and an area scan is called a c-SAM. The c-SAM image in Figure 7-32 shows the location of voids in underfill in a flip chip assembly. The sample being inspected needs to be in water during the SAM analysis. Voids or delaminations that are open to water ingress cannot be detected with this method. 7.3.6 BGA Standoff Measurement Feeler gauges provide a nondestructive method of determining the approximate finished standoff of the BGA after reflow. Feeler
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30X - 50X
Field of View
gauges can be used at each corner after reflow and the combined results can be used to determine an average standoff measurement. This method is not as accurate as cross-sectioning, but it is much less expensive and nondestructive provided that the operator does not attempt to force a feeler gauge under the device. Doing so could result in breaking solder joints. It does require adequate space around the BGA for the feeler gauges to be inserted. The standoff height of a BGA can give some indication that the solder balls reflowed completely and uniformly. The standoff of a typical PBGA with a 0.75 mm ball is approximately 0.60 mm prior to reflow and drops to 0.45 mm (including solder paste) after reflow. Other BGA packages have their own stand-off height characteristics based on the ball size, alloy used, and whether the BGA contains a metal heat spreader. Since each package has its own stand-off characteristics, users should develop a part assembly profile in order to make the use of feeler gauges applicable. 7.3.7 Optical Inspection Endoscopy is an optical inspection method that permits visual inspection of tiny objects in a small, confined area. This technology has been adapted and applied to BGA solder joint inspection. BGA solder joints can be inspected and analyzed for a variety of critical factors such as:
• Overall Solder Joint Quality – evidence of proper wetting • Solder Joint Shape – evidence of proper reflow • Solder Joint Surface Texture – smooth vs. irregular • Overall Solder Joint Appearance – flux residue, etc. • Solder Joint Defects – solder shorts, opens, cold solder • Missing balls This technology is best suited for inspecting exterior row BGA solder joints as shown in Figure 7-33. A limitation of this technology is the inability to view interior rows with the same level of quality and clarity. It is sometimes possible to focus on interior solder joints but not at the same level of detail as the exterior rows. It is usually not possible to see paste on the second or third row of balls. The analogy would be the inability to see trees in the center of a forest from the outside. Lens design is a distinguishing feature of this technology. The highly advanced lenses are able to focus and redirect
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Reflected Pulse
Input Pulse T Sample
T - Transducer - Ultrasound - Application Zone
Fluid IPC-7095b-7-32
Figure 7-32
Scanning acoustic microscopy
Figure 7-33
Endoscope example
an image 90° using a mirror or prism. A high-resolution CCD camera and monitor are used to capture and display the image. Magnification, depending on working distance, ranges from 50x to 200x (see Figures 7-34 and 7-35).
Figure 7-34 Lead-free 1.27 mm pitch BGA reflowed in nitrogen and washed between SMT passes
Lighting is a critical factor. The image quality will be poor if the light source does not properly illuminate the solder joint being inspected. Front lighting permits frontal inspection of a solder joint while back lighting is useful for detecting solder shorts and other obstructions. Back lighting also displays the solder joint outline which makes it easy to view the overall shape.
Analytical software is also desirable. In addition to displaying a real time image of the solder joint it is useful to have features such as image capture and measurement. Some systems provide reference photographs of acceptable and unacceptable solder joints. These images can be compared simultaneously with the image being evaluated, which reduces subjectivity during inspection.
A robust positioning system that provides adequate support and protection for the lens and CCD camera is essential. It must eliminate motion due to shock and vibration and it must be adjustable through the desired range of motion.
7.3.7.1 Protocols for BGA Assembly Reliability and mechanical strength of SMT joints are very important, especially in high reliability applications. Voids and other defects may hurt thermal cycle reliability; however, there is
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study. One analysis compared void content of several styles of early-fail BGAs vs. void content of equivalent later-fail BGAs. No correlation was found. Early and late failures had the same void content. Note that all this BGA data involved ‘‘all-ball nets.’’ No data exists to statistically link ‘‘first-fail joint’’ of a BGA to its life. Therefore there is no numerical correlation of life vs. void percentage. No data was taken that would be good enough to establish trends within the 5-10 accuracy that might be useful. At this time, there is no new data that would establish a numerical link (voids vs. life) for any/all of the component types, under any/all conditions. Some information suggests that normal voids variations are: • For in-process control, use >35% area percent as the threshold with a >50% void diameter threshold. Figure 7-35 Lead-free BGA reflowed in air and washed between SMT passes
some evidence that indicates voids could help reliability. Voids probably impact mechanical strength. Voids in solder joints are common and unavoidable at low levels. Voids in BGAs are very difficult to characterize quantitatively, nondestructively. X-ray is the only practical solution, but it’s tricky! Void quality protocols must apply to all assembly situations. Rework, even when ‘‘required,’’ can make matters worse. In-process and lot-acceptance protocols must be developed. Out-sourcing/extended supply-chains pose additional challenges. Several early studies document the inevitable occurrence of voids. Testing included some void characterization of conventional SMT joints, as well as an objective to link abnormal failures to abnormal causes, (e.g., extreme voids). Most SMT joints have voids (under foot, plus inside/toe/ heel fillets). The majority are between 5 to 20 area percent voids with a small amount at 0% or around 25%. Early-fail SMT joints do not have more voids than later-fail joints. This is based on hundreds of comparisons of symmetrical parts: the ‘‘first-fail’’ joint does not have a larger area percent void than the ‘‘last-fail’’ joint. Strong data shows that variations in normal levels of voids are not linked to thermal cycle life. Methods (x-ray and fracture plane visuals) are approximately equivalent but both are very limited, difficult, or subjective. Typical BGA solder joints average ~10 area percent, with some averages as low as 5% and others in the 15% range. Within the BGA the joints had different area percent voids ranging from 0% to 35%. No abnormal voiding, and no striking trend or anecdote linking voids and thermal cycle life was encountered in this 92
• For reject/rework, use >45% area percent as the criteria with a >65% void diameter threshold. 7.3.7.2 Cracked Peripheral Interconnect Determinations In addition to simply viewing solder joints, this
technique can be used to identify cracked peripheral interconnects (solder joints). Using a torque limited screwdriver, an engineer can apply a small force which will separate fractured surfaces. This technique enables an engineer to determine, in a nondestructive manner, whether there is an open connection as shown in Figure 7-36. The engineer can also determine if the open is due to a lifted land, interfacial fracture or bulk solder failure. This technique does not work on some substrates, typically those of low thickness laminates which produce a more flexible component substrate (interposer). If the nondestructive measures used to identify a malfunction do not succeed in eliciting the cause of failure, then destructive analysis techniques may be used. Such techniques will render the analyzed assembly unusable. Once the cause of the failure has been identified the information can be used to implement corrective actions to eliminate the problem. 7.3.8 Destructive Analysis Methods
7.3.8.1 Cross-Sectioning If nondestructive methods fail to identify the cause of an anomaly, it may be necessary to use destructive methods to isolate the problem area. One such method is cross-sectioning, which looks at a section of the components, substrate and solder joints after cutting it apart.
The first step in cross-sectioning is to identify or make a best guess regarding the area that needs to be examined. If more than one area is suspect then it needs to be determined whether those areas can be accessed sequentially on the same component. If not, then the areas will need to be prioritized according to the possibility of finding the problem or more than one component will need to be analyzed.
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Torque Screwdriver set at ~ 0.02 Nm
Side View
A
BGA
End View
B
A ~ 0.03 mm minimum gap
B IPC-7095b-7-36
Figure 7-36
Engineering crack evaluation technique
Next, if the problem area is a part of a larger assembly, it may need to be isolated into a small more manageable portion by cutting it out of the larger assembly. Care should be taken to ensure that the evidence is not tampered with or destroyed during the cutting process. For proper sectioning, the sample should be molded in resin to alleviate chipping or destruction of the sample during cross-sectioning (see Figures 7-37 and 7-38). If fine polishing of the area of interest is going to be required, then the sample should be sectioned a reasonable distance away from the interface of interest leaving sufficient distance for fine polishing of the interface. In some cases, the entire component may need to be ground through and looked at for the integrity of various interfaces. A common failure analyzed through crosssectioning is an open occurring in an assembly. Such opens may occur at the solder interface.
Figure 7-38 Cross-section of a crack initiation at the ball/ pad interface
delamination. The sample is immersed in a low viscosity liquid dye which penetrates any cracks, delaminated areas, or open voids. The sample can then be peeled away and examined for the presence of dye in the solder joints or at material interfaces. If a fluorescent dye is used, the sample is inspected under UV light. The dye enhances the visibility of flaws that might otherwise be difficult to detect. The presence of dye on a solder land indicates poor wetting to the land, and can be used to estimate the portion of the land that was not wetted; however, very thin cracks may be so small that liquids cannot completely enter because the surface tension of the liquid will not allow it (see Figures 7-39 and 7-40). 7.4 Testing and Product Verification
Figure 7-37 A solder ball cross sectioned through a void in the solder ball
Dye penetrant methods can be used during process set-up and in failure analysis to detect solder joint cracking and wetting problems, and package 7.3.8.2 Dye Penetrant
7.4.1 Electrical Testing Electrical testing is used to evaluate the functionality of the electronic assembly. There are two commonly used electrical test approaches: in-circuit test (ICT) and functional test (FT).
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higher temperatures on lead-free solder pastes, there may be an increase in oxidized test lands or test vias. Typically, with tin/lead alloys you may print and reflow solder pastes to provide a soldered test point for the ICT probes. Leadfree solder pastes do not wet as well and may cause issues with ICT. It is recommended to run a quick experiment during the development stage of the process to understand the impact of lead-free solder pastes on this process. 7.4.2 Test Coverage Given the current complexity in electronic assemblies, the level of ‘‘coverage’’ of test has become an industry issue. The more complex a board or assembly, the more difficult it is to fully test. Indeed, it may be difficult to test even a reasonable portion of the assembly in a reasonable, i.e., cost effective, period of time. Figure 7-39
No dye penetration under the ball
While test of an assembly may be aided by incorporating test into the silicon devices, this strategy is not applicable to bare boards. Thus the challenge of test is to provide test coverage at a high level of confidence within a reasonable period of time. An effective process monitoring system consists of overlapping tools that create a large bandwidth of coverage. Multiple tools and methods are required since there is not one single tool or method that provides the desired coverage. Optical inspection, X-ray, SAM, ICT and FT are examples of overlapping coverage. These verification methods should be used to monitor products and process; they should not be used solely to screen and separate good and bad product.
Figure 7-40 Corner balls have 80-100% dye penetration which indicate a crack
ICT utilizes a dedicated bed-of-nails fixture to probe the completed assembly. This test method is used to detect faults caused by the manufacturing process and also to isolate the majority of nonfunctional components. The faults found by ICT include solder bridge, solder open, component mis-orientation, wrong component, component not functional and conductor short. Another approach is to place a low cost in-circuit tester near the end of the assembly line and use it as a manufacturing defect analyzer (MDA). Boards are tested immediately after the components are placed and soldered. Problems are quickly relayed back to manufacturing so corrective action can take place while the product is being assembled. ICT can be supplemented by a complete functional test at the end of assembly. This test for product functionality can, depending on type of product and the acceptability requirements, be as simple as a ‘‘go/no-go’’ test or as complex as a complete exercising of all circuit functionality. FT is used to detect device faults on the assembly at speed. With the 94
7.4.3 Burn-In Testing Burn-in is an operational and environmental test of the complete assembly at the upper limits of the application. This test typically finds more component related problems than solder joint defects. The use of burn-in testing is still in use for component evaluation. Burn-in on electronic assembly is decreasing in favor of some form of accelerated test exposure to screen out marginal results. 7.4.4 Product Screening Tests Environmental stress screening (ESS) is used to screen ongoing production for poor product quality and latent defects. The purpose of ESS is to accelerate the latent defects to actual failures, thus eliminating these latent defects from causing failures in the field. Care must be taken that the ESS procedures are not sufficiently severe to damage good product and produce new latent defects. Solder fatigue life on BGAs shall be evaluated on the thermal cycling of these ESS tests, other tests, and the operating life thermal environments. 7.5 Assembly Process Control Criteria for Plastic BGAs The degree of voids permitted in the BGA assembly attachment process and the impact on reliability is of interest to members of the electronics industry. The
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detailed requirements for end product acceptance shall be in accordance with J-STD-001; workmanship requirements shall follow the requirements of IPC-A-610. This section establishes the practicable process development and maintenance criteria as well as attempting to address the issues related to an acceptable assembly process. The majority of the recommendations are based on the use of plastic BGAs with the eutectic solder balls as the input/output termination. Current industry data suggests that voids in the solder joint are not a reliability concern. In fact, the appearance of a void after assembly reflow is an indicator that the reflow process has taken place and the BGA ball has changed characteristics. However, a change in void size or frequency of voids may be an indication that the manufacturing parameters need to be adjusted. Two reported causes of voids are trapped flux that has not had enough time to be released from the solder paste, and contaminants on improperly cleaned circuit boards. Voids appear as a lighter area inside the solder balls and are usually found randomly throughout the package. Some X-ray systems can distort the size of voids through blooming. It is possible to accurately measure the true volume of a void but the procedure can be involved and requires a known reference for radiometric calibration of the X-ray film or detector. In most cases the effort is better spent on identifying and eliminating the cause of the voids. 7.5.1 Voids
7.5.1.1 Sources of Voids There can be voids in a BGA solder ball, in the solder joint to BGA interface, or in the solder joint to PCB interface. Various sources or reasons can be responsible for these voids.
Voids can be carried over from original voids in solder balls, which could be the result of the ball manufacturing process. Voids can be induced into the reflowed solder joint by either the voids in the original component solder ball, or during the reflow attachment process of the ball to the component. Voids can also form near the PCB to ball interface during BGA to PCB attachment. These voids are typically formed during the reflow soldering process by flux volatiles trapped during the solidification of the molten solder. The source of flux volatiles can be either from applied flux itself (typically rework), or flux which is one of the constituents of the solder paste used in the reflow assembly process. Solder joint voids are caused by solidification shrinkage, moisture, and flux volatilization. This occurs in leaded devices but is more critical on a BGA due to higher stress on the solder joint compared to leaded devices. • Shrinkage – the interior of a solder joint is the last part of the joint to solidify so you expect it to have a void. • Moisture and contaminates supply gases that can be trapped.
IPC-7095B
• Flux in the paste degrades and becomes gaseous during ramp-up in the reflow oven. On a BGA the gases are tightly sandwiched between two surfaces and the voids that occur typically rise to the top of the solder joint. A high ramp rate can cause more voiding by not allowing time for void migration out of the joint (ramp rate example, 75 vs. 60°C/minute) • Paste flux to attach PBGAs tends to produce fewer voids than with solder paste. • Too much flux added during the rework process can cause voids. • Proper oven profile and clean parts can reduce solder voids In addition to voids formed from via-in-pad construction (see 6.3.5), some voids are detected in the middle to top (ball/ BGA interface) of the reflowed solder joint. This is expected because the trapped air bubble and the vaporized flux, which is applied to the PCB BGA lands, rises during the reflow profile. This occurs when the applied solder paste and the BGA’s collapsible eutectic solder ball(s) melt together during the reflow profile, typically 210-230°C peak temperature for tin/lead and 235-245°C for lead free. The metallurgical composition and surface roughness of an incoming component ball can also add to ball void creation. If the reflow profile cycle doesn’t allow sufficient time for either the trapped air or vaporized flux to escape, a void is formed as the molten solder solidifies in the cool down area of the reflow profile. Therefore, the development of the reflow profile is extremely important as a contributor to the formation of voids. It is important to work with your solder paste manufacturer to establish the reflow profile for the solder paste formulation you are going to implement. Voids in solder joints are not new. Voids can be detected under leaded components when using X-ray equipment; however, leaded component solder joints were historically visually inspected, not X-rayed, and therefore hidden voids were never detected. BGA suppliers should X-ray components before and after the J-STD-002 Surface Mount Simulation Test (Test S) is run to reveal anomalies that may lead to solderability problems. Voiding can be a result of surface contamination at the component land or PCB land, intermetallics forming between solder ball and land, or un-expelled flux residues from the assembly process as shown in Figure 7-41. 7.5.1.2 Impact of Voids How many and what size of voids should be allowable in the product before they impact the product’s required reliability? Voids may impact reliability by weakening the solder balls and reducing functionality because the reduced cross-section will have lower heat transfer and current carrying capabilities.
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Land Pattern on Package Small Voids at Ball-to-Land Interface
IPC-7095b-7-41
Figure 7-41 Small voids clustered in mass at the ball-toland interface
Large voids are more detrimental but small preexisting voids can merge during reflow to create large voids. The elimination of voids, or at least a substantial reduction, is generally preferred. The process controls to minimize voiding should be established during the development stage of the process. There are a number of studies that have shown that a small increase in reliability is observed as a result of moderate size voids. These are typically from processes that are in control. The increased reliability results from increased solder joint height and a temporary and local retardation of crack propagation. X-ray inspection is required for the detection of voids in BGA solder joints; cross-sectioning may be necessary in order to determine the impact of the void or its location and size. Low cost equipment is based on transmission X-ray. Unlike a leaded component, BGAs have solder joints that are not only on the component’s periphery, but have internal solder joints that are not inspectable by normal visual techniques. Higher cost equipment is based on X-ray tomography or laminography. Both types of these systems provide valuable techniques for void detection and location (see 7.3.1). It is recommended that the process be qualified for void acceptance before being released for production. 7.5.1.3 X-Ray Detection and Measurement Cautions
Some of the real time X-ray inspection systems still in use for the detection of solder voids employ an X-ray imaging device that exhibits an aberration referred to in the literature as Voltage Blooming or Phosphor Blooming. Any system using an image intensifier or flat panel detector can, in theory, be made to bloom. However, modern, high contrast x-ray systems, using either image intensifiers or flat panel detectors are more than capable of providing proper images. Figure 7-42 is an example of voltage blooming in older systems. If it is determined that the X-ray inspection system in use exhibits voltage blooming, the following recommendations are made to obtain a more precise measurement of void size: 96
• X-ray film images not being subject to voltage blooming have been found to provide a more accurate determination of void size. • Correlation of the X-ray source voltage, to the degree of blooming, when the actual size of a void has been determined by cross sectioning or simulation. Note: The tonal quality should be good enough to see a wire through the void. • For every voltage and current setting, the gray scale should be reset to between 120 and 140, for a 1 to 256 gray scale system. Normalizing gray scale will maintain consistency between measurements. 7.5.1.4 Void Classification In order to assess different conditions, voids have been given a specific identifier, based on location, to establish a method of void identification and the possibility of corrective action for process improvement. The details are provided in Table 7-6 which shows classification criteria for the location of voids in the BGA solder ball structure.
The following descriptions identify the five different void types: Type A: Void(s) within the ball (package level) as received. Type B: Void(s) at the ball/package substrate interface as received. Type C: Void(s) within the ball after board level assembly process. Type D: Void(s) at the ball/package substrate interface after board level assembly process. Type E: Void(s) at the ball/board substrate interface after board level assembly process. 7.5.1.5 Control of Voids End users should work with their suppliers to control the frequency and size of voids in the BGA solder balls to some acceptable level. The suppliers can adjust their process and/or materials control in order to meet these objectives. Typically, few voids are detected in the incoming BGA solder joints.
Reflow time/temperature profile, flux amount, type and properties should be investigated for improvement. The formation of voids can also be influenced through material and/or process adjustment and optimization. The use of excessive flux in the initial BGA attachment or in BGA rework has a tendency to create voids due to flux volatilization. The process should be characterized to keep flux application to a minimum. There are some significant variables in the lead-free process that need to be evaluated as to their influence occurrence of voids. These important conditions include but are not limited to: • Stencil design • Flux and flux application
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(a) Figure 7-42
(b)
IPC-7095b-7-42a,b
X-ray image of solder balls with voids at 50 kV (a) and 60 kV (b) Table 7-6
Void Analysis
Void classification
Voids Within the Ball
Voids in BGA balls prior to attachment to a PWB
Voids at the Package Interface
Voids at the Mounting Surface Interface
N/A
Voids in BGA balls after attachment to a PWB
• Solder paste formulation • Reflow profile • Reflow atmosphere (nitrogen or oxygen) • Surface finish • One pass vs. two pass reflow • Presence or absence of microvias Many of the conditions explained in the following paragraphs can be significantly improved through working with the paste material supplier in order to fine tune the process that matches the specific paste and paste supplier’s formulation. The process control issues are not a text book solution. In order to make process improvements each of the variables need to be evaluated and controlled, usually through design of experiment (DoE) actions.
during the soldering processes. These macrovoids generally do not affect the solder joint reliability unless they are present at interfacial regions in the solder joints where cracks typically propagate. Planar Microvoids are a series of small voids, in relatively the same plane, located at the interface between the PCB Lands and the solder. These are caused by copper caves under ImAg- surface-finish coated lands. They do not affect initial product quality, but can affect long term solder joint reliability. They can be eliminated by strict control of the ImAg surface finish plating solutions and etching chemicals and other critical process parameters, at all times during surface finish plating on boards.
Six types of voids in solder joints have been identified and described. The characteristics of each of these voids are summarized in Figure 7-43 which illustrates the typical size and location of these voids in a BGA solder joint.
Shrinkage Voids are caused by the shrinkage during solidification, mostly for SAC and other lead-free solders. They do not generally appear near the solder-to-PCB land interface and do not impair the solder joint reliability. These shrinkage voids can be minimized by increasing the cooling rate during soldering and avoiding disturbance to the joint while it’s solidifying.
Macrovoids are the most widely occurring voids in solder joints. These are caused by volatile compounds that evolve
Microvia Voids are caused by the presence of microvias designed in the PCB lands. Large Microvia Voids, if
7.5.1.6 Voids in BGA Solder Joints
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BGA Solder Joint after Reflow Soldering
11
11
7.5.1.7 Process Control Criteria for Voids in Solder Balls There is a continuing need for process development
1 1
and control to accommodate changing technologies. As BGA land sizes, solder ball sizes and land pitch continue to decrease, the dimensional parameters used on the production floor need to change. New materials and processes may be required to meet quality and reliability goals.
1 1
3 1 1 2 2
66
4 4
2 2
2 2
66
Cu-IMC-Solder Interface after High Temp Aging Cu6Sn5 Cu6Sn
1: Macrovoids 2: Planar Microvoids 3: Shrinkage Voids
order to determine their impact on joint reliability and to assess corrective actions to minimize or eliminate them.
5
4: Micro-Via Voids 5: IMC Microvoids 6: Pinhole Voids IPC-7095b-7-43
Figure 7-43 Typical size and location of various types of voids in a BGA solder joint
located in solder joints in high stress areas of a package, can impact solder joint reliability. Plating the microvia shut, or filling it completely with solder paste by double printing, can minimize the creation of these voids.
Voids will likely be encountered during various stages of product life from development through manufacturing. Maintaining a minimum acceptable standard is necessary to assure that the product meets customer expectations, product-life and reliability requirements. Manufacturers need to use process control and continuous product improvement techniques for void control. Readily available statistical process control and process improvement tools may be used. A change in frequency and size of voids should indicate a need for process control as well as improving the process and materials. A baseline can be used to determine the need for process adjustments to control the frequency and size of voids. In addition, a void size limit could be established. Size is determined in relationship to the ball. Thus a void size larger than 25% of the solder ball’s cross sectional image diameter is approximately 6% of the total projected area variation (see Figure 7-44). Any such process control limits should be set with customer agreed-to contractual commitment.
IMC Microvoids occur within the Intermetallic Compound (IMC) formed between copper and high tin solders, including SAC and tin/lead solders. These IMC Microvoids do not form immediately after the soldering process, but after aging at high temperatures or during temperature cycling of the solder joints. The true root cause is still under investigation, but a Kirkendall voiding mechanism may play a part. These voids can affect solder joint reliability, particularly in instances when brittle fracture is initiated within the IMC during drop or mechanical shock to the solder joint. Doping the solder with certain elements such as zinc is one way to diminish the amount of these IMC microvoids. Pinhole Voids are caused by pinholes in the copper lands of the PCB. With sufficient quantity, they can affect solder joint reliability. These voids are caused by entrapped PCB fabrication chemicals within these pinholes that volatilize during the reflow soldering process. The pinholes occur due to an excursion within the copper plating process at the PCB fabricator and can be eliminated by improved copper plating process control systems. Whenever voids are observed in solder joints, they first need to be identified in one of the above categories, in 98
Solder Outline Void Outline
0.25 d
d IPC-7095b-7-44
Figure 7-44 Interface
Example of voided area at land and board
When there is more than one void per solder ball, the dimensions of the voids will be added to calculate the total voiding in that solder ball. Once the relationship of the void diameter to the ball image diameter is known, the actual numbers and size relationships become important. A 25% difference in diameters is
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not significant at the larger ball image sizes but becomes more important when the land diameter shrinks to accommodate a smaller ball or smaller BGA pitch. This is shown through the determination of the area connected to the land after the void has been determined. Image of a BGA ball 600 µm with a 25% void = (Dvoid)2 = 22500 µm2 (Dball)2 = 360000 µm2 = 6.25% area taken up by the void. Comparing area of ball image with area of void image leaves 265073 µm2 remaining (πr2). Image of a BGA ball 300 µm with a 25% void = (Dvoid)2 = 5625 µm2 (Dball)2 = 90000 µm2 = 6.25% area taken up by the void. Comparing area of ball image with area of void image leaves 66268 µm2 remaining (πr2). In regard to voids and the percentage of voids within the ball, location of the voids is of greater concern. There is no evidence or empirical data that indicates that voids within the ball will cause failure. Voids at the interface between the ball-and-package substrate as well as voids at the interface between the ball and the PCB will be more likely to contribute to solder joint cracking. This is because cracks (if they occur) will typically occur at the interface and the void or voids can provide (in time) a path to accelerate the cracking condition. The determination of the impact that voids have on the final product can best be expressed in terms of the flow diagram shown in Figure 7-45. 7.5.1.8 Process Control Criteria The accept/reject criteria for BGA assemblies is established by J-STD-001 and IPC-A-610. Those documents provide the final accept/ reject criteria used in contractual agreements. The process corrective actions identified in the following sections are intended to establish continuous process improvement based on the size of the voids, their location, and method of determination of the void occurrences.
Void clarification is also defined as to whether the voids occur prior to attachment to the mounting structure, or after the assembly has taken place. This useful information can be correlated to reliability conditions based on the end-use environment. Using the size limitation structure a process can be established that helps to meet the customers’ defined acceptability conditions. 7.5.1.9 Process Characterization The process characterization information is based on void size and follows the recommendations of the flow diagram shown in Figure
7-45. The combination of void location, void size, and number of occurrences helps to establish the actions required based on the standard IPC three class structures. Table 7-7 identifies the recommendations for ball pitches of 1.5, 1.27 and 1.0 mm. Table 7-8 identifies the recommendations for ball pitches of 0.8, 0.65, 0.5 mm. Table 7-9 identifies the recommendations for pitches of 0.5, 0.4 and 0.3 mm using the via-in-pad technology. All three tables identify the particular void types and relate this information to the number of occurrences that there could be in the three performance classes adopted by IPC. The evaluation of an increase in the number of voids that has been set as a target value can be a good aide to determining a process shift or a required change in some of the process parameters. A process change should be driven by an appropriate SPC methodology which should be used during normal production cycles. The use of these tables should also be for new product introduction, product and process qualifications, equipment set changes, component qualifications, response to customer feedback, and any similar change to the process or parameters. The sampling plan used should be done at a printed circuit assembly level, unless the SPC results show a component related issue i.e., voids in one collapsible BGA and no voids across the other collapsible BGAs on the board. In this case, the sampling plan should be executed at a component level of the suspect component part rather than examining the assembly process. Fine Pitch BGAs – As explained in 7.1.5.7, the amount of attachment area that remains after the void is identified is much less than in the standard pitch BGA. Table 7-8 is intended to show the corrective actions that should be taken when the X-ray image shows the presence of voiding in the incoming evaluation of the component or the evaluation after assembly. The ball image is based on the BGA pitch and, as it gets smaller, so does the land and the resultant attachment area. The recommendations for corrective action have taken this into account and reduced the void size to compensate and thus improve the final attachment reliability. Via-in-Pad Design in Fine Pitch BGAs – As designs get into finer and finer pitch the need to obtain sufficient routing space encourages the use of microvias and via-in-pad design. The conditions become more critical especially in the use of designs that require lead-free assembly. Figure 7-46 shows an example as to how the cracks in the solder joint propagates out from the void that has been created by the absence on material in the land. This condition can be overcome if the via is filled and over-plated so that air entrapment does not promote this condition. Via-in-pad designs require a further restriction of void allowance as shown in Table 7-9. 99
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Inspect BGAs
Yes BGAs Pass Inspection Criteria Sample Inspect Component Lot No
Yes
Ship BGAs More Voided Balls than Allowable Percentage? Assemble PCA
No Inspect PCA
No Process Action Required
Take Appropriate Corrective Action for Product Class
Yes Any Balls with Voids Larger than Maximum Void Size? Replace BGA and Sample Inspect Assembly Lot
No
Yes More Voided Balls than Allowable Percentage?
No
Ship PCA
No Process Action Required
Take Appropriate Corrective Action for Product Class
Note: Sampling rates for void inspection to be determined by product requirements. IPC-7095b-7-45
Figure 7-45
100
Typical flow diagram for void assessment (See Tables 7-7 to 7-9 for corrective action indicators.)
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IPC-7095B Table 7-7
Void Type
Corrective action indicator for lands used with 1.5, 1.27 or 1.0 mm pitch Corrective Action Indicator
Void Description
Class 1
Class 2
Class 3
Action Taken
Determined by cross section/X-ray laminography (sampling according to Section 7.5.1.10) at Component Incoming Evaluation A
Voids within the solder ball (prior to assembly)
Up to 90% balls may have voids Maximum Void size in any ball is 20% of Area (45% of the image diameter)
B
Voids at package interface (prior to assembly)
Up to 80% balls may have voids Maximum Void size in any ball is 15% of area (40% of the image diameter)
Up to 70% balls may have voids Maximum Void size in any ball is 10% of area (32% of the image diameter)
Investigate root cause in process & take corrective action Up to 50% balls may have voids Maximum Void size in any ball is 5% of area (22% of the image diameter)
Investigate root cause in process & take corrective action
All balls with cumulative voids no matter what size are considered Determined by cross section/X-ray laminography (sampling according to Section 7.5.1.10) Evaluation after Assembly C
Voids within the ball after PCA reflow
Up to 100% balls may have voids Maximum Void size in any ball is 25% of Area (50% of the image diameter)
D
Voids at the package interface after PCA reflow
Up to 100% balls may have voids Maximum Void size in any ball is 25% of area (50% of the image diameter)
Up to 80% balls may have voids Maximum Void size in any ball is 20% of area (45% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action Up to 60% balls may have voids Maximum Void size in any ball is 15% of area (40% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action
All balls with cumulative voids no matter what size are considered E
Voids at the mounting surface interface after PCA reflow
Up to 100% balls may have voids Maximum Void size in any ball is 25% of area (50% of the image diameter)
Up to 80% balls may have voids Maximum Void size in any ball is 20% of area (45% of the image diameter)
Up to 60% balls may have voids Maximum Void size in any ball is 15% of area (40% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action
Balls with cumulative voids smaller than 2% of the area (15% of the image diameter) are not counted Determined by transmission X-ray (sampling according to Section 7.5.1.10) for Process Evaluation either at Component Incoming or after Assembly A, B
Voids at incoming
Up to 80% balls may have voids Maximum Void size in any ball is 15% of area (40% of the image diameter)
Up to 70% balls may have voids Maximum Void size in any ball is 10% of area (32% of the image diameter)
Up to 50% balls may have voids Maximum Void size in any ball is 5% of area (22% of the image diameter)
Investigate root cause in process & take corrective action.
All balls with cumulative voids no matter what size are considered C, D, E
Voids after PCA reflow
Up to 70% balls may have voids Maximum Void size in any ball is 25% of area (50% of the image diameter)
Up to 60% balls may have voids Maximum Void size in any ball is 25% of area (50% of the image diameter)
Up to 50% balls may have voids Maximum Void size in any ball is 20% of area (45% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action
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March 2008 Table 7-8
Void Type
Corrective action indicator for lands used with 0.8, 0.65 or 0.5 mm pitch Corrective Action Indicator
Void Description
Class 1
Class 2
Class 3
Action Taken
Determined by cross section/X-ray laminography (sampling according to Section 7.5.1.10) at Component Incoming Evaluation A
Voids within the solder ball (prior to assembly)
Up to 90% balls may have voids Maximum Void size in any ball is 15% of Area (40% of the image diameter)
B
Voids at package interface (prior to assembly)
Up to 80% balls may have voids Maximum Void size in any ball is 12% of area (35% of the image diameter)
Up to 70% balls may have voids Maximum Void size in any ball is 9% of area (30% of the image diameter)
Investigate root cause in process & take corrective action Up to 50% balls may have voids Maximum Void size in any ball is 4% of area (20% of the image diameter)
Investigate root cause in process & take corrective action
All balls with cumulative voids no matter what size are considered Determined by cross section/X-ray laminography (sampling according to Section 7.5.1.10) Evaluation after Assembly C
Voids within the ball after PCA reflow
Up to 100% balls may have voids Maximum Void size in any ball is 20% of Area (45% of the image diameter)
D
Voids at the package interface after PCA reflow
Up to 100% balls may have voids Maximum Void size in any ball is 20% of area (45% of the image diameter)
Up to 80% balls may have voids Maximum Void size in any ball is 15% of area (40% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action Up to 60% balls may have voids Maximum Void size in any ball is 12% of area (35% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action
All balls with cumulative voids no matter what size are considered E
Voids at the mounting surface interface after PCA reflow
Up to 100% balls may have voids Maximum Void size in any ball is 20% of area (45% of the image diameter)
Up to 80% balls may have voids Maximum Void size in any ball is 15% of area (40% of the image diameter)
Up to 60% balls may have voids Maximum Void size in any ball is 12% of area (35% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action
Balls with cumulative voids smaller than 2% of the area (15% of the image diameter) are not counted Determined by transmission X-ray (sampling according to Section 7.5.1.10) for Process Evaluation either at Component Incoming or after Assembly A, B
Voids at incoming
Up to 80% balls may have voids Maximum Void size in any ball is 9% of area (30% of the image diameter)
Up to 70% balls may have voids Maximum Void size in any ball is 6% of area (25% of the image diameter)
Up to 50% balls may have voids Maximum Void size in any ball is 4% of area (20% of the image diameter)
Investigate root cause in process & take corrective action
All balls with cumulative voids no matter what size are considered C, D, E
Voids after PCA reflow
Up to 70% balls may have voids Maximum Void size in any ball is 20% of area (45% of the image diameter)
Up to 60% balls may have voids Maximum Void size in any ball is 15% of area (40% of the image diameter)
Up to 50% balls may have voids Maximum Void size in any ball is 10% of area (32% of the image diameter)
Balls with cumulative voids smaller than 4% of the area (20% of the image diameter) are not counted
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Investigate root cause in process & incoming parts, take corrective action
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IPC-7095B Table 7-9
Void Type
Corrective action indicator for microvia in pad lands used with 0.5, 0.4 or 0.3 mm pitch Corrective Action Indicator
Void Description
Class 1
Class 2
Class 3
Action Taken
Determined by cross section/X-ray laminography (sampling according to Section 7.5.1.10) at Component Incoming Evaluation A
Voids within the solder ball (prior to assembly)
Up to 90% balls may have voids Maximum Void size in any ball is 9% of Area (30% of the image diameter)
B
Voids at package interface (prior to assembly)
Up to 80% balls may have voids Maximum Void size in any ball is 6% of area (25% of the image diameter)
Up to 70% balls may have voids Maximum Void size in any ball is 4% of area (20% of the image diameter)
Investigate root cause in process & take corrective action Up to 50% balls may have voids Maximum Void size in any ball is 2% of area (15% of the image diameter)
Investigate root cause in process & take corrective action
All balls with cumulative voids no matter what size are considered Determined by cross section/X-ray laminography (sampling according to Section 7.5.1.10) Evaluation after Assembly C
Voids within the ball after PCA reflow
Up to 100% balls may have voids Maximum Void size in any ball is 25% of Area (50% of the image diameter)
D
Voids at the package interface after PCA reflow
Up to 100% balls may have voids Maximum Void size in any ball is 15% of area (40% of the image diameter)
E
Voids at the mounting surface interface after PCA reflow
Up to 80% balls may have voids Maximum Void size in any ball is 10% of area (32% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action Up to 60% balls may have voids Maximum Void size in any ball is 5% of area (22% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action
All balls with cumulative voids no matter what size are considered Up to 100% balls may have voids Maximum Void size in any ball is 15% of area (40% of the image diameter)
Up to 80% balls may have voids Maximum Void size in any ball is 10% of area (32% of the image diameter)
Up to 60% balls may have voids Maximum Void size in any ball is 5% of area (22% of the image diameter)
Investigate root cause in process & incoming parts, take corrective action
Balls with cumulative voids smaller than 2% of the area (15% of the image diameter) are not counted Determined by transmission X-ray (sampling according to Section 7.5.1.10) for Process Evaluation either at Component Incoming or after Assembly A, B
C, D, E
Voids at incoming
Not Recommended
Investigate root cause in process & take corrective action
Voids after PCA reflow
Not Recommended
Investigate root cause in process & incoming parts, take corrective action
Note: If a board design or manufacturing does not include filling vias, a joint team between the designer, customer, material supplier, and assembly engineering should be formed to conduct experiments to minimize voiding. Once the voiding has been minimized, an acceptable level of voiding for that specific product should be established and used for process control for that product.
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crack
BGA ball at
1st
025" land 06" void 24% DIAMETER 6% AREA
025" land 010" void 50% DIAMETER 16% AREA
25 + 6,6,6,3,3,3,3,3 24% AREA
25 + 6,6,6,4,3,3,3,3 25% AREA
025" land 013" void 52% DIAMETER 27% AREA
025" land 015" void 60% DIAMETER 36% AREA
25 + 10,10,6 38% AREA
25 + 10,6,6,6 37% AREA
.020" X .030" .010" VOID 50% DIAMETER 10% AREA
corner pin
.020" X .030" .014" VOID 70% DIAMETER 19% AREA
.020" X .030" .016" VOID 80% DIAMETER 25% AREA
20 X 40 + 10,5,5,5,5,5,5 24% AREA
Figure 7-47
no crack
.020" X .030" .018" VOID 90% DIAMETER 31% AREA
20 X 40 + 10,10,5,5,3 26% AREA IPC-7095b-7-46
Examples of suggested void protocols
under typical x-ray inspection should be discussed with your x-ray equipment supplier. Although much description data is provided on identification of voids, there is not always correlation to significant factors related to thermal cycle life of the joint. In addition, no data is currently available on rework vs. thermal cycle life.
BGA ball adjacent to 1st corner pin IPC-7095b-7-46
Figure 7-46 lead
Voids in BGAs with crack started at corner
7.5.1.10 Void Protocol Development In many applications, engineering teams create a void protocol which describes the allowable voiding after the controlled experiments have determined the characteristics of the project. Figure 7-47 shows an example of a protocol that can be established to show the variation of void size compared to ball diameter for various land pattern geometries.
For in-process control, use >35% area as the threshold with a >50% void diameter threshold. For reject-rework, use >45% area as the criteria with a >65% void diameter threshold. Use of X-ray requires some caution regarding radiation overexposure on vulnerable materials or components, as the radiation dose from different x-ray systems can vary widely. The implications of radiation dose to radiosensitive components may need to be discussed with your component supplier and the dose rates that will be achieved 104
Normal area percent voids is 15 ± 10% of the projected area. Note: Voids at ~30% warrant process-control attention. Voids > 50% warrant rework. (See Section 7.5.) Considering a 0.20 mm diameter void as an example, Table 7-10 lists the void percentages for different ball sizes. The percentage void diameter detectable becomes larger as solder joint size decreases; that is, 27% on a 0.75 mm joint inflates to 67% on a 0.30 mm solder joint. Table 7-10 Ball-to-void size image comparison for various ball diameters Void 0.20 mm Diameter
Solder Ball Diameter/ X-Ray Image
% Void Diameter
% Void Area
0.85 mm
24%
6%
0.75 mm
27%
7%
0.65 mm
31%
9%
0.55 mm
36%
13%
0.45 mm
44%
20%
0.40 mm
50%
25%
0.30 mm
67%
44%
March 2008
IPC-7095B
Defect determination is made by the product’s reliability requirements. As an example, if the maximum allowable void size is 31% of the solder ball diameter, the equivalent of the void area is 9%. This can be either one void, or the summation of many voids. Some of the newer X-ray equipment use algorithms that are able to summarize the void areas. Unfortunately the current algorithms for X-ray tomography do not perform the summation of the voids.
Solder Land Area
For a single void, X-ray tomography can identify a defect caused by a void that is greater than the predetermined size. Example: If the solder ball size = 0.75 mm and the maximum allowable void size = 30% of the ball diameter, the maximum void size at the center of the ball would be calculated as follows: 30% of 0.75 mm (0.75 mm)(0.3) = 0.225 mm maximum void diameter When the void is not in the center of the ball and near the land of either the board or the component, the cross sectional diameter of the ball will be reduced as well as the maximum allowable size for a void. Example: If the ball diameter at the land is approximately equal to the land and the land size is 75% of the ball size (25% reduction), then: 75% of 0.75 mm = 0.56 mm ball diameter at the land 30% of 0.56 mm = maximum void diameter (0.56)(0.3) = 0.17 mm maximum void diameter at the land Process control criteria for the number and size of voids discourage a general presence of voids, which indicates an out of control process and calls for the need to use the necessary tools for process and material improvement. Void size is also important as shown in Table 7-7 to 7-9 and Figure 7-48. The criteria define the characteristics for void acceptability based on size and pitch. For collapsible solder balls, when attached to the land pattern, the ball takes an elliptical sphere form rather than a uniform round sphere shape. Therefore, the solder joint diameter at the ball’s center is typically greater than the diameter at the ball-to-land interface. The criteria applied to varying ball sizes and land sizes will result in different void sizes. 7.5.1.11 Sampling Plans for Void Evaluation Because of the industry concern regarding voids, this standard attempts to define criteria for void baseline goals and process control techniques. Everyone agrees that it makes no sense to throw away good product, or rework product where a void is identified without some indication as to the complexity and the impact on reliability of that condition.
Void occurrence criteria are not based on 100% inspection, but are accomplished through the use of sampling plans.
12% Void Area Figure 7-48
IPC-7095b-7-48
Void diameter related to land size
The sampling plan conditions are identical to those shown in IPC-6012 and are repeated in Table 7-11. It should be noted that the table is based on C=0. What this means is that, as within all IPC standards, when a sample is selected, any occurrence of exceeding the characteristics for void size shown in Table 7-9, requires 100% evaluation of the total lot. The appropriate corrective action may vary based on class of product and customer requirements. The ultimate action is to remove and replace the affected component, however those solutions must be carefully evaluated as the product should have been designed to permit repair procedures that include reevaluation. Once a void protocol has been established as to the percent attachment permitted, random samples should be taken from the production units and evaluated as to compliance with the accepted conditions identified in the protocol. The decision as to how many samples to take depends on the number of units being produced. A consideration should also be given to the number of BGAs that are part of the particular assembly. The index value of 2.5 is a good representation that can provide an insight into the capabilities of the process regarding BGA assembly and the occurrence of voids. The Level A 2.5 index can be used for evaluating commercial product used in consumer goods and computer applications. It is also appropriate for telecommunication equipment. For a Class 2 equipment where high performance and extended life is required, and for which uninterrupted service is desired but is not critical, and certain cosmetic imperfections are allowed an index indicator of 1.5 should be used. 105
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March 2008 Table 7-11
C=0 sampling plan (sample size for specific index value*)
Class 1 Lot Size
Class 2
Class 3
2.5*
4.0*
6.5*
1.5*
2.5*
4.0*
0.10*
1.0*
2.5*
4.0*
1-8
5
3
2
**
5
3
**
**
5
3
9-15
5
3
2
8
5
3
**
13
5
3
16-25
5
3
3
8
5
3
**
13
5
3
26-50
5
5
5
8
5
5
**
13
5
5
51-90
7
6
5
8
7
6
**
13
7
6
91-150
11
7
6
12
11
7
125
13
11
7
151-280
13
10
7
19
13
10
125
20
13
10
281-500
16
11
9
21
16
11
125
29
16
11
501-1200
19
15
11
27
19
15
125
34
19
15
1201-3200
23
18
13
35
23
18
125
42
23
18
3201-10,000
29
22
15
38
29
22
192
50
29
22
10,001-35,000
35
29
15
46
35
29
294
60
35
29
*Index Value is associated to the A.Q.L. value. If a particular product is determined to be ‘‘critical’’ by the user and a smaller index value is required, the user shall designate the requirement in the procurement document and should state the ‘‘critical’’ requirement on the master drawing. **Denotes inspect entire lot.
Class 3 is for High Reliability Electronic Products and includes equipment for commercial and military products where continued performance or performance on demand is critical. Equipment downtime cannot be tolerated, and must function when required such as for life support items, or critical weapons systems. Printed board assemblies that contain BGAs in this class are suitable for applications where high levels of assurance are required and service is essential; thus, the evaluation requires a sampling of 1.0 index value. The purpose of the index value is to define the possibility that, although the samples reviewed all meet the defined void protocol, there is still a statistical possibility of the percentage shown by the index that some of the product may not meet the conditions established. A 1.0 index for level C requires that 13 samples be examined from a production lot of 125 assemblies. Even if the samples all meet the protocol, there is still a possibility that 1.0% of the lot size do not. This relates to less than 2 assemblies and would be a satisfactory risk in many applications. 7.5.2 Solder Bridging Solder bridging is unacceptable. Electrical testing, optical inspection (endoscope) or X-ray inspection is necessary to detect solder bridging. Poor solder paste printing, inaccurate placement, manual ‘‘tweaking’’ after placement, and solder splattering during reflow are typical causes of solder bridging. Solder balls too large for the gap between the two substrates can also cause bridging. 7.5.3 Opens Solder opens are also unacceptable. Electrical testing, optical inspection (endoscope) or X-ray inspection is necessary to detect solder opens. Poor solder paste printing, inaccurate placement and manual ‘tweaking’’ after placement are typical assembly related causes of solder
106
opens. Coplanarity and substrate solderability problems can also cause opens. Excessive mechanical stress can also cause solder joints to crack and create opens. 7.5.4 Cold Solder The reflow profile should reach temperatures high enough to ensure that the solder melts completely and proper wetting of the land surface occurs. A cold solder joint can reduce mechanical integrity and can cause it to fail electrically or function intermittently. Optical inspection after cross-sectioning is the best way to inspect for cold solder joints. 7.5.5 Defect Correlation/Process Improvement It is important to use inspection information to control the manufacturing process to maximize quality and yield. The manufacturing process leaves a signature (acceptable or unacceptable) on each component; this signature can be observed through inspection. The signature can be observed using methods and tools discussed previously.
In many cases a visual inspection of a BGA is the first clue to any problems. An operator can look at the edge of the BGA on all four sides. The distance between the BGA and the circuit board should appear uniform and the solder balls should appear consistent in shape. To directly observe the solder connections under a BGA, X-ray or optical inspection (endoscope) is necessary. These methods can be used to inspect for obvious defects such as bridges and missing balls. They are also useful for characterizing the BGA reflow process. During inspection the BGA solder balls should be examined for uniformity of size and shape. In the absence of wetting indicators, the solder balls should appear round and of equal size throughout the package. A PBGA with a 0.75 mm diameter ball prior to reflow will swell to a nominal 0.90 mm diameter after reflow; a 36% increase. A 10-15% variation in solder
March 2008
ball area from the center to the edge of the package is normal, but a larger variation can indicate a problem with the reflow process.
IPC-7095B
indicating that the solder ball and solder paste did not flow together to form a single solder joint (see Figures 7-49 and 7-50).
X-ray inspection of the BGA from an angle is also useful to examine the shape of the BGA solder ball in the area at which it makes contact with the land. By changing the angle of X-ray inspection, the land is shifted so that it does not obscure the rest of the solder ball. This allows the operator to inspect the shape of the solder connection as it forms onto the land to verify that the land is in contact with the solder ball and the solder is completely wetted to the land. Quantitative measurement of the solder bond X-ray image can be performed using image analysis software. Such software is useful but not required for the inspection of BGAs. The advantage of the software is in its ability to identify and display subtle variations in the size and shape of the solder bond image which is not easily observed by an operator. These subtle variations are a signature of the process used to manufacture the part and can be used to monitor the process and to correct for deficiencies. A number of signatures can be correlated with known process deficiencies. 7.5.6 Insufficient/Uneven Heating A common process problem is insufficient or uneven heating of the BGA. This problem occurs more often during rework but can also be seen in production when working with multilayer boards with many ground or power planes. The problem can also occur on double-sided boards when a shielded component is on the backside near the location of the BGA. The problem results when a thermal conductor removes the heat from the BGA before complete reflow can occur. The X-ray image of this problem is characterized by a variation in the size of the solder balls at different locations under the package.
Insufficient heating is generally characterized in an X-ray image by small partially reflowed solder balls in the center or to one side of the package. Insufficient heating may also be characterized by a jaggedness around the perimeter of these solder balls; indicating that the solder partially reflowed but not long enough to completely wet to the land and collapse to a nice round ball. Misalignment of the solder ball with respect to the land is also an indicator of inadequate heating. The X-ray image of misalignment is characterized by elongated solder balls which may or may not have a consistent orientation. X-ray inspection at a 45° angle is also a useful technique to locate signatures associated with insufficient heating or nonwetting. The solder ball should contact and completely wet to the land forming a smooth pillar. Signatures associated with insufficient heating include incomplete wetting to the land, or an image elongation in the solder connection
Figure 7-49
X-ray image showing uneven heating
Note the solder balls are larger at the bottom than the top.
Figure 7-50 X-ray image at 45° showing insufficient heating in one corner of the BGA Note the irregular shape of the solder bonds at the top of the image.
7.5.7 Component Defects Component defects such as popcorning and warpage are generally caused by improper handling of the BGA component prior to reflow. Both of these problems produce a characteristic signature in the X-ray image. Popcorning causes the BGA package to expand below the die; resulting in an increase in size (and possibly bridging) of the solder balls in the center of the package as they are squished between the package and the board (see Figure 7-51).
The X-ray image of a warped BGA tends to have large elongated solder connections at the corner of the package where warpage has occurred. The illustration in Figure 7-52a shows the X-ray image and Figure 7-52b shows a video microscope image of the package. Note that in Figure 7-52b the ripple in the substrate, which is characteristic of a stress relief which likely occurred during reflow. BGA warpage is more subtle than popcorning and can be more difficult to detect in an X-ray image (see Figure 7-52). Warpage tends to be the largest at the corners of the package. 107
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will properly align itself. With a controlled process and appropriate equipment, rework should be kept to a minimum. There are many rework systems on the market, most of which use a prism for placement, which allows the viewing of the land pattern on the board with the ball image superimposed over it. Most systems also allow board preheat and stored reflow profiles for many different component sites. This section will focus on conditions that should be met in order to successfully rework a plastic BGA. Figure 7-51
X-ray image of popcorning
Solder balls in the center of the package are oversized but had not bridged.
7.6.2 Removal of BGA When removing a BGA a decision has to be made regarding whether the component will be reballed and used again or simply discarded. Special considerations need to be made if the BGA will be reballed and reused (e.g., Maximum number of reflow cycles as recommended by the component vendor. Typically 3 reflows is the maximum recommendations so reballing a removed BGA and reinstalling it would exceed this number).Therefore, a reballed BGA will always exceed this limit. Many OEMs do not allow reballed BGAs, or reuse of any component. One should check with the customer before proceeding.
(a)
(b)
IPC-7095b-7-52a.b
Figure 7-52
X-ray image showing warpage in a BGA
The x-ray image (a) shows a distortion of the ball bonds in the lower right corner; characterized by large elongated bonds. The same location as viewed through a visual microscope (b) shows warpage and the solder ball peaking away from the package.
7.6 Repair Processes 7.6.1 Rework/Repair Philosophy Plastic ball grid arrays are a forgiving component package. With their self alignment characteristics, a ball grid array can be placed as much as 50% ball off land and when reflowed the package
108
There are four main rework functions for BGAs: removing the component, redressing the site, placing the component, and reflowing the component. These will be discussed in the following paragraphs.
If the component is to be reused and it is overmolded plastic, it will have to be baked. These packages are nonhermetic and therefore absorb water if they have been out of a moisture controlled atmosphere longer than the time allowed in J-STD-020. The baking process drives off moisture and prevents the ‘‘popcorning effect,’’ which is water vaporizing within the component during reflow and causing catastrophic failure. Another consideration before removal concerns the components adjacent to the BGA. If hot air is used, and if the profile to be used exceeds 4°C per second, the components surrounding the BGA may need to be shielded due to thermal shock or secondary reflow. Polyimide tape or water soluble mask that is commonly used in the wave solder processes can be used as shielding. These deficiencies can be resolved with proper equipment design. See Figure 7-53 for shielding with polyimide tape to prevent damage to adjacent components when using hot air for BGA repair. With lead-free technology, it is recommended to minimize the temperature delta between the bottom side of the board and topside of the board during the profiling process for BGA removal and reattach. The temperature of the bottom side of the board heating should be increased to minimize the topside nozzle heat when setting up the profile. This will minimize exposure of potential delamination of the bare board or heat transfer to adjacent components.
March 2008
Figure 7-53
IPC-7095B
BGA/assembly shielding examples
7.6.3 Replacement
Once the BGA has been removed from the board, solder will have to be removed from the land pattern. Solder vacuums and solder wick work well for removing solder off the lands. Caution is recommended when using any of these tools because the land can lift with excessive heat or pressure. Each land must be completely flat and clean before placing the new BGA. With the higher temperatures of lead-free alloys, it is critical to minimize contact with the solder mask dams between the lands and the vias (dog bone design). The higher temperatures may increase the potential to damage this solder mask. It can also be affected by the surface finish of the bare board. Two variables that can influence the adhesion of the solder mask to the land are the length of the solder mask dam (encroached vias is recommended) and the surface finish of the bare printed boards. 7.6.3.1 Land Pattern Site Dressing
then liquid flux or the paste flux are commonly used when reattaching a BGA, especially BGAs with less than 208 balls. Flux is applied to the land pattern or the BGA solder spheres and the BGA is placed over it. One drawback of this method is the coplanarity issue. If the lands are not perfectly flat, some of the balls may not touch. Excessive flux application may also cause bridging between solder balls. With lead-free technology most BGAs are going to be a SAC alloy which will reflow into the solder joint. Paste can be used for lead-free BGA as well and may result in less voiding of the BGA solder joint.
7.6.3.2 Flux Application Although the solder mask encroached on the via land is over bare copper, adhesion can be affected when subjected to the surface finish chemistry.
7.6.3.3 Paste Application Paste application is the preferred method but it does add time to the rework process as well as tooling cost. Paste can be applied locally with the use of mini-stencils. When ordering mini stencils for ceramic packages, the same aperture/thickness should be used as used for initial attach. This will ensure the reliability of the ceramic packages for reworked components. These stencils can be purchased from many different suppliers and are tailored to fit specific land patterns. A fixture or tape can be used to hold the stencil in place during application on the land pattern.
Two different methods of flux application can be used: paste/liquid flux or solder paste, however using flux only (in a liquid or paste form) is only applicable for eutectic BGA reattachment. In addition, some applications require the addition of solder paste in order to promote a robust solder joint. If paste flux (also called tack flux) is to be used ensure that the solder balls are Sn63/Pb37 (eutectic). Many ceramic BGAs use Pb90/Sn10 solder balls which reflow at 302°C. If the solder balls are not Sn63/Pb37, then solder paste has to be used. If solder balls are Sn63/Pb37,
When using these methods, considerations have to be made for solder paste handling and stencil cleaning. Solder paste can also be applied to the BGA using a syringe or paste dispensing frame with other proper tooling. The amount of solder paste applied should be carefully controlled. When printing solder paste for CSPs, there may not be enough room on the bare board for mini-stencils. In this situation it is a common process to screen the solder paste onto the package (bottom side of the balls) and then place the module onto the board for replacement. 109
IPC-7095B 7.6.3.4 Rework Issues Interpackage spacing is decreasing constantly. Even if companies have some design for manufacture (DFM) guidelines for interpackage spacing, those on the front line of manufacturing know very well that DFM guidelines are not always followed. So, using mini-stencils to print solder paste is becoming more difficult. Also, because a mini-stencil is needed for each size and type of part, it not only slows down the process but also quickly adds to the cost of repair.
Using a ministencil is not the only issue with everdecreasing interpackage spacing. Using different hot air nozzles for each size and type of part being removed also adds to the cost and complexity of rework. Additionally, the potential for melting solder joints of neighboring components is a serious concern. In addition to increased intermetallic thickness because of unnecessary reflow, which weakens the solder joints, the boards must be baked before rework, increasing cycle time. Throughput in rework is very important. Unfortunately, BGAs and some of the larger components can take at least 20 minutes per component for removal and replacement. Another important issue in rework is PCA board warpage. Warpage is partly due to intense local heating for a relatively long time,which is necessary to remove the component. For BGA repair, there are two rework processes in use today: hot air and laser. Hot air is the most common. The new process for removal and replacement of surface mount components, including BGAs and CSPs, is laser based. Multiple rework on the same BGA site can result in barrel cracking of the printed wiring board. Consideration must be made for printed wiring board materials and number of heat cycles the materials can withstand. 7.6.3.5 Hot Air Systems for BGA Repair Hot air systems are either totally manual or semiautomated. Using a nozzle, they blow hot air on the part to be reworked. The part is pulled away from the board when the solder on all joints is molten. Bottom-side heating is used to uniformly heat the entire board to a preheat setting prior to applying topside nozzle heat, thus reducing thermal shock. The hot air usually is directed on the BGA package by a nozzle designed specifically for that component. The package body is heated by the hot air impinging on the package and conduction within the package. Initially, the package is preheated with the nozzle some distance away (typically 25 mm or more) from the package body. Then the nozzle is lowered to a point just above the package body and lead temperature increases sharply until it reaches a peak. During this process of blowing hot air, the solder joints of neighboring components even 12 mm away can reflow, an unwanted and undesirable result. With higher velocity air, smaller components such as CSPs are prone to movement during rework.
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After the component is removed, paste application for reattachment is a most difficult and time-consuming process. However, using flux only (liquid or paste form) is only applicable for eutectic BGAs reattachment. Some applications require solder addition to promote a robust joint. Typically, a mini-stencil or dispenser is used to apply the paste. Both hot air nozzles and ministencils are needed for each type and size of part being reworked. Both these items require sufficient interpackage spacing for rework. The forced convection heating of the bottom side of the board will minimize the temperature of the nozzle required to achieve an acceptable lead-free profile. Typically tin/lead bottom side preheating is approximately 100°C. This temperature should be increased to 130°C minimum for leadfree products. 7.6.3.6 Laser Systems for BGA Repair The laser systems use from one to four diode lasers. Some of the laser systems are limited to reworking only peripheral components, in which the leads are in the laser’s line of sight. However, there are other laser systems that use multiple diode lasers and can rework both peripheral and array type packages such as BGAs, chip scale packages (CSPs) and flip chips by rapidly scanning top of package surfaces. This causes BGA/CSP/flip chip ball to reflow underneath by conduction through the package, as is the case in hot air rework. Some of these laser systems also have a built-in automated thermal management capability to monitor and control package temperatures within the specified limits to prevent overheating. There are laser systems with or without dispensing and pick and place capabilities.
Because the laser beam is very narrow, components even 1 mm away do not experience any heat. Laser systems heat the package without melting the solder joints of neighboring components. 7.6.3.7 Profile Requirements Whether using laser or hot air, the reflow profile for a BGA during rework is the same as the profile for a convection oven. Preheating the board to 100°C before initiating the removal or replacement cycle should be sufficient in keeping board warpage to a minimum. These requirements are summarized in Table 7-12 for tin lead and 7-13 for lead free. Be careful not to push the preheat towards 120°C since this is where some fluxes typically activate. If this happens the flux could be activated before it is needed and cause poor solderability during reflow. For lead-free solder pastes, this preheat temperature should be 120°C to 130°C minimum.
Sufficient time should be allowed for the flux to clean the ball and the land during the reflow profile. Flux should stay within 120-150°C for 30 to 120 seconds. After the flux has cleaned the site, a ramp rate of 2° to 4°C can be used. The standard 2°C for SMT profiling can be amended since there should not be any heat sensitive components such as
March 2008
IPC-7095B Table 7-12 Profile Topic
Preheat Soak or preheat activation Component ramp rate
Repair process temperature profiles for tin lead assembly Temperature Range
Time Range
100-150°C; not to exceed 150°C
N/A
100-180°C*
60-120 seconds*
2-4°C per second
Reflow dwell
Above 183°C
60 to 90 seconds
210-220°C
Not to exceed 10 seconds
A moisture sensitive component maximum temperature
225°C
Not to exceed 20 seconds
Component maximum temperature
230°C
60 seconds
Maximum adjacent component temperature**
170°C
0 seconds
Above 150°C
Not to exceed four minutes
Solder joint peak
Board temperature * Verify with supplier ** Adjacent component equals 5 mm away
Table 7-13 Profile Topic
Preheat Soak or preheat activation Component ramp rate Reflow dwell
Repair process temperature profiles for lead-free assemblies Temperature Range
Time Range
100°C to 190°C; not to exceed 190°C
N/A
140 -220°C*
60 to 150 seconds*
2°C to 4°C per second Above 220°C
60 to 90 seconds
230-245°C
Not to exceed 20 seconds
A moisture sensitive component maximum temperature
245°C
Not to exceed 20 seconds
Component maximum temperature
245°C
60 seconds
Maximum adjacent component temperature**
210°C
0 seconds
Above 190°C
Not to exceed four minutes
Solder joint peak
Board temperature * Verify with supplier ** Adjacent component equals 5 mm away
capacitors or resistors within the reflow nozzle when using hot air. The components that are adjacent to the nozzle should be shielded with polyimide tape or water soluble mask to protect components from thermal damage when using hot air. The reflow dwell time should be in the range of 30 to 90 seconds with the solder joint peaking between 200-220°C (for tin/lead) and 235-245°C for lead free. The balls at the center of the BGA package may exceed the 90 second recommendation due to entrapped heat from the reflow process. The board temperature should not be kept above 150°C for any longer than four minutes. This requirement is due to the glass transition temperature for FR-4. See J-STD-020.
These ‘‘infant mortalities’’ can be reduced by appropriate screening techniques prior to shipping, but not eliminated. Longer term failures are the result of premature wear-out damage caused by inadequate design of the assembly. The design guidelines in IPC-D-279 are a good reference. Reliability qualification requirements are given in IPC9701 together with well-defined test methodologies. For lead-free solder attachments, IPC-9701A contains guidelines for accelerated solder joint reliability testing; however, in the absence of useful acceleration models for the various lead-free solders, reliability requirements based on accelerated thermal cycling cannot be established.
Reliability is the ability of a product to function under given conditions, for a specified period of time within an acceptable level of confidence. The reliability of electronic assemblies requires a definitive design effort to be carried out during the developmental phase of the product to meet requirements. Reliability is defined in IPC-SM-785.
8.1 Accelerated Reliability Testing The validation and qualification tests should follow the guidelines given in IPC-SM-785, Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments and/or IPC-9701, Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments. For some products, the accelerated temperature cycling (ATC) needs to be combined with mechanical shock and/or vibration testing.
Short term reliability is threatened by early life failures generally attributed to insufficient production quality.
Accelerated reliability testing is carried out on design prototypes, typically to failure or until a predetermined
8 RELIABILITY
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reliability goal is achieved. The appropriate reliability goal can be determined with an appropriate acceleration model (see IPC-D-279, Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies).
ity Committee developed the table, ‘‘Accelerated Testing for End Use Environments.’’ Table 8-1 attempts to relate seven product categories by typical application to the thermal, mechanical, atmospheric, and electrical performance requirements that they must meet during typical manufacturing processes, storage, and during operation.
Once failure occurs, the resulting failure modes are analyzed as to the underlying failure mechanism(s). If it fails expectations then corrective action is necessary. Either the assembly process needs to be improved or the product needs to be redesigned. In either case retesting may be necessary after the corrective action has been implemented.
8.2 Damage Mechanisms and Failure of Solder Attachments The reliability of an electronic assembly depends
on the reliability of the sum of the individual elements of the mechanical thermal and electrical interfaces (or attachments) between these elements. One interface type, the surface mount solder attachment, is unique since the solder joint not only provides the electrical interconnection, but is
Recognizing that a matrix was needed to determine the exact requirements and the testing necessary for performance under various conditions, the IPC Product ReliabilTable 8-1
Accelerated testing for end use environments
Worst-Case Use Environment
Use Category
Tmin °C
ΔT °C
tD hrs
(1)
Tmax °C
Accelerated Testing
Cycles/ Year
Typical Approx. Years Accept. of Failure Service Risk %
Tmin °C
Tmax °C
ΔT(2) °C
tD min
1) Consumer
0
+60
35
12
365
1-3
1
+25
+100
75
15
2) Computers
+15
+60
20
2
1460
5
0,1
+25
+100
75
15
3) Telecom
-40
+85
35
12
365
7-20
0,01
0
+100
100
15
4) Commercial Aircraft
-55
+95
20
12
365
20
0,001
0
+100
100
15
5) Industrial & Automotive Passenger Compartment
-55
+95
20 &40 &60 &80
12 12 12 12
185 100 60 20
10
0,1
0
+100
100
15
& COLD 6) Military Ground & Ship
-55
+95
40 &60
12 12
100 265
10
0,1
0
+100
(3)
100
15
& COLD(3) 7) Space leo geo
-55
+95
3 to 100
1 12
8760 365
5-30
0,001
0
+100
100
15
& COLD(3) 8) Military Avionics a b c
-55
+95
40 60 80 &20
2 2 2 1
365 365 365 365
10
0,01
0
+100
100
15
& COLD(3) 9) Automotive Under Hood
-55
+125
60 &100 &140
1 1 2
1000 300 40
5
0,1
0
+100
100
15
& COLD(3) & LARGE ΔT(4) & = in addition 1) ΔT represents the maximum temperature swing but does not include power dissipation effects; for power dissipation calculate ΔT; power dissipation can make pure temperature cycling accelerated testing significantly inaccurate. It should be noted that the cyclic temperature range, ΔT is not the difference between the possible minimum, Tmin and maximum, Tmax, operational temperature extremes; ΔT is typically significantly less. 2) All accelerated test cycles shall have temperature ramps, 20°C/minute and dwell times at temperature extremes shall be 15 minutes measured on the test boards. This will give ~24 test cycles/day. 3) The failure/damage mechanism for solder changes at lower temperature; for assemblies seeing significant cold environment operations, additional ‘‘COLD’’ cycling, from perhaps -40 to 0°C, with dwell times long enough for temperature equilibration and for a number of cycles equal to the ‘‘COLD’’ °C operational cycles in actual use is recommended. 4) The failure/damage mechanism for solder is different for large cyclic temperature swings traversing the stress-to-strain -20 to +20°C transition region; for assemblies seeing such cycles in operation, additional appropriate ‘‘LARGE ΔT’’ testing with cycles similar in nature and number to actual use is recommended.
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also the sole mechanical attachment of the electronic components to the printed board. It often provides the critical heat transfer function as well. A solder joint in isolation is neither reliable nor unreliable; it becomes so only in the context of application. The characteristics of these three elements—component, substrate, and solder joint—together with the use conditions, the design life, and the acceptable failure probability determine the reliability of the surface mount solder attachment. The general characteristics of most lead-free solders as compared to tin/lead solders, include (1) significantly increased alloy stiffness, (2) significantly slower creep rates, (3) greater difficulties of proper spread, and (4) significantly higher soldering temperatures. The consequence of the greater stiffness or lower ductility and the slower creep rates are higher stresses on the whole solder attachment structure during either temperature changes, causing thermal expansion mismatches or PCB/ component warping or bending. These higher stresses, combined with less strong solder to base material connections due to inadequate wetting or interfacial structural weaknesses, may cause brittle interfacial failure.
Figure 8-1 BGA solder joint of eutectic tin/lead solder composition exhibiting lead rich (dark) phase and tin rich (light) phase grains
8.2.1 Comparison of Thermal Fatigue Crack Growth Mechanism in SAC vs. Tin/Lead BGA Solder Joints
Eutectic tin/lead solder joints develop different damage mechanisms than SAC BGA solder joints during Thermal Fatigue Tests, such as Temperature Cycling. Eutectic tin/ lead solder microstructure is multi-grained, with each BGA solder joints having many individual grains of lead-rich (dark phase) and tin-rich (light colored phases) precipitated out, as seen in Figure 8-1. In contrast, each SAC BGA solder joint has very few grains of tin. These grains can be seen under cross-polarizing light. Figure 8-2 shows two examples of SAC BGA solder joints. The one on the left has 6 grains, whereas the entire solder joint on the right is comprised of a single grain. For eutectic tin/lead BGA solder joints, during temperature cycling, grain coarsening occurs in areas of the solder joint where the strains due to thermal mismatch build up. These coarser grains are softer than the original as solidified grains, and promote crack propagation. This is shown in Figure 8-3. For lead-free SAC BGA solder joints, when subjected to thermal cycling, recrystallization of grains takes place in regions of large thermo-mechanical stress. These recrystallized grains are smaller in size than the original grains and are more prone to grain boundary sliding and hence creep deformation. This causes the fatigue cracks to propagate through this recrystallized region, as shown in Figure 8-4.
Figure 8-2 Socket BGA solder joints of SnAgCu composition, showing the solder joint comprised of 6 grains (top photo) and a single grain (bottom photo).
During the transition to lead-free reflow soldering, there will be occasions when it 8.2.2 Mixed Alloy Soldering
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lead BGAs in favor of lead-free BGAs. When confronted with this situation there are several options: • Refuse to build the PCBA • Reball the BGA with tin/lead solder balls (may not be acceptable to all companies) • Convince the supplier to provide a Sn/Pb version
Figure 8-3 Thermal-fatigue crack propagation in eutectic tin/lead solder joints in a CBGA module
8.2.2.1 Reflow Solder Using a Lead-Free Profile Some companies have successfully soldered mixed alloy BGAs and the reliability results have been acceptable in many cases. Studies have shown that the homogeneous contamination of SAC solder with <20% wt. Lead will not degrade fatigue life below that of tin/lead. However, be very cautious. Perform adequate reliability testing (cross-sections, thermal cycling, shock testing) to confirm solder joint reliability in the intended use environment.
All components on a mixed alloy (lead-free BGAs with tin/lead solder) PCBA should be evaluated for lead-free soldering process compatibility before soldering is attempted. This evaluation will ensure that all components will survive lead-free soldering temperatures. While most tin/lead components are rated to a peak temperature of 230°C, evidence suggests that many tin/lead components will survive lead-free soldering temperatures, though this is not always the case. Once again, be very cautious. Adequate reliability testing should be done to confirm reliability expectations. Use Table 8-2 as a guide for component compatibility with lead-free soldering process temperatures.
Figure 8-4 Thermal-fatigue crack propagation in Sn-3.8Ag-0.7Cu joints in a CBGA module [3]
may be necessary to solder tin/lead and lead-free BGAs on the same PCBA with tin/lead or lead-free solder. Soldering mixed alloy BGAs is an undesirable scenario, but it is likely to happen. The most likely scenario is soldering lead-free BGAs with tin/lead solder. This scenario occurs when a component supplier provides end-of-life (EOL) tin/ Table 8-2
for BGA balls typically contain Sn, Cu, and Ag. During the initial lead-free transition, the alloys used typically matched the assembly process alloys of Sn96.5Ag3.0Cu0.5 (SAC305), Sn95.5Ag3.8Cu0.7 (SAC387) or Sn95.5Ag4.0 Cu0.5 (SAC405). Problems such as balls dropping off and susceptibility to mechanical strain have led BGA suppliers to evaluate and suggest the use of additional alloys for the balls. For some packages, the change involves moving
Tin/lead component compatibility with lead-free reflow soldering
Tin/lead Component Type
Ceramic resistors/capacitors
8.2.2.2 Implementation of BGAs with Low-Ag SAC, or Non-SAC BGA Ball Alloys Lead-free solder alloys used
Compatibility
Okay
Molded capacitors (tantalum)
Use lead-free process temperature compatible components only
Aluminum electrolytic capacitors
Use lead-free process temperature compatible components only
Molded ICs (SO, PLCC, QFP)
Use lead-free process temperature compatible components only
Connectors, sockets, etc.
Use lead-free process temperature compatible components only
Crystals, oscillators
Use lead-free process temperature compatible components only
Transistors, diodes
Okay
LEDs
Use lead-free process temperature compatible components only
BGAs
May or may not be Okay. Evaluate on a case-by-case basis
DIP switches
Okay
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from silver (Ag) content of 3-4% down to 1-3%. The addition of other alloying elements has also been suggested; however, these additions can affect solder under-cooling, the formation of various intermetallics, unusual matrix properties and changes in solder microstructure. Depending on the specific alloy the melting point of the solder ball can increase by as much as 10°C. This can have a significant impact on the PCA assembly process. Great care must to be taken when introducing new alloys into BGAs and new alloyed BGAs into the assembly process. 8.2.2.3 PCA Manufacturing Impact The new lead-free BGA ball alloys may have an impact on the printed circuit assembly (PCA) reflow process due to higher melting point. Some component manufacturers have had unexpected yield losses due to low Ag alloys when they were not aware of their presence. The change to low Ag ball alloys may require a change to the PCA reflow target temperatures. For example, an increase of 10°C in melting point for a specific BGA may cause other locations on the PCA to exceed the temperature limits of either components or PCB.
Reliability Impact – Improperly assembled low Ag parts, assembled with too low of a reflow temperature, are at significant reliability risk since they may pass electrical test but may still produce an unacceptable solder joint (see Figure 8-5). Some experimental data suggests that the drop reliability of well manufactured low Ag parts seems to be better than current SAC alloys; however the thermal fatigue reliability of the new alloys is not currently understood. Additional factors (BGA pad and PCB land finish) are critical for reliability and are being investigated. 8.3 Solder Joints and Attachment Types Solder joints are not homogeneous structures. A solder joint consists of a number of different materials, many of which are only superficially characterized. A solder joint consists of:
1. The base metal at the printed board. 2. One or more intermetallic compounds (IMC). 3. The bulk solder. 4. A layer from which the solder constituent forming the component-side IMC(s) has been depleted. 5. One or more IMC layers of a solder constituent with the component base metal. 6. The base metal at the component. The grain structure of solder continues to change over time. At room temperature, eutectic tin/lead solder is above its recrystallization temperature; the grains will grow in size over time. The grain structure growth reduces the internal energy of a fine-grained structure. This grain growth process is enhanced by elevated temperatures as well as strain energy input during cyclic loading. The grain growth process is thus to some degree an indication of the accumulat-
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CSP Package
PCB
Unmelted solder ball
CSP Package
PCB Unacceptable solder joints
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Figure 8-5 Incomplete solder joint formation for 1% Ag ball alloy assembled at low end of typical process window
ing fatigue damage. This indication is significantly more pronounced for solder joints subjected to aging (and is less pronounced in cyclic testing) than for solder joints in operational use. Contaminants, like lead oxides and flux residues, sometimes migrate to the outer surface of the solder, but reside predominantly at the grain boundaries. As the grains grow, the concentration of these contaminants is increased at these grain boundaries, therefore weakening them. After the consumption of about 25% of the fatigue life of the solder, microvoids can be found at the grain boundary intersections; these microvoids grow into microcracks after ~40% of the fatigue life. These microcracks grow and coalesce into macro-cracks leading to total fracture of the solder joint, more or less. The solder joints frequently connect materials of differing properties, one of which is global thermal expansion mismatch. Solder often has properties significantly different than the bonding structure materials, causing local thermal 115
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expansion mismatches. The severity of these thermal expansion mismatches, and thus the severity of the reliability threat, depends on the design parameters of the assembly and the operational use environment. For lead-free solder joints there is a higher propensity for interfacial microvoiding due from either surface layer ‘cratering’ causing ‘champagne’ voids, also known as Planar Microvoids, or differential solid diffusion causing Kirkendall voids, also known as IMC Microvoids. The higher propensity for IMC microvoiding is associated, at least in part, with the higher soldering temperatures required for lead-free solders. Planar Microvoiding is seen on lead-free surface finishes such as Immersion Silver, which entail typically more complex soldering surface treatments than HASL. 8.3.1 Global Expansion Mismatch The global expansion mismatches result from differential thermal expansions of an electronic component or connector and the printed board to which it is attached via the surface mount solder joints. These thermal expansion differences result from differences in the CTEs and thermal gradients as the result of thermal energy being dissipated within active components. Global CTE mismatches typically range from about 2 ppm/°C for CTE-tailored high reliability assemblies to >=14 ppm/°C for ceramic components on FR-4 printed boards. Figure 8-6 is showing a solder joint failure due to CTE mismatch on a wafer level CSP. The silicon die on the top expands much less than the FR-4 substrate on the bottom. This causes shear stress on the solder joint, which eventually fails at the die to solder interface when subjected to temperature cycling stresses.
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to which it is soldered. These thermal expansion differences result from differences in the CTE of the solder and those of the base materials from thermal excursions. Local CTE mismatches typically range from ~7 ppm/°C with copper to ~18 ppm/°C with ceramic and ~20 ppm/°C with Alloy 42 and Kovar. Local thermal expansion mismatches typically are smaller than the global expansion mismatches, since the acting distance, the maximum wetted area dimension, is much smaller: in the order of hundreds of micrometers instead of thousands. 8.3.3 Internal Expansion Mismatch An internal CTE mismatch of ~6 ppm/°C results from the different CTEs of the tin-rich and lead-rich phases of the solder. Internal thermal expansion mismatches typically are the smallest, since the acting distance, the size of the grain structure, is much smaller than either the wetted length or the component dimension - in the order of less than 25 µm.
For lead-free solders, the metallurgy is more complicated due to the ternary or quarternary alloy composition concentrated at very high tin contents. 8.4 Solder Attachment Failure Failure of the solder attachment of a component to the substrate to which it is surface mounted is commonly defined as the first complete fracture of any of the solder joints of which the component solder attachment consists. Given that the loading of the solder joints is typically in shear, rather than in tension, the mechanical failure of a solder joint is not necessarily the same as the electrical failure. Electrically, the mechanical failure of a solder joint results, at least initially, in the occasional occurrence of a short-duration (<1 µs) high impedance event during either a mechanical or thermal disturbance.
From a practical point of view, the solder joint failure is defined as the first observation of such an event. For some applications this failure definition might be inadequate. For high speed signals with sharp rise times, signal deterioration prior to the complete mechanical failure of a solder joint might require a more stringent failure definition. Similarly, for applications which subject the electronic assemblies to significant mechanical vibration and/or shock loading, a failure definition that considers the mechanical weakening of the solder joints as the result of the accumulating fatigue damage might be necessary.
Figure 8-6 Solder joint failure due to silicon and board CTE mismatch 8.3.2 Local Expansion Mismatch The local expansion mismatch results from differential thermal expansions of the solder and the base material of the component or PWB
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8.4.1 Solder Attachment Failure Classification There are some common BGA failure signatures. These defects can be induced during the assembly process or they could be latent solder joint defects or failures. Such defects and/or failures are the result of an inadequate assembly process, defective material or excessive mechanical stress during assembly. The defects could be a partial open or very weak interfaces, the latent failures could be hairline
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cracks, open joint with a full contact and partially lifted land. They are difficult to detect using conventional process verification tools such as X-ray and ICT test. They are a major reliability concern since they can be intermittent. Subsequently, they are tracked down following high levels of fields returns. 8.4.2 Failure Signature-1: Cold Solder Cold solder joint is a result of a low peak temperature during the reflow process (
Figure 8-7
Grainy appearing solder joint
8.4.3 Failure Signature-2: Land, Nonsolderable Contamination on the PCB land will cause nonsolderable interface between the PCB land and the BGA ball. The solder will wet to the BGA ball but not to the land. There might be a partial or complete open with electrical contact. A failure with this signature could be a result of faulty nickel plating on the PCB with ENIG as a surface finish. One type of failure, known as ‘‘black pad,’’ is shown in Figures 8-8 and another type of failure is shown in Figure 8-9. It also could be a result of PCB supplier rework process and reapplying solder mask to the BGA area. 8.4.4 Failure Signature-3: Ball Drop This is an open solder joint which forms between the solder ball and the BGA component substrate. This causes the BGA ball to drop and creates elongated solder ball with round or a flat top. Ball drop is a failure caused by a high topside temperature during wave solder (>Liquidus-20°C). The Liqui-
Figure 8-8
Nonsolderable land (black pad)
Figure 8-9
Land contamination (solder mask residue)
dus temperature of a solder alloy is the temperature above which the whole solder volume is liquid. During wave soldering, the BGA balls are softening due to the high topside temperature. Thermo-mechanical stress is causing the balls to pull away from the component substrate and create an open joint as shown in Figure 8-10. Ball drop can also be caused by high peak temperature and dwell time during reflow.
Figure 8-10
Solder ball down
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8.4.5 Failure Signature-4: Missing Ball Missing solder ball during ball attached process or due to handling damage is shown in Figure 8-11. This defect signature is usually very clear and is easy to detect with X-ray or ICT techniques.
Figure 8-11
Missing solder ball
8.4.6 Failure Signature-5: Package Warpage This signature occurs when the BGA is warping during the reflow process as shown in Figure 8-12. The worst case situation is low end package warpage (concave shape). The interface between the solder ball and the solder paste is not wetted. Both the solder paste and the BGA balls are reflowed. In
some cases this signature might be associated with elongated joints (column) adjacent to the failed one. 8.4.7 Failure Signature-6: Mechanical Failure Mechanical stress caused by board flexing from in-circuit testing is not uncommon in PCB assembly. As the size of the BGA becomes larger, the stress experienced by corner joints becomes more significant. Even probing beneath and surrounding the BGA is required. Mechanical stress caused by probe pins and vacuum force is sometimes ignored. It is important to note that excessive monotonic stress induced by mechanical stresses will lead to solder joint failures.
Since the weakest interface is the one that breaks, this failure signature could be different. The crack could be within the BGA ball or at the PCB or package interface or within the PCB as a lifted land (pad ‘‘cratering’’). Figure 8-13 shows two examples of a lifted corner land caused by excessive mechanical stress. This defect is also termed as pad cratering.
BGA is placed on solder paste.
BGA warped. Ball & paste are molten but not touching.
After cooling, paste is solidifying & causing indentation on the molten ball.
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Figure 8-12
118
Deformed solder joint due to BGA warping
Figure 8-13 Two examples of pad cratering (located at corner of BGA)
Pad cratering can result in a failure of the joint due to electrical opens. The initial crack weakens the joint mechanically. As it progresses, the crack may intercept electrical
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traces causing an open. This is shown in Figure 8-14. Failure by this signature is enhanced by the higher temperatures of lead-free reflow temperatures, harder laminates, and increasing land or trace densities.
Figure 8-14 Pad crater under 1.0 mm pitch lead-free solder ball. Crack in metal trace connected to the land is clear; however, the pad crater is difficult to see in bright field microscopy.
The robustness of the BGA joints against mechanical stress is a function of several factors: • Location of the BGA • Thickness of the PCB
Figure 8-15A
Insufficient reflow temperature
Sometimes, insufficient reflowed solder joints occur due to the existence of a feature on a component, such as a cam on a socket, sinking away the heat from that area during the reflow process. Figure 8-15B below illustrates an example of insufficiently melted solder joints due to this reason.
• Stack Up
8.5 Critical Factors to Impact Reliability
• Land Size
8.5.1 Package Technology Area array components come in a variety of styles and materials. The majority of the commercial array devices utilize plastic encapsulation and a reinforced rigid organic substrate interposer material for packaging. For package-to-board interconnect, a metallized land or alloy sphere (ball) is employed. Land grid array (LGA) packaged ICs are often specified when package height is an issue, while the ball grid array (BGA) uses small alloy spheres for the interconnect system. The contact alloys furnished on the majority of the plastic based BGA is a Sn/Pb (eutectic) or a Sn/Ag/Cu (lead-free) composition. Area array packages using a ceramic based substrate interposer may be supplied with high-lead solder ball or solder column, e.g., Pb90/Sn10. A growing number of area array package variations adapt nonreinforced film dielectric for the substrate and a diverse combination of encapsulation materials. Miniature fine-pitch (FBGA) and die-size package (DSP) are also widely used (especially in portable or hand-held electronic products) and many higher power applications incorporate an in-package heat spreader or heat-spreading layer (see Section 4).
• Stiffening Mechanism • Solder Volume • Solder Mechanical Properties • Solder Creep Properties • Quality of solder Joint Interfaces As a remedy, some designers especially in the cell phone industry had adopted larger corner lands, elongated lands, and underfill to enhance robustness. From the assembly perspective, enforcing proper fixturing and handling are keys to avoid solder joint damage. 8.4.8 Failure Signature-7: Insufficient Reflow This failure signature occurs when the BGA ball does not receive sufficient heat for the solder to reach a temperature above liquidus temperature of the solder. Figure 8-15A shows a classical example of the result of insufficient reflow profile; the solder ball never became sufficiently liquid to meld with the solder on the land pattern.
Insufficiently reflowed solder joints, when they occur, are typically found underneath the center portion of the BGAs, because those areas heat the slowest during soldering process, and would be the most prone to not reaching adequate soldering temperatures.
Long-term reliability of the solder attachment of the area array package, when soldered to a conventional printed board, is of primary concern. The difference in the coefficient of thermal expansion (CTE) for materials can 119
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Figure 8-15B Cross-section photographs illustrating insufficient melting of solder joints during reflow soldering. These solder joints are located below the cam of a socket.
generate undue stress to the solder interface. The solder attachment integrity for area array packages will vary, depending on the loading conditions to which the solder joints are subjected and the reliability requirements for the product. CTE mismatch is further aggravated when large silicon die are attached to an organic substrate with a noncompliant epoxy compound. Silicon CTE is near 3 ppm/°C while the organic substrate is closer to 16 ppm/°C. Package warp during assembly processing and even the power dissipation within the package can subject the solder joints to significant tensile stresses. Excessive stress and strain at the solder interface will cause solder joint failure and even separation of the metallized lands. When the die is attached to the package substrate with rigid epoxy, the substrate material directly beneath the die may be restricted to a CTE nearer that of the die. When solder balls are retained in the same zone and exposed to a wide variable of operating temperature, the solder interface will be subjected to excessive strain. For ‘cavity-up’ components (die attached facing away from the package substrate), only a thin dielectric layer separates the solder joints from the die. The larger the die is, the more acute the concerns for solder attachment reliability. Furthermore, when the BGA solder joints fracture, they are typically near the ball-to-package interface. This is a consequence of the local expansion mismatch between the solder and the dieconstrained BGA substrate. The current trend for larger BGA package outlines is to move the contacts toward the package perimeter, with the possible exception of some thermal solder balls and vias retained at the central area of the package. Several manufacturers that cannot move the ball contact outside the die attach area have adapted a more compliant die attach material. The compliant die-to-package interface is slightly 120
thicker and exhibits a dramatic reduction in stress at the solder-to-board interface, furnishing a substantial increase in fatigue life. 8.5.2 Stand-off Height Stand-off height significantly affects reliability of solder joints. The higher the stand-off, the better is the reliability of solder joints. BGAs attached with Sn63Pb37 solder balls result in solder joint heights that are less controlled and lower (height~400 to 640 µm), while the Sn10Pb90 solder balls (diameters of 760-890 µm) result in uniform solder joint heights of the same dimension since the Sn10Pb90 solder has a Liquidus temperature significantly above the near-eutectic tin/lead solders and does not melt during a typical reflow process. Table 8-3 provides information on typical stand-off heights for tin/ lead ball and solder paste metallurgy packages. Table 8-3 Typical stand-off heights for tin/lead balls (in mm) Ball Pitches
Stand-off Heights
Ball Diameter Prior to Reflow
PCB Land Size
1.27
0.40-0.60
0.75
0.65
0.45-0.55
0.60
0.45
0.35-0.45
0.50
0.40
0.30-0.40
0.45
0.35
0.35-0.45
0.50
0.40
0.30-0.40
0.45
0.35
0.28-0.35
0.40
0.35
0.18-0.25
0.30
0.25
0.18-0.26
0.25
0.25
0.08-0.15
0.17
0.25
1.00
0.80
0.50
Weight of the package also affects reliability of solder joint since it impacts solder joint or stand-off height. The key factors that control stand-off are land size, available solder
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volume, and the weight of the component. The lower the weight the smaller the land size and the larger the solder volume, the higher the stand-off. 8.5.3 PCB Design Considerations Another influence on reliability is the geometry of the solder joints as well as the solder land metallization. Solder masks can have a negative influence if they are used for solder mask-defined (SMD) lands with the solder mask on the metallization lands affecting the solder joint geometries. Stress concentrations created by the SMD solder joint geometries can be the origin of solder joint failures and reduced reliability. More than that, the solder mask shape and thickness could influence the reliability of the solder joint. Figure 8-16 shows crack due to stress concentration at the solder mask.
extensive internal resources to validate reliability of solder joints with via in pad technology. Microvias are becoming more common in BGA lands. Most of the BGAs will have voids whenever microvias are used. Studies showed that most voids are not a reliability risk to initiate a crack, however, they reduce the joint area and will shorten the time to failure when a crack is propagated. Figure 8-17 shows a failure after reliability testing where the void was so large the ball collapsed.
Figure 8-17
Reliability test failure due to very large void
8.5.4 Reliability of Solder Attachments of Ceramic Grid
Figure 8-16
Solder mask influence
For equal solder joint height, increases in fatigue life by factors of about 1.25 to 3 can be anticipated with the use of nonsolder mask defined (NSMD) vs. SMD lands with the larger improvements for solder joints with the more severe loading conditions. Surface finish also plays a critical role in BGA solder joint reliability. HASL, a commonly used surface finish may be too thick or too thin. Insufficient solder thickness may be consumed as intermetallic, which is unsolderable. Immersion gold over electroless nickel is prone to the black pad defect which leads to brittle interfacial solder joint failures under mechanical and/or thermal stress. The ‘‘black pad’’ defect is thought to be caused by excessive corrosion of the nickel during the gold plating process. Laminate cracking is also a possible failure mechanism under BGA solder joint lands. Such failure is thought to be caused by thermal mechanical stress during reflow and or subsequent mechanical stresses on the joints. Via-in-pad or via next to land may cause drainage of solder. This is generally not recommended. Via-in-pad is being tried by some companies with successful results. However, such an approach should be considered only by companies with
Array Ceramic CTE is about 6 ppm/°C; the CTE of organic-based PCBs is in the range of 16-20 ppm/°C. Thus, a global CTE-mismatch of about 10-14 ppm/°C exists between ceramic components and organic printed boards. To compensate for the large global CTE-mismatch, ceramic components typically require solder columns to function reliably in most applications. Since the corner joints are loaded more than other solder joints (they are farthest from the neutral point or DNP), they fail first.
The solder columns, which currently are only used for ceramic GACs, are 10Sn/90Pb columns with lengths of 1.27 mm to 2.29 mm that are either cast onto the CGA or are wire soldered to both the CGA and the substrate with near-eutectic tin/lead solder. The ratios of fatigue lives, all parameters other than the solder joint height being equal, are CBGA (0.41 mm [16 mils]): CBGA (0.76 mm [30 mils]): CGA (2.29 mm [90 mils]) = 1:4:45. The height of the solder columns is limited by the requirement that the column aspect ratio (height-to-diameter) does not produce slender columns thus changing the loading conditions; cast columns can accommodate larger aspect ratios. 8.5.5 Lead-Free Soldering of BGAs The reasons for conversion to lead-free soldering processes are first enumerated followed by a description of various available lead-free alloys and their selection. Board design and assembly consideration for BGAs are described next with a discussion on the transition technologies that occur when
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converting from a tin/lead to a lead-free package and assembly concluding this section. 8.5.5.1 Drivers for Lead-Free Technology There are two drivers for corporations to convert their products from those containing the ubiquitous tin/lead solder to a leadfree solder. One is a legislative driver and the other is a marketing driver.
The current legislative driver for eliminating lead in electronics and electrical equipment is the Restrictions on Hazardous Substances (RoHS) Directive (2002/95SEC). The RoHS Directive states that lead, mercury, cadmium, hexavalent chromium and two brominated flame retardants cannot be present in electrical and electronic equipment that enters the market in the European Union (EU) after 1 July 2006. Currently there is no legislation in either the United States or Japan that restricts the use of lead in electronic products. There are requirements in Japan to recycle a limited number of used electronic equipment including PCs, CRTs, TVs and White Goods. There is also a new EU Directive on Waste in Electrical and Electronic Equipment (WEEE). It requires that the waste be managed and recycled according to the Directive which took effect in 2005. The other driver is a marketing driver. Corporations are developing and introducing lead-free products as a marketing initiative. Essentially, they do not want to be upstaged by competitors who could introduce lead-free products before them. 8.5.5.2 Lead-Free Alloy Selection Ideally, the lead-free alloys selected should be drop-in replacements for the currently used tin/lead (Sn-Pb) alloys. Drop-in replacement alloys do not require any significant change in the materials, equipment and processes for package and board assembly. Unfortunately, no such drop-in replacement exists within the list of potential lead-free solder alloys that are currently available.
The seminal work to select the best lead-free solder alloys in existence was the three year study undertaken by the National Center for Manufacturing Sciences (NCMS). This study culminated in a report that covered the evaluation of over 79 lead-free solder alloys. Table 8-4 shows some of the common lead-free solders that were evaluated by the NCMS group. These are listed according to their melting points. The overwhelming majority of these alloys are tin-rich alloys (>90%Sn) with Sn respectively forming binary or ternary systems with other elements such as Bi, Zn, Sb, Ag, and Cu. The melting points and the advantages and drawbacks for these alloy systems as well as other potential alternatives are listed in the table. 122
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The tin-rich alloys noticeably have ~30-40°C higher melting points than eutectic tin/lead solder (melting point, mp = 183°C). Alloys with lower or comparable melting points are scarce. Some consortia around the world have selected alloys from the Sn-Ag-Cu family as the lead-free solders of choice. In determining this final choice of the alloy family as well as the particular alloy compositions, many factors were considered and evaluated. These included: • Melting temperature. • Wettability to common component substrate and board surface finishes. • Compatibility to common fluxes, particularly no-clean fluxes. • Component and board reliability. • Mechanical, electrical and thermal properties. • Reworkability. • Compatibility with lead (during transition period). • Availability from suppliers. • Cost. • Patent concerns. Table 8-5 compares the composition selected by three consortia. The compositions are very close to each other and behave very similarly in the reflow soldering process. Further, solder alloy suppliers usually state a tolerance of ± 0.2% by weight for each elemental component of the solder, which is consistent with the ANSI J-STD-006 specification. When taking this into consideration, the alloy compositions below all overlap. 8.5.5.3 Recommendations for Alloys with Ag Content around 1%:
• Solder joints must reach a minimum of 235°C with a TAL of at least 60 s. • Reflow profiles for some PCAs may need to be modified when BGAs with low Ag alloys are used. • At a minimum, reflow profiles may need to be validated using metallography, requiring additional engineering effort. Along with careful oven profiling, metallography should be performed (with statistically significant sample sizes) to validate that components with low Ag solder ball alloys are forming proper joints. The number of thermocouples used to validate a profile should be significantly increased so that the low-Ag component can be shown to meet the conditions given above, and that all other components meet the existing specifications (no overheating). The 1% Ag alloys appear to be incompatible with many current industry lead-free assembly specifications that require a minimum reflow peak temperature/TAL of
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IPC-7095B Table 8-4
Alloys or Alloy Systems
Common solders, their melting points, advantages and drawbacks
Melting Point (°C)
Advantages
Drawbacks
Sn95Sb5
240
Good fatigue resistance.
Higher toxicity than lead; high melting temperature; 8°C pasty range; poor wetting; low tensile strength.
Sn99.3Cu0.7
227
Low cost in comparison to other lead-free solders; not prone to fillet lifting in the absence of lead.
Reduced wettability in air, but adequate in an inert atmosphere.
Sn96.5Ag3.5
221
One of the primary choices by NCMS study; used for many years in certain applications; fatigue properties are similar to tin/lead solders for some accelerated reliability test results.
Poorest wetting in reflow soldering among high-tin alloys; though wettability still adequate for most board assembly operations.
SnAgCu
217-220
Better creep resistance than tin/lead solders; fatigue properties are better than tin/lead solders for some accelerated reliability test results. Optimum pasty range for tombstone control.
Prone to fracture in high shock applications. Some compositions are patented.
SnZnBi
191-199
Closest in melting point to tin/lead alloys; better strength than tin/lead solders; fatigue properties are better than tin/lead solders for some accelerated reliability test results.
Very susceptible to oxidation and corrosion but small amount of Al could alleviate these problems; requires special fluxes and solder processes for achieving acceptable manufacturing yields.
Sn91Zn9
199
Sn63Pb37
183
Most widely used solder alloy.
Contains lead.
Sn62Pb36Ag2
179
Higher tensile strength, pasty range for anti-tombstone, greater creep resistance
Contains lead, more expensive.
Bi58Sn42
139
One of the alloys down-selected by NCMS; presently used in low temperature applications.
Melting point is too low for computer applications; susceptible to formation of low melting ternary phase by lead contamination.
In52Sn48
118
One of the lowest melting point solders.
Indium supplies are limited; melting point too low for computer applications; susceptible to corrosion.
Table 8-5 Comparison of lead-free solder alloy compositions in the Sn-Ag-Cu family selection by various consortia % Ag
be expected. A reduction in under cooling is required to solidify the BGA ball.
Consortium
% Sn
% Cu
IDEAL
95.5
3.8
0.7
Solder Products Value Council
96.5
3.0
0.5
iNEMI
95.5
3.9
0.6
230°C/60 s, while current specifications are likely adequate for other alloys. The actual limit in Ag content at which significant change to the lower limit of the reflow profile is needed has not been precisely identified. It appears to be between 1% and 2.3% Ag. Other variables may impact this value, so caution is warranted for any alloy with less than 3% Ag. Reliability of Solder Joints – Industry studies consistently indicate better drop performance for low Ag alloys than for near-eutectic SAC. Results depend on the solder land finishes in addition to alloy composition. The exact reason for the improvement is still being debated. It may be due to reductions in the stiffness and yield strength of the bulk solder ball. It is known that changes to the intermetallic layer composition and/or structure of the solder joint can
The impact of ball alloy on thermal fatigue resistance is unclear at this time. There is conflicting data for the trend of fatigue life vs. Ag content. There are currently no acceleration models available for these alloys, making product life predictions impossible. There are very few study results available so it is not clear how low Ag alloys perform relative to eutectic tin/lead as well. Managing the Change to a Low Ag Ball Alloy – Due to the potential impacts on reflow process window and reliability, changing from a near-eutectic SAC ball alloy to one with less than 3% Ag should be considered to be a change in form, fit, or function. In this case a change in part number for any BGA component, where the only change is ball alloy, is considered appropriate. 8.5.5.4 Board Design Considerations Board Design for BGA Assembly with Lead-Free Solders is generally very similar to that for presently used tin/lead solders. The same Design for Manufacturability (DfM) rules and guidelines should be applied for lead-free boards as those used to tin/ lead (SnPb) boards. These include consideration for component orientation, soldering, via holes, solder mask,
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repairability and testability. Some of these are described further below.
rial type, surrounding components, location of part on the board, and package densities.
BGA Land Pattern Designs – As in the case of tin/lead BGA soldering, the preferred BGA Land style for SnAgCu soldering is the nonsolder mask defined design as opposed to the solder mask-defined land style since it allows the maximum flexibility for the PCB designer, and less stress points are introduced to the solder joint by the solder mask.
To avoid moisture and thermo-mechanical stress induced failures on plastic components, it is best to measure the temperature of the component body and check to ensure that it doesn’t exceed the maximum temperature it is rated for. Hence, thermocouples, which are generally used to measure the temperatures during reflow profiling, should be attached at the solder joint as well as the body of the various components during reflow profiling of board assemblies. Large components generally have greater than 5°C difference between the leads/solder balls and the molding compounds of the component.
Component Placement Location on the PCB – Since SnAgCu solders require higher reflow temperatures for component soldering, the placement location of large, temperature sensitive BGA components may need to be addressed carefully. The regions near the edges of the board are, depending on the board size, thickness and layer count, typically 5-15°C higher in temperature than those in the central locations. Since large packages are more prone to moisture and thermal stress induced defects when subjected to higher reflow temperatures, such packages, if possible, should be confined to the central regions of the board. Other factors, such as trace routability and density, may make it necessary to place large BGAs at the edges of the board. In such cases, the reflow soldering process window will be narrowed to keep the maximum temperature the BGA components are exposed to below acceptable limits. Reflow soldering is commonly done in an IR convection oven with heated air convection. Despite the higher reflow temperatures necessary to melt the SnAgCu (SAC) solders when compared with the tin/lead solders, new equipment may not be necessary for lead-free reflow soldering. The same ovens as used before for tin/lead solders can be used with the obvious increase in the settings for the various heating zones in the reflow oven. Having said that, as the PWB mass increases the ability to limit the maximum reflow temperature, delta T across the PWB and reflow time becomes more difficult without extended zone ovens. 8.5.5.5 Reflow Soldering Considerations
The environment in the oven can be either air or inert, such as nitrogen. For lead-free soldering, to minimize the oxidation of the materials on the board assemblies during the high temperature reflow operation, an inert atmosphere can be helpful. A lot of the criteria depends on the solder paste and the solder paste manufacturer as well as the thermal mask of the electronic assembly. Some board surface finishes, such as organic solderability preservatives (OSP) on copper may require an inert atmosphere during reflow soldering to attain acceptable solder joint yield levels. A reflow solder profile should be developed for all board assemblies. Since SAC solders require higher reflow soldering temperatures, it is important to determine the maximum temperature at various different locations on the board. Component temperatures may vary because of mate124
A typical SAC reflow profile is compared with a tin/lead reflow profile for a BGA solder joint in Figure 8-18. Four different regions of the reflow profile are shown: the Preheat region during which the low melting volatile ingredient in the solder paste vehicle are evolved; the Flux Activation region which enables the temperature to start equilibrating across the board and to start to activate the flux; the Reflow region where the solder melts, wets the land surface and forms the solder joint; and finally the Cool down stage, where the solder solidifies and the board assembly exits the oven to be cooled down by forced air blown down on the board by fans. The profiles illustrated in Figure 8-18 are termed ‘‘FAT’’ (flux activation time) profiles since they have a soak zone before the solder is reflowed. Alternatively, ‘‘ramp’’ profiles can also be developed which contain a continuous ramp from the preheat zone to the reflow soldering zone. These ramp profiles increase the throughput of the board assemblies in the reflow ovens. But, care should be taken to avoid overheating of components, particularly on the edges of the boards. 8.5.5.6 Appearance of BGA Lead-Free Solder Joints
The BGA package body obscures its solder joints. However, with the help of special microscopes such as the endoscope, peripheral solder joints can be viewed. SnAgCu solder joint microstructures are multiphase microstructures and the surface of the solder joints appears rough. Figure 8-19 shows a typical SnAgCu BGA solder joint. This is much different from typical SnPb BGA solder joints which usually have a shiny surface. The transition from a total tin/lead soldering system to a total leadfree soldering system is not going to happen overnight. There may be an interim phase where tin/lead and lead-free solders will co-exist on board assemblies because the timing and the technology readiness in the various sectors of the electronic manufacturing industries are not in sync. This transition phase entails that the impact of lead in the SAC solder be evaluated for impact on solder joint yields and reliability. 8.5.5.7 Transition Lead-Free Technologies
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IPC-7095B
257
Lead Free Solder Profile Reflow @ 217°C Peak Temp = 235 to 245°C
227
197
Temperature
167
137
107
Tin-Lead Solder Profile Reflow @ 183°C Peak Temp. = 205 to 220°C
77
47
17 0.0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8
Time in Minutes
Figure 8-18
5.4
6.0
IPC-7095b-8-18
Comparison of a lead-free (SnAgCu) and tin/lead (SnPb) BGA reflow soldering profiles Table 8-6
Types of lead-free assemblies possible Component Termination/ BGA Ball
Solder Paste
Forward compatibility
contains lead
lead-free
may contain lead
Backward compatibility
lead-free
63Sn37Pb
may contain lead
Total lead-free
lead-free
lead-free
lead-free
Definition
Board Surface Finish
having a conversion date later than the board assembler’s conversion date. This results in the tin/lead solder joints of the BGA-type components being ‘contaminated’ by the lead replacement metals in the lead-free solder paste.
Figure 8-19 ball
Endoscope photo of a SnAgCu BGA solder
The various lead-free board assemblies possible during this transition phase are listed in Table 8-6. The first possible lead-free board assembly listed above is ‘‘forward compatibility.’’ The board assembly soldering process for forward compatibility assemblies has been converted to lead-free technology with a change in the solder paste composition and the reflow soldering profile to match this change. However, some components, such as BGAs that are soldered on the board, will still have tin/lead solder due to the component supplier’s lead-free roadmap
The second possible lead-free board assembly listed above is ‘‘backward compatibility.’’ Backward compatibility scenarios arise when component suppliers introduce the leadfree components, but not all board assemblers that use these components have converted their board assembly lines to lead-free technology. These assemblers will still be soldering the lead-free components with the ubiquitous eutectic tin/lead solder paste using tin/lead reflow soldering profiles. A tin/lead component would obviously be preferable in this case, but the component suppliers may, due to economic reasons, not want to carry two component line items, one tin/lead and one lead free, for the same device. The solder joints formed with this combination of materials will have lead ‘‘contamination’’ in the lead-free solder balls for BGA type components. When soldering a Ball Grid Array package with SnAgCu lead-free solder balls using tin/lead solder paste, two different scenarios arise based on the reflow profile used. The two reflow profiles compared are shown in Figure 8-20 with the total lead-free reflow profile also shown for comparison. 125
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300 Typical Lead Free Solder (SnAgCu) Profile
Temperature, Deg C
250 Tmelting for SnAgCu 200 Tmelting for SnPb 150 SnAgCu Balls do NOT Melt Not good for backward compatibility
100
SnAgCu BAlls Melt Will be OK for backward compatibility
50
0
0
50
100
150
200 Time, Seconds
Figure 8-20 blies
250
300
350
400 IPC-7095b-8-20
Comparison of reflow soldering profiles for tin/lead, backward compatibility and total lead-free board assem-
The tin/lead reflow profile, which is illustrative of the profile used today for tin/lead assemblies, does not exceed the melting point of the BGA’s SnAgCu solder ball. This causes an impact to solder joint yield and reliability. The tin/lead solder paste deposited on the lands of the solder balls melts but the SnAgCu solder balls are still not molten. The lead diffuses through the grain boundaries of the still solder ball. How high the lead from the tin/lead solder diffuses up the SnAgCu solder ball will depend on how high the reflow temperature gets and for how long the tin/lead solder is molten. As shown in Figure 8-21, which depicts a micrograph of a cross-section of a SnAgCu solder ball of a BGA package soldered to a board using the standard tin/lead profile, the resulting solder joint microstructure is inhomogeneous and unstable. This deleteriously impacts the solder joint reliability. Yield impact on such solder joint is also deleterious due to two reasons. One is due to the poor self-alignment of the BGA during reflow soldering because the solder ball does not become molten. This creates a potential for open joints when the component is misaligned to some extent during or after the Placement process step. Secondly, the lack of ‘‘ball collapse’’ may cause open solder joints from a lack of contact between the solder paste deposit and the solder ball. Hence, for better solder joint yields and solder joint reliability, the backward compatibility reflow soldering profile depicted in Figure 8-20 should be used. During this reflow profile, the SnAgCu solder ball also melts, and lead from the molten tin/lead solder paste mixes thoroughly with molten SnAgCu solder ball and generates a homogeneous, refined structure of a lead-rich phase in the tin matrix. Such a microstructure is shown in Figure 8-22. 126
Figure 8-21 Micrograph of a cross-section of a BGA SnAgCu solder ball, assembled onto a board with tin/lead solder paste using the standard tin/lead reflow soldering profile. The SnAgCu solder ball does not melt; black/grey interconnecting fingers are lead-rich grain boundaries; rod shape particles are Ag3Sn IMCs; grey particles are Cu6Sn5 IMCs.
Moreover, since the SnAgCu solder ball melts and collapses, the self-aligning process and coplanarity reduction also occur, thereby enhancing solder joint yields of the BGA. 8.5.5.8 Ball Replacement Due to limited availability of components with SnPb balls, some functional designs may require ball replacement of the BGA component to allow common processing with tin lead production assemblies. This practice, while commonly employed, has drawbacks due to the additional thermal cycles required for the ball removal and subsequent replacement. Additionally, the resulting interface alloy at the component to ball attachment site may not achieve the desired or expected eutectic
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IPC-7095B
Detailed procedures for BGA Reballing are available in IPC-7711/21B, ‘‘Rework, Modification and Repair of Electronic Assemblies.’’ 8.6 Design for Reliability (DfR) Process As a general recommendation, the Design for Reliability procedures detailed in IPC-D-279 should be followed.
Appropriate DfR measures to improve reliability for grid array components take one of two forms, which are best employed in combination for improved reliability margins. These measures are: 1. CTE-tailoring to reduce the global expansion mismatch. Figure 8-22 Micrograph of a cross-section of a BGA SnAgCu solder ball, assembled onto a board with tin/lead solder paste using a backward compatibility reflows soldering profile. The SnAgCu solder ball has melted.
properties. The process however does allow the use of limited component types to comply with tin lead use strategies for performance, contract mandates, and/or compatibility with legacy or production designs that are susceptible to the additional temperature excursion required for lead free production processes. The sphere replacement process avoids paste alloy, PCB surface finish, and component finish compatibility issues that can be very complex to balance for successful production results. Reballing of BGA components involves removal of the original balls with a localized heat source such as a vacuum desoldering tool, blade tip or solder wick. The component surface is then cleaned and prepared for attachment of new spheres that are located with a fixture that aligns to the original pattern of the component. The spheres are then attached to the component using a typical rework heat source such as a convection reflow oven, or the fixture with component and replacement spheres can be placed in a reflow oven. As an alternate when many parts are to be reballed, one can use automated laser systems that will pick and place balls from a tray and then reflow them in place on the BGA substrate using the laser beam. In either case, the heat source must be controlled using a thermal profile appropriate for the component and new ball alloy. Once the balls are attached, the BGA package is removed from the fixture and the balls can be examined and cleaned in preparation for installation and soldering with the remainder of the assembly components. As with all BGA component processes, moisture and ESD sensitivity must be considered. BGA balls are commonly available in a wide range of solder alloys and dimension but they must be selected for compatibility with other process elements such as the board surface plating and solder paste. It is also critical to maintain the component design spacing and pitch through proper ball size and placement.
2. Increasing attachment compliancy to accommodate the global expansion mismatch by increasing the solder joint height (stand-off). Further, a DfR procedure aiming at high-reliability could also include: 3. Eliminate the effect of the global expansion mismatch by mechanically coupling the component and the substrate with an appropriate underfill. 4. Choosing a soft die attach to reduce the impact of the low die CTE (2.7 to 2.8 ppm/°C) on both the global and local thermal expansion mismatch. CTE-tailoring involves choosing the materials or material combinations of the multilayer board and/or the components to achieve an optimum CTE. An optimum CTE for active components dissipating power is ~1-3 ppm/°C (depending on the power dissipated) with the multilayer board having the larger CTE, and 0 ppm/°C for passive components. Of course, since an assembly has a multitude of components, full CTE optimization cannot be achieved for all components—it needs to be for the components with the largest threat to reliability. For military applications with the requirement of hermetic and thus ceramic components, CTE-tailoring has meant the CTE-constraining of the multilayer boards with such materials as Kevlar™ and graphite fibers, or copper-Invar-copper and coppermolybdenum-copper planes. Such solutions are too expensive for most commercial applications for which glassepoxy or glass-polyimide are the materials of choice for the multilayer boards. Thus, CTE-tailoring has to take the form of avoiding larger size components that are either ceramic (CGAs, MCMs), plastic with Alloy 42 lead frames (TSOPs, SOTs, or plastic with rigid bonded silicon die (PBGAs). Increasing attachment compliancy for leadless solder attachments means increasing the solder joint height (C4, C5, shimming, gluing, 10Sn90Pb balls, 10Sn90Pb columns) or switching to a leaded attachment technology. For leaded attachments, increasing lead compliancy can mean changing component suppliers to those having lead geometries promoting higher lead compliancy or switching to fine-pitch technology. 127
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The DfR process needs to emphasize a physics-of-failure perspective without neglecting the statistical distribution of failures. The process might involve the following steps: • Identify Reliability Requirements – expected design life and acceptable cumulative failure probability at the end of this design life. • Identify Loading Conditions – use environments (e.g., IPC-SM-785) and thermal gradients due to power dissipation, which may vary and produce large numbers of minicycles (Energy Star). • Identify/Select Assembly Architecture – part and substrate selections, material properties (e.g., CTE), and attachment geometry. • Assess Reliability – determine reliability potential of the designed assembly and compare to the reliability requirements using the approach shown here, a ‘‘Figure of Merit’’ approach, or some other suitable technique; this process may be iterative. • Balance Performance, Cost and Reliability Requirements. 8.7 Validation and Qualification Tests Performance test methods and qualification requirements are specified in IPC-9701; IPC-9701A includes guidelines for lead-free solder joint reliability testing. However, in the current absence of generally useful reliability acceleration models, there currently are no qualification requirements for lead-free solder joint.
The validation and qualification tests should follow the guidelines given in IPC-SM-785, Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments. However, for large components with significant heat dissipation, for components of asymmetric construction, and for small global CTE-mismatches, temperature cycling tests are inadequate to provide the required information;
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full functional cycling including external temperature and internal power cycling is necessary. 8.8 Screening Procedures 8.8.1 Solder Joint Defects The solder joint defects of greatest reliability concern are those involving inadequate wetting for whatever reason. Properly wetted solder joints have adequate strength even for severe mechanical loading conditions as well as no diminished thermal cyclic fatigue reliability. However, solder joints not properly wetted, can prematurely fail both as the result of mechanical and thermal cyclic loading.
Voids in the solder joints are generally regarded as not constituting a reliability threat. Possible exceptions are large voids reducing the solder joint cross-section enough to reduce a required thermal heat transfer function, and voids in high-frequency applications where the voids can cause signal deterioration. BGA components having noncollapsible balls (high temperature solder 90% Pb 10% Sn, with a melting point of 302°C) typically will have few or no induced voids because the ball solder never melts during the reflow profile. 8.8.2 Screening Recommendations Effective screening procedures need to be capable of causing the failure of latent solder joint defects, i.e., weak inadequately wetted solder joints, without causing significant damage to high quality solder joints. The best recommendation is random vibration (6-10 grams for 10-20 minutes), preferably at low temperature, e.g., -40°C. This loading does not damage good solder joints, but overstresses weakly bonded ones. Thermal shock can also be successfully used, however some damage to good solder joints can be expected, particularly for larger components.
March 2008 9 DEFECT AND FAILURE ANALYSIS CASE STUDIES
IPC-7095B 9.1.2 Solder Mask Defined Land on Product Board
The following clauses identify possible assembly anomalies related to the assembly of BGA components. The descriptions include post process failures related to the mounting structure characteristics and the variation in the solder ball used as the BGA termination. In many instances attachment metallurgy are discussed especially if the characteristics contributed to the joint failure. Final joint configurations are also analyzed. 9.1 Solder Mask Defined BGA Conditions There are two ways BGA Lands are defined: solder masked defined (SMD) where the land size is larger than solder mask and the molten BGA ball touches the solder mask after reflow. The other method for designing the BGA land is called etched or nonsolder mask defined (NSMD) where the mask opening is larger than the copper land and hence the ball does not touch the solder mask after reflow. This condition is shown in 9.1.1 and 9.1.2. 9.1.1 Solder Mask Defined and Nondefined Lands
Possible Cause Solder mask encroaches too far on land at board level. This condition creates stresses in the ball that can propagate a crack during temperature changes. Potential Solution Always design product boards using only metal-defined (NSMD) lands.
The main disadvantage of solder mask defined land is that the stress concentrations created by SMD (solder mask defined) solder joint can be the origin of solder joint failures and reduced reliability. This condition is shown in 9.1.3. For equal solder joint height, increases in fatigue life by factors of about 1.25 to 3 can be anticipated with the use of nonsolder mask defined (NSMD) vs. SMD lands, with the larger improvements for solder joints with the more severe loading conditions. There are three main disadvantages of SMD lands: • Less real estate for topside breakout Possible Cause Interposer is solder mask defined; board is metal-defined. If the two areas are very different the stresses are not uniform and cracks may occur at the solder mask defined side. Board land pattern too large.
• Loss of accuracy of land dimension • Reduced reliability as it is the origin of early solder joint failure
Potential Solution Area of the two attachment conditions should be similar or identical. In addition solder mask defined lands create additional stress and should be avoided on both the interposer and the printed board land.
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IPC-7095B 9.1.3 Solder Mask Defined BGA Failures
Crack starts in the solder and eventually travels down to and through the intermetallic layer. Nickel buildup under the solder mask is also evident. Possible Cause Crack starts in solder at sharp corner of solder mask. The condition due to stresses in the ball caused crack propagation. Potential Solution Always design product boards using only metal-defined (NSMD) lands.
9.2 Over-Collapse BGA Solder Ball Conditions The plastic BGA, generally, has solder balls that collapse to about 625 µm from its original size of 750 µm. After the package is soldered to the board, the ball collapses to about 500 µm. However, if there is a heat spreader or a heat slug in the package for heat dissipation, the ball may collapse to as low as 300 µm. As the ball flattens there is a decrease in reliability due to limited solder height and solder joint compliancy. Also, solder ball spread may occur beyond the desirable pitch clearance. A good approximation is that the initial reflow reduces the height by about 10%; with the added weight of a heat spreader this figure may increase to 25% of the original height (ball diameter). The land pattern and solder mask clearance also play a part in the analysis. The extremes of this condition are shown in 9.2.1 through 9.2.4.
March 2008 9.2.1 BGA Ball Shape without Heat Slug 500 µm Standoff Height
Possible Cause Weight of BGA does not over-collapse ball. This is the target condition and becomes the measure of evaluation over other BGAs or balls on the same BGA. Potential Solution Use spacer if more clearance is desired. It should also be judged to check on the variation between ball collapse.
9.2.2 BGA Ball Shape with Heat Slug 375 µm Standoff Height
Possible Cause Weight of BGA with heat slug causes ball to over-collapse. This deformation may be acceptable depending on the component pitch so that balls do not touch. Potential Solution Mandatory requirement to include spacer preventing ball collapse.
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March 2008 9.2.3 BGA Ball Shape with Heat Slug 300 µm Standoff Height
Possible Cause Weight of BGA with heat slug causes ball to over-collapse. This is a definite poor quality condition and should be remedied. Potential Solution Mandatory requirement to include spacer preventing ball collapse.
9.2.4 Critical Solder Paste Conditions The amount of solder paste deposited for plastic BGA attachment is helpful, but not very critical in formation of good solder joint since the ball itself can be the source of solder. However, in the case of ceramic BGA (CBGA), it is very important that enough solder paste is deposited. The recommended volume of solder paste for 890 µm CBGA is 0.12 cubic mm and 0.08 cubic mm minimum. If sufficient solder paste is not deposited, as shown in 9.3.1, the reliability of solder joint may be questionable. The reason solder must be added to the high temperature solder ball or column is that there is no contribution of solder volume from the package termination to the solder joint.
IPC-7095B 9.2.5 Thicker Paste Deposit
Possible Cause Thicker paste is incorrect stencil opening for BGA land pattern. Potential Solution Reduce stencil thickness; microetch down at BGA area; reduce stencil opening.
9.2.6 Void Determination Through X-Ray and CrossSection Transmission X-ray can detect void presence
(light areas) and the associated X-Y location. The technique can also detect uneven or missing solder balls (various dark image diameters). An example of this condition is shown in 9.4.1. However, cross-section X-ray is required to determine the vertical (Z axis) location of the void in the solder joint.
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IPC-7095B 9.2.7 Voids and Uneven Solder Balls
Possible Cause – Excess voiding in solder ball attachment. – Via in pad design (voids related to via in pad design are not considered a defect as per IPC-A-610D) – Fast ramping profile – Forward compatibility scenarios (tin/lead BGA ball with Lead Free Solder Paste) Potential Solution – Evaluate structural strength of joint through thermal stress or microsection – Use reflow profile with long soak – Avoid situations noted under potential causes
There are many reasons for formation of voids in BGA. However, the presence of voids does not pose any reliability risks. Voids , as shown in 9.4.2, can survive 1000 thermal cycles (no shock, 0-100°C), although more common voids are shown in 9.4.1. Even though voids do not pose reliability concerns, excessive presence of voids is an indication of design or process problems. Reliability is related to where the product is located.
March 2008 9.2.8 Eggshell Void
Microvia 0.65mm @ 1000 cycles Shows collapse of solder joint, intermittent contact failure resulted Possible Cause Entrapment of air or other gaseous species during reflow. The air or other gaseous species could possibly have evolved from the microvia in the PCB. Potential Solution Remove component and replace with new one.
9.3 BGA Interposer Bow and Twist Plastic BGAs have a tendency to warp during normal assembly reflow processes. The warpage can occur on the BGA substrate or on the product PCB. The result can be an open or short condition at the solder joint that deals with the stresses. The temperature (reflow profile), BGA construction, solder paste volume, and cooling condition all contribute to the possible defect. Shorts in the corner balls, is an indication of warpage in BGA where the corners of the BGA package are bent inward (frowning BGA).
Solder shorts are caused in adjacent and/or opposite BGA corners as the substrate bows downward (frowning) and applies a stress to the corner balls. This same phenomena can cause balls, away from the corner, to lift away from the mounting substrate as the substrate changes from frowning to smiling as shown in 9.5.1.
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IPC-7095B
BGA package or the BGA interposer cannot be redesigned, or the product board cannot be redesigned. In addition, the anomaly must consistently occur and solder and component inventory should be considered prior to making any process changes. If the decision is made to use excess solder paste to correct opens in corner balls, the process should be closely monitored to insure that additional defects are not created such as solder bridging, solder balling, etc.
9.3.2 Solder Joint Opens Due to Interposer Warp
Possible Cause – Warpage of the BGA caused by thermal mechanical stresses during reflow soldering. – Check other corners for similar conditions. – May be caused by frowning BGA interposer where the corner becomes raised. Potential Solution – Increase ball size at corner or use glue-dot. In some instances add in tape during the reflow process. – Return package to supplier. – Check coplanarity using shadow moiré at reflow temperature.
Opens in corner balls is an indication of warpage in BGA where the corners of the package are lifted upward. Such opens, as shown in 9.5.3, could be minimized by use of solder paste on the excess side. Adding excess solder is a band-aid and not a real solution to the problem. Determining the root cause and addressing the reasons for the anomaly is more important toward establishing a robust process. Modifying the stencil aperture to permit solder paste deposits on the board should be used as a solution to open corners only when certain process or component conditions cannot be altered, such as when the reflow process has already been optimized, the
Possible Cause – The failure appears to be due to insufficient paste release from the stencil or insufficient ball size. – Warped package (smiling BGA) with corner balls lifted up. Potential Solution – Check balls at incoming prior to assembly. – Return package to supplier, Implement incoming inspection and or source audit, Apply extra solder paste on corner lands.
9.4 Solder Joint Conditions The following sections deal with the conditions of the solder ball in relationship to the mounting structure and the component interposer. In each instance, an explanation is provided as to the reason for the occurrence of the condition.
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IPC-7095B 9.4.1 Target Solder Condition
Possible Cause Solder balls exhibit a uniform shape and texture, and they are symmetrically aligned to the attachment sites, showing ball collapse on both top and bottom of BGA balls. Potential Solution Document process parameters and maintain a stable process.
9.4.2 Solder Balls With Excessive Oxide
March 2008 9.4.3 Evidence of Dewetting
Possible Cause Dewetting of the solder at the contact interface may be due to excessive oxidation on the land, organic contamination. Poor plating can contribute to this condition as well. ENIG comes in a number of systems, i.e., hi P and low P systems. Dewetting of ENIG is due to oxidation of Ni barrier not excess P on surface. Potential Solution Develop process effect controlled experiment to determine which attribute contributes most to dewetting.
9.4.4 Mottled Condition
Possible Cause Solder ball oxides will form due to exposure to multiple reflow solder cycles (topside or bottom side). Potential Solution This can be reduced significantly by correct flux selection, reducing the number of production reflows to two and not cleaning the PWB between reflows.
Possible Cause The surface condition of the solder ball is likely the result of overheating during the reflow solder process or excessive/ repeated exposure to temperatures above liquidus. Potential Solution Evaluate reflow process in order to determine proper ball characteristics.
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March 2008 9.4.5 Tin/lead Solder Ball Evaluation
Possible Cause Reflow of solder paste should form a proper ball geometry. Potential Solution Maintain process effects standardization.
IPC-7095B 9.4.7 Cold Solder Joint
Possible Cause The ball contacts have not completed wetting at the attachment sites. Condition may be due to poor solder paste printing or contamination on the attachment site that cannot accept wetting. Potential Solution Check stencil and printing process to determine sufficient solder paste deposit.
9.4.6 SAC Alloy 9.4.8 Incomplete Joining Due to Land Contamination
Possible Cause Slightly mottled appearance of the tin-silver-copper alloy. Potential Solution Determine paste and ball characteristics through experimentation.
Possible Cause Organic contamination or oxidation of the PCB land can negatively compromise the uniform and complete joining of the solder ball and PCB land surface. PCB land was not sufficiently clean to promote proper wetting prior to application of solder paste. Potential Solution Test for cleanliness as part of process. Implement proper PCB storage and handling procedures to prevent contamination and exposure to conditions which promote oxidation.
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IPC-7095B 9.4.9 Deformed Solder Ball Contamination
Possible Cause Solder ball deformation can occur due to the component moving during the reflow soldering process (package warp or board warp) and/or when the land pattern geometry is not correct. Potential Solution Avoid overheating which causes quality disparities of the interposer.
9.4.10 Deformed Solder Ball
March 2008 9.4.11 Insufficient Solder and Flux for Proper Joint Formation
Possible Cause The solder ball suspended in air is due to the lack of solder and flux. This condition is due to a solder skip during the stencil printing process. In evaluating the solder ball interface at the left it appears that the two materials did not reach a fully liquidus condition. Potential Solution Check stencil and solder deposition as well as flux contained within solder paste.
9.4.12 Reduced Termination Contact Area
Possible Cause Ball deformation (column shaped) can result from temporary warping of the substrate during reflow soldering. The package substrate corner, in this case, moved upward at the higher temperature, away from the board surface. While in this condition, the solder alloy cooled to a solidus condition resulting in a column shape. This is known as dynamic warping because the warping increases along with the reflow temperature. As it cools, the package would return to its original shape if the solidified solder was not preventing it from doing so. Potential Solution This is caused by CTE mismatch of the materials in the package or board. Though elimination of this condition is outside the control of the SMT process, the effect can be minimized by avoiding overheating of the interposer and the board.
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Possible Cause The condition may be due to package warping upward in the area shown. The three center connections have extended into a column while the adjacent contacts remain somewhat spherical. Potential Solution Movement during BGA ball solidification as well as overheating within the reflow process.
March 2008 9.4.13 Excessive Solder Bridging
IPC-7095B 9.4.15 Disturbed Solder Joint
Possible Cause Excessive solder bridging between contacts is likely due to the transfer of solder paste residue during the solder printing process or because the stencil did not seat securely to the board surface during the process.
Possible Cause The condition is a result of package movement while the molten solder is returning to a solidus condition.
Potential Solution Check stencil opening and avoid excess solder paste depositions.
Potential Solution Check conveyor and method of assembly capture in reflow oven.
9.4.14 Incomplete Solder Reflow
Possible Cause The solder ball on the substrate and the solder paste on the board did not reach a fully liquidus condition during the reflow soldering process. Potential Solution Determine reflow profile in order to validate solder paste used in attachment.
The movement may be caused by physical contact with the component or severe mechanical shock to the assembly.
9.4.16 Missing Solder
Possible Cause The condition is a result of package missing solder paste deposit on the PCB land(s). The presence of the solder paste deposit is necessary to form the BGA solder joint. This solder paste deposit would melt during reflow soldering and coalesce with the molten BGA solder to form the solder joint. Potential Solution Check stencil aperture for clogging with solder paste. Also. ensure that the stencil is designed correctly with each aperture opening for each SMT land on the PCB.
137
IPC-7095B
March 2008
10 GLOSSARY AND ACRONYMS
MCM
Multichip Module
AABUS
As Agreed Upon Between User and Supplier
MCM-L
Multichip Module-Laminate
MCP
Multichip Package
ASIC
Applications Specific IC
MD
Metal Defined
ASM
Array Surface Mount
MDS
Multi Device Subassembly
ASMP
Application Specific Module Packaging
MLC
Multilayer Ceramic
BGA
Ball Grid Array
MMB
Moisture Membrane Bag
BOC
Board-On-Chip
MMC
Maximum Material Condition
BT
Bismaleimide-Triazine
NAND
Not ‘‘And’’
CBGA
Ceramic Ball Grid Array
NSMD
Nonsolder Mask Defined
CGA
Column Grid Array
OEM
Original Equipment Manufacturer
COB
Chip-On-Board
OSP
Organic Solderability Preservative
CPU
Central Processing Unit
PBB
Polybrominated Biphenyl
CSP
Chip Scale Packages
PBBO
Polybrominated Biphenyl Oxide
CTE
Coefficient of Thermal Expansion
PBDE
Polybrominated Diphenyl Ether
CTF
Critical To Function
PBGA
Plastic Ball Grid Array
DBDPE
Decabromodiphenyl Ether
PCA
Printed Circuit Assembly
DDRSDRAM
Double-Data-Rate Synchronous Dynamic Random Access Memory
PCB
Printed Circuit Board
PCM
Phase Change Materials
Df
Dissipation Factor
PCMCIA
DfR
Design for Reliability
Personal Computer Memory Card International Association
DIG
Direct Immersion Gold
PGA
Pin Grid Array
Dk
Dielectric Constant
PLCC
Plastic Leaded Chip Carrier
DSBGA
Die-Size Ball Grid Array
PSA
Pressure Sensitive Adhesives
ENEPIG
Electroless Nickel/Electroless Palladium/ Immersion Gold
PTH
Plated Through-Hole
QFP
Quad Flat Pack
ENIG
Electroless Nickel Immersion Gold
RDS
Rectangular Die Size
FAT
Flux Activation Time
RF
Radio Frequency
FBGA
Fine Pitch Ball Grid Array
RFID
Radio Frequency Identification
FC
Flip Chip
RMS
Root Mean, Square
FPT
Fine Pitch Technology
RoHS
Restriction of Hazardous Substances
FRBGA
Fine-Pitch, Rectangular Ball Grid Array
SDRAM
HASL
Hot Air Solder Level
Synchronous Dynamic Random Access Memory
HAST
Highly Accelerated Stress Testing
SMD
Solder Mask Defined
HDB
High Density Printed Boards
SMOBC
Solder Mask Over Bare Copper
I/O
Input/Output
SMT
Surface Mounting Technology
IMC
Intermetallic Compound
IR
Infrared
SO-DIMM Small Outline Dual In-Line Memory Module
Kirkendall Voiding
http://www.electronicproducts.com/rohs/ ?filename=dfr.sep2005.html
SOIC
Small Outline Integrated Circuit
SPC
Statistical Process Control
LCP
Liquid Crystal Polymer
SRAM
Static Random Access Memory
LFBGA
Low-Profile Fine-Pitch Ball Grid Array
SSO
Simultaneously Switching Output
LMC
Least Material Condition
TAB
Tape-Automated Bonding
138
March 2008
IPC-7095B
TBBPA
Tetrabromobisphenol A
TBGA
Tape Ball Grid Array
Td
Decomposition Temperature
TFBGA
Thin Profile Fine Pitch Ball Grid Array
Tg
Transition Temperature
TIM
Thermal Interface Materials
UFPT
Ultra Fine Pitch Technology
UtRAM
Uni-transistor Random Access Memory
UUT
Unit Under Test
UV
Ultraviolet
VFBGA
Very Thin-Profile Fine-Pitch Ball Grid Array
11 BIBLIOGRAPHY AND REFERENCES
[1] Davignon, John, and Gray, Foster. ‘‘An evaluation of via hole tenting with solder mask designed to pass Mil-P-55110D thermal shock requirements.’’ Proceedings of Technical Program SMI 91, San Jose, August 25-29, 1991, pp. 905-921. [2] Denkler, J. D. ‘‘The speed of liquid.’’ Circuits Manufacturing, May 1986, pp. 21-24. [3] John Lau, ‘‘Ball Grid Array Technology’’ 1995. p.122. Shows a graph of relative PCB cost per layer count. [4] ‘‘Designed Experiment to Determine Attachment Reliability Drivers for PBGA Packages,’’ Theo I. Eijm, Albert Holliday, Frank E. Bader and Steven Gahr. AT&T Bell Laboratories, Princeton, NJ. [5] ‘‘Thermal and Power Cycling Limits of Plastic Ball Grid Array (PBGA) Assemblies,’’ Robert Darveaux and Andrew Mawer, Motorola. [6] ‘‘Designed Experiment to Determine Attachment Reliability Drivers for PBGA Packages,’’ Theo I. Eijm, Albert Holliday, Frank E. Bader and Steven Gahr. AT&T Bell Laboratories, Princeton, NJ. [7] Ref: Robert Crowley, Chip Scale Review, May 1998, p 37). [8] IPC-TR-462,’’Solderability Evaluation of Printed boards with Protective Coatings over Long Term Storage,’’ October 1987, IPC Publications. [9] Katchmar, R., ‘‘Position Dependence of CTE in Plastic Ball Grid Arrays,’’ Proc. Int. Electronics Packaging Conf. (IEPS), Atlanta, September 1994, pp. 271283. [10] Katchmar, R., ‘‘Position Dependence of CTE in Plastic Ball Grid Arrays,’’ Proc. Int. Electronics Packaging Conf. (IEPS), Atlanta, September 1994, pp. 271283.
[11] Mawer, A. J., S. C. Bolton, and E. Mammo, ‘‘Plastic BGA Solder Joint Reliability Considerations,’’ Proc. Surface Mount International Conf., San Jose, CA, August-September 1994, pp. 239-251. [12] Engelmaier, W., ‘‘Solder Joint Reliability for BGAs and Other Advanced Electronic Components, ’’Workshop Notes, Engelmaier Associates, L.C., Ormond Beach, FL, 1999. [13] Mawer, A. J., S. C. Bolton, and E. Mammo, ‘‘Plastic BGA Solder Joint Reliability Considerations,’’ Proc. Surface Mount International Conf., San Jose, CA, August-September 1994, pp. 239-251. [14] Attarwala, A. I., and R. Stierman, ‘‘Failure Mode Analysis of a 540 Pin Plastic Ball Grid Array,’’ Proc. Surface Mount International Conf., San Jose, CA, August-September 1994, pp. 252-257. [15] Phelan, G., and S. Wang, ‘‘Solder Ball Connection Reliability Model and Critical Parameter Optimization,’’ Proc. 43rd Electronic Components and Technology Conf., Orlando, FL, June 2-4, 1993, pp. 858862. [16] Rukavina, J., ‘‘Ball Grid Array Attachment Methodologies,’’ Proc. Ball Grid Array Nat. Symp., Dallas, TX, March 1995. [17] Bogatin, E., ‘‘BGAs for Workstation Application,’’ Proc. Ball Grid Array Nat. Symp., Dallas, TX, March 1995. [18] ANSI/IPC-MF-150F, ‘‘Metal Foil for Printed Wiring Applications,’’ The Institute for Interconnecting and Packaging Electronic Circuits, Lincolnwood, IL, October 1991. [19] Hines, L. L., ‘‘SOT-23 Surface Mount Attachment Reliability Study,’’ Proc. 7th Annual Int. Electronics Packaging Conf. (IEPS), Boston, MA, November 1987, pp. 613-629. [20] Orsten, G. S. F.,W. New, Y. Wang, and M. L. Peloquin ‘‘SMT Considerations in Spaceflight and Critical Military Applications,’’ Proc. 18th Ann. Electronics Manufacturing Seminar, China Lake, CA, February 1994, pp. 75-89. [21] Orsten, G. S. F., ‘‘The Problems Associated with Adhesive Bonding of Components on Surface Mount Assemblies,’’ Proc. 19th Ann. Electronics Manufacturing Seminar, China Lake, CA, February 1995, pp. 153-163. [22] Engelmaier, W., ‘‘Reliability Figures of Merit for Surface Mount Solder Attachments of Components: 2nd Generation Generic Design Tools,’’ Proc. Surface Mount International Conf., San Jose, CA, August 1991, pp. 1239-1243.
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March 2008
[23] Engelmaier, W., ‘‘Surface Mount Solder Joint Reliability: Issues, Design, Testing, Prediction,’’ Workshop Notes, Engelmaier Associates, Inc., Mendham, NJ, 1995.
[26] Engelmaier, W., ‘‘Surface Mount Solder Joint Reliability: Issues, Design, Testing, Prediction,’’ Workshop Notes, Engelmaier Associates, Inc., Mendham, NJ, 1995.
[24] Engelmaier, W., and B. Fuentes, ‘‘Alloy 42: A Material to be Avoided for Surface Mount Solder Component Leads and Lead Frames,’’ Proc. Surface Mount International Conf., San Jose, CA, August-September 1994, pp. 644-655; also in Proc. Int. Electronics Packaging Conf. (IEPS), Atlanta, September 1994, pp. 503-516.
[27] Lebonheur, C. Matayaba, S. Houle, and Y. Xu, Thermal Interface Material Development, Intel Assembly & Test Technology Journal, Vol 3, 2000.
[25] Mawer, A. J., S. C. Bolton, and E. Mammo, ‘‘Plastic BGA Solder Joint Reliability Considerations,’’ Proc. Surface Mount International Conf., San Jose, CA, August-September 1994, pp. 239-251.
140
[28] NCMS, Lead-free Solder Project Final Report, August 1997, www.ncms.org.
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