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Su S ubject: professional practice Topic To ic:: 8155-multipurpose programmable device
INTRODUCTION TO 8155
The 8155 is a multipurpose programmable peripheral device.
It has a RAM & i/o ports built into itself
Internally latch is present
It is generally used to implement a minimum system with 8085 processor
block schematic OF 8155 VCC (+5V)
GND (0V)
CE
8155
IO/M AD0-AD7 ALE
256*8 Static RAM
A
PA 0-7
B
PB 0-7
C
PC 0-5
RD WR
Timer
RESET
Timer in
Timer out
Pin diagram of 8155
Features
A 256 byte RAM
2 programmable 8 bit I/O ports
1 programmable 6 bit I/O port
1 programmable 14 bit binary counter/timer
Internal address latch to demultiplxed AD0-AD7,using ALE line
Internal block diagram of 8155
Functions of blocks Internal
latch: it is used to latch lower address bus from data bus.
Internal
decoder: it is used to select the ports and control reg.
CWR-
it is used to select the ports in I/P or O/P
mode. Ports:
they can be used in I/P or O/P mode depending upon data pattern written in the control register.
Registers of 8155 Port A Port
B
Port
C
Timer
Register
Control Status
Register
Register
Control word (command register) format: D7
D6
Timer command
D5
D4
D3
IEB
IEA
PC
D2
D0, D1: mode for PA and PB, 0=i/p, 1=o/p D2, D3: mode for PC D4, D5: interrupt enable for PA and PB, 0=disable 1=enable D6, D7: Timer command: o 00: No effect o 01: Stop if running else no effect o 10: Stop after terminal count (TC) if running, else no effect o 11: Start if not running, reload at TC if running.
D1
D0
PB
PA
Port C bits (D2, D3): ALT D3 D2 PC5 PC4 PC3 PC2
PC1 PC0
1 0 0 I
I
I
I
I
I
2 1 1 O
O
O
O
O
O
3 0 1 O
O
O
STB - A BF-A INTR-A
4 1 0 STB-B BF-B INtR-B STB-A BF-A INTR-A I - input O - output