HyperLynx Signal Integrity Analysis Student Workbook

HyperLynx Signal Integrity Analysis Student Workbook August 2002

Copyright  Mentor Graphics Corporation 2002. All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may not be duplicated in whole or in part in any form without written consent from Mentor Graphics. In accepting this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use of this information.

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Part Number: 069717

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QUASAR is a trademark of ASM Lithography Holding N.V. Red Hat is a registered trademark of Red Hat Software, Inc. SCO, the SCO logo and The Santa Cruz Operation are trademarks or registered trademarks of the Santa Cruz Operations, Inc. in the USA and other countries. Signalscan is a trademark of Design Acceleration, Inc. SimWave product is a registered trademark of Systems Science, Inc. Sneak Circuit Analysis Tool (SCAT) is a registered trademark of SoHaR Incorporated. SPARC is a registered trademark, and SPARCstation is a trademark, of SPARC International, Inc. Spectre and SpectreRF are registered trademarks of Cadence Design Systems, Inc. Sun Microsystems, Sun Workstation, and NeWS are registered trademarks of Sun Microsystems, Inc. Sun, Sun-2, Sun-3, Sun-4, OpenWindows, SunOS, SunView, NFS, and NSE are trademarks of Sun Microsystems, Inc. SuperH is a trademark of Hitachi, Ltd. Synopsys, Design Compiler, Library Compiler, and Chronologic VCS are trademarks or registered trademark of Synopsys, Inc. TASKING is a registered trademark of TASKING. Teamwork is a registered trademark of Cadre Technologies, Inc. Tensilica and Xtensa are trademarks of the Tensilica, Inc. Times and Helvetica are registered trademarks of Linotype AG. TimingDesigner, QuickBench, and Chronology, are registered trademarks of Chronology Corp. Transmission Line Calculator (TLC), Crosstalk Toolkit (XTK), Crosstalk Field Solver (XFX), Pre-Route Delay Quantifier (PDQ), and Mentor Graphics Board Station Translator (MBX) are trademarks of Quad Design. Tri-State, Tri-State Logic, tri-state, and tri-state logic are registered trademarks of National Semiconductor Corporation. UG Wiring is a registered trademark of Unigraphics Solutions, Inc. UNIX and OPEN LOOK are registered trademarks of UNIX System Laboratories, Inc. Versatec is a trademark of Xerox Engineering Systems, Inc. ViewDraw, Powerview, Motive, and Viewlogic are registered trademarks of Viewlogic Systems, Inc. Visula is a registered trademark of Zuken-Redac. VxSim, VxWorks and Wind River Systems are trademarks or registered trademarks of Wind River Systems, Inc. Z80 is a registered trademark of Zilog, Inc. ZSP and ZSP400 are trademarks of LSI Logic Corporation. XVision is a registered trademark of Visionware Limited, a subsidiary of the Santa Cruz Operation, Inc. X Window System is a trademark of MIT (Massachusetts Institute of Technology).

Other brand or product names that appear in Mentor Graphics product publications are trademarks or registered trademarks of their respective holders. Updated 07/25/01

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Table of Contents

TABLE OF CONTENTS Introduction ............................................................................................................1 Course Goals ..........................................................................................................2 Table of Contents ...................................................................................................4 Help ........................................................................................................................6 Help Dialog Boxes .................................................................................................7 Manuals ..................................................................................................................8 On Line Manuals ...................................................................................................9 Support .................................................................................................................10 Web Based Help ..................................................................................................11 Additional Resources ...........................................................................................12 Additional Resources ...........................................................................................14 Other Resources ...................................................................................................16 Recommended Reading .......................................................................................17 Licensed Options .................................................................................................18 Licensing ..............................................................................................................19 Licensing: Node Locked ......................................................................................20 Licensing: Networked ..........................................................................................21 Using LM_LICENSE_FILE ................................................................................23 Viewing Licensed Options ..................................................................................24 LMTOOLS – Configuration ...............................................................................25 LMTOOLS - System Information .......................................................................26 LMTOOLS - Utilities ..........................................................................................27 LMTOOLS – Starting/Stopping/Reread ..............................................................28 LMTOOLS – Server Status .................................................................................29 LMTOOLS – Configure Service .........................................................................30 Exercise 1 .............................................................................................................31

HyperLynx Signal Integrity Analysis

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TABLE OF CONTENTS (cont.) Module 1 Signal Integrity Overview ...................................................................................1-1 PCB Design Trends ............................................................................................1-2 The Solution Space is Shrinking! .......................................................................1-3 The Domain of SI Analysis ................................................................................1-4 Zo and the Incident Wave ...................................................................................1-5 Steady State Solution ..........................................................................................1-6 Impedance Mismatches ......................................................................................1-7 The Incident Wave ..............................................................................................1-8 Reflection ............................................................................................................1-9 Reflection Coefficient .......................................................................................1-10 Reflected Again! ...............................................................................................1-11 … And So It Goes ... .........................................................................................1-12 SI and Crosstalk Errors .....................................................................................1-13 Delay Errors ......................................................................................................1-14 Threshold Errors ...............................................................................................1-15 Overshoot Errors ...............................................................................................1-16 Multicrossing Errors .........................................................................................1-17 Another View ....................................................................................................1-18 Crosstalk ...........................................................................................................1-19 Crosstalk Factors: Microstrip vs. Stripline .......................................................1-21 Non-Monotonic Edges ......................................................................................1-22 Other Crosstalk Factors ....................................................................................1-23 The 4 T’s of Signal Integrity ............................................................................1-24 Solution Space Exploration (SSE) ....................................................................1-25 The Solution Space ...........................................................................................1-26 Solution Space Example ...................................................................................1-27 Benefits .............................................................................................................1-28

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TABLE OF CONTENTS (cont.) Module 2 Overview of LineSim and BoardSim .................................................................2-1 Overview Of LineSim & BoardSim ...................................................................2-2 HyperLynx Tool Suite .......................................................................................2-3 What Is LineSim? ...............................................................................................2-4 LineSim Inputs And Outputs ..............................................................................2-7 Why Use LineSim? .............................................................................................2-9 LineSim: Pre-Layout ........................................................................................2-11 What Is BoardSim? ...........................................................................................2-13 BoardSim Inputs ...............................................................................................2-16 BoardSim Outputs ............................................................................................2-17 Why Use BoardSim? ........................................................................................2-19 BoardSim: Post-CAD .......................................................................................2-20 BoardSim: Post-Layout ....................................................................................2-21 Module 3 The LineSim User Interface ...............................................................................3-1 The LineSim User Interface ................................................................................3-2 Mouse Use ..........................................................................................................3-3 Left Mouse ..........................................................................................................3-4 Right Mouse ........................................................................................................3-6 Windows .............................................................................................................3-7 HyperLynx Toolbar ............................................................................................3-9 Opening/Closing LineSim Files .......................................................................3-11 LineSim Main Toolbar .....................................................................................3-13 The File and Edit Menus ...................................................................................3-15 The Options and Help Menus ...........................................................................3-16 Inserting Rows and Columns ............................................................................3-17 View Options ....................................................................................................3-18 Options ..............................................................................................................3-20


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TABLE OF CONTENTS (cont.) General Purpose File Editor ..............................................................................3-24 Exercise 2 ..........................................................................................................3-25 Module 4 Identifying Signal Integrity Symptoms .............................................................4-1 Design Requirements ..........................................................................................4-2 Delay ...................................................................................................................4-3 Skew ...................................................................................................................4-5 Signal Integrity Symptoms .................................................................................4-7 Signal Integrity Sensitivities ...............................................................................4-9 Crosstalk ...........................................................................................................4-10 Crosstalk Design Implications ..........................................................................4-12 Crosstalk in LineSim/BoardSim .......................................................................4-14 Crosstalk Sensitivities .......................................................................................4-16 EMC ..................................................................................................................4-17 Symptom Identification ....................................................................................4-21 Handling SI Problems .......................................................................................4-23 Exercise 4 ..........................................................................................................4-24 Module 5 Running LineSim .................................................................................................5-1 Running LineSim ................................................................................................5-2 Creating/Opening LineSim .................................................................................5-3 Assigning Models .............................................................................................5-18 Simulation Power Supply Voltage ....................................................................5-20 Scope/Sim Analysis ..........................................................................................5-21 Running Scope/Sim Analysis ...........................................................................5-23 Terminator Wizard ............................................................................................5-34 SPICE Writer ....................................................................................................5-36 Exercise 5 ..........................................................................................................5-41

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TABLE OF CONTENTS (cont.) Module 6 Solutions with LineSim .......................................................................................6-1 Solutions with LineSim ......................................................................................6-2 Causes .................................................................................................................6-3 Technology .........................................................................................................6-5 Topology .............................................................................................................6-7 Termination .......................................................................................................6-10 Comparing Solutions ........................................................................................6-16 Exercise 6 ..........................................................................................................6-18 Module 7 Strategies for Using LineSim ..............................................................................7-1 Strategy for Using LineSim ................................................................................7-2 Design Flow ........................................................................................................7-4 High-speed Clock and Bus Nets .........................................................................7-6 Known Troublesome Signals ..............................................................................7-8 Evaluating Design Tradeoffs ............................................................................7-10 Multi-Board Systems Analysis .........................................................................7-14 Exercise 7 ..........................................................................................................7-16 Module 8 Constraint Generation ........................................................................................8-1 Constraint Generation .........................................................................................8-2 Layout Constraints ..............................................................................................8-3 Selecting Constraints ..........................................................................................8-5 Transmission Line Impedance ............................................................................8-9 Delay and Length Constraints ..........................................................................8-11 Width and Spacing Constraints ........................................................................8-17 Termination Constraints ...................................................................................8-19


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TABLE OF CONTENTS (cont.) Layout Constraints ............................................................................................8-20 Editing a Constraints File .................................................................................8-22 Exercise 8 ..........................................................................................................8-24 Module 9 Creating Models ..................................................................................................9-1 Creating Models ..................................................................................................9-2 Modeling Requirements ......................................................................................9-3 Creating MOD Models .......................................................................................9-5 Testing MOD Models .......................................................................................9-11 Creating IBIS Models .......................................................................................9-13 IBIS Model Data and Parameters .....................................................................9-15 Testing IBIS Models .........................................................................................9-28 Exercise 9 ..........................................................................................................9-36 Module 10 The BoardSim User Interface ..........................................................................10-1 The BoardSim User Interface ...........................................................................10-2 Mouse Use ........................................................................................................10-3 Dialog Boxes ....................................................................................................10-4 The BoardSim Toolbar and Icons .....................................................................10-5 Viewing the Layout ..........................................................................................10-9 View Commands ............................................................................................10-10 Selecting Nets .................................................................................................10-12 Highlighting Nets ............................................................................................10-14 SPICE Writer ..................................................................................................10-15 Report Files .....................................................................................................10-17 The HyperLynx General Purpose Editor ........................................................10-20 Help Files and Manuals ..................................................................................10-21 Exercise 10 ......................................................................................................10-23

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Table of Contents

TABLE OF CONTENTS (cont.) Module 11 Running BoardSim ............................................................................................11-1 Running BoardSim ...........................................................................................11-2 Setting Up Your Layout ....................................................................................11-3 Translation GUI ................................................................................................11-5 Translation PCB Files to Hyperlynx .................................................................11-7 Setting Up BoardSim ........................................................................................11-8 Opening and Closing BoardSim Files ............................................................11-11 Stackup Editing ...............................................................................................11-13 Assignment of Models and Values .................................................................11-15 Board Wizard: Batch Mode ............................................................................11-31 Setting Up Crosstalk Options .........................................................................11-35 Running EMC Spectrum Analysis ..................................................................11-45 Terminator Wizard ..........................................................................................11-49 Quick Terminators ..........................................................................................11-51 Exercise 11 ......................................................................................................11-53 Module 12 Quick Analysis in BoardSim ............................................................................12-1 Quick Analysis in BoardSim ............................................................................12-2 Quick Analysis in the Design Cycle .................................................................12-3 Early Identification of Risk Areas ....................................................................12-5 Quick Analysis Options ....................................................................................12-8 Show Signal Integrity Problems .....................................................................12-10 Suggest Termination Changes ........................................................................12-12 Show Crosstalk Strengths Estimate ................................................................12-14 Quick Analysis Report Options ......................................................................12-18 Back Annotation .............................................................................................12-21 The Final Check ..............................................................................................12-23 Exercise 12 ......................................................................................................12-25


xiii

Table of Contents

TABLE OF CONTENTS (cont.) Module 13 Using BoardSim to Find Solutions ...................................................................13-1 Using BoardSim to Find Solutions ...................................................................13-2 Causes ...............................................................................................................13-3 Finding Possible Solutions ...............................................................................13-5 Technology and Topology ................................................................................13-8 Termination and Quick Terminators ..............................................................13-10 Quick Analysis ................................................................................................13-13 Terminations ...................................................................................................13-15 Comparing Solutions ......................................................................................13-17 Exercise 13 ......................................................................................................13-21 Module 14 Strategies for Using BoardSim .........................................................................14-1 Strategy for Using BoardSim ............................................................................14-2 Design Flow ......................................................................................................14-3 Quick Analysis ..................................................................................................14-9 Detailed Simulation in Batch Mode ...............................................................14-11 Evaluating Design Tradeoffs ..........................................................................14-13 Signal Integrity Signoffs .................................................................................14-15 Module 15 Multiboard Analysis ..........................................................................................15-1 MultiBoard Capabilities ....................................................................................15-2 MultiBoard Caveats ..........................................................................................15-3 MultiBoard Wizard ...........................................................................................15-4 MultiBoard Display ........................................................................................15-10 Editing MultiBoard Projects ...........................................................................15-11 Multiple Instances ...........................................................................................15-12

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Table of Contents

TABLE OF CONTENTS (cont.) MutliBoard Net Selection ...............................................................................15-13 Setting Probes for Multiple Boards ................................................................15-14 Model Assignments ........................................................................................15-15 Adding Terminators: Multiple Boards ............................................................15-16 Exercise 15 ......................................................................................................15-17 Module 16 Wrap-up .............................................................................................................16-1 Wrap-up ............................................................................................................16-2 Sharing Answers to Users’ Questions ..............................................................16-7 Appendix A Installation and System Requirements .............................................................A-1 System Requirements ........................................................................................A-2 Software Requirements ......................................................................................A-3 Hardware Requirements ....................................................................................A-5 Hardware Protection Key ..................................................................................A-7 Setting Up LineSim ...........................................................................................A-9 Appendix B More on High-Speed Design .............................................................................. B-1 What is “High Speed Design?” ..........................................................................B-2 The Real Culprit ................................................................................................ B-4 Critical Length ................................................................................................... B-5 System Frequency: How Fast is Too Fast? ........................................................ B-6 The Domain of SI Analysis ............................................................................... B-7 Transmission Line Behavior .............................................................................. B-8 Characteristic Impedance .................................................................................B-10 Steady State Solution .......................................................................................B-11


xv

Table of Contents

TABLE OF CONTENTS (cont.) Impedance Mismatches ................................................................................... B-12 Reflection ......................................................................................................... B-13 Reflection Coefficient ...................................................................................... B-14 Reflected Again! .............................................................................................. B-15 … And So It Goes ... ........................................................................................B-16 Ringing ............................................................................................................ B-17 Calculating Z and S .........................................................................................B-18 Incident vs. Reflective Switching .................................................................... B-19 Points to Remember .........................................................................................B-20 Transmission Line Behavior Summary ........................................................... B-22 Causes of Impedance Mismatch ...................................................................... B-23 Impedance Mismatch Experiment ................................................................... B-25 Other Crosstalk Factors ................................................................................... B-27 Crosstalk Experiment: Edge Rate .................................................................... B-28 Board Stackup .................................................................................................. B-29 Crosstalk Effects .............................................................................................. B-30 What Is A “Bad” Signal? .................................................................................B-31 System Budget - Example ...............................................................................B-32 Signal Quality .................................................................................................. B-33 Points To Remember .......................................................................................B-34 The Technology Paradox .................................................................................B-35 Technology Techniques ................................................................................... B-36 Can Edge Rates Be Controlled? ...................................................................... B-37 Topology .......................................................................................................... B-38 Starburst Routing ............................................................................................. B-39 Starburst Impedance ........................................................................................B-40 Starburst Experiment: Impedance .................................................................... B-41 Daisy Chain Routing ........................................................................................B-42 Combination Routing .......................................................................................B-43 Routing Issues .................................................................................................. B-44 Termination ......................................................................................................B-47 Termination Techniques .................................................................................. B-48 Simple Pullup/Pulldown (Shunt) ..................................................................... B-49

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TABLE OF CONTENTS (cont.) Thevenin Termination ..................................................................................... B-50 AC Termination ...............................................................................................B-51 Diode Termination ........................................................................................... B-52 Series Termination ........................................................................................... B-53 Signal Quality Strategies .................................................................................B-54 Appendix C High-Speed Design Methodologies ...................................................................C-1 Real World Consequences .................................................................................C-2 Using SI Tools ................................................................................................... C-3 SI Analysis Terminology ...................................................................................C-4 Signal Integrity Analysis: Traditional Approaches ...........................................C-5 Worst Case Analysis: Traditional Approaches ..................................................C-6 A New Approach: Solution Space Exploration (SSE) ...................................... C-7 Solution Space Exploration ............................................................................... C-8 Swept-Variable Analysis ...................................................................................C-9 Solution Space Exploration Example: PCI Bus .............................................. C-10 Layout Planning ...............................................................................................C-11 The New Role of Post-Layout SI Analysis ...................................................... C-12 Design for Simulation (DFS) ........................................................................... C-13 Recommended Methodology ........................................................................... C-14 High Speed Design Process ............................................................................. C-15 Analysis Methodology ..................................................................................... C-16 Benefits ............................................................................................................ C-17 Closing Points .................................................................................................. C-18


xvii

Table of Contents

TABLE OF CONTENTS (cont.)

xviii


Introduction


1

Introduction

Course Goals Course Goals ♦ ♦ ♦ ♦ ♦ ♦

Describe LineSim and BoardSim Where each fits in the design cycle Run LineSim Import a completed layout into BoardSim Run BoardSim Hands-on labs so you can explore software features

1 • HyperLynx Signal Integrity Analysis: Introduction

Copyright © 2002 Mentor Graphics Corporation

Notes: This PADS Software product training course covers the operation of the signal integrity analysis software from the HyperLynx division. Software operation is described in the context of signal integrity requirements and a typical product design cycle. At the end of this training, you should be able to : Describe the differences between LineSim and BoardSim and where each fits in the design cycle; Create a new LineSim schematic, adding components and connections; Open and edit an existing LineSim schematic (TLN file); Import a completed layout into BoardSim; Open a BoardSim layout (HYP file); Simulate a net and describe the signal integrity characteristics; Simulate a net and describe

2


Introduction

EMC emissions characteristics and driver current characteristics; Add a termination; optimize component values; and determine the effect on signal integrity; Run a batch mode analysis to identify all risk areas for signal integrity; Run a batch mode analysis to simulate critical nets. Hands-on examples at the end of each section allow you to develop a more complete understanding. They have been carefully designed to help you retain more of the material covered in this training presentation. During the hands-on time, you should feel free to explore the software features. This is also a good opportunity to discuss the easiest ways to perform analysis tasks which you expect to do frequently.


3

Introduction

Table of Contents Table of Contents Module 0 – Introduction Module 1 – System Requirements Module 2 – Overview of LineSim and BoardSim Module 3 – The LineSim User Interface Module 4 – Identifying Signal Integrity Symptoms Module 5 – Running LineSim Module 6 – Solutions with LineSim Module 7 – Strategy for Using LineSim Module 8 – Constraint Generation Module 9 – Model Creation



Notes:

4


Introduction

Table of Contents (Cont.) Table of Contents (Cont.) Section 10 - The BoardSim User Interface Section 11 - Running BoardSim Section 12 - Quick Analysis in BoardSim Section 13 – Solutions with BoardSim Section 14 – Strategy for BoardSim Section 15 – MultiBoard Analysis Section 16 – Wrapup



Notes:


5

Introduction

Help Help ♦ Help dialog boxes are activated by selecting Help, then the topic from the dropdown menu. ♦ Access to the on line manuals is also initiated from the Help menu ♦ Help menu also provides quick links to the web for more information on High speed tools as well as IBIS models.



Notes:

6


Introduction

Help Dialog Boxes Help Dialog Boxes

♦ Help is context sensitive ● ●

LineSim help opens when running LineSim BoardSim help opens when running BoardSim

♦ Links to topics are embedded in the text on the right ♦ Clicking on the plus/minus sign, ‘+/-’, expands/colapses contents



Notes:


7

Introduction

Manuals Manuals ♦ Every user has access to a softcopy of the documentation ♦ Manuals are released in .pdf format ♦ Uses the standard Acrobat reader ♦ Manuals may be printed



Notes:

8


Introduction

On Line Manuals On Line Manuals



Notes:


9

Introduction

Support Support ♦ Phone:

(425) 869-2320

♦ E-Mail:

[email protected]

♦ FAX:

(425)881-1008



Notes:

10


Introduction

Web Based Help Web Based Help

Technical support options



Notes:


11

Introduction

Additional Resources Additional Resources ♦ http://www.innoveda.com ♦ HyperLynx HyperTalk ● ●

[email protected] subscribe hypertalk

♦ The signal integrity reflector ● ●

[email protected] subscribe si-list



Notes: Additional Resources Your instructor is familiar with HyperLynx software, as well as other PADS and Innoveda products. Additional resources can be found on the web at http://www.hyperlynx.com. You may wish to join one or more of the email reflectors listed below. For each, you can subscribe by sending an email to the indicated address, and entering the command in the body of the email. All of these reflectors restrict content to technical discussions (no job ads). For each, adding the work "digest" to the end of the command results in just one combined email for an entire day's messages, rather than one email per message sent on that reflector.

12


Introduction

HyperLynx HyperTalk is for HyperLynx users. Discussion threads have included model availability, tool tricks, and dealing with board fabricators. To post a message to the list, send e-mail to [email protected]. For technical support, please continue to send requests to [email protected]. [email protected], subscribe hypertalk The signal integrity reflector covers issues related to signal integrity and EMC, including design, simulation, and testing. To post a message to the list, send email to [email protected]. [email protected], subscribe si-list


13

Introduction

Additional Resources Additional Resources ♦ The IBIS reflectors ● ●

[email protected] subscribe

♦ The groups available are: ● ● ● ●

ibis-info ibis ibis-users ibischk-bug



Notes: The IBIS reflectors cover various aspects of IBIS models and modeling techniques. There are several reflector groups. To subscribe, use "subscribe . To send a message to a group, send email to @eda.org. [email protected], subscribe The groups available are: ibis-info - To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member.

14


Introduction

ibis - To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users - To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug - To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.


15

Introduction

Other Resources Other Resources ♦ SI-List ●

Email Signal Integrity Forum

●

Archives: www.qsl.net/wb6tpu/

●

Free Subscription: For info on the list and subscription procedures send e-mail to: [email protected] In the BODY of the message place "info si-list" or to subscribe place "subscribe si-list" (no quotes)

♦ Dr. Howard Johnson’s High-speed Digital Design Website ● ● ● ●

www.sigcon.com Bi-monthly newsletter Presentations Articles



Notes:

16


Introduction

Recommended Reading Recommended Reading ♦ Signal Integrity ●

●

●

●

High-Speed Digital System Design; Stephen H. Hall, Garrett W. Hall, James A. McCall; John Wiley & Sons, Inc. 0-471-36090-2 High-Speed Digital Design, A Handbook of Black Magic; Howard W. Johnson and Martin Graham; Prentice Hall; ISBN 0-13395724-1 Signal and Power Integrity in Digital Systems; James E. Buchanan; McGraw Hill; ISBN 0-07-008734-2 Computer Circuits Electrical Design; Ron K. Poon; Prentice Hall; ISBN 0-13-213471-3

♦ EMI ●

●

Noise Reduction Techniques in Electronic Systems; Henry W. Ott; Wiley-Interscience; ISBN 0-0471-85068-3 Printed Circuit Board Design Techniques for EMC Compliance; Mark I. Montrose; IEEE Press; ISBN 0-7803-5376-5



Notes:


17

Introduction

Licensed Options Licensed Options ♦ Available Options ●

Prelayout – – – –

●

Linesim EMC for LineSim Crosstalk for LineSim Spice for LineSim

Postlayout – – – – – –

BoardSim EMC for BoardSim Crosstalk for BoardSim Spice for BoardSim EBD for BoardSim MultiBoard (Includes Export to XTK/Scratchpad)



Notes: HyperLynx has several options which can be purchased separately. In most cases, when you first receive HyperLynx software, it is pre-licensed to run the options you have purchased. However, sometimes the product cannot be pre-licensed. If you receive an error message saying you are not licensed to run it, contact HyperLynx or your local reseller to obtain a license code. Usually, the code will be sent by fax or e-mail. Additional options, floating seats, and board/layout translators can be purchased at any time.

18


Introduction

Licensing Licensing ♦ Two methods of licensing ● ●

Node-Locked Networked

♦ Hyperlynx uses the FLEXlm™ License Manager



Notes:


19

Introduction

Licensing: Node Locked Licensing: Node Locked ♦ Software can only be executed on the licensed machine ♦ Each machine has unique Hostid (CPU Hostid, IP address, NIC id, dongle, disk ID) ♦ Each machine has unique license file which matches the host id ♦ Windows NT requires sentinel driver to be loaded when using dongle ♦ Default license name is hyplic.dat ♦ Install license file in Hyperlynx\license ♦ Uses HYP_LIC_FILE_60 to point to the license file if not default



Notes:

20


Introduction

Licensing: Networked Licensing: Networked ♦ Network Server machine grants licenses to the clients ♦ Network Server Machines: Supported operating systems: Windows 98/NT 4X/2000 Solaris 2.6/2.7

♦ Network Server machines are responsible for running: lmgrd.exe hyprlnx.exe

- the license daemon - the vendor daemon

♦ Network Client Machines: Supported operating systems: Same as Network Servers above



Notes:


21

Introduction

Licensing: Networked (Cont.) Licensing: Networked (Cont.) ♦ ♦ ♦ ♦

If using a Dongle goes on license server Install from “Administrator” account Can have more than one user Use the License Manager Tool to manage licensing ●

♦ ♦ ♦ ♦

Start -> Programs -> Hyperlynx License 6.0 -> License Manager Tool

Install license file in HyperlynxServer60\license Default license name is hyplicsr.dat (can be anything) Use HYP_LIC_FILE_60 to point to the license file if not default LM_LICENSE_FILE variable may be used if enabled.



Notes: Installing a Floating license requires you to be logged on the NT "administrator" or "supervisor" account. Detailed installation instructions are shipped in writing. With a floating license, it is possible for more than one user to use the software at the same time. Each floating license is sold with a seat-limit, or the maximum users that may access the same software license at the same time.

22


Introduction

Using LM_LICENSE_FILE Using LM_LICENSE_FILE ♦ Set LM_LICENSE_FILE =1 in licensing section of the bsw.ini ♦ LM_LICENSE_FILE environment variable points to license file ♦ Software now uses LM_LICENSE_FILE to locate file



Notes:


23

Introduction

Viewing Licensed Options Viewing Licensed Options ♦ Display current licensed options, by selecting, from the Main Toolbar ●

Options -> Installed Options



Notes: It is easy to quickly check licensed options. When you open the license window, you will see all of the licensed options. If an option is grayed out or missing, it is not licensed on your hardware protection key (dongle).dongle. When you contact support at HyperLynx, you may be asked for you license number. Regarding translator licenses: For HyperLynx 5.52 and earlier, if a board was translated using the PADS translator, it cannot be opened unless the PADS translator is present on your computer (or on the designated server).

24


Introduction

LMTOOLS – Configuration LMTOOLS – Configuration



Notes: The Serices/License file tab provides the user with the ability to specify a license file and declare whether or not to use Windows Services for the licensing process. It is recommended that the lmgrd.exe process be started as a service. This will ensure that the licensing process will restart whenever the server machine is rebooted.


25

Introduction

LMTOOLS - System Information LMTOOLS - System Information



Notes: The System Settings tab is used to display or confirm the current system settings. This is useful when debugging a server license issue and one needs to either update the license file (e.g. the SERVER line must have the correct machine name), or, needs to give the correct ethernet address, disk ID, so Innoveda can generate the correct license in the first place. The license files also have a begin and end date. If the date is outside of the end date, the lmgrd process will not serve a license. Also, if the server and client machines times are different by more than 15 minutes, a license will not be served.

26


Introduction

LMTOOLS - Utilities LMTOOLS - Utilities

Press Find Version to get report

Version of Flex which was compiled in the exe


Executable name

Current license files


Notes: This tab is used to determine the version of Flex which is called for by an executable file. This would be useful during license debugging. It is a quick technique which can be used to ensure that the appropriate version of lmgr.exe is being used for the executable. This is extremely useful for companies who have multiple versions of FLEXlm on their systems. This enables them to determine if they need to maintain multiple versions of the lmgrd.exe.


27

Introduction

LMTOOLS – Starting/Stopping/Reread LMTOOLS – Starting/Stopping/Reread



Notes: The Start/Stop/Reread tab allows for server maintenance. When an updated license file is received, one may either stop the service, replace the license file, and restart it, or, click on the Reread license File button. Typically a new license would simply be reread. If one is updating the software, and the software and license service reside on the same machine, the license service should be stopped.

28


Introduction

LMTOOLS – Server Status LMTOOLS – Server Status



Notes: When you are using a floating license (with a dongle on a "server"), it is still easy to quickly check licensed options. You can also see how many licenses are available to share, and which ones you have checked out. FLEXlm support is available for HyperLynx releases 6.0 and higher.


29

Introduction

LMTOOLS – Configure Service LMTOOLS – Configure Service

Check these boxes to activate the license as a service (network only) and to automautomatically start at powerup


Use the Browse buttons to specify the license and log file locations Note: Non default license/log file locations are shown


Notes: The Configure Services tab is used to create a new license service which, at the users request, can be setup to start in the background anytime the machine is rebooted. The user will need to enter the location of the lmgrd executable, the location of the license file and the location of the log file. Typical installations will have a single directory which contains the license files for any software which uses the FLEXlm licensing scheme. This promotes ease of maintenance (e.g. the administrator maintains all FLEXlm based licenses from a single directory). If anyone needs more information, we can discuss it off line.

30


Introduction

Exercise 1 Exercise 1

Finding the License Options



Notes: This exercise introduces the following:

• Opening the HyperLynx software. • Using the main toolbar and pulldown menus. • Checking Licenses under Options. Make sure the PowerPCB translator is licensed. This is needed in order to open the BoardSim files for some of the later labs.


31

Introduction

32


Module 1 Signal Integrity Overview


1-1

Signal Integrity Overview

PCB Design Trends PCB Design Trends

♦ Faster clock and bus speeds ♦ Denser packaging ♦ Constant board sizes …. but what does this mean to the Systems Designer?

1-1 • HyperLynx Signal Integrity Analysis: Signal Integrity Overview


Notes:

1-2



The Solution Space is Shrinking! The Solution Space is Shrinking!

Early 1990’s

Late 1990’s Decreasing Timing Budgets

Design Space

20-50Mhz 300MHz-1GHz+

• Higher Clock Speeds • Low Voltage Signaling • Driver/Receiver Technology

Increasing Power System Issues -- Drift

Increasing SI/EMI Effects

Finished Design

• Faster Edge Rates • Smaller Form Factors • Tighter Emission Standards

• Faster Edge Rates • Signal Density/ SSO • Clever Packaging & Power Plane Design

Much Less Design Margin to Work With 1-2 • HyperLynx Signal Integrity Analysis: Signal Integrity Overview


Notes:


1-3


The Domain of SI Analysis The Domain of SI Analysis U2

U1

F u n c t i o n

PCB Trace

Component Pins

F u n c t i o n

Drivers/Receivers

♦ Other elements: passive devices, coupled traces, connectors, vias, cables, other cards 1-3 • HyperLynx Signal Integrity Analysis: Signal Integrity Overview


Notes:

1-4



Zo and the Incident Wave Zo and the Incident Wave ♦ Characteristic impedance (Z0) of a line is the impedance the driver sees as it is switching ♦ The characteristic impedance and driver resistance form a voltage divider that determines the incident wavefront

RD = 50 Ω 1V

+ -

0V

0.33V Drop

Z0 = 100 Ω

...

0.67V Wavefront

0

Ideal 1V voltage source Rise Time = 0 Source Resistance = 0

I0 = 1V/(50+100) Ω = 6.7mA



Notes:


1-5


Steady State Solution Steady State Solution ♦ The final ( Ifinal ) current is determined only by the driver and load resistances

RD = 50 Ω 1V

+ -

0V

Z0 = 100 Ω

IFinal = 1V/(50+950) Ω = 1mA

RL = 950 Ω

0


** Remember Remember that that the the series, series, or or DC DC resistance resistance of of aa trace trace is is very very low, low, on on the the order order of of 0.3 0.3 -- 0.5 0.5 Ω Ω // ft. ft.



Notes:

1-6



Impedance Mismatches Impedance Mismatches ♦ In this example the transmission line and the load are mismatched, since the initial and steady state currents are quite different

RD = 50 Ω 1V

+ -

0V

Z0 = 100 Ω

IFinal = 1V/1000 Ω = 1mA

I0 = 1V/150 Ω = 6.67mA

RL = 950 Ω

0

Ideal 1V voltage source Rise Time = 0 Source Resistance = 0 Note: Io is nearly 7 times larger than IFinal 1-6 • HyperLynx Signal Integrity Analysis: Signal Integrity Overview


Notes:


1-7


The Incident Wave The Incident Wave

RD = 50 Ω 1V

+ -

0V

0.33V Drop

Z0 = 100 Ω

...

0.67V Wavefront

0


I0 = 1V/(50+100) Ω = 6.7mA



Notes:

1-8



Reflection Reflection ♦ When the initial wavefront reaches the terminating resistor, most of the voltage is reflected due to the impedance mismatch 1

0.67V, 6.7mA Incident Wave Z0 = 100 Ω

3

0.54V Reflected Wave

2

950 Ω will not sink 6.7mA. Most of the wavefront is reflected RL = 950 Ω

0.54V + 0.67V = 1.21V Potential



Notes:


1-9


Reflection Coefficient Reflection Coefficient ♦ The Reflection Coefficient defines how much of the initial wave will be reflected. 2 1

Vi = 0.67V Incident Wave Z0 = 100 Ω

Vo = ρL * Vi

3

ρ = (R - Z ) / (R + Z ) L L 0 L 0

= (950 - 100) / (950 + 100) = 850 / 1050 = .8095

RL = 950 Ω

VL

= (.8095)(.67) = 0.54V Reflected Wave VL = Vi + Vo = 0.67V + 0.54V = 1.21V 1-9 • HyperLynx Signal Integrity Analysis: Signal Integrity Overview


Notes:

1-10



Reflected Again! Reflected Again!

♦ When the wavefront reaches the driver, it is reflected again due to an impedance mismatch. Note that the reflection coefficient is negative 1

Vi = 0.54V Wavefront ( riding on top of 0.67V DC ) RD = 50 Ω

+ -

Z0 = 100 Ω 3

2

ρ = (R - Z ) / (R + Z ) D D 0 D 0

Vo = ρL * Vi = (-0.333)(.54) = -0.18V Reflected Wave

= (50 - 100) / (50 + 100) = -50 / 150 Vs = Vi + Vo = 1.21V + (-0.18V) = 1.03V = -0.333



Notes:


1-11


… And So It Goes ... … And So It Goes ... ♦ The wavefront continues to reflect back and forth on the line with decreasing amplitude until the line “settles” to the steady state current and voltage

V = 1.21, 0.88, 0.97, 0.95, ... RD = 50 Ω

Z0 = 100 Ω

+ -

RL = 950 Ω V = 0.67, 1.03, 0.93, 0.96, ...



Notes:

1-12



SI and Crosstalk Errors SI and Crosstalk Errors ♦ D = Delay

♦ ♦

♦ ♦

min. delay to pin < net's min. delay threshold OR max. delay to pin > net's max. delay threshold T = Threshold during transition the pin's signal level did not reach the switching threshold O = Overshoot pin's signal level exceeded the steadystate level by more than the net's overshoot threshold M = Multi-crossing pin's signal level crossed the threshold more than once during transition X = Crosstalk Crosstalk from neighbor nets exceeded the threshold value for this net



Notes:


1-13


Delay Errors Delay Errors ♦ ♦ ♦ ♦

Min Rise Delay: Max Rise Delay: Min Fall Delay: Max Fall Delay:

VM VM VM VM

of Driver to VL of Driver to VH of Driver to VH of Driver to VL

High State

of Receiver of Receiver of Receiver of Receiver

Low State

Common Causes

VH

■

Overloaded drivers

■

Long Traces Driver Receiver

VM VL Dmin(lh) Dmax(lh)

Dmin(hl) Dmax(hl)



Notes: Each receiver will have 4 delay numbers associated with it:

• Min Rising • Max Rising • Min Falling • Max Falling

1-14



Threshold Errors Threshold Errors ♦ Signal does not achieve the necessary high or low signal threshold ♦ Threshold errors are tested at the end of High state and Low state simulations

High State

Low State

Common Causes ■

Overloaded drivers

■

Slow drivers / fast signals

High?

VH

Boundary determined by: (Period * Duty Cycle)

VL Low?



Notes: When the simulator (XTK) analyzes a net, it performs a High State test followed by a Low State test. The boundary between these tests is determined by the Period and Duty Cycle (simulation parameters that the user controls). At the end of each of these tests, XTK determines if the signal at the receiver made it to the intended logic state. If not, XTK flags a Threshold error. Period = T(High_Test) + T(Low_Test) Duty Cycle = T(High_Test)/Period * 100%


1-15


Overshoot Errors Overshoot Errors ♦ Occurs when inputs exceed power / ground voltages ♦ Can damage components

5V

High State Overshoot

Overshoot (+)

Common Causes

VH Overshoot (-)

■

Long Traces

■

Fast Edge Rates

VL GND

Low State Overshoot Overshoot (+)



Notes: Overshoot is reported as the peak voltage relative to the state's nominal steady state voltage. Therefore, Positive (+) Overshoot reports mean the signal went beyond the nominal steady state voltage by the reported value. Negative Overshoot reports mean the signal never hit the nominal steady state voltage. Remember it this way: "Positive Overshoot is Bad."

1-16



Multicrossing Errors Multicrossing Errors ♦ Occur when a signal passes in and out of the threshold region several times during transition

Common Causes

VH

■

Excessive capacitance

■

Excessive inductance

■

Long Traces

Max. Delay

VL



Notes: When a signal exhibits Multi-crossing, it's maximum delay is measured at the last crossing of the "destination state's" threshold. Because the excursion into the threshold region may not be significant enough for the receiving device to actually switch, delay reports for multi-crossing signals are noted with an asterisk (*).


1-17


Another View Another View



Notes:

1-18



Crosstalk Crosstalk ♦ Current in a PCB trace creates electric and magnetic fields

♦ Increasing current flow increases the magnetic field, and vice versa

Increasing


Decreasing


Notes:


1-19


Crosstalk (Cont.) Crosstalk (Cont.) ♦ When two traces are close together, a change in current flow in one trace can induce current in an adjacent trace



Notes:

1-20



Crosstalk Factors: Microstrip vs. Stripline Crosstalk Factors: Microstrip vs. Stripline ♦ Microstrip results in greater crosstalk

Microstrip


Stripline


Notes:


1-21


Non-Monotonic Edges Non-Monotonic Edges

♦ Reported as Delay and/or Multi-crossing errors, depending on the voltage level and times at which it occurs

VH

VL


Common Causes ■

Long traces

■

Crosstalk

■

Excessive loading


Notes: Oscillation measures non-monotonic behavior between the logic thresholds. The delta between the valley and peak of the oscillation is reported. The peak and valley do not have to be confined to the region between the logic thresholds. Multi-crossing errors are almost always Oscillation errors too. Only one oscillation value is reported (the direction of the signal is not included).

1-22



Other Crosstalk Factors Other Crosstalk Factors ♦ Driver Edge Rate ●

The faster I and V change, the stronger the electric and magnetic fields - more coupling

♦ Distance ● ● ●

Coupling increases as distance between conductors decreases Crosstalk increases with conductor height above ground Crosstalk increases with coupling length or parallelism (but does hit a maximum limit)



Notes:


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The 4 T’s of Signal Integrity The 4 T’s of Signal Integrity ♦ Four basic factors will determine the success or failure of a circuit with regard to signal integrity ●

Technology – Swap or Sweep Models – Change model parameters

●

Topology – Different topologies – Sweep xline lengths and parameters

●

Termination – Different Strategies – Sweep values

●

Trace Parameters – Layer and conductor dimensions & Coupling –



Notes:

1-24



Solution Space Exploration (SSE) Solution Space Exploration (SSE) ♦ Solution Space Exploration: The process identifying design constraints by analyzing a circuit’s electrical performance while varying multiple circuit parameters. ♦ Solution Space: The range or ranges of circuit parameters where a circuit meets all of its performance requirements (such as Delay and Overshoot). ♦ Design Constraint: A limit on the value of a circuit characteristic that will ensure manufacturability and successful operation.



Notes:


1-25


The Solution Space The Solution Space ♦ Solution Space: The range or ranges of circuit parameters where a circuit meets all of its performance requirements (such as Delay and Overshoot). ♦ Each grid intersection of the 3D chart is a simulation result ♦ To determine solution with the greatest latitude: Identify the largest rectangle within all of the design’s limits ♦ Tip: Use 2D and Data Queries to quickly identify the most promising regions



Notes:

1-26



Solution Space Example Solution Space Example

Delay

Delay AND Overshoot

Length

Impedance

Solution Space

Impedance

Impedance

♦ A circuit must meet a Delay requirement and an Overshoot requirement. The Solution space is where the passing cases for each of these requirements overlap.

Overshoot Length

Length 1-26 • HyperLynx Signal Integrity Analysis: Signal Integrity Overview


Notes: A sweep was performed on a circuit that had a Delay requirement and an Overshoot requirement. The light colored boxes on the left represent the conditions where the Delay and the Overshoot requirements were met. The dark region in the figure on the right represents the region where both requirements are met. This is the circuit's Solution Space. If the design is to work properly, the Length and Impedance of the circuit must be Constrained to within the dark region. The actual design constraint should be a subset of the Solution Space. By setting the constraint within the Solution Space, you provide the circuit some design margin.


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Benefits Benefits ♦ Gain SI expertise ●

♦ ♦ ♦ ♦ ♦

Applicable to future designs

Fewer iterations through CAD Reduce integration/prototype effort Increased Design Reliability Reduce design cost Reduce Time to Market



Notes:

1-28


Module 2 Overview of LineSim and BoardSim


2-1

Overview of LineSim and BoardSim

Overview Of LineSim & BoardSim Overview Of LineSim & BoardSim ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

The HyperLynx Product Line What is LineSim? LineSim Inputs and Outputs Why Use LineSim? LineSim in a Typical Design Cycle What is BoardSim? BoardSim Inputs and Outputs Why Use BoardSim? BoardSim in a Typical Design Cycle

2-1 • HyperLynx Signal Integrity Analysis: Overview of LineSim & BoardSim


Notes: HyperLynx software is used for simulation of signal integrity, crosstalk, and EMC for printed circuit boards and IC packages. Inputs are IBIS models for the IC pins and either a (schematic) TLN or (complete layout) HYP file.

2-2



HyperLynx Tool Suite HyperLynx Tool Suite ♦ LineSim (pre-layout ) ♦ BoardSim (post-layout) ♦ The IBIS Development System (IDS) ♦ HyperSuite EXT is a licensing bundle



Notes: HyperLynx Products include LineSim, BoardSim, and the IBIS Development System (IDS). LineSim and BoardSim are pre-layout and post-layout analysis packages available from HyperLynx. The IBIS Development System is included with both LineSim and BoardSim. The IBIS Development System can also be purchased separately. The IBIS Development System (IDS) provides a user interface for editing and validating IBIS models. It is included with LineSim and BoardSim. It is also available free of charge to IBIS model developers (typically in a semiconductor design or manufacturing company) who provide free models externally. HyperSuite EXT is a licensing bundle that includes LineSim and BoardSim.


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What Is LineSim? What Is LineSim? ♦ Pre-Layout Analysis ♦ Use LineSim to: ● ● ● ● ● ● ●

Edit Stackup Choose models Simulate Signal Integrity Simulate Crosstalk Simulate EMC Try Terminations Netlist output



Notes: LineSim pre-layout analysis functions: Edit Stackup: Define board stackup: dielectric layers, signal layers, plane layers. Transmission line characteristic impedance and delay are automatically calculated whenever the stackup is changed. Choose models: You can select from over 7,000 IC models, including over 2,000. IBIS models. Both generic and vendor parts are available to help you do what-if evaluation of technology choices. You can also assign component values and select ferrite bead models.

2-4



Simulate SI: The Scope Simulator allows you to set probes and run simulations, much as you would do with a digital oscilloscope. Check Crosstalk: Transmission lines can be assigned crosstalk coupling. The simulator uses this coupling information, allowing you to see the impact of crosstalk on noise, ringing and delays. Simulate EMC: The Spectrum Analyzer allows you to run EMC simulations. The spectrum of emitted differential radiation can be displayed. Alternatively, the spectrum of a current waveform can be displayed. Try Terminations: The Termination Wizard calculates the optimum value(s) for termination components. These values can be automatically applied to the LineSim schematic. Netlist output: The SPICE netlist for the LineSim schematic can be automatically generated. If transmission lines are assigned crosstalk coupling, the HSPICE Welement is used to represent the coupling.


2-5


What Is LineSim? (Cont.) What Is LineSim? (Cont.) ♦ Pre-Layout Analysis ♦ LineSim modules: ● ● ● ●

LineSim Crosstalk for LineSim EMC for LineSim SPICEWriter for LineSim



Notes: LineSim is the pre-layout analysis software from HyperLynx. LineSim can be used to analyze nets for signal integrity, crosstalk, and EMC. During pre-layout analysis, you have the greatest flexibility to select options with the lowest cost. There are four separately licensed modules: LineSim, Crosstalk for LineSim, EMC for LineSim, and SPICEWriter for LineSim.

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LineSim Inputs And Outputs LineSim Inputs And Outputs ♦ ♦ ♦ ♦

GUI for schematic and stackup entry Models for IC pins (IBIS) Ferrite bead models Outputs ● ● ● ● ● ●

Stackup and field solver views Signal Integrity “scope” waveforms Crosstalk “scope” waveforms EMC spectrum plot Recommended terminations SPICE netlist



Notes: The LineSim schematic and stackup are created using the LineSim GUI (Graphical User Interface). Models for the IC pins (such as IBIS) are external files. A model library is shipped with LineSim, and additional models can be added by the user. A number of graphical items can be saved to the Microsoft Windows clipboard. These include the Stackup and field solver cross-sectional views, the scope waveforms from signal integrity and crosstalk analysis, and the EMC analysis spectrum. The LineSim SPICEWriter creates a file containing the SPICE netlist for the schematic. The file contains only the transmission lines and passive components;


2-7


you will add the IC pin models before using the file in SPICE. If you have crosstalk coupled transmission lines, the HSPICE W-component is used for the coupling. There is no direct data connection between LineSim and BoardSim at this time.

2-8



Why Use LineSim? Why Use LineSim? ♦ ♦ ♦ ♦ ♦ ♦

Build in quality Prevent board turns due to SI/EMC problems Reduce development time and cost Reduce cost of testing Predict product schedules reliably Shorten time to market



Notes: Using LineSim effectively can prevent board layout turns or even prototype turns, saving you weeks of work and thousands of dollars. Using LineSim can help you get your product to market sooner. And, by preventing signal integrity problems before they occur, you can build quality into your products from the ground up. For example, as simple a problem as constraining termination components to be physically near the desired IC pin before layout begins can save much time and effort. And you can make sure that all necessary termination components, and only the necessary ones, are placed on the board, which can lead to significant savings in board space as well as design time.


2-9


LineSim can be used early in the design cycle to evaluate tradeoffs between logic families using generic models, and then to tradeoff edge rates and drive strengths among IC output drivers. Trial routing topologies for critical nets can be evaluated. You can optimize your routing constraints to meet your signal integrity goals. Because LineSim can be used early in the design cycle, before final design decisions have been made, designers can take full advantage of this flexibility. LineSim can also be used after the layout is complete. If a board is returned for layout changes, LineSim can be used to evaluate tradeoffs between component placement, routing, and termination, and to update the layout rules to address the problems that caused the board to be returned.

2-10



LineSim: Pre-Layout LineSim: Pre-Layout ♦ No placement/routing information needed ♦ I/O technology ● ● ●

♦ ♦ ♦ ♦

I/O type Drive strength Edge rate

Routing topology Termination strategy Layout rules and constraints Perform more extensive “What-if” scenario simulation postlayout (e.g. analyze interplanar placement of signals)



Notes: LineSim is used for pre-layout analysis of signal integrity, crosstalk and EMC. No placement or routing information is needed. The electrical system designer can use LineSim to develop constraints and layout rules that can be used throughout the design. A system design typically starts by choosing a technology for the I/O. This is based on the system architecture and integrated circuits specified in the system requirements. LineSim can be used to evaluate options for drivers. For example, in an FPGA, each I/O pin can be assigned a driver type (such as PCI or AGP), drive strength (such as 8 mA or 16 mA), and edge rate control (such as slow/fast). While it is fairly easy to select a driver type, it is much more difficult to decide


2-11


whether an 8 mA fast driver or a 16 mA slow driver is best for signal integrity purposes, since they have about the same delay in many circuits. LineSim is used for what-if analysis prior to layout. Once the technology has been chosen, various routing topologies and termination styles can be evaluated. Line widths and spacings can be varied to optimize line impedance for each signal layer. Minimum line spacings can be determined that meet crosstalk requirements. Rules can be generated and communicated to the layout designer. And when the layout designer tells you that meeting all of the rules might requires 4 extra signal layers, you can quickly make tradeoffs to make the board more manufacturable while still meeting signal integrity requirements.

2-12



What Is BoardSim? What Is BoardSim? ♦ Post-Layout: Placement and routing available ♦ Use BoardSim to: ● ● ● ● ● ●

Edit Stackup Choose models Simulate SI, Crosstalk, EMC Try Terminations Netlist output Batch checks prior to prototype



Notes: BoardSim is the post-layout analysis software from HyperLynx. As you can see, the functionality is similar to LineSim. The main difference is that BoardSim works from actual physical data, whereas LineSim has only manually entered physical data. There are four separately licensed modules: BoardSim, Crosstalk for BoardSim, EMC for BoardSim, and SPICEWriter for BoardSim. BoardSim can be used to analyze nets for signal integrity, crosstalk and EMC as soon as layout information is available. Layouts can be imported from many layout packages, such as PADS PowerPCB and Cadence/OrCAD. Import


2-13


translators are presently available for approximately 15 Windows and UNIX layout packages.

2-14



What Is BoardSim? (Cont.) What Is BoardSim? (Cont.) ♦ Post-Layout Analysis ♦ BoardSim modules: ● ● ● ● ●

BoardSim Crosstalk for BoardSim EMC for BoardSim SPICEWriter for BoardSim Multi-board



Notes: LineSim is the pre-layout analysis software from HyperLynx. LineSim can be used to analyze nets for signal integrity, crosstalk, and EMC. During pre-layout analysis, you have the greatest flexibility to select options with the lowest cost. There are four separately licensed modules: LineSim, Crosstalk for LineSim, EMC for LineSim, and SPICEWriter for LineSim. Multi-board will be available with the release of Version 6.0.


2-15


BoardSim Inputs BoardSim Inputs ♦ Translated physical layout (HYP file) ● ● ●

Layout Stackup data Component values

♦ REF file for IC model mapping ♦ Models for ICs (IBIS) ♦ Models for ferrite beads



Notes: The BoardSim layout and stackup data are translated from the layout files. The list of files required depends on the layout package used; more information can be found under the Help file for each translator. The translator produces a HYP file representing the layout information. You may optionally generate a REF file for the IC model mapping. When a BoardSim design is saved, BUD, BBD, and PJH files are created as necessary. All of these BoardSim files are text (ASCII). Models for the I/O pins (such as IBIS) are external files. A model library is shipped with BoardSim, and additional models can be added by the user.

2-16



BoardSim Outputs BoardSim Outputs ♦ Interactive Outputs ● ● ● ● ●

Report files Signal Integrity and Crosstalk “scope” waveforms EMC spectrum plot Recommended termination SPICE netlist

♦ Batch Outputs ● ● ●

Quick Analysis to assess risk Signal integrity, Crosstalk, and EMC reports Design Change summary

♦ Export to XTK, Scratchpad (ePlanner), or LineSim



Notes: Various report files can be generated by the user. Interactive report files may be presented in a window or in a file. Batch operations always report results in a report file. A number of graphical items can be saved to the Microsoft Windows clipboard. These include the Stackup and field solver cross-sectional views, the scope waveforms from signal integrity and crosstalk analysis, and the EMC analysis spectrum. The BoardSim SPICEWriter creates a file containing the SPICE netlist for the selected net. The file contains only the transmission lines and passive components; you will add the IC pin models before using the file in SPICE. If you


2-17


have crosstalk turned on, the crosstalk coupled nets that are highlighted are included in the SPICE netlist, and the HSPICE W-component is used for the coupling. There is no direct data connection between BoardSim and LineSim at this time.

2-18



Why Use BoardSim? Why Use BoardSim? ♦ ♦ ♦ ♦ ♦ ♦ ♦

Build in quality Prevent board turns due to SI/EMC problems Reduce EMI emissions Reduce development time and cost Reduce cost of testing Predict product schedules reliably Shorten time to market



Notes: Using BoardSim effectively can prevent prototype turns, saving you weeks of work and thousands of dollars. Using BoardSim can help you get your product to market sooner. And, by identifying and preventing signal integrity problems, you build quality into your products. BoardSim can be used throughout the layout cycle to evaluate tradeoffs between edge rates and drive strengths among IC output drivers, based on actual routing information. Termination strategies to reduce EMI emissions can be evaluated. While LineSim makes assumptions about routing tracks, BoardSim works from complete layout information.


2-19


BoardSim: Post-CAD BoardSim: Post-CAD ♦ Early placement information ♦ Critical nets routed ♦ I/O technology ● ● ●

I/O type Drive strength Edge rate

♦ Routing topology & Layer assignment ♦ Termination strategies



Notes: BoardSim is used for post-layout analysis. All placement and routing information is available in the layout. The electrical system designer or layout designer can use BoardSim to check to ensure signal integrity constraints, including crosstalk and EMC, have been met. A layout can be done by routing critical nets first, then simulating them in BoardSim to analyze the board for signal integrity hot spots.

2-20



BoardSim: Post-Layout BoardSim: Post-Layout ♦ ♦ ♦ ♦ ♦ ♦

Final placement/routing Quick Analysis to assess risk Routing Layer assignment Termination strategies ECO reports Ensure signal integrity design requirements have been attained, including crosstalk and EMC



Notes: Next, the remaining nets can be routed, and BoardSim can be used again for analysis. BoardSim can also be used to evaluate options for drivers, letting you evaluate the tradeoff between an 8 mA fast driver and a 16 mA slow driver based on the actual routing topology they must drive. BoardSim is used for what-if analysis after layout. By using the Quick Analysis features in the Batch Mode, you can quickly identify and prioritize hot spots for signal integrity and crosstalk, as well as the nets most likely to require additional termination. Then you can run the Terminator Wizard or add Quick Terminators to improve signal quality, and run signal integrity and EMC simulations to optimize your design. Finally, you can simulate every net in batch mode before releasing the design to prototype fabrication.


2-21


2-22


Module 3 The LineSim User Interface


3-1

The LineSim User Interface

The LineSim User Interface The LineSim User Interface ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

Mouse Use Windows The Main Toolbar and Icons Opening and Closing LineSim Files The LineSim Main Toolbar View Options Options The General Purpose File Editor Help Files and Manuals

3-1 • HyperLynx Signal Integrity Analysis: The LineSim User Interface


Notes:

3-2



Mouse Use Mouse Use ♦ ♦ ♦ ♦ ♦

The LineSim user interface is mouse-driven Limited keyboard use Left mouse button is “Select” Right mouse button is “Menu Popup” Middle mouse button not used



Notes: The LineSim user interface is mouse-driven. For most operations, keyboard interaction is limited to text entry. For example, to select OK in a window, the left mouse button is used, and the (ENTER) key is ignored. This allows you to use the to enter data and then update information displayed within a window without closing that window. The left mouse button is used as the Select button. The right mouse button is used as the "Menu Popup" button. If there is a middle mouse button, it is not used.


3-3


Left Mouse Left Mouse ♦ Left mouse button select menu options ♦ Left mouse to add/remove components ● ● ●

Cursor over grayed out component, left click adds it Over dark gray component, removes it Component highlighted box when cursor is over it



Notes:

The left mouse button is used to select options from the pulldown menus on the main toolbar and to select options within windows. The left mouse button is a used to toggle components in the schematic diagram. When placed over a grayed-out IC pin (triangular shape) or passive (R or C shape), the first click will add the component to the schematic. A second click of the left mouse button will remove it. (Passive series components are removed by selecting "None" on the pop-up menu that appears when the right mouse button is used.)

3-4



Similarly, when the cursor is placed over a grayed-out transmission line symbol, the first click of the left mouse button will add a transmission line to the schematic. The second click changes the transmission line to a short circuit (ideal wire), and the third click removes it.


3-5


Right Mouse Right Mouse ♦ Right mouse is context sensitive ♦ Over component, opens component menu ♦ Over grayed-out area, opens Edit menu



Notes: The right mouse button makes a context-sensitive window call. When placed over a component in the LineSim schematic, a right click opens the window for setting options for that component. For an IC pin, a driver or receiver model can be selected. For a ferrite bead, a model can be selected; for other passive components, values can be selected. For transmission lines, the type of transmission line and related information can be entered. If the right mouse is clicked over a grayed-out component, the Views menu window will appear.

3-6



Windows Windows ♦ ♦ ♦ ♦ ♦

Windows appear based on context Tabs for overlays Radio buttons and check boxes Text entry boxes Informational text



Notes: New windows appear when certain menu items are selected. They also appear when you click the right mouse button. If you click the right mouse button over a component, a window associated with that component appears. If you click the right mouse button in an area of the schematic with only grayed-out (unselected) components, the View command window appears. Windows may contain several selectable tabs or overlays. By left clicking on the tab on the top section of the window, you can select which overlay is displayed. For example, in the transmission line window, the tabs are Transmission-Line Type and Values.


3-7


Windows can be closed by clicking OK/Close or the "X" in the upper right corner of the window; changes will be saved. Some windows can be closed using Cancel; this causes changes to be discarded.

3-8



HyperLynx Toolbar HyperLynx Toolbar ♦ Pulldown Command Menus ♦ Menu Bar: File operations, Project (Muti-Board), Edit commands, Options, Help. Open LineSim File

Layout Translator

(hover cursor over any icon to display the tool tip)

Open File Editor

Help

Open BoardSim File 3-6 • HyperLynx Signal Integrity Analysis: The LineSim User Interface


Notes: The main toolbar allows access to commands, as well as a link to the HyperLynx web site. The menus on the main toolbar are selected with the left mouse; selecting a command may cause a window to appear. They provide access to file commands, Help and Manuals, and other functions. The HyperLynx Main Toolbar: Toolbar Items (left to right): File operations, Edit commands, Options, Help. Some of the pulldown menu items are also available as icons below the main toolbar. These provide shortcuts to commonly used features.


3-9


Icons (left to right): Layout Translator, Open BoardSim File, Open LineSim File, Open New LineSim File, Open File Editor, Help.

3-10



Opening/Closing LineSim Files Opening/Closing LineSim Files ♦ Schematic files have the extension .TLN ♦ Open/Save/Save As/Close are under the File menu ♦ LineSim or New LineSim icons open/create LineSim Schematics

♦ ♦ ♦ ♦

Double click on any *.TLN in the Explorer “X” of schematic window to close “X” of HyperLynx window to exit Opening/creating LineSim files automatically closes the current file ♦ Only one LineSim schematic may be open at a time 3-7 • HyperLynx Signal Integrity Analysis: The LineSim User Interface


Notes: LineSim schematic files are named *.TLN. They are text (ASCII) files. It is possible to edit a TLN file manually or using a text processing script, although most people use only the user interface. New or existing LineSim schematics can be opened using the pulldown menus under File on the main toolbar. Existing schematics can also be opened using the LineSim icon. You can also open an existing LineSim file by double-clicking on the filename in a file list (such as Windows Explorer). A LineSim file can be saved using Save or Save As from the pulldown menus under File on the main toolbar.


3-11


A LineSim file can be closed by clicking the "X" in the upper right corner of the schematic window, or by choosing Close from under File on the main toolbar. If you close a LineSim schematic without previously saving it, you will be asked if you want to save changes. If you click the "X" in the main HyperLynx window, the program will exit after asking you if you want to save changes. Selecting a new LineSim File causes LineSim to open with a default filename, "unnamed#.tln".

3-12



LineSim Main Toolbar LineSim Main Toolbar ♦ Menu Bar: File, Project, Edit, View, Insert, Scope/Sim, Spectrum/Sim, Wizards, Options, Help

Show Coupled regions

File Editor BoardSim New LineSim

Layout Translator

Print

LineSim

Getting Started with Crosstalk

Zoom into Area

Help

Terminator Wizard Previous Zoom Edit Stackup


Oscilloscope/Simulator

Spectrum Analyzer


Notes: Toolbar Items (left to right): File operations, Edit commands, View commands, Insert (row/column), Scope/Sim, Spectrum/Sim, Wizards, Options, Help. Some of the pulldown menu items are also available as icons below the main toolbar. These provide shortcuts to commonly used features, including the Stackup Editor, the Scope Simulator and Spectrum Analyzer. Icons (left to right): PCB Layout Translator, Open BoardSim File, Open LineSim File, Open New LineSim File, Print, Open File Editor, Edit Stackup, Zoom into Area, Return to Previous Zoom, Open Oscilloscope/Simulator, Open Spectrum Analyzer/Simulator, Open Terminator Wizard, Getting Started with Crosstalk, Help on LineSim.


3-13


If you select PCB Layout Translator, Open BoardSim File, Open LineSim File, Open New LineSim File, or Exit, LineSim will close the current schematic. A window will ask if you want to save changes. You must select Yes or No before LineSim can release the file that is currently open. Demo: Walking through each major pulldown menu, notice how the commands are organized. For example, SPICE Writer, which creates a SPICE netlist, is located under File, since it generates a new file. The Help option brings up the complete list of Help files, Manuals and links, while the ? icon takes you directly to the main LineSim Help page.

3-14



The File and Edit Menus The File and Edit Menus



Notes:


3-15


The Options and Help Menus The Options and Help Menus



Notes:

3-16



Inserting Rows and Columns Inserting Rows and Columns

♦ After Insert=>New Row (or New Column) is selected, and the cursor is moved onto the schematic, a red line appears indicating the insertion point, click the left mouse button ♦ Connections on either side of the insertion point are broken. 3-11 • HyperLynx Signal Integrity Analysis: The LineSim User Interface


Notes: The Insert option allows you to insert a row or column between existing rows or columns in your schematic. This is useful when you need to break a transmission line into two segments (such as when the route changes layers). Once you specify whether to add a row (or column), a horizontal (or vertical) line appears on the schematic showing you where the row (or column) will be added.


3-17


View Options View Options



Notes: The viewing options are located under View on the main toolbar. Zoom commands are supported. Panning is done using the scroll bars on the bottom and right hand sides of the schematic. View commands can be accessed from this menu, or by clicking the right mouse button in any unused (gray) part of the schematic diagram. Zooming a specified area of the schematic is done by choosing Zoom Area, and using the left mouse button to draw a box around the desired area. A rectangular box showing the area selected is displayed. When you release the left mouse button, the selected area becomes the new view. Choosing to Zoom Previous returns you to the previous view. Zoom Normal displays the same area as shown

3-18



when LineSim is first opened. Zoom In and Zoom Out scale the viewing area by a fixed scale factor, centered on the same center as the previous view. Normally, the lines connecting coupled transmission lines are shown only when the cursor is over the transmission line. The Show Coupling Regions option allows you to have these lines on at all times. This acts as a toggle, so you can also reset the option here. Note that a gray background is preferred to white for contrast when you want to see the coupling lines.


3-19


Options Options



Notes: Options allows you to set preferences that are common to multiple sessions. The General tab options include model best/worst case scaling factors, trace width fabrication compensation values, and simulation temperature. The LineSim tab provides options to set default trace to trace and trace to plane settings, and to enable Advanced Coupling Mode. The default stackup layer values are set under the Default Stackup tab. The General tab allows you to set the scale factors to be applied to models that do not contain min/max information, and also to set the simulation temperature, which influences metal resistance. The LineSim tab provides options to set

3-20



default trace to trace and trace to plane settings, and to enable Advanced Coupling Mode. The default stackup layer values are set under the Default Stackup tab.


3-21


Options (Cont.) Options (Cont.)



Notes: The options menu allows you to select units (English/metric, thickness/weight), set background color for the display window, set preferences for simulation, and check/add licenses. Options settings are saved in the install directory (usually C:\HyperLynx) in Bsw.ini. You can also set the directory path for your model library by choosing Directories under Options. The default path is the install directory. Note that there is only one allowed path; however, you may use a different path for each project as long as all required model files are available under that path. The Libs directory must be located in the model library path, as well as the files Bsw.fbd (ferrite bead models) and Bsw.pak (resistor pack models).

3-22



The default path for searching for LineSim files is the last opened directory used by LineSim. This can be set to a fixed path in the Set Directories window.


3-23


General Purpose File Editor General Purpose File Editor ♦ Edit text files ● ● ●

Analysis results & constraints Model and Stackup changes Not Word control-key compatible (i.e. Ctlr- doesn’t work)



Notes: The General Purpose File Editor can be used for editing text files. In LineSim, this is particularly useful for creating files to document design considerations used to generate constraints, model changes and stackup changes. You can also open previously created report files. This editor is also available from the main HyperLynx product menu and form BoardSim. There are some minor differences between this file editor and other Microsoft style editors. Control commands (such as ^c and ^v for cut and paste) are not supported. Instead, editor commands are implemented using mouse clicks.

3-24




Using the LineSim User Interface



Notes:


3-25


3-26


Module 4 Identifying Signal Integrity Symptoms


4-1

Identifying Signal Integrity Symptoms

Design Requirements Design Requirements ♦ ♦ ♦ ♦ ♦ ♦

Delay Skew Signal integrity Crosstalk EMC Symptom identification using simulation

4-1 • HyperLynx Signal Integrity Analysis: Identifying Signal Integrity Symptoms


Notes:

4-2



Delay Delay ♦ Delay impacts setup & hold margins ♦ Setup & hold margins are analyzed via functional timing simulation and static timing analysis ♦ Caused by physical properties of traces ♦ Adds to logic delays inside ICs

Longer delay

Shorter delay 4-2 • HyperLynx Signal Integrity Analysis: Identifying Signal Integrity Symptoms


Notes: Propagation delay is the time a signal takes to travel from the driver to the receiver. This delay is caused by the physical properties of the traces. A longer trace has a longer delay. This delay occurs in addition to the logic delays internal to the integrated circuits. Excessive delay can result in logic failures during testing on the printed circuit board. If a delay is too long, data cannot reach the receiver before the start of the next clock cycle. This appears as a data failure, since the receiver does not have the correct current state. This is a timing failure rather than a logic design problem.


4-3


If a clock has a long delay, the hold time may be violated at the receiving IC. If a data line has a long delay, a setup time may be violated. If two signal lines have unequal delays, a comparator (or logic gate) may toggle unacceptably late in a clock cycle. Signal delay depends on the transmission line characteristics of the traces. Delay will usually be different for inner and outer layers (striplines and microstrips). It can be different for signal layers closer to planes than for signal layers that are further from the planes. Delay will also change with dielectric thickness, trace width and spacing. There is a Technical Application Note on the HyperLynx web site discussing in detail how to correct databook (lumped capacitive) timing to address actual propagation delays using LineSim. Delay problems can be addressed by shortening traces or by moving traces to a layer with a shorter delay per inch.

4-4



Skew Skew ♦ Signal from one driver arriving at multiple receivers at different times ♦ Caused by physical properties of traces ♦ Depends on layer assignment ♦ Star-route topologies tend to equalize delays



Notes: Skew is the difference in signal arrival times at different receivers when the receivers all are driven from the same driver. Both LineSim and BoardSim can be used to measure skew, and to evaluate design tradeoffs to reduce skew. The most common way to reduce skew is to make delays equal. Star routing produces the smallest skew, if each leg of the star is routed to the same delay. Excessive skew can result in logic failures during testing on the printed circuit board. A large skew can cause data to appear at two receivers in different clock cycles; during testing, one receiver will have incorrect data at its input. Smaller skews can lead to data not arriving where needed within the allowed timing budget.


4-5


Signal skew depends on the transmission line delays of the trace segments. Skew effects will usually be different for inner and outer layers (microstrips and striplines) due to the different delays. They can be different for signal layers closer to planes than for signal layers that are further from the planes. Skew will also change with dielectric thickness, trace width and spacing. Skew problems can be addressed by matching each driver-to-receiver trace delay for a signal.

4-6



Signal Integrity Symptoms Signal Integrity Symptoms ♦ Overshoot ● ● ●

Can slow logic Can clear memory Damages clamp diodes

♦ Undershoot ● ● ●

Logic faults False or double clocks “Glitchy” performance

v

♦ Ringing and settling time



Notes: Signal integrity problems are most commonly observed as overshoot and undershoot. Overshoot and undershoot (ringback) are the minimum and maximum voltages that occur after a signal has transitioned through a valid logic level (VIL or VIH). Overshoot is the amount of voltage past the final value. In the example here, the overshoot is roughly 2V on the rising edge and 2V on the falling edge. Overshoot causes several problems, including slowing the logic by turning on the clamp diodes in the receivers. A large overshoot is capable of clearing latches and "losing" data as a result.


4-7


Undershoot is the voltage ringback. In the example here, the undershoot is roughly 1.5 V on the rising edge and 2 V on the falling edge. The main problem with undershoot is that is can cause the signal to cross a logic threshold a second time. This can cause double-triggering of a clock input, or misreading of a data value. Two related problems are ringing and settling time. Ringing is the occurrence of more than one undershoot on the same signal edge. Settling time is the time required for the signal's voltage to settle to an acceptable level at the receiver. For a driver with a fast edge rate, the settling time can be many times longer than the driver's edge time, leading to timing problems. Overshoot and undershoot problems can be addressed by termination or by keeping trace delays much shorter than driver edge times.

4-8



Signal Integrity Sensitivities Signal Integrity Sensitivities ♦ Signal Integrity: Sensitivities ● ● ● ●

Power supply Temperature IC process variation Board process variation

♦ Hard to troubleshoot in the test lab



Notes: Signal integrity symptoms are sensitive to the edge rate of the IC driver, which in turn depends on the power supply voltage, temperature, variations. Both IC and printed circuit board variations can be quite large. Because of the dependencies, signal integrity problems can be intermittent on a board, or may vary from one board to another, leading to reduced production yields. Intermittent problems can be hard to troubleshoot in the test lab.


4-9


Crosstalk Crosstalk ♦ Coupling between signal traces ♦ Can be any traces on your board ● ● ● ●

Depends on edge rate, faster edge rates increases crosstalk Depends on separation, both horizontal and vertical Depends on height above/below planes Not just nearest neighbors

VC C



Notes: Crosstalk involves the coupling between signal lines. This is due to the transmission line properties of the signal lines. The electromagnetic field from a transmission line extends into space. The electric field lines must end on another piece of metal, such as another trace or a plane. LineSim is helpful in viewing the electric field lines (blue) and constant field lines (red). The coupling between the lines causes a signal in one trace to generate a signal in its neighboring traces. In the example, the trace on the left couples to both the middle trace and the trace on the right. Since electric field lines end on metal, putting a plane in between two traces will eliminate coupling between them.

4-10



Commonly, a switching signal causing the coupled signal is called an "aggressor", and a net receiving the coupled signal is called the "victim". The victim signal may be static or it may be switching. A victim net can also be an aggressor net, since the coupling is mutual.


4-11


Crosstalk Design Implications

Notes: If a victim's signal is static (quiescent), crosstalk still causes a change in voltage on it. The crosstalk will be small when observed at the driver of the victim net, and larger at the receiver. Example: A switching aggressor causes a static victim (green) to have a voltage change. The aggressor's driver is shown in red and the aggressor's receiver is shown in blue. If a victim net is switching, the crosstalk voltage results in a change in propagation delays. During testing, this appears as a timing problem that is dependent on how neighboring nets are switching.

4-12



Excessive crosstalk voltage can result in logic failures during testing on the printed circuit board. Excessive crosstalk can cause a receiver to toggle briefly, or to toggle at the wrong time. Excessive crosstalk voltage can cause an edgetriggered latch to capture data if the receiver is a clock input, or cause data to be misread when a clock edge occurs and the data receiver is toggled briefly at the same time. Any time crosstalk causes a signal to go between VIL and VIH, there is a high risk of these errors occurring. Design specifications often require crosstalk limits of 10% of the signal swing, since crosstalk and undershoot effects add together.


4-13


Crosstalk in LineSim/BoardSim Crosstalk in LineSim/BoardSim

LineSim Crosstalk is defined by the user and can be modified quickly to investigate the pros and cons of different relationships can be used to specify constraints to layout

BoardSim Crosstalk is defined by the actual components, layout topology, and board stackup; cannot be modified quickly



Notes: Crosstalk coupling depends on the transmission line characteristics of the traces and on the driver edge rate. Crosstalk is highest for long parallel traces and fast driver edges. Crosstalk coupling depends on the spacing of parallel trace segments in both the horizontal and vertical directions. It also depends on the distance to planes, and will usually be different for inner and outer layers (striplines and microstrips). Crosstalk coupling will also change with trace width. LineSim is used to do "what-if" analysis and to generate constraints to prevent crosstalk, and to try solutions such as shortening parallel traces, placing a plane between problem traces, or adding terminations. Most often, layout constraints (such as trace widths, spacings, and lengths)are expressed in mils.

4-14



BoardSim can be used to quickly identify which nets are aggressors on the actual layout. Aggressors of concern are those that cause excessive crosstalk on a victim net. BoardSim's aggressor identification is based on a unique electrical threshold algorithm. By using an electrical threshold to specify the acceptable crosstalk coupling limit, every net on the entire board can be checked to see if it generates crosstalk in excess of the threshold on any other net. This means you no longer have to worry about missing an aggressor because your geometric threshold was too small (because the algorithm checks every net), or using a large geometric threshold and having too many aggressors for simulation (because the algorithm rejects only nets with crosstalk coupling below the electrical threshold). Once you specify your electrical threshold, BoardSim checks the entire board for nets that are either aggressors or victims to your selected to the selected net whenever crosstalk is enabled.


4-15


Crosstalk Sensitivities Crosstalk Sensitivities ♦ Crosstalk ● ● ● ● ●

Power supply Temperature IC process variation Board process variation Switching of other nets



Notes: Crosstalk symptoms are sensitive to the edge rate of the IC driver, which in turn depends on the power supply voltage, temperature, and IC process variation. Signal integrity symptoms also depend on the physical characteristics of the printed circuit board traces, which depends on the printed circuit board fabrication variations. Both IC and printed circuit board variations can be quite large. Because of the dependencies, signal integrity problems can be intermittent on a board, or may vary from one board to another, leading to reduced production yields. Crosstalk is also sensitive to the switching of other traces. This allows it to be distinguishes from other signal integrity symptoms.

4-16



EMC EMC ♦ Radiated/emitted electro-magnetic energy ♦ Emissions standards ● ● ● ●

FCC CISPR VCCI User (industry specific)

♦ Antenna testing ♦ Current probe testing



Notes: EMC, or ElectroMagnetic Compatibility, involves the electromagnetic field from a transmission line that extends into space. This is often referred to as the "far field", because measurements are made at distances that are far away compared to the spacing between traces on the board. ElectroMagnetic Interference (EMI) is the reception of these fields by another system, such as another board or an antenna. Many types of electronics must meet EMC limits. There are several regulatory agencies, such as the FCC (Federal Communications Commission) in the United States. Others include CISPR (Europe) and VCCI (Japan). Medical instruments and automotive electronics, among other industries, have additional requirements.


4-17


EMC measurements are done using an antenna placed at a distance from the board. The board is then moved vertically and rotated to find the maximum radiation. The board fails to meet EMC requirements if the maximum electromagnetic radiation exceeds the EMC limits at any frequency. Current probe testing can be used to pinpoint the source of the current that causes the spectral characteristics of the emissions peaks.

4-18



EMC (Cont.) EMC (Cont.) ♦ Analysis of one net ♦ Check emissions against standards ♦ Assumes differential emissions dominate ●

Use bypass caps near splits and slots

♦ Depends on driver edge rate & layer assignment ♦ Keep traces short on outer layers ♦ Planes block most EMI



Notes: EMC can be checked using the Spectrum Analyzer in LineSim. Emissions are calculated only for a single net. If one net exceeds the EMC limits, the board will probably fail in testing. If the net meets the limits with a suitable design margin, the board has a good chance of passing the antenna tests. Note that only differential emissions are simulated by HyperLynx. If there is a slot in a plane, or split planes, EMI can be higher than predicted. However, for high speed designs to pass EMC testing, it is usually necessary to provide highspeed coupling paths between planes, particularly for high speed signal return paths. This high-speed coupling between planes reduces common mode emissions significantly.


4-19


EMI depends on the transmission line characteristics of the traces and on the driver edge rate. It is highest for long traces and fast driver edges. It also depends on the distance to planes. Placing a trace on an inner layer between planes reduces EMI. EMC problems can be addressed by shortening traces or by placing a problem trace between planes. Termination can be used to reduce EMC problems.

4-20



Symptom Identification Symptom Identification ♦ Simulating a single net ♦ Quickly identify ● ● ●

Delay and skew between receivers on that net Overshoot, undershoot, and ringing EMC for that net

♦ Try various solutions



Notes: Identifying problems begins with simulating a single net. This net may be one that has shown problems in a previous simulation or a previous design. It may be a net that has been identified using Board Wizard's Quick Analysis as a likely hot spot in a layout. Running a scope simulation allows you to identify signal integrity (overshoot, undershoot, and ringing) problems, as well as skew between receivers and propagation delays. While examining this one net, you can run an EMI spectrum simulation. This allows you to check for EMC using an antenna probe. You may also obtain the spectrum for a current at any pin using the current probe. This is useful for identifying the current causing EMC problems.


4-21


Symptom Identification (Cont.) Symptom Identification (Cont.) ♦ Simulating more than one net ♦ Quickly identify ● ● ● ●

Delay, skew, overshoot, and undershoot on each net Skew between receivers on different nets (Version 6.0) Crosstalk voltage coupled due to multiple aggressors Timing effects due to multiple aggressors

♦ Try various solutions



Notes: Crosstalk effects on overshoot and timing on a victim net require simulating the victim net and one or more aggressors together. The victim net can also be an aggressor so it's important to simulate the nets together. This allows you to check the voltage coupled onto a static (non-switching) victim, overshoot and undershoot on both nets, and the change in the victim net's delays caused by crosstalk coupling.

4-22



Handling SI Problems Handling SI Problems Problem

Probable Cause

Solution

alternate Solution

Excesive Overshoot

Impedance Missmatch at Destination Too Much Load on Line

Terminate Line Near Destination Replace DC Termination with AC

Use Slower or RTC Driver Use Higher Current Driver

Bad DC Voltage Level Too Much Crosstalk Line Too Slow Line Too Slow EMC

Alternate Solution 2

Use Series Termination at Driver

Too much Use Slower Terminate at Re-route offending coupling Risetime or Passive wires. Place on inner between wires RTC Driver Receiver layer(s) Not Switching on Check for Use Use Alternate routing Incident or RC series Impedance scheme. effects Termination matched To much Re-Route, ReDistance from place/re-route Source Long net, fast Use Slower Terminate at Re-route offending edge, Risetime or driver wires. Place on inner impedance RTC Driver layer(s)



Notes:


4-23



Identifying Signal Integrity Symptoms Identifying EMC Symptoms Identifying Crosstak Symptoms



Notes:

4-24


Module 5 Running LineSim


5-1

Running LineSim

Running LineSim Running LineSim ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

Open LineSim Stackup Editing Schematic Editing Assigning Models Setting the Simulation Power Supply Voltage Running Scope/Sim Running Spectrum Analysis Terminator Wizard SPICE Writer

5-1 • HyperLynx Signal Integrity Analysis: Running LineSim


Notes:

5-2


Running LineSim

Creating/Opening LineSim Creating/Opening LineSim

♦ New LineSim Schematic ●

Select the New LineSim Schematic icon, or

●

Select the New LineSim File... menu pick, if the schematic exists

♦ Existing LineSim Schematic ●

Select the Open LineSim .TLN File icon, or

●

Select the Open LineSim File (.TLN) menu pick



Notes:


5-3

Running LineSim

Stackup Editing (Cont.) Stackup Editing (Cont.)



Notes: The Stackup Editor, available under Stackup on the main toolbar or as an icon, can be used to modify the stackup to improve signal integrity. You add (and delete) layers and modify both dielectric and metal layer characteristics to correspond to your manufacturing requirements. You can also assign colors to each layer; these colors are used when displaying traces. Also, the stackup view can be saved to a Microsoft-compatible clipboard.

5-4


Running LineSim


Metal Layer


Dielectric Layer


Notes: The impedances values shown in the stackup window are calculated for the Test Trace Width shown in the Edit Layer window. Actual values in the schematic will depend on the actual trace width. Width compensation factors, which account for variations in fabrication during and plating, can be set in Preferences under Options; compensation is applied before impedances are calculated. The layer can also be changed to another layer type in this window. The Advanced option allows you to set bulk resistivity and temperature coefficient for the metal layers. Similarly, the Edit Layer window for dielectrics allows you to set the dielectric constant and the thickness. One use for this is examining the effects of fabrication


5-5

Running LineSim

variations in dielectric constant, which depends on both material and fabrication (for example, FR-4 can vary between 4.3 and 4.9 due to the curing process). The layer can also be changed to another layer type in this window.

5-6


Running LineSim




Notes: The Stackup Wizard, under Wizards on the main toolbar, can be used to check your stackup. The Stackup Wizard will report errors that cannot be corrected. The examples shown here include one stackup with no errors and one where there is no dielectric between two metal layers. While the Stackup Wizard will try to clean up any problems that it finds, you should fix the stackup to make sure the correct information is used.


5-7

Running LineSim

Stackup Editing (Cont.) Stackup Editing (Cont.) ♦ ♦ ♦ ♦ ♦

Left click to add/delete pin Cursor marks selected component Component also highlighted Right click to open the Assign Models dialog box Assign Models dialog box displays model name/status



Notes: To add an IC pin, left click on any gray IC pin symbol in the schematic. To assign a model to this pin, put the cursor over the pin and right click on the same pin to open the Model selection window. The Assign IC Models window opens.

5-8


Running LineSim




Notes: There are about 8,000 models available to choose from, including IBIS models as well as models for ferrite beads, PML (packaged generic parts) and MOD (technology models) in HyperLynx's proprietary model formats. To select a model, left click on Select in the Assign IC Models window, which opens the Select IC Model window. Left click on the radio button to select the library of parts you wish to use, and then select the model by left clicking on the device name and then the pin name. Note that there may be more than one component within a single file, as shown here. After selecting a model, click OK. The Select IC Model window will close, and the Assign IC Models box will now show the model you selected.


5-9

Running LineSim




Notes: When the Select IC Model window closes, the power supply voltage is checked. If the voltage is different for this pin than for the current voltage set for the simulator, you will be asked if you wish to update the voltage for simulation. An IC buffer model may be an input, output, or bi-directional I/O. Once you have selected a model, you can select from the I/O options by left clicking the appropriate radio button in the Buffer Settings area of the Assign IC Models window. When you open the Select IC Model window, you can assign as many models as you want to the pins. To assign the same model to several pins, you can use the

5-10


Running LineSim

Copy and Paste buttons. It is often convenient to assign the models using copy and paste, and then to assign the input and output directions. Under File, there is an option to generate a model finder index, which updates HyperLynxIcModels.CSV in the HyperLynx install directory. The Find Model option on the Select IC Model window then allows you to locate models using keyword searches in this file.


5-11

Running LineSim

Stackup Editing (Cont.) Stackup Editing (Cont.) ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

Left click to add/delete transmission line Left click also makes an “ideal” wire Cursor marks selected component Component also highlighted Right click for transmission line type Radio button selects type Enter text comment Enter width and length under Values tab



Notes: To add a transmission line, left click on any gray transmission line symbol in the schematic. To assign a model, put the cursor over the transmission line and right click. The Edit Transmission Line window opens. You can use the radio buttons to select the type of transmission line (including connectors and cables). The area on the right side of the window displays the properties of the current transmission line. You may use the "Comment" text box to label your transmission line. When you select any type of transmission line, there will be a place to enter the characteristics (usually under the Values tab). The characteristics that can be entered depend on the type of transmission line selected. For example, for a cable, you can choose from a pick list of standard cables, while for a stackup you can

5-12


Running LineSim

specify layer, length, and width. You can use Copy to use the same characteristics for additional transmission line segments.


5-13

Running LineSim




Notes: When you select the Values tab, the Values for the currently selected transmission line type can be entered into the text boxes or selected from a pulldown list. The electrical properties are calculated and displayed.

5-14


Running LineSim




Notes: Coupled transmission lines require that the coupled lines all be of type Stackup. This is because the crosstalk simulation uses information from the stackup to obtain the field coupling. Coupled lines must be in the same row (or column) to be coupled; if they are in different row or columns, they will automatically be assigned to different coupling regions.


5-15

Running LineSim




Notes: Once a transmission line has been assigned a type of Coupled Stackup, a new set of tabs is available in the Edit Transmission Line window. First, the transmission line is assigned to a coupling region using Add to Coupling Region. Once the coupling region has been assigned, the tab name changes to Move to Coupling Region, allowing you to move the transmission line to a different coupling region at any time. The Edit Coupling Region tab allows you to assign length, spacing, and layers to all traces in the coupling region. The field solver tab allows you to view the electric field lines and propagation characteristics of each mode for the selected coupling region. Note that the field solver view can be copied to the Microsoft-compatible clipboard.

5-16


Running LineSim


♦ Parallel Passives: ♦ Series passives:

Left click to add or delete Left click,then select the type from menu (None to remove it) ♦ Set values for R, L, C; models for ferrite beads



Notes: Passive components have both values and parasitics that can be set within LineSim. The parasitics will depend on both the packaging and the connection to the board (through-hole having higher inductance than surface mount, for example). In addition, a via can be modeled by setting the resistor value to zero and setting the parasitics to values typical for your vias. A series component can be removed by setting its type to None. AC components can be removed by left clicking on the component symbol.


5-17

Running LineSim

Assigning Models Assigning Models ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

IBIS (*.ibs) Generic.MOD Easy.MOD *.PML Probes.MOD Bsw.PAK Bsw.FBD Diodes.MOD Open.MOD User.MOD Custom library path



Notes: IBIS (*.ibs): An IBIS model file may provide several buffer models, with different functionality (in/out/bi-di, PCI, AGP, etc.). Usually, both Device and Pin must be selected to fully specify your model selection. Generic.mod: The file contains generic components for several logic families in a variety of edge rates. Easy.mod: A set of generic technology models, used for evaluating effects of edge rates, package parasitics, and driver output impedance. PML: These files contain typical models for packaged parts, including package parasitics for typical packages.

5-18


Running LineSim

Probes.mod: The file contains models for typical input probes for oscilloscopes. Bsw.pak: This file, located in the main HyperLynx directory, contains models for resistor and RC packs. Bsw.fbd: This file, located in the main HyperLynx directory, contains models for ferrite beads and EMC filters. Diodes.mod: This file contains basic diode models. User.mod: This file is set up for models you create using the HyperLynx proprietary .MOD format, and put them here. Open.mod: This file contains models for "open" IC pins with package parasitics. Custom library path: If you specify a new directory path for your library, you should retain the same file extensions as are used in the HyperLynx/Libs directory.


5-19

Running LineSim

Simulation Power Supply Voltage Simulation Power Supply Voltage



Notes: Power supply voltages are set using Edit/Power Supplies. The nominal value for each power supply net voltage must be set. At least one power supply net (Vcc) and one ground net must be specified. There can be several power supply nets, each with its own voltage. At present only one power supply voltage can be used during any one simulation.

5-20


Running LineSim

Scope/Sim Analysis Scope/Sim Analysis ♦ Time-domain analysis of signal integrity ♦ Running the Oscilloscope/Simulator ●

● ● ●

Select the Open Oscilloscope/Simulator icon, OR select the menu Simulate=>Run Scope... Assign the probes to the part pins of interest Setup desired simulation (e.g. rising/falling edge, etc) Click Simulate

♦ Scope probes will be assigned automatically to arbitrary channels ♦ Every net on schematic is analyzed.



Notes: The oscilloscope simulator is used to analyze the signal integrity and crosstalk performance of signals on your schematic. If you have assigned traces to coupling regions, the simulation will include crosstalk coupling effects automatically. Every net on the schematic is simulated at once. This means that large and complex schematics will take longer to simulate than very simple ones. You will want to limit a schematic to alternative topologies for a set of nets, or tradeoffs that you want to look at graphically (such as driver edge rates). There are two ways to open the Oscilloscope Simulator: you may select the Scope/Sim from the main toolbar, or you can click on the Oscilloscope icon. Both open the Scope window. (From the main toolbar, there is also an option to open


5-21

Running LineSim

the Probes window, which is also accessible by selecting Probes on the Scope window.) You can set your probes before running a simulation; if you do not set any probes, the first six will be used automatically. Probes can be set on any IC pin and any pin of a two-terminal component (such as a resistor). All available probe points are shown in the Probes window. If no probes are selected, the simulator will automatically assign them using the first six IC pins.

5-22


Running LineSim

Running Scope/Sim Analysis Running Scope/Sim Analysis



Notes: Note that simulation results are saved only for the probes that are enabled. If you change or add probes, you must rerun the simulation to see the results for the new probes. After simulation, you can enable and disable probes to remove and restore waveforms to the display area. Clicking in the waveform display area places the first crosshair. A second click places the second cursor and displays the cursor values and delta from the first crosshair. A third click clears all crosshairs.


5-23

Running LineSim

Running Scope/Sim Analysis (Cont.) Running Scope/Sim Analysis (Cont.) ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

Driver Waveform IC Modeling Display Vertical scale and offset Horizontal scale Copy to Buffer Copy to Clip Save as CSV Erase Print



Notes: Driver Waveform: Rising Edge, Falling Edge, Osc (for observing both edges at once). Osc has additional settings for frequency and duty cycle. IC Modeling: Slow-Weak, Typical, or Fast-Strong IC driver(s). Selects from the appropriate column of the IBIS or MOD model data tables. Accounts for IC process and package variations. Display: Select which waveforms and information you want displayed together. Vertical scale and offset: Scope display for the voltage waveform, and vertical position of the DC ground (green line). Click right or left markers to increase or decrease the scale. Move slider to change the vertical position.

5-24


Running LineSim

Horizontal scale: Scope display for the timebase for the waveform. Click right or left markers to increase or decrease the timebase. Copy to Buffer: Saves current waveform to the waveform display buffer. You can display up to three waveforms (current, previous, and buffer). Copy to Clip: Copies display to Microsoft-compatible clipboard. Use for pasting results into a document (such as Word or PowerPoint). Save as CSV: Save simulation results as comma separated values. Use for pasting results into a spreadsheet. Erase: Clear the screen of waveforms. Print: Send to a printer.


5-25

Running LineSim

Running Scope/Sim Analysis (Cont.) Running Scope/Sim Analysis (Cont.) ♦ EMC / Spectrum simulator ♦ Frequency-domain analysis ♦ Only one driver on schematic



Notes: The EMC simulator (Spectrum Analyzer) is used to evaluate EMC performance of one route on your schematic. Only one IC pin can be assigned as an output driver during EMC simulation. All IC pins except the one output driver must be either Input or Output High-Z. There are two ways to open the Spectrum Analyzer: you may select the Spectrum Analyzer from the main toolbar, or you can click on the Spectrum Analyzer icon. Both open the Spectrum Analyzer window. Because there is no layout information available, LineSim makes some simplifying assumptions about placement of trace segments. Please refer to the User Manuals for details. If there are coupled transmission traces on your

5-26


Running LineSim

schematic, coupling effects will be included in the simulation. This can be used to evaluate the effects of guard traces and other nearby nets. However, only one driver is permitted; all other pins must be tied to receivers for EMI simulation.


5-27

Running LineSim

Running Scope/Sim Analysis (Cont.) Running Scope/Sim Analysis (Cont.)



Notes: You must set your probe before running a simulation. This can be done by clicking on Settings in the Spectrum/Sim window, or choosing the Probes option under Spectrum/Sim from the main toolbar. The default is an antenna probe, much like the probes used in EMI testing. The settings associated with the antenna probe allow you set the antenna distance. You can examine emissions at a single antenna location and polarity, or sweep to find the maximum radiation location. This can be reached either under the pulldown menu for the Spectrum Analyzer, or under the Settings option on the Spectrum Analyzer window.

5-28


Running LineSim

A current probe is also available; this can be set on any IC pin (such as the driver) or any pin of a passive component (such as a resistor). All available current probe points are shown in the Probes window when Current Probe is selected.


5-29

Running LineSim

Running Scope/Sim Analysis (Cont.) Running Scope/Sim Analysis (Cont.) ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

Driver Waveform IC Modeling Show New / Show Previous Regulations Vertical offset Center Freq and MHz/div (Scale) Erase Print Copy to Clip Save as CSV View Points



Notes: Driver Waveform: Frequency and Duty Cycle. Normally, a duty cycle slightly different from 50% is used to allow both even and odd harmonics to appear in the results. IC Modeling: Slow-Weak, Typical, or Fast-Strong IC driver(s). Selects from the appropriate column of the IBIS or MOD model data tables. Accounts for IC process and package variations. Show New / Show Previous: Select which simulation results you want displayed. Useful for evaluating a proposed design change. These boxes are located under the display area.

5-30


Running LineSim

Regulations: Selected regulations will have the limits shown in the display area, as an overlay to the simulated emissions spectrum. Edit User allows you to enter limits of your own. Vertical offset: RMS values are displayed in dB uV/m (20 log E-field). Click right or left markers to increase or decrease the offset. Center Freq and MHz/div (Scale): Sets the frequency base for the horizontal display. Type in the center frequency. Click right or left markers to increase or decrease the scale factor. Erase: Clear the screen of waveforms. Print: Send to a printer. Copy to Clip: Copies display to Microsoft-compatible clipboard. Use for pasting results into a document (such as Word or PowerPoint). Save as CSV: Save simulation results as comma separated values. Use for pasting results into a spreadsheet. View Points: Display the simulation results as a text file. Useful for checking numeric values.


5-31

Running LineSim

Running Scope/Sim Analysis (Cont.) Running Scope/Sim Analysis (Cont.) ♦ ♦ ♦ ♦

FCC CISPR VCCI User



Notes: Once a simulation has been run and an FFT (Fast Fourier Transform) used to extract the frequency information, the results are plotted in the two display windows. The upper window shows the driver current waveform on a linear scale. The lower window shows the EMC spectrum on a log scale in dB uV/m. If you use the Current Probe option, the lower window displays the spectrum of the current using a log scale. In addition to displaying the EMI spectrum, you can overlay one or more Regulations in the display window. This makes it easy to spot any frequency components that do not meet regulatory requirements. The available regulations include FCC (United States), CISPR (Europe), VCCI (Japan), and User (company

5-32


Running LineSim

or industry requirements). You can use Autoscale to center the highest peaks in the display window.


5-33

Running LineSim

Terminator Wizard Terminator Wizard



Notes: The Terminator Wizard can be used to optimize component values for terminations. There are two ways to open the Terminator Wizard: you may select the Terminator Wizard from the main toolbar under Wizards, or you can click on the Terminator Wizard icon. Both open the Terminator Wizard window. The Terminator Wizard performs several functions:

• Calculating the driver impedance and the transmission line input impedance • Finding termination components or recommending a termination style • Calculating values for terminations

5-34


Running LineSim

• Applying the values to the components on the schematic Component values may be exact, or selected from a set of standard tolerances. To assign the calculated values, click Apply Values. If you close the window without applying values, the schematic is not updated. If there is no termination component on the net, the Apply Values box is grayed out; you must add the components manually, before Terminator Wizard can apply values to them. If the receivers are all near the end of the transmission line, then the capacitor value should be well optimized. In some cases, you may want to further optimize termination capacitors manually, particularly if several receivers are distributed all along a long trace.


5-35

Running LineSim

SPICE Writer SPICE Writer



Notes: SPICEWriter is found under File on the LineSim menu. It is designed for users who wish to perform simulations in SPICE. The transmission line topology for the schematic is translated into SPICE format, along with the passive components, and an SPICE file is generated. The format for uncoupled transmission lines in compatible with SPICE 2G6. For coupled transmission lies, the format is compatible with HSPICE. You may optionally include lead parasitics for your passive components. If lead parasitics are included, SPICE simulations will take longer run, but may improve accuracy if parasitics are significant. SPICE node numbers may start with any number, the default is 100.

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Running LineSim

SPICE Writer (Cont.) SPICE Writer (Cont.)



Notes: You will be prompted for the name of the file.


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Running LineSim

SPICE Writer (Cont.) SPICE Writer (Cont.) * Netlist for net Lsw00 * Design file: CASCADE.TLN * Special Settings: Coupled .SUBCKT Lsw00 100 102 103 107 108 111 * Node

#

= .

********************************************** * Node 100 = U(A0) * Node 102 = U(D0) * Node 103 = U(A1) * Node 107 = U(D2) * Node 108 = U(A3) * Node 111 = U(D3) * Node

0 = Common Return



Notes: Subcircuit starts with comment lines for documentation. Comments begin with ‘*’. No models or circuits are attached for the drivers and receivers.

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Running LineSim

SPICE Writer (Cont.) SPICE Writer (Cont.)

RSA0_1

100

101 50.0

Coupled line: T001 T002

102

RSA1_1

104

101 0

106

0

* Coupled line: T005 T006

108

RSA3_1

110

T007

111

0

113

0 Z0=8.030857e+001 TD=7.889858e-010

0 Z0=8.080424e+001 TD=1.738987e-009

105 107 107 109

0

106

0 Z0=8.030799e+001 TD=8.865251e-010

0 Z0=8.080424e+001 TD=4.347467e-010 0

108

0 Z0=8.030857e+001 TD=7.889858e-010

0 Z0=8.080424e+001 TD=4.347467e-010

111 25.0 0


102

105 33.0


103

0

0

112 112 114

0 Z0=8.080424e+001 TD=4.347467e-010 0

113

0 Z0=8.030799e+001 TD=8.865251e-010

0 Z0=8.080424e+001 TD=8.694935e-010



Notes: Note that resistors (R*), transmission lines (T*) and coupling lines (W*) are all included in the file. No models or circuits are attached for the drivers and receivers.


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Running LineSim

SPICE Writer (Cont.) SPICE Writer (Cont.) ♦ W format is HSPICE-specific

WCascade000 l=0.152400

N=2

105

109

0

106

110

0

RLGCfile=Cascade000.rlc

WCascade001 l=0.152400

N=2

100

103

0

101

104

0

RLGCfile=Cascade001.rlc

.ENDS



Notes: The format for the W components is based on HSPICE, and varies between SPICE products. HSPICE also uses two other files created by SPICEWriter: Cascade000.rlc and Cascade001.rlc.

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Running LineSim


Creating a LineSim Schematic Simulation and Analysis Termination Wizard Simulation with Crosstalk



Notes:


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Running LineSim

5-42


Module 6 Solutions with LineSim


6-1

Solutions with LineSim

Solutions with LineSim Solutions with LineSim ♦ ♦ ♦ ♦ ♦ ♦

Causes Technology Topology Termination Trace Parameters Comparing Solutions

6-1 • HyperLynx Signal Integrity Analysis: Solutions with LineSim


Notes: OUTLINE You have already seen how to identify symptoms of signal integrity, crosstalk, and EMC problems. Now you are ready to find solutions to these problems, and evaluate design tradeoffs using LineSim.

6-2



Causes Causes ♦ Four fundamental solutions ● ● ● ●

Technology Topology Termination Trace Parameters

♦ Use LineSim to ● ● ●

Identify solutions early in the design Quickly evaluate tradeoffs Develop constraints for layout



Notes: You have already seen how to identify symptoms of signal integrity, crosstalk, and EMC problems. Now you are ready to find solutions to these problems, and evaluate design tradeoffs using LineSim. There are three fundamental solutions to signal integrity problems: technology, topology, and termination. Technology: Fast driver edge rates increase the risk of signal integrity, crosstalk, and EMC problems. Slowing the edge rate and increasing the drive strength can help solve signal quality problems.


6-3


Topology: Changing the way a net is routed, or the transmission line characteristics of traces, helps delay and skew problems. Making a net shorter than the circuit length helps solve problems, although it may not always be practical. Termination: Termination, while adding components which do not perform any logic function, is required for long nets with fast drivers. LineSim helps you quickly evaluate different termination strategies and can calculate optimal component values. Getting to a solution quickly requires a combination of experience and tools. LineSim helps you identify solutions early in the design, and to quickly evaluate tradeoffs when there are multiple solutions.

6-4



Technology

Notes: Let's begin by looking at the effect of the driver edge rate. As edge rate gets faster, more ringing is visible at the receiver. In fact, the fastest edge rate may not have the fastest settling time. As seen on the left, the middle edge rate actually settles the fastest. In some cases, an I/O buffer family has options for various edge rates and drive strengths. Sometimes it is possible to trade edge rate and drive strength against each other to improve signal integrity and timing at the receiver. Which driver produces the best edge rate will be highly dependent on the routing and stackup for any given net.


6-5


In the example on the right, the 2mA fast and 6mA slow drivers have similar edge rates at the receiver, but different signal integrity.

6-6



Topology Topology ♦ Signal integrity depends on length ♦ Routing topology (daisy chain vs. star routing)



Notes: The length of the trace also has a significant effect on the ringing. For a longer line, both delay and ringing increase. To eliminate signal integrity problems, the recommendation is that the line be no longer than the critical length (Lc = vel*Tr/6), where vel is the speed of the signal down the line and Tr is the driver edge transition time. Another way of saying this is that the delay in the transmission line should be no more than 1/6 of the driver transition time. For example, for an edge rate of 1 nsec, the critical length is approximately (6 inches/nsec * 1 nsec / 6), or 1 inch. At 250 psec, this length becomes only 0.25 inches! This figure shows how ringing depends on transmission line length


6-7


Careful choice of topology and following topology constraints during layout can prevent many problems. Shortening critical nets and stubs helps reduce signal integrity problems and EMC problems. For example, when skew must be minimized, star routing is preferred over daisy chain routing. Star arms of equal length do not always have equal delay time, depending on which layers are used for routing. LineSim can be used to analyze various topologies, allowing you to select those that improve your design's signal integrity performance. Using LineSim to develop spacing constraints can help you prevent crosstalk before layout is even started. Changing trace width impacts trace delay and impedance. Changing dielectric thickness or materials changes delay, impedance, and even crosstalk and EMC performance. Changing the stackup and layer assignments are topology solutions that can be implemented during design and layout.

6-8



Topology (Cont.) Topology (Cont.) ♦ Signal integrity depends on length and edge rate ♦ If length > critical length, then termination is recommended ♦ Lcrit = vel * Tedge / 6



Notes:


6-9


Termination Termination ♦ Termination styles ♦ Terminator Wizard



Notes: If the edge rate cannot be increased and the transmission line cannot be made shorter, termination is usually required. Typical terminations include a series resistor near the driver, or an AC load (RC to ground or Vcc) at the receiver. The series resistor helps match the driver's output impedance to the transmission line impedance, damping any ringing at the driver end of the transmission line. The AC load helps match the receiver impedance to the transmission line impedance, damping any ringing at the receiver end of the transmission line. Other termination styles, such as pullup resistors, may be required by the I/O interface specification. LineSim is capable of analyzing many common termination styles using the Terminator Wizard. The Terminator Wizard calculates optimum values for

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termination components, saving you the task of running unnecessary Monte Carlo analyses. The Terminator Wizard includes the effects of impedances for drivers, receivers, and segments automatically. If there is no termination, the Termination Wizard can even suggest a termination style. Finally, the Terminator Wizard allows you to specify the tolerance on the termination components, and picks the nearest standard value in that tolerance range. (Exact values are useful for ideal analysis, and on MCMs, where passive components can be fully customized.)


6-11


Termination (Cont.) Termination (Cont.) ♦ Nets with one receiver ● ● ●

Keep as short as possible Series termination, IF additional delay is not a problem Place resistor close to driver

♦ Nets with many receivers ● ●

Use star routing to reduce skew AC Termination – Place R and C together – Place R and C near receiver



Notes: With more than one receiver, skew becomes an issue. Skew is controlled by making the delay time from the driver to each receiver the same. Note that equal delay is not the same as making routes the same length during layout, since signal speed is often different on different layers of the stackup. To achieve the best signal integrity, each routing leg or stub needs to be terminated if its associated stub is longer than the critical length. Often, in practice, this is done by AC terminating each receiver. On a daisy chain with short stubs to receivers, acceptable termination can be achieved by terminating the two ends of the daisy chain. If any stub is long compared to the critical length, then that receiver must be individually terminated.

6-12




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Termination (Cont.) Termination (Cont.)

900mV of undershoot Data integrity may be compromised 1.1 mV of overshoot No termination on “center” stub


Protection diodes turn on


Notes: As an example, let's look at a multi-drop bus with one receiver each on long/short stubs, with and without termination. For each case, simulation can be used to show signal quality at each driver and receiver. In this example, failing to terminate the center stub leads to 0.9V of undershoot, crossing VIL. This could lead to a false clock or a digital data fault. The 1.1V overshoot is sufficient to begin turning the clamp diodes on.

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Termination (Cont.) Termination (Cont.) ♦ Bi-directional nets ● ● ● ● ●

Terminate at each end of the bus AC termination Series termination => longer delay at each end Same rules for stub lengths Same rules for termination location



Notes: A bi-directional net should be terminated at each end of the bus. AC termination is normally used. Series termination at both ends may be used, but the delay will be significantly longer. If there are many I/Os, the same rules for stub lengths and termination location apply as with any net having more than one receiver. Simulation should be used to check signal integrity for each driver.


6-15


Comparing Solutions Comparing Solutions ♦ Simulate technology, topology, termination, and trace parameters ♦ Visual comparisons ● ● ● ●

Scope waveforms Crosstalk amplitudes and timing EMC spectrum CSV and spreadsheets

♦ Explore the solution space ♦ Decide which combination of technology, topology, termination, and trace parameters best suites the design requirements.



Notes: Simulation results allows you to evaluate tradeoffs in a very visual way. For example, by trying two different termination strategies and looking at their receiver waveforms, you can quickly see which produces the better delay and signal integrity. LineSim contains two simulation engines. The Scope Simulator allows you to look at plots of voltage waveforms vs. time. This is useful for checking delay, skew, overshoot, undershoot and crosstalk. The Spectrum Analyzer runs a time simulation for several clock cycles, performs an FFT (Fast Fourier Transform), and gives you a plot of energy (dB) vs. frequency. The Spectrum Analyzer can plot either emitted radiation to an antenna, or the energy in a current (such as in a driver pin).

6-16



Fixing a signal integrity problem often helps reduce EMC problems, since higher EMC is associated with signal ringing. However, a termination that has a small effect on ringing may have a large effect on EMC. The typical design strategy is to change "technology, topology, termination" until the signal integrity goals are met. At this point, simulation results in the scope should look reasonable. Next, the termination component values are adjusted to see how much EMC is improved. Finally, the worst-case combination of driver edge rate, stackup variation, and component tolerances are checked to make sure the design will have acceptable yield during production. Many tradeoffs can be made in LineSim to increase the design margins for timing, signal integrity, crosstalk, and EMC. This makes it easier to meet specifications, and improves the chances of your prototype passing testing first time through. Larger design margins also increase production yield in many cases. Often there will be a couple of iterations between layout and LineSim for critical nets. During layout, nets will be assigned to layers, changing the impedance, skew, and thus the signal integrity and EMC. Since more than one net must be assigned to each layer, crosstalk will change as nets are added to each layer. In a matter of minutes, you can evaluate the impact of suggested layout changes, allowing you to respond faster to changes while critical net are being routed. Once the layout of critical nets has been completed, you can begin running BoardSim. By working from actual layout information for critical nets, you can catch potential problems early, and check out solutions in LineSim.


6-17



Finding Solutions



Notes:

6-18


Module 7 Strategies for Using LineSim


7-1

Strategies for Using LineSim

Strategy for Using LineSim Strategy for Using LineSim ♦ ♦ ♦ ♦ ♦

Design Flow Targeting High-speed Clock and Bus Nets Targeting Known Troublesome Signals Evaluating design tradeoffs Multi-Board Systems Analysis

7-1 • HyperLynx Signal Integrity Analysis: Strategies for Using LineSim


Notes: The best strategy for integrating LineSim into your design environment will depend on your present design process. However, there are some useful techniques that you can put to use immediately. The biggest impact of using LineSim comes when you use it for evaluating routing topologies and termination strategies for critical nets, and making design tradeoffs. When you do this early in the design cycle, you have the greatest flexibility in making optimum tradeoffs. Your choices become be more constrained as architecture and circuit choices are made. Evaluating signal integrity, crosstalk, and EMC implies two things. First, it implies that you have some idea how much noise margin is available for signal integrity and crosstalk. Second, it implies that there is a specification for noise

7-2



and EMI emissions for each net. Because acceptable error levels, such as clock jitter or BER (bit error rate), vary by application, the level of acceptable noise will also vary.


7-3


Design Flow Design Flow ♦ Target high-speed clock and bus nets ●

Most return for your efforts.

♦ Target known troublesome signals ●

Recheck after changes

♦ Evaluate tradeoffs ♦ Make design choices ♦ Document layout constraints



Notes: Ideally, the acceptable noise for critical signals (clocks, buses, etc) is specified in a document. In practice, the specification is often unwritten (and therefore easily violated). Part of the strategy for using LineSim is determining the level of acceptable noise, and documenting it so it can be checked throughout the design cycle. The following steps, when integrated into your design process, can help you build in quality and prevent signal integrity problems right from the start.

• Target high-speed clock and bus nets. This is where you get the most return for your efforts.

7-4



• Target known troublesome signals. If you have seen a problem in a

previous design iteration, you should continue to keep an eye on that signal/net.

• Evaluate tradeoffs. Solutions may involve technology, topology, or

termination. These can be traded against circuit performance, component count, board area, stackup complexity, and production cost.

• Document layout constraints. Constraints may be phrased in terms of

geometry (length) or electrical characteristics (delay or crosstalk coupling), depending on the preferences of your layout staff.

Ideally, these steps are integrated into the architectural and electrical design from the start. This makes performing signal integrity analysis throughout the design cycle most effective.


7-5


High-speed Clock and Bus Nets High-speed Clock and Bus Nets ♦ Most likely to have signal integrity problems ● ● ●

Delay and skew Fast edges Long traces

♦ Most likely to cause EMC problems ♦ Most sensitive to crosstalk ♦ Most likely to cause crosstalk



Notes: Targeting certain classes of nets can be done to make sure critical nets are caught without spending time on those that are not problems. For example, clock nets are sensitive to delay and skew, which are influenced by technology (driver edge rate), topology (routing) and termination. The targeted nets should include all long nets with high-speed drivers. These generally include clock and strobe nets. The targeted nets list also includes bus nets, even though their switching rates are lower, since they are often driven by drivers with fast edge rates. In addition, buses are often routed with long parallel segments in densely routed areas of the board, which may cause significant crosstalk between bus nets as well as with other nets.

7-6



To make it easier to visualize the layout, you can use this information when drawing the schematic for each targeted net. Nets can be drawn to resemble the desired routing (such as star or daisy-chain), and termination components can be placed next to the appropriate ICs. Layout notes can be placed directly on the schematic diagram to specify such things as the maximum distance between the ICs and their termination components. Production notes for stackup can also be placed on the schematic diagram, or in a documentation file.


7-7


Known Troublesome Signals Known Troublesome Signals ♦ Identified for SI/Crosstalk/EMC ● ● ●

Previous design Simulation General suspicion

♦ Maintain the list ● ● ●

Add Do not remove Especially for crosstalk coupled nets



Notes: Once a net has been identified as a risk for signal integrity, crosstalk, or EMC, it becomes a "known" troublesome net. This net may have been identified from a previous simulation, or by actual testing of a prototype. All known troublesome signals should be included in all analysis regressions to make sure any problems stay resolved. Particular attention should be paid to a known troublesome signal with a crosstalk problem. Changes in other nets can affect the crosstalk on this net. Changes in this troublesome net can affect the crosstalk with other nets. Because crosstalk problems involve interactions between the troublesome net and other nets, it can be difficult to anticipate how the crosstalk may change due to a design change.

7-8



For example, a simple termination change can change crosstalk voltages significantly.


7-9


Evaluating Design Tradeoffs Evaluating Design Tradeoffs ♦ Many tradeoffs made during circuit design ● ● ● ● ●

Performance Component tolerance Component count Board area Cost

♦ Tradeoff signal integrity performance ● ●

Overshoot and Undershoot Settling time



Notes: A system designer makes many tradeoffs during circuit design. For example, adding a termination component may increase component count (along with board area and cost), but it can solve a signal integrity problem. You will often find more than one solution, involving choices for technology, topology, or termination. These solutions can be traded against each other. Each solution will have a different impact on circuit performance, component count, board area, stackup complexity, and production cost. Using LineSim to evaluate tradeoffs that impact signal integrity and EMC performance can assist you in making those critical choices.

7-10



Evaluating Design Tradeoffs (Cont.) Evaluating Design Tradeoffs (Cont.) ♦ ♦ ♦ ♦

Terminator Wizard for style and values Termination component values and placement Discrete vs. pack components Simulation for tweaking and tolerances



Notes: One of the choices you can make is the tolerance of termination components. The Terminator Wizard can analyze more than one termination in one pass, calculating the components values for each type. It then presents you with the choice of which termination type to use when Apply Values is clicked. The first type displayed is the "Best" option from the termination styles in the schematic. The Terminator Wizard allows you to select any value in a standard tolerance range. Analysis using LineSim can help you decide if you might need the next lower or higher standard value of a terminating resistor.


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Evaluating Design Tradeoffs (Cont.) Evaluating Design Tradeoffs (Cont.) ♦ Fabrication tolerances ● ● ● ● ●

Stackup (dielectrics and metal) Trace widths ICs (Vcc, temperature, process variations) Packaging parasitics (ICs and passives) Passive components, tolerances

♦ Termination component placement (stub lengths)



Notes: You can vary the stackup to thickest and thinnest dielectrics within the manufacturing tolerances, as well as varying the dielectric constant and metal thickness. The trace width can be varied using the Compensation factor in Preferences under Options. During simulation, you can choose between Fastest and Slowest IC models. You can also vary component values with their tolerance range. This analysis helps you find out how sensitive your design is to variations among boards, components, and ICs in real-life manufacturing. You may find that some designs will require tighter tolerances for board impedance or component values, or that you can use lower-tolerance, and lower-cost, parts in some places.

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The location of termination components can be critical to signal integrity. In LineSim, you can vary the length of the resistor stub, between the resistor and the IC. You can even place the resistor a longer distance away using a transmission line. For an AC load, the distance between the resistor and capacitor can also be varied. This helps you develop constraints for component placement during layout. Since there is only so much real estate next to an IC, the layout designer needs to know which components are critical near which pins - and which can be placed further away.


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Multi-Board Systems Analysis Multi-Board Systems Analysis ♦ Multiple boards ♦ Backplanes and connectors



Notes: LineSim analysis can include nets on more than one printed circuit board, since transmission line models include cables and connectors. This is particularly useful for analyzing signals that are driven from one board to receivers on other boards. Examples include system clocks and data buses that cross a backplane. The transmission line types available in LineSim include standard cables, along with the AMP connector models. Of course, the stackup transmission line type should be used for the net trace segments on each board. A trace that crosses between boards can be drawn as three transmission lines - one for the first connector, one for the cable between boards, and the third is the connector on the second board. More complex topologies can be done using

7-14



additional transmission line segments, as shown here. In this diagram, comments were applied to identify the physical portion of the net represented by each transmission line. The creation of the traces on the boards themselves is done using the stackup transmission line type. If the two boards have the same stackup, then the stackup is drawn just once. If the boards have different stackups, the stackup is made of two stackups, one on top of the other, with a dielectric air layer (er=1.0) between them; typically 1/2" of dielectric is enough to represent the physical separation of the boards for simulation. EMC and crosstalk cannot be analyzed for nets that cross between boards, since LineSim contains no information about whether the cable is flat or has bends and does not know if the second card is parallel or perpendicular to the first card.


7-15



Optimizing Terminations Optimizing Routing Topologies



Notes:

7-16


Module 8 Constraint Generation


8-1

Constraint Generation

Constraint Generation Constraint Generation ♦ ♦ ♦ ♦

Layout Constraints Selecting Constraints Generating Layout Constraints Editing a Constraints File

8-1 • HyperLynx Signal Integrity Analysis: Constraint Generation


Notes: Layout constraints provide communication between the system (electrical) designer and the layout (physical) designer. In some companies, the two functions are performed by the same person; in other companies, the two functions belong in separate departments. Some layouts are done by external service companies. Layout constraints must meet the needs of your particular design flow.

8-2



Layout Constraints Layout Constraints ♦ Electrical vs. geometric constraints ♦ Electrical design ●

Delay and skew in nsec

♦ Layout design ●

Length and matching in inches and mils

♦ If traces change layer ● ●

Conversion between delay & length changes How constraints are presented to autorouter



Notes: There is a fundamental difference in the way most electrical designers and most layout designers think about signals. Electrical designers tend to think in terms of electrical units such as ohms, volts, and nanoseconds. Layout designers tend to think in geometric units such as inches, mils and millimeters. For example, where an electrical designer might talk about a data bus needing to be stable at least 0.5 nsec ahead of the clock or strobe, a layout designer would describe this as needing to keep the data lines at least 3 inches shorter than the clock line. Consider the requirement to minimize common mode noise in a differential net pair. For the electrical designer, this means making sure the two traces have the same total delay. For the layout design, this means making sure the two traces have the same length. At first glance, it seems they are saying the same thing.


8-3


But, when traces are routed on different layers, they have different delays per unit length - so equal length does not provide equal delay unless the each trace segment pair is always together on the same layer. A better constraint phrasing would require the two traces to be side-by-side on a layer, have the same impedance, and go through adjacent vias when layer changes are required. And this still does not specify what to do when the traces must go around obstacles in a crowded section of the board. So before the first constraint is generated, it is wise to give some thought to how those constraints will be expressed. You want to provide as much information as possible for the layout designer. Tradeoffs must be made during layout, and it is usually impossible to meet 100% of the constraints (except for the very simplest boards). The more information you can provide, the better the layout designer can interpret your goals and priorities. If you are doing autorouting, check out how constraints must be presented. For example, if the autorouter expects constraints in geometric form, you know that differential nets may need to be manually routed. (In practice, some autorouters "hang" if all of the constraints cannot be met at the same time - or simply skip the problem net and move on to the next one, leaving some of the design unrouted.) Ideally, in high-speed routing, the critical nets are routed manually, tweaked until you are happy, and an autorouter can then do the remaining nets.

8-4



Selecting Constraints Selecting Constraints ♦ Selecting constraint types ● ● ●

Autorouters Manual layout Critical net rules

♦ Common constraints ● ● ●

Delay / Length Skew / Length Matching Termination placement



Notes: Which types of constraints you use depends on the intended goal. If the constraints will be used to drive an autorouter, then only those constraints that can be input to the autorouter are of interest. If constraints will be used to guide manual routing, then any constraint that improves the signal integrity can be included. Length constraints are used to make sure signals satisfy timing requirements. For delays on critical nets, component placement and orientation can be as important as the routing. This is why constraints need to be addressed early in the design, while there is still time to change placement and orientation without ripping up weeks of work.


8-5


For signal integrity purposes, the most common constraint is the physical length of an unterminated trace. When this length is exceeded, a termination is required. With experience, layout designers can use the Terminator Wizard to optimize component values. Proper termination reduces ringing, which usually improves EMC too.

8-6



Selecting Constraints (Cont.) Selecting Constraints (Cont.) ♦ Crosstalk constraints ● ●

Trace separation Maximum parallel length

♦ EMC constraints ● ●

Maximum segment length Layer assignment

♦ Net classes ● ●

Nets with fast edges Non-critical nets



Notes: Crosstalk involves constraints between pairs of nets. The constraint is usually expressed as a maximum parallel length and minimum spacing. However, the length and spacing constraint values depend on the layers assignment. The coupling depends on the trace layer, and on the distance to the nearest plane. Even if two traces are on different layers, they will have some coupling unless a plane is between them. This means that crosstalk constraints involve several variables: layer assignment, stackup (layer spacing and distance to planes), and maximum parallel length as a function of the spacing. Since EMC involves radiated emissions, constraints are usually applied to signals routed on the TOP and BOTTOM layers. The constraints may be expressed as maximum segment length or maximum trace length on those two layers. At


8-7


higher speeds, where emissions from traces routed at the edge of the board become significant, a constraint on the minimum spacing between the trace and the outer edge of the board can be applied to the inner signal layers. Constraints may be applied to every trace, or to selected classes. For example, since crosstalk depends on edge rate, the spacing and parallel length constraints may be applied to just the class of nets with a specified range of edge rates. Once you have a good idea of the constraints you plan to use, you can set up some of your critical nets in LineSim. Simulation can then be used to analyze the performance for signal integrity, crosstalk, and EMC with various constraints to decide which constraints are most critical to your design.

8-8



Transmission Line Impedance Transmission Line Impedance ♦ Impedance influenced by: ● ● ●

Trace width Trace spacing Dielectric and metal properties

♦ Fabrication variation ● ● ●

1% along one trace 3-5% between boards in a run 10-20% between boards over time



Notes: The Stackup Editor shows you the transmission line impedance for each signal layer, based on a user-defined trace width. To achieve a specific impedance (such as 50 ohms), you can change the trace width, dielectric thicknesses, and copper thickness until the desired impedance is reached. Having another trace nearby changes the impedance. Once you have close to the right impedance, you can add traces on each side, and pick your spacing and width constraints. In the actual layout, there may not be close neighbors for some traces, or the spacing may be larger than minimum. The best constraints make your impedance less sensitive to these variations.


8-9


The manufacturing process will add variation. The prepreg (starting material) composition choice, firing cycle, and other process steps typically introduce 10% to 20% variation in impedance. Measurements in a closely controlled production test showed 1% variation along a line, and 3% variation between boards in a single run.(1) If transmission line impedance is critical to your design, you may wish to work closely with your board manufacturer to specify impedance control and to find out how much it will cost. (1) Information courtesy of Doug Brooks, UltraCAD Design Inc.

8-10



Delay and Length Constraints Delay and Length Constraints ♦ Absolute constraints ● ● ●

Setup and Hold timing Settling time D1 > 10 nsec, D2 < 1 nsec

♦ Relative constraints ● ● ●

Skew control Self-timed circuits D1=D2 +/- 0.2 nsec

♦ Constraints for each net class



Notes: Delay constraints can be absolute minimum or maximum (D1 > 1", D2 < 0.3 nsec) or relative (D1 > D2). These constraints can be used for several design goals, such as maximum delay constraints for performance (system timing); minimum delay constraints so specified data lines switch when others have settled; relative delay constraints for reducing clock skew. Clearly, delay constraints can be used for a wide variety of timing requirements. Delay constraints can also be expressed as length constraints. The main problem is that the propagation speed for a signal on a trace may vary 2:1 between signal layers, being faster on the outer layers and slower on the inner layers. In some routers, and manual constraint lists, your length constraints can be specified separately for inner and outer layers. However, if the same speed or length


8-11


constraint is used on all layers, the design will be either severely over-constrained (making the layout job more difficult) or under-constrained (risking timing failures). LineSim lets you quickly determine timing and length constraints. LineSim can help you correct delays from the data book (usually measured under fixed capacitor loads) to on-board delays, which are affected by both transmission lines and capacitive IC inputs. This is covered in the Technical Application Note "Timing Correction for Flight Time Compensation", available from HyperLynx.

8-12



Delay and Length Constraints (Cont.) Delay and Length Constraints (Cont.) ♦ ♦ ♦ ♦

Converting delay to length Use Stackup Editor Use trace “routed” in LineSim Watch for SI & crosstalk effects



Notes: You can use LineSim to convert a timing constraint to a length constraint. The delay and length of each transmission line is displayed on the LineSim schematic, allowing you to calculate the propagation speed on the layer (speed = length/delay). Note that the delay will change with the trace layer, as well as width and spacing and dielectric thickness. If any of these are changed, the new delay will appear on the schematic. Also, the delay of an actual trace may be different from the value shown in the stackup editor window, if the test trace and the schematic trace have different widths. Signal integrity and crosstalk must also be accounted for in calculating propagation delays. As was seen earlier, signal integrity problems can lead to multiple threshold crossings; data is not valid until the last threshold crossing,


8-13


while clocks may trigger latches on every threshold crossing. Crosstalk can lead to a false clock edge. And finally, crosstalk, can lead to a variation in propagation delay of 4:1 or more, as seen here. Simulation in LineSim can help you decide the maximum transmission line delay (or length) before termination must be used to avoid multiple threshold crossings. For example, if the edge time is 500 psec (0.5 nsec), then any line longer than 2 inches on FR-4 should be terminated. While it may not be practical to keep all nets shorter than that, a recommended length can be used as a constraint. If nets can be kept shorter than this constraint, the number of termination components (and product cost) can be reduced.

8-14



Delay and Length Constraints (Cont.) Delay and Length Constraints (Cont.) ♦ Matching constraints for skew control ♦ Absolute constraints ●

T1-T2 < 0.1 nsec

♦ Relative constraints ● ●

T1-T2 = T3-T1 D1 to D4 arrive no later than C0

♦ Converting to length constraints



Notes: Matching delays are often used even when total delay is not critical. Matching constraints can be used for a number of purposes, such as controlling skew between receivers on a single net or between clock and data pins at an IC. For example, source synchronous nets, where the data bus is strobed with a "clock" that has a matched delay rather than a traditional clock with a fixed cycle time, required close matching. For differential nets, delay matching makes the two halves of the signal arrive at the receiver at the same time and reduces common mode problems; even a small mismatch can cause severe signal integrity problems. Matching constraints can be absolute minimum and/or maximum value (T1-T2 < 0.1 nsec) or relative (T1-T2 = T3-T1 within tolerance). For example, a matching


8-15


constraint might read "nets D1 to D4 must arrive no later than the clock signal C0, and matching across all 5 signals must be within 100 psec"; this example combines both absolute and matching requirements. Matching constraints may be expressed as length requirements using the same techniques described earlier. As with expressing delay constraints as length constraints for individual nets, care must be taken to avoid over-constraining or under-constraining lengths.

8-16



Width and Spacing Constraints Width and Spacing Constraints ♦ Crosstalk rules -> spacing rules ●

Simulation

♦ Width and Spacing influence ● ●

Impedance control Crosstalk control

♦ Can specify for each layer ♦ Develop guard trace rules



Notes: Controlling crosstalk requires keeping aggressor traces far enough away from victim traces. The tighter your crosstalk specifications, the greater the spacing must be. Crosstalk coupling is also influenced by the stackup, including the distance to the nearest plane, so spacing constraints may be specified separately for inner and outer layers. In some cases, guard traces may help to reduce crosstalk; in other cases, they may actually make the problem worse - and you can use LineSim to tell you whether they help or hurt. In LineSim, you can quickly set up transmission lines, and assign them as Coupled Stackup lines to see crosstalk effects. You can vary both trace width and spacing. Guard traces can be connected to ground through a via (resistor). Running the Field Solver (under the Transmission line tabs) gives an easily interpreted graphic


8-17


showing where electric field lines go - if most of the lines go between signal traces, then crosstalk will be higher than if most of the lines go to a plane. Once drivers and receivers have been added to the LineSim schematic, Scope simulations can be used to check crosstalk effects. Typically, the victim net is modeled as Stuck Low or Stuck High, which allows you to see the coupled crosstalk voltage clearly. Note that the coupled crosstalk is usually different for Stuck Low and Stuck High, since the output impedance in the two states is usually different for the victim's driver. To see the variation in delay on the victim net due to crosstalk, the victim net must be switching. Aggressor nets can be switched in various combinations to see the impact on crosstalk voltage or delay. Often the biggest impact (min and max delays) is with all aggressors rising and all aggressors falling.

8-18



Termination Constraints Termination Constraints ♦ Terminator Wizard for style and values ♦ Constrain component placement ● ● ●

Relative to driver or receiver pin Maximum stub length to pin Maximum separation for R and C

♦ Specify termination prior to layout ● ●

Can specify for L > Lcrit Less rip-up and reroute



Notes: For signals that you know will require termination, you can use LineSim to test termination strategies, and then use the Terminator Wizard to optimize component values. By adding transmission lines at termination components, the effect of trace length between termination components and drivers (or receivers) can be observed in simulation. Termination constraints can specify both electrical requirements (termination style and component values) and layout constraints (component locations). For example, for an AC termination, a constraint might require the maximum distance from the receiver to the resistor be no more than 0.5", and from the resistor to the capacitor no more than 0.2".


8-19


Layout Constraints Layout Constraints ♦ System designer develops constraints ● ●

Overconstrain = no layout Underconstrain = poor signal integrity

♦ Work closely with layout designers ● ● ●

Review layout after placement Review layout after critical nets routed Update terminations



Notes: During layout, as the trace length between the driver and receiver varies, the optimal value for the termination components may change. Experienced layout designers can use LineSim decide which nets exceed the critical length, and optimize component values "on the fly", allowing the layout to be completed more quickly. Even in this case, the design engineer should always review the layout after initial placement, after critical net routing, and after final routing, and check termination strategies and component values at each point. By selecting terminations prior to layout, you reduce the likelihood of having to rip up and reroute a section of the board to make room for more terminators. Also, you assure that terminators will be located close to the IC pins, rather than being placed too far away to provide any benefit. Board area can be reduced, since

8-20



terminators are used only where required. Once the layout is complete, you can use BoardSim to check your termination component values using actual routing, and make any necessary changes.


8-21


Editing a Constraints File Editing a Constraints File ♦ Document impact on signal integrity ♦ Document WHY as well as WHAT ● ●

Document simulation results Use the Copy to Clipboard

♦ Guidance during layout ♦ Rules for autorouters



Notes: As you generate constraints, you will want to document them in a file. You may use the General Purpose Editor provided with the HyperLynx software, or any editor of your choice, to record your constraints and notes. In particular, notes on critical lengths and on how delays are translated to lengths on various layers can prove helpful to the layout designer. Software tools for generating constraint files from LineSim are available, depending on your targeted placement and routing tools. You can also manually enter your constraints into your layout tools. Remember that the text file you create provides additional information. By saving your notes, you can provide memory aids to yourself and guidelines to the layout designer. The more information you obtain from simulation, and the more

8-22



complete the notes you provide, the more likely your design will meet both signal integrity and schedule requirements.


8-23



Generating Signal Integrity Constraints



Notes:

8-24


Module 9 Creating Models


9-1

Creating Models

Creating Models Creating Models ♦ ♦ ♦ ♦

Modeling requirements Creating MOD models Creating IBIS models Testing an IBIS model

9-1 • HyperLynx Signal Integrity Analysis: Creating Models


Notes:

9-2


Creating Models

Modeling Requirements Modeling Requirements ♦ How will the model be used? ● ● ●

Edge rate and driver strength effects Architecture (PCI 133, GTL+, etc.) Accurate models for design tradeoffs

♦ Obtaining models ● ● ●

Vendors / manufacturers In-house modeling Purchase from a third party

♦ MOD and IBIS models



Notes: Modeling requirements for any given model depend on how the model will be used. For early I/O architecture decisions, a model that is typical of a technology (such as PCI 133) is adequate. Also, tradeoffs between edge rates and driver strengths can be made with simple models. For detailed design tradeoffs, you will want models that more accurately represent vendor parts. Models can be obtained from vendors, created in-house, or purchased from a third party. During the early stages of the design, you can use the HyperLynx MOD or PML libraries. You can also create your own MOD models. These models allow you to quickly evaluate the tradeoffs between driver edge rates and signal integrity, allowing you to focus on the ICs and I/O technologies that can meet your design requirements.


9-3

Creating Models

In the later stages of the design, IBIS models are usually used. IBIS models may be derived from SPICE simulations, or from actual measurement results. If you are simulating just a few nets and IC pins, you might even use SPICEWriter to extract the transmission lines and then simulate with SPICE subcircuits and transistor models.

9-4


Creating Models

Creating MOD Models Creating MOD Models



Notes: Using MOD models gets you started simulating as quickly as possible, even before you have IBIS models. The data for a MOD model is based on typical I/O buffer characteristics of an integrated circuit (IC). Because the models are not based on actual device data, they should be used only for comparing performance of logic families for the I/O architecture. The data required for a MOD model is typically found in a databook. In some cases, an I/O specification (such as the PCI 133 spec) may contain enough details for you to estimate reasonable parameters. To create or edit a MOD model, you choose Databook IC Models under Edit on any main menu. The MOD model editor is available under Edit on the main


9-5

Creating Models

HyperLynx menu, or within LineSim or BoardSim. The name of the model library file and the device model name must be specified when opening or saving a model. When saving a model using Save, or Save As, the file extension must be MOD. Models can be saved to any *.MOD file in your Libs directory (normally c:\HyperLynx\Libs) except Easy.MOD and Generic.MOD. User.MOD is already set up for your use, and you can create new *.MOD files. A model can be deleted by entering the Model Library and Device Model, and then clicking Delete. You can edit models in Generic.MOD and Easy.MOD, but you must use Save As to save them to a new library.

9-6


Creating Models

Creating MOD Models (Cont.) Creating MOD Models (Cont.)



Notes: Every MOD model contains both input and output parameters. The input model is a resistor to ground and optional clamp diodes (one to each rail). The output model is a pair of driver transistors and optional clamp diodes. The drive transistors can be connected as normal, 3-state, open-drain or open source outputs. The drive transistors can be any of the standard types: CMOS, ECL, Schottky, Ramp, or Open. "Ramp" allows you to create a resistor driver, which switches between OFF and the resistance value. "Open" removes that transistor from the driver circuit, and is used for open-collector (or open drain) outputs. The resistance of the driver transistor is the ON resistance when the transistor is switching. You can estimate this from the midpoint slope of the I-V curve in the


9-7

Creating Models

databook. Avoid using the slope near IOH or IOL, since these will give you an unrealistically high resistance; normal resistances are around 5 ohms to 25 ohms. For MOD models, the slew time is the time to switch between 10% and 90% of the output signal swing. The offset voltage models the internal biasing of the output transistors. This offset voltage is added to Vss for calculating "Low" output voltages. For example, to make an ECL driver switch to -1.55V when Vee = -4.5V, set the low-side offset voltage to +2.95V.

9-8


Creating Models

Creating MOD Models (Cont.) Creating MOD Models (Cont.)



Notes: Clamp diodes are available for both input and output ports. Silicon and Schottky clamp diodes are supported. The diode resistance is the slope of the V-I curve for the diode once it is fully turned on; this value is typically a few ohms. The buffer capacitance is the total capacitance seen at the I/O pin. This includes the clamp diodes, driver transistors (drain junctions), input transistors (gate oxide), and metal routing on the integrated circuit. The default power supply is the voltage rail from which the buffer is operated (the other rail is assigned to ground as a reference). In BoardSim and in LineSim, you may change this power supply voltage. The offset voltage can be used to adjust the other side of the signal swing.


9-9

Creating Models

The input buffer may have a different capacitance from the output buffer. The input also has an input resistance and optional clamp diodes. VIH and VIL are the input logic thresholds for the logic family. Input and output characteristics may be quite different for the input and output of a bi-directional buffer. If the buffer has only an input or only an output, both sets of characteristics are still created in the MOD model. To avoid accidentally using a model in the "wrong" direction, you can use very high output resistance and very low input resistance for the "unallowed" polarity. The driver parameter Vmeasure and the receiver parameters VIH and VIL are used for start and stop points for pin-to-pin delay measurements in BoardSim's Board Wizard. Rload, Vload, and Cload are the manufacturer's test load components for measuring delays; simulating with this load determines the offset for correcting signal delays on the board to include both the propagation delay through the IC at a known load and the simulated pin-to-pin propagation delay on the transmission line.

9-10


Creating Models

Testing MOD Models Testing MOD Models ♦ Create LineSim schematic ●

Add Rload, Cload, Vload

♦ Simulate ●

Check edge rate against data sheet

♦ Use transmission line and receiver ● ●

Check ability to drive typical load Receiver input clamp works

♦ Edit model if necessary



Notes: Once you have created a MOD model and saved it, it can be tested using LineSim. The biggest reason to test models is to make sure they function as expected in simulation, and that there are no glaring typographical errors. Both input and output devices should be checked. In a new LineSim schematic, add a driver and a load, assign the new model to the driver, and you are ready to simulate. If you use the manufacturer's Rload, Cload and Vload as your load, driver edge rates and signal swings should match the data sheet fairly closely.


9-11

Creating Models

If you replace the passive load with a receiver, assigning your new model to the receiver, you can check the clamp characteristics. If you add a transmission line with the receiver, you can check the driver's output impedances. If any problems are observed, you can change a MOD model by entering the Model File name and Device Model name on the Edit Databook Model dialog box. This brings up the model. Once you are done editing, you can save the model back and overwrite over the old model with the new one.

9-12


Creating Models

Creating IBIS Models Creating IBIS Models



Notes: Using IBIS models gets you better simulation results that using databook models, since IBIS models are built from either Spice simulation or measurement data. IBIS models also include package effects. Both LineSim and BoardSim convert the L and C for the package pins into transmission lines for simulation to improve accuracy. To open the Visual IBIS Editor and create or edit an IBIS model, choose IBIS IC Models under Edit on the menu. The IBIS model editor is available from the main HyperLynx window, or from LineSim or BoardSim. With the Visual IBIS Editor, you can edit IBIS files, view data tables graphically, run the IBIS "golden" parser, test an IBIS model in LineSim, and read IBIS documentation. The commands can be accessed from the dialog boxes or from the icons.


9-13

Creating Models

You can crate new models using the Easy IBIS Wizard, or edit existing models by opening the IBIS model file. Once you have entered all of the sections required in an IBIS model, you should run the parser (red check mark) before saving the model. File extensions must be .ibs and files must be in the default model library directory (normally C:\HyperLynx\Libs). When you build an IBIS model using the Visual IBIS Editor, default table data is used to fill in the tables. For accurate models, these default tables must be replaced with actual device data, either from measurements or from Spice simulations. Buffer models can be created externally, and copied into the IBIS model file in the editor.

9-14


Creating Models

IBIS Model Data and Parameters IBIS Model Data and Parameters

♦ ♦ ♦ ♦

IBIS Standard 3.x Component/Device models I/O buffer models Pin assignment

| PIN 27 31 A2 N9 34 39

signal DQ24 A7 NC VCC RAS2# VSS


buffer D_Q INPUT_1 NC POWER INPUT_3 GND Copyright © 2002 Mentor Graphics Corporation

Notes: Every IBIS model must follow the IBIS 3.X specification. IBIS is a backcompatible standard, so older models automatically meet the 3.X specification. If you are creating a new model using the Easy IBIS Wizard, you can either create a template, or a complete model with default table data. Typically, an FPGA model from a vendor has all of the buffer models, but only a few pin names are mapped to show the format and available buffer types, since most pins can be assigned specific buffer models by the user. In this case, you need to create the pin assignment section, using a text editor or script; the file should then be saved under a new name. Pin names in the model must match pin names on the schematic. (Example shown here).


9-15

Creating Models

Before creating your first IBIS model, it is recommended that you read the IBIS 3.2 specification to familiarize yourself with the model structure and terminology. For example, it is helpful to know that the IBIS specification uses 20-80% points to define transition times.

9-16


Creating Models

IBIS Model Data and Parameters (Cont.) IBIS Model Data and Parameters (Cont.)



Notes: The Easy IBIS Wizard provides a set of dialog boxes to guide you through model creation. The Wizard then takes the data and puts it into the standard IBIS format. When you save the file, just remember that IBIS limits file names to "8+3" format (such as "abcdefgh.IBS"). Once you enter information on any dialog box within the Easy IBIS Wizard, clicking on Next or Back will take you forward or back within the dialogs. Click Finish on the last dialog box to have the file created and saved. The first dialog box defines the name of the integrated circuit. This may have any length, but it is often best to make it the same as the file name. Spaces and tabs are not permitted in this name.


9-17

Creating Models

The next three screens allow you to enter text for documentation. It is important to note whether the data came from Spice models or from measurements, as this has an impact on things like "acceptable data noise" in the tables.

9-18


Creating Models




Notes: Note that IBIS has a line length limit of 80 characters, and it will be necessary to use the to terminate each line of typing in the text fields in these windows. The Notes page can be used for any documentation related to the product that might be of interest to the end user of the model. The Disclaimer screen contains a standard disclaimer statement. Many companies have their own disclaimers. As with the Notes page, it is necessary to use the to terminate each line of typing in the text fields in this window.


9-19

Creating Models




Notes: The Additional Header Info window provides a place to enter name of the Manufacturer, which is required in IBIS. This is normally the name of the company producing the physical component (usually the silicon foundry). A contact name and email should be provided, so end users can resolve their questions quickly. A contact phone number is useful for supporting internal end users.

9-20


Creating Models




Notes: Once all of this textual information is entered, you are ready to start defining the IBIS model data. Easy IBIS contains many built-in data blocks, such as package information for standard packages. A predefined package can be selected by clicking on the Predefined option button and highlighting the package name. A User Defined Package can be selected by clicking on the User Defined Package option button, entering the number of pins and the default pin parasitics. When you click Next, your selection is remembered. If many of the pins in a User Defined Package have the same parasitics, use those parasitic values for the defaults to reduce later typing.


9-21

Creating Models




Notes: The Pin Data dialog box allows you to assign a pin name (such as A3) and a signal name (such as IN1) to each pin. The pin names must match the schematic and layout tool pin names. The pin parasitics for each pin can be entered here (in the example, L has been changed from 2 nH to 3 nH); these values will override the defaults for the specified pin only.

9-22


Creating Models




Notes: The next dialog box sets up the scale factors for generating MIN/MAX data. IBIS buffer models allow three columns of table data: TYP, MIN, MAX. All TYP values will be automatically scaled to generate MIN and MAX columns. If you wish to have MIN and MAX tables created from TYP data, specify your desired MIN and MAX scale factors. If you will be pasting in buffer models that contain MIN/MAX columns, use the default scaling parameters. The scaling factors are applied to the package parasitics, the on-chip capacitance (Ccomp), and the dt portion of dV/dt. Power supply voltage is scaled +/- 10% for MIN/MAX calculations; this produces a conservative overscaling for power supplies with tighter tolerances. Typical scale factors for CMOS circuits are


9-23

Creating Models

roughly 0.5 and 2.0, but actual scaling may vary depending on the buffer technology and circuit design.

9-24


Creating Models




Notes: The next dialog box allows you to assign buffer models. You can edit a buffer model here; however, it is usually easier to use cut-and-paste operations to insert the buffer model after the IBIS file is created. The next dialog box allows you to edit existing buffers that are supplied with the Visual IBIS Editor (similar to Easy.MOD models), or to type in new buffers. If you have a new buffer model, it is usually preferred to use cat-and-paste to add the buffer to your model. To make this easier, you could create a New Buffer at this stage, and give it a dummy name (such as "XYZ1"). Later, when you are adding the buffer models, you can do a global replace on XYZ1 with the actual model name.


9-25

Creating Models




Notes: The next step is to assign buffer models (such as CMOS,5V,FAST,INPUT) to each pin. In addition to the signal buffers, pins can be connected to POWER, GND, or NC (No Connection). To assign a buffer to a pin, click on the buffer, click on the pin, and then the right arrow. You can do this for several pins that use the same buffer without reselecting the buffer each time. The pin name and its buffer assignment will appear in the left box when you select a different buffer model. Note that at least one pin must be connected to POWER and one to GND. To unassign a buffer, click on the pin in the right column and then click on the left arrow.

9-26


Creating Models

IBIS Model Data and Parameters (Cont.) IBIS Model Data and Parameters (Cont.) ♦ Click Finish ♦ IBIS model is formatted ♦ Saves the model file ● ●

Eight character limit Extension is *.ibs

♦ Opens in Visual IBIS Editor



Notes: Clicking Finish opens the Enter IBIS File Name dialog box. The file name is limited to eight characters by IBIS, and the file extension must be ibs. The IBIS file is generated, saved, and opened.


9-27

Creating Models

Testing IBIS Models Testing IBIS Models ♦ ♦ ♦ ♦

Check for errors Check for warnings Check for other problems Two key types of checks: ● ●

Visual IBIS Editor checks Simulation in LineSim



Notes: The biggest reason to test models is to make sure there are no errors. For IBIS models, there are two types of testing: quality checks made within the Visual IBIS Editor, and simulation in LineSim. To test a model within the Visual IBIS Editor, you should first run the IBIS Validation Check (IBIS Parser), and then check the IBIS buffer data graphically. Finally, you should use the Test feature to automatically create a LineSim schematic for testing your model.

9-28


Creating Models

Testing IBIS Models (Cont.) Testing IBIS Models (Cont.)

♦ IBIS Validation Check ♦ IBIS "Golden" Parser on CD ♦ Check IBIS web site for updated parser (and download)



Notes: Quality checking begins by running the IBIS Validation Check on your model by clicking on the IBIS Validation Check icon. HyperLynx includes the EIA's most recent IBIS "Golden" Parser when the product CD master is created. This parser can also be downloaded from the IBIS web site to get the most up-to-date version. The validation check runs the IBIS parser and reports both errors and warnings. Errors must be fixed, and warnings should be fixed or else documented in the header. One common warning is "TYP not between MIN and MAX". This can be caused by several things, such as exchanging the TYP and MIN columns, incorrectly dividing the output current between driver transistors and clamp diodes, or even noise in measurement data. The easiest way to check these is to


9-29

Creating Models

view the data graphically, using the tabs under the Views icon. You can view I-V tables, rising or falling V-T tables, and VDD or GND Clamp tables.

9-30


Creating Models

Testing IBIS Models (Cont.) Testing IBIS Models (Cont.) ♦ In the Select tab, select Pin/Signal to test a buffer model



Notes: The Select command opens a dialog box which lists all components in the file in the first column. (Remember that one IBIS file may contain many components and buffers.) For the selected component, the list of pins or signals is listed in the next column; the list can by toggled between pin names and signal names using the option button above the column. Once you have selected a pin and you see the desired buffer name displayed, you are ready to click on the Views icon. A visual check of the waveforms can spot things that are indicate possible problems. Since these problems may cause the simulator to run into problems later, it is better to catch them as soon as possible. One typical problem seen in models is a non-monotonic I-V or clamp diode waveform ("glitch"). A slope inversion in the I-V waveform can indicate potential convergence problems for


9-31

Creating Models

simulation. Another common problem is excessively large currents in diodes; this can lead to numeric overflow problems. If you do a quick check of each waveform, you can assure yourself that the models pass these visual checks. Each waveform type has a tab, as does the pin information. If no data table is available under a tab, a brief message appears instead of a plot. If there is more than one table, such as Rising Waveforms, using the pulldown arrow on the right side of the table name will present a list of available tables. TYP, MIN, and MAX data are plotted together, making it easy to identify potential problems, such as where TYP is not between MIN and MAX.

9-32


Creating Models

Testing IBIS Models (Cont.) Testing IBIS Models (Cont.) ♦ Select different Views Tabs to check graphical views of data for anomalies



Notes:


9-33

Creating Models

Testing IBIS Models (Cont.) Testing IBIS Models (Cont.) ♦ Simulation in LineSim ●

The ultimate test

♦ Test against data sheet ● ● ●

Rload Cload Vload

♦ Test driving typical load ● ●

Board trace and receivers Clamp diodes work



Notes: Once you are done checking the graphical views, you should test the model using LineSim. A simple LineSim schematic (driver with resistor load) is automatically created when you click on the Test icon. The presently selected pin/model will be used for the driver. This opens a small LineSim window schematic loaded with a driver having the model already assigned and a 50 ohm resistor load. Running rising edge and falling edge simulations allows you to check voltage levels and edge rates. If you want to test the model for more complex loads, you can edit the schematic. This is particularly useful for testing using the manufacturer's Rref, Cref and Vref; with this load, driver edge rates and signal swings should match the data sheet.

9-34


Creating Models

If you replace the load with an unterminated transmission line and a receiver using your new model, you can check the clamping diodes and clamp voltages. If any problems are observed during the model validation process, you can edit the IBIS model file by opening it in the Visual IBIS Editor or any text editor (such as the HyperLynx General Purpose Editor). This brings up the IBIS model for editing. Because there can be many components and many buffer models in one IBIS file, you need to exercise care in selecting where to make changes. Once you are done editing, you can save the file and validate the revised model.


9-35

Creating Models


Creating a MOD Model Testing an IBIS Model Creating an IBIS Model



Notes:

9-36


Module 10 The BoardSim User Interface


10-1

The BoardSim User Interface

The BoardSim User Interface The BoardSim User Interface ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

Mouse Use Dialog Boxes The BoardSim Toolbar and Icons Viewing the Layout Selecting and Highlighting Nets Assignment of Models and Values SPICEWriter Report Files The HyperLynx General Purpose Editor Help Files and Manuals

10-1 • HyperLynx Signal Integrity Analysis: The BoardSim User Interface


Notes:

10-2



Mouse Use Mouse Use ♦ Any compatible mouse ♦ Left mouse button to select options ● ● ● ●

Pulldown menus Area for Zoom Area Nets selected from pick list Components not selectable

♦ Right mouse button rarely used ♦ Middle mouse button never used



Notes: The BoardSim User Interface is mouse-driven. Some operations cannot be accessed from the keyboard. For example, to select OK in a window, the left mouse button is used, and the (ENTER) key is ignored. This allows you to use the to enter data and then update information displayed within a popup window without closing that window. The left mouse button is used as the Select button. Nets selected from pick list rather than using the mouse, and components not selectable at all. The right mouse button is rarely used. The middle mouse button is not used. The left mouse button is also used to define the area for the Zoom Area command.


10-3


Dialog Boxes Dialog Boxes ♦ ♦ ♦ ♦ ♦ ♦

Open based on context Radio buttons Check boxes Text entry Tabs Informational text



Notes: Windows appear when certain pulldown menu items are selected. Windows may contain several selectable tabs or overlays. By left clicking on the tab on the top section of the window, you can select which overlay is displayed. A window may contain radio buttons or check boxes for selecting options, boxes for text entry, or tabs for selecting a window overlay. Windows can be closed by clicking OK/Close or the "X" in the upper right corner of the window.

10-4



The BoardSim Toolbar and Icons The BoardSim Toolbar and Icons

File

Edit

Multi-board View Zoom, etc. Open BoardSim

Open LineSim

Layout Translator Open New LineSim

Select nets/models/ Quick terminators

Oscilloscope/Simulation & EMC Simulation (Spectrum analyzer)

Edit Stackup

File Editor

Generate Reports Setup Crosstalk analysis

Previous Zoom

Zoom Area

Select Net

Quick Terminator

Select Models/Values

Terminator Wizard

Getting Started with Crosstalk Spectrum Analyzer/Simulator

Enable Crosstalk


Board Wizard

Scope/Simulator Copyright © 2002 Mentor Graphics Corporation

Notes: The main toolbar allows access to commands, as well as a link to the HyperLynx web site. The pulldown menus on the main toolbar are accessed with the left mouse. They provide access to file commands, Help and Manuals, and other functions. Toolbar Items (left to right): File operations, Edit commands, View commands, Select commands, Crosstalk, Scope/Sim, Spectrum/Sim, Report generators, Wizards, Options, Help. Some of the pulldown menu items are also available as icons below the main toolbar. These provide shortcuts to commonly used features, including the Stackup Editor, the Scope Simulator and Spectrum Analyzer.


10-5


Icons (left to right): Layout Translator, Open BoardSim File, Open LineSim File, Open New LineSim File, Open File Editor, Edit Stackup, Zoom into Area, Return to Previous Zoom, Enable/Disable Crosstalk, Select Net, Select Component Models/Values, Add Quick Terminator, Open Oscilloscope/Simulator, Open Spectrum Analyzer/Simulator, Open Board Wizard, Open Terminator Wizard, Getting Started with Crosstalk, Help. NOTE: The BoardSim toolbar is different between Version 5.5 and Version 6.0. Selecting a command may cause a window to appear. Many of the toolbar icons and commands similar to what you saw in LineSim. This is true even if the underlying software is different. For example, the simulator in LineSim makes assumptions about the placement of transmission lines, while BoardSim is able to use the available layout information, but the scope User Interface appears the same. Notice how the commands are organized. For example, SPICE Writer, which creates a SPICE netlist, is located under File, since it generates a new file. The Help option brings up the complete list of Help files, Manuals and links, while the ? icon takes you directly to the main Help page.

10-6



The BoardSim Toolbar and Icons (Cont.) The BoardSim Toolbar and Icons (Cont.)



Notes: The File options are shown here. If you choose Open LineSim, Translate PCB, Open BoardSim, or Exit, the current BoardSim file will be closed, and a window will ask if you want to save changes. You must select Yes or No before BoardSim can release the file that is currently open. You can create a SPICE netlist for the currently selected net; if crosstalk is enabled, then the crosstalk aggressors will be included. You can set up your printer options. There are web links to both HyperLynx and EIA/IBIS web pages to help you quickly access the most up-to-date models from vendors, as well as HyperNews, our quarterly newsletter for users. There is also an option to generate


10-7


a model finder index, which updates the file HyperLynxIcModels.CSV to assist you in searching for models by keyword (such as vendor name).

10-8



Viewing the Layout Viewing the Layout ♦ View -> Options



Notes: When a BoardSim file is first opened, only the component outlines are displayed. This allows the entire board to be displayed quickly. The display default is to show the currently selected net; when you first load the board, no net is selected and no net is displayed. To view all of the nets, you can choose View from the main menu toolbar, then Options. If you choose All Nets, then every trace on the board is displayed. Each routing layer has a color, which can be assigned in the Stackup Editor, and these colors will be used when the nets are displayed.


10-9


View Commands View Commands ♦ ♦ ♦ ♦

Zoom commands Highlight Net Flip Board Options



Notes: The viewing options are located under View on the main toolbar. In addition to the usual Zoom commands, you can choose Highlight Net to highlight one or more nets, and Flip Board to reorient the view. Flipping the board is useful when you want to look from the back side, or if you want to rotate the board in the display. Panning is done using the scroll bars on the bottom and right hand sides of the schematic. Zooming a specified area of the schematic is done by choosing Zoom Area, and using the left mouse button to draw a box around the desired area. A rectangular box showing the area selected is displayed. When you release the left mouse button, the selected area becomes the new view. Choosing to Zoom Previous returns you to the previous view. Zoom Full displays the entire board. Zoom In

10-10



and Zoom Out scale the viewing area by a fixed scale factor, centered on the same center as the previous view. Zoom Point moves the center of the view to the point selected with the left mouse button. Under View options, you have access to the information displayed for each component. For example, you can specify whether or not Reference Designators are displayed. You can also set the display to show all nets, the current net, or the current net and its associated net. If crosstalk is turned on, nets crosstalk coupled with the currently selected net are automatically displayed. If All Nets is currently selected, it will be turned off when a net is selected.


10-11


Selecting Nets Selecting Nets



Notes: Selecting a net is done from a pick list of all nets. The list can be opened under Select (Net by Name or Net by Reference Designator), or from the Net icon. Once a net is selected, it is automatically displayed using the stackup layer colors. The list of nets can be sorted by signal name, length, or width. Sorting by name is used when you know the net name from a report file or other source. Sorting by length is used when you are looking for the longest nets in the design. Sorting by width is useful for locating nets of various widths, such as narrow traces in tightly routed areas of the board. Nets can also be selected by Reference Designator and pin name. This is useful for selecting adjacent nets on a package or nets that touch particular ICs.

10-12



If you are not sure of a signal's name, you can place the cursor over the net. The name will be displayed in the lower left corner of the BoardSim display area. If you have trouble, try zooming in to make the trace more pixels wide. This feature is particularly useful when you are viewing all nets, or when you need to know the name of an aggressor net.


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Highlighting Nets Highlighting Nets ♦ Select BoardSim menu View => Highlight Net



Notes: Highlighting a net supports ease of viewing. You can highlight a net by choosing Highlight Net under View on the main toolbar, selecting the net, and clicking on Apply. A dialog box allows you to set the color. You can highlight as many nets as you wish. The last net highlighted becomes the currently selected net. To remove all highlighting, click on Remove All. To remove highlighting for only one net, click on the net in the Highlight Net pick list, and remove highlighting by clicking on Remove Net Highlight on the Select Net Highlight Color menu. Note that highlighting a net is the same as selecting a net, except that highlighting is not removed when another net is selected. This means that aggressors will also be highlighted when you apply highlighting to a net. To avoid this, simply make sure Crosstalk is disabled before selecting a net for highlighting.

10-14



SPICE Writer SPICE Writer



Notes: SPICEWriter is found under File on the BoardSim menu. It is designed for users who wish to perform simulations in SPICE. The transmission line topology for the selected net is translated into SPICE format, along with the passive components, and a SPICE file is generated. If crosstalk is enabled, then any crosstalk coupled nets will also be included in the output file. The format for uncoupled transmission lines in compatible with SPICE 2G6. For coupled transmission lies, the format is compatible with HSPICE. SPICEWriter also creates a file to allow the generated subcircuit to be tested, _TEST.SP. This files does not represent any actual circuit, and is intended only for testing the generated subcircuit in your SPICE simulator.


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You can specify any file name. The default file extension is SP. Other extensions, such as SPI or CIR, are also permitted by SPICE. The SPICE netlist for a coupled transmission line is shown on the next page. Note that resistors (R*), transmission lines (T*) and coupling lines (W*) are all included in the file. No models or circuits are attached for the drivers and receivers. The format for the W components is based on HSPICE, and varies between SPICE products. HSPICE also uses two other files created by SPICEWriter: Cascade000.rlc and Cascade001.rlc.

10-16



Report Files Report Files ♦ Select the BoardSim menu ● ● ●

Reports => Net Statistics Reports => Board Statistics Reports => Design Change Summary (next page)



Notes: Report files can be automatically generated using the pulldown menu under Reports on the main toolbar. Most reports appear as windows, except for the Design Change Summary and batch mode reports, which are automatically saved as files. The Net Statistics Report display shows information about the total net length, segment impedances, and receiver capacitance; if crosstalk is enabled, the coupling information and a list of coupled nets is also reported. The Board Statistics Report gives the total number of nets, segments, pins, and vias. The Design Change Summary lists changes in added components (Quick Terminators) and passive component values. It does not report changes in stackup


10-17


or IC model assignments for pins. This is useful for documenting new components that must be added to the schematic and layout.

10-18



Report Files (Cont.) Report Files (Cont.)

CHANGED PASSIVE-COMPONENT VALUES ************************************* Reference Designator

User Entered Value

--------------------

-------------

R1 .................

0.0 ohms

R2 .................

75.0 ohms

NEW TERMINATING COMPONENTS (Quick Terminators) ************************************* Terminator Location Type

Value(s)

--------------------------U100, pin AF2 .............

Parallel RC ....R = 50.0 ohms \...C = 100.0 pF



Notes: The Design Change Summary is always saved as .TXT, so you should rename previous copies if you do not want them overwritten. Here are examples of the reports available under Reports on the main BoardSim toolbar. The Design Change Summary file appears as the same whether the design change report is generated interactively or in batch mode.


10-19


The HyperLynx General Purpose Editor The HyperLynx General Purpose Editor ♦ Document design changes ● ● ●

Model changes Stackup changes Termination changes



Notes: The HyperLynx General Purpose File Editor can be used for editing text files. In BoardSim, you may want to create files to document model changes and stackup changes. You can also open previously created report files. IBIS models also can be edited manually using this editor. This editor is also available from the main HyperLynx product menu and form LineSim. Note that this editor does not support the Microsoft keyboard shortcuts, such as ^c and ^v.

10-20



Help Files and Manuals Help Files and Manuals ♦ ♦ ♦ ♦ ♦ ♦

Help & Manuals ship on CD In the install directory (c:\HyperLynx) Context sensitive Help Hot links to related Help topics Manuals in PDF format Tutorial text and files



Notes: Help is invoked by clicking on the Help option on the main toolbar or the question mark icon. There are also links to the HyperLynx web site, under File and Help. One of the links takes you directly to the HyperLynx web page that links you to vendors' IBIS models. Help is presented using a window. It includes hot links, where left clicking takes you to a related topic. If you click on any LineSim window Help box, Help will open the related topic page. Both Help and the Manuals are also available from outside the software. The Help and Manual files are found in the install directory (normally C:\HyperLynx), and have extensions of HLP and PDF respectively. They can be opened by


10-21


double-clicking on the file name. (Opening the Manuals requires Adobe's Acrobat Reader.) The tutorial is a quick way to review the features and operation of LineSim and BoardSim. The tutorial can be accessed from the Start menu, or by selecting Demo.exe in the install directory.

10-22




Using the BoardSim User Interface



Notes:


10-23


10-24


Module 11 Running BoardSim


11-1

Running BoardSim

Running BoardSim Running BoardSim ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

Setting Up Your Layout Setting Up BoardSim Opening and Closing BoardSim Files Stackup Editing Assigning Models Running Board Wizard (Batch Mode) Setting Up Crosstalk Running Scope/Sim Running EMC Spectrum Analysis Terminator Wizard Quick Terminators

11-1 • HyperLynx Signal Integrity Analysis: Running BoardSim


Notes:

11-2


Running BoardSim

Setting Up Your Layout Setting Up Your Layout ♦ PowerPCB as an example



Notes: The HyperLynx translators support importing many types of data from your layout package. Depending on the layout package, you may be able to import component values, IC model assignments, and stackup information, as well as the actual physical trace data. To bring this information into BoardSim, attributes must be assigned in the layout. For PADS Software layout (PowerPCB), the stackup data can be entered using Layer Stackup under SETUP on the PowerPCB toolbar. Component values must be assigned to the VALUE attribute for the component. To assign a model to an IC, the file name is assigned to the HyperLynx.Model


11-3

Running BoardSim

File attribute, and the component name within that file to the HyperLynx.Model attribute. Once the layout is ready for translation, the PowerPCB file can be translated using the BoardSim option under Tools on the PowerPCB toolbar. This automatically translates the layout to the BoardSim HYP format, and generates the REF file for the ICs. The process is similar in principle for other layout software packages, but will vary with the tool features and user interfaces. Not all layout packages support stackup entry or all attributes. Unsupported data can later be entered into BoardSim interactively.

11-4


Running BoardSim

Translation GUI Translation GUI



Notes: Once BoardSim has been installed, you are ready to use to import a layout and run analysis. BoardSim files can be generated from over 15 different layout packages, as well as from the standard DSN format. Some layout packages, including PADS PowerPCB, have translators included. Because each layout package is different, each translator is also unique. There are various options available, depending on the layout package and translator. For example, when translating a PADS' PowerPCB layout, you can choose whether to include translation of unrouted nets. To begin translation, choose Translate PCB to .HYP File under File on the main toolbar, or select the Translate PCB icon. (From inside PADS' PowerPCB, you can choose BoardSim under Tools on the main menu bar.) Then follow the steps for your translator. Since new features are added to layout packages by their


11-5

Running BoardSim

respective vendors, you may require an updated translator; these are available from HyperLynx Technical Support. Older layout packages are supported, so you still assured use HyperLynx software with layouts for mature products as well as your newest designs. The translation process uses files created by your layout package. Please refer to the Manual or Help file for your specific translator to find out which files are required. Note that, in some layout systems, these files may not be saved by default. Write access is required to the directory containing these files during translation; in some cases, you may need to temporarily copy the required files to a local directory to provide write access. Note that the translation for PADS PowerPCB files is done inside PowerPCB, and there is no external translator required. Additional information can be found in the PCB Translators Users Guide.

11-6


Running BoardSim

Translation PCB Files to Hyperlynx Translation PCB Files to Hyperlynx



Notes:


11-7

Running BoardSim

Setting Up BoardSim Setting Up BoardSim



Notes: Options allows you to set preferences that are common to multiple sessions. The General tab options include MOD model best/worst case scaling factors, fabrication compensation values, and simulation temperature.

11-8


Running BoardSim

Setting Up BoardSim (Cont.) Setting Up BoardSim (Cont.)



Notes: The BoardSim tab provides options to set defaults for vias, net handling, and the Board Wizard default rise/fall time. The default stackup layer values are set under the Default Stackup tab. The options menu allows you to select units (English/metric, thickness/weight), set background color for the display window, set preferences for simulation, and check/add licenses. Options settings are saved in the install directory (usually C:\HyperLynx) in Bsw.ini.


11-9

Running BoardSim

Setting Up BoardSim (Cont.) Setting Up BoardSim (Cont.)



Notes: You can also set the directory path for your model library by choosing Directories under Options. The default path is the install directory. Note that there is only one allowed path; however, you may use a different path for each project as long as all required model files are available under that path. The Libs directory must be located in the model library path, as well as the files Bsw.fbd (ferrite bead models) and Bsw.pak (resistor pack models). The default path for searching for BoardSim files is the last opened directory used by BoardSim. This can be set to a fixed path in the Set Directories window.

11-10


Running BoardSim

Opening and Closing BoardSim Files Opening and Closing BoardSim Files ♦ ♦ ♦ ♦ ♦

Opens files *.hyp Reads *.REF Read User Preferences (Bsw.ini & *.PJH) Reads *.BUD, *.PJH Writes *.BUD, *.BBD, *.PJH



Notes: A BoardSim layout file is named *.HYP, and is a text (ASCII) file. It is possible to edit a HYP file manually or using a text processing script, although most people use only the GUI. There may also be a *.REF file, which contains the mapping of ICs to model files. Existing BoardSim HYP files can be opened using the pulldown menus under File on the main toolbar. Existing files can also be opened using the BoardSim icon. You can also open an existing BoardSim file by double-clicking on the filename in a file list (such as Windows Explorer). The Open BoardSim file window includes browser features such as checking Favorites, or moving up and down the directory tree.


11-11

Running BoardSim

A BoardSim file can be saved using Save from the pulldown menus under File on the main toolbar. When you save a BoardSim session, .BBD, .BUD, and .PJH files are written, saving your design changes. Options settings are saved in Bsw.ini in the install directory (usually C:\HyperLynx). The BUD (BoardSim User Data) session file contains your interactive edits (model and value updates, stackup changes, power supply settings, simulation temperature, etc.). The BBD (Backup Session file) is a copy of the previous BUD file (if any) for the design. The PJH (Project) file contains design-specific preferences, such as Crosstalk Threshold and Batch settings. The file Bsw.ini contains general preferences, such as reference designator mappings, that are set under Options. Note that the BUD and PJH files override the BBD file, which in turn overrides the Bsw.ini values. A BoardSim file can be closed by clicking the "X" in the upper right corner of the BoardSim window, or by choosing Close from under File on the main toolbar. If you close a BoardSim file without previously saving it, you will be asked if you want to save changes. Saving changes will write out .BUD, and .BBD, and .PJH files.

11-12


Running BoardSim

Stackup Editing Stackup Editing



Notes: The Stackup Wizard, under Wizards on the main toolbar, can be used to check your stackup. The Stackup Wizard will try to clean up any problems that it finds. Since not all layout packages support complete stackup information, it is always a good idea to use the Stackup Wizard and the Stackup Editor to check your stackup. The Stackup Editor is available under Edit/Stackup on the main toolbar or as an icon. If the layout tool or translator does not provide full support for stackup translation, the Stackup Editor can be used to correct any problems in the imported stackup. It can also be used to modify the stackup to improve signal integrity.


11-13

Running BoardSim

In BoardSim, the Stackup Editor can be used to reorder the signal layers (such as moving the TOP layer to an inner layer). It is not possible to move individual trace segments to new layers; that must be done in your layout tool. Layer colors, thicknesses, and other properties can be assigned, and dielectric properties and metal conductivities change. When you make changes, impedances are calculated using the default trace width for each signal layer, and displayed in the Stackup Editor window.

11-14


Running BoardSim

Assignment of Models and Values Assignment of Models and Values ♦ Read Reference Designator Mapping ♦ Read *.Ref file ♦ Read Board User Data (BUD) file



Notes: Models should be assigned to ICs and ferrites, and values should be assigned for all passive components. Quick Analysis can be done in Board Wizard using the Default IC Model. Detailed simulations, on the other hand, treat unassigned models as open circuits. All models are read from the specified library path, and all models used must be in that path. The default directory is c:\HyperLynx\Libs. The FBD and PAK models remain in the install directory (normally c:\HyperLynx). Routing segments (transmission lines) cannot be edited directly, except for changing width (which does not change the spacing to nearby traces). Layer assignments can be changed only by changing layer order in the stackup. All


11-15

Running BoardSim

other editing of traces must be done in the layout tool, and the board imported back into BoardSim. Vias are modeled based on the Options settings and the net's driver edge rate. A via is modeled as a capacitor or as a transmission line, depending on the via size and the signal edge rate, except when there are components connected to the via on both sides of the board, in which case it is always modeled as a transmission line. To assign a model to an individual pin or passive component, select the net to which it is attached. Then, from the main toolbar, choose Component Models under Select., or click on the Select Components icon This opens the Assign Models window. In BoardSim, all pins (ICs, resistors, capacitors, beads, inductors) for the selected net are displayed, and you can change the value for any component in this picklist.

11-16


Running BoardSim

Assignment of Models and Values (Cont.) Assignment of Models and Values (Cont.) ♦ *.Ref file U4,GENERIC.MOD,CMOS,5V,FAST U11,74HC.PML,74HC192_SOIC U7,CYFC16SD.IBS,CY74FCT16244

♦ Read when board is loaded ♦ Can be automatically generated (PowerPCB) ♦ Can be edited manually



Notes: To assign a model to a pin, you must first select the net. To open the model selection window, choose Select, then Component Models/Values. The Assign Models window opens. Note that both IC pins and passive components (R, L, C, Ferrites) appear in the window. The settings for the currently selected model are displayed, including its power supply and ground return pins for a driver. The Vcc and ground pin return pins can be updated here. In the Assign Models window, pins and components may be selected either by clicking on a specific component, or by clicking on the tab for the type (such as


11-17

Running BoardSim

resistor). When you select a type, the first component of that type is selected from the list. An IBIS or PML model for an entire IC can be assigned using a REF file; an MOD model can be assigned to every pin of an IC. The REF file is a list, one line per component, of IC reference designators and the model file and component name in the model file to be used for that component. The REF file is read when a board is loaded into BoardSim; interactively assigned models will override the information loaded in from the REF file. The REF file can be created and edited using IC Automapping (REF) under Edit, or it can be created using any word editor; the file name must be .REF. In some layout software tools, such as PowerPCB, the REF file is automatically generated from the attributes on the IC components. Here is a *.REF file example.

11-18


Running BoardSim

Assignment of Models and Values (Cont.) Assignment of Models and Values (Cont.) ♦ Reference Designator Mapping ♦ Options -> Reference Designator Mappings ♦ Read when board is loaded

LED = IC L = inductor



Notes: The reference designator mapping is used when loading a BoardSim HYP file to assign part types to each component on the board. This reference designator mapping can be edited by choosing Reference Designator Mappings under Options. The Reference Designator Mapping is read while the HYP file is bring loaded into BoardSim. If you make changes to this file, they will not be used until the board is reloaded.


11-19

Running BoardSim

The default reference designator mapping assigns R* to resistors, C* to capacitors, and U* to ICs, among others. The mapping uses the first matching designator in the list to map a component when a board is read in, so LED is mapped to IC (diode models), while L is mapped to inductors.

11-20


Running BoardSim

Assignment of Models and Values (Cont.) Assignment of Models and Values (Cont.)



Notes: When the layout is opened in BoardSim, the model information from the REF file is automatically loaded. Once the board has been loaded, you can set the model for individual pins; these will override the earlier model assignments. This is often needed for FPGAs, where buffer types may be changed based on the loading in the routed layout. If you need to assign a model to a pin, you must make sure that the model is valid for that IC in that package, and that the change is documented. This information is available in the .BUD file, but it is not written to the Design Change Summary.


11-21

Running BoardSim

To interactively assign a model to a pin, you must first select the net. To open the model selection window, choose Select, then Component Models/Values. The Assign Models window opens. Note that both IC pins and passive components (R, L, C, Ferrites) appear in the window. The settings for the currently selected model are displayed, including its power supply and ground return pins for a driver. The Vcc and ground pin return pins can be updated here. In the Assign Models window, pins and components may be selected either by clicking on a specific component, or by clicking on the tab for the type (such as resistor). When you select a type, the first component of that type is selected from the list. In the Assign Models window, pins and components may be selected either by clicking on a specific component, or by clicking on the tab for the type (such as resistor). When you select a type, the first component of that type is selected from the list. If you find the number of pins to be too large, turn off crosstalk. The crosstalk coupled pins (indicated by red lines between green bars) will be removed from the list.

11-22


Running BoardSim




Notes: Under File, there is an option to generate a model finder index, which updates HyperLynxIcModels.CSV in the HyperLynx install directory. The Find Model option on the Select IC Model window then allows you to locate models using keyword searches into this file.


11-23

Running BoardSim




Notes: An IC buffer model may be an input, output, or bi-directional I/O. Once you have selected a model, you can select from the I/O options by left clicking the appropriate radio button in the Buffer Settings area of the Assign Models window.

11-24


Running BoardSim




Notes: Similarly, values can be changed for passive components; this is necessary if the values do not come over during translation of the layout. To change a value for a passive component (R, L, C), select that component from the list of components in the Assign Models list, or select the tab for that type of component. Quick Terminators can be also be assigned and their values changed in the Assign Models. Assigning existing terminators ideal values can be used to effectively remove them from affecting the circuit while you are testing new terminations. Example values to use for "removing" a real terminator: resistors of 1000 ohms or more,


11-25

Running BoardSim

capacitors of 0 pF, and series resistors of 0 ohms. Parasitics on passive components cannot be set within BoardSim. Ferrite bead models are assigned using the Assign Models window. New models can be created for ferrites and added to the library in User.fbd by specifying the series resistance and three frequency points. The frequency curve in the Select Ferrite Bead Model window shows the frequency characteristics of the highlighted model. Once models have been assigned, close the window by clicking OK or the "X" in the upper right corner of the window. Note that there is no option to "Cancel" model assignment; instead, models must be individually reset manually. If none of the IC pins is a driver, a warning message is displayed when you close the window. You will usually want each net in a simulation to have one output pin (driver) before simulating.

11-26


Running BoardSim

Assignment of Models and Values (Cont.) Assignment of Models and Values (Cont.) ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

IBIS (*.ibs) Generic.MOD Easy.MOD * PML Probes.MOD Bsw.PAK Bsw.FBD Diodes.MOD User.MOD Open.MOD Custom library path



Notes: IBIS (*.ibs): An IBIS model file may provide several buffer models, with different functionality (in/out/bi-di, PCI, AGP, etc.). Usually, both Device and Pin must be selected to fully specify your model selection. Generic.mod: The file contains generic components for several logic families in a variety of edge rates. Easy.mod: A set of generic technology models, used for evaluating effects of edge rates, package parasitics, and driver output impedance.


11-27

Running BoardSim

PML: These files contain typical models for packaged parts, including package parasitics for typical packages. Probes.mod: The file contains models for typical input probes for oscilloscopes. Bsw.pak: This file, located in the main HyperLynx directory, contains models for resistor and RC packs. Bsw.fbd: This file, located in the main HyperLynx directory, contains models for ferrite beads and EMC filters. Diodes.mod: This file contains basic diode models. User.mod: This file is set up for models you create using the HyperLynx proprietary .MOD format, and put them here. Open.mod: This file contains models for "open" IC pins with package parasitics. Custom library path: If you specify a new directory path for your library, you should retain the same file extensions as are used in the HyperLynx/Libs directory.

11-28


Running BoardSim




Notes: It is often useful to automatically identify nets at risk of signal integrity problems as soon as the layout is received. You can scan your entire board in one run using the Board Wizard, available under Wizards on the main toolbar or by clicking on the Board Wizard icon. The Board Wizard window features two sections: the top set of options runs detailed simulations, and the lower set of options runs Quick Analysis. Only those options that are selected on the Board Wizard's menu are run. Since Quick Analysis runs much faster than detailed simulations, it is the first thing run on a newly imported layout, checking for "hot spots" or high-risk areas for signal integrity and crosstalk. Once nets at high risk have been identified, detailed simulations can be run on just those nets to quantify the


11-29

Running BoardSim

problem. Later, you can run interactive simulations on your risky nets to evaluate tradeoffs among solutions, such as termination changes. All of the Batch analysis results are saved in a text (ASCII) file. The default file name is .RPT; you can change the name on the last menu of the Board Wizard (that has the Finish box). Simulation data is not saved, but the analysis comparing the simulation results against the user-set limits is reported in the report file. For a board with many thousands of nets, depending on the options selected, simulation and analysis can take hours or even days. Batch mode is designed to run without user interaction once the Finish box has been clicked on the last Board Wizard menu. For detailed signal integrity simulations, you can specify the maximum time spent per net; this prevents simulations from "hanging" on one net, so simulation can be completed for the remaining nets. Quick Analysis can be used to quickly scan the entire board for nets at risk. Quick Analysis performs checks on every net on the entire circuit board. For crosstalk, every net is checked against every other net. Net Statistics, stackup information, and the component change summary report information can be also generated using Quick Analysis options. No detailed simulations are run during Quick Analysis. Instead, expert system algorithms are used to predict the risk for signal integrity and crosstalk. Using the Board Wizard for Batch Mode analysis is covered in more detail in a later chapter. The Quick Analysis options are covered in more detail in the next chapter.

11-30


Running BoardSim

Board Wizard: Batch Mode Board Wizard: Batch Mode



Notes: Once you have used Quick Analysis to identify the high-risk nets, you can run detailed simulations on selected nets. You may choose to run signal integrity and/or EMC simulations. Because detailed simulations take more time per net than Quick analysis, you will probably want to simulate only selected nets. For both signal integrity and EMC simulation, there are Nets Spreadsheets for specifying which nets to simulate. The signal integrity simulation menu has several options. You can decide which IC models (Fast/Typ/Slow) you want to use (Monte Carlo functionality). You can decide whether or not to include crosstalk aggressors during signal integrity simulation (Signal Integrity simulations include crosstalk effects only if you select


11-31

Running BoardSim

"Run at high accuracy by including coupled neighbor nets in simulation"); including aggressors improves accuracy but slows simulation. Finally, you can run crosstalk simulations with the victim stuck high or stuck low. The more options selected, the longer the batch simulation will take. The more nets that are selected from the Nets Spreadsheet (lower right corner), the longer simulation will take. If you selected SI simulation, you must select at least one net in the SI Nets Spreadsheet; In the Nets Spreadsheet, when a net is selected, its electrically associated net is also selected. The nets to be simulated must be specified on the Nets Spreadsheet. At least one net in the Nets Spreadsheet must be selected if you have selected Signal Integrity simulation. When a net is selected, its electrically associated net is automatically selected and assigned the same limits for checking rising/falling overshoots, delays, and crosstalk. (Undershoot is not checked.) In this example, selecting net CLK2 automatically selects net $$$4 with the same limits. Setting the minimum delay less that zero means that delays on this net will always meet this minimum requirement; setting the maximum delay very high means that delays on this net will always meet this maximum requirement. The Nets Spreadsheet should be closed using Close under File; this saves any changes.

11-32


Running BoardSim

Board Wizard: Batch Mode (Cont.) Board Wizard: Batch Mode (Cont.)



Notes: Batch mode EMC simulation has the same options for setting the antenna location as is used in interactive analysis. In addition, the which IC model (Fast/Typ/Slow) you want to use; note that only one can be selected. You can select one or more EMC regulatory limits to check; all nets will be checked to the same specifications. When a net's EMI emissions exceed the specified regulatory limits, the net name and the regulation (FCC/CISPR/VCCI/USER) is reported in the report file for the first frequency that exceeds the regulatory limit. The Nets Spreadsheet is opened by clicking the Nets Spreadsheet icon on the EMC window. If you selected EMC simulation, you must select at least one net in the EMC Nets Spreadsheet. In the Nets Spreadsheet, when a net is selected, its electrically associated net is automatically selected. The frequency (repetition


11-33

Running BoardSim

rate) and Duty Cycle can be set independently for each net. The Nets Spreadsheets for EMC and for Signal Integrity simulations are independent. Note that the Default IC Model is not used for any detailed batch simulations, except to identify aggressor nets if the related options are enabled. To make sure all pins have assigned models before simulating, you should either assign every IC a model in the REF file or make assignments interactively. Both interactive and batch simulations use the assigned driver/receiver settings that are presently stored in the simulation database.

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Running BoardSim

Setting Up Crosstalk Options Setting Up Crosstalk Options



Notes: Simulation can be performed with or without crosstalk aggressors. To enable crosstalk, and have aggressors automatically identified and highlighted in the layout window, select Enable Crosstalk from the main toolbar or click on the crosstalk icon. Note that the icon acts as a toggle, and is light gray when crosstalk is enabled. When Crosstalk is enabled, the expert system algorithm used for Quick Analysis for Crosstalk identifies all crosstalk coupled pairs of nets on the entire board. These nets are displayed as dashed lines, while the selected net remains displayed as a solid line.


11-35

Running BoardSim

Setting Up Crosstalk Options (Cont.) Setting Up Crosstalk Options (Cont.)



Notes: Nets are selected if their crosstalk coupling voltage (peak to peak) exceeds the crosstalk threshold voltage, and are rejected if it is below the threshold. The Crosstalk Threshold menu is under Crosstalk on the main toolbar for interactive analysis, and is a menu page for batch mode. Separate threshold voltages can be used for batch mode and interactive analysis. To have the same aggressors identified, it is necessary to have the same crosstalk threshold. If you set the crosstalk threshold high, you will pick up only the strongest aggressors; these are the most important crosstalk problems to fix. Setting a low crosstalk threshold will increase the number of aggressors and increase the simulation time, but may not significantly increase the total crosstalk on the victim net.

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Running BoardSim

Geometric Thresholds remain available. However, using geometric thresholds raises a risk of missing an aggressor with a fast edge rate that is geometrically far from the victim net. Default IC models are used to identify crosstalk coupled nets even when no driver model has been assigned to a net. If a driver model has been assigned, then it will override the default model. Separate default IC models can be used for batch mode and interactive analysis. To have the same aggressors identified, it is necessary to have the same default IC models. The Default IC Model settings menu is reached by clicking on Change Default IC Model in the Set Crosstalk Thresholds window for interactive analysis, and is a menu page for batch mode. The default should be set to the fastest edge rate on your board, with corresponding minimum package parasitics. Because the Default model is used only to identify aggressor nets, you still need to assign actual driver models to those nets before simulating. The Default IC Model is not used for any detailed simulations. To make sure all pins have assigned models before simulating in batch mode or interactive mode, you should either assign every IC a model in the REF file or make assignments interactively. Both interactive and batch simulations use the assigned driver/receiver settings that are presently stored in the simulation database.


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Running BoardSim

Setting Up Crosstalk Options (Cont.) Setting Up Crosstalk Options (Cont.) ♦ Crosstalk =>Walk Coupling Regions (Field Solver Views)



Notes: Coupling regions can be viewed by choosing Walk Coupling Regions, under Crosstalk on the main toolbar. Each group of segments that contributes to the estimated crosstalk is displayed as you scroll using the Next and Back buttons. When a group of coupled segments is displayed, there is a choice of views for those segments: Nets (net names, layers, widths, spacings, coupling length), Cross-section, and Impedance (impedance matrices and ideal terminations). From the view shown here, coupling between offset traces can be seen.

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Running BoardSim

Setting Up Crosstalk Options (Cont.) Setting Up Crosstalk Options (Cont.)



Notes: When crosstalk is enabled, interactive Signal Integrity and EMC simulations will include coupling both from the aggressors to the victim and from the victim to the aggressors. In batch mode, Signal Integrity includes crosstalk coupling only if you select "Run at high accuracy by including coupled neighbor nets in simulation". To observe the crosstalk coupled voltage, the victim net should be set to Stuck Low or Stuck High. This puts the driver in a low impedance state. The aggressors should all be set to the same state, either Output or Output Inverted. The probes should be set on the receivers of the victim net. Simulation will then show the crosstalk amplitude at each receiver. Other combinations of aggressor switching directions can be tried to determine which is worst case for this victim.


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Running BoardSim

To observe the effects of crosstalk coupling on timing, the victim net should be set to Osc, making it easier to observe both rising and falling edges. The aggressors should all be set to the same state, either Output or Output Inverted. The probes should be set on the receivers of the victim net. Simulation will then show the pin-to-pin delay at each receiver. Other combinations of aggressor switching directions can be tried to determine which is worst case for timing on this victim.

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Running BoardSim

Running Interactive Scope/Sim (Cont.) Running Interactive Scope/Sim (Cont.)



Notes: The interactive Scope/Sim simulator is used to analyze the signal integrity and crosstalk performance of signals on your board. Each net is simulated using transmission line information generated by the field solver. Whereas LineSim had to make assumptions about where line segments were located, the routing information is now available and all routing segment locations and orientations are known. There are two ways to open Scope/Sim: you may select Scope/Sim from the main toolbar, or you can click on the Scope/Sim icon. Simulation can be run with Crosstalk enabled or disabled. When Crosstalk is enabled and aggressor nets are shown in the layout window, simulations can take longer to run. In general, the more aggressors that are selected, the longer the simulation takes. For this reason, you can set the maximum number of aggressors


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Running BoardSim

to keep in Preferences for BoardSim, under Options on the main toolbar. Typically, termination and signal integrity are first checked with crosstalk disabled. Then crosstalk is enabled, and signal integrity and timing are checked. Probes should be before running a simulation. The Probes window is accessible from the main toolbar, or by selecting Probes on the Scope window. Probes can be set on any component pin. All available probe points are shown in the Probes window. If no probes are selected, or if you use Attach All, the simulator will automatically assign the first six IC pins. Note that simulation results are saved only for the probes. If you change probes, you must rerun the simulation to see the results for the new probes. And the probes that are no longer selected are no longer saved during for this next simulation.

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Running BoardSim

Running Interactive Scope/Sim (Cont.) Running Interactive Scope/Sim (Cont.)



Notes: Once the probes have been selected, you can set the simulator input and display settings. The settings are:

• Driver Waveform: Rising Edge, Falling Edge, Osc. Osc (for observing both edges at once) has additional settings frequency and duty cycle.

• IC Modeling: Slow-Weak, Typical, or Fast-Strong IC driver(s). Selects

the appropriate the IBIS or MOD model data. Accounts for IC process and package variations.

• Show Readout: Overlay scale information on top section of display area.


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Running BoardSim

• Show Previous: Show results of previous simulation. • Show Buffer: Show results of simulation from display buffer. • Vertical scale and offset: Scope display for the voltage waveform, and

vertical offset of the DC ground (green line). Click right or left markers to increase or decrease the scale. Move slider to change the offset.

• Horizontal scale: Scope display for the timebase for the waveform. Click right or left markers to increase or decrease the timebase.

• Copy to Buffer: Saves current waveform to the waveform display buffer. You can display up to three waveforms (current, previous, and buffer).

• Copy to Clip: Copies display to Microsoft-compatible clipboard. Use for pasting results into a document (such as Word or PowerPoint).

• Save as CSV: Save simulation results as comma separated values. Use for pasting results into a spreadsheet.

• Erase: Clear the screen of waveforms. • Print: Send to a printer.

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Running BoardSim

Running EMC Spectrum Analysis Running EMC Spectrum Analysis



Notes: The EMC simulator (Spectrum/Sim) is used to evaluate EMC performance of one routed net on your board. If Crosstalk is enabled and aggressor nets are displayed, they will all be included in the simulation. This can be used to evaluate the effects of guard traces and other nearby nets. Where LineSim had to make assumptions about where line segments were located, all of the routing information is now available and all routing segment locations and orientations are known. This means the EMI for each trace segment can be calculated, and the total for that net can be determined. A total for the entire board can not be calculated, since the driver transition times (relative to each other) are usually not known in sufficient detail, and can vary from one clock cycle to another.


11-45

Running BoardSim

There are two ways to open the Spectrum Analyzer: you may select the Spectrum Analyzer from the main toolbar, or you can click on the Spectrum Analyzer icon. Both open the Spectrum Analyzer window. (From the main toolbar, there is also an option to open the Probes window, which is also accessible by selecting Setting in the Probes section of the Spectrum Analyzer window.) Probe settings can be made by choosing Probes under Spectrum/Sim, or by clicking on Settings in the Spectrum Analyzer window. You must set your probes before running a simulation. The default is an antenna probe three meters from the board, much like the probes used in FCC testing. The settings associated with the antenna probe allow you set the antenna distance. You can examine emissions at a single antenna location and polarity, or sweep to find the maximum radiation location. A current probe is also available; this can be set on any IC pin or any pin of a twoterminal component (such as a resistor). All available current probe points are shown in the Probes window when Current Probe is selected.

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Running BoardSim

Running EMC Spectrum Analysis (Cont.) Running EMC Spectrum Analysis (Cont.)



Notes: Once the probes have been selected, you can set the simulator input and display settings. The settings are:

• Driver Waveform: Frequency and Duty Cycle. Normally, a duty cycle

slightly different from 50% is used to allow both even and odd harmonics to appear in the results.

• IC Modeling: Slow-Weak, Typical, or Fast-Strong IC driver(s). Selects

from the appropriate column of the IBIS or MOD model data tables. Accounts for IC process variation, power supply variation, and temperature variation??


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Running BoardSim

• Show New / Show Previous: Select which simulation results you want

displayed. Useful for evaluating a proposed design change. These buttons are located under the display area.

• Regulations: Selected regulation limits are shown in the display area, as an

overlay to the simulated emissions spectrum. Edit User allows you to enter limits of your own.

• Vertical offset: RMS values are displayed in dB uV/m (20 log E-field). Click right or left markers to increase or decrease the offset.

• Center Freq and MHz/div (Scale): Sets the frequency base for the

horizontal display. Type in the center frequency. Click right or left markers to increase or decrease the scale factor.

• Erase: Clear the display of waveforms. • Print: Make hardcopy on a printer. • Copy to Clip: Copies display to Microsoft-compatible clipboard. Use for pasting results into a document (such as Word or PowerPoint).

• Save as CSV: Save simulation results as comma separated values. Use for pasting results into a spreadsheet.

• View Points: Display the simulation results as a text file. Useful for checking numeric values.

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Running BoardSim

Terminator Wizard Terminator Wizard



Notes: The Terminator Wizard can be used to calculate component values for terminations. There are two ways to open the Terminator Wizard: you may select the Terminator Wizard from the main toolbar under Wizards, or you can click on the Terminator Wizard icon. Both open the Terminator Wizard window. The Terminator Wizard performs several functions:

• Calculating the driver impedance and the transmission line input impedance • Suggesting a termination style when termination is missing, or when there is more than one termination type


11-49

Running BoardSim

• Calculating values for the selected termination style • Looking up standard values for a given tolerance • Applying the values to the components in the layout The warnings in the text box provide messages indicating what solutions can be applied. In the example above, the resistor is identified as Zero ohms. Other common warnings include wide driver impedance variation, and long termination stubs. To assign the calculated values, click Apply Values. If you close the window without applying the values, the layout is not updated. If there is no termination component on the net, the Apply Values button is grayed out. If there is no termination on the net, you can add a Quick Terminator and rerun the Terminator Wizard. The Terminator Wizard cannot handle some termination combinations of terminations on the same net, such as a series resistor at each end. In this case, you can use the information provided in the Terminator window as an aid in calculating the values manually.

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Running BoardSim

Quick Terminators Quick Terminators



Notes: Sometimes you discover that a net lacks terminations and consequently does not have good signal integrity. The board has been completely laid out, but you still need to add a termination. Quick Terminators are used for "what-if" analysis, allowing you to add these virtual components to your board for simulation and analysis. Quick Termination components are reported when the Design Change Summary is generated. A Quick Terminator is added by selecting the net, and then clicking on the Quick Terminator icon; this opens the Assign Models window with the Quick Terminator tab selected. The window displays a list of all pins available on the selected net, as well as the crosstalk coupled nets if crosstalk is enabled. There is a pick list of termination types. Click on the pin where you want the terminator,


11-51

Running BoardSim

and then on the terminator style. The termination is now in the board for simulation purposes. There are five terminator styles supported for Quick Terminators. Quick Termination may be applied one or more pins on a net. When a Quick Terminator is present, the IC pin symbol shows a gray "resistor" symbol in the Assign Models box. When that pin is selected, the schematic for the termination and the component values are shown whenever you choose the Quick Terminator tab. To remove a Quick Terminator, select None for the Terminator style. To set the value of the new termination you can type in the value in Assign Models, or run the Terminator Wizard. If there is more than one termination on the net, the Terminator Wizard allows you to choose which one to optimize. For the series resistor, you can also define the stub routing from the IC pin to the resistor pin. The Quick Terminators can be added using the tab in the Assign Models window, or by left clicking on the Quick Terminators icon. In the Quick Terminator window, specify the IC pin, the termination type, and the component values. Note that component values can later be optimized using the Terminator Wizard, so it is acceptable to use the default component values when adding Quick Terminator components.

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Running BoardSim


Assigning Models in BoardSim Running in BoardSim Running with Crosstalk Enabled



Notes:


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Running BoardSim

11-54


Module 12 Quick Analysis in BoardSim


12-1

Quick Analysis in BoardSim

Quick Analysis in BoardSim Quick Analysis in BoardSim ♦ ♦ ♦ ♦ ♦

Quick Analysis in the Design Cycle Early Identification of Risk Areas Quick Analysis Option Back Annotation The Final Check

12-1 • HyperLynx Signal Integrity Analysis: Quick Analysis in BoardSim


Notes:

12-2



Quick Analysis in the Design Cycle Quick Analysis in the Design Cycle ♦ ♦ ♦ ♦ ♦ ♦

Early identification of "hot spots” for risk Signal integrity and crosstalk problems Report generation Final checks before building the first prototype Expert algorithms No detailed simulation



Notes: Quick Analysis has three main uses:

• Early identification of "hot spots" or nets at high risk for signal integrity and crosstalk problems

• Report generation • Final checks or analysis before building the first prototype Each Quick Analysis option generates a section that is placed in the report file. The file name defaults to .RPT, but you can specify a different name for this text file.


12-3


Since Quick Analysis is part of the Board Wizard and operates in batch mode, you can set up all of the menus, and then go get a quick cup of coffee. For small boards (a few hundred nets), batch analysis can take less than a minute. For larger boards, it make take several minutes, depending on the number of nets and the number of options selected. Quick Analysis runs quickly because no detailed simulations are done. The expert algorithms that are used take into account transmission line field effects (impedance and coupling), as well as driver edge rates and stackup. Without detailed simulation, the magnitude of the risk can only be estimated. You will find that risks tend to be somewhat overestimated during Quick Analysis. This provides a conservative risk assessment, since it is preferred to include a net that might not have a problem than to leave one out that needs to be fixed. On the other hand, the estimates are usually not overly conservative, so that the nets needing work on are not buried in a large set of low-risk nets. To find the actual magnitude of the problem, whether signal integrity overshoot, delay, or crosstalk, you must run a detailed simulation. Because Quick Analysis runs much faster than simulation, it provides an efficient way to identify those nets which require detailed simulations.

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Early Identification of Risk Areas Early Identification of Risk Areas



Notes: The BoardSim Quick Analysis allows you to quickly assess the "hot spots" or high-risk nets on your board for signal integrity and crosstalk. This can be done as soon as placement is complete and critical nets have been routed. Once the initial routing is complete, Quick Analysis allows you to scan the entire board to look for risk. You may not know which nets have the highest crosstalk, or the longest unterminated lengths, when a layout is done. Even though constraints have been specified, the layout designer may have been forced to make tradeoffs that violate the constraints in order to meet manufacturing requirements. For example, nets may be routed closer together or placed on different layers than specified in the design constraints, to keep the total number of layers few and the production cost low.


12-5


Early Identification of Risk Areas (Cont.) Early Identification of Risk Areas (Cont.) ♦ Identify highest risk areas ♦ Focus design efforts on those spots ♦ Catch nets overlooked during a manual check ● ●

Edge rate vs. switching rate Missing terminations

♦ Example: Crosstalk coupling ● ● ●

Set crosstalk threshold high at first Catch (and fix) the worst crosstalk coupled nets Tighten crosstalk threshold



Notes: Early identification of risk provides two benefits. First, the highest risk areas are clearly identified, allowing you to focus your efforts on areas which provide the most improvement for your efforts. Second, high risk areas are identified that might have been overlooked during a manual check. For example, a manual check may lead you to think that a 1 MHz net will not require termination; Quick Analysis might see that with an edge rate under 2 nsec, termination is required, even though the repetition rate is low. Initially, you will probably want to see only the highest-risk nets. For example, you would initially set your Crosstalk Electrical Threshold high, so that you would only see the very worst coupled nets in the report. As the layout is refined, you could reduce the threshold to catch the remaining aggressors. By the time you

12-6



finish iterating analysis and layout changes, you will be using the smallest Electrical Threshold that could cause your design to violate crosstalk specifications. Because Quick Analysis can be run in a matter of minutes for many boards, it is possible to run analysis, evaluate tradeoffs, and have routing changes finished in the same day. While it will take longer for complex boards with many nets, it is still faster than not catching problems, only to see them occur during prototype testing (and consequent debugging).


12-7


Quick Analysis Options Quick Analysis Options ♦ ♦ ♦ ♦ ♦

The Board Wizard Report Default name is .RPT Date/time stamp Files and parameters used Run time at end of report file



Notes: The Quick Analysis options include both analysis options for risk assessment and solutions, and report generators, which were covered in the previous chapter. Every report file header includes settings used during analysis. This allows new report files to be generated using the same stackup and settings as previous ones (or to easily detect when two report files were not run with the same settings). At the bottom of each report file is the end time summary.

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Quick Analysis Options (Cont.) Quick Analysis Options (Cont.) START TIME ************************************************************ Date ............................. Tuesday Jun. 20,2000 Time ............................. 17:36:45

GENERAL INFORMATION ******************************************************************* Board ............................ demo_corp.hyp Total number of nets ............. 43 Total number of components........ 42 Board temperature ................ 20.0 degrees C Default IC model (used for quick analysis if IC model is missing) IC driver rise/fall time ..1.000 ns IC driver output impedance 28.0 ohms IC input capacitance ..... 7.0 pF **********************************



Notes: Example of header section describing design files and parameters.


12-9


Show Signal Integrity Problems Show Signal Integrity Problems



Notes: The Show Signal Integrity Problems option adds a section in the report file listing all nets longer than the critical length. If no driver is found on the net, then the default IC model is used. The nets are sorted in the order in which they occur in the database. The "Show signal-integrity problems caused by line lengths" option uses the Terminator Wizard algorithm to identify nets that are long enough to require termination. There is an option to not report nets that have a resistor (i.e. nets that have been terminated). In addition to listing all nets that are too long, the report will also include termination components whose stub lengths are too long. This includes series

12-10



terminations that are too far from a driver and AC terminations where the resistor is too far from the receiver or the capacitor.


12-11


Suggest Termination Changes Suggest Termination Changes



Notes: The "Suggest termination changes and optimal values" option calculates termination values to add to the report file. There is an option to include IC input capacitances and effective trace impedances in the report file. This option runs the Terminator Wizard algorithm to calculate component values. Sometimes, if multiple terminations are found on a net and no component values are calculated, you can get the necessary information by running the Terminator Wizard in interactive mode. If no driver is found on the net, then the default IC model is used.

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The Crosstalk Threshold is used to calculate trace impedances, which depend on the influence of neighboring nets. The Default IC Model is used to calculate terminations. These are also used for calculating terminations for differential nets.


12-13


Show Crosstalk Strengths Estimate Show Crosstalk Strengths Estimate



Notes: The Crosstalk Strength report uses the same expert algorithm used to identify aggressor nets that is used in interactive simulations. Every net is checked against every other net on the board, ensuring that no crosstalk aggressor is overlooked. You have the option of reporting only nets above your electrical threshold, or reporting every net on the board. The expert algorithm that identifies the crosstalk coupled nets makes worst-case assumptions to insure no crosstalk coupled nets are overlooked. This means the the Default IC Model is used if there is no driver model on the net. Also, the algorithm assumes all nets are unterminated. The sum of the two strongest aggressor strengths is also shown in the report file, since that is more typical (although not always worst case).

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The Crosstalk strengths report section is sorted with the highest crosstalk nets at the top of the list. Also, the sum of the two strongest aggressors is calculated, since the sum of all crosstalk amplitudes often overestimates the crosstalk observed in simulations. To generate the Crosstalk Strengths Report, the expert algorithm uses the driver edge rate and the transmission line coupling information from the stackup. If you change the driver or the stackup, the crosstalk will change. There is an option to report all nets, or just those that exceed the Electrical Threshold specified on the batch mode menu. Crosstalk analysis requires a Default IC Model, which is used only on nets with no driver models assigned. This Default IC Model should be set to the fastest edge rate on your board, with corresponding "fast corner" resistance and capacitance. Note that the Default IC Model and the Electrical Threshold settings for batch analysis are saved separately from those for interactive analysis, and that the window titles indicate that these are batch mode values.


12-15


Show Crosstalk Strengths Estimate (Cont.) Show Crosstalk Strengths Estimate (Cont.) ♦ Lower Threshold = More Coupled Nets



Notes: A net may have significant self-coupling, such as net SERP_CLOSE in the listing shown below. When a net has significant self-coupling, detailed simulations should be run with Crosstalk enabled, since this self-coupling leads to an impact on delay. Differential nets should have self-coupling; if they do not, then you will probably want to use a smaller value for your Crosstalk Threshold.

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Show Crosstalk Strengths Estimate (Cont.) Show Crosstalk Strengths Estimate (Cont.) Default IC model (used for quick analysis if IC model is missing) IC driver rise/fall time ..2.000 ns IC driver output impedance 5.0 ohms IC input capacitance ..... 5.0 pF CROSSTALK STRENGTH REPORT ********************************************************************** The following crosstalk information is intended to be worst case estimates assuming all nets are unterminated. Maximum allowed crosstalk ........... 200 mv peak NET = IMP_A6 ELECTRICALLY ASSOCIATED NETS -------------------------------------None AGGRESSOR NETS (Estimated peak crosstalk) IMP_A5 ......................... 291 mv

IMP_A7 ......................... 289 mv Sum of the two strongest aggressors ............. 580 mv ** Warning ** Estimate exceeds maximum allowed crosstalk!



Notes: Sections clipped from a typical report file with only the Crosstalk Quick Analysis option selected.


12-17


Quick Analysis Report Options Quick Analysis Report Options



Notes: The remaining five Quick Analysis options generate summary reports. For the entire board, you can choose from Show component changes, Show new components and Show stackup. For each net on the entire board you can choose from Show metal interconnects or Show counts. Some of these options require information about the Default IC Model and the Electrical Threshold for Crosstalk. Showing component changes reports all changes of component values for existing terminations, while showing new components reports all added terminations (Quick Terminators). Showing stackup adds the layer information to the report file.

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Quick Analysis Report Options (Cont.) Quick Analysis Report Options (Cont.)



Notes: If you select "Show metal interconnects", you can then choose to report any of the following Interconnect Statistics for each net:

• Min and Max trace impedance • Total trace length • Total trace capacitance (w/o ICs) • Total trace inductance • Total trace resistance


12-19


• Average trace impedance • Total trace delay (copper only, w/o ICs) The "Show Metal Interconnects" produces the same information as Net Statistics. It reports data based on segments, not on the actual routing topology, and ignores the ICs. For example, the reported total delay is the sum of the segment delays, independent of how the segments are connected; to obtain pin-to-pin delays, you must run signal integrity simulations. Min, max, and average trace impedance are the min, max, and average of the segment impedance values, and do not take into account the length of any segment. These statistics can be used to estimate maximum trace delays and to check nets for potential impedance discontinuities.

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Back Annotation Back Annotation ♦ Component changes ● ●

Quick Terminators Value changes

♦ Present Stackup in Report file ♦ Model annotations are manual



Notes: Quick Analysis reports can be generated at any time. Because the schematic diagram and layout can be done in any of several layout tools (HyperLynx provides interfaces to about 20), BoardSim may not provide back annotation to your CAD interface. Example: Suppose you use Quick Analysis, and find a net requires termination. You add a Quick Terminator and optimize the component values with the Terminator Wizard. This design change requires adding components to both the schematic diagram and the physical layout. There are two ways to do this: generating a Report of design changes, or documenting it manually. (Remember that changes to a pin's IBIS model must


12-21


always be documented manually.) Since you may generate several changes in the design as you find nets requiring different terminations, it is usually easiest to use the automatic report generation to help you document termination changes since the layout was last imported. Remember that changes of IC model assignments must be done manually. The two options, "Show new components" and "Show component changes", report Quick Terminators and changes to component values respectively. While your layout tools probably provide automatic checking between the schematic and the layout, there is no automatic checking against your final BoardSim simulation file. This makes it particularly important to run these options as a final check. Version 6.0 will support ECO back annotation for PowerPCB layout and ViewLogic schematic tools.

12-22



The Final Check The Final Check ♦ ♦ ♦ ♦ ♦ ♦

ECO changes complete Board Wizard as a P/F checker Use smallest value for Crosstalk Threshold Quick Analysis Simulation on known-troublesome nets Release to Prototype



Notes: Once layout has been finished, the Board Wizard should be run one last time as a final check. This final check should be run prior to submitting the board for prototype build, with signoff by engineering. Quick Analysis can be used to make sure all back annotation has been done and that no signal integrity risks remain. This is also a good time to run final detailed simulation on all critical nets that have been identified throughout the design cycle. During these final checks, you should use the smallest Crosstalk Electrical Threshold that could cause your design to violate crosstalk specifications. By this time, you have run detailed signal integrity, crosstalk, and EMC analysis on your high speed and "known troublesome" nets. You have made design and layout changes based on results from Quick Analysis and from simulation.


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Because changing a termination on one net will change the net's signal integrity and EMC performance and the crosstalk interaction with neighboring nets, running Quick Analysis and detailed simulations checks helps you make sure that none of the changes made along the way "broke" nets that did not previously have problems.

12-24




Using Quick Analysis Crosstalk Self Coupling



Notes:


12-25


12-26


Module 13 Using BoardSim to Find Solutions


13-1

Using BoardSim to Find Solutions

Using BoardSim to Find Solutions Using BoardSim to Find Solutions ♦ Causes ♦ Finding possible solutions ♦ Comparing solutions

13-1 • HyperLynx Signal Integrity Analysis: Using BoardSim to Find Solutions


Notes:

13-2



Causes Causes ♦ ♦ ♦ ♦

Technology Topology Termination Trace Parameters



Notes: You have already seen how to identify symptoms of signal integrity, crosstalk, and EMC problems. While many of these problems can be solved early in the design cycle using LineSim, others cannot be solved until placement is done. BoardSim can use any routing information that is supplied during translation (including unrouted nets if the translator supports them). There are three fundamental solutions to signal integrity problems: technology, topology, and termination. Technology: Fast driver edge rates increase the risk of signal integrity, crosstalk, and EMC problems. Slower edge rates, or trading the edge rate against the drive strength, can help solve signal quality problems.


13-3


Topology: Changing the way a net is routed, or the transmission line characteristics of traces, helps delay and skew problems. Making a net shorter than the critical length reduces ringing, crosstalk, and EMI problems. Termination: Termination, while adding components which do not perform any logic function, is required for long nets with fast drivers. BoardSim helps you identify long nets in the physical layout, evaluate different termination strategies and calculate optimal component values.

13-4



Finding Possible Solutions Finding Possible Solutions ♦ ♦ ♦ ♦

Combine experience + analysis tools Quick Terminators for adding new terminations Termination most likely changes Can change layer assignments fairly easily ●

Keep blind/buried via layers together

♦ Base changes on post-layout information



Notes: Getting to a solution quickly requires a combination of experience and tools. BoardSim helps you identify solutions due to tradeoffs made during layout, and to quickly evaluate tradeoffs when there are multiple solutions. Quick Terminators are especially useful, since terminations are one of the most common things to change on a completed board (stackup being another). The same solutions as we saw in LineSim still apply: technology, topology, and termination. For technology, you will probably tune your driver selection, such as deciding how to trade rise time against driver strength. The advantage of doing this in BoardSim is the ability to evaluate tradeoffs based on actual layout, rather than estimated lengths for LineSim.


13-5


Finding Possible Solutions (Cont.) Finding Possible Solutions (Cont.) ♦ Edge rates have major impact ●

Depending on routing loading

♦ Select drivers based on net’s topology ♦ Bi-directional nets ●

Optimize both ends



Notes: 12.2.1: Technology The driver edge rate has a major impact on signal integrity. Sometimes, choosing a 6mA "slow" driver may actually provide better signal integrity than a 2mA "fast" driver. This is because the slower edge rate may provide a faster settling time due to the buffer having a slower edge rate limit internal to the buffer. Simulation in BoardSim can help you evaluate the tradeoffs. This is particularly important for driver assignment in FPGAs, where driver assignment can be optimized after layout of critical nets. At this point, all drivers on a net can be optimized. Each driver can be individually optimized based on its loading ("driving point impedance").

13-6



12.2.2: Topology Changing dielectric thickness or materials changes delay, impedance, and even crosstalk and EMC performance. Changing the stackup and layer assignments are topology solutions that can be implemented during layout as well as design. Changing layer stackup has almost no cost, as long as the layers connected by blind and buried vias remain connected. If a routing change is required, it must be made in the layout tool and translated/imported into BoardSim. Typical topology changes made in BoardSim are reordering layers in the stackup or identifying places shorten stub lengths. For long traces, moving layers in the stackup can be used to evaluate the effects of layer assignment. (In BoardSim, it is not possible to reassign individual trace segments to different layers.) For example, to evaluate the effect on EMI, swapping the top layer and an inner signal layer can be used; a long trace on the top layer will have significantly reduced EMI after the swap. Once you have determined your stackup and routing layer assignments, the routing changes can be made in the layout tool and the design imported back into BoardSim. In Version 6.0, Manhattan length routing for unrouted nets will be supported, as well as ripup of existing nets.


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Technology and Topology Technology and Topology ♦ ♦ ♦ ♦

Edge rates are important Signal integrity depends on length and edge rate If length > critical length, then termination is recommended Lcrit = vel * Tedge / 6



Notes: The length of the trace also has a significant effect on the ringing. For a longer line, both delay and ringing increase. To eliminate signal integrity problems, the recommendation is that the line be no longer than the critical length (Lc = vel*Tr/6), where vel is the speed of the signal down the line and Tr is the driver edge transition time. Another way of saying this is that the delay in the transmission line should be no more than 1/6 of the driver transition time. For example, for an edge rate of 1 nsec, the critical length is approximately (6 inches/nsec * 1 nsec / 6), or 1 inch. At 250 psec, this length becomes only 0.25 inches! This figure shows how ringing depends on transmission line length

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Careful choice of topology and following topology constraints during layout can prevent many problems. Shortening critical nets and stubs helps reduce signal integrity problems and EMC problems. For example, when skew must be minimized, star routing is preferred over daisy chain routing. Star arms of equal length do not always have equal delay time, depending on which layers are used for routing. LineSim can be used to analyze various topologies, allowing you to select those that improve your design's signal integrity performance. Using LineSim to develop spacing constraints can help you prevent crosstalk before layout is even started. Changing trace width impacts trace delay and impedance. Changing dielectric thickness or materials changes delay, impedance, and even crosstalk and EMC performance. Changing the stackup and layer assignments are topology solutions that can be implemented during design and layout.


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Termination and Quick Terminators Termination and Quick Terminators ♦ Unterminated nets ● ●

Termination style Termination values

♦ Crosstalk ● ● ●

Solve with termination Solve with stackup changes These also impact signal integrity

♦ EMC ● ●

Solve with termination Solve with stackup changes



Notes: Termination is the most commonly applied solution during BoardSim analysis. The Terminator Wizard is used to optimize component values and Quick Terminators are added where new terminations are required. Typical terminations include a series resistor near the driver, or an AC load (RC to ground or Vcc) at the load. The series resistor helps match the driver's output impedance to the transmission line impedance, damping any ringing at the driver end of the transmission line. The AC load helps match the receiver impedance to the transmission line impedance, damping any ringing at the receiver end of the transmission line. BoardSim supports most of the termination styles used on high speed boards.

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The Terminator Wizard calculates optimum values for termination components, whether they are in the physical layout or have been added as Quick Terminators. This saves you running unnecessary Monte Carlo analyses to optimize values. The Terminator Wizard includes the effects of impedances for drivers, receivers, and segments automatically. If there is no termination, the Termination Wizard can even suggest a termination style. Finally, the Terminator Wizard allows you to specify the tolerance on the termination components, and picks the appropriate standard value, while exact values are useful on MCMs where passive components can be fully customized.


13-11


Termination and Quick Terminators (Cont.) Termination and Quick Terminators (Cont.) ♦ Choose from termination styles ♦ Optimize with Terminator Wizard ♦ “Remove” existing termination ● ● ●

Rseries = 0 ohms Rshunt > 10K ohms Cshunt = 0 pF

♦ Add Quick Terminators



Notes: In addition to choosing the termination style, you can effectively remove terminations be setting series resistor to 0 ohms, shunt resistors to 10K ohms or larger, and shunt capacitors to 0 pF. If the Terminator Wizard recommends a terminator style that is not on the net on the layout, you can add it by "removing" the existing terminator (if any), and applying a Quick Terminator at the desired IC pin.

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Quick Analysis Quick Analysis ♦ ♦ ♦ ♦ ♦

Identifies nets needing termination Recommends termination style & values Identifies crosstalk problems Fix with stackup changes Fix with termination changes



Notes: Quick Analysis is the fastest way to identify nets that require termination. In addition, Quick Analysis can recommend termination component styles and values. Using the Quick Analysis options for termination analysis allows you to quickly identify nets longer than their critical lengths (Lc = vel*Tr/6, where vel is the speed of the signal down the line and Tr is the driver edge transition time). You can also identify nets lacking terminations, allowing you to quickly focus on nets requiring Quick Terminators. Often, crosstalk problems occur in areas of the board where traces have been closely routed due to routing congestion. Crosstalk effects can be reduced by


13-13


making dielectrics thinner. This can be done without changing the layout, allowing this solution to be quickly tested in BoardSim. Another solution, moving traces further apart, must be done in the layout tool and the new layout translated back into BoardSim. Remember that these changes will impact signal integrity and EMC performance, so check the board with Quick Analysis if a change is made to the stackup. Fixing crosstalk by termination requires checking only crosstalk for the entire board, which should always be part of the final pass. Often the total stackup must maintain a fixed thickness. In this case, it make sense to change the dielectric between two planes, rather than between a plane and a signal layer, since this does not change any trace impedances. If one or more layer thicknesses are changed, Quick Analysis should be run to check for changes in termination recommendations and crosstalk risk across the entire board.

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Terminations Terminations ♦ Nets with one receiver ●

Series termination

♦ Nets with more than one receiver ● ●

AC termination Terminate every driver (bi-di) pin

♦ Placement of termination components ● ●

Series next to driver AC next to receiver



Notes: 12.2.3.2: Nets with One Receiver A net with one receiver should be short as possible. If termination is required, a series resistor between the driver and the transmission line is most commonly used. This reduces the initial current and voltage into the transmission line. At the receiver end, the energy coming down the transmission line is reflected back towards the driver, causing the voltage to double due to signal reflection, and as a result the signal at the receiver crosses the logic threshold. If the resistor is added using a Quick Terminator, it should be added at the driver IC pin. On a routed board, a net may be laid out as several segments on different layers, resulting in each segment having a different characteristic impedance. The


13-15


Terminator Wizard takes these into account when optimizing the termination component values. Receivers are treated as being lumped at the end of the line, so a long bus with many drops may require some fine tuning of the capacitor. 12.2.3.3: Nets with More than One Receiver With more than one receiver, skew becomes an issue. If one net is routed on an outer layer, and another on an inner layer, they may have different delays for the same length, since signal propagation speeds will be different on different layers. This is a major problem for differential nets, which should always be routed on the same layers for the same lengths. Skew between receivers (on the same net or between nets) should be checked after layout is complete. Skew can also be checked while routing critical nets, while there is some flexibility in placement and routing. 12.2.3.4: Placement of Termination Components BoardSim has all of the information for distances to termination components, as well as pin parasitics from the IBIS or PML models for the drivers and receivers. For Quick Terminators, the series resistor has a user-definable stub length. Once you have decided on the termination components to be added, the physical layout can be updated and the new layout imported into BoardSim. This brings in the new information on physical routing distances between terminators and ICs.

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Comparing Solutions Comparing Solutions ♦ Detailed simulation ♦ Scope simulation ● ● ● ● ●

Delay Skew Overshoot Undershoot Crosstalk

♦ EMC/Spectrum simulation



Notes: Simulation results present tradeoffs in a very visual way. For example, by trying two different termination strategies and looking at their receiver waveforms, you can quickly see which produces the better signal integrity. Because BoardSim works from actual layout information, these simulations can be used as virtual prototypes, without the time and cost associated with a physical prototype. BoardSim contains two simulation engines. The Scope Simulator allows you to look at plots of voltage waveforms vs. time. This is useful for checking delay, skew, overshoot, undershoot and crosstalk. The Spectrum Analyzer runs a time simulation for several clock cycles, performs an FFT (Fast Fourier Transform), and gives you a plot of electric field (dBuV/m) vs. frequency. The Spectrum


13-17


Analyzer can plot the frequency spectrum of emitted radiation at an antenna, or the current in a component pin (such as a driver). Fixing a signal integrity problem often helps reduce EMC problems, since higher EMC is associated with signal ringing. However, a termination that has a small effect on ringing may have a large effect on EMC. Thus terminations that were optimized in LineSim need to be tuned for the actual routing.

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Comparing Solutions (Cont.) Comparing Solutions (Cont.) ♦ ♦ ♦ ♦

Early placement & unrouted traces Final placement & routing Final driver IBIS models The typical design strategy is to change "technology, topology, termination, and trace parameters” ♦ Iterate LineSim/BoardSim until design specifications are met ♦ Practice “due diligence”



Notes: Once the placement is done, you can begin simulation using estimated lengths for unrouted traces; this guides the detailed routing of those critical nets. After layout of critical nets has been completed, performance can be tested. You can import the layout into BoardSim throughout the layout cycle for additional analysis. By working from actual layout information for critical nets, you catch potential problems early. Ideally, actual IBIS models for drivers will be selected early in the layout process, since this influences the optimal values for terminations. The typical design strategy is to change "technology, topology, termination" until the signal integrity goals are met. Since components have been placed and nets routed, the preferred solutions in BoardSim are termination changes and stackup modifications. Once termination is done, signal integrity and crosstalk simulation


13-19


results should look reasonable. Next, the termination component values can be adjusted to improve EMC. Finally, the worst-case combination of driver edge rate, stackup variation, and component tolerances can be checked to make sure the design will have acceptable yield during production. Termination and stackup tradeoffs can quickly be made in BoardSim to increase the design margins for timing, signal integrity, crosstalk, and EMC. Stackup can also be changed. This makes it easier to meet specifications, and improves the chances of your prototype passing testing first time through. Terminations may increase design margins; which in turn can improve production yield. Often there will be a couple of iterations between layout and BoardSim for critical nets. During layout, nets were assigned to layers, changing the impedance, skew, and thus the signal integrity and EMC. Since more than one net must be assigned to each layer, crosstalk will change as nets are moved to a different layer. In a day, you can make layout changes, import the revised layout to BoardSim, and evaluate the signal integrity and EMC performance. Virtual prototyping can save you the pain of hardware prototype failures and redesign time. Occasionally, a change must be made to placement or routing topology. LineSim is more efficient for exploring layout tradeoffs, and the results are more meaningful when better estimates of trace lengths are available. The LineSim schematic is created manually, using the routing information from the board instead of the rougher estimates used earlier in the design. Because lengths as small as 0.1" or less are important for high-speed designs, care must be taken to match the actual trace routing lengths in LineSim as closely as possible. Once the layout choices have been made, the improvements can be added using the layout tool, and the board imported into BoardSim for analysis.

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EMC Solutions Bi-directional Solutions



Notes:


13-21


13-22


Module 14 Strategies for Using BoardSim


14-1

Strategies for Using BoardSim

Strategy for Using BoardSim Strategy for Using BoardSim ♦ ♦ ♦ ♦ ♦

Design flow Quick analysis Detailed simulation in batch mode Evaluating design tradeoffs Signal integrity signoffs

14-1 • HyperLynx Signal Integrity Analysis: Strategies for Using BoardSim


Notes:

14-2



Design Flow Design Flow ♦ Biggest impact in evaluating critical nets ● ● ●

♦ ♦ ♦ ♦

Placement Routing Crosstalk

Run analysis early in layout cycle Fix problems Update layout Iterate



Notes: The best strategy for integrating BoardSim into your design environment depends on your current design process. However, there are some useful techniques that you can put to use immediately. The biggest impact of using BoardSim comes when you use it for evaluating component placement with critical nets routed, and for running Quick Analysis to identify the highest priority nets for your detailed analysis throughout the layout process. When you do this early in the layout cycle, you have the greatest flexibility in making optimum tradeoffs. Your choices become more constrained as placement is completed and the less critical nets are routed. Evaluating signal integrity, crosstalk, and EMC implies that noise margins have been defined for signal integrity and crosstalk and that there is a specification for


14-3


total noise and EMI emissions for each net. Acceptable noise, and the associated system effects, such as clock duty cycle variation, vary by application. Usually the same specifications are used that were used with LineSim.

14-4



Design Flow (Cont.) Design Flow (Cont.) ♦ Run Quick Analysis ● ● ●

After Initial placement After critical nets have been routed Each time the layout is updated.

♦ Target nets ● ● ●

Identified in Quick Analysis High-speed clock and bus nets Known troublesome nets



Notes: The following steps, when integrated into your design process, can help you build in quality and prevent signal integrity problems right from the start. 1. Run Quick Analysis after initial placement, after critical nets have been routed, and each time the layout is updated. 2. Target nets identified in Quick Analysis, as well as high-speed clock and bus nets, and known troublesome signals.


14-5


Design Flow (Cont.) Design Flow (Cont.) ♦ Use Quick Terminators to add terminations ♦ Use the Terminator Wizard to optimize terminations ●

Based on the physical layout

♦ Run detailed simulations on targeted nets ● ●

Interactive simulations Detailed Batch simulations

♦ Use LineSim to evaluate topology changes



Notes: 3. Use Quick Terminators to add terminations if necessary. 4. Use the Terminator Wizard to optimize terminations based on the physical layout. 5. Run detailed simulations on targeted nets, either interactively or in batch mode. 6. Use LineSim to evaluate any major topology changes.

14-6



Design Flow (Cont.) Design Flow (Cont.) ♦ Document design changes (Models, Quick Terminators, component values) ♦ Run Quick Analysis one last time ♦ Run detailed simulations one last time ●

On all targeted nets

♦ Get signoff on signal integrity, crosstalk, and EMC



Notes: 7. Document design changes (IC models, Quick Terminators, component values). 8. Run Quick Analysis one last time. 9. Run detailed simulations one last time on all targeted nets. 10. Get signoff on signal integrity, crosstalk, and EMC results before releasing the design to prototype build. Generally, you will optimize your signal integrity first. This usually also helps both crosstalk and EMC performance. Once signal integrity meets your


14-7


requirements, you may find that changes in the stackup or tweaking component values are sufficient to meet EMC and crosstalk requirements. Or you may find that using one termination style on a net does not meet requirements, in which case Quick Terminators can be used to evaluate alternative termination strategies. Ideally, signal integrity analysis is integrated into the layout process from start to finish. This makes it easier to design signal integrity into the design, and makes your efforts most effective.

14-8



Quick Analysis Quick Analysis ♦ ♦ ♦ ♦

First thing to do with a layout Avoid overlooking nets Terminator Wizard for every net Crosstalk estimation for every net ● ●

High threshold early in layout Tighter threshold in final checks

♦ Identify any new “troublesome nets”



Notes: Running Quick Analysis is the first thing to do when a Board is loaded into BoardSim after a layout change. This is the fastest way to identify nets at risk for signal integrity or crosstalk problems. While you may have identified critical nets in LineSim, there will be additional nets that should be added to the list of nets to be targeted due to the way they have been routed. Quick Analysis uses expert algorithms, and runs much faster than detailed simulation, making it practical for evaluating every net on the entire layout. The Terminator Wizard algorithm can be automatically run for every net on the board. In the report file, recommended terminations are listed for each net.


14-9


The Crosstalk Strengths Report section lists all aggressor nets where the expert algorithm's estimate of crosstalk exceeds the Electrical Threshold. Since the Crosstalk Strengths Report is sorted with the greatest coupling at the top, you can quickly identify the nets that you need to work on.

14-10



Detailed Simulation in Batch Mode Detailed Simulation in Batch Mode ♦ Critical nets ● ●

Clocks High speed bus nets

♦ Known troublesome nets ♦ Check all driver “corners” ♦ Crosstalk ● ● ●

Crosstalk voltage if in Crosstalk Strengths Report Early timing without crosstalk effects Final timing with crosstalk effects



Notes: There are many ways to identify nets for targeting. Clocks and selected nets on buses, nets with fast drivers, and known troublesome signals should all be included in your list of nets for detailed simulation in batch mode. Nets identified during Quick Analysis or in LineSim should also be included. Targeted nets can be selected for detailed simulation done in batch mode. While setting up Detailed Simulation for Batch mode, enter your targeted nets in the Nets Spreadsheets, and specify the limits for reporting errors. For example, you might select a maximum Overshoot of 0.9 volts, a Pin Delay of 2.1 nsec, or an EMC Frequency of 133 MHz with checking against FCC limits. Once you have entered the values for each targeted net, you can save these settings for all future


14-11


batch analyses. By keeping the Nets Spreadsheet up to date, there is a complete list of targeted nets. Early in the design, you may set your crosstalk thresholds high, and exclude aggressors during signal integrity simulation. This allows simulation to run faster. You can still do crosstalk simulations to observe the amplitude of the coupled voltages. During early analysis, you may choose to use the Fast driver model option, which usually generates the largest signal integrity and EMC problems. However, it is recommended that you also check using the Slow driver models. For example, changing the model will change the frequencies exhibiting the strongest EMC emissions, and Fast and Slow models produce different spectral peaks. As the signal integrity and EMC issues are resolved, crosstalk risk can be assessed using Quick Analysis under the Batch Wizard. Initially, a high Electrical Threshold can be used, limiting reporting to the worst aggressors. The electrical crosstalk threshold can later be tightened. Crosstalk coupled voltages can be checked using detailed simulations, either interactively or in batch mode. Finally, crosstalk can be included during detailed signal integrity simulation on critical nets, allowing you to see the impact of crosstalk upon pin delays (timing). Since simulation with crosstalk enabled slows simulation speeds, you will probably use this option only after other signal integrity issues have been resolved.

14-12



Evaluating Design Tradeoffs Evaluating Design Tradeoffs ♦ Tradeoffs made throughout layout ♦ Terminations and topology ● ● ●

Board area Component count & cost Manufacturing cost

♦ Slower Driver or Add Termination? ♦ Stackup changes for Crosstalk and EMC ● ●

Layer ordering Dielectric thicknesses



Notes: A system designer makes many tradeoffs during circuit design and layout. For example, adding a termination component to solve a signal integrity problem increases component count (along with board area and cost). There is often more than one solution, involving choices for technology, topology, or termination. These solutions can be traded against each other, even during layout. Each solution has a different impact on circuit performance, component count, board area, stackup complexity, and production cost. Using BoardSim to evaluate tradeoffs that impact signal integrity and EMC performance can assist you in making those critical choices. One of the choices you can make is the selection of a driver. Because the best choice between drive strength and edge rate depends on the actual routing length


14-13


and topology, this can be reevaluated after layout. For example, if you are designing using an FPGA, the final decisions about I/O buffers can be made late in the design - right up until the files are sent to the FPGA vendor. Another design tradeoff that can be made once layout is complete is the choice of terminations in critical nets (or even nets that have low switching frequencies but fast edges). The Terminator Wizard can suggest termination values, and allow you to select from standard tolerance ranges from 0% to 20%. If additional terminations are needed, Quick Terminators can be added. Stackup changes, such as layer ordering or dielectric thicknesses, can be traded off to optimize signal integrity, crosstalk and EMC performance. Typically, dielectric thicknesses can be adjusted in fixed increments. One or more layers are used to adjust the total thickness; these should be between [planes if possible, since their thickness (and therefore impedance) are not as tightly controllable as the other dielectric layers. Evaluating design tradeoffs is best done using interactive analysis. This allows you to work only on the most troublesome nets identified in Quick Analysis reports. Detailed Simulations have been used to check the magnitude of the problem. Interactive analysis also allows you to check the ringing, including both overshoot and undershoot, for critical nets.

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Signal Integrity Signoffs Signal Integrity Signoffs ♦ SI requirements in design specifications ♦ Signoff required at the end ♦ Use Quick Analysis as a signoff tool ● ●

Batch report file can be quickly scanned Use Warning & Severe Warning "find" icons

♦ ECO back annotation complete ♦ Manual back annotation complete ♦ Scripts to process files



Notes: One of the key steps that is often overlooked in the rush to get a design out the door is the signoffs for signal integrity and EMC. It is not sufficient to generate a report file using the Batch Wizard. At some point, the report file needs to be checked for violation reports from both Quick Analysis and from detailed simulations on the targeted nets. The batch report file can be quickly scanned using the automated Warning and Severe Warning "find" icons. These can be used to find nets that violate limits during detailed simulation for signal integrity, crosstalk, or EMC. Alternatively, scripts or functions such as "grep" can be used to search the file; if there are no warnings, there are no violations found during detailed simulations.


14-15


Another signoff step is to make sure all back annotation steps that required manual intervention (such as placing termination components) were done correctly. Also, Quick Analysis should be run with the options set to report only those nets without resistors; this catches any remaining unterminated nets.

14-16


Module 15 Multiboard Analysis


15-1

Multiboard Analysis

MultiBoard Capabilities MultiBoard Capabilities ♦ MultiBoard analysis is performed by joining multiple .HYP files ♦ MultiBoard project data is stored in a .PJH file ●

● ●

♦ ♦ ♦ ♦ ♦ ♦

Board names(.HYP files), board IDs, directory locations, and, comments Board-to-Board interconnectivity Electrical charactizations of the interconnect

MultiBoard Project Wizard is used to create the .PJH file Analyze signal integrity on nets that span across boards Analyze Crosstalk on nets that span across boards Analyze nets using the Board Wizard (Batch mode analysis) Use the current probe on nets which span multiple boards Use unique name for .PJH file (e.g. make different than single board)

15-1 • HyperLynx Signal Integrity Analysis: Multiboard Analysis


Notes:

15-2


Multiboard Analysis

MultiBoard Caveats MultiBoard Caveats ♦ Maximum Number of boards ● ● ● ●

Physical memory 252 metal stackup layers maximum Layers of boards which are multiple instances counted once Dielectric stackup layers are not limited

♦ Unavailable features: ● ● ●

EMC Analysis Terminator Wizard Back Annotation



Notes:


15-3

Multiboard Analysis

MultiBoard Wizard MultiBoard Wizard



Notes: The MultiBoard wizard is accessed via the Hyperlynx MultiBoard menu pick. The wizard guides the user through the process of creating and managing MultiBoard Designs. To create a project, one would, from the Hyperlynx MultiBoard Menu, select New MultiBoard Project..., Use the Browse button to either verify the directory to which the Wizard is pointing or to set it to a different location.

15-4


Multiboard Analysis

MultiBoard Wizard (Cont.) MultiBoard Wizard (Cont.)



Notes: Select the Insert button (point to the insert button) to open the Select BoardSim File(s) dialog box. Navigate to the appropriate directories, select the desired .HYP files, and click the Open button. Multiple .HYP files may be selected using the You will note, that the Project Wizard dialog box updates with the boards which are to be connected in the system. Each board is automatcally assigned a board id. The board id and the connectors on the boards are used to connect the boards together.


15-5

Multiboard Analysis

The three textual columns may be edited. Modifying the first and third are not recommended. It is suggested, however, that one add comments when processing a complex system. This helps when one comes back to the Wizard at a later date.

15-6


Multiboard Analysis




Notes: The boards are assigned a unique identifier called the Board ID. To connect the boards, select the Design File (e.g. Board id) on the left side of the dialog box, then select the connector by reference designator, then select the mating board from the right side and the appropriate mating connector from the Reference Designator list. Once the appropriate boards and corresponding mating connectors, have been selected, click on the Insert button. To correct mistakes, simply select the erroneous connection, and select the Delete button. Once the Insert button has been activated, the lower portion of the wizard will update displaying the board ids and the mating connectors.


15-7

Multiboard Analysis

The interconnect is one for one, for example, J1-1 on Board B00 is connected to P3-1 on board B01. One may also select Don't Connect on the right.

15-8


Multiboard Analysis




Notes: Once all the boards have been connected, click the Next button. This action gives the user the ability to select the board/pairs and specify the connector parasitics. The vendor should be contacted for the most accurate information. If there isn't any data available, use the defaults. The parametrics may be described in terms of R/L/C or R/Delay/Z0. The simulation engine views connectors as two transmission lines connected through a resistor. As such, if the data is entered in terms of R/L/C, the wizard calculates and displays the equivalent Delay and Z0.


15-9

Multiboard Analysis

MultiBoard Display MultiBoard Display



Notes:

15-10


Multiboard Analysis

Editing MultiBoard Projects Editing MultiBoard Projects ♦ ♦ ♦ ♦

Use menu: MultiBoard => Edit MultiBoard Project (.PJH)... Opens the MutliBoard Wizard Board interconnectivity modified as previously described Use menu: Edit => Power Supplies to update any supplies not auto recognized; Ensure Apply to similiar boards is enabled



Notes:


15-11

Multiboard Analysis

Multiple Instances Multiple Instances ♦ Changes made to one affects all (one data set describes a board) ♦ Recommend create a copy of .HYP for each instance ♦ Multiple files allows changes to be saved to unique BUD files ♦ Apply similiar propagates changes to all boards of same name ♦ Apply similiar affects ● ● ● ● ● ●

IC model assignment Passive Component Values Quick Terminator Power Supply Net Specification Manhattan Routing Unrouting



Notes:

15-12


Multiboard Analysis

MutliBoard Net Selection MutliBoard Net Selection



Notes:


15-13

Multiboard Analysis

Setting Probes for Multiple Boards Setting Probes for Multiple Boards



Notes:

15-14


Multiboard Analysis

Model Assignments Model Assignments



Notes:


15-15

Multiboard Analysis

Adding Terminators: Multiple Boards Adding Terminators: Multiple Boards



Notes:

15-16


Multiboard Analysis


Creating and Running with a Muti-board Design Running with a Muti-board Design



Notes:


15-17

Multiboard Analysis

15-18


Module 16 Wrap-up


16-1

Wrap-up

Wrap-up Wrap-up ♦ Describe LineSim and BoardSim ♦ Where each fits in the design cycle ♦ Strategies for solving signal integrity problems ● ●

Pre-layout Post-layout

16-1 • HyperLynx Signal Integrity Analysis: Wrap-up


Notes: At this point, you can now:

• Describe the differences between LineSim and BoardSim and where each fits in the design cycle;

• Create a new LineSim schematic, adding components and connections; • Strategies for solving both pre-layout and post-layout signal integrity problems.

16-2


Wrap-up

Wrap-up (Cont.) Wrap-up (Cont.) ♦ ♦ ♦ ♦ ♦ ♦

Create and edit a LineSim schematic Import a completed layout into BoardSim Open a BoardSim layout (HYP file) Simulate and describe signal integrity Simulate and describe crosstalk effects Simulate and describe EMC emissions



Notes: • Create and edit a LineSim schematic (TLN file), adding components and connections;

• Import a completed layout into BoardSim; • Open a BoardSim layout (HYP file); • Simulate a net and describe the signal integrity characteristics; • Simulate a net and describe the crosstalk effects on signal integrity and on timing;


16-3

Wrap-up

• Simulate a net and describe EMC emissions characteristics and driver current characteristics;

16-4


Wrap-up

Wrap-up (Cont.) Wrap-up (Cont.) ♦ Fix common signal integrity problems ● ●

♦ ♦ ♦ ♦ ♦

Pre-layout Post-layout

Change IC models Change stackup Add a termination & optimize value(s) Run batch mode Quick Analysis Run batch mode analysis on critical nets



Notes: • Fix common signal integrity problems in pre- and post-layout designs; • Change IC models for drivers and receivers; • Change stackup layer properties and layer ordering; • Add a termination; optimize component values; and determine the effect on signal integrity;

• Run batch mode Quick Analysis to identify all risk areas for signal integrity;


16-5

Wrap-up

• Run batch mode analysis to simulate critical nets.

16-6


Wrap-up

Sharing Answers to Users’ Questions Sharing Answers to Users' Questions ♦ ♦ ♦ ♦

HyperLynx Listserver (HyperTalk) Signal integrity reflector (si-list) IBIS reflectors [email protected]



Notes: Everyone can benefit by sharing ideas and answers. Many of the things shared during this course have helped all of us better understand the product features and capabilities that will help you meet your daily design challenges. To continue sharing ideas and solutions, you will want to join the community of HyperLynx users on the HyperLynx Listserver. This is a great place to ask signal integrity and IBIS questions of other HyperLynx users, as well as share ideas on ways to use the software tools to solve design problems. You may also want to join the signal integrity reflector or one of the many IBIS reflectors.


16-7

Wrap-up

Users can send tool-related questions to [email protected].

16-8


Appendix A Installation and System Requirements


A-1

Installation and System Requirements

System Requirements System Requirements ♦ ♦ ♦ ♦ ♦ ♦ ♦

Hardware Requirements The Hardware Protection Key Floating Licenses Software Requirements Licenses for Options The Installation Process Finding Licensed Options and Key Code

A-1 • HyperLynx Signal Integrity Analysis: Installation & System Requirements


Notes:

A-2



Software Requirements Software Requirements ♦ Files on the CD ● ● ● ● ● ●

All executables Tutorial Help files Manuals IBIS Libraries HyperLynx proprietary libraries

♦ Install using the Install Wizard ♦ Updating Microsoft DLLs



Notes: All software, model libraries, and documentation required for operation is shipped on the product CD. The Install Wizard guides you through all steps once the CD is inserted in the drive. The default install puts all files under C:\HyperLynx. If you wish to use another directory, this must be specified during the install process. Use default options unless instructed otherwise on the Installation documentation. HyperLynx software uses several Microsoft DLL files in the Windows and NT versions. Updates for these are obtained over the Web (use Windows Update on your Start menu), and on product CDs from HyperLynx. Normally, you will not


A-3


need to worry about this unless you download the latest Demo CD, since (rarely) the download may be missing an updated DLL.

A-4



Hardware Requirements Hardware Requirements ♦ Operating System ● ●

Windows 98, NT 4.0 and higher Sun Solaris for 5.52 and later

♦ System Hardware ● ● ● ● ● ●

SVGA or higher screen resolution 16 Mbytes of RAM (64 Mbytes for large boards) 65 Mbytes of disk CD drive for install & documentation Mouse Parallel port



Notes: HyperLynx software Versions 5.52 and earlier run under Microsoft operating systems Windows 95, Windows 98, and NT 4.0. The software does not run under Windows 3.1, 3.11, or NT 3.5. Windows 95 will not be supported on 6.0 and higher. HyperLynx 5.52 on Sun/Solaris was demo'ed at DAC in June 2000. The release is expected in Q4, 2000. HyperLynx 6.0 and later will be supported on Windows 98, and NT 4.0 and higher, as well as on Sun/Solaris.


A-5


Support for other operating systems, such as Windows 2000, may be provided in the future. Please inquire for details. The video must have SVGA or greater video resolution (800 x 600). The computer should include at least 16 MegaBytes of physical RAM. Large boards may require 64MB. BoardSim may require additional memory to handle large boards; in general, BoardSim requires about the same amount of memory as the layout tool used for the same board. LineSim and BoardSim may run out of memory if the RAM is being used by other applications. A mouse is required. (2 buttons used, 3 button mouse works.) The computer must have a parallel port for the dongle.

A-6



Hardware Protection Key Hardware Protection Key ♦ Hardware key (Dongle) ● ● ●

Any parallel port used for dongle On user’s computer (node locked) On license server computer (Networked)

♦ Demo/tutorials run without dongle



Notes: Normally the hardware protection key passes signals to printers and other peripheral devices without problems, although the device may need to be powered up for the hardware protection key to function. If a problem is encountered, the peripheral device and the hardware protection key should be connected to separate parallel ports. The license protection is based on a hardware protection key (dongle). This hardware key can be used on a single computer ("node-locked"), or on a designated "server" computer that grants licenses (when available) over the network to client computers ("floating license"). The hardware key must be plugged into a parallel port of the appropriate computer (your computer or a designated server computer, depending on which type of licensing you


A-7


purchased). If the hardware key is not attached, the SIMULATION SOFTWARE button is not operable. (The DEMO remains operable without any dongle.) If there is more than one parallel port, any of them can be used; the software will query the ports to find the hardware protection key. The first time you run LineSim/BoardSim after entering a new license code, the program queries you for the name of the licensed user. The user name is "burned" into the hardware key; from then on, it "travels" with the key. This user name will then appear on all printouts from LineSim and BoardSim. By default, the user name will taken from the user name on the computer. It can be changed via the Options->Preferences->License menu pick.

A-8



Setting Up LineSim Setting Up LineSim ♦ ♦ ♦ ♦

Install CD Set favorite Options -> Preferences Set path for model library Open LineSim



Notes: Once LineSim has been installed, you are ready to use it to enter a schematic and run analysis. The first thing you will want to do is check your Preferences (under Options on the main toolbar). You can set your default stackup information, such as dielectric thickness and test trace width (used for calculating characteristic impedance). There are many other general purpose options, such as using English or metric units for reporting information. You can even change the background color. The options settings are stored on your local computer in the HyperLynx install directory as Bsw.ini. The default path for all model searches is HyperLynx/Libs. Alternatively, you can specify a new directory path under Options for your design-specific model files. If you specify a new library path, you will not be able to see the libraries provided


A-9


with the HyperLynx software, and you will need to copy over any HyperLynx models that you wish to use. All I/O buffer models used in your design must be in the same directory. This includes IBIS, MOD, and PML models. (Models for beads and resistor packs go in the main HyperLynx directory.)

A-10


Appendix B More on High-Speed Design


B-1

More on High-Speed Design

What is “High Speed Design?” What is “High Speed Design?” ♦ At low speeds, all receivers see the same signal at the same time

8 ns Rise/Fall

♦ The PCB trace delay can be modeled as a lumped (single) delay on the driver’s output ♦ No special analog analysis is required

B-1 • HyperLynx Signal Integrity Analysis: More on High-Speed Design


Notes:

B-2



What is “High Speed Design?” (Cont.) What is “High Speed Design?” (Cont.) ♦ At high speeds, transmission line effects cause receivers to see different signals

3 ns Rise/Fall

♦ The PCB trace delay must be considered as a set of pathdependent delays ♦ Transmission line analysis is needed to ensure that Signal Integrity is maintained B-2 • HyperLynx Signal Integrity Analysis: More on High-Speed Design


Notes:


B-3


The Real Culprit The Real Culprit ♦ Rise/fall times, not data/clock speed, determines the degree to which high speed problems will occur

10 nS = 100 MHz


These two driver driver waveforms waveforms have the the same period, period, yet the the upper signal will create create more high speed design design problems. problems.


Notes:

B-4



Critical Length Critical Length ♦ When a net exceed the “Critical Length” it is likely to exhibit poor signal quality and may require termination ♦ Critical Length = Trf/(6*S)

(

Point-to-Point Length

)>

90% Rise Time

/ 6(Trace Vel)

10%

♦ Example: Given, 1ns Risetime, 2ns/ft trace velocity(S); the critical length is: (1ns )/(6*2ns/ft) = 1/12 ft. = 1.0 in. B-4 • HyperLynx Signal Integrity Analysis: More on High-Speed Design


Notes:


B-5


System Frequency: How Fast is Too Fast? System Frequency: How Fast is Too Fast? ♦ If driver rise/fall time is 20% of the systemclock cycle:

20 %

80 %



Notes:

B-6



The Domain of SI Analysis The Domain of SI Analysis

U2

U1

F u n c t I o n

PCB Trace

Component Pins

F u n c t I o n

Drivers/Receivers



Notes:


B-7


Transmission Line Behavior Transmission Line Behavior ♦ All PCB traces have capacitances, inductances and resistances distributed along their length:

Rn

... l1

l2

Rn = Series resistance per unit length Ln = Inductance per unit length


Ln

RPn

Cn

ln RPn = Parallel resistance per unit length Cn = Capacitance per unit length


Notes:

B-8



Transmission Line Behavior (Cont.) Transmission Line Behavior (Cont.) ♦ Parasitic resistances are usually ignored, since: ●

Series resistance is typically 0.3-0.5 ohms/foot

●

Parallel resistance is very high due to dielectric layer

♦ The characteristic impedance, Z0, is equal to √L/C

Ln

... l1

l2

Total Capacitance C = C1 + C2 … + Cn B-8 • HyperLynx Signal Integrity Analysis: More on High-Speed Design

Cn

ln Total Inductance L = L1 + L2 … + Ln Copyright © 2002 Mentor Graphics Corporation

Notes:


B-9


Characteristic Impedance Characteristic Impedance ♦ Characteristic impedance (Z0) of a line is the impedance the driver sees as it is switching ♦ The characteristic impedance and driver resistance form a voltage divider that determines the incident wavefront RD = 50 Ω 1V

+ -

0V

0.33V Drop

Z0 = 100 Ω

...

0.67V Wavefront

0


I0 = 1V/(50+100) Ω = 6.7mA



Notes:

B-10



Steady State Solution Steady State Solution ♦ The final current is determined only by the driver and load resistances (assuming lossless line)

RD = 50 Ω 1V

+ -

0V

Z0 = 100 Ω

IF = 1V/(50+950) Ω = 1mA

RL = 950 Ω

0


** Remember Remember that that the the series, series, or or DC DC resistance resistance of of aa trace trace is is very very low, low, on on the the order order of of 0.3 0.3 -- 0.5 0.5 Ω Ω // ft. ft.



Notes:


B-11


Impedance Mismatches Impedance Mismatches ♦ In this example the transmission line and the load are mismatched, since the initial and steady state currents are quite different

RD = 50 Ω 1V

+ -

0V

Z0 = 100 Ω

I0 = 1V/150 Ω = 6.67mA

IF = 1V/1000 Ω = 1mA

RL = 950 Ω

0




Notes:

B-12



Reflection Reflection ♦ When the initial wavefront reaches the terminating resistor, most of the voltage is reflected due to the impedance mismatch

1

0.67V, 6.7mA Incident Wave

2

950 Ω will not sink 6.7mA. Most of the wavefront is reflected

Z0 = 100 Ω

3

0.54V Reflected Wave ( +0.67V = 1.21V Potential)


RL = 950 Ω


Notes:


B-13


Reflection Coefficient Reflection Coefficient ♦ The Reflection Coefficient defines how much of the initial wave will be reflected.

1

2

Vi = 0.67V Incident Wave

ρ = (R - Z ) / (R + Z ) L L 0 L 0

= (950 - 100) / (950 + 100) = 850 / 1050 = .8095

Z0 = 100 Ω

Vo = ρL * Vi

3

RL = 950 Ω

= (.8095)(.67) = 0.54V Reflected Wave ( +0.67V = 1.21V Potential)



Notes:

B-14



Reflected Again! Reflected Again! ♦ When the wavefront reaches the driver, it is reflected again due to an impedance mismatch. Note that the reflection coefficient is negative.

1

Vi = 0.54V Wavefront RD = 50 Ω

+ -

Z0 = 100 Ω 3

2

ρ = (R - Z ) / (R + Z ) D D 0 D 0

= (50 - 100) / (50 + 100) = -50 / 150 = -0.333


Vo = ρL * Vi = (-0.333)(.54) = -0.18V Reflected Wave ( +1.21V = 1.03V Potential)


Notes:


B-15


… And So It Goes ... … And So It Goes ... ♦ The wavefront continues to reflect back and forth on the line with decreasing amplitude until the line “settles” to the steady state current and voltage

V = 1.21, 0.88, 0.97, 0.95, ... RD = 50 Ω

Z0 = 100 Ω

+ -

RL = 950 Ω V = 0.67, 1.03, 0.93, 0.96, ...



Notes:

B-16



Ringing Ringing ♦ The settling behavior of mismatched transmission lines is one cause of “ringing” on rising and falling edges

Settling Settling Behavior Behavior of of Transmission Transmission Line Line 1.4 1.4 1.2 1.2

Volts Volts

11 0.8 0.8

VD VD VL VL

0.6 0.6 0.4 0.4 0.2 0.2 00 11

22

33

44

55

66

77

88

99

Time Time (Line (Line Delays) Delays)



Notes:


B-17


Calculating Z and S Calculating Z and S ♦ Simple Microstrip ♦ Impedance rises with H ♦ Impedance lowers with increasing W ♦ Trace Velocity (S) is mainly a function of Dielectric Constant ♦ These Formulae are approximate

Zo =

w t h

Er

87 . h   598 ln    0.8 w + t  Er + 141 .

S = 85 0.475 Er + 0.67 B-17 • HyperLynx Signal Integrity Analysis: More on High-Speed Design


Notes:

B-18



Incident vs. Reflective Switching Incident vs. Reflective Switching ♦ Incident Wave Switching occurs when the initial wavefront is large enough to trigger [and maintain] the receiver

Z0 = 100 Ω

VIH = 0.50 VIL = 0.33

0.67V Wavefront

♦ Reflected Wave Switching occurs when the receiver does not switch on the incident wave



Notes:


B-19


Points to Remember Points to Remember ♦ General behavior of a transmission line is guided by 2 relationships: ●

Driver to Transmission Line

●

Transmission Line to Receiver

♦ A change in the impedance seen by the signal is called a Discontinuity, or Impedance Mismatch ♦ Positive Reflections occur when a signal encounters a discontinuity with higher impedance. ♦ Negative Reflections occur when a signal encounters a discontinuity with lower impedance



Notes:

B-20



Points to Remember (Cont.) Points to Remember (Cont.) ♦ Positive Reflections occur in the direction of the driving edge ● ●

Increase voltages on rising edges and vice versa Can contribute to overshoot and undershoot

♦ Negative Reflections oppose the direction of the driving edge ● ●

Decrease voltages on rising edges and vice versa Can extend the signal’s flight time

♦ Plumbing Analogy ● ●

High Z = Small diameter pipe Low Z = Large diameter pipe



Notes:


B-21


Transmission Line Behavior Summary Transmission Line Behavior Summary

Im p e d a n c e R e la tio n s h ip D r i v e r to L in e L i n e to R e c e i v e r ) < < < = < > = 0 < = 0 = = 0 > > + < > + =

) 0 + 0 + 0


T r a n s m i s s io n L in e B e h avio r G r e a t e r th a n 5 0 % in c id e n t , N e g a t iv e R e f le c ti o n G r e a t e r th a n 5 0 % in c id e n t , N o R e fle c ti o n G r e a t e r th a n 5 0 % in c id e n t , P o s iti v e R e fl e c t io n 5 0 % i n c i d e n t, N e g a ti v e R e fl e c t io n 5 0 % i n c i d e n t, N o R e fl e c t io n 5 0 % i n c i d e n t, P o s it iv e R e fle c ti o n L e s s th a n 5 0 % in c id e n t, N e g a ti v e R e f le c tio n L e s s th a n 5 0 % in c id e n t, N o R e f le c tio n


Notes:

B-22



Causes of Impedance Mismatch Causes of Impedance Mismatch ♦ Differing driver/receiver technologies ●

Example: FCT Driver / CMOS Receiver

+V RH = 25 Ω

Z0 = 55 Ω

RLH = 1M Ω RLL = 1M Ω

RH = 15 Ω



Notes:


B-23


Causes of Impedance Mismatch (Cont.) Causes of Impedance Mismatch (Cont.) ♦ Uncontrolled PCB Impedances ●

Example: PCB with varying trace widths

Z0 = 116 Ω Top Layer Height = 15 mil Width = 5 mil Thick = 1 mil B-23 • HyperLynx Signal Integrity Analysis: More on High-Speed Design

Z0 = 53 Ω First Layer Height = 5 mil Width = 10 mil Thick = 1 mil Copyright © 2002 Mentor Graphics Corporation

Notes:

B-24



Impedance Mismatch Experiment Impedance Mismatch Experiment Z0 = 55 Ω

Z0 = 5 to 105 Ω

4.5

XLINE $1I8:IMPEDANCE

Variable (X-Axis) Maximum Delay (NET)

XTK Results

4

Maximum Delay (NET)

3.5

3

2.5

2

1.5

1

0.5

0 0

20

40

60

80

100

120

XLINE_$1I8:IMPEDANCE



Notes:


B-25


Causes of Impedance Mismatch (Cont.) Causes of Impedance Mismatch (Cont.) ♦ Variable connectivity ●

Example: PCI bus with multiple slots

RD = 50 Ω

RL = 100 Ω

Z0 = 55 Ω

Z0 = 55 Ω


RL = 75 Ω

Z0 = 55 Ω


Notes:

B-26



Other Crosstalk Factors Other Crosstalk Factors ♦ Rate of Magnetic Flux ●

How quickly the magnetic field is changing, determined mostly by driver edge rate

♦ Distance ● ● ●

Coupling increases as distance between conductors decreases Crosstalk increases with conductor height above ground Crosstalk increases with coupling length (but does hit a maximum limit)



Notes:


B-27


Crosstalk Experiment: Edge Rate Crosstalk Experiment: Edge Rate 5ns Edge Rate

1ns Edge Rate

0.25ns Edge Rate



Notes:

B-28



Board Stackup Board Stackup ♦ Coupling occurs in both X and Y directions ● ●

Co-planar: Adjacent traces on same layer Bi-planar: Parallel traces on adjacent layers

♦ Bi-planar coupling can be minimized by making adjacent signal layers orthogonal

Conductor Layers

Dielectric Layers

Ground Plane



Notes:


B-29


Crosstalk Effects Crosstalk Effects ♦ Crosstalk appears as changes in signal voltages ♦ Crosstalk can occur at any point in the cycle ♦ The system noise margin usually defines the maximum allowable level of crosstalk

Switching Signal

VH Affected Signal

VL



Notes:

B-30



What Is A “Bad” Signal? What Is A “Bad” Signal? ♦ Damages a component ♦ Causes system to behave improperly ♦ Violates system budgets (margin) for ● ● ● ●

Signal Integrity (overshoot) Crosstalk Oscillation Delay



Notes:


B-31


System Budget - Example System Budget - Example ♦ In practice, designs have many technologies and many different budgets

5V

High State Overshoot Limit

VH Noise Margin

VL GND


Low State Overshoot Limit


Notes:

B-32



Signal Quality Signal Quality ♦ Assuming the delay is reasonable, is this signal good or bad?

5V VH

VL GND



Notes:


B-33


Points To Remember Points To Remember ♦ PCB signals are subject to transmission line effects whenever the trace length is greater than 1/6 the effective length of the driver’s edge ♦ Transmission line effects can cause unwanted problems like overshoot, ringing and oscillation ♦ Crosstalk occurs between close, parallel traces and degrades noise margin ♦ Whether a signal is “good” or “bad” depends on system margins & requirements



Notes:

B-34



The Technology Paradox The Technology Paradox ♦ High speed signals require fast drivers ● ● ●

Low driver impedances needed to switch state quickly Higher current flow increases overshoot Faster edges increase crosstalk

♦ High speed receivers increase chance of impedance mismatch ●

High input impedances provide minimal loads



Notes:


B-35


Technology Techniques Technology Techniques ♦ Change technology to match driver / line and line / receiver impedances ♦ Use controlled edge-rate drivers ♦ Use devices with integrated termination



Notes:

B-36



Can Edge Rates Be Controlled? Can Edge Rates Be Controlled? ♦ Slower edge rates can result in faster signals ♦ Minimum rates are controlled by cycle time

Cycle Time

Device Prop Delay Rise Time Margin Data Sample

♦ New driver technologies control edge rate ♦ Many devices are not under designer control B-36 • HyperLynx Signal Integrity Analysis: More on High-Speed Design


Notes:


B-37


Topology Topology ♦ Basic ways to connect device pins:

●

Starburst

●

Daisy Chain

●

Combination



Notes:

B-38



Starburst Routing Starburst Routing ♦ ♦ ♦ ♦

Shortens distance for each driver/receiver pair Receivers see signal at (about) the same time Line lengths can be matched to control delays Requires more board space for multiple traces

■ Driver VH

■ Receiver 1 ■ Receiver 2

VL


■ Receiver 3


Notes:


B-39


Starburst Impedance Starburst Impedance ♦ Parallel paths reduce effective trace impedance ●

Driver will see negative reflection from split point

♦ Requires increased driver strength

Z0 Z0

Z0 Z0 ZEFF = Z0/3



Notes:

B-40



Starburst Experiment: Impedance Starburst Experiment: Impedance



Notes:


B-41


Daisy Chain Routing Daisy Chain Routing ♦ ♦ ♦ ♦

Controls trace impedance, requires less space Device placement defines timing relationships Can be terminated with single resistor Receivers see signals at different times

■ Driver VH

■ Receiver 1 ■ Receiver 2

VL


■ Receiver 3


Notes:

B-42



Combination Routing Combination Routing ♦ Provides different tradeoffs of delay and board space

Daisy Mid-driven


Daisy Balanced


Notes:


B-43


Routing Issues Routing Issues ♦ Length matching can be used to minimize skew on critical signals

L1

L2

L3

L4

L1 = L2 = L3 = L4



Notes:

B-44



Routing Issues (Cont.) Routing Issues (Cont.) ♦ Compute allowable coupling per unit of length ♦ Establish maximum parallel length rules ♦ Factors to consider: ● ● ●

Direction of signals affects crosstalk Location of coupling (near driver, near receiver, middle) Load and source resistance

♦ A single Max Parallel rule is not enough

PMax B-44 • HyperLynx Signal Integrity Analysis: More on High-Speed Design


Notes:


B-45


Routing Issues (Cont.) Routing Issues (Cont.) ♦ Critical signals are sometimes restricted to a single layer, sandwiched between power and ground planes

Power Plane Critical Signals

Ground Plane



Notes:

B-46



Termination Termination ♦ Terminators help provide a controlled-impedance path to minimize reflections

Low Impedance Driver

+V High Impedance Receiver

RH = 25 Ω

Z0 = 55 Ω

RLH = 1M Ω RLL = 1M Ω

RL = 15 Ω

RT = 50 Ω Terminating resistor sinks most of the current



Notes:


B-47


Termination Techniques Termination Techniques ♦ Match line impedance at the receiver ● ●

Eliminate/minimize reflections Enable incident wave switching

♦ Match line impedance at the driver ● ●

Useful when receiver load varies Usually prevents incident wave switching



Notes:

B-48



Simple Pullup/Pulldown (Shunt) Simple Pullup/Pulldown (Shunt)

+V

Z0

RT ≈ Z0 RT ≈ Z0

Z0

♦ Advantages ●

Simple and inexpensive

♦ Disadvantages ● ●

DC power drain Decreased Noise Margin



Notes:


B-49


Thevenin Termination Thevenin Termination

+V RTH Z0

(RTH * RTL) (RTH + RTL)

≈ Z0

RTL

♦ Advantages ●

Termination voltage closely controlled

♦ Disadvantages ●

Cost, complexity, DC power drain



Notes:

B-50



AC Termination AC Termination

Z0 RT ≈ Z0 CT based on frequency ♦ Advantages ●

No DC power drain

♦ Disadvantages ● ●

Cost and complexity Works best for periodic signals (e.g. clocks)



Notes:


B-51


Diode Termination Diode Termination +V (GND - 0.7) < VIN < (PWR + 0.7) Z0

♦ Advantages ●

●

Often automatic, since many devices have input protection diodes Very low power consumption


Requires very high diode frequency response to be effective ($$$)



Notes:

B-52



Series Termination Series Termination

VO

RT

Z0

RD

...

RD + RT ≈ Z0

♦ Advantages ●

Works even when loads vary


Incident wave is 1/2 VOH, problematic on long daisy chains

♦ Tradeoffs: ●

RT may improve SI in one direction (ex. High to Low), while degrading the other



Notes:


B-53


Signal Quality Strategies Signal Quality Strategies ♦ Know the signal’s purpose and requirements ♦ Use the 4 T’s to ensure design success ●

Topology – Daisy Chain • Minimize lengths • Re-order pins

– Starburst ● ●

Technology Termination – Shunt – AC Shunt

●

Trace Parameters



Notes:

B-54


Appendix C High-Speed Design Methodologies


C-1

High-Speed Design Methodologies

Real World Consequences Real World Consequences ♦ No single set of design guidelines will adequately cover all cases in modern designs ♦ Forced use of standard “guidelines” will result in over-design, driving up manufacturing cost and complexity ♦ Critical nets and buses must often be designed and analyzed on a case-by-case basis

C-1 • HyperLynx Signal Integrity Analysis: High-Speed Design Methodologies


Notes:

C-2



Using SI Tools Using SI Tools ♦ Pre-Layout ● ● ● ●

Develop Design Constraints Layout Planning and Timing Critical Net Design Solution Space Exploration

♦ Post-Layout ● ●

Design Extraction Design Verification (SI and Timing)



Notes:


C-3


SI Analysis Terminology SI Analysis Terminology ♦ Delay Calculation ●

Determine line delay based on placement, device technology, & stackup

♦ Transmission Line Simulation ●

Accurate analysis of signal behavior based on detailed driver/receiver models and layout information

♦ Crosstalk Analysis ●

Includes effects of EM coupling from other nets

♦ EMC Analysis ●

Simulation of radiation effects of transitioning signals



Notes:

C-4



Signal Integrity Analysis: Traditional Approaches Signal Integrity Analysis: Traditional Approaches

♦ Signal Integrity analysis tools are used post-layout ♦ Problems are not found until late in the design cycle ♦ Problems can be like a “Lump in the Carpet”



Notes:


C-5


Worst Case Analysis: Traditional Approaches Worst Case Analysis: Traditional Approaches

Impedance

♦ Worst Case analysis is limited

Best Case

Worst Case

Driver Strength

♦ Parameters are chosen to model expected extremes of circuit behavior ♦ Separate simulations are performed for “best” and “worst” case conditions



Notes:

C-6



A New Approach: Solution Space Exploration (SSE) A New Approach: Solution Space Exploration (SSE) ♦ Use SI tools early in the design cycle to define workable strategies and drive data to layout Which topology works best?

P1

P2

CS

P3

P4

Which termination schemes minimize fall delay? P1

P2

P3

P4

CS

CS

P1

P2

P3

P4

♦ Toolset must allow user to explore different topologies quickly



Notes:


C-7


Solution Space Exploration Solution Space Exploration ♦ ♦ ♦ ♦ ♦

Define all parameter ranges Define sample topologies for net families Simulate all possible permutations Correlate results Ascertain Critical parameters and safe working ranges



Notes:

C-8



Swept-Variable Analysis Swept-Variable Analysis ♦ ♦ ♦ ♦

Models effects of all manufacturing tolerances Automatically determines worst-case conditions Identifies “unexpected” worst-cases Design tolerances are input as variables

T2=R:1,3,0.5

Delay distribution over manufacturing range

R1=L: X,Y,Z 30 0 30 0 25 0 25 0

D1=L: D,E,F

20 0 20 0 15 0 15 0

T1=R:1,5,1

10 0 10 0

Proposed Topology and Variances


6300 6300

5850 5850

5 400 5 400

4950 4950

4500 4500

4 050 4 050

3600 3600

3150 3150

2700 2700

2 250 2 250

1 800 1 800

1350 1350

0

0

0

0

900 900

T3 =R:1,3,0.5

450 450

50 50

R1=L: A,B,C

Simulation


Notes:


C-9


Solution Space Exploration Example: PCI Bus Solution Space Exploration Example: PCI Bus ♦ ♦ ♦ ♦ ♦ ♦

PCI Bus Z = 45Ω-65Ω S= 1.5 - 2.5 ns/ft Stub length = .2-1.0 inch Inter Length = 2.0 inches Length Multipier = .75-1.25 ♦ Plotting Settled Delay



Notes:

C-10



Layout Planning Layout Planning ♦ SI tools during schematic capture provide “what-if” analysis without requiring a physical design ♦ Develop and refine constraints for CAD

What If?



Notes:


C-11


The New Role of Post-Layout SI Analysis The New Role of Post-Layout SI Analysis ♦ Locate all SI & Crosstalk problems ♦ System level analysis ● ● ●

Multiple boards Cables Connectors

♦ Back-annotate timing ♦ Design Verification



Notes:

C-12



Design for Simulation (DFS) Design for Simulation (DFS) ♦ Understand what your simulation methodology can handle. ♦ Try to avoid design constructs that play to your simulators weaknesses. ♦ If you must design something you can’t simulate well, over design it. ♦ Correlate to measurement whenever feasible.



Notes:


C-13


Recommended Methodology Recommended Methodology ♦ “Full system” approach ● ● ●

●

Define signal quality requirements up-front Control edge rates where needed & possible SSE & Layout Planning identify problem nets and help develop routing/termination strategies Post-layout SI analysis validates topology & termination

♦ Education and Communication between Engineering and CAD departments



Notes:

C-14



High Speed Design Process High Speed Design Process Logic Design Solution Space Exploration

Architecture, Driv/Rec Tech, Timing Budgets, Board Stackup, Termination Sys Constraints...

Layout Planning

Timing, Signal Integrity. Topologies, Termination, Elec Constraints,

Tight integration required here Placement & Analysis

Timing, EMI, Ground Bounce, Signal Integrity, Phys Constraints

Final Place & Route

Final Placement, Routing, Test Points, Manufacturability, Tape out

Post-Layout Verification

Timing, EMI, Ground Bounce, Signal Integrity

High Speed Issues Considered Early and Throughout the Process C-14 • HyperLynx Signal Integrity Analysis: High-Speed Design Methodologies


Notes:


C-15


Analysis Methodology Analysis Methodology

Study: - Technology - Topology - Termination - Trace Parameters

SSE

Develop: - Constraints - Board Params.

Constraints

Schematic

Apply Constraints to Nets Verify Schematic Implementation Refine Constraints

Layout Planning

Constraints

CAD

Board & System Verification C-15 • HyperLynx Signal Integrity Analysis: High-Speed Design Methodologies


Notes:

C-16



Benefits Benefits ♦ Gain greater understanding of transmission line behavior ●

♦ ♦ ♦ ♦ ♦

Applicable to future designs

Fewer iterations through CAD Reduce integration/prototype effort Increased Design Reliability Reduce design cost Reduce Time to Market



Notes:


C-17


Closing Points Closing Points ♦ Physical design is KEY to design success ♦ Understand the variables in the design ● ●

Board parameters Device variances

♦ New design strategies are needed to meet the challenges of 100 MHz + ♦ Solutions can be implemented today ●

SSE, Layout Planning, and swept-variable analysis are production-proven



Notes:

C-18


NOTES:

HyperLynx Signal Integrity Analysis August 2002

Part Number: 069717

HyperLynx Signal Integrity Analysis Student Workbook

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