FSM VHDL

19-Feb-11

Finite State Machines (FSMs) • Any Circuit Circuit with with Memory Memory Is a Finite Finite State State Machine

Finite State Machine Design Using VHDL

– Even computers can be viewed viewed as huge FSMs

• Design Design of of FSMs FSMs Involv Involves es – Defining states – Defining transitions between between states – Optimization / minimization minimization

• Above Approach Approach Is Practica Practicall for Small Small FSMs FSMs Only FSM Design Using VHDL

1

Moore FSM

Mealy FSM

clock reset

Inputs

Next State function Next State


Present State

clock reset

Present State Register

Outputs

Output function FSM Design Using VHDL

state 1 / output 1

2

• Output Output Is a Function Function of of a Present Present State State and Inputs

• Output Output Is a Functio Function n of Present Present State State Only Only Inputs

FSM Design Using VHDL

Present State


Output function 3


Moore Machine

Mealy Machine

transition condition 1

transition condition 1 / output 1

transition condition 2


state 2 / output 2

Outputs 4

state 2

state 1 transition condition 2 / output 2

5


6

1

19-Feb-11

Moore vs. Mealy FSM (1)

Moore vs. Mealy FSM (2)

• Moore and Mealy FSMs Can Be Functionally Equivalent

• Mealy FSM Computes Outputs as soon as Inputs Change

– Equivalent Mealy FSM can be derived from Moore FSM and vice versa

– Mealy FSM responds one clock cycle sooner than equivalent Moore FSM

• Mealy FSM Has Richer Description and Usually Requires Smaller Number of States

• Moore FSM Has No Combinational Path Between Inputs and Outputs – Moore FSM is more likely to have a shorter critical path

– Smaller circuit area FSM Design Using VHDL

7


8

Moore FSM - Example 1

Mealy FSM - Example 1

• Moore FSM that Recognizes Sequence “10”

• Mealy FSM that Recognizes Sequence “10”

0

1 S0 / 0

1

reset Meaning of states:

0/0

0 S1 / 0

1

S2 / 1

S0

0 S0: No elements of the sequence observed

S1: “1” observed

Meaning of states:

9

Moore & Mealy FSMs – Example 1 1

0

0

S0

S1

S2

S0

S0

S0

S1

S0

S0

S0

0/1 S0: No elements of the sequence observed

S1: “1” observed


10

Synchronous Design Summary using VHDL • Draw a state graph and state table • Write VHDL code and implement in EDA software package • Check and simulate your design • Download or fabricate

clock 0

1/0 S1

reset S2: “10” observed


0

input Moore

1/0

Mealy


11


12

2

19-Feb-11

State assignment in VHDL

State assignment in VHDL

• State encoding:

• Binary state encoding

– Binary state encoding – One-hot state encoding

• Example: four states S0,S1,S2,S3 Binary state encoding: 00,01,10,11 One-hot state encoding: 1000,0100,0010,0001 • Binary state encoding: CPLD

• One-hot state encoding

• One-hot state encoding: FPGA, rich resources in registers. FSM Design Using VHDL

13

14

State machine VHDL code

State machine VHDL code

• Two or Three processes for Moore machine:

• TWO processes for Mealy Machine:

– One process is used to model the state registers to decide the next state – Second process models to update the next state – Three process models the output logic – OR 2nd and 3rd combined into one process

– One process is used to model the state registers to decide the next state – Second process models to update the next state and output logic



15


16

0110 Detector Mealy FSM No overlapping

FSM VHDL Design Example

library IEEE; use IEEE.STD_LOGIC_1164.all; entity MEALY0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MEALY0110NV;

• 0110 sequence detector, Mealy machine no pattern overlapping

architecture NOOV of MEALY0110NV is type STATE_TYPE is (IDLE,S0,S01,S011); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK,RST) is begin if (rising_edge(CLK)) then if (RST=‘1’ ) then CS<=IDLE; else CS <= NS; end if; end if;


17

process FSM Design Usingend VHDL

SEQ;

18

3

19-Feb-11

0110 Detector Mealy FSM-No overlapping COM: process (CS,X) is begin Z<=‘0’; case CS is when IDLE => if (X = ‘0') then NS<=S0; else NS<=IDLE; end if; when S0 => if (X = ‘0') then NS<=S0; else NS<=S01; end if;

when S01=> if (X = ‘0') then NS<=S0;

0110 Detector Mealy FSM No overlapping Simulation

else NS<=S011; end if; when S011 => if (X = ‘0') then NS<=IDLE; Z<=‘1’; else NS<=IDLE; end if; end case; end process COM; end architecture NOOV; FSM Design Using VHDL

19


20

0110 Detector Moore FSM No overlapping

0110 detector Moore Machine • 0110 sequence detector, Moore machine no pattern overlapping

library IEEE; use IEEE.STD_LOGIC_1164.all; entity MOORE0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MOORE0110NV;

architecture NOOV of MOORE0110NV is type STATE_TYPE is (IDLE,S0,S01,S011,S0110); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK) is begin if (rising_edge(CLK)) then if (RST=‘1’ ) then CS<=IDLE; else CS <= NS; end if; end if; end process SEQ;


21

0110 Detector Moore FSM No overlapping with two processes COM: process (CS,X) is begin Z<=‘0’; case CS is when IDLE => if (X = ‘0') then NS<=S0; else NS<=IDLE; end if; when S0 => if (X = ‘0') then NS<=S0; else NS<=S01; end if;

when S01=> if (X = ‘0') then


22

0110 Detector Moore FSM No overlapping Simulation

NS<=S0; else NS<=S011; end if; when S011 => if (X = ‘0') then NS<=S0110; else NS<=IDLE; end if; when S0110=> Z<=‘1’; NS<=IDLE; end case; end process COM; endVHDL architecture NOOV; FSM Design Using

23


24

4

19-Feb-11

0110 Detector Moore FSM No overlapping Another VHDL code style

(three processes)

architecture NOOV of MOORE0110NV is

library IEEE; use IEEE.STD_LOGIC_1164.all; entity MOORE0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MOORE0110NV;

type STATE_TYPE is (IDLE,S0,S01,S011,S0110);

if (X = ‘0') then

begin

end if; when S0 => if (X = ‘0') then NS<=S0; else NS<=S01; end if; 25

NS<=IDLE;

No output Z in the COM process

end if; when S0110=> NS<=IDLE; end case; end process COM; FSM Design Using VHDL

26

FSMs in VHDL

OR Z<=‘1’ when CS=S0110 else

• Finite State Machines Can Be Easily Described With Processes • Synthesis Tools Understand FSM Description If Certain Rules Are Followed

‘0’; end architecture NOOV;

3rd process defines the output function

• State transitions should be described in a process sensitive to clock and asynchronous reset signals only • Outputs described as concurrent statements outside the process 27


28

Mealy FSM

process(clock, reset)

process(clock, reset) Inputs

Next State function


Present State

Output function

Outputs



Next State

concurrent statements

if (X = ‘0') then NS<=S0110; else

NS<=IDLE;

Moore FSM

clock reset

end if; when S011 =>

NS<=S0; else

SEQ: process (CLK) is begin if (rising_edge(CLK)) then if (RST=‘1’ ) then CS<=IDLE; else CS <= NS; end if; end if; end process SEQ;


Inputs

else NS<=S011;

when IDLE => if (X = ‘0') then

0110 Detector Moore FSM No overlapping OUTPUTZ: process (CS) is begin case CS is when IDLE|S0|S01|S011=> Z<=‘0’; when S0110=> Z<=‘1’; end case; end process OUTPUTZ; end architecture NOOV;

NS<=S0;

case CS is

signal CS,NS: STATE_TYPE; begin


0110 Detector Moore FSM No overlapping when S01=> COM: process (CS,X) is

clock reset

29


Present State



Outputs

30

5

19-Feb-11

FSM States (1)

FSM States (2)

architecture behavior of FSM is type state is (list of states ); signal FSM_state: state; begin process(clk, reset) begin if reset = ‘1’ then FSM_state <= initial state; elsif (clock = ‘1’ and clock’event) then case FSM_state is

case FSM_state is when state_1 => if transition condition 1 then FSM_state <= state_1; end if; when state_2 => if transition condition 2 then FSM_state <= state_2; end if; end case; end if; end process;


31

• Moore FSM that Recognizes Sequence “10” 1 S0 / 0 reset

1

1

S2 / 1

0


TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state; U_Moore: PROCESS (clock, reset) BEGIN IF(reset = ‘1’) THEN Moore_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF;

0 S1 / 0

32

Moore FSM in VHDL (1)

Moore FSM - Example 1

0


33

Moore FSM in VHDL (2)


34

Mealy FSM - Example 1

WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS;

• Mealy FSM that Recognizes Sequence “10” 0/0

1/0

S0 reset

1/0 S1

0/1

Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’; FSM Design Using VHDL

35


36

6

19-Feb-11

Mealy FSM in VHDL (1)

Mealy FSM in VHDL (2)

TYPE state IS (S0, S1); SIGNAL Mealy_state: state;

WHEN S1 => IF input = ‘0’ THEN Mealy_state <= S0; ELSE Mealy_state <= S1; END IF; END CASE; END IF; END PROCESS;

U_Mealy: PROCESS(clock, reset) BEGIN IF(reset = ‘1’) THEN Mealy_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Mealy_state IS WHEN S0 => IF input = ‘1’ THEN Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;

Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;


37

Moore FSM – Example 2: State diagram


Moore FSM – Example 2: State table

Next state

Present state


A

A

B

0

B

A

C

0

C

A

C

1


40

USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( clock resetn w z END simple ;



z

w = 1

Moore FSM – Example 2: VHDL code (1)

process(clock, reset)

clock resetn

Output

w = 0

39

Moore FSM Input: w

38


Present State: y

Output function

Output: z


: IN STD_LOGIC ; : IN STD_LOGIC ; : IN STD_LOGIC ; : OUT STD_LOGIC ) ;

ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN 41


42

7

19-Feb-11

Moore FSM – Example 2: VHDL code (2) CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; FSM Design Using VHDL

END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ;

43

process (clock, resetn)

Next State function

Next State: y_next clock resetn





44

Alternative VHDL code (1)

Moore FSM process Input: w (w, y_present)

Moore FSM – Example 2: VHDL code (3)

Present State: y_present

Output: z

45

Alternative VHDL code (2)

ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; FSM Design Using VHDL

46

Mealy FSM – Example 2: State diagram

WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (clock, resetn) BEGIN IF resetn = '0' THEN y_present <= A ; ELSIF (clock'EVENT AND clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ; FSM Design Using VHDL

47


48

8

19-Feb-11

Mealy FSM – Example 2: State table

Mealy FSM process(clock, reset) Input: w

Present state

Output z

Next state w = 0

w = 1

w = 0

A

B

0

0

B

A

B

0

1


Next State

w = 1

A

clock resetn

49

Mealy FSM – Example 2: VHDL code (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Mealy IS PORT ( clock : IN resetn : IN w : IN z : OUT END Mealy ;



Present State: y



Output: z

50

Mealy FSM – Example 2: VHDL code (2) CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ;

STD_LOGIC ; STD_LOGIC ; STD_LOGIC ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN

Next State function

51


52

Mealy FSM – Example 2: VHDL code (3) END IF ; END PROCESS ; WITH y SELECT z <= w WHEN B, z <= ‘0’ WHEN others;

Example of a Moore state machine

END Behavior ;


53


54

9

19-Feb-11


55


56

10

FSM VHDL

Recommend Documents