CR-1
:
@FALCON_LIB.FALCON(SCH_1):PAGE1
PAGE CONTENTS [1] [2] [ 3] [ 4] [5] [ 6] [7] [8] [9] [10] [11] [12] [ 1 3] [ 1 4] [ 1 5] [ 1 6] [ 1 7] [18] [19] [20] [21] [22] [23] [24] [25] [26] [ 2 7] [ 2 8] [29] [ 3 0] [ 3 1] [ 3 2]
RULES RULES:: 1 ..)) 2 .) .) 3.) 3.) 4.) 4.) 5.) 5.) 6.) 6.) 7.) 8 .) .) 9 .) .) 1 0. 0. ) 1 2. 2. ) 1 3. 3. ) 1 4. 4.) 15.) 15.)
PAGE
COVER PAGE CLOCK DIAGRAM RESET/ENABLE DIAGRAM CPU, CLOCKS + EEPROM + STRAPPING CPU, FS F SB CPU, FSB POWER + PLL POWER CPU, CORE POWER CPU, POWER CPU, DECOUPLING CPU, DECOUPLING CPU, DECOUPLING GPU, FS FSB GPU, VIDEO + PC P CIEX + EE E EPROM GPU, MEMORY CONTROLLER A + B GPU, MEMORY CONTROLLER C + D GPU, PLL POWER + FSB POWER GPU, CORE PO POWER + MEM POWER GPU, DECOUPLING MEMORY, A (T (TOP) MEMORY, A MI MIRRORED (BOTTOM) MEMORY, B (T (TOP) MEMORY, B MI MIRRORED (BOTTOM) MEMORY, C (TOP) MEMORY, C MI MIRRORED (BOTTOM) MEMORY, D (TOP) MEMORY, D MI MIRRORED (BOTTOM) HANA, CLOCKS + ST STRAPPING HANA, VIDEO + FA F AN + JTAG CONN, HD HDMI HANA, POWER + DECOUPLING HANA, POWER + DECOUPLING POWER TRACE E MI MI CAPS
(APPLI (APPLIED ED
[33 ] [34] [35] [36 ] [37 ] [38 ] [39] [40] [41] [42 ] [43] [44 ] [45 ] [46 ] [47 ] [48 ] [49 ] [50 ] [51 ] [52 ] [53 ] [54 ] [55 ] [56] [57 ] [58 ] [59 ] [60 ] [61 ] [62 ] [63 ] [64 ] [65-6]
SCHEMATIC 1.0
CONTENTS
RE REV
SB, PCIEX + SMM GPIO + JT J TA G SB, SM S MC SB, FLASH + US U SB + SP S PI SB, ETHERNET + AUDIO + SATA SB, STANDBY POWER + DECOUPLE SB, MAIN POWER + DECOUPLE SB OU OUT, ETHERNET SB OUT, AUDIO SB OUT, FLASH SB OU O UT, FAN + INFRARED + BUTTONS CONN, AV AVIP CONN, RJ45 + US U SB CO COMBO CONN, GAME PO PORTS + MEMORY PORTS MISC, V_5P0 DUAL, DEBUG MAPPING CONN, ODD AND HDD CONN, ARGON + POWER VREGS, INPUT + OUTPUT FI FILTERS VREGS, CPU CONTROLLER VREGS, GPU OU OUTPUT PHASE 1,2,3 VREGS, GPU CONTROLLER VREGS, GPU OUTPUT P HA HASE 1 ,2 ,2 VREGS, SWITCHED 1. 1 . 8, 5.0V VREGS, LINEAR REGULATORS XDK, DEBUG CONN DEBUG BO BOARD, CPU + GPU BR BREAKOUT DEBUG BOARD, CPU CO CONN DEBUG BO BOARD, CPU CO C ONN + TERM DEBUG BOARD, CPU TE TERM DEBUG BOARD, TITAN + YE Y ETI CONN DEBUG BO BOARD, GPU CO CONN + TERM XDK, LEDS, BDCM PHY LABELS AND MOUNTING, PCI SWIZ MEM QUAL BOARDS
BOM RELEASE XX/XX/06
DA DATE
FALCON RETAIL REV 1.0 FAB D
PLEA PLEASE SE REFE REFER R TO THE THE XENO XENON N DESIGN DESIGN
BOM RELEAS RELEASE
DATE DATE
SIGNATURE
FALCON_FABD T ue ue
M ay ay 0 8 1 8: 8: 21 21 :4 :4 3
2 00 00 7
XX/XX/06
DATE
PB NUMBER NUM BER
SPEC SPEC
X80XXXX-00X
DRN DRN BY
MICR MICROS OSOF OFT T XB XBOX OX
CHK CHK BY
TITLE
ENGR APVD
DRAWING
PAGE PAGE]]
RE V D
FALCON
WHEN WHEN POSSIB POSSIBLE) LE)
MS B TO TO L SB SB IS TOP TO B OT OTTOM W HE HE N P OS OS SI SI BL BL E: E: IN PU PU TS TS O N LE LE FT FT , O UT UT PU PU TS TS ON R IG IG HT HT ORDE ORDER R OF OF PAGES PAGES=C =CHI HIP P INTE INTERF RFAC ACES ES,, TERM TERMIN INAT ATIO ION, N, POWE POWER, R, DECOU DECOUPL PLIN ING G AVOI AVOID D USIN USING G OFF OFF PAGE PAGE CONN CONNEC ECTO TORS RS FOR FOR ON PAGE PAGE CONN CONNEC ECTI TION ONS S LANE LANED D SIGN SIGNAL ALS S ARE ARE GROU GROUPE PED D ON ON SYMBO SYMBOLS LS TRAN TRANSI SIMI MITT TTER ER NAME NAME USE USED D AS PREF PREFIX IX WITH WITH RX AND AND TX CONN CONNEC ECTI TION ONS S S UF UFFIX V_ IS US ED ED F OR OR V OL OLT AG AGE RA IIL L S IIG GNA L NA ME ME S S UF UF FI FI X _ DP DP A ND ND _ DN DN A RE RE U S ED ED F OR OR D IF IF FE FE RI RI EN EN TA TA L P AI AI RS RS U NN NN AM AM ED ED NE NE TS TS A RE RE N AM AM ED ED W IT IT H / 2 T EX EX T S IZ IZ E S UF UF FI FIX _ N F OR OR A CT CT IV IV E L OW OW OR OR N J UN UN CT CT IO IO N S UF UF FI FIX _ P F O R P J UN UN CT CT IO ION S UF UF FI FIX _ EN EN F OR OR EN EN AB AB LE LE 'CL K' K' F OR OR CL CL OC OC KS KS , 'RS T' T' F OR OR RE RE SE SE TS TS PWRG PWRGD D FOR FOR POWE POWER R GOO GOOD D
[PAG [PAGE_ E_TI TITL TLE= E=CO COVE VER R
PCBA NUMBER X 8 X X X X X -0 0 1
APVD APVD
SCH,
MICROSOFT
CONFIDENTIAL
PBA,
FALCON
PROJEC PROJECT T NAME NAME FALCON_RETAIL
PAGE 1/82
REV 1.0
CR-2
:
@FALCON_LIB.FALCON(SCH_1):PAGE2
AVIP CONN
RJ45/USB CONN
ENET PHY
*
FAN CONN
I2S_MCLK(12.288MHZ) I2S_BCLK(3.072MHZ)
AUDIO DAC
OUT OF O F DATE *
POWER
CONN
ANA_XTAL_IN(27MHZ) NA_XTAL_IN(27MHZ)
GPU GPU VR
DEBUG CONN
ANA BCKUP
SB
IS
CLOC CLOCK K DIAG DIAGRA RAM M
ENET_CLK(25MHZ)
DVD SATA CONN
THIS
ANA GPU GPU VR CNTL
STBY_CLK(48MHZ) SATA_CLK_REF(25MHZ) SATA_CLK_DP/DN(100MHZ) PCIEX_CLK_DP/DN(100MHZ) AUD_CLK(24.576MHZ) UD_CLK(24.576MHZ)
CPU_CLK_DP/DN(100MHZ) GPU_CLK_ GPU_CLK_DP/D DP/DN N
DVD PWR CONN ANA BCKUP
1 P8 P8
MEM CLAM CLAM C+D C+D
MC_CLK1_DP/DN(800MHZ) MC_CLK0_DP/DN(800MHZ) MD_CLK1_DP/DN(800MHZ) MD_CLK0_DP/DN(800MHZ)
CONN
CPU
GPU ) ) ) ) Z Z Z Z H H H H M M M M 0 0 0 0 0 0 0 0 8 ( 8 ( 8 ( 8 ( N N N N D / D / D / D / P P P P D D D D _ _ _ _ 1 0 1 0 K K K K L L L L C C C C _ _ _ _ A A B B M M M M
VR FLSH
HDD CONN
3P3
RISCWATCH
PIX_CLK_OUT_DP/DN(100MHZ) (100MHZ) (100MHZ)
VR VMEM VMEM VR 5P0
MPORT MPORT VR
MEM CLAM CLAM A+B A+B
TITA TITAN N CONN EFUS EFUSE E
CPU VR
JTAG JTAG
VR
CPU CPU VR CNTL
VR
GAME CONN IR
MEM CONN
EJECT SW
DIAG DIAGRA RAM> M>
MEM CONN
BIND SW
ARGON CONN
DRAWING FALCON_FABD T ue ue M ay ay 0 8 1 1: 1: 47 47 :3 :3 2
2 00 00 7
MICROSOFT
CONFIDENTIAL
PROJEC PROJECT T NAME NAME FALCON_RETAIL
PAGE 2/82
REV 1.0
CR-2
:
@FALCON_LIB.FALCON(SCH_1):PAGE2
AVIP CONN
RJ45/USB CONN
ENET PHY
*
FAN CONN
I2S_MCLK(12.288MHZ) I2S_BCLK(3.072MHZ)
AUDIO DAC
OUT OF O F DATE *
POWER
CONN
ANA_XTAL_IN(27MHZ) NA_XTAL_IN(27MHZ)
GPU GPU VR
DEBUG CONN
ANA BCKUP
SB
IS
CLOC CLOCK K DIAG DIAGRA RAM M
ENET_CLK(25MHZ)
DVD SATA CONN
THIS
ANA GPU GPU VR CNTL
STBY_CLK(48MHZ) SATA_CLK_REF(25MHZ) SATA_CLK_DP/DN(100MHZ) PCIEX_CLK_DP/DN(100MHZ) AUD_CLK(24.576MHZ) UD_CLK(24.576MHZ)
CPU_CLK_DP/DN(100MHZ) GPU_CLK_ GPU_CLK_DP/D DP/DN N
DVD PWR CONN ANA BCKUP
1 P8 P8
MEM CLAM CLAM C+D C+D
MC_CLK1_DP/DN(800MHZ) MC_CLK0_DP/DN(800MHZ) MD_CLK1_DP/DN(800MHZ) MD_CLK0_DP/DN(800MHZ)
CONN
CPU
GPU ) ) ) ) Z Z Z Z H H H H M M M M 0 0 0 0 0 0 0 0 8 ( 8 ( 8 ( 8 ( N N N N D / D / D / D / P P P P D D D D _ _ _ _ 1 0 1 0 K K K K L L L L C C C C _ _ _ _ A A B B M M M M
VR FLSH
HDD CONN
3P3
RISCWATCH
PIX_CLK_OUT_DP/DN(100MHZ) (100MHZ) (100MHZ)
VR VMEM VMEM VR 5P0
MPORT MPORT VR
MEM CLAM CLAM A+B A+B
TITA TITAN N CONN EFUS EFUSE E
CPU VR
JTAG JTAG
VR
CPU CPU VR CNTL
VR
GAME CONN IR
MEM CONN
EJECT SW
DIAG DIAGRA RAM> M>
MEM CONN
BIND SW
ARGON CONN
DRAWING FALCON_FABD T ue ue M ay ay 0 8 1 1: 1: 47 47 :3 :3 2
2 00 00 7
MICROSOFT
CONFIDENTIAL
PROJEC PROJECT T NAME NAME FALCON_RETAIL
PAGE 2/82
REV 1.0
CR-3
:
@FALCON_LIB.FALCON(SCH_1):PAGE3
AVIP CONN
RJ45/USB CONN
ENET PHY
ENET_RST_N
N _ N O _ R W P _ T X E
POWER CONN
FAN CONN
RES ESET ET//ENAB ENABL LE AUD_CLAMP AUD_RST_N
AUDIO DAC
PSU_V12P0_EN
GPU GPU VR
HANA_CLK_OE HANA_RST_N
DVD SATA CONN
DIAG AGR RAM
HANA
VREG_GPU_EN_N
SMC_RST_N
N _ T S R _ B S
SB
VREG_GPU_PWRGD EXT_PWR_ON_N CPU_CHECKSTOP_N CPU_RST_N CPU_PWRGD GPU_RST_N
DVD PWR CONN
RISCWATCH
CONN
GPU_RST_DONE
N E _ G B N D E _ _ C 3 M P S 3 _ G E R V
HDD CONN
GPU GPU VR CNTL
D G R W P _ U P C _ G E R V
MEM CLAM CLAM C+D C+D
MEM_RST MEM_SCAN_EN MEM_SCAN_TOP_EN MEM_SCAN_BOT_EN
CONN
GPU
CPU
N N E N E _ _ E P _ T N O O T T A _ B _ S C N N R S A A _ _ C C M M S E E S _ _ M M M M E E M M
3P3 VR
DEBUG
CPU VR
VREG_1P8_EN_N VREG_5P0_EN_N
CPU_PWRGD TITA TITAN N CONN
MEM CLAM CLAM A+B VMEM VMEM VR 5P0
EFUS EFUSE E
JTAG JTAG
VR
CPU CPU VR CNTL
VR
VREG_EFUSE_EN VREG_CPU_EN
GAME CONN IR
EJECT SW
[PAG [PAGE_ E_TI TITL TLE= E=RE RESE SET/ T/EN ENAB ABLE LE
MEM CONN
MEM CONN
DIAG DIAGRA RAM] M]
BIND SW
ARGON CONN
DRAWING FALCON_FABD T ue ue M ay ay 0 8 1 1: 1: 47 47 :3 :3 2
2 00 00 7
MICROSOFT
CONFIDENTIAL
PROJEC PROJECT T NAME NAME FALCON_RETAIL
PAGE 3/82
REV 1.0
CR-6
:
@FALCON_LIB.FALCON(SCH_1):PAGE6
CPU,
FSB POWER + PLL
POWER
V_1P8
V_CPUPLL
V_GPUCORE U7D1
FB7R1
1
2
C7R1
1
2
1K
FB 603
0.2A 0.7DCR
.1UF 10% 6.3V X5R 402
1
2
1
C7R7
.1UF 10% 6.3V X5R 402
1
2
C7R116 .1UF 10% 6.3V X5R 402
1
4 of
.1UF 10% 6.3V X5R 402
2
V_EFUSE
SHORT
2
FB6D1
1
2
C6D1
1
2
1K
FB 603
0.2A 0.7DCR
.1UF 10% 6.3V X5R 402
10K 402
1
1
CPU_VDDE
5% CH
C6D4 V_CPU_CORE_HF_VDDA_PLL V_CPU_CORE_HF_GNDA_PLL
ST6D1 2
V_CPU_CORE_IF_VDDA_PLL V_CPU_CORE_IF_GNDA_PLL
SHORT
V_CPU_FSB_HF_VDDA_PLL V_CPU_FSB_HF_GNDA_PLL
FB6R1
1
2
C6R2
V_CPU_FSB_IF_VDDA_PLL
1
2
1K
FB 603
0.2A 0.7DCR
.1UF 10% 6.3V X5R 402
V_CPU_FSB_IF_GNDA_PLL V_CPU_VDDA_RNG
1
V_CPU_GNDA_RNG
C6R4
VDD_IO VDDE VDDE_SEC
AG17 AF17
CORE_HF_VDDA_PLL CORE_HF_GNDA_PLL
AH17 AH16
CORE_IF_VDDA_PLL CORE_IF_GNDA_PLL
AD20 AE20
FSB_HF_VDDA_PLL FSB_HF_GNDA_PLL
AD18 AE18
FSB_IF_VDDA_PLL FSB_IF_GNDA_PLL
AH11 AG11
VDDA_RNG GNDA_RNG
2.2UF 10% 6.3V X5R 603
2 ST6R1 2
1
AH4 A7 B7
2.2UF 10% 6.3V X5R 603
2 1
R7T2
10
IC
LOKI
C7R114
2.2UF 10% 6.3V X5R 603
2 ST7R1 2
1
C7R115
VDD_FSB0 VDD_FSB1 VDD_FSB2 VDD_FSB3 VDD_FSB4 VDD_FSB5 VDD_FSB6 VDD_FSB7 VDD_FSB8 VDD_FSB9 VDD_FSB10 VDD_FSB11 VDD_FSB12 VDD_FSB13 VDD_FSB14 VDD_FSB15 VDD_FSB16 VDD_FSB17 VDD_FSB18 VDD_FSB19 VDD_FSB20 VDD_FSB21 VDD_FSB22 VDD_FSB23 VDD_FSB24 VDD_FSB25 VDD_FSB26 VDD_FSB27 VDD_FSB28 VDD_FSB29 VDD_FSB30 VDD_FSB31 VDD_FSB32 VDD_FSB33 VDD_FSB34
AA25 AB24 AC25 AD24 AE25 AF24 AG25 AH24 B11 B15 B19 B23 B27 C24 D8 D12 D16 D20 D25 E24 F25 G24 H25 J24 K25 L24 M25 N24 P25 R24 T24 U25 V24 W25 Y24
SHORT
FB6R2
1
2
C6R3
1
2
1K
FB 603
0.2A 0.7DCR
1
.1UF 10% 6.3V X5R 402
2 1
ST6R2 2
C6R5 2.2UF 10% 6.3V X5R 603
X806937-001
SHORT
FB7D1
C7D1
1
2
1K
FB 603
0.2A 0.7DCR
1UF 10% 16V EMPTY 603
1
2 1
ST7D1 2
C7D2 2.2UF 10% 6.3V X5R 603
SHORT
[PAGE_TITLE=CPU,
FSB POWER + PLL
POWER]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :0 9
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 6/82
REV 1.0
CR-7
:
@FALCON_LIB.FALCON(SCH_1):PAGE7
CPU, V_CPUCORE
V_CPUCORE
IC
U7D1 5 of
V_CPUCORE
U7D1
10
6 of
LOKI AA2 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AB1 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AC2 AC4 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AD1 AD3 AD5 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD21 AD23 AE1 AE4
VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47
CORE POWER
10
V_CPUCORE
IC
V_CPUCORE
VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD76 VDD77 VDD78 VDD79 VDD80 VDD81 VDD82 VDD83 VDD84 VDD85 VDD86 VDD87 VDD88 VDD89 VDD90 VDD91 VDD92 VDD93 VDD94 VDD95
AE6 AE8 AE10 AE12 AF4 AF7 AF10 AF13 AG3 AG6 AG9 AG12 G2 G4 G6 G8 G10 G12 G14 G16 G18 G20 G22
K5 K7 K9
K11 K13 K15 K17 K19 K21 K23 L2 L4 L6 L8
L10 L12 L14 L16 L18 L20 L22 M1
H1
M3 M5
H3
M7
H5
M9 M11 M13 M15 M17 M19 M21 M23 N2 N4 N6 N8 N10 N12 N14 N16 N18 N20 N22
H7 H9
H11 H13 H15 H17 H19 H21 H23 J2 J4 J6 J8 J10 J12 J14 J16 J18 J20 J22 K1 K3
P1
P3 P5
VDD96 VDD97 VDD98 VDD99 VDD100 VDD101 VDD102 VDD103 VDD104 VDD105 VDD106 VDD107 VDD108 VDD109 VDD110 VDD111 VDD112 VDD113 VDD114 VDD115 VDD116 VDD117 VDD118 VDD119 VDD120 VDD121 VDD122 VDD123 VDD124 VDD125 VDD126 VDD127 VDD128 VDD129 VDD130 VDD131 VDD132 VDD133 VDD134 VDD135 VDD136 VDD137 VDD138 VDD139 VDD140 VDD141 VDD142 X806937-001
V_CPUVCS
IC
U7D1 7 of
10
LOKI
LOKI VDD143 VDD144 VDD145 VDD146 VDD147 VDD148 VDD149 VDD150 VDD151 VDD152 VDD153 VDD154 VDD155 VDD156 VDD157 VDD158 VDD159 VDD160 VDD161 VDD162 VDD163 VDD164 VDD165 VDD166 VDD167 VDD168 VDD169 VDD170 VDD171 VDD172 VDD173 VDD174 VDD175 VDD176 VDD177 VDD178 VDD179 VDD180 VDD181 VDD182 VDD183 VDD184 VDD185 VDD186 VDD187 VDD188 VDD189
P7
P9 P11 P13 P15 P17 P19 P21 P23 R2 R4 R6 R8 R10 R12 R14 R16 R18 R20 R22 T1
T3 T5 T7
T9 T11 T13 T15 T17 T19 T21 T23 U2 U4 U6 U8 U10 U12 U14 U16 U18 U20 U22
V9 V11 V13 V15 V17 V19 V21 V23 W2 W4 W6 W8 W10 W12 W14 W16 W18 W20 W22 Y1
Y3 Y5 Y7
Y9 Y11 Y13 Y15 Y17 Y19 Y21 Y23
VDD190 VDD191 VDD192 VDD193 VDD194 VDD195 VDD196 VDD197 VDD198 VDD199 VDD200 VDD201 VDD202 VDD203 VDD204 VDD205 VDD206 VDD207 VDD208 VDD209 VDD210 VDD211 VDD212 VDD213 VDD214 VDD215 VDD216 VDD217 VDD218 VDD219 VDD220
VCS0 VCS1 VCS2 VCS3 VCS4 VCS5 VCS6 VCS7 VCS8 VCS9 VCS10 VCS11 VCS12 VCS13 VCS14 VCS15
B1
B3 C1
C2 C3 D1
D3 D4 D5 E2 E4 E6 F1
F3 F5 F7
V1
V3 V5 V7
X806937-001
X806937-001
[PAGE_TITLE=CPU,
CORE POWER]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 0
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 7/82
REV 1.0
CR-9
:
@FALCON_LIB.FALCON(SCH_1):PAGE9
CPU,
V_CPUCORE
1
C7T94
2
4.7UF 10% 6.3V EMPTY 805
1
C7T93
2
4.7UF 10% 6.3V EMPTY 805
1
C7T33
2
4.7UF 10% 6.3V X5R 805
1
C7R2
2
4.7UF 10% 6.3V X5R 805
1
C7E10
C7T32
2
4.7UF 10% 6.3V X5R 805
1
C7R26
2
4.7UF 10% 6.3V X5R 805
1
C7E9
2
4.7UF 10% 6.3V EMPTY 805
1
C7T1
2
4.7UF 10% 6.3V X5R 805
1
C7T6
2
4.7UF 10% 6.3V X5R 805
[PAGE_TITLE=CPU,
DECOUPLING]
C7E6
2
1
C7D12
2
4.7UF 10% 6.3V X5R 805
1
C7D19
1
C7D3
2
4.7UF 10% 6.3V X5R 805
1
2
4.7UF 10% 6.3V EMPTY 805
1
C7E5
2
4.7UF 10% 6.3V X5R 805
1
C7D5
2
4.7UF 10% 6.3V EMPTY 805
C7R121
1
2
4.7UF 10% 6.3V EMPTY 805
1
C7R23
2
4.7UF 10% 6.3V X5R 805
1
C7R24
1
C7R3
2
4.7UF 10% 6.3V X5R 805
2
4.7UF 10% 6.3V X5R 805
1
C7E1
2
4.7UF 10% 6.3V X5R 805 C7R119
2
4.7UF 10% 6.3V EMPTY 805
C7R120
2
4.7UF 10% 6.3V EMPTY 805
1
1
4.7UF 10% 6.3V X5R 805
DECOUPLING
1
2
4.7UF 10% 6.3V EMPTY 805
1
C7R90
2
4.7UF 10% 6.3V X5R 805
1
C7E2
2
4.7UF 10% 6.3V X5R 805
1
C7T83
2
4.7UF 10% 6.3V X5R 805
1
C7D11
2
4.7UF 10% 6.3V X5R 805
1
C7T84
2
4.7UF 10% 6.3V X5R 805
1
C6T1
2
4.7UF 10% 6.3V X5R 805
1
C7R30
2
4.7UF 10% 6.3V X5R 805
1
C7R27
2
4.7UF 10% 6.3V X5R 805
1
C7D8
2
4.7UF 10% 6.3V X5R 805
1
C7D4
2
4.7UF 10% 6.3V X5R 805
1
C7D18
2
4.7UF 10% 6.3V EMPTY 805
1
C7D7
2
4.7UF 10% 6.3V X5R 805
1
C7R91
1
C6R7
2
4.7UF 10% 6.3V X5R 805
1
C6R10
2
4.7UF 10% 6.3V X5R 805
1
C7R28
2
4.7UF 10% 6.3V X5R 805
1
C7R29
2
4.7UF 10% 6.3V X5R 805
1
C7T4
2
4.7UF 10% 6.3V X5R 805
2
4.7UF 10% 6.3V X5R 805
1
C7T5
2
4.7UF 10% 6.3V X5R 805
1
C7R5
2
4.7UF 10% 6.3V X5R 805
1
C7R4
2
4.7UF 10% 6.3V X5R 805
1
C7R25
2
4.7UF 10% 6.3V X5R 805
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 1
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 9/82
REV 1.0
CR-10
:
@FALCON_LIB.FALCON(SCH_1):PAGE10
CPU,
V_CPUCORE
1
C7R49
2
.1UF 10% 6.3V X5R 402
1
C7R44
2
.1UF 10% 6.3V X5R 402
1
C6R29
2
.1UF 10% 6.3V X5R 402
1
C6R28
2
.1UF 10% 6.3V X5R 402
1
C6R17
2
.1UF 10% 6.3V X5R 402
1
C7R76
2
.1UF 10% 6.3V X5R 402
1
C6R39
2
.1UF 10% 6.3V X5R 402
1
C6R42
2
.1UF 10% 6.3V X5R 402
1
C7R67
2
.1UF 10% 6.3V X5R 402
1
C7T3
2
.1UF 10% 6.3V X5R 402
[PAGE_TITLE=CPU,
DECOUPLING]
1
C7T9
2
.1UF 10% 6.3V X5R 402
1
C7R22
2
.1UF 10% 6.3V X5R 402
1
C7R35
2
.1UF 10% 6.3V X5R 402
1
C7R34
2
.1UF 10% 6.3V X5R 402
1
C7R19
2
.1UF 10% 6.3V X5R 402
1
C7R43
2
.1UF 10% 6.3V X5R 402
1
C6R16
2
.1UF 10% 6.3V X5R 402
1
C6R19
2
.1UF 10% 6.3V X5R 402
1
C7R61
2
.1UF 10% 6.3V X5R 402
1
C6R35
2
.1UF 10% 6.3V X5R 402
1
C6R44
2
.1UF 10% 6.3V X5R 402
1
C6R32
2
.1UF 10% 6.3V X5R 402
C7R102
1
2
.1UF 10% 6.3V X5R 402
1
C7R81
2
.1UF 10% 6.3V X5R 402
1
C7R68
2
.1UF 10% 6.3V X5R 402
1
C7R69
2
.1UF 10% 6.3V X5R 402
1
C7R57
2
.1UF 10% 6.3V X5R 402
1
C6R20
2
.1UF 10% 6.3V X5R 402
1
C6R21
2
.1UF 10% 6.3V X5R 402
1
C6T26
2
.1UF 10% 6.3V X5R 402
DECOUPLING
1
C7R52
2
.1UF 10% 6.3V X5R 402
1
C7R51
2
.1UF 10% 6.3V X5R 402
1
C7R50
2
.1UF 10% 6.3V X5R 402
1
C6T6
2
.1UF 10% 6.3V X5R 402
1
C6R36
2
.1UF 10% 6.3V X5R 402
1
C6R23
2
.1UF 10% 6.3V X5R 402
1
C7R58
2
.1UF 10% 6.3V X5R 402
1
C7R59
2
.1UF 10% 6.3V X5R 402
1
C7R60
2
.1UF 10% 6.3V X5R 402
1
C7T2
2
.1UF 10% 6.3V X5R 402
1
C6T10
2
.1UF 10% 6.3V X5R 402
1
C7T22
2
.1UF 10% 6.3V X5R 402
1
C7T27
2
.1UF 10% 6.3V X5R 402
1
C7R48
2
.1UF 10% 6.3V X5R 402
1
C7T51
1
C7T21
2
.1UF 10% 6.3V X5R 402
1
C6T2
2
.1UF 10% 6.3V X5R 402
1
C7T10
2
.1UF 10% 6.3V X5R 402
C7R111
1
2
.1UF 10% 6.3V X5R 402
2
.1UF 10% 6.3V X5R 402
1
C7T37
2
.1UF 10% 6.3V X5R 402
1
C7R89
2
.1UF 10% 6.3V X5R 402
1
C6T25
2
.1UF 10% 6.3V X5R 402
1
C7R99
2
.1UF 10% 6.3V X5R 402
C7R100
1
2
.1UF 10% 6.3V X5R 402
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 1
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 10/82
REV 1.0
CR-11
:
@FALCON_LIB.FALCON(SCH_1):PAGE11
CPU,
DECOUPLING
V_CPUCORE
V_CPUVCS
N:EMPTIES 1
C7R31
2
.1UF 10% 6.3V X5R 402
1
C7T54
2
.1UF 10% 6.3V X5R 402
1
C6T16
2
.1UF 10% 6.3V X5R 402
1
C7R56
2
.1UF 10% 6.3V X5R 402
1
C6R26
2
.1UF 10% 6.3V X5R 402
1
C6T9
2
.1UF 10% 6.3V X5R 402
1
C6T3
2
.1UF 10% 6.3V X5R 402
1
C7R21
2
.1UF 10% 6.3V X5R 402
1
C6R41
2
.1UF 10% 6.3V X5R 402
1
C6R13
2
.1UF 10% 6.3V X5R 402
[PAGE_TITLE=CPU,
1
C7T25
2
.1UF 10% 6.3V X5R 402
1
C6T24
2
.1UF 10% 6.3V X5R 402
1
C6T13
2
.1UF 10% 6.3V X5R 402
1
C7R20
2
.1UF 10% 6.3V X5R 402
1
C7R42
2
.1UF 10% 6.3V X5R 402
1
C7R41
2
.1UF 10% 6.3V X5R 402
1
C7R40
2
.1UF 10% 6.3V X5R 402
1
C7R39
2
.1UF 10% 6.3V X5R 402
1
C6T21
2
.1UF 10% 6.3V X5R 402
1
C6R12
2
.1UF 10% 6.3V X5R 402
DECOUPLING]
1
C7T38
2
.1UF 10% 6.3V X5R 402
C7R110
1
2
.1UF 10% 6.3V X5R 402
1
C6T14
2
.1UF 10% 6.3V X5R 402
1
C7T28
2
.1UF 10% 6.3V X5R 402
1
C7R14
2
.1UF 10% 6.3V X5R 402
1
C7T49
2
.1UF 10% 6.3V X5R 402
1
C6T22
2
.1UF 10% 6.3V X5R 402
1
C7T41
2
.1UF 10% 6.3V X5R 402
1
C7R33
2
.1UF 10% 6.3V X5R 402
1
C7R32
2
.1UF 10% 6.3V X5R 402
1
C7T58
2
.1UF 10% 6.3V X5R 402
1
C6R24
2
.1UF 10% 6.3V X5R 402
1
C7T56
2
.1UF 10% 6.3V X5R 402
1
C7T50
2
.1UF 10% 6.3V X5R 402
C7R106
1
2
.1UF 10% 6.3V X5R 402
1
C7T11
2
.1UF 10% 6.3V X5R 402
1
C7T40
2
.1UF 10% 6.3V X5R 402
1
C7R75
2
.1UF 10% 6.3V X5R 402
1
C7T47
2
.1UF 10% 6.3V X5R 402
1
C7T46
2
.1UF 10% 6.3V X5R 402
1
C6T17
2
.1UF 10% 6.3V X5R 402
1
C7R95
2
.1UF 10% 6.3V X5R 402
1
C6T18
2
.1UF 10% 6.3V X5R 402
C7R101
1
2
.1UF 10% 6.3V X5R 402
1
C7T57
2
.1UF 10% 6.3V X5R 402
1
C7T55
2
.1UF 10% 6.3V X5R 402
1
C7R83
2
.1UF 10% 6.3V X5R 402
1
C7T39
2
.1UF 10% 6.3V X5R 402
1
C7T26
2
.1UF 10% 6.3V X5R 402
1
C7T48
2
.1UF 10% 6.3V X5R 402
1
C7R66
2
.1UF 10% 6.3V EMPTY 402
1
C6T4
2
.1UF 10% 6.3V EMPTY 402
1
C7T15
2
.1UF 10% 6.3V EMPTY 402
1
C7T24
2
.1UF 10% 6.3V EMPTY 402
1
C6T11
2
.1UF 10% 6.3V EMPTY 402
1
C7R74
2
.1UF 10% 6.3V EMPTY 402
1
C6R30
2
.1UF 10% 6.3V EMPTY 402
1
C7R82
2
.1UF 10% 6.3V EMPTY 402
1
C7T23
2
.1UF 10% 6.3V EMPTY 402
1
C7R65
2
.1UF 10% 6.3V EMPTY 402
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 2
1
C7T7
2
.1UF 10% 6.3V X5R 402
1
C7T14
2
.1UF 10% 6.3V X5R 402
1
C7T12
2
.1UF 10% 6.3V X5R 402
1
C7T13
1
C7T29
2
.1UF 10% 6.3V X5R 402
1
C7T30
2
.1UF 10% 6.3V X5R 402
1
C7T31
2
.1UF 10% 6.3V X5R 402
2
.1UF 10% 6.3V X5R 402
1
C7T8
2
.1UF 10% 6.3V X5R 402
1
C7T16
2
.1UF 10% 6.3V X5R 402
1
C7T17
2
.1UF 10% 6.3V X5R 402
1
C7T18
2
.1UF 10% 6.3V X5R 402
1
C7T19
2
.1UF 10% 6.3V X5R 402
1
C7T20
2
.1UF 10% 6.3V X5R 402
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 11/82
REV 1.0
CR-16
:
@FALCON_LIB.FALCON(SCH_1):PAGE16
GPU,
PLL
POWER + FSB POWER
V_GPUCORE FB4D1 2
1
120 0.2A 0 .5 D CR
FB 603
1
C4D6 2.2UF 10% 6.3V X5R 603
2
1
2
C4D5 .1UF 10% 6.3V X5R 402
1
2
C4D4
0.01UF 10% 16V X7R 402
V_GPUCORE V_GPUPCIE
U4D1
G PU Y 2
FB4T1 2
1
120 0.2A 0 .5 D CR
V_PVDDA
FB 603
1
C4T48 2.2UF 10% 6.3V X5R 603
2
1
2
C4T30 .1UF 10% 6.3V X5R 402
C4T37 0.01UF 10% 16V X7R 402
1
C5R7
2
.1UF 10% 6.3V X5R 402
V_PVDDA_MEM
FB4R1 2
1
0 .5
120 0.2A D CR
V_PVDDA_ED
FB 603
1
2
C4R68 2.2UF 10% 6.3V X5R 603
1
2
C4R4 .1UF 10% 6.3V X5R 402
C4R6
0.01UF 10% 16V X7R 402
V_PVDDA_FSB
1
2
C4R8 .1UF 10% 6.3V X5R 402
A20 A21
PVDDA PVSSA
C27 C26
VDD_BSB1 VSS_BSB1
C25 C24
VDD_BSB0 VSS_BSB0
AG10 AG9
PVDDA_MEM PVSSA_MEM
A18 A19
PVDDA_ED PVSSA_ED
B25 B24
PVDDA_PEX PVSSA_PEX
G34 F34
PVDDA_FSB PVSSA_FSB
V_GPUPCIE
IC
8 OF 1 2 V ER SI ON
1 VDD_FSB24 VDD_FSB23 VDD_FSB22 VDD_FSB21 VDD_FSB20 VDD_FSB19 VDD_FSB18 VDD_FSB17 VDD_FSB16 VDD_FSB15 VDD_FSB14 VDD_FSB13 VDD_FSB12 VDD_FSB11 VDD_FSB10 VDD_FSB9 VDD_FSB8 VDD_FSB7 VDD_FSB6 VDD_FSB5 VDD_FSB4 VDD_FSB3 VDD_FSB2 VDD_FSB1 VDD_FSB0
AA27 AB28 AB32 AC27 AD28 AD31 K28 K31 L27 M28 M32 N27 P28 P31 R28 R32 T27 U28 U31 V27 V30 W28 W32 Y28 Y31
X02125-001
1
2
C4R5
C4R7
.1UF 10% 6.3V X5R 402
0.01UF 10% 16V X7R 402
C5R13
C5R15
FB5R1 1
120 0.2A 0 .5 D CR
2
FB 603
1
2
[PAGE_TITLE=GPU,
C5R19 2.2UF 10% 6.3V X5R 603
PLL
1
2
.1UF 10% 6.3V X5R 402
0.01UF 10% 16V X7R 402
POWER + FSB POWER]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 4
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 16/82
REV 1.0
CR-18
:
@FALCON_LIB.FALCON(SCH_1):PAGE18
GPU,
DECOUPLING
V_GPUCORE
V_GPUCORE
V_GPUCORE
N:EMPTIES 1
C4R20
2
.1UF 10% 6.3V X5R 402
1
C4R37
2
.1UF 10% 6.3V X5R 402
1
C4T15
2
.1UF 10% 6.3V X5R 402
1
C4R14
2
.1UF 10% 6.3V X5R 402
1
C4R39
2
.1UF 10% 6.3V X5R 402
1
C4T25
2
.1UF 10% 6.3V X5R 402
1
C4T11
2
.1UF 10% 6.3V X5R 402
1
C4T3
2
C4R49
2
.1UF 10% 6.3V X5R 402
1
C4R18
2
.1UF 10% 6.3V X5R 402
[PAGE_TITLE=GPU,
C4R11
2
.1UF 10% 6.3V X5R 402
1
C4R17
2
.1UF 10% 6.3V X5R 402
1
C4R55
2
.1UF 10% 6.3V X5R 402
1
C4R47
2
.1UF 10% 6.3V X5R 402
1
C4T20
2
.1UF 10% 6.3V X5R 402
1
C4R36
2
.1UF 10% 6.3V X5R 402
1
C4R34
2
.1UF 10% 6.3V X5R 402
1
.1UF 10% 6.3V EMPTY 402
1
1
C4R42
2
.1UF 10% 6.3V X5R 402
1
C4T16
2
.1UF 10% 6.3V X5R 402
1
C4T1
2
.1UF 10% 6.3V X5R 402
DECOUPLING]
1
C4R16
2
.1UF 10% 6.3V X5R 402
1
C4R21
2
.1UF 10% 6.3V X5R 402
1
C4T26
2
.1UF 10% 6.3V X5R 402
1
C4T21
2
.1UF 10% 6.3V X5R 402
1
C4R46
2
.1UF 10% 6.3V X5R 402
1
C4R41
2
.1UF 10% 6.3V X5R 402
1
C4R35
2
.1UF 10% 6.3V X5R 402
2
C4R67
1
.1UF 10% 6.3V X5R 402
1
C4R63
2
.1UF 10% 6.3V X5R 402
1
C4T2
2
.1UF 10% 6.3V X5R 402
1
C4R28
2
.1UF 10% 6.3V X5R 402
1
C4R22
2
.1UF 10% 6.3V X5R 402
1
C4T23
2
.1UF 10% 6.3V X5R 402
1
C4R44
2
.1UF 10% 6.3V X5R 402
1
C4T24
2
.1UF 10% 6.3V X5R 402
1
C4T19
2
.1UF 10% 6.3V X5R 402
1
C4T18
2
.1UF 10% 6.3V X5R 402
1
C4R62
2
.1UF 10% 6.3V X5R 402
1
C4R43
2
.1UF 10% 6.3V X5R 402
1
C5R17
2
.1UF 10% 6.3V X5R 402
1
C4R13
2
.1UF 10% 6.3V X5R 402
1
C5R16
1
2
1
.1UF 10% 6.3V X5R 402
2
C5R10
1
.1UF 10% 6.3V X5R 402
1
C5R12
2
.1UF 10% 6.3V X5R 402
1
C4R24
C4R40
C5R8
1
1
C4R9
1
C5R14
2
1
C5R9
2
.1UF 10% 6.3V X5R 402
2
C4T6
2
C4R57
1
C4R56
1
C4T4
2
2
.1UF 10% 6.3V EMPTY 402
1
C4R58
2
C4T8
2
.1UF 10% 6.3V EMPTY 402
C6E2
C5R5
C5R4
2
C5R20
1
C5R2
C5R1
C6E1
1
2
C5D3
1
4.7UF 10% 6.3V X5R 805
2
C5D4
1
4.7UF 10% 6.3V X5R 805
2
1
C5D6
2
C4R29
1
10UF 20% 6.3V X5R 805
2
C4T17
1
10UF 20% 6.3V X5R 805
2
C4R30
1
10UF 20% 6.3V X5R 805
2
C4R69
1
10UF 20% 6.3V X5R 805
1
4.7UF 10% 6.3V X5R 805
2
4.7UF 10% 6.3V X5R 805
2
2
1
4.7UF 10% 6.3V X5R 805
1
4.7UF 10% 6.3V X5R 805
1
4.7UF 10% 6.3V X5R 805
C6R47
4.7UF 10% 6.3V X5R 805
1
4.7UF 10% 6.3V X5R 805
2
C5D5
1
4.7UF 10% 6.3V X5R 805
1
4.7UF 10% 6.3V X5R 805
2
.1UF 10% 6.3V EMPTY 402
1
2
2
1
4.7UF 10% 6.3V X5R 805
2
2
C5D2
4.7UF 10% 6.3V X5R 805
2
.1UF 10% 6.3V EMPTY 402
2
.1UF 10% 6.3V X5R 402
C4R59
1
2
2
2
.1UF 10% 6.3V EMPTY 402
.1UF 10% 6.3V X5R 402
1
C4T5
.1UF 10% 6.3V EMPTY 402
2
.1UF 10% 6.3V X5R 402
2
.1UF 10% 6.3V EMPTY 402
.1UF 10% 6.3V X5R 402
1
2
.1UF 10% 6.3V EMPTY 402
.1UF 10% 6.3V X5R 402
1
C4R54
.1UF 10% 6.3V EMPTY 402
C5R3
1
4.7UF 10% 6.3V X5R 805
2
C5R11
1
4.7UF 10% 6.3V X5R 805
2
C5R6
1
4.7UF 10% 6.3V X5R 805
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 4
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 18/82
REV 1.0
CR-22
:
@FALCON_LIB.FALCON(SCH_1):PAGE22
MEMORY PARTITION C HI P
S EL EC T = 1 ,
B,
M IR RO R F UN CT IO N
BOTTOM = 1
V_MEM
1
1
R5U2
R5U1
60.4
60.4
1%
2 14
IN
1%
CH
CH 402
402
2
U5U1
IC
GDDR136 MF=1
MB_CLK1_DP
14
IN
13
IN
14
J11 J10
MB_CLK1_DN MEM_RST MB_A<11..0>
IN
V9 11 10
9 8 7
6 5 4 3
2 1
0 14
IN
MB_BA<2..0>
H3 G4 G9
2 1
0
IN IN IN IN IN
MB_CKE MB_WE_N MB_CAS_N MB_RAS_N MB_CS1_N
IN
MEM_SCAN_BOT_EN
12
IN
MEM_SCAN_EN
22
IN IN
MEM_B_VREF0 MEM_B_VREF1
14 14 14 14 14 12
21
L9 K11 M4 K2 L4 K3 H2 K4 M9 K10 H11 K9
H9 H4 F9 H10 F4 A9
CLK_DP CLK_DN
RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N MF
V4
SCAN_EN
H1
VREF1 VREF0
H12
T3 T2 R3 R2 M3 N2 L3 M2 P2 P3 N3
MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2
BI BI BI BI BI BI BI BI
DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2
T10 T11 R10 R11 M10 N11 L10 M11 P11 P10 N10
MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DM3
BI BI BI BI BI BI BI BI
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1
G10 F11 F10 E11 C10 C11 B10 B11 D11 D10 E10
MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_WDQS0 MB_RDQS0 MB_DM0
BI BI BI BI BI BI BI BI
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0
G3 F2 F3 E2 C3 C2 B3 B2 D2 D3 E3
MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_WDQS1 MB_RDQS1 MB_DM1
BI BI BI BI BI BI BI BI
ZQ
A4
RESET A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 A5/A1 A4/A0
V_MEM
V_MEM
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3
14
21
14
21
14
21
14
21
14
21
14
21
14
21
14
21
IN OUT IN
21
V2 M12 M1 V11 F12 F1 A11 A2
VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>
K12 K1
VDDA<1> VDDA<0>
J12 J1
VSSA<1> VSSA<0>
14
14 21
14
21
14
21
14
21
14
21
14 14 14
IN OUT IN
21 21 21 14 21
14
14 14
21
14
21
14
21
14
21
14
21
14
21
14
21
14
21 14
IN OUT IN
21
14
14 14
21
14
21
14
21
14
21
14
21
14 14 14
IN OUT IN
VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>
14
14
IC
U5U1
V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1
21
GDDR136 MF=1 VSSQ<19> VSSQ<18> VSSQ<17> VSSQ<16> VSSQ<15> VSSQ<14> VSSQ<13> VSSQ<12> VSSQ<11> VSSQ<10> VSSQ<9> VSSQ<8> VSSQ<7> VSSQ<6> VSSQ<5> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> VSSQ<0>
T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1
VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>
V3 L12
NC<1> NC<0>
L1
G12 G1 A10 V10 A3 J3 J2
X801995-011
21 21 14 21
14
14
MB_ZQ_BOT
1 1
R4U1
X801995-011
R5F1
243 1%
549 1%
CH
CH
2
2
402
MEM_B_VREF0
OUT
21
402
V_MEM MEMORY B,
22
1
R5F2 1.27K
1% CH
2
402
[PAGE_TITLE=MEMORY
C4U10 .22UF 10% 6.3V X5R 402
C5F1 .1UF 10% 6.3V X5R 402
PARITION
B,
TOP]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 5
2 00 7
C5U4 .22UF 10% 6.3V X5R 402
C4U7 .22UF 10% 6.3V X5R 402
BOTTOM,
C4U4 .22UF 10% 6.3V X5R 402
MICROSOFT
CONFIDENTIAL
DECOUPLING
C4U3 .22UF 10% 6.3V X5R 402
C5U1 .22UF 10% 6.3V X5R 402
C 5U 2
PROJECT NAME FALCON_RETAIL
.22UF 10% 6.3V X5R 402
C 5U 3 .22UF 10% 6.3V X5R 402
PAGE 22/82
REV 1.0
CR-29
:
@FALCON_LIB.FALCON(SCH_1):PAGE29
R2A11 0
5% CH
603
44
NA SM CM2A1 EMPTY 28
28
IN IN
HDMI_TX2_DP
CMCHOKE
1
1 1 1
2
1
HDMI_TX2_DN
1
4
3
ESDB-MLP7 402
1
X801560-001
EG2A2
R2A12 0
1
ESDB-MLP7 402
1
1
EG2A1
DIO
1
DIO
FTP
FT2M2
FTP
FT2M3
FTP
FT2M4
FTP
FT2M5
FTP
FT3M1
FTP
FT3M2
FTP
FT3M3
FTP
FT3M4
IN
V_AVIP 1
C2A9 .1UF 10% 6.3V X5R 402
2
J2A1
5%
603
CH 2
2
HDMI_TX2_DN_CM
3
HDMI_TX1_DP_CM
HDMI_TX0_DN_CM
4 5 6 7 8 9
HDMI_TXC_DP_CM
10
HDMI_TX1_DN_CM HDMI_TX0_DP_CM
R2A13 0
5%
CH
603
11
NA SM CM2A2 EMPTY 28
28
IN IN
HDMI_TX1_DP
1
CMCHOKE
12
HDMI_TXC_DN_CM
1
DB3A1
V_5P0STBY
13
HDMI_CEC
14 15 16
2
17 18
HDMI_TX1_DN
4
1
3
ESDB-MLP7 402
1
X801560-001
EG2A4
R3M5
EG2A3
DIO
DIO
2
CH 2
28 28 44
34
2
34
IN IN
23 22
2K
1%
5%
603
19
R3M6
2K
1%
CH
R2A14 0
ESDB-MLP7 402
1
1
1
CH
402
2
FTP
FT4N2
FTP
FT2N6
402
HDMI_DDC_CLK HDMI_DDC_DATA
1
ME4 ME3 ME2 ME1
21
N I P _ D P H I_ M D H
20
X806395-002
1
44
R3A10 0
CR3M1
5%
CH
603
3
28
28
IN IN
HDMI_TX0_DP HDMI_TX0_DN
1
4
2
BAV99 DIO
ESDB-MLP7 402
EG3M2
3 1
ESDB-MLP7 402
1
EG3A2
R3A11
ESDB-MLP7 402
EG3A1
DIO
1
R3M1 1
BAV99 DIO
HDMI_HPD
OUT
28
CH
DIO
CH
2 EMPTY
PGB0010603 603
EG3M1
47K 5%
ESDB-MLP7 402
EG3M3
EMPTY
X801560-001
0
1
4
1 1
CMCHOKE
2
5%
5 6
NA SM CM3A1 EMPTY
R3M7
10K 402
CR3M1
2
HDR
HDMI TMDS_DATA2_DP TMDS_DATA2_SHD TMDS_DATA2_DN TMDS_DATA1_DP TMDS_DATA1_SHD TMDS_DATA1_DN TMDS_DATA0_DP TMDS_DATA0_SHD TMDS_DATA0_DN TMDS_CLK_DP TMDS_CLK_SHD TMDS_CLK_DN CEC RESERVED SCL SDA DDC_CEC_GND 5VCC HOT_PLUG_DET
1 2
HDMI_TX2_DP_CM
402 2
2 2
DIO
5%
603
CH
2
2
R3A12 0
5% CH
603
NA SM CM3A2 EMPTY 28
IN
HDMI_TXC_DP
1
28
IN
HDMI_TXC_DN
4
CMCHOKE
2
3 1
X801560-001
0
[PAGE_TITLE=CONN,
HDMI]
1
EG3A4
R3A13 603
ESDB-MLP7 402
ESDB-MLP7 402
EG3A3
DIO
DIO
5% CH 2
2
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 6
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 29/82
REV 1.0
CR-30
:
@FALCON_LIB.FALCON(SCH_1):PAGE30
HANA,
POWER + DECOUPLING
V_3P3STBY
FB4N5 2
1
V_HANA_VAA_RTS33S
FB 603
120 0.2A C4N360 .5 DC R 4.7UF 10% 6.3V X5R 805
1
C4N37 4.7UF 10% 6.3V X5R 805
2
C4N35 .1UF 10% 6.3V X5R 402
V_1P8STBY U4C2
IC
3 OF 4 HANA
V_3P3
D12 D11
FB4N8 2
1
C4N15
60 0.5A 0.1DCR
V_HANA_VAA_DAC33M
FB 603
1
4.7UF 10% 6.3V X5R 805
2
C4N24
C4N23 .1UF 10% 6.3V X5R 402
4.7UF 10% 6.3V X5R 805
1
2
C4N29 .1UF 10% 6.3V X5R 402
V_3P3STBY
V_3P3STBY
VAA_DAC33M3 VAA_DAC33M2 VAA_DAC33M1 AVSS_DAC33M1
C7 D7
VAA_DAC33M0 AVSS_DAC33M0
C6
VAA_POR33S
C10
VAA_FAN33S
R3 1
R4N1
100 402
2
V_HANA_VAA_XTAL_33S
5% CH
1
C4N16 .1UF 10% 6.3V X5R 402
2
VAA_RTS33S AVSS_RTS33S
E9 D9 C9 D8
VDDIO33S_STBY_PLL VSSIO33S_STBY_PLL
M6 N6
VDDIO33S_25M_PLL VSSIO33S_25M_PLL
2
C4N25 4.7UF 10% 6.3V X5R 805
1
2
C4N8 4.7UF 10% 6.3V X5R 805
2
.1UF 10% 6.3V X5R 402
P7
N15 P15 R15
VAA_100M_PLL_D AVSS_100M_PLL_D
R12 P12
VDDC_STBY_PLL VSSC_STBY_PLL
N7
VDDC_25M_PLL VSSC_25M_PLL
N5 M5
VDDC_AUD_PLL VSSC_AUD_PLL
N4 P4
VDD_DAC18S VAA_POR18S
M7
V_1P8STBY
E7
1
D6
VDDIO18S_100M_PLL5 VDDIO18S_100M_PLL4 VDDIO18S_100M_PLL3
N14 N13 P11
VDDIO18S_100M_PLL2 VSSIO18S_100M_PLL2
M10 N12
VDDIO18S_100M_PLL1 VSSIO18S_100M_PLL1
N9 N11
VDDIO18S_100M_PLL0 VSSIO18S_100M_PLL0
M9 N10
VDDIO18S_PIX_PLL VSSIO18S_PIX_PLL
L13 L12
1
C3C6
2
4.7UF 10% 6.3V X5R 805
2
C4P13 4.7UF 10% 6.3V X5R 805
1
2
C3N3 4.7UF 10% 6.3V X5R 805
V_1P8STBY
1
C4N18
R7
X802478-003
V_3P3STBY
1
M12 M13
VAA_100M_PLL_A AVSS_100M_PLL_A1 AVSS_100M_PLL_A0
VDDIO33S_AUD_PLL VSSIO33S_AUD_PLL
V_3P3STBY
1
VAA_GP_PLL AVSS_GP_PLL
VAA_XTAL33S
N8 P8
P5 R5
VAA_VID_PLL AVSS_VID_PLL
1
2
C4N19 .1UF 10% 6.3V X5R 402
[PAGE_TITLE=HANA,
1
2
C4N20 .1UF 10% 6.3V X5R 402
1
2
C4N28 .1UF 10% 6.3V X5R 402
1
2
C4P8 .1UF 10% 6.3V X5R 402
1
2
C4N42 .1UF 10% 6.3V X5R 402
POWER + DECOUPLING]
2
C4N31 .1UF 10% 6.3V X5R 402
1
2
C4N17 .1UF 10% 6.3V X5R 402
1
2
C4P5 .1UF 10% 6.3V X5R 402
1
2
C4N34 .1UF 10% 6.3V X5R 402
1
2
C4P6
.1UF 10% 6.3V X5R 402
1
2
C4N27 .1UF 10% 6.3V X5R 402
1
2
C4P11 .1UF 10% 6.3V X5R 402
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 6
1
2
C4P1 .1UF 10% 6.3V X5R 402
2 00 7
1
2
C4P9 .1UF 10% 6.3V X5R 402
1
2
C4N26 .1UF 10% 6.3V X5R 402
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 30/82
REV 1.0
CR-31
:
@FALCON_LIB.FALCON(SCH_1):PAGE31
HANA,
POWER + DECOUPLING
V_3P3STBY U4C2
4
of
IC
4
V_1P8STBY
HANA E13 J4 J3 C3
V_3P3STBY
FB4N6 1
C4N3
120 0.5A 0.2DCR
4.7UF 10% 6.3V X5R 805
F4 E4 F3 G4 G3 C2
V_HANA_VDDIO_33S_AVCC
2
FB 603
1
2
C 4N 6 4.7UF 10% 6.3V X5R 805
1
C 4N 9 .1UF 10% 6.3V X5R 402
2
1
C4N10 .1UF 10% 6.3V X5R 402
C4N14 .1UF 10% 6.3V X5R 402
2
1
C4N13
2
.1UF 10% 6.3V X5R 402
G1 C1
G2 A1
E2 E3 J2
J1
1
C4N5
2
H3
VDDIO_33S_PVDD1
D3
VDDIO_33S_PVCC0
H4 D4
VSSIO_33S_PVSS1 VSSIO_33S_PVSS0
C4N12
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
VSSIO_33S_AVSS8 VSSIO_33S_AVSS7 VSSIO_33S_AVSS6 VDDIO_33S_AVCC5 VDDIO_33S_AVCC4 VDDIO_33S_AVCC3 VDDIO_33S_AVCC2 VDDIO_33S_AVCC1 VDDIO_33S_AVCC0 VSSIO_33S_AVSS5 VSSIO_33S_AVSS4 VSSIO_33S_AVSS3 VSSIO_33S_AVSS2 VSSIO_33S_AVSS1 VSSIO_33S_AVSS0
E1
V_3P3STBY
VDD33S3 VDD33S2 VDD33S1 VDD33S0
V_3P3STBY
FB4N7 1
C4N4 4.7UF 10% 6.3V X5R 805
120 0.2A 0 .5 D CR
V_HANA_VDDIO_33S_PVCC0
2
FB 603
1
2
C4 N7 4.7UF 10% 6.3V X5R 805
C4 N1 1
.1UF 10% 6.3V X5R 402
FB4P1 VDD18S21 VDD18S20 VDD18S19 VDD18S18 VDD18S17 VDD18S16 VDD18S15 VDD18S14 VDD18S13 VDD18S12 VDD18S11 VDD18S10 VDD18S9 VDD18S8 VDD18S7 VDD18S6 VDD18S5 VDD18S4 VDD18S3 VDD18S2 VDD18S1 VDD18S0 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0
L11 K11 G11 J10 H10 J9 H9 M8 L8 K8 G8 F8
2
1
V_HANA_VDD18S
1
2
C4P4 .1UF 10% 6.3V X5R 402
1
FB 603
120 0.5A 0.2DCR
C4P3
1
4.7UF 10% 6.3V X5R 805
2
2
C3P1 4.7UF 10% 6.3V X5R 805
L7 K7
G7 F7 J6 H6 J5 H5 E5 D5
1
2
C4N32 .1UF 10% 6.3V X5R 402
1
2
C4N30 .1UF 10% 6.3V X5R 402
1
2
C4N41 .1UF 10% 6.3V X5R 402
1
2
C4N33 .1UF 10% 6.3V X5R 402
1
2
C4N22 .1UF 10% 6.3V X5R 402
1
2
C4P7 .1UF 10% 6.3V X5R 402
1
2
C4N21 .1UF 10% 6.3V X5R 402
J13 H13 G13 F13 D13 K12 M11 J11 H11 L10 K10 G10 F10 E10 L9 K9 G9 F9 J8 H8 E8 J7 H7
L6 K6 G6 F6 E6 L5 K5 G5 F5 C5 L4 C4 R1
X802478-003
[PAGE_TITLE=HANA,
POWER + DECOUPLING]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 6
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 31/82
REV 1.0
CR-32
:
@FALCON_LIB.FALCON(SCH_1):PAGE32
POWER TRACE DECOUPLING V_12P0
V_12P0
1
C7G2
2
1
10% 0.01UF 16V X7R 402
1
C4N40
C9F2
C3N2
2
10% 0.01UF 16V X7R 402
2
1
10% 0.01UF 16V X7R 402
1
V_5P0STBY
C1N12
2
10% 0.01UF 16V X7R 402
2
1
10% 0.01UF 16V X7R 402
C1C7
2
10% 0.01UF 16V X7R 402
1
C7B1
2
.1UF 10% 6.3V X5R 402
1
C6B1
2
.1UF 10% 6.3V X5R 402
1
C4A1
2
.1UF 10% 6.3V X5R 402
V_3P3STBY
V_5P0DUAL
1
C2F2
2
1
.1UF 10% 6.3V X5R 402
1
C2G1
C3G3
C1C8
2
.1UF 10% 6.3V X5R 402
2
1
.1UF 10% 6.3V X5R 402
1
55
C8G2
2
.1UF 10% 6.3V X5R 402
2
1
.1UF 10% 6.3V X5R 402
C1F1
IN
V_VREG_V1P8V5P0
1
C4F13
2
10% 0.01UF 16V X7R 402
1
C5G1
2
10% 0.01UF 16V X7R 402
2
.1UF 10% 6.3V X5R 402
V_5P0 1
C9E2
2
1
10% 0.01UF 16V X7R 402 1
1
C9C7
2
10% 0.01UF 16V X7R 402
C1C15
2
10% 0.01UF 16V X7R 402
C7N1
2
10% 0.01UF 16V X7R 402
C2T4
1
C5G3
2
1
.1UF 10% 6.3V X5R 402
C1B2
2
.1UF 10% 6.3V X5R 402
1
C1C12
.1UF 10% 6.3V X5R 402 1
1
C1C1
2
.1UF 10% 6.3V X5R 402
1
C1N13
2
.1UF 10% 6.3V X5R 402
1 1
C1D10
2
.1UF 10% 6.3V X5R 402
1
C1G1
2
.1UF 10% 6.3V X5R 402
C6N1
2
1
10% 0.01UF 16V X7R 402
C1B3
2
.1UF 10% 6.3V X5R 402
1
C1F2
2
.1UF 10% 6.3V X5R 402
C5N1
C4N1
C5N2
2
C3N1
2
.1UF 10% 6.3V X5R 402 C7N2
2
.1UF 10% 6.3V X5R 402
2
10% 0.01UF 16V X7R 402
1
2
.1UF 10% 6.3V X5R 402
1
1
C9N1
.1UF 10% 6.3V X5R 402
1 1
2
2
2
.1UF 10% 6.3V X5R 402
C5G5
.1UF 10% 6.3V X5R 402
V_1P8 1
2
.1UF 10% 6.3V X5R 402
1
1
C3U3
2
2
.1UF 10% 6.3V X5R 402
1
1
C5V1
C1D8
.1UF 10% 6.3V X5R 402
2
10% 0.01UF 16V X7R 402
[PAGE_TITLE=POWER
TRACE EMI
CAPS]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 6
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 32/82
REV 1.0
CR-35
:
@FALCON_LIB.FALCON(SCH_1):PAGE35
SB,
FLASH U2C1
58 58 58
42 42
SPI_CLK SPI_MOSI SPI_SS_N
IN IN IN
FLSH_DATA<7..0>
BI
7
6 5 4
FLSH_WP_N
OUT
3
V_3P3STBY
2
2
42
IN
FTP FTP
FT2P20 FT2P21
FTP FTP
1
1
0
5%
2.2K 402
FLSH_READY
FT2P22 FT2P23
R1P7
1 1
USBPORTA3_DP USBPORTA3_DN
1 1
USBPORTA2_DP USBPORTA2_DN
SPI_CLK SPI_MOSI SPI_SS_N*
Y2 AA2 Y3 AA3 AB3 Y4 AA4 AB4
FLSH_DATA7 FLSH_DATA6 FLSH_DATA5 FLSH_DATA4 FLSH_DATA3 FLSH_DATA2 FLSH_DATA1 FLSH_DATA0
46 46
BI BI
GAMEPORT2_DP GAMEPORT2_DN
46 46
BI BI
GAMEPORT1_DP GAMEPORT1_DN
W18 Y18 AA17 AB17 W16 Y16
AA15 AB15 W12
S A I B
3
of
6
SB VERSION
U3 Y5 AA5
Y1 V1
CH
+ USB + SPI IC
106 SPI_MISO
AB5
R1R1
2
SPI_MISO_R
33
1
SPI_MISO
W1
FLSH_CLE
OUT
42
FLSH_CE_N*
V3
FLSH_CE_N
OUT
42
FLSH_RE_N*
V2
FLSH_RE_N
OUT
42
FLSH_WE_N*
W3
FLSH_WE_N
OUT
42
FLSH_ALE
W2
FLSH_ALE
OUT
42
FLSH_CLE
OUT
5% CH
402
FLSH_WP_N* FLSH_READY
USBA_D3_DP USBA_D3_DN
USBB_D4_DP USBB_D4_DN
Y10 W10
ARGONPORT_DP ARGONPORT_DN
BI BI
49 49
USBA_D2_DP USBA_D2_DN
USBB_D3_DP USBB_D3_DN
Y8 W8
MEMPORT1_DP MEMPORT1_DN
BI BI
46 46
USBA_D1_DP USBA_D1_DN
USBB_D2_DP USBB_D2_DN
AB7 AA7
EXPPORT_DP EXPPORT_DN
BI BI
45 45
USBA_D0_DP USBA_D0_DN
USBB_D1_DP USBB_D1_DN
AB9 AA9
MEMPORT2_DP MEMPORT2_DN
BI BI
46 46
USB_RBIAS
USBB_D0_DP USBB_D0_DN
AB11 AA11
MEMPORT3_DP MEMPORT3_DN
BI BI
60 60
58
X02047-012
R _ B S U _ B S
1
1
2
[PAGE_TITLE=SB,
FLASH
R2P14
C2P40 .1UF 10% 6.3V EMPTY 402
+ USB + SPI]
113 1%
CH
2
402
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 7
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 35/82
REV 1.0
CR-36
:
@FALCON_LIB.FALCON(SCH_1):PAGE36
SB,
40
39
IN
R1B9
MII_TX_CLK 33
39
IN
33
MII_TX_CLK_R
U2C1 MII_RX_CLK_R
CH
40 40 40 40
39
40 40
39
39 39 39
39
40 40
39 39
39
27
B3 C3
MII_TX_CLK MII_RX_CLK MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
IN IN IN IN
MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
D1
IN IN
MII_RXDV MII_RXER
C2 B2
MII_RXDV MII_RXER
IN IN BI
MII_COL MII_CRS MII_MDIO
B5 A5
MII_COL MII_CRS MII_MDIO
D2 D3 C1
E1
of
R1C3
MII_MDC_CLK_OUT_R
IC
6
33
MII_MDC_CLK_OUT MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 MII_TXEN
MII_MDC_CLK_OUT
A8
AUD_CLK
E2
B4 C4
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
A3
MII_TXEN
C5 A4
OUT OUT OUT OUT
39 39 39 39
OUT
40 40 40 40 39
40
R2B11 47
R2B14 I2S_MCLK_OUT I2S_BCLK_OUT I2S_SD I2S_WS SPDIF
C7
I2S_MCLK_R
B8
I2S_BCLK_R
A7 B7
I2S_SD_R I2S_WS_R
C6
SPDIF_R
5% CH
402
47
CH
R2B13 47
R2B12
402
5% CH
1
HDD_RX_DP HDD_RX_DN
48 48
IN IN
ODD_RX_DP ODD_RX_DN
SATA1_RX_DP SATA1_RX_DN
SATA1_TX_DP SATA1_TX_DN
R2 P2
HDD_TX_DP HDD_TX_DN
OUT OUT
48 48
1
L3
SATA0_RX_DP SATA0_RX_DN
SATA0_TX_DP SATA0_TX_DN
N1
ODD_TX_DP ODD_TX_DN
OUT OUT
48 48
10K 402
M3
SATA_RBIAS
U2
SATA_RBIAS
M1
1
1
2
[PAGE_TITLE=SB,
ETHERNET
R1C8
C1C9 .1UF 10% 6.3V X5R 402
X02047-012
1%
2
1
CH 402
+ AUDIO
1
41
OUT
28
CH
41
I2S_WS
OUT
28
41
SB_SPDIF_OUT
OUT
28
5% CH
CH
2
5% CH
R2N10 2 5% CH
R1B3
10K 402
+ SATA]
28
I2S_SD
5%
R2N11
10K 402
374
41
OUT
R2N12 2
10K 402 1
OUT
I2S_BCLK
5%
R2B15 2
402
N4 P4
I2S_MCLK
5%
402
47
IN IN
40
CH
402
48 48
39
OUT
5%
402
106
47
AUD_CLK
IN
4
SB VERSION
5%
402
40
+ SATA
CH
R1B10
MII_RX_CLK
+ AUDIO
5%
402
40
ETHERNET
2
5% CH
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 7
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 36/82
REV 1.0
CR-37
:
@FALCON_LIB.FALCON(SCH_1):PAGE37
SB, SB,
STAN STANDB DBY Y POWE POWER R + DECO DECOUP UPLI LING NG U2C1
5
of of
V_1P8STBY
FB2P4 2
1
120 0.2A 0 .5 .5 D CR
C2R5 4.7UF 10% 6.3V X5R 805
V_AVDD_USB V_AVSS_USB
FB 603
1
C2P47 2.2UF 10% 6.3V X5R 603
2 1
ST2P3
2
1
2
C2P43
V_CMPAVDD18_USB
.1UF 10% 6.3V X5R 402
V_CMPAVSS18_USB V_VDD18_USB
SHORT
0 .5 .5
120 0.2A DC R
FB 603
1
2 1
CMPAVDD18_USB CMPAVSS18_USB
V13 V12 V11 V10 V9 V8
VDD18_USB<9> VDD18_USB<8> VDD18_USB<7> VDD18_USB<6> VDD18_USB<5> VDD18_USB<4> VDD18_USB<3> VDD18_USB<2> VDD18_USB<1> VDD18_USB<0>
Y6 W6 V6
2
ST2P2
2
1
C2P46 2.2UF 10% 6.3V X5R 603
2
C2P42 .1UF 10% 6.3V X5R 402
V_CMPAVSS33_USB V_VDD33_USB
SHORT
AVDD_USB AVSS_USB
Y13 W13
V7
FB2P3 1
AB13 AA13
Y14 W14
CMPAVDD33_USB CMPAVSS33_USB
V17 V16 V15 V14
VDD33_USB<3> VDD33_USB<2> VDD33_USB<1> VDD33_USB<0>
FB2R1 2
1
1
2
C2R3
FB 603
120 0.5A 0.2DCR
1
4.7UF 10% 6.3V X5R 805
C2P45 10UF 20% 6.3V X5R 805
2
1
2
V_3P3STBY 37
FB2P5 FB 603
120 0.2A 0 .5 .5 DC R
4.7UF 10% 6.3V X5R 805
1
2 1
.1UF 10% 6.3V X5R 402
1
2
C2P2 .1UF 10% 6.3V X5R 402
1
2
C2P3 .1UF 10% 6.3V X5R 402
V_CMPAVDD33_USB
OUT
106 VDD18_AUX<9> VDD18_AUX<8> VDD18_AUX<7> VDD18_AUX<6> VDD18_AUX<5> VDD18_AUX<4> VDD18_AUX<3> VDD18_AUX<2> VDD18_AUX<1> VDD18_AUX<0>
J18 H18 G18 J15 H15 R14 H14 R12 P12
VDD33_AUX<14> VDD33_AUX<13> VDD33_AUX<12> VDD33_AUX<11> VDD33_AUX<10> VDD33_AUX<9> VDD33_AUX<8> VDD33_AUX<7> VDD33_AUX<6> VDD33_AUX<5> VDD33_AUX<4> VDD33_AUX<3> VDD33_AUX<2> VDD33_AUX<1> VDD33_AUX<0>
V19 D19 V18 F18 E18 E17 D17 E16 E15
VSS_USB<25> VSS_USB<24> VSS_USB<23> VSS_USB<22> VSS_USB<21> VSS_USB<20> VSS_USB<19> VSS_USB<18> VSS_USB<17> VSS_USB<16> VSS_USB<15> VSS_USB<14> VSS_USB<13> VSS_USB<12> VSS_USB<11> VSS_USB<10> VSS_USB<9> VSS_USB<8> VSS_USB<7> VSS_USB<6> VSS_USB<5> VSS_USB<4> VSS_USB<3> VSS_USB<2> VSS_USB<1> VSS_USB<0>
R9
S B B AL AL LS LS V 18 18 AN D V1 V1 9 A RE RE I N TH E LOWE LOWER R RIGHT RIGHT HAND HAND OF THE THE CHIP CHIP THEY THEY HAVE HAVE BEEN BEEN ISOLAT ISOLATED ED FOR BETTER BETTER POWER POWER ROUTIN ROUTING G V_CMPAVDD33_USB
37
IN
V_3P3STBY
W5 V5 U5 W4 V4 U4
Y19 W19 AB18 AA18 Y17 W17 AB16 AA16 Y15 W15 AB14 AA14 AB12 AA12 Y11 W11 AB10 AA10
V_1P8STBY
1
Y9
2
W9
AB8 AA8
C2P38
.1UF 10% 6.3V X5R 402
C2P37 .1UF 10% 6.3V X5R 402
C2P23
C2P24
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
Y7 W7
AB6 AA6
X02047-012
V_3P3STBY
2
1
C2R6
C2P41
V_1P8STBY
IC
6
SB VERSIO VERSION
ST2P4
2
C2P48 2.2UF 10% 6.3V X5R 603
1
2
C2P44 .1UF 10% 6.3V X5R 402
1
2
C2P6
C2N1
.1UF 10% 6.3V X5R 402
.1UF 10% 6.3V X5R 402
C2P5
.1UF 10% 6.3V X5R 402
SHORT
FB2P1 1
C2P8
120 0.2A 0 .5 .5 D CR
4.7UF 10% 6.3V X5R 805
[PA [PAGE_T GE_TIT ITLE LE=S =SB, B,
2
FB 603
1
2
C2P34 2.2UF 10% 6.3V X5R 603
1
2
C2P35 .1UF 10% 6.3V X5R 402
STAN TANDBY DBY POWE POWER R + DECO DECOU UPLIN PLING] G]
DRAWING FALCON_FABD T ue ue M ay ay 0 8 1 8: 8: 24 24 :1 :1 7
2 00 00 7
MICROSOFT
CONFIDENTIAL
PROJEC PROJECT T NAME NAME FALCON_RETAIL
PAGE 37/82
REV 1.0
CR-39
:
@FALCON_LIB.FALCON(SCH_1):PAGE39
N: N:
123.8 123.8 OHM OHM TERM TERMIN INAT ATIO ION N REQU REQUIR IRED ED FOR FOR ICS ICS 100 OHM OHM TER TERMI MINA NATI TION ON REQU REQUIR IRED ED FOR FOR BROADC BROADCOM OM ENET_RX_DP
BI
40 45
1 39
R1A4
V_ENET
IN
61.9 1%
1
R1B7
2
5% CH 402
1
CH 402
1K
27
2
ENET_CLK
IN
IC
U1B2
47 1
33
ENET_RST_N
IN
40 40 40
36
2
36
R1C1
36
10K 5%
40 40 40 40
36
CH
36
402
1
36 36 36
40
IN
39
IN
MII_MDC_CLK_OUT
R1B11
36
36 36
1% CH
1.5K 402 40
1
MII_RX_CLK MII_RXDV MII_RXER
OUT OUT OUT OUT
MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
IN IN IN IN
36 36
2
V_ENET
OUT OUT OUT
OUT IN
36 36
46
ENET_REF_CLK_OUT
28 29
30 31
TXCLK TXEN
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
42
TXD<3> TXD<2> TXD<1> TXD<0>
41 40
39
40 40
MII_COL MII_CRS
OUT OUT
43
ENET_AMDIX_EN
R1N4
2 100 402
V_ENET
2
R1N1
9.53K 402
1
33
MDC MDIO
44 10
AMDIX_EN
20 19
100TCSR 10TCSR
10K 5% CH 402
2
CH 402
1%
CH
13
ENET_RX_DN
BI
40 45
16
ENET_TX_DP
BI
40 45
15
8 6 4
1
R1A1 61.9
3
ENET_P2LI_R
1
L C 1 P _ T E N E
36
25 21
1
D R 4 P _ T E N E
D T 3 P _ T E N E
1
17
11 5 2
10K 5%
10K 5%
ENET_TX_DP_R
CH
1
402
R1M2 ENET_LINK_N
1
CH
2
2
402
0
OUT
ETHERNET ETHERNET
40 45
1
R1N5
2
R1B5 1K
10K 5%
1
CH
CH
402
402
2
ENET_10_100_OUT
5% CH 603 ENET_TX_DN_R
5%
CH
402
2
CH 402
R1B4
2
R1N6 1
1%
45
OUT
1
9
R1N7
10/ 10 100 PI N INDICA INDICATIO TION N
CH 402
TP_BP TP_BN
R1A2 61.9
EMPTY EMPTY FOR BROAD BROADCOM COM STUF STUFF F FOR FOR ICS ICS
AMDIX_EN HAS INTERNAL PULLUP AUTO MDIX IS ON BY DEFAULT
402
1
1%
2
2
2K
1%
1
R1A3
40 45
OUT
12
DB1N3
1.58K
ENET_RX_DN_R
1
61.9
ENET_ACT_N
X800188-002
R1N3
5% CH 603
TP_AP TP_AN
VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>
2
R1N2
2
EMPTY 402
18
ENET_10BIAS
1% CH
1%
10K 5%
ENET_100BIAS
2
332
7
24 22
10/100
COL CRS
2
14
P4RD P3TD P2LI P1CL P0AC
1
5% EMPTY
48 45
VDD<7> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDD<0>
RXD<3> RXD<2> RXD<1> RXD<0>
37 38
26
36
IN
RXCLK RXDV RXER
27
36
39
34 32 35
MII_TX_CLK MII_TXEN
MII_MDIO
BI
RESET_N*
0
STUFF STUFF FOR BROADCOM BROADCOM EMPT EMPTY Y FOR FOR ICS ICS R1B13
1
R1B6
REF_IN REF_OUT
23
R1M1 45
OUT
1
ICS1893BF
DB1N4
ENET_RX_DP_R
ENET_POAC_R
1%
2
I S F OR OR O UT UTP UT UT OF CONNEC CONNECTIO TION N SPEED SPEED
CH 402
ENET_TX_DN
BI
40 45
ADDRESS="000 ADDRESS="00001" 01"
V_3P3 FB1B1 1
60 0.5A
2
0.1DCR 603
1 C1A5 100UF 20% 16V ELEC 2 RDL
[PAG [PAGE_ E_T TITL ITLE=SB E=SB
OUT,
ETH ETHERNET] ET]
V_ENET
2 1
C1B1
10UF 20% 6.3V X5R 805
C1N1
.1UF 10% 6.3V X5R 402
C1N4
.1UF 10% 6.3V X5R 402
C1N5
.1UF 10% 6.3V X5R 402
C1N3 .1UF 10% 6.3V X5R 402
C1N9 .1UF 10% 6.3V X5R 402
C1N11 .1UF 10% 6.3V X5R 402
C1 C 1N2 .1UF 10% 6.3V X5R 402
OUT
39 4 0
45
C1N10 .1UF 10% 6.3V X5R 402
DRAWING FALCON_FABD T ue ue M ay ay 0 8 1 8: 8: 24 24 :1 :1 7
2 00 00 7
MICROSOFT
CONFIDENTIAL
PROJEC PROJECT T NAME NAME FALCON_RETAIL
PAGE 39/82
REV 1.0
CR-40
:
@FALCON_LIB.FALCON(SCH_1):PAGE40
BDCM PHY V_1P8 FB1N1 2
1
2
27
4.7UF 10% 6.3V EMPTY 805
1
DB1N1 IN
V_ENET
33
1
R1B12
2 36
39
OUT
4.7K 5% EMPTY 402
MII_RXD0
36
39
36
39
36
39
36
39
36
39
36
39
36
39 36 36 36 36 36
36 39
36
40
IN
ENET_REF_CLK2_OUT
36
39
36
39
10
RESET_N
OUT OUT OUT
MII_RX_CLK MII_RXDV MII_RXER
20 19 21
RXC RX_DV/TEST0 RX_ER/TEST1
OUT OUT OUT
MII_RXD3 MII_RXD2 MII_RXD1
15 16 17 18
RXD3/ISOLATE RXD2/F100 RXD1/ANEN RXD0/PHYAD0
OUT IN
MII_TX_CLK MII_TXEN
23 24
TXC TX_EN
MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
28
TXD3 TXD2 TXD1 TXD0
27
26 25
OUT OUT
30
31
32
ENET_AVDD
2
DEBUG LEDS,
14 13
29
MII_COL MII_CRS
1
[PAGE_TITLE=XDK,
2
BDCM PHY]
2
OUT
40
C1N14 .1UF 10% 6.3V EMPTY 402
EMPTY BCM5241
ENET_RST_N
MII_MDC_CLK_OUT MII_MDIO
IN
BI
10UF 20% 6.3V EMPTY 805
1
XTALI2 XTALO2
IN
IN IN IN IN
C1N7
2
U1B1 1
39
1
C1N8
ENET_CLK
IN
ENET_AVDD
1
EMPTY 603
60 0.5A 0.1DCR
MDC_CLK_OUT MDIO
OVDD2 OVDD1 AVDD LINK# ACT#
22
V_ENET
IN
39
ENET_AVDD
IN
40
9 7
12
ENET_LINK_N ENET_ACT_N
OUT OUT
39
4
ENET_RX_DP ENET_RX_DN
OUT OUT
39
RDP RDN
6 5
ENET_TX_DP ENET_TX_DN
OUT OUT
39
RDAC
8
TDP TDN
GND
11 3
39
39
39
45 45 45 45 45 45
C A D R _ T E N E
33
COL/ENERGYDET CRS/LOWPWR0 1
REGVDDIN REGVDDOUT
R1N8 1.27K
C1N6
.1UF 10% 6.3V EMPTY 402
1%
X801554-002
LCC32
2
EMPTY 402
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :2 0
MICROSOFT 2 00 7
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 40/82
REV 1.0
CR-41
:
@FALCON_LIB.FALCON(SCH_1):PAGE41
V_12P0
1
1
R2B6 0
603
R2B1 0
1
FTP
FT2N1
2
C2A7
2
4.7UF 10% 16V X5R 1206
AUD_VDD
5% CH
1
2
C2B11 4.7UF 10% 6.3V X5R 805
FT2M1
1
C2B5
2
10UF
402
AUD_AC_R
1
FB2B2 2
1
AUD_CLAMP_R
1K
5% CH
0.7DCR 603
0.2A
2
C2B7
R2B5
0.1UF 10% 25V X7R 603
1
10K 5% CH
.1UF 10% 6.3V X5R 402
1
PGB0010603 603 EG2B2 X801161-001 EMPTY
1
IC
U2B1
1K
2
20% 16V TANT 1206
AUD_VAA
5% CH
603
FTP
R2B3
2
C2B10
1
V_3P3
402
2 1
C2B3
470PF 5% 50V X7R 402
XDAC
IN IN IN IN
36 36
FT2N2
FTP
36
1
36
I2S_MCLK I2S_BCLK I2S_SD I2S_WS
2
14
DVDD
13
MCLK BCLK SD WS
4 3
2 5
33
IN
AUD_RST_N
NC PDN DVREF
12
11
AUD_DCAP
1
R2N3 1K
5% CH
2
402
C2B1 10UF 20% 6.3V X5R 805
C2B6
.1UF 10% 6.3V X5R 402
1
AVDD
9
VOUTR VOUTL
6
AUD_VOUTR
10
AUD_VOUTL
AVREF
8
AGND
AUD_R_OUT
OUT
44
AUD_L_OUT
OUT
44
AUD_ACAP
7
C 2B 4 .1UF 10% 6.3V X5R 402
DGND
X02238-003
C 2B 8 10UF 20% 6.3V X5R 805
PGB0010603 603 EG2B1 X801161-001 EMPTY
1
2
R2B4 10K 5%
2
CH 2
1
402 1
C2B2
470PF 5% 50V X7R 402
C2B9 1
10UF
2
AUD_AC_L
20% 16V TANT 1206
R2B2
2 1K
402
FT2P1
1
FTP
1
FB2B1 0.2A
CR2M2
34
AUD_CLAMP
IN
2
3
AUD_CLAMP_C
Q2N1 1
V_3P3STBY 1
MMBT3906 XSTR
R2N23 2
4.7K 402
5% CH
1K
402
1
AUD_CLAMP_B2
0.7DCR 603
1K
MBT3904
R2N2
2
2
1
AUD_CLAMP_L
5% CH
3
6
5
2
AUD_CLAMP_B3
R2N1
2 1K
5% CH
4
1
402
XSTR
1
5% CH
AUD_CLAMP_B1
1
R2N22 1K
5% CH
2
[PAGE_TITLE=SB
OUT,
AUDIO]
402
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 7
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 41/82
REV 1.0
CR-42
1 A T A D0 _ H 1 S L F
:
@FALCON_LIB.FALCON(SCH_1):PAGE42
N: N:
FLSH_DATA0 0 1
8MB
16MB
32MB
64MB
RETAIL=16MB XDK=64MB
V_3P3STBY
1
1
FT1R3 FT1R4 FT1R5 FT2R3 FT2R4 FT2R5 FT2R6 FT2R7 35
IN
FTP FTP FTP FTP FTP FTP FTP FTP
10K 5%
1 1 1 1 1 1 1 1
FLSH_DATA<7..0>
CH
2
402
2
N: N:
1
R2D6
R2D7
10K 5% CH 402
1
R1E2 10K 5% CH
402
2
2
1
C2E6 4.7UF 10% 6.3V X5R 805
2
1
C2E5
.1UF 10% 6.3V X5R 402
2
C2R11 .1UF 10% 6.3V X5R 402
STUFFED AT CONFIG LEVEL UPDATE TO RECENT PART NO#
U2E1
IC
NAND FLASH RDY
1
37 FTP
FT1T1
12
7
44
6 5 4
43
3 1
32 31 30
0
29
42 41
2
35 35
1
1
R2D8
2
10K 5% EMPTY 402
1
R2D5
2
10K 5% EMPTY 402
1
R2D4
R2D3
10K 5% CH
2
402
1
2
10K 5% CH 402
1
R2D1
2
10K 5% CH 402
1
R1D4
R1D3
CH
CH
402
402
10K 5%
2
1
R1D2
10K 5%
2
35
2
10K 5% CH 402
35 35 35
IN IN IN IN IN IN
FLSH_CE_N FLSH_RE_N FLSH_WE_N FLSH_WP_N FLSH_ALE FLSH_CLE
9 8 18 19
17 16
6 36 13
NC<27> NC<26> NC<25> NC<24> NC<23> NC<22> NC<21> NC<20> NC<19> NC<18> NC<17> NC<16> NC<15> NC<14> NC<13> NC<12> NC<11> NC<10> NC<9> NC<8> NC<7> NC<6> NC<5> NC<4> NC<3> NC<2> NC<1> NC<0>
VCC1 VCC0 DATA<7> DATA<6> DATA<5> DATA<4> DATA<3> DATA<2> DATA<1> DATA<0> CE_N* RE_N* WE_N* WP_N* ALE CLE VSS/NC VSS1 VSS0
X802184-001
[PAGE_TITLE=SB
OUT,
FLASH]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 7
FLSH_READY
7 38
FLSH_NC38
R2D2
2
48
0
47
402
OUT
35
1
5% EMPTY
46 45 40 39 35 34 33
28 27
26 25 24 23 22 21
20 15 14
11 10
5 4 3
2 1
TSOP
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 42/82
REV 1.0
CR-43
:
@FALCON_LIB.FALCON(SCH_1):PAGE43
V_3P3STBY BINDING
BUTTON
FAN CONTROL 1
TH
V_12P0 R5V3
SWITCH
SW5G1 THR
2
4
1
3
2
10K 5% CH 402
R5V2
2
BINDSW_N_R
10K 402
1
OUT
FAN1_Q1_C
34
CH
IN
FAN1_OUT
1
2
2
TH
1
R1G4
SW1G1 THR
2
Q3M1
MJD210 XSTR
1
10K 5% CH 402
3
Q3M2
V_3P3STBY
SWITCH
1
3
28
BUTTON
1
1% CH
2
BINDSW_N
5%
X02246-002
ODD EJECT
R3M9
2 5.11K 402
3
MMBT2222 XSTR
E _ 1 Q _ 1 N A F
C4P14 2700PF 10% 50V X7R 402
1
J3A2 1X3HDR
2
1 2
V_FAN1
R3M8 100 5%
1
3
2
R1G3
2
EJECTSW_N_R
10K 402
1
EJECTSW_N
5%
34
OUT
48
CH
X02246-002
R _ K B D F _ 1 N A F
1
3
C3A9 1UF 10% 16V X7R 603
CH
4
D3A1 1N4148 SOT23 DIO
402
1
R3A7
CONN
30.1K
1% CH
R4P2
2
1
2
402
FAN1_FDBK
1% CH
5.11K 402
OUT
28
R2V1
2
1
V_3P3STBY
R3A2 11K 1% CH
1
T IL T
S WI TC H,
A LP S
EMPTY SW2G1 SM
2
4
1
3
2
TILTSW_N_R
2
R2G2 10K 5% CH 402
2 10K 402
X800550-003
402
R2G3
1
TILTSW_N
5%
OUT
34
CH
IR TILT
SWITCH,
SOLICO
SM SW2G2 SM
4
1
3
2
MODULE V_3P3STBY
N : X 80 05 50 -0 03 H OL DS A LL T HR EE T I LT S WI TC HE S TMEC ONLY HAS 3 PINS WHICH REQUIRES A DIFFERENT UNIQUE PART NUMBER TO HOLD THE SYMBOL NAME N : B OM MU ST C AL L O UT X 80 05 50 -0 03 W IT H Q TY 1 A ND LIST ALL THREE REF DES. FACTORY CHOOSES FROM THERE
V_IR
C2V1 4.7UF 10% 6.3V X5R 805
X800550-003 U1G1
IC
1
2
1
49.9 402
1%
CH
C2V2
2
R2N7
.1UF 10% 6.3V X5R 402
10K 5% CH
1
402
IR
T IL T EMPTY
S WI TC H,
VCC DATA GND ME2 ME1
T ME C
SW2G3
3 1
IR_DATA
2 5 4
OUT
34
X803473-002
TH
1 3
2
X813350-001
[PAGE_TITLE=CONN,
FAN + INFRARED
+ SWITCHES]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 8
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 43/82
REV 1.0
CR-44
:
1
VID_DACA_DP
IN
28
@FALCON_LIB.FALCON(SCH_1):PAGE44
9 O I 3 9 6 D V 3 A T B O S
6
2 A 3 R C
V_3P3
1
R3A4
1
75 1%
CH
2
402
2
2
L3A3
.27UH 0.45A NA
1
2
VID_DACA_OUT
1 1
C3A6 62PF 5% 50V NPO 402
2
75PF 5% 50V NPO 402
28
1
VID_DACB_DP 3
2 A 3 R C
V_3P3
9 O 3 I 9 6 D V 3 A T B O S
.27UH 0.45A NA
1
R3A3 75 1%
1
402
2
S 3 9 2 9 T V O I O A D S B
22PF 5% 50V NPO 402
THRMSTR 1206
1
VID_DACC_DP
IN
V_3P3
1 A 3 R C
R3A6 75
1
CH 402
2
1
2
1
44
OUT
1
2
8 A 2 R
C3A1 75PF 5% 50V NPO 402
2
33
33
1
WSS_CNTL1
IN
R2A6
WSS_CNTL0
IN
1
R2A7
1
CR2A1
28
IN
3
V_3P3
1 A 3 R C 5
9 1 O I 3 9 6 D V 3 A T B O S
R3A9 75
2
CH 402
1
.27UH 0.45A NA
5 4
2
44 1
IND 1210
2
C3A7
1%
62PF 5% 50V NPO 402
1
4
IN
1
VID_VSYNC_OUT_R
R3M3 2
49.9 402
33
44
OUT
SCART_RGB
IN
2
5
4
9 O 3 I 9 6 D V 3 A T B O S
28
IN
1
VID_HSYNC_OUT_R
49.9 402 9 O I 9 D V A B
6
V_3P3STBY
2 M 3 R C 2
[PAGE_TITLE=[CONN,
AVIP]
1
1% CH
R
R
C
N/A
N/A
PB
PB
D
CVBS(COMP)
C VB S( CO MP )
C VB S
N/A
HDTV
VGA
B
B
CVBS
CVBS
VID_DACB_OUT VID_DACB_RET
IN
VID_DACC_OUT VID_DACC_RET
7
44
IN
VID_DACD_OUT
44
IN
VID_HSYNC_OUT
11 9
VID_HSYNC_OUT VID_HSYNC_RET
44
IN
VID_VSYNC_OUT
12 10
VID_VSYNC_OUT VID_VSYNC_RET
25
SPDIF
IN
AUD_R_OUT
15 13
AUD_R_OUT AUD_R_RET
41
IN
AUD_L_OUT
16 14
AUD_L_OUT AUD_L_RET
1
17
R2A5
2 402
H % 5 C
2 1 0 0 3
2 K 0 0 1
WSS_CNTL_OUT
1
2
C2A8
1
4
1
3
OUT
44
H %
C 0 5 1 M 2 R 2
2 K 0 0 1 4
58
34
44
BI
28 28
34
29 29
28 24 20
AV_MODE2 AV_MODE1 AV_MODE0
BI
OUT OUT OUT
34 34 34
34
44 44 44
34 33 32
31
MTGB<8-1> MTGA<8-1>
TH
1
44 44 44 44
IN IN IN IN
EXT_PWR_ON_N AV_MODE2 AV_MODE1 AV_MODE0
5% CH
2
1
R2M9 2
402
1
2
1
2
C2M4
0.01UF 10% 16V X7R 402
10K 5% CH 402
C2A3
470PF 5% 50V X7R 402
2
1
2
LAYOUT:PLACE
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 8
MICROSOFT 2 00 7
CONFIDENTIAL
1
R2M6
R2A1
58
33
VID_HSYNC_OUT
OUT
HDMI_DDC_CLK HDMI_DDC_DATA
18
SHIELD<3> SHIELD<2> SHIELD<1> SHIELD<0>
1
MMBT3906 XSTR
1
EXT_PWR_ON_N
23
V_3P3STBY
Q2N3
CH
30 21
26 22
GND<2> GND<1> GND<0>
T U O _ B G R _ T R A C S
2
SCART_RGB_R
AV_MODE2 AV_MODE1 AV_MODE0
X806743-001
75PF 5% 50V NPO 402
1
5%
DDC_CLK DDC_DATA
CH
4 A 2 R
4
EXT_PWR_ON
WSS_CNTL SCART_RGB
19
5%
CONNECTOR
VID_DACD_OUT VID_DACD_RET
5
41
2
H % 1 C
CONN
XENON AVIP V_AVIP V_AVIP_RET
8 6
WSS_CNTL_OUT_R
R2N19
10K 402
R3M2 2
PR
VID_DACC_OUT
SCART_RGB_OUT_R
2 M 3 R C
PR
VID_DACA_OUT VID_DACA_RET
XSTR
1
3
V_3P3STBY
C(CHROMA)
3 1
75PF 5% 50V NPO 402
VID_VSYNC_OUT
N/A
VID_DACB_OUT
C3A8
1% CH
B
IN
V_3P3
28
G
44
2
9 A 2 R
OUT
G
4 2
2
L3A4 VID_DACD_OUT
Y
VID_DACA_OUT
1K
2
Y
IN
6
3
MBT3904
2
1
470PF 5% 50V X7R 402
WSS_CNTL_B
WSS_CNTL_E
VID_DACD_DP
Y(LUMA)
44
K 2 2 0 8 4 .
1% CH
4.75K 402
H % 1 C
2
1% CH
5.36K 402
N/A
J3A1
75PF 5% 50V NPO 402
IND 1210
62PF 5% 50V NPO 402
4.7UF 10% 6.3V X5R 805
29 27
VID_DACC_OUT
C3A4
1%
2
2
.27UH 0.45A NA
9 O I 3 9 6 D V 1 3 A T B O S
6
C2A1
C3A2
44
28
C2M5
1
V_12P0
L3A1
1
V_3P3
2
ADVANCED
SCART
STANDARD
A
1 A 2 D 2
1
SDTV
DAC
3
44
OUT
IND 1210
62PF 5% 50V NPO 402
2
4
C2A6
29
V_AVIP
2
VID_DACB_OUT
C3A5
CH
2
5
L3A2
2
HANA_SPDIF_OUT
IN
2 IN
RT2M1
1.1A 0.21DCR
C3A3
1
28
OUT
V_5P0
44
OUT
IND 1210
10K 5% CH 402
C2M3 470PF 5% 50V X7R 402
1
R2M4
2
1
2
10K 5% CH 402
C2M2 470PF 5% 50V X7R 402
R2N20
2
1
2
10K 5% CH 402
C2N3
470PF 5% 50V X7R 402
CLOSE TO CONNECTOR EMI CAPS PROJECT NAME FALCON_RETAIL
PAGE 44/82
REV 1.0
CR-45
:
@FALCON_LIB.FALCON(SCH_1):PAGE45
V_5P0DUAL RT1B1 45
2
V_EXPPORT
IN
D1A2
R1B2 0
L1B1 35
35
BI BI
EXPPORT_DN
1
EXPPORT_DP
4
THRMSTR 1206
3
CH
BAV99 SOT23S DIO
2
1
C1A3
470PF 5% 50V X7R 402
2 1
1
C1M2 4.7UF 10% 6.3V X5R 805
FTP
OUT
45
FT1N2
EXPPORT_DN_CM
3
EXPPORT_DP_CM
D1A1
X801560-001
2
PGB0010603 603
1
R1B1
1
EG1A2
3
0
2
1
NA SM EMPTY
CMCHOKE
603
1 C2A4 220UF 20% 10V ELEC 2 RDL
2
5%
603
V_EXPPORT
1
1.1A 0.21DCR
EG1A1
EMPTY
1
PGB0010603 603
EMPTY
5% CH
BAV99 SOT23S DIO
2
2
J1A1
IN
13
ARGON_NTX
14
D1B1 45
IN
V_EXPPORT
15
2
C1A4
2 3
470PF 5% 50V X7R 402
1
16 39
40
1
IN
V_ENET
39 39
BAV99 SOT23S DIO 39
CONN
XENON RJ45/USB 12
40 1
R1M3 2 0
402 1
5% EMPTY
R1A5 0
402
2
5% EMPTY
39
VBUS DD+ GND OMNI
IN IN
ENET_P2LI_R ENET_LINK_N
1 2
LED_LEFT_A LED_LEFT_C
IN IN
ENET_POAC_R
3
ENET_ACT_N
4
LED_RIGHT_A LED_RIGHT_C
11
ENET_TX_CT
10
40
39
IN
ENET_TX_DP
40
39
IN
ENET_TX_DN
7
40
39
IN
ENET_RX_DP
40
39
IN
ENET_RX_DN
9 6 5
XFMER1_P XFMER1_C XFMER1_N
8
CAP
ENET_RX_CT
C1M1 .1UF 10% 6.3V X5R 402
C1A2
.1UF 10% 6.3V X5R 402
20 19 18 21 17
COMBO
XFMER2_P XFMER2_C XFMER2_N
EMI4 EMI3 EMI2 EMI1 ME1
X806148-001
[PAGE_TITLE=CONN,
RJ45
+ USB COMBO]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 8
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 45/82
REV 1.0
CR-46
:
@FALCON_LIB.FALCON(SCH_1):PAGE46
V_MEMPORT1
RT2G1
RT8G1 1
1.1A 0.21DCR
V_GAMEPORT2
THRMSTR 2 1206
1
2
1 C9G2 220UF 20% 10V 2 ELEC RDL
C9G5 4.7UF 10% 6.3V X5R 805
1
470PF 5% 50V X7R 402
PGB0010603 603
35
35
BI BI
CH
1
NA SM EMPTY
1
BI
MEMPORT2_DP
4
2
4.7UF 10% 6.3V X5R 805
MEMPORT2_DN_CM
2
V_5P0DUAL
2 3
GAMEPORT1_DN_CM
5 6
GAMEPORT1_DP_CM
7
1
220UF 20% 10V ELEC RDL
2
11
2
C9G3
C9G4
ME1 ME2
12
470PF 5% 50V X7R 402
1
EG4G1
J4G2 1
X800245-003
GND VBUS DD+ GND
2
3
2
4 5 6
GND VBUS DD+ GND
7
1 C2G2 220UF 20% 10V 2 ELEC RDL
R3G4 0
35
35
BI
MEMPORT1_DN
1
BI
MEMPORT1_DP
4
1
C3V5
8 9
2
10
C2G3
470PF 5% 50V 1 X7R 402
4.7UF 10% 6.3V X5R 805
14 13 12
CH
15 16 17 18
NA SM EMPTY
CMCHOKE
EMI4 EMI3 EMI2 EMI1
11
5%
603
L2G1
2
2
MEMPORT1_DN_CM
3
MEMPORT1_DP_CM
ME4 ME3 ME2 ME1 MTGA<8-1> MTGB<8-1> MTGC<8-1> X800059-001
X801560-001 1
R2G5
2
R9V2 0
603
1
L9V1 35
BI
GAMEPORT1_DN
4
1
3
0
PGB0010603 603
BI
2
1
X801560-001
PGB0010603 603
EMPTY D9V1 2
R9V1 603
[PAGE_TITLE=CONN,
5% CH
1
2
3
0
DIO
CH
2
2
V_5P0
2
1
GAMEPORT1_DP
EG2G1
DIO
5%
603
EG9V1 35
TH
PGB0010603 603
EMPTY BAV99 SOT23S DIO
EMPTY
CMCHOKE
1
EG9V2
3
5% CH
NA SM
PGB0010603 603
EG3G1
V_5P0DUAL D9V2
CONN
XENON MU
DIO
2
EMI1 EMI2
10
V_GAMEPORT1
1
PGB0010603 603
1
5% CH
VBUS DD+ GND
9
4.7UF 10% 6.3V X5R 805
603
VBUS DD+ GND
8
C9G6
TH CONN
J9G1
4
RT8G2 THRMSTR 1206 2
PGB0010603 603
XENON GAME CONN
GAMEPORT2_DP_CM
BAV99 SOT23S DIO
MEMPORT2_DP_CM
1
R4G4
1 GAMEPORT2_DN_CM
1
1
3
DIO
2
D9G1
CH
1.1A 0.21DCR
35
CMCHOKE
EG9G1
5%
2
1
EG4G2
3
0
MEMPORT2_DN
PGB0010603 603
2
603
BI
0
X801560-001
R9G1
35
EMPTY
2
1
C5G6
1
EMPTY
X801560-001
BAV99 SOT23S DIO
3
1
GAMEPORT2_DP
2
2
470PF 5% 50V X7R 402
3
CMCHOKE
4
220UF 20% 10V ELEC RDL
C4V6
NA SM
2
5%
L9G1
GAMEPORT2_DN
1
C5G4
5% CH
L4G1
2
D9G2
603
1
R4G5 0
603
EMPTY
V_5P0DUAL
2
FB 603
2
EG9G2
R9G2
V_MEMPORT2
1
120 0.5A 0.2DCR
THRMSTR 1206
C9G1
1
0
2
1
1.1A 0.21DCR
60
FB5G1
2
2
1
OUT
V_MPORT
V_5P0DUAL
2
C1U2 1.0UF 10% 16V X7R 805
V_MPORT
IC
U1F2 NCP1117
3
IN
1
ADJUST/GND
OUT
2
1 1
X800499-001
2
C1F6 0.1UF 10% 25V X7R 603
1
FTP
FT1V1
C1F4
100UF 20% 16V
2 ELEC RDL
1
BAV99 SOT23S DIO
MEMORY PORTS + GAME PORTS]
DRAWING FALCON_FABD Tu e M ay 0 8 1 8:24 :18
20 07
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 46/82
REV 1.0
CR-47
:
@FALCON_LIB.FALCON(SCH_1):PAGE47
XDK BOARD MAPPING DEBUG BOARD MAPPING
59
IN
1 1 1
CPU_DBGSEL_XDK<0..69> N:CONNECT TO CPU DEBUG OUT
FTP FTP FTP
FT6U11 FT6U9 FT6U10
N:CONNECT TO CPU DEBUG OUT
DBG_CPU_LINKTRAINED DBG_CPU_SECURE_SYS DBG_CPU_PLL_LOCK DBG_CPU_TST_CLK
52 53 54 55
1
57
58 59 60 61
62 63
DB6E1 DB6E2 DB6E3 DB6E4
1 1 1
DBG_CPU_POST_OUT0 DBG_CPU_POST_OUT1 DBG_CPU_POST_OUT2 DBG_CPU_POST_OUT3 DBG_CPU_POST_OUT4 DBG_CPU_POST_OUT5 DBG_CPU_POST_OUT6 DBG_CPU_POST_OUT7
56
C PU _D BG SE L_ DE BU G< 0. .6 9>
IN
1 1 1 1 1 1 1 1
FTP FTP FTP FTP FTP FTP FTP FTP
FT6U8 FT6U2 FT6U3 FT6U4 FT6U5 FT6U6 FT6U7 FT6U1
0
0
1
1
2
2
3
3
4 5 6
4 5 6
7
7
8 9
8 9
10
10
11
11
12
12
13 14
13 14
15
15
16
16
17 18
V_5P0STBY V_5P0STBY
V_12P0
1
1
19 20
21
21
22 23 24 25 26
22
27
27
28 29
28
30
2
10K 5% CH 402
2 10K 402
VREG_V5P0_SEL_C
R1R5
2
10K 5% CH 402
3
1
4
VREG_V5P0_SEL_PGATE
CH
2
CR1D1
34
IN
FT1R1
FTP
1
1
R1D6
4.7K 402
2
1 VREG_V5P0_SEL_B1
VREG_V5P0_SEL_B2
5% CH
D<3> D<2> D<1> D<0>
V_5P0
C1R3 .22UF 10% 6.3V X5R 402
2 1
2
XSTR
V_5P0DUAL
S2 G2
VREG_V5P0_SEL_NGATE
5%
MBT3904
VREG_V5P0_SEL
SI4501DY
1
5 8 1
7
40 41 42
G1 S1
47
4.7K 5%
47
48 49 50
48
1%
51
51
CH 1206
52 53 54 55 56
52
57
57
58 59 60
58
61
61
62 63 64 65 66
62 63
67
67
68 69
68
402
CH 1206
2
2
2 C _ R E D E E L B 1
VREG_5P0_SEL
V_5P0DUAL
HIGH LOW
[PAGE_TITLE=[MISC,
LOW
V_5P0STBY
SMC_RST_N
2 10K 402
R1V1
1
BLEEDER_B
1
MMBT2222 XSTR
Q1V1
5% CH
Q1G2
2
MMBT2222 XSTR
V_5P0
HIGH
V_5P0
IN
2
3
27
DUAL,
DEBUG MAPPING]
49
1%
20
3
VREG_5P0_SEL NGATE/PGATE
46
5%
20
E D E E L B
402
45
R1V2
1 C _ R
CH
1
1
44
R1G1
CH
2
FT1R2
43
R1G2 1K
X801132-002
R1D5
1
6
FTP
29
39
38
IC
26
42 43 44 45 46
37
U1R1
25
41
36
R1R3
24
40
34 35
R1R2
23
30 31 32 33 34 35 36 37 38 39
33
1 C1D11 220UF 20% 10V 2 ELEC RDL
18
20
32
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :2 0
2 00 7
OUT
17
19
31
C PU _D BG _T ER M< 0. .6 9>
50
53 54 55 56
59 60
64 65 66
69
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 47/82
REV 1.0
CR-48
:
@FALCON_LIB.FALCON(SCH_1):PAGE48
V_5P0 D1E4 2 3
C1E4
1
HDD_TX_DP
IN
36
2
1
10% 0.01UF 16V X7R 402
BAV99 SOT23S DIO
HDD_TX_DP_C
HDD SATA AND POWER
HDD_TX_DN_C
HDD_TX_DN
IN
36
D1E3
C1E3
1
2
J1E1
2
10% 0.01UF 16V X7R 402
1
3
2 3
1
4 5 6
BAV99 SOT23S DIO
7
8 9
11
12 13 14
GND GND GND V_HDD V_HDD V_HDD V_XPOD
15 16
EMI1 EMI2
17 18
ME1 ME2
V_5P0
10
D1E2 2
1
36
OUT
1
C1E2
2
BAV99 SOT23S DIO
HDD_RX_DN_C
36
HDD_RX_DP
OUT
C1E1
1
PGB0010603 603
EMPTY
2
2
MTGA<8-1> MTGB<8-1>
V_5P0 RT1U1
2
2
2
1.5A 0.11DCR
3
1
V_HDD
THRMSTR 1812
1 C1E5 100UF 20% 16V 2 ELEC RDL
1
BAV99 SOT23S DIO
36
IN
C1C6
2
C1T4
1UF 10% 16V X7R 603
ODD_TX_DP_C
10% 0.01UF 16V X7R 402
C1T3
1UF 10% 16V X7R 603
470PF 5% 50V X7R 402
RT1R1 2
ODD POWER DECOUPLING
1
1.1A 0.21DCR
V_XPOD
THRMSTR 1206
C1T1 1UF 10% 16V X7R 603
V_3P3
V_12P0
TH
X800351-002
C1T5
V_5P0DUAL
ODD SATA 1
PGB0010603 603
EG1E1
EMPTY
2
D1E1
10% 0.01UF 16V X7R 402
ODD_TX_DP
1
EG1E2
EMPTY
2
HDD_RX_DP_C
PGB0010603 603
EG1E3
EMPTY
1
10% 0.01UF 16V X7R 402
1
1
EG1E4
3
HDD_RX_DN
PGB0010603 603
CONN XENON HDD CONN
GND D+ DGND DD+ GND
V_3P3
V_3P3
C1T2
470PF 5% 50V X7R 402
ODD POWER AND CONTROL CR1D2
CR1D3
2 36
IN
ODD_TX_DN
1
C1C5
2
J1C1 SATA
ODD_TX_DN_C
1 C1C10 100UF 20% 16V 2 ELEC RDL
9
10% 0.01UF 16V X7R 402
1
2
C 1C14
1 C1C11 100UF 20% 16V 2 ELEC RDL
C1C13
1UF 10% 16V X7R 603
0.1UF 10% 25V X7R 603
C1D6
1UF 10% 16V X7R 603
C1R1
.1UF 10% 6.3V X5R 402
36
OUT
ODD_RX_DN
1
2
ODD_RX_DN_C
10% 0.01UF 16V X7R 402
36
OUT
ODD_RX_DP
1
C1C3
2
34
4 5 6
V_5P0
7
OUT
TRAY_STATUS
1
R1R4
100 402
2
CONN ODD_RX_DP_C
5%
C1D4 1UF 10% 16V X7R 603
C1D1 1UF 10% 16V X7R 603
C1D3
BAV99 SOT23S EMPTY
CH
V_3P3
1 C1D9 100UF 20% 16V 2 ELEC RDL
1
BAV99 SOT23S EMPTY
TRAY_STATUS_R
J1D1
V_5P0
8
10% 0.01UF 16V X7R 402
[PAGE_TITLE=CONN,
3 1
3
C1C4
2
3
1 3
4 6 8 10 12
V_12P0
.1UF 10% 6.3V X5R 402
5 9
11
CONN
ODD + HDD]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :2 0
2 00 7
EJECTSW_N TRAY_OPEN
IN IN
43 34
7
MICROSOFT
CONFIDENTIAL
1
2
C1R4 75PF 5% 50V NPO 402
PROJECT NAME FALCON_RETAIL
PAGE 48/82
REV 1.0
CR-49
:
@FALCON_LIB.FALCON(SCH_1):PAGE49
V_3P3STBY
V_12P0
1 1
1
1
2
C6G5
100UF 20% 16V ELEC RDL
2 1
C6G2
470PF 5% 50V X7R 402
FTP
1
1 C9B1 1500UF 20% 16V ALUM 2 RDL
FT9N1
C9A1 0.1UF 10% 25V X7R 603
2
1
1
1
C9A5 0.1UF 10% 25V X7R 603
2
1
C9A6
0.1UF 10% 25V X7R 603
2
DB8M1 DB8M2 DB8M3
C9A2 0.1UF 10% 25V X7R 603
2
J9A1
2
GND GND GND
4 5 6
V12P0 V12P0 V12P0
7
PSU_EN
8
VSB5P0
3
1
R6G7 0
2
34
IN
5% CH
603
2
PSU_V12P0_EN
L6G1 35
ARGONPORT_DN
BI
R8A1
1
PSU_V12P0_EN_R
5%
1
CH
10K 5%
2
3
1
C8A1 .1UF 10% 6.3V X5R 402
2
CH
EMPTY
CMCHOKE
4
100 402
1
NA SM
R8A2
402
2
C8A2
470PF 5% 50V EMPTY 402
9
35
ARGONPORT_DP
BI
2
1
X801560-001
1
R6G8 0
1
2 2
1
C6G3
470PF 5% 50V EMPTY 402
2
C6G4
1
470PF 5% 50V EMPTY 402
ARGON_DN_CM ARGON_DP_CM
3
4 5 6
5% CH
603
2
7
8 9
USE LC NETWORK FOR USB 1.1 USE USB CHOKE FOR USB 2.0
V_3P3STBY
10
11
1
R3N7 10K 5% CH 402
2 34
IN
PWRSW_N
2
R3N6
10K 402
5% CH
12 34 34
2
1
PWRSW_N_R
2 1
1
C6V15 470PF 5% 50V X7R 402
1
11
BI
MEMPORT3_DP_ARGON
603
5% EMPTY
L6G2
NA SM EMPTY
CMCHOKE
4
C6V11 470PF 5% 50V X7R 402
2 1
XENON RF CONN
1
V_5P0STBY
SPARE C_DATA C_CLK GND NTX
MTGA<8-1> MTGB<8-1>
DB8N1
1
FTP
1 C5B7 100UF 20% 16V
FT8N1
1 C8B1 100UF 20% 16V
2 ELEC RDL
2 ELEC RDL
C9A4
470PF 5% 50V X7R 402
2
ME1 ME2
V_5P0STBY
V_12P0
1
1
X800095-001
C6V10 470PF 5% 50V X7R 402
R8B5
R7B2
CH
CH
2.2K 5% 402
402
2
1 C _ 0 P 2 1 V _ R E D E E L B
MEMPORT3_DP_ARGON_CM
V_12P0
2.2K 5%
2 549 402
2 C _ 0 P 2 1 V _ R E D E E L B
R8N1
60
BI
2
1
1
MEMPORT3_DN_ARGON_CM
3
2
X801560-001 1
[PAGE_TITLE=CONN,
2.2K 402
R6G38 2
56 603
5% EMPTY
ARGON + POWER SUPPLY]
27
IN
ANA_V12P0_PWRGD
2 2.2K 402
R8A4
1
BLEEDER_V12P0_B1
1
CH
R8A3
2
3 1
BLEEDER_V12P0_B2
Q8N1
BCP51 XSTR
2 4 BLEEDER_V12P0_LOAD
1
1
MMBT2222 XSTR
2
1
1
R7N3
R7N1
R7N4
R7N2
CH 805
CH 805
CH 805
CH
10 1%
Q8B4 2
Q8B5
5%
1
1%
CH
3
MEMPORT3_DN_ARGON
TH
X811487-001
1
EMI1 EMI2
2
3
ME1 ME2
12
CONN
R6G37 2 0
60
13
ARGON_DATA ARGON_CLK
BI BI
VCC DD+ GND
EMI1 EMI2 EMI3 EMI4
10 13 14
TH
J6G1
CONN XENON PWR
1
10 1%
2
10 1%
2
10 1%
2
805
MMBT2222 XSTR
1
5% CH
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 8
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 49/82
REV 1.0
CR-50
:
@FALCON_LIB.FALCON(SCH_1):PAGE50
4
4
IN
CPU_VREG_APS5
IN
CPU_VREG_APS4
R7E3 0
5
5%
402
0
4
IN
CPU_VREG_APS3
4
IN
CPU_VREG_APS2
4
IN
CPU_VREG_APS1
4
IN
CPU_VREG_APS0
R7E5 0
CH
0
R7E2 0
3
1
R7E4
CH
402
5% 1K
402
1
2
5% CH
R7T6 CH
402
2
0
5% CH
2
5
10K 5% EMPTY 402
2
10K 5% EMPTY 402
1
2
10K 5% CH 402
10K 5% EMPTY 402
2
2
10K 5% CH 402
0
1
VREG_CPU_VID<5..0>
R7T14
R7T12
CH
CH
CH
402
402
402
10K 5%
N:CPU
INPUT
1
2
C9B2 4.7UF 10% 16V X5R 1206
L9B1
2
2
N:GPU
FILTER
1.6UH 10A NA
2
V_VREG_CPU
IND
TH
C9C4
1500UF 20% 16V ALUM RDL
C9C1
1500UF 20% 16V ALUM RDL
C9E3
1
C9D2
1500UF 20% 16V ALUM RDL
1500UF 20% 16V ALUM RDL
C9B4
4.7UF 10% 16V EMPTY 1206
2
1
2
1 C8C2 820UF 20% 6.3V 2 EMPTY RDL
1
2
C8E3
820UF 20% 6.3V ALUM RDL
1 C8E1 820UF 20% 6.3V ALUM 2 RDL
1
OUTPUT FILTER
1 C8F1 820UF 20% 6.3V ALUM 2 RDL
1
2
C8E2
820UF 20% 6.3V ALUM RDL
1
2
C8D1
820UF 20% 6.3V ALUM RDL
2
INPUT
DB8P2 FTP
1 C8C1 820UF 20% 6.3V 2 EMPTY RDL
+ OUTPUT FILTERS]
C8B2
L8B1
1.6UH 10A NA
INPUT
FILTER
2
V_VREG_GPU
IND
TH
4.7UF 10% 16V X5R 1206
1 C6B3 1500UF 20% 16V ALUM 2 RDL
1 C7B3 1500UF 20% 16V ALUM 2 RDL
1
2
C8B4 4.7UF 10% 16V X5R 1206
1
2
C6B5 4.7UF 10% 16V X5R 1206
1
OUT
C6N2
2
4.7UF 10% 16V X5R 1206
1
2
C7B4 4.7UF 10% 16V X5R 1206
1
2
53 54
C7N3 4.7UF 10% 16V X5R 1206
DB8P1
V_GPUCORE N:GPU
FT7T9
1
2
C8D4
1 C7C2 820UF 20% 6.3V ALUM 2 RDL
820UF 20% 6.3V ALUM RDL 1
[PAGE_TITLE=VREGS,
1
4.7UF 10% 16V EMPTY 1206
1
N:CPU
52
51
C9C3
1
V_CPUCORE
OUT
51
10K 5% EMPTY 402
1 1
OUT
R7T16
10K 5%
V_12P0 V_12P0
WATERNOSE=011100=1.1625V D D1 .0 R EQ UI RE S V I D0 R C DD 2. 0 N O STU FF R C LOKI=100001=1.05V
1
R7T15
2
R7T9
1
1
10K 5%
2
10K 5% EMPTY 402
N: N: N: N:
1
R7T5
R7T7
2
1
R7T11
2
10K 5% EMPTY 402
3
1
R7T13
1
R7T8
4
1
2
1
R7T4
10K 5%
1
R7E6
CH
402
4
5%
402
5%
402
V_GPUCORE
R7E1
CH
FTP
1 C7C1 820UF 20% 6.3V ALUM 2 RDL
1
OUTPUT FILTER
1 C6C3 820UF 20% 6.3V ALUM 2 RDL
1 C7C3 820UF 20% 6.3V ALUM 2 RDL
FTP
1 C6C2 820UF 20% 6.3V ALUM 2 RDL
FT5R2
1 C6C1 820UF 20% 6.3V ALUM 2 RDL
1 C5C8 820UF 20% 2.5V 2 EMPTY 8X8
1 C5C9 820UF 20% 2.5V 2 EMPTY 8X8
FT7U4
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 8
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 50/82
REV 1.0
CR-51
:
@FALCON_LIB.FALCON(SCH_1):PAGE51
3188
V_5P0
50 1
R8G1
R8G1 R8V10 C8U4
V_VREG_CPU
IN
3190A
STUFF EMPTY EMPTY
EMPTY STUFF STUFF
1
2
R8U5
10
1%
603
CH
1K 1%
CH
50 34
IN
R8V10
2
V_VREG_CPU
IN
VREG_CPU_EN
1
10
1%
805
EMPTY
VREG_CPU_RAMPADJ_R
FTP
1
1UF 10% 16V X7R 603
R8F7 10K 5% CH 402
2
52
IN
VREG_CPU_PHASE3
IN
VREG_CPU_PHASE2
IN
100UF 20% 16V ELEC RDL
1
1
R8U3 294K 1%
2
2
402
C8U4 .1UF 10% 6.3V X5R 402
1
0
U8U1
5% EMPTY VREG_CPU_RAMPADJ
R8V7 0
R8V9
VREG_CPU_PHASE1 0
CH
R _ P M O C S
2
2
R8V2
R8V1 47.5K
R8V4
47.5K
1%
1
C _ U
2 47.5K
1%
1%
CH
EMPTY 603
1
RAMPADJ
RT8F1
P C _ G
R8V3
1
E R V
22 23
FT8U1
PWRGD
EN
2
CH 1
76.8K 1%
2
CH
603
1
C8V1
360PF 10% 50V NPO 603
SW4 SW3 SW2 SW1
18
CSCOMP
17
CSSUM
16
CSREF
1
FTP
1%
35.7K 603
R8V5
1
21
VREG_CPU_CSCOMP
2 THRMSTR 603
20
VREG_CPU_PHASE2_R
TEMP SENSOR
2
603
1
VCC
14
VREG_CPU_PHASE3_R VREG_CPU_PHASE1_R
NA 100K
CH
603
1
VREG_CPU_SW4
1
TP
5%
603
8
FB
9
COMP
7
FBRTN
6
PWM4 PWM3 PWM2 PWM1
24 25 26
1 2 3 4 5
27
VREG_CPU_VID<5..0>
5 4 2 1
1
0
VREG_CPU_FBRTN
603
2
VREG_CPU_PWM3 VREG_CPU_PWM2 VREG_CPU_PWM1
OUT OUT OUT
2
5% CH 52 52 52
VREG_CPU_DRV_EN
DELAY
12
VREG_CPU_DELAY
RT
13
VREG_CPU_RT
GND
19
1
2
R8U2 422K ST7T1
R8F8 0
402
1%
CH
50
IN
3
15
ILIMIT
8200PF 10% 16V
2
10
VID5 VID4 VID3 VID2 VID1 VID0
X806818-001
C8U3
34
IC
CH
DB8U4
FT2P16
OUT
ADP3190A
28
11
5%
FTP
VREG_CPU_PWRGD
R8V6
603 52
2
C8G5
CH
603 52
1
C8V15
1
FT2P17
2
VREG_CPU_VCC
402
2
2
2
R8U1
C8U1
.047UF 10% 16V X7R 603
1
R8U4
1%
324K
240K 5%
CH
CH
603
1
2 1
402
OUT
52
C8U2
1000PF 10% 50V EMPTY 402
CH
1
1
402
SHORT
2
VREG_CPU_CSSUM
V_CPUCORE
1
LAYOUT:ATTACH TO CLOSEST INDUCTOR 1
ST8F1 2
FT8U2
VREG_CPU_CSREF
1
R8G3 10
SHORT
2
1% CH
402
1
ST7T2 2
SHORT
R8U13 2
1
5% EMPTY
0
402
2
C8U7
1
[PAGE_TITLE=VREGS,
TARGET FSW=233KHZ
1000PF 10% 50V X7R 402
VREG_CPU_FB
C8U8
2 1
1% CH
N:
C8G1
10% 0.1UF 25V EMPTY 603
1 R8U10
1
1000PF 10% 50V X7R 402
VREG_CPU_CSREF_R
2
VREG_V_CPUCORE_S
1
FTP
C8U10
2
1.33K 603
1
C8U6
2
330PF 5% 50V X7R 402
VREG_CPU_COMP_R
CPU CONTROLLER]
1
R8U11
24.3K 402
2
22PF 5% 50V NPO 402
VREG_CPU_COMP
1% CH
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 8
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 51/82
REV 1.0
CR-52
:
@FALCON_LIB.FALCON(SCH_1):PAGE52
50
50
IN
R9P2
1
V_VREG_CPU
2.2 805
D9C1 1N4148
2
51
IN
VREG_CPU_DRV_EN
1
1%
EMPTY
1
2
51
3
1
VREG_CPU3_VCC
V_VREG_CPU
IN
VREG_CPU_BST3
1.0UF 10% 16V EMPTY 805
VREG_CPU_PWM3
IN
R9P1
1
U9P1 4 2 3 6
2
D
MOS DRIVER VCC BST IN DRVH OD_N* SW PGND DRVL
1 8 7
2
1
VREG_CPU_BST3_R
1%
2.2 805
EMPTY
3
Q9D2
Q9D1
D
NTD60N02R DPAK
10% 0.01UF 50V EMPTY 805
SOT23 EMPTY
C9P4
3
C9P3
C9P2
1
1 G
2
S
2
1
NTD60N02R DPAK S
G
EMPTY
EMPTY
2
2
C9D3 4.7UF 10% 16V X5R 1206
1
2
C9D1
4.7UF 10% 16V EMPTY 1206
VREG_CPU_PHASE3
5% 0.015UF 16V EMPTY 805
EMPTY
3
TH
D
V
Q9C1
D
NTD85N02R DPAK
1 G
S
2
R9C1
3
2.2
Q8C1
1%
NTD85N02R DPAK
1
S
G
EMPTY
2
1
0.6UH 30A NA
EMPTY
1 3 G B _ U P C _ G E R
2
EMPTY 805
EMPTY
VREG_CPU_SW3_R
1
R9T2
1
D9E1 1N4148
2 1
2
51
VREG_CPU_BST2
1
1.0UF 10% 16V X7R 805
1
U9T1 4 2 3
6
3
2
D
0.01UF 10% 50V X7R 805
SOT23 DIO
C9T3
VREG_CPU_PWM2
IN
3
1
VREG_CPU2_VCC
1% CH
2.2 805
2 C9T2
2.2 805
IC
MOS DRIVER VCC BST IN DRVH OD_N* SW PGND DRVL
R9T1
2
VREG_CPU_BST2_R
1%
1
2
3
Q9E1 NTD60N02R DPAK
G
S
2
5% 0.015UF 16V X7R 805
CH
1
8
1
C9T1
Q9D4
D
NTD60N02R DPAK
1
S
G
FET
1
2
EMPTY
2
C9D4
4.7UF 10% 16V EMPTY 1206
1
2
4.7UF 10% 16V X5R 1206
VREG_CPU_PHASE2
2
VREG_CPU_DRVH2
7
3 D
E R V
D
NTD85N02R DPAK
1 G
S
2
S
G
2
OUT
1
1%
2
EMPTY 805
FET
VREG_CPU_SW2_R
1
1
R9U2
D9F1 1N4148
2
3
1
VREG_CPU1_VCC
1
1%
2.2 805
CH
1
2
SOT23 DIO
C9U3 1.0UF 10% 16V X7R 805
1
U9U1
51
VREG_CPU_BST1
IN
VREG_CPU_PWM1
4 2 3
6
MOS DRIVER VCC BST IN DRVH OD_N* SW PGND DRVL X801233-001
R9U1
2.2 805
IC
C9U2
2 2
3 D
10% 0.01UF 50V X7R 805
2
1% CH
VREG_CPU_BST1_R
1
C9U1
2
NTD60N02R DPAK
1 G
5% 0.015UF 16V X7R 805
3
Q9F1
S
2
FET
Q9F4
D
NTD60N02R DPAK
1
S
G
EMPTY
2
1
2
C9F4 4.7UF 10% 16V X5R 1206
1
2
VREG_CPU_PHASE1
2
VREG_CPU_DRVH1
7
IND
5
TH
1 1 G B _ U P C _ G E R V
3 D
NTD85N02R DPAK
1 G
S
2
R9F1
3
Q9F2
FET
D
G
S
2
L8F1
OUT
CPU OUTPUT PHASE 1,2,3]
51
1
0.6UH 30A NA
1%
2
EMPTY 805 VREG_CPU_SW1_R
FET 1
2
[PAGE_TITLE=VREGS,
4700PF 10% 50V EMPTY 603
2.2
Q8F1 NTD85N02R DPAK
1
C9E4
C9F1
4.7UF 10% 16V EMPTY 1206
1
8
51
2.2
Q9D3 NTD85N02R DPAK
1
FET
4700PF 10% 50V EMPTY 603
0.6UH 30A NA
TH
R9E1
3
Q9E3
L8E1
IND
1 2 G B _ U P C _ G
C9C5
C9E1
5
X801233-001
51
V_CPUCORE L8D1
2
VREG_CPU_DRVH3
5
X801233-001
OUT
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 8
2 00 7
MICROSOFT
CONFIDENTIAL
C9F3
4700PF 10% 50V EMPTY 603
PROJECT NAME FALCON_RETAIL
PAGE 52/82
REV 1.0
CR-53
:
@FALCON_LIB.FALCON(SCH_1):PAGE53
50
V_GPUCORE ST5R2
R8C9
1
VREG_GPU_VFB_R
2
R8P7
1.1K 402
R8P9
2 1.21K 402
FT8P2
FTP
FT8P1
FTP
1 1
2
CH 805
5% EMPTY 402
OUT
THRMSTR 603
1
1
1% CH
R8P4
2
1
2
1
2
C8P2
R8P3
2
VREG_GPU_COMP_R
1.0UF 10% 16V X7R 805
1
R8P1
7.5K 603 C8N5
C9P1
2
.047UF 10% 16V X7R 603
1
IN
YR3
G UN GA
AN Y
V ID
0 =1 00 00
1 .1 50 V
26
VCCL
VREG_GPU_VFB
1
VFB
VREG_GPU_VDRP
2
VDRP
VREG_GPU_5VREF
10
NSEN
PGD
29
VREG_GPU_CS2
CS2 CS1
GH2 GL2
19
CSREF
GH1 GL1
22
9
ROSC
28
CPGD
27
2
C8N4
0.01UF 10% 16V X7R 402
1
R8B8
COVC
1
R8P6
3
2
R8B9
2
CH
R8B10 2
62 5%
0
CH
5% CH
402
1
1
R8B2
[PAGE_TITLE=VREGS,
C9B3
D8B1 MMSZ18 SOD123 DIO
2
17 1
24
LGND
3
GND2 GND1
18 23
R8B4
2 1
2
1% CH
7.5K 603
2
3
R8C1
C9C2 0.1UF 10% 25V X7R 603
6.19K 1%
CH 402
1
1
V_5P0STBY
X800631-001
2
R5N1 10K 5%
34
402 1
VREG_GPU_EN_N
IN
FT2P6
FTP
1
Q8B3 FET 2N7002 SOT23
R _ N _ N E _ U P G _ G E R V
1
2
0.1UF 10% 25V X7R 603
R9B1
10K 402
2
5%
CH
VREG_GPU_PWRGD 1
VREG_GPU_GH2_R
1
R8N5
2
1A CH
1
CH
805 VREG_GPU_GH1_R
2
2
1
1
R8N3 0
750K
C8B7
470PF 5% 50V X7R 402
R8N6 0
1
1%
R8B3 1
0.1UF 10% 25V X7R 603
2
C8P4
C8B8 0.1UF 10% 25V X7R 603
54 53
1
C8N1
53
OUT
0.1UF 10% 25V X7R 603
1
2K 402
2
OUT
0.1UF 10% 25V X7R 603
1
805
2
0
SHORT
2
R8N2
805
2
VREG_GPU_PHASE1
VREG_GPU_NPNC
1
5%
VREG_GPU_GL2_R VREG_GPU_CSREF_R
1
CH
C8P3
2
2
C8B3
0.1UF 10% 25V BAV99 X7R 603 SOT23S DIO
1
V_GPUCORE
ST8C1
2
3
2
1% CH
7.5K 603
1
VREG_GPU_PHASE1_C
5%
402 1
D8B2 1N4148 SOT23 DIO
CH
1
2
2
VREG_GPU_ILIM
VREG_GPU_SEN
5
1% CH
VREG_GPU_PHASE1
31 8 21
VREG_GPU_CSREF
1
VREG_GPU_VCCH
VREG_GPU_VID0
11
CBOUT
1
62
12
COMP
VREG_GPU_CS1
R8P5
ILIM 5VREF
OUT
20
14 13
32
1
5%
402
62
15
VREG_GPU_COMP
1%
2
OUT
D8B3 1
1
2
CH
0
VCCH
CH 603
R8B7
402
62
VREG_GPU_VID1
VFFB
35.7K
1
2
5% EMPTY
0
NCP5331 VCCL2 VCCL1
5VSB
R8C7
7.5K 603
V_GPUCORE
16 25
1% CH
ST5R1 2
VREG_GPU_PHASE2
VREG_GPU_VID3
IC
7
VREG_GPU_CPGD
R8B1 0
0
U8N1
30
VREG_GPU_ROSC
1
402
62
VREG_GPU_VID2
1.0UF 10% 16V X7R 805
VREG_GPU_VFFB
2
V_VREG_GPU
IN
VREG_GPU_VID4
OUT
C8B9
6 4
1
IN
1.150V
VREG_GPU_5VREF
2
SHORT
53
0=10000
VID4 VID3 VID2 VID1 VID0
1
6800PF 10% 50V X7R 603 1
54
2
1% CH
4.02K 402
VREG_GPU_COMP_C
IN
VID
VREG_GPU_VCCL
53
1
ANY
CH
2
6800PF 10% 50V X7R 603
54
1
C8N3
1000PF 10% 50V EMPTY 402
2
B13
1%
1%
CH
C8P1
YR2
50 62
OUT
OUT
5.11K 402
1
1.150V 1 .1 25 V 1 .1 50 V 1 .1 50 V 1 .1 25 V 1. XXXV
1%
2 2
VOLTAGE
VID 0=10000 V ID -1 =1 00 01 V ID 0=1 00 00 V I D 0 =1 00 00 V ID -1 =1 00 01 V ID ? =0 11 10
2.2 1 0
NA 10K
VID
ANY S EC I FX H YN IX A NY AN Y
YR1
R8N7 2
SHORT
RT7C1
MEM
<4.5 4 .5 -6 .0 4 .5- 6. 0 4 .5 -6 .0 6 .0 -7 .0 7 .0 -8 .0
1
1
62
GPU
V_VREG_GPU
IN
805
1A CH
VREG_GPU_GL1_R
2
R8N4
1%
0
CH
805
34
VREG_GPU_GH2
OUT
54
VREG_GPU_GL2
OUT
54
VREG_GPU_GH1
OUT
54
VREG_GPU_GL1
OUT
54
FT2P3
1A CH
2 1
OUT
FTP
2
1A CH
603
GPU CONTROLLER]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 9
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 53/82
REV 1.0
CR-54
:
@FALCON_LIB.FALCON(SCH_1):PAGE54
50
IN
V_VREG_GPU 3 D
53
4.7UF 10% 16V X5R 1206
NTD60N02R DPAK
1
VREG_GPU_GH2
IN
C6B2 Q6B1
G
S
2
V_GPUCORE VREG_GPU_PHASE2
FET
2
L6C1
3 D
3
Q6B2
TH
R6C2
Q6C1
D
53
1
0.6UH 30A NA
IND 1
OUT
2.2 1%
53
1
VREG_GPU_GL2
IN
NTD85N02R DPAK G
S
2
NTD85N02R DPAK
1
S
G
FET
CH
2
FET
2
R _ 2 H P _ U P G _ G E R V
2 3 D
53
4.7UF 10% 16V X5R 1206
NTD60N02R DPAK
1
VREG_GPU_GH1
IN
C7B2 Q7B1
G
S
2
805
1
C5C6
4700PF 10% 50V X7R 603
FET L7C1 2
1
IND 3 D
3
Q7B2
TH
1
R7B6
Q7C1
D
0.6UH 30A NA
VREG_GPU_PHASE1
2.2 1%
53
1
VREG_GPU_GL1
IN
NTD85N02R DPAK G
S
2
NTD85N02R DPAK
1
S
G
FET
FET
2
OUT
53
CH
2
805
R _ 1 H P _ U P G _ G E R V
2 1
C8B6
4700PF 10% 50V X7R 603
V_5P0 V_1P8 U2T1 1
R2E7 10
1210 1
10
1
1
2
5%
2
CH
IC
NCP1117
3
IN
1
ADJUST/GND
C2T5 0.1UF 10% 25V X7R 603
X800500-001 DPAK 1.8V
OUT
1
2
1
2
C2R4 0.1UF 10% 25V X7R 603
1
2
FTP
FT2R8
V_1P8
V_MEM
C2D6
100UF 20% 16V ELEC RDL
1
2
CH
R2T8
2
0
1A
805
EMPTY
1
5%
R1E1 10
1210
[PAGE_TITLE=VREGS,
1
R1E3 10
1210
V_V3P3TOV1P8
5%
CH
R2E6
1210
2
R2T7
2
0
1A
805
EMPTY
2
5% CH
GPU OUTPUT PHASE 1,2]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 9
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 54/82
REV 1.0
CR-55
:
@FALCON_LIB.FALCON(SCH_1):PAGE55
V_12P0
1
L7F1
2
1 C6F3 1500UF 20% 16V ALUM 2 RDL
C6U2
V_VREG_V1P8V5P0
OUT
NA
1.6UH 10A
32
TH
D3V1
1UF 10% 16V X7R 603
1
1 3
V_5P0
ADI_VREG
0.1UF 10% 25V X7R 603
2
2
BAT54A SOT23S DIO
DB6G1
1
1
1
3
1
FTP
ST6F1
Q6F1 FET
D
FT6V1 S
1
SHORT
0
5% EMPTY 402 1
L6F1
C6U1 1UF 10% 16V X7R 603
1
VREG
VREG_V5P0_BST2
11
BST2
R4V7
1
2
ST5V1
2
VREG_V5P0_DH2
12
DH2
VREG_V5P0_SW2
13
SW2
VREG_V5P0_CSL2
14
1% CH
7.5K 402
CSL2
VREG_V5P0_DL2
16
DL2
15
PGND2
2
TH
C7F3
2 P M O C _ 0 P 5 V _ G E R
3
820UF 20% 6.3V
Q6F2 FET
D
ALUM 2 RDL
NTD60N02R DPAK 1
S
G
V
2
357
1%
C _ 2 B 2 F _ 0 P 5 V _ G E 1 R V
2
CH 402 1
R4V6
1
C4V12
2
1.82K 1%
C4V1
3300PF 10% 50V X7R 402
2
402
R4V4
1
C4V13
1 34
R4V5
OUT
DH1
22
VREG_V1P8_DH1
SW1
21
VREG_V1P8_SW1 VREG_V1P8_CSL1
DL1
18
VREG_V1P8_DL1
19
COMP1
32
UV2 FB2
FB1
1
8
TRK2 EN2 POK2 FREQ SYNC
3 2
2 S S _ 0 P 5 Q V E _ R G F E I_ R D V A
LCC32
R4V3
10K 402
C4V14 .1UF 10% 6.3V X5R 402
ST2F2
2
2
VREG_V1P8_SW1_S
31
25 24
IN
R4G9 0
ST3G1
2
S
G
2
2 4
TH VREG_V_MEM_S_0
1 C2F1 820UF 20% 4V 2 EMPTY RDL
Q2F3
1
2
C2F3
820UF 20% 4V POLY RDL
1 C3F6 820UF 20% 4V 2 POLY RDL
C3U5 1UF 10% 16V X7R 603
1
FET
R4G1 464 1%
R4G6 2 1
R4V1
2
1
VREG_V1P8_COMP1_R
1
C4V9
1%
330PF 5% 50V X7R 402
2
2
55
402
IN
OUT
VREG_V5P0_VMEM_PWRGD
1
ADI_VREG
VREG_V1P8_EN
R4V10 2
10K 402
1
VREG_V5P0_EN FT2P18
FTP
1
R3V5
47K 402
1
R3V4
1
5% CH
FTP
IN
1K
2
VREG_V5P0_EN_R
5%
CH
FT2P19
2
402
V1P8
2
5% CH 402
1
2
R 4G 6
R 4G7
1.9V 1.95V 2.0V 2.1V
1.91K 1.91K 1.91K 1.91K
75 43.2 267 301
R 4G 8 806 806 549 464
THESE ARE THE VOLTAGES NEEDED FOR VARIOUS MEMORIES. CONSULT WITH MEM TEAM FOR USAGE.
C3V8 .22UF 10% 6.3V X5R 402
AND V5P0]
V_ MEM
402 VREG_V1P8_FB1_R
1
R4G8 806 1%
CH
CH
[PAGE_TITLE=VREGS,
62
75 1%
34
1
5%
2
2700PF 10% 50V X7R 402
R4G7
1K
IN
C4G1
1
R3V3
34
C _ 1 B F _ 8 P 1 V _ G E R V
VREG_V1P8_FB1
1%
CH
1
402
2
82PF 5% 50V NPO 402
.1UF 10% 6.3V X5R 402
CH 402
1.91K
2
CH
1% CH
C4V10
C4V11
243
2
5% EMPTY 402
1
18.2K 402
2
2
NTD60N02R DPAK
1
2
F RE Q P I N 3 : 0 300KHZ 1 6 00 KHZ
L3F1
3
CH
1
1
D
55
5% EMPTY
1
SHORT
1.7UH 13.8A
1 S S _ 8 P 1 V _ G E R V
ST2F1
1
SHORT
1% CH
7.5K 402
5%
R4V2
10K 402
2 ADI_VREG
1
FTP
FET
SHORT
3 3
1
R3V1
1 P M O C _ 8 P 1 V _ G E R V
X807026-001
1
DB3F1 FT2U1
2
1
1
4
1
2
TRK1 EN1 POK1
G U L S D D N N G G
S
2
VREG_V1P8_CSL1_R
5 6
Q3F1 NTD60N02R DPAK
1
1
CSL1
PGND1
D
470NF 10% 10V X7R 603
G
20
30
10
2
VREG_V1P8_BST1
SS1
2
220PF 5% 50V NPO 402
VREG_V5P0_FB2
23
SS2
26
1
BST1
9
1% CH
7.5K 402
820PF 10% 50V X7R 402
CH
1
VREG_V5P0_COMP2_R
27
COMP2
VREG_V5P0_CSL2_R
SHORT
LDOSD
ADP1823
C3V7
2
IC
P I N V
7
4
1.7UH 13.8A
R _ 2 B F _ 0 P 5 V _ G E R V
2
1
R4V11
2
ST6F2
7 8 1 2
U4V1
29
G
VREG_V5P0_SW2_S
C3V6
1UF 10% 16V X7R 603
3
1
1UF 10% 16V X7R 603
2
2
1
R4V9
2
V_MEM C4V8
470NF 10% 10V X7R 603
NTD60N02R DPAK 1
SHORT
1
C4V15
1 C7F1 1500UF 20% 16V ALUM 2 RDL
C4V7
55
OUT
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 9
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
CH
2
402
PAGE 55/82
REV 1.0
CR-56
:
@FALCON_LIB.FALCON(SCH_1):PAGE56
V_3P3
U6T2
V_5P0
V_5P0
1 IC
U1F1 34
IN
VREG_3P3_EN
1
1
NCP5662
2
IN
TAB
6
3
GND
OUT
4
C1U1 1.0UF 10% 16V X7R 805
1
2
R1F7
1
EN
ADJ
5
1K
1K
1
1
2
C5B3
NCP1117 IN
EMPTY 402
5% CH
FTP 4
FT5N1
PART # X 80 79 64 -0 01 X807089-001
R1U1 E MP TY 1.27K
1K
1
1
C5B1 0.1UF 10% 25V X7R 603
2
C5B2
FT7T8
100UF 20% 16V
402
1
FTP
2
VREG_1P8STBY_D1
2
2
1
IF D5B1 DIO SMA
D5N2 DIO SOD123 MBR130L
S1A 1 VREG_1P8STBY_D2 1
1
R4C31
CH
0
402
603
4
1
1206
1
2
VREG_1P8STBY_IN
IN
V_GPUCORE
1
ADJUST/GND
1.0UF 10% 16V X7R 805
1 1
1
R5B1
X800500-001 DPAK 1.8V
549 1%
2
EMPTY 402
R4P13
2
VREG_GPUPCIE_IN
5% EMPTY
VREG_1P8STBY_ADJ
0
V_3P3
FTP
1 C5B4 100UF 20% 16V 2 ELEC RDL
C5B6 0.1UF 10% 25V X7R 603
U3P1
IN
ADJUST/GND
NCP1117
1
2
OUT
R4P13
R4C31
R4P14
E MP TY S TU FF
ST UF F E MP TY
EM PT Y S TU FF
R5C6 0
U5C1
1
S TU FF E MP TY
ADJUST/GND
OUT/TAB
R3C21
549
EMPTY 402
2
1
V _S BP CI E
R 3C 22
1.87V 1.80V
499 549
2
R2C3
C2C6
.1UF 10% 6.3V EMPTY 402
243 1%
2
EMPTY 402
1
2
[PAGE_TITLE=[VREGS,
LINEAR
VREGS]
CH
402
0402
2
R6C1 0
2
402
1
2
2
VREG_CPUPLL_IN
FT2P26
C6P1 1.0UF 10% 16V X7R 805
C5C5 4.7UF 10% 6.3V X5R 805
1A CH
805
1A CH
FT5R1
R _ X E I C P _ G E R V
V_CPUPLL
EMPTY
R5C4 0
FTP
1 1%
CH
EMPTY NCP1117
3
IN
1
ADJUST/GND
OUT OUT/TAB
N:
T AR GE T I S
2 .2 0V 1
2 1
4
2
1%
1 1%
EMPTY 402
CH 0402
VREG_CPUPLL_ADJUST
EMPTY 0402 1
1
2
R6R2
C6R1
.1UF 10% 6.3V EMPTY 402
FT7R3
R6R1
499
X800501-001 SOT223 1.8V
FTP
1
R6R3
R _ X E P _ D D V _ G E R V
VREG_VDD_PEX_ADJ
1
CH
5%
2
1 1%
1%
2
R5C9
0
.1UF 10% 6.3V X5R 402
2
1A
1
X800501-001 SOT223 1.2V
1.0UF 10% 16V X7R 805
1 1
R5P2
R5P1
C5P1
U6R1
805
FTP
1UF 10% 16V EMPTY 603
1 .2 5V
1K 1%
2
2
1
R3C22
C2C5
T AR GE T I S 1
4
X800501-001 SOT223 1.2V
1
1
1 1
N:
2
OUT/TAB
2 1
V_SBPCIE
2 4
1UF 10% 16V X7R 603
2.9V
FT7T6
C7T99
V_GPUPCIE
OUT
V_3P3
EMPTY
IN
C7T98
FTP
2
NCP1117
3
1.0UF 10% 16V X7R 805
B 13L G UN GA
2
CH
NC
4
1
FT5N2
5%
402
2
IC
1
C4C6
GPU
805
R5B2
5
GND
5% EMPTY
U5C1
V_1P8 1
VOUT
1
2
2
3
PLACEHOLDERS OUT
VREG_PCIEX_ADJUST
IC
3
C5N3
1
R4P14 0
603
S ET T O 1 .8 16 V
V_1P8STBY NCP1117
ENABLE
T HI S I S A CT UA LL Y A 3 .3 V P AR T N CP 61 2 F AM IL Y. N EE D T O M A KE N E W S YM BO L
XSTR
CH
2 -
VIN
3
X810988-001 SC70
5%
S ET T O 1. 8V
U SI NG U 5B 2 A S A N A DJ US TA BL E R 5B 1 = 5 4 9 O HM R 5B 2 = 2 2 1 O HM
IC
1
6
CH
U5B2
2
-
V_EFUSE
2
1
5% 1
1
IF
R5B3
U SI NG U 5B 2 A S A F IX ED R 5B 1 = E MP TY R5B2 = 0 OHM
4
2.9V
V_3P3 10K 5%
1
2
3
5%
0
D5N1 DIO SOD123 MBR130L
2
X803461-001
1UF 10% 16V X7R 603
VREG_EFUSE_EN_C2
VREG_EFUSE_EN_R
603
1
5
GND
CH
V_5P0STBY
2
2
C7T100
R6T1
2 ELEC RDL
1
V_5P0
1
VOUT
NC
10K 5% CH 402
5
R6T4
2
VREG_EFUSE_EN
IN
ENABLE
NCP502D
MBT3904
R1U2 E MP TY 475
3
U6T1
CR6T1 TYPE F IX ED ADJ
1
ADJUST/GND
10K 5% CH 402
2
475
2
VIN
R6T3
1 C _ N E _ E S U F E _ G E R V
R1U2
VREG_3P3_EN_R
2
OUT
X800499-001 DPAK 3.3V
1.0UF 10% 16V X7R 805
2
V_3P3STBY
IC
U5B1
EMPTY 402
VREG_V3P3_ADJ
1
1
R7T10
1%
R1F8
402
3
2
X807964-001
1
V_5P0STBY
0.1UF 10% 25V X7R 603
2
1
1
5% CH 402
2
1%
FT1U1
1 C1F3 100UF 20% 16V 2 ELEC RDL
C1F5
R1U1 1.27K
1
FTP
EMPTY LP2980
V_5P0
374
2 R _ L L P U P C _ G E R V
1%
2
EMPTY 402
1
2
C7P1 4.7UF 10% 6.3V X5R 805
C3C1
4.7UF 10% 6.3V EMPTY 805
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 9
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CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 56/82
REV 1.0
CR-57
:
@FALCON_LIB.FALCON(SCH_1):PAGE57
VCS REGULATOR
V_5P0
R7G23 0
805 1A
2
1
CH DB8U1
4
1
TP
CPU_SRVID
IN
2 1
R7T19
V_CPUCORE DB8U2
0
2
TP
5% EMPTY 402
2
1
2 2
R8U9
5% EMPTY 402
5%
V_CPUCORE
402
2
3
1
VREG_VCS_LTO
1
1
Q7F1
EMPTY 2N7002 SOT23
2
2
C7U5
1
DB8F4
C7U6 .1UF 10% 6.3V X5R 402
TP
1K
402
2
1
5% VREG_VCS_CPUCORE_R EMPTY
1
Q7U1 2
C8U9
MMBT2222 EMPTY
1
VREG_VCS_RT
2
.1UF 10% 6.3V X5R 402
2
NC2
12
COMP
R7U6
FB
D N G
HDRV
9
VREG_VCS_HDRV
LDRV
6
VREG_VCS_LDRV
PGND
8
1 C C N NSSOP
X811812-001
0
7
5
402 EMPTY 5%
4 1
S WI TC H
S TUF F E MP TY
2
1
VREG_VCS_COMP_C
1%
VREG_VCS_NC
C7U8
2
F RE Q
C7U7
C7G4 4 .7 UF 10% 16V X5R 1206
1
1 C7G7 1500UF 20% 16V
EMPTY 2 RDL
1
C7V2 0.1UF 10% 25V X7R 603
1
C7G5
10A NA
0.1UF 10% 25V X7R 603
1
C7F5 4.7UF 10% 16V X5R 1206
2
1
4 00 KHZ 2 00 KH Z
GATE0
3
SRC0
5 6
DRN0 DRN0
2
GATE1
1
SRC1
DRN1
FTP
FT7U3
1
TH
7 8
DRN1
1
L8F2 2
VREG_VCS_VOUT_L
1.7UH 13.8A
4
1 C7F4 820UF 20% 6.3V ALUM 2 RDL
SO-8
2 1
C7T103 4.7UF 10% 6.3V X5R 805
2 1
C7T102 4.7UF 10% 6.3V X5R 805
DB7U1
DB8U3
1
VREG_VCS_FB
VREG_VCS_COMP
R7U7
10K 402
2
1
47PF 5% 50V EMPTY 402
C7U11
R8U6
2.67K 402
2
2
1%
EMPTY
220PF 5% 50V NPO 402
1
R8U14 2
VREG_VCS_FB_R
2
1
1%
0
CH
402
VREG_VCS_FB_COMP
1
C8U5
5% EMPTY
2
ST7D2
1
SHORT
2
2700PF 10% 50V EMPTY 402
1
R7U8 4.02K
R8U12
1%
CH
2
4
V_CPUVCS
VREG_VCS_NC1
1 1
4. 7UF 10% 16V X5R 1206
TH
CR7V2 MBR0520L SOD123 EMPTY
3300PF 10% 50V EMPTY 402
EMPTY
C7G3
1
1
R 7U6
R7U5
1
2 EMPTY
FET
X807111-001
2
15K 402
4.7UF 10% 16V X5R 1206
IND
1
1
C8G4
2
IRF8915PBF
U7F1
IC
C V
IR3638
SS
11
1
3
R7U4
2
0 1
C C V
NC0 VP
13
4.7NF 10% 16V X7R 603
4
U7U2 3
VREG_VCS_SS_SD_N
1
TP
2
1
5% EMPTY 402
VREG_VCS_VP
DB7U2
1
1UF 10% 16V X7R 603
2
0
CH
1
C8F2
1UF 10% 16V X7R 603
2
1.6UH
R8U7
0
R7F9 10K 5% EMPTY 402
C7U9
1
R8U8 0
V_12P0
VREG_VCS_VREF
1
2
L7G1
1
V_VREG_VCS
V_12P0
402
GAIN=20% WITH R7U7=10K, OUTPUT = CPU_SRVID(1+GAIN)
33.2K
1%
R8U12=49.9K
CH
402
2
VREG_VCS_COMP_R 1
2
C7U10 0.01UF 10% 16V X7R 402
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :2 0
2 00 7
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CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 57/82
REV 1.0
CR-58
:
@FALCON_LIB.FALCON(SCH_1):PAGE58
XDK, 35 35
SPI_SS_N SPI_MISO
OUT IN
J1D2 2X5HDR_10 2 4 6 8
1 3
5
SPI_MOSI SPI_CLK
V_5P0STBY
35
OUT OUT
DEBUG CONNECTORS KER_DBG_RXD
35
7
33
OUT
SMC_DBG_RXD_R
9
60
OUT
C1D7
HDR
.1UF 10% 6.3V X5R 402
1
R2P18 2
100 402
SMC_RST_N
27
IN
5% CH
V_3P3STBY
V_5P0STBY
J9A2
1X2HDR N _ K
V_3P3 33
KER_DBG_TXD SMC_DBG_TXD SMC_DBG_EN
IN IN
34 34
OUT
2 4 6 8 10 12
SMB_CLK_R
1
2
C 2B 12
34
SMB_CLK
BI
1
9
1
SMB_DATA_R
11
R2N14 2
100 402
HDR
R2N13 2
100 402
SM HDR
C9A3 .1UF 10% 6.3V X5R 402
1 3
7
13
27
1UF 10% 16V X7R 603
5
C1R2 .1UF 10% 6.3V X5R 402
C 2B 15
.1UF 10% 6.3V X5R 402
R _ C M S
J2B1 2X7HDR_14
1
2
D X _ T S
EXT_PWR_ON_DBG
R3B3
1
1K
BI
2
EXT_PWR_ON_N
OUT
5%
27
34
44 58
34
CH
402
5%
SMB_DATA
5% CH
CH
V_12P0
V_5P0STBY
1
1
2
C3B8
D8B4
C3B9 1UF 10% 16V X7R 603
.1UF 10% 6.3V X5R 402
2
GREEN SM LED
1
CPU_CHECKSTOP_N_LED
R8B6 2K
1%
CH 402
2 CPU_CHECKSTOP_N_LED_B
CPU_CHECKSTOP_N_LED_C
3
1
R8A5 1K
J3C1
33 33 33 33
Q8B6
CH
2
MMBT2222 XSTR
V_3P3STBY
V_1P8
R2P19 10K 5% CH
2
1
3
IN IN
PEX_SB_GPU_L0_DP PEX_SB_GPU_L0_DN
4 6 8
7
IN IN
PEX_SB_GPU_L1_DP PEX_SB_GPU_L1_DN
10
9
PEX_GPU_SB_L0_DP PEX_GPU_SB_L0_DN
IN IN
5
12
11
14
13
16
15
18
17
20
19
22
21
24
23
X801071-001
N: FOOTPRINT PADS 13-24 REMOVED. N: REMOVED PADS FREE UP NEEDED BOARD SPACE FOR ROUTING.
PEX_GPU_SB_L1_DP PEX_GPU_SB_L1_DN
IN IN
2
13 13 13 13
1
4
CPU_RST_V1P1_N
IN
R8C2
2 1K
59 59 59 59
OUT OUT IN OUT
CPU_TMS CPU_TRST_N CPU_TDO CPU_TDI FT7R7
DEBUG CONN]
2
R8C3
FTP
1
402
10K 5% EMPTY 402
2
R8C4
1
10K 5% EMPTY 402
2
R8C5
1
10K 5% EMPTY 402
R8C6
1
1
10K 5% EMPTY 402
2
1
5% CH
CPU_RST_N_2_R
2 4 6 8
1
2 .1UF 10% 6.3V X5R 402
1
1 CPU_CHECKSTOP_N_R
1
R8C8 2
3
0
5
402
402
SMC_CPU_CHKSTOP_DETECT 34 BI
R8P8
C8P5
J8C1 2X5HDR
10K SMC_CPU_CHKSTOP_DETECT_B 5% 3 EMPTY 1 R3N8 2 Q2P1 402 1 MMBT2222 1K 5% EMPTY 402 EMPTY 2
CPU_CHECKSTOP_N
5%
IN
59
CH
CPU_TCLK EXT_PWR_ON_N
7
10
9
OUT OUT
59 44 58
34
HDR 1
2
[PAGE_TITLE=XDK.
2
V_1P8
EMPTY
PCIEX MIDBUS
1
5%
402
PCIEX DEBUG CONNECTOR N: DEBUG BOARDS ONLY I225 SM
2
C7D23 .1UF 10% 6.3V X5R 402
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 9
2 00 7
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CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 58/82
REV 1.0
CR-59
:
@FALCON_LIB.FALCON(SCH_1):PAGE59
V_GPUCORE U4D1
G PU Y 2
V ER SI ON
DEBUG BOARD,
CPU + GPU DEBUG BREAKOUT]
IC
7 OF 1 2
U7D1
1
TBCLK1 TBCLK0
58 58 58 58
G30 F32
IN IN IN IN
CPU_TCLK CPU_TDI CPU_TMS CPU_TRST_N
AF5 AH6 AH2 AH5
2 TB15 TB14 TB13 TB12 TB11 TB10 TB9 TB8 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0
D28 H29 E29 H30 C30 B30 A30 G31 B31 A31 B32 A32 F33 E33 D33 E34
C6T35 .1UF 10% 6.3V X5R 402
1
2
C7T90 .1UF 10% 6.3V X5R 402
1
2
C6T36 .1UF 10% 6.3V X5R 402
1
2
C7T91 .1UF 10% 6.3V X5R 402
V_GPUCORE
1
2
C6T12 .1UF 10% 6.3V X5R 402
1
2
C6T34 .1UF 10% 6.3V X5R 402
1
2
C7T92 .1UF 10% 6.3V X5R 402
1
2
TDO CHECKSTOP_B DEBUG_CLKOUT_DP DEBUG_CLKOUT_DN DEBUG_OUT0 DEBUG_OUT1 DEBUG_OUT2 DEBUG_OUT3 DEBUG_OUT4 DEBUG_OUT5 DEBUG_OUT6 DEBUG_OUT7 DEBUG_OUT8 DEBUG_OUT9 DEBUG_OUT10 DEBUG_OUT11 DEBUG_OUT12 DEBUG_OUT13 DEBUG_OUT14 DEBUG_OUT15 DEBUG_OUT16 DEBUG_OUT17 DEBUG_OUT18 DEBUG_OUT19 DEBUG_OUT20 DEBUG_OUT21 DEBUG_OUT22 DEBUG_OUT23 DEBUG_OUT24 DEBUG_OUT25 DEBUG_OUT26 DEBUG_OUT27 DEBUG_OUT28 DEBUG_OUT29 DEBUG_OUT30 DEBUG_OUT31 DEBUG_OUT32 DEBUG_OUT33 DEBUG_OUT34 DEBUG_OUT35 DEBUG_OUT36 DEBUG_OUT37 DEBUG_OUT38 DEBUG_OUT39 DEBUG_OUT40 DEBUG_OUT41 DEBUG_OUT42 DEBUG_OUT43 DEBUG_OUT44 DEBUG_OUT45 DEBUG_OUT46 DEBUG_OUT47 DEBUG_OUT48 DEBUG_OUT49 DEBUG_OUT50 DEBUG_OUT51 DEBUG_OUT52 DEBUG_OUT53 DEBUG_OUT54 DEBUG_OUT55 DEBUG_OUT56 DEBUG_OUT57 DEBUG_OUT58 DEBUG_OUT59 DEBUG_OUT60 DEBUG_OUT61 DEBUG_OUT62 DEBUG_OUT63 DEBUG_OUT64 DEBUG_OUT65 DEBUG_OUT66 DEBUG_OUT67 DEBUG_OUT68 DEBUG_OUT69
V_GPUCORE
1
IC
3 OF 1 0 LOKI
TCLK TDI TMS TRST_B
C6T31 .1UF 10% 6.3V X5R 402
X02125-001
CPU_TDO CPU_CHECKSTOP_N
AG5 AG1 D23 C23 F9 C8 E8
0 1
2
D7
3
B8 A8 F11 D9 C9 F13 A9 E10 C10 B10 E12 D11 A10 C11 A11 C12 F15 B12 E14 D13 C13 A12 C14 D15 C15 B14 E16 A13 A14 C16 B16 A15 A16 A17 D17 C17 F17 A18 B18 A19 C18 C19 D19 E18 C20 C21 E20 F19 A20 B26 B20 A21 A22 A26 B22 A24 A27 A23 A28 A25 F21 D21 B24 C22 E22 F23
4 5 6
OUT OUT CPU_DBG_CLK_DP OUT CPU_DBG_CLK_DN OUT CPU_DBGSEL_XDK<0..69>
58 58
OUT
47
N:CPU_DBGSEL_DEBUG<0..69> N:CPU_DBGSEL_XDK<0..69>
7
8 9 10
11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
X806937-001
[PAGE_TITLE=DEBUG
BOARD,
CPU + GPU DEBUG BREAKOUT]
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :1 9
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 59/82
REV 1.0
CR-60
:
@FALCON_LIB.FALCON(SCH_1):PAGE66
XDK DEBUG,
LEDS 2 R6G36 60
BI
60
BI
5% EMPTY
MEMPORT3_DN_ARGONYETI MEMPORT3_DP_ARGONYETI
1
2 R6G35 5% EMPTY
V_MEM
0
MEMPORT3_DN_ARGON MEMPORT3_DP_ARGON
402
49
BI BI
2
49
R7F6
1
0 5%
0
402
CH
J7G3
2
R6V2
5% EMPTY
0
402
5
MEMPORT3_DN_YETI
7
MEMPORT3_DP_YETI
2
R6V1
5% EMPTY
34
IN
9 11
1
CPU_PWRGD
2 R2D14
35
BI BI
MEMPORT3_DN MEMPORT3_DP
5% EMPTY
2
2
1 R7V8
2
[PAGE_TITLE=XDK,
DEBUG LEDS,
BDCM PHY]
V_MEMPORT1 1
C7G9
.1UF 10% 6.3V EMPTY 402
2 CPU_PWRGD_R
2 1
IN
46
C7G8
4.7UF 10% 6.3V EMPTY 805
1K
402
MEMPORT3_DN_ARGONYETI MEMPORT3_DP_ARGONYETI
BI BI
60 60
V_5P0
V_3P3
V_1P8
1 1
0
402 J1E2 1X5HDR
1
0
402
MEMPORT3_DN_FLASH MEMPORT3_DP_FLASH
R2R7
5% EMPTY
10 12
HDR
1
R2R8
5% EMPTY
N: CONNECTED TO V_MEMPORT FOR BETTER ROUTING
0
402
2 R2D13 5% EMPTY
V_YETI
0
402
5% CH
35
2 4 6 8
1 3
603
1
2X6HDR
1
1 0
402
1
2
1 2 3 4 5
C2T10 .1UF 10% 6.3V EMPTY 402
2 1
C1T6
4.7UF 10% 6.3V EMPTY 805
C2T9
2
.1UF 10% 6.3V EMPTY 402 1
C2T8
2
.1UF 10% 6.3V EMPTY 402 EMPTY TH
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :2 0
2 00 7
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 66/82
REV 1.0
CR-61
:
@FALCON_LIB.FALCON(SCH_1):PAGE67
INTELLIGENT
SERIAL
NUMBER TARGET.
LB7G1 LABEL 1
1375X250_TARGET X801181-001
MIDDLE EDGE
EMPTY
EDGE MTG9G1 MTG_HOLE 9 NC9
EMPTY
EMPTY
GND=1,2,3,4,5,6,7,8 CTR
MTG1G1 MTG_HOLE 9 NC9
GND=1,2,3,4,5,6,7,8 EDGE
MTG5B1 MTG_HOLE 9 NC9
EMPTY
MTG9B1 MTG_HOLE 9 NC9
EMPTY
GND=1,2,3,4,5,6,7,8
EMPTY
GND=1,2,3,4,5,6,7,8
HEAT SINK STD
EMPTY
GND=1,2,3,4,5,6,7,8
STD MTG3C1 MTG_HOLE 9 NC9
MOUNTING HOLES
EMPTY
GND=1,2,3,4,5,6,7,8 STD MTG3E1 MTG_HOLE 9 NC9
EMPTY
GND=1,2,3,4,5,6,7,8
STD MTG6C1 MTG_HOLE 9 NC9
EMPTY
GND=1,2,3,4,5,6,7,8
STD MTG8E1 MTG_HOLE 9 NC9
EMPTY
GND=1,2,3,4,5,6,7,8
STD MTG5C1 MTG_HOLE 9 NC9
EMPTY
GND=1,2,3,4,5,6,7,8
STD MTG5E1 MTG_HOLE 9 NC9
EMPTY
GND=1,2,3,4,5,6,7,8
PCI
GND=1,2,3,4,5,6,7,8
STD MTG6E1 MTG_HOLE 9 NC9
MTG8C1 MTG_HOLE 9 NC9
AND MOUNTING,
EAST PCB MOUNTING HOLES
MTG5G1 MTG_HOLE 9 NC9
GND=1,2,3,4,5,6,7,8 EDGE
[PAGE_TITLE=LABELS
PCB MOUNTING HOLES CTR
MTG1B1 MTG_HOLE 9 NC9
SWIZ]
EMPTY
GND=1,2,3,4,5,6,7,8
DRAWING FALCON_FABD T ue M ay 0 8 1 8: 24 :2 0
2 00 7
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CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 67/82
REV 1.0
CR-62
:
@FALCON_LIB.FALCON(SCH_1):PAGE68
GPU VID
BOARD 60
OHM COUPONS (TOP
& BOTTOM)
TP7M2 TDRX2
TDR_SINGLE_XDK2
90
TDR_DIFF_XDK3_DP
1 2
TDR_DIFF_XDK3_DN
3 4
DP GND
TP7M1 EMPTY TDRX2
DN
GND 1 2
TP5A2 TDRX4 1 2 3 4
EMPTY
SIG GND
THESE CONNECTORS ARE EMPTY BY DEFAULT THEY ARE ONLY STUFFED WHEN VIPER IS REQUIRED
TP5A1 EMPTY TDRX4
OHM COUPONS (TOP)
1 2
EMPTY
DP GND DN
SIG GND
J8B1 1X8HDR 53 53 53 53 53
IN IN IN IN IN
VREG_GPU_VID4 VREG_GPU_VID3 VREG_GPU_VID2 VREG_GPU_VID1 VREG_GPU_VID0
53
IN
VREG_GPU_VFFB
GND
1 2 3 4
TP8A2 TDRX2 TDR_SINGLE_XDK1
5 6 7 8
1 2
EMPTY
SIG GND
EMPTY TH
TP8A1 EMPTY TDRX2 THIS IS ON THE MOTHERBOARD T HE R ES T I S O N A S EP AR AT E B OA RD O N T HE F AN C U TO UT
100
OHM COUPONS (TOP
TP7A1 EMPTY TDRX4
& BOTTOM)
TDR_DIFF_XDK2_DP
1
TDR_DIIFF_XDK2_DN
2 3 4
J4F1
1X3HDR
GND
1 2
J4G1
55
OUT
VREG_V1P8_FB1
EMPTY
TP7A2 TDRX4 2 3 4
1 2
1X2HDR 50
OHM COUPONS (TOP)
TDR_SINGLE_XDK3
TDR_DIFF_XDK1_DN
THESE ARE ON THE MOTHERBOARD
DN
GND
DP GND
4
GND
TP6A1 EMPTY TDRX2
3
1 2
SIG GND
DN
TP8M2 TDRX4
4
EMPTY
SIG GND
DP GND
1 2 3
1 2
1 2
EMPTY
TP8M1 EMPTY TDRX4 TDR_DIFF_XDK1_DP
TP6A2 TDRX2
TH EMPTY
3
1
SIG GND
V_MEM
DP GND DN
1 2
EMPTY
DP GND DN
GND
MICROSOFT
CONFIDENTIAL
PROJECT NAME FALCON_RETAIL
PAGE 68/82
REV 1.0
