KEEE 2276 EXPERIMENT E1.07: DIFFERENTIAL AMPLIFIER (ELECTRONIC LAB) MOHD FUAD BIN SARMAN (KEE 120026) DEMONSTRATOR: MR. MOHAMMAD AL SAMMAN
ABSTRACT
This experiment is about the operation of the differential amplifier in two cases which each is conducted in different tests. The first test is to study on the operation of differential amplifier with asymmetric operating voltage while the second test is a study on the differential amplifier with asymmetrical operating voltage. This experiment also signify the importance of offset adjustment and the characteristics of differential amplifier itself.
INTRODUCTION
The differential amplifier is a fundamental building block of analogue circuits. Differential amplifier or briefly diff-amp is a special multi-transistors circuit configuration. The amplifiers available today are reliable, small in size, and consume a small amount of power. Diff-amp is the input stage of virtually every operational amplifier or op-amp, device used primarily to perform mathematical operations such as integration, subtraction, differentiation and addition. Op-amp has one output terminal and two input terminals. Perhaps one of the most important qualities of an op-amp is that it amplifies only the difference between its two input signals, while severely attenuating or rejecting signals common to both inputs. This allows op-amp to be used in electrical systems where a large amount of electrical noise is present. In this case the desired signal is amplified while the noise common to both inputs is
attenuated. This is made possible by the use of the diff-amp as the input stage of the op-amp. Hence the understanding of the diff-amp is vital to the understanding of op-amp. In this experiment, we examine the differential amplifier constructed from discrete components. We investigate the operation of the differential amplifier with both symmetrical and asymmetrical operating voltages.
Differential Amplifier Most operational amplifiers consist of a series of transistor, resistors, and capacitors forming a complete system on a single chip. The input stage of most operational amplifier is a differential amplifier. The differential amplifier is composed of two emitter-coupled commonemitter dc amplifiers with two inputs and three outputs. The differential amplifier have some special features as show below: 1. It contains two common-emitter amplifiers. 2. It is directly-coupled (emitter-to-emitter) amplifier. 3. It uses only resistors and transistors. Voltages may be applied to either or both input terminals and output may be taken from either or both output terminals.
DC Transfer Characteristics When signal input is large, the differential amplifier does not operate linearly. To simplify the analysis, we assume that RE is large, meaning that the base resistance of the transistor is negligible and that the output resistance of the transistor is large. You can see Figure 1 on previous page for verification. RE is used in the differential amplifier as the large value of resistor RE keeps the emitter-resistor voltage drop nearly constant. If V1-V2 becomes greater than several hundred millivolts, the collect current in Transistor Q2 becomes small and the transistor is essentially cut off. The collector current in Transistor Q1 is approximately equal to IEE and this transistor is saturated. The collector current and hence the output voltage VC becomes independent of the difference between the two input voltages. Linear amplification appears only for input voltage differences less than
approximately 100mV. In order to increase the linear range of the input voltage, small emitter resistors can be used.
Common Mode and Differential Mode The differential amplifier is intended to respond only to the difference between the two input voltages. However, in a practical operational amplifier, the output depends to some degree on the sum of these inputs. For example, if both inputs are equal, the output voltage should be zero but in a practical amplifier it is not. When the circuit responds to the difference, it is in the differential-mode. If the two inputs are made equal, the circuit is in its common-mode. Ideally, the circuit is expected to produce an output only in the differential-mode. If the two halves of the differential amplifier are identical, the ac output voltage will be zero. The differential amplifier is said to be perfectly balanced.
OBJECTIVE
To explain the operation of the differential amplifier as constructed from discrete components with both symmetrical and unsymmetrical operating voltage using voltage using this module.
RESULT AND DISCUSSION
TEST 1: DIFFERENTIAL AMPLIFIER WITH ASYMMETRICAL OPERATING VOLTAGE
UB (V)
UB1 (V)
UB2 (V)
UC1 (V)
UC2 (V)
14.92
7.37
7.38
11.73
11.73
Table 1 Voltages after the offset adjustment.
Table above shows the tabulation of initial value of the differential amplifier circuit with asymmetrical operating voltage after the offset adjustment in which UB1 = UB2. From the above result, we can see that when both of base input of respective transistor are the same, thus UC1 = UC2. This is because the offset adjustment that had be done to make the difference between two inputs is zero, UC1 - UC2 = 0 V. This offset adjustment to ensure that the signal from one transistor is delivered equally to the other transistor in which no different of signal in both transistors. UB1 (V)
UC1 (V)
UC2 (V)
+ 0.0 V
7.37
11.73
11.73
+ 0.1 V
7.47
11.34
12.06
+ 0.2 V
7.57
10.93
12.41
- 0.1 V
7.27
12.15
11.35
- 0.2 V
7.17
12.54
11.01
Table 2 Tabulated value of UC1 and UC2 when UB1 is changed.
The above results show when the input base voltage UB1 is increased, the collector voltage UC1 will decrease while UC2 is increases. However, once UB1 is decreased, a vice
versa output is resulted in which the drop happen in UC2 while UC1 is increased. Consider the following equation: VB
=
VBE + IERE ………………... (1)
VCC
=
ICRC + VCE + VEE ………… (2)
VC
=
VCC – ICRC ………………... (3)
By referring to figure 1 from the experiment manual, when UB1 is increased, there is an increment in the base-emitter junction forward bias, V1 which lead to the increment of base current IB1. Since the collector current IC = βIB, thus, IC1 will experience the increment in the proportion of β. With that increment, from equation (1), since VBE is fixed, this cause the emitter current to increase, thus also cause the emitter voltage to rise. This then cause the collector voltage, UC1 to drop as described in equation (2) and (3). Since the emitter voltage is increased and UB2 is fixed, this reduces the forward bias, V2 thus IB2 is decreased and causes IC2 is reduced thus results in the increment of UC2 as described in equation (2) and (3). When the value of UB1 is decreased, it will be a vice versa description of the above discussion. This validate the results in table 1.
Graph of UC1 and UC2 against UB1 12.8 12.6 12.4
UC1 & UC2 (V)
12.2 12 11.8
UC1
11.6
UC2
11.4 11.2 11 10.8 7.07
7.17
7.27
7.37
7.47
7.57
UB1 (V)
Graph 1 Graph of UC1 and UC2 against UB1.
7.67
The Significance of Offset Adjustment The input offset voltage is a parameter defining the differential DC voltage required between the inputs of an amplifier, to make the output zero. An ideal differential amplifier amplifies the differential input; if this input is 0 V, the output should be zero. However, due to manufacturing process, the differential input transistors of real differential amplifier may not be exactly matched. This causes the output to be zero at a non-zero value of differential input, called the input offset voltage. By referring to the circuit, ideally the output voltage UA should be zero when there are no input voltages. However, due to internal circuit mismatch, there is a slight difference in the base-to-emitter voltages of V1 and V2, resulting in a nonzero value of UA when there are no input voltages. Hence the offset adjust is necessary to correct this nonzero output voltage when there are no input voltages.
The Circuit Operation When UB1 is increased, the forward bias of base-emitter junction of transistor, V1 is increased cause the base current, IB1 to raise up which also makes the collector current, IC1 to increase by following the relationship IC1 = βIB1. This increment then cause the IC1R2 voltage to increase and thus result in the drop of UC1 as mentioned in equation (1). Since UB2 is constant, this reduces the forward bias, V2 thus IB2 is decreased which lead to the decrement of IC2 and thus caused an increment in UC2 as described in equation (2) and (3). When UB1 is reduced, V1 is decreased cause IB1 to decrease which also makes IC1 to decrease by following the relationship IC1 = βIB1. This decrement then cause the IC1R2 voltage to decrease and thus result in the increment of UC1 as mentioned in equation (1). Since UB2 is constant, this increases V2 thus IB2 is increased which lead to the increment of IC2 and thus caused a decrement in UC2 as described in equation (2) and (3).
TEST 2: DIFFERENTIAL AMPLIFIER WITH SYMMETRICAL OPERATING VOLTAGE
Scope 1 Sinusoidal AC signal of input Ue.
Scope 2 Sinusoidal AC signal of UC1 (upper wave) and UC2 (bottom wave) when UB1 = 200 mVpp and UB2 = 0 V.
Scope 3 Sinusoidal AC signal of UC1 (upper wave) and UC2 (bottom wave) when UB1 = UB2 = 200 mVpp.
UB1: 200 mVpp
UC1 (V)
UC2 (V)
UA (V)
0.880
0.820
0.060
0.096
0.094
0.002
UB2: 0 V UB1: 200 mVpp UB2: 200 mVpp
Table 3 Tabulation of UC1, UC2 and UA with different setting of applied sinusoidal AC signal of UB1 and UB2.
From the result above, when UB1 and UB2 are not the same, the difference between UC1 and UC2 are large (nonzero value) while when both UB1 and UB2 have the same voltage inputs, the difference become much smaller (zero value). In the first case, we found that UC1 and UC2 is out of phase and that the difference in the input voltages had been amplified while in the second case, the signal is in phase of each other results in zero output voltage.
Modes of Control This experiment implies two modes of control which are differential mode and common mode. Differential mode is when the input signal applied to both inputs UB1 and UB2 are different. In the experiment, the setup is when the base input V1 is supplied by sinusoidal AC voltage Ue1 while the base of V2 is connected to the reference point. Voltage is applied to one input and the other input is grounded in single-ended input differential mode; voltages of opposite polarity are applied to input 1 and input 2 respectively in double-ended input differential mode. The output voltage in this mode is nonzero and the voltage gain is very high. Common mode is when both base voltage, UB1 and UB2 are supplied with the same input signal. In this experiment, the setup is when the base input V1 is supplied by sinusoidal AC voltage Ue1 while the base of V2 is connected to the base of V1. Both UB1 and UB2 is supplied with the voltages of same phase, frequency and amplitude. Theoretically, this common mode will result in 0V output voltage in case of differential amplifier is ideal. In reality, the output voltage will be non-zero value however the voltage gain is very low.
Characteristic Properties of a Differential Amplifier i.
It has very high input resistance, so small voltage signals can be amplified without losses. But, it gives higher gain than two cascaded stages of ordinary direct coupling.
ii.
It provides very uniform amplification of signal from dc up to very high frequencies.
iii.
It uses no frequency-dependent coupling or bypassing capacitors.
iv.
Its temperature drift is minimum (almost negligible).
v.
It has two input terminals w.r.t. ground i.e. inverting and non-inverting inputs.
vi.
It can compare any two signals and detect any difference. It amplifies difference between two input signals only & rejects any external electrical noise.
vii.
It uses direct coupling of transistors (i.e. without capacitors); so the circuit can be fabricated in IC (i.e. integrated circuit) form.
viii.
It provides isolation between input and output circuits.
CONCLUSION
To conclude, when the differential amplifier is operated with asymmetrical voltage and when the differential amplifier has been offset adjusted, the collector voltages are the same when the base voltages are the same. When the base voltage of the first transistor is increased, its collector voltage decreases and the collector voltage of the second transistor increases. The vice versa observation is obtained when the base voltage of the first transistor is decreased. When the differential amplifier is operated with symmetrical operating voltage, the output voltage is zero when the input voltages are the same and that the difference of the input voltages is amplified when the input voltages are unequal.
REFERENCES [1] Donald A. Neaman, “Differential and Multistage Amplifiers,” in Microelectronics: Circuit Analysis and Design,th ed. New York, NY, 2010, ch. 11, sec. 11.1, pp. 754 – 800. [2] C. J. Savant, Jr., Martin S. Roden, Gordon L. Carpenter, “Electronic Design: Circuits and Systems,” Second Edition, The Benjamin/Cummings Publishing Company, Inc. [3] Dharma Raj Cheruku, “Differential Amplifier,” in Electronic Devices and Circuits, 2nd ed. India: Pearson Education India, 2008, ch. 13, sec. 13.4, pp. 564–568.
APPENDIX TEST 1: DIFFERENTIAL AMPLIFIER WITH ASYMMETRICAL OPERATING VOLTAGE
Diagram A1 UB1 = UB2 = 7.37 V
Diagram A2 UB1 = 7.47 V
Diagram A3 UB1 = 7.57 V
Diagram A4 UB1 = 7.27 V
Diagram A5 UB1 = 7.17 V
TEST 2: DIFFERENTIAL AMPLIFIER WITH SYMMETRICAL OPERATING VOLTAGE
Diagram B1 UB1 = 200mVpp, UB2 = 0 V
Graph B1.1 Ue1
Graph B1.2 UC1 and UC2
Diagram B2 UB1 = UB2 = 200mVpp
Graph B2.1 UC1 and UC2
