Semester 2 Reports INTRODUCTION This booklet contains all the written reports for the lab b ased experiments for semester 2, which are focused on analog electronics. electronics. Nowadays, most applications adopt a digital approach, leaving us with the impression that the analog circuits are gradually disappearing. However, this is n ot the case as the pervasiveness of digital circuits has only increased the importance of anolog electronics. The analog nature of electronic signals is of great importance as the real w orld itself is analog where even in modern microchips; the digital circuits exhibit analog behaviours. This report presents the detailed design and expe rimental evaluation of the six experiments based on analog electronics conducted during the second semester in the electronics laboratory which considerably improved our understanding in the concept of analog electronics. The experiments were performed by Sunnoo Dishan, Bhowon Anshuman and Chamane Neekita in the electronics laboratory under the supervision of Mr M.Bheekaroo. The lab experiments and the dates when they were performed are as follows:
Expe Ex perr iment No.:
Ex per per i ment base based on:
Date Dat e per per f orme orm ed:
1.
Capacitor in d.c and a.c circuits
04 feb 2014
2.
The Semiconductor Diode
04 feb 2014
3
Rectification
04 feb 2014
4.
Limiting or Clipping and Clamping Networks
11 Feb 2014
5.
Transistor Amplifier
11 Feb 2014
6.
nalog computing
18 Feb 2014
In addition, for the completion of the report, the software ‘livewire’ was used to implement and check the circuits, and the books, electronic books, lab sheet theories and the internet were used for the referencing part.
Our sincere appreciation should be extended to our laboratory instructor, Mr M.Bheekaroo and our lecturer, Mr Y.K.Ramgolam for their valuable instructions, guidelines and assistance.
Semester 2 Reports
1. Capacitor in dc and ac circuits 1.1 Introduction
The objectives of the experiment are to analyze the charging and discharging of a capacitor and to inspect the reactance of a capacitor with respect to frequency. 1.2 Theory
A capacitor is a device for storing charge. It consists of 2 metal plates separated by an insulator known as a dielectric. The circuit below consists of a capacitor with plates A and B.
capacitor B
+ -
A
R
+
-
Figure 1.0 shows capacitor with plates A and B 1.2.1 Charging of a capacitor When the capacitor is connected to the battery, electrons flow from the negative terminal of the battery and accumulate on plate A of the capacitor. Simultaneously, electrons flow from plate B of the capacitor to the positive po sitive terminal of the battery. Equal positive and negative charges get accumulated on their respective plates. The capacitor is said to be fully charged when wh en the potential difference across it is equal to the battery voltage. 1.2.2 Discharging of a capacitor When the battery is removed and plates A and B are joined by connecting wires, electrons flow from plate A to plate B causing current cu rrent to flow for some time until the positive charges on plate B are neutralized. The capacitor is said to be discharged. 1.2.3 Capacitive Reactance It is defined as the opposition to the flow of charge. It is measured in ohm and is obtained as follows:
(equation 1.0)
Semester 2 Reports 1.3 Instrumentation
Power supply (AC and DC) 33 K and 100 R resistors Oscilloscope 100 µF electrolytic capacitor 47 nF capacitor
1.4 Procedure (a) Charging and discharging of a capacitor
1. A 100 µF electrolytic capacitor and a 33 KΩ resistor were connected as shown below.
Figure 1.1 circuit for expt (a) It was made sure that the capacitor was introduced with the polarity the correct way round. 2. When a trace on the oscilloscope was obtained, the time-base was set to 1 ms/cm and the horizontal line set to zero volts on the center line of the screen. DC coupling coup ling was selected for the CH1 input and 5 V/cm on the CH1 sensitivity. 3. The dc supply was turned on and adjusted to 15 V, Observations were noted. 4. The 33 KΩ resistor was pulled out and the power turned off. 5. The 33 KΩ resistor was inserted back again and observations and observations made.
Semester 2 Reports (b) Inspection of the reactance of a capacitor
1. The circuit was connected as shown below.
Figure 1.2 Circuit for expt (b) 1. 2. The signal generator was selected to produce 2 KHz sine wave and the output level adjusted to 2 V peak – peak – to – to – peak peak signal across the capacitor. 2. The waveform across the 100 R resistor was measured and recorded. 3. The experiment was repeated with frequencies ranging from 1 to 10 KHz, maintaining a level of 2 V across the capacitor cap acitor and measuring the voltage across the resistor. 4. The reactance Xc was calculated using the formula:
(Equation 1.1)
5. Where Vc = 2 V. 6. The theoretical values of Xc was then calculated using the formula:
(Equation 1.2)
7. The values were recorded in tabular form and plotted on graph.
Semester 2 Reports 1.5 Results (a) Charging and discharging of capacitor
The picture below shows the signal obtained when the capacitor is charged.
Figure 1.3 CRO showing signal obtained when capacitor is charged
As it can be observed, the horizontal line moves vertically up to 14.7 V (approximately 15 V). The signal below was obtained when the capacitor was discharged.
Figure 1.4 CRO showing signal obtained when capacitor is discharged
Semester 2 Reports (b) Inspection of the reactance of a capacitor
The table below shows the experimental values obtained and the reactance derived from them. F / KHz
1 2 3 4 5 6 7 8 9 10
VR (peak to peak) / mV 64 165 170 222 300 330 410 430 505 530 Table 1.0
IR / mA
Xc / Ω
0.64 1.65 1.70 2.22 3.00 3.30 4.10 4.30 5.05 5.30
3125 1212 1176 900.9 666.7 606.1 487.8 465.1 396.0 377.4
The table below shows the theoretical values of the reactance. Xc/ Ω
F / KHz 1 2 3 4 5 6 7 8 9 10
3386 1693 1129 846.6 677.3 564.4 483.8 423.3 376.3 338.6 Table 1.1
The graph on the next page was plotted for both the experimental values and theoretical values of reactance.
Semester 2 Reports Graph of Reactance X/ohm against Frequency/ f
Figure 1.5 showing graph of Reactance against frequency
1.6 Discussion and Conclusion (a) Charging and discharging of a capacitor
The horizontal line moves up to 14.7 V showing that the capacitor charges to 14.7 V. When the 33 KΩ resistor is re – inserted, it is observed on the C.R.O that the horizontal line moves down to the 0 V line, that is, the x – axis. This implies that the capacitor is discharges to 0 V. (b) Inspection of the reactance of a capacitor
From the graphs obtained, it can be observed that the theoretical values are close to the values obtained during the experiment. The slight differences may be due to heating of wires. It can be observed that the reactance decreases steeply for low frequencies bu t less steeply for higher frequencies.
Semester 2 Reports Precautions:
1. It was made sure that no loose connections were left behind before starting the experiment. 2. The components and wires were carefully connected ensuring that they do not get damaged, particularly the pins. 3. Care was taken while fitting components into the breadboard so as not to damage them.
2.The Semiconductor Diode 2.1 Introduction
This practical was conducted for the determination of diode polarity and for the analysis of the characteristics of Forward Bias Diodes. 2.2 Theory
A Semiconductor Junction Diode is made from a piece of P-type and a piece of N-type semiconductor joined together. It is made of semiconductor materials such as silicon, germanium and gallium arsenide (GaAs).
Figure 2.0 shows diode circuit symbol and internal structure for a P-N junction diode.
Semester 2 Reports
Figure 2.1 Diode IV characteristic Reverse biasing the diode
To reverse bias the diode, an external potential must be applied to it such that the anode is at a negative potential and the cathode is at a positive potential. When this is done the external potential adds to the built-in-potential to increase the opposition to the flow of majority carriers in the diode. The increasing opposition widens the depletion region and hence hardly any majority carriers can flow across the junction.
Semester 2 Reports 2.3 Instrumentation
Breadboard DC power supply Digital multi-meter Diode (1N4007) Resistors( 4K7,100R)
2.4 Procedure (i) Determining Diode Polarity The circuit is constructed as shown in figure below. i. 4K7 10V dc
1N4007
V
A
0v
Figure 2.2 circuit (ia)
1) The power supply control is adjusted to give 10V on the voltmeter. 2) The corresponding value of the diode current from the ammeter is recorded. 3) The power is switched off and the 1N4007 diode is reversed to give the circuit as shown below. 4K7 10V dc
1N4007
V
A
0v
Figure 2.3 circuit (ib)
4) The power supply is switched on and the voltage readjusted to 10V reading. 5) The new value of diode current is read and recorded.
Semester 2 Reports
ii.
The Characteristics of Forward Biased Diodes
1) The circuit is constructed as shown below. VR
100R
1N4007
Vs
Vd
Figure 2.4 circuit (ii) 2) The potentiometer of the supply is adjusted to zero; after which it is varied to set VS to 0V, 0.1V, 0.2V, etc up to 1.0V. 3) The value of VR for each setting is recorded. 4) For each set of reading of VS and VR . the corresponding values of the diode voltage (Vd) and the diode current (If ) are calculated using the following equations. Vd = Vs – VR and VR = If x 100; If = (VR / 100) A = (VR / 100) A x 1000mA; If = 10 VR mA 5) A graph of Vd against If is plotted.
2.5 Results , Questions & Discussions (i)
Determining Diode Polarity
Circuit
Current (mA)
Figure 1
2.09
Figure 2
0.00
Table 1.0
Semester 2 Reports Questions: 1. Which side of a di ode shou ld be connected to the positive voltage suppl y to make it conduct current?
The anode (P-type) of the diode should be connected to the positive voltage supply in order to make it conduct current. This is because it is then that, the voltage applied across the diode opposes its built-in potential reducing the size of the depletion region. This allows the transfer more of majority carriers between the p-type and the n-type material, which allows the flow of a current.
1. When the diode was connected the opposite way roun d was the cur rent? c) too small to measure When the N type cathode is connected to the positive terminal, that is when it is reverse biased, the positive holes are attracted towards the negative voltage and away from the junction. Likewise the negative electrons are attracted awa y from the junction towards the positive voltage applied to the cathode. This action leaves a greater area at the junction without any charge carriers left. This causes the depletion layer to widen. The applied voltage attracts more charge carriers away from it. The diode will not cond uct with a reverse voltage (a reverse bias) applied. (ii)
The characteristics of Forward Biased Diodes
Results:
Table 1.1 Vs (V)
VR (mV)
VR (V)
Vd=Vs-VR (V)
If = 10VR (mA)
0.0
0.0
0.0
0.000
0.000
0.1
0.0
0.0
0.100
0.000
0.2
0.5
0.0005
0.200
0.005
0.3
3.6
0.0036
0.296
0.036
0.4
13.5
0.0135
0.387
0.135
0.5
69.3
0.0693
0.431
0.695
0.6
129.8
0.1298
0.470
1.298
0.7
186.9
0.1869
0.513
1.869
0.8
279.1
0.2791
0.521
2.791
0.9
368.8
0.3688
0.531
3.688
1.0
412.0
0.4120
0.588
4.120
Semester 2 Reports Graph of V d against I f Vd/ V 0.6
0.5
0.4
0.3
0.2
0.1
If/ mA 0.5
1
1.5
2
2.5
3
3.5
4
Figure 2.5 Graph of Vd against If Questions:
1. At what approximate value of V d does the cur rent I f begin to rise noti ceably? At Vd ≈ 0.35V
2. Does V d rise much above thi s value for lar ger values of I f ? From the above graph, it can be deduced that for larger values of If , Vd increases slightly for a range of 0.2V till Vd is approximately equal to 0.6V. This is because once the built-in potential of the diode is overcome, the size of the depletion region reduces hence resulting in a significant increase in current (If ) with a small variation in the voltage (Vd) across the diode.
3. I s it a germaniu m or sil icon diode? It is a germanium diode as the built in potential is approx Vd ≈ 0.35 V
Semester 2 Reports 2.6 Precautions taken during the experiment
Loose connections were avoided.
Before conducting the practical, the resistors and diodes should be tested using millimeters.
The power supply must be switched off each time the connections were altered.
Care was taken while fitting the components into the breadboard so as not to damage them.
3. Rectification 3.1 Overview of experiment:
This experiment studies the simplest circuits for achieving the conversion of signals from ac (alternating) to dc (direct) forms. Semiconductor diodes are used to rectify ac signals and are commonly referred as rectifiers. In this experiment, three types of rectification processes are encountered mainly half-wave, the effect of a reservoir capacitor and full-wave rectification from a single phase ac supply. 3.2 Introduction:
3.2.1Half-wave rectification: In half wave rectification of a single-phase supply, either the positive or negative half of the AC wave is passed, while the other half is blocked depending on the direction of the diode with respect to the supply voltage. Half-wave rectification requires a single diod e in a single-phase supply, or three in a three-phase suppl y. Rectifiers yield a unidirectional but pulsating direct current. As depicted in figure 3.1 (a) and (b), the half-wave rectifier takes as input an a.c signal and rectifies only the positive half cycles of the inpu t signal producing an output voltage waveform [figure 3.1 (b)]. Because only one half of the input waveform reaches the output, mean voltage is lower. From the circuit below, the negative h alf of the input voltage is truncated and the peak voltage of the positive half cycle is reduced by the built-in potential of the diode (V D or φk ).
Semester 2 Reports
Figure 3.1 (a) Half rectifier circuit
(b) Input and output waveforms of half rectifier
The rectified voltage output voltage unlike the input a.c voltage has a non-zero mean (average) voltage given by the following equation:
Vmean= x V pk
(Equation 3.0)
V pk : amplitude of the rectified voltage waveform Vmean: average voltage of output voltage 3.2.2Full-wave rectification: Full-wave rectification produces an output voltage with lesser ripples than h alf-wave rectified ones. The full-wave bridge rectifies both positive and n egative half-cycles of the input sinusoidal voltage. To provide unipolar output, it inverts the negative half cycles of the input a.c signal. The bridge rectifier [figure 3.2(a) and (b)] consists of four diodes (D1, D2, D3 and D4) to accomplish its tasks. During the positive half cycles of the input voltage (Vs>0), the current is conducted form positive terminal of Vs through diode D1, resistor R and diode D2. Meanwhile diodes D3 and D4 are reversed biased. During the negative half- cycles of the input voltage (Vs<0), current flows from the negative terminal of Vs through D3, R and D4. Meanwhile D1 and D2 are reverse biased. It is noted that during both half cycles, current flows through R in the same direction (from right to left) and thus output V 0 stays positive.
Semester 2 Reports
Figure 3.2(a) Full wave diode bridge
Figure 3.2(b) Input and output waveform
There are two diodes in series in the conduction path and thus V0 is less than Vs by two built in potential drops compared to one drop in the half wave rectifier circuit. The average dc voltage of the full wave rectified waveform is twice that of the half wave one.
Vmean= *V pk
(Equation 3.1)
3.2.3Rectification with Reservoir capacitor: For both the half wave and full wave rectifiers, we see that the output is not a steady direct voltage because it fluctuates. The solution to reduce the variation of the output voltage is to place a filter capacitor across the load resistor. The capacitor charges to the peak (Vpk) of the output d.c. voltage Vo from the rectifier. Then as Vo decreases from its peak value, the capacitor discharges through the load resistance R and continues doing so for almost the entire cycle, until the time at which Vo exceeds the capacitor voltage where the capacitor charges again to Vpk. This process repeats itself producing an output voltage with fewer fluctuations across R. To avoid the output voltage from decreasing too much during capacitor discharge, a large value for C is chosen so that the time constant CR is much greater than the discharge interval.
Semester 2 Reports 3.3 Equipment used:
Breadboard Diodes (1N4007) Capacitors CRO Ac signal generator Resistors (10 kΩ) Voltmeter
3.4 Procedure: i) Half-wave rectification
1. A circuit is set up as shown below (figure 3.3) by connecting a diode in series with a load resistor R with magnitude 10kΩ. This combination is conn ected to a 50 Hz ac signal generator. The peak-to peak voltage of the signal is adjusted by viewing it from a cathode ray oscilloscope.
Figure 3.3: half wave rectification 2. The output voltage is taken across the resistor and is observed on another channel of the CRO. The channel is a.c coupled and the time base and the Y amplifier sensitivity are adjusted to obtain a steady trace. A waveform as shown in figure 3.4 below is expected.
Figure 3.4: Half wave rectified waveform
Semester 2 Reports 3. The time period T and the peak voltage Vpk are then measured and recorded. The mean voltage is measured using a voltmeter. ii) The Effect of a Reservoir Capacitor
1. The previous half-wave rectified circuit is modified by conne cting a 2.2 µF capacitor across the load resistor R as shown in figure 3.5 below.
Figure 3.5: Half wave rectification with reservoir capacitor C 2. The output is taken across the parallel combination of the load resistor R and the reservoir capacitor C, and is observed using a CRO. The time-base and the Y amplifier sensitivity are adjusted to obtain a steady trace. According to theory, a steady direct voltage free from variations of the sort observed in figure 3.6 must be obtained. The amplitude V pk is measured from the trace and the mean voltage of the waveform is measured with a voltmeter.
Figure 3.6: The effect of reservoir capacitor 3. A larger capacitor is then used (50 µF) and the same procedural step 2 is repeated.
Semester 2 Reports iii) Full- wave Rectification
1. A diode bridge circuit consisting of 4 diodes is set up as shown in figure 3.7 (a).
Figure 3.7 (a): Diode bridge circuit
2. A capacitor is then connected in parallel to the load resistor R (figure 3.7 (b)) and the output waveform, the value of Vpk and also the mean voltage of the output waveform is analyzed.
Figure 3.7 (b): Diode bridge circuit with capacitor
Semester 2 Reports 3.5 Results and Discussions:
Half-Wave Rectification
Figure 3.8 Graph of voltage against time Peak Voltage, Vpk= 9.3 V Mean voltage recorded by voltmeter, Vmean = 2.65 V Time period, T= 20 ms Question
I s the V pk equal to the peak voltage of th e alternati ng supply? And i f not equal, why? The peak value of the rectified waveform, Vpk is not equal to the peak input ac voltage because when the diode is conducting, there is a built in potential (φk) across it. Therefore, at that time the output voltage (Vout) across the load is given by: Vout= supply voltage (Vs)-φk
Semester 2 Reports
Effect of Reservoir Capacitor
Figure 3.9 effect of reservoir Capacitor i)
C=2.2 µF
ii)
C=50 µF
Peak voltage, Vpk= 9.3 V
Vpk=9.3 V
Mean voltage, Vmean=4.49 V
Vmean=8.33 V
Questions:
1) I s the mean voltage with the 2.2 µF capacitor added greater or less than i t was before? The mean voltage is greater with the 2.2 µF capacitor than it was before. It is now 4.49 V as compared to 2.65 V previously. This is due to the capacitor charging to the value:
Vs-φk and
then discharging across the resistor R at a rate based on the time constant (RC) maintaining a non-zero output voltage over the full cycle.
2) The variati ons on the rectif ied wavefor m are call ed RI PPLE. I S the ripple with the lar ger capacitor i s less than or mor e than it was with the lower value capacitor? The ripple is much less with the higher capacitor (50 µF) than with 22 µF capacitor. The output voltage is even smoother with the larger capa citor. This is because a capacitor with larger capacitance can store more charge and takes time to discharge, hence smoothing the output voltage even more with lesser ripples.
3) I s the mean rectif ied voltage now gr eater or l ess? The mean rectified voltage is now greater with large capacitors.
Semester 2 Reports
Full wave Rectification
Figure 3.10 Full wave Rectification Questions:
1. I s Vpk be the same as it was for a half wave rectif ier? Wh y? The peak value of the full rectified signal is smaller than the peak value of the half wave rectified signal. This is because of the two diodes conducting at a time in the full rectified bridge circuit implying that total voltage across them is 2 * φk. Vout hence becomes Vs- (2* φk) thus having smaller magnitude compared to half wave rectified one.
2. H ow does the mean value compared with that f ound f or h alf wave rectification? The mean output voltage for the full wave rectifier is approximately twice to that of the half wave rectified one. 3.6 Precautions taken:
The capacitor was connected correctly according to polarity Care was taken while handling and fitting the components into the breadboard so as not to damage the components. The sensitivity of CRO was increased to obtain a steady trace. Loose connections were avoided. It was ensured that the applied voltage and current never exceeded the maximum rating of the components
Semester 2 Reports
4.Limiting or Clipping and Clamping Networks 4.1 Introduction
The objective of the experiment is to analyse the functioning of clipper and clamper circuits and observe their effect on a signal. 4.2 Theory
4.2.1 Clipper Network A clipper (diode limiter) circuit is one which removes part of an inpu t signal. It usually consists of resistors, a diode, an AC source and may also include a DC source sometimes. Clipper circuits are categorized into two parts: 1) Series clipper circuit – output is read across the resistor. It can be biased or unbiased. Biased implies that a DC source is present while un biased implies that a DC source is absent. 2) Parallel clipper circuit – output is read across the diode. Just like the series clipper circuit. It can also be biased or unbiased.
4.2.2 Clamping Network A clamper circuit is also known as a DC restorer. In other words, it adds a constant DC only to an input signal. A clamper circuit consists of a diode , resistor, capacitor, an input signal and ma y at times contain a constant DC source. Clampers can be biased or unbiased. Biased clampers usually have a DC source present in the circuit.
Semester 2 Reports
4.3 Equipment Used
Breadboard Cathode Ray Oscilloscope Diodes (1N4007) Electrolytic capacitor (1 µF) Resistors ( 8K2 10K, 220K) Signal Generator
4.4 Procedures (a) Experiment 1
1) The series limiter was constructed as shown below.
Figure 4.3 Circuit (a)
2) The output on the CRO was observed and the waveform recorded. 3) The diode was then reversed and the output recorded.
Semester 2 Reports (b) Experiment 2
1. The series limiter was constructed as shown below.
Figure 4.4 Circuit (b) 2. The output on the CRO was observed and the waveform recorded. 3. The diode was then reversed and the output recorded. (c) Experiment 3 1.The shunt limiting was constructed as shown below.
Figure 4.5 Circuit (c) 2.The output was recorded. The diode was reversed and output recorded.
Semester 2 Reports (d) Experiment 4
1.A second diode was added to the circuit as shown below.
Figure 4.6 Circuit (d) 2.The output was recorded. (e) Experiment 5
1. The clamping circuit below was constructed.
Figure 4.7 Circuit (e) 2.A square wave of 100 Hz was applied and the output recorded. The DC components of the waveform were determined in both the forward and reverse biased diode position. The CRO was set in the DC mode. The diode was reversed and the waveform recorded.
Semester 2 Reports 4.5 results
Figure 4.10
Figure 4.11
Semester 2 Reports iii.
Experiment iiii Shunt limiting
Diode in original direction Input signal: blue output signal:
Diode in reverse direction Input signal: blue output signal: yellow
yellow
iv.
Experiment iv
v.
Experiment v
When diode is in original direction
When diode is in reverse direction
Figure
Figure
Input signal: yellow
Input signal: yellow
Output signal: blue
Output signal: blue
Semester 2 Reports 4.5 Discussion and Conclusion (a) Experiment 1
During the positive half – cycle of the input signal, the diode does not conduct resulting in the output voltage to be 0 V. During the negative half – cycle, the diode conducts when input voltage becomes greater than the built – in potential of the diode. The output voltage obtained is negative as diode conducts only for the negative half – cycle of the input signal. When the diode is reversed, the latter conducts only during the positive half – cycle once the input signal becomes greater than the built – in potential of the diode. As it was observed, output voltage was positive as it was measured for the po sitive half – cycle of the input voltage. For negative half – cycle, output voltage is 0 V as diode does not conduct. (b) Experiment 2
As per the circuit, the diode is forward biased and will conduct only during the positive half – cycle of the input signal. The diode conducts when the input signal is greater than the built – in potential of the diode. During the negative half – cycle, the output is the same as the input voltage signal as the diode does not conduct resulting in the output voltage being the same as the input voltage. When the diode in the circuit is reversed, the latter conducts only during the negative half – cycle. The output voltage will be equal to the built – in potential of the diode. During the positive half – cycle, the output will be the same as the input. (c) Experiment 3
The diode is forward bias during the positive half – cycle of the input signal and conducts when the input voltage is greater than the built – in potential. The output measured is equal to the built – in potential of the diode. During the negative half – cycle, the diode is reverse biased and will therefore not conduct. The circuit will be one with the 2 resistors in series. The output voltage will be: Vout = Vin / 10K + (10K+8.2K)
Semester 2 Reports When the diode is reversed, the diode will conduct only during the negative half – cycle of the input voltage.During the positive half – cycle, the output voltage is given by: Vout = Vin / 10K + (10K + 8.2K (d) Experiment 4
During the positive half – cycle, the diode to the left is forward bias while the one on the right is reverse bias. The output voltage observed is equal to the built – in potential of the conducting diode and is positive. During the negative half – cycle, the diode to the left is reverse bias while the one on the right is forward bias. The output voltage observed is equal to the built – in potential of the conducting diode and is negative. (e) Experiment 5
During the positive half – cycle of the input signal, the capacitor charges to a DC voltage and when it becomes equal to the peak input voltage, the diode is reverse bias and therefore does not conduct. The circuit is then comprised of the input voltage, the charged capacitor equivalent to the DC supply and a resistor across which Vout is measured. Vout will be the resultant of Vin and the capacitor’s DC voltage. Vout = Vin - Vcapacitor When the diode is reversed, the capacitor charges during the negative half – cycle. It gets charged with polarity opposite to the one it had with the diode in its original positin. Therefore,
Vout = Vin + Vcapacitor
4.6 Precautions
The components were installed on the breadboard with utmost care so as not to break their pins.
It was ensures that the applied voltage did no t exceed the maximum ratings of the components.
Semester 2 Reports
5.TRANSISTOR AMPLIFIER 5.1 Brief overview of the experiment:
This practical is based on the analysis of the basic configuration of an amplifier circuit, where the current gain of the amplifier is determined and the operation of the common emitter amplifier is investigated. Also, the amplifier circuit was modified and investigated by direct coup ling to load, and by adding coupling capacitors. 5.2 Theories concerning the experiment: Rs
Biased Transistor RL
VL
A.C input signal
load
Amplifier
coupling
fig 1
coupling
The basic configuration for an amplifier circuit is shown in figure 5.1. The amplifier itself is a transistor biased in the forward active region, where
B F is the current gain and is also denoted by
H FE
Ic
F I B where
.Two examples of biasing configurations are
shown in fig 5.2 and fig. 5.3.
+Vcc
+Vcc
RB
.R2.
Rc
R3
RE
Rc
0V
Figure 5.2:Fixed Bias
Figure 5.3 Potential-divider biasing
Semester 2 Reports The signal to be amplified is applied to the base of the transistor usually via a large coupling capacitor. This produces a small modulation of the base voltage from the static value (when no signal applied).
Figure 5.4
As a consequence, IB is also modulated with respect to the input signal. If the transistor stays in I C F I B the forward active region, and the small change in base current gives rise to large changes in Ic (because F 1 normally). Hence an amplified version of the input signal appears at the output of the amplifier. As an example, consider the amplifier circuit in fig .5.5 +Vcc
RB
Rc
C1 Vo Vs
Figure 5.5 Amplifier Circuit
Semester 2 Reports In this case, capacitive coupling is used at the amplifier’s input and the output is open-circuited (no load). When no signal Vs is applied, Vo assumes a static value Vo, d.c. When no signal is applied Vo varies about Vo, d.c. In mathematical terms,
Vo = Vo,dc + Vo,ac ……Eq(1)
Where Vo, ac is the varying component of Vo.
The ac voltage gain of the amplifier, Av, is defined as
Av = Vo,ac/Vs ……..…Eq(2)
It can be shown that, for the circuit of fig 5.5
Vo,dc = Vcc – RcIc ……………………Eq(3)
Av
And
Vo V s
g m R c
…………………… Eq(4)
g m is the transconductance and is given by
Where
g m 40i c
5.3 Objectives:
Determination of hfe, that is, the current gain of the amplifier. Examining the Common Emitter (CE) amplifier characteristics of transistor. Investigating Direct Coupled Amplifiers. Investigating capacitively coupled amplifiers.
Semester 2 Reports 5.4 Equipment required:
DC power supply; Function generator; Oscilloscope; Voltmeter; Transistor; 100K, 1K, 470 and 220 Ω resistors; 2 capacitors, 1 μF each.
5.5 Procedures: (i)
Experiment 1: Determination of h fe
1) The circuit is constructed as shown below, in figure 5, using R=1KΩ. 12v
R
100k
vo 0v fig 5
2) With no input signal, the d.c voltage, Vo and VBE are measured and recorded. 3) The d.c current gain of the amplifier is calculated. d.c current gain may be be given as follows: IB (12 V BE .)/100K Ω IC (12 - Vo) /R d.c current gain hFE
IC IB
Semester 2 Reports (ii)
Experiment 2: The CE amplifier
12v
220
100k
To CRO c1
vo
Vin
0v fig 6
1) The circuit is connected as shown below, in figure 6, where C1 is 1μF. 2) The signal generator is connected to the input of the amplifier and it is adjusted to give a sine wave of frequency 10 KHz. 3) The amplitude of the input signal is adjusted to give an undistorted sinusoidal output, V0. 4) The oscilloscope is adjusted to measure dc signals and the amplitude of the input signal, the amplitude of the a.c component of V0(V0, a.c), the d.c component of output voltage, V0(V0, d.c) are measured and recorded. 5) The ac voltage gain, Av, of the amplifier is calculated which is given by: Av = Vo.ac/ Vin 6) The theoretical value of Av and Vo,d.c are calculated. (iii)
Experiment 3: Direct Coupling to load
1) The circuit is connected as shown in the figure below, using R L = 470Ω and C1=1μF. 2) Steps 2 to 5 of experiment 2 are repeated and values of Av and V0,d.c are compared with 12v
220
100k
c1
RL
Vi n
0v
fig 7
those obtained in experiment 2.
vo
Semester 2 Reports (iv)
Experiment 4: Capacitive Coupling (a.c coupling)
1) The circuit is connected as shown in figure 8 with C1=C2= 1 μF and R L= 470 Ω. 2) Steps 2 to 5 of experiment 2 are repeated and values of Av and V0,d.c are compared with those obtained in experiment 2. 12v
220
100k
c2 c1
vo
RL
Vin
0v
fig 8
5.6 Results, Questions and Conclusion: (i)
Experiment 1: Determination of h fe
VBE = 0.7 V and V0 = 144.7 mV
IB (12 V BE .)/100K Ω = (12 – 0.7)/ 100K = 113 μA
IC (12 - Vo) /R = (12- 0.1447)/ 1K = 11.9 mA
d.c current gain, hFE = IC / IB -3
-6
= (11.9 x 10 ) / (113 x 10 ) = 104.9
Semester 2 Reports (ii)
Experiment 2: The CE amplifier
Out of phase
Vod.c=5.1V
Figure 5.0 CRO output for CE amplifier
Amplitude of input signal, Vin = 14 mV Amplitude of a.c component of output voltage, Vo = -1.8 V (Vo is negative due to 180 phase difference with respect to Vin) D.C component of output voltage, Vo = 5.1 V a.c voltage gain, Av, of amplifier = Vo.ac/ Vin = -1.8/ 0.014 = -128.6
Semester 2 Reports Theoretical Values: Ic = (12-Vo)/ R = (12 – 5.1)/ 220 = 31.4 mA
Av = -gmR c = -40IcR c = -40 * 0.0321 * 220 = -282.5 Vo, d.c = Vcc - R cIc = 12 – 220(0.0321) = 4.9 V
Use h F E = 110 for tran sistor BC107 h F E = 120 for transistor BC108 h F E = 180 for transistor BC109 Questions
1. H ow do these valu es compare with experi mental values? Since experimental value of hFE = 104.9, it can be determined that transistor BC107 was used. The difference might be due to experimental uncertainties such as internal heating or conta ct resistance.
2. Use both chan nels of the CRO to observe Vi n and Vo simultaneously. What can you say about th eir phase relati onshi p? Expl ain why this is so. It produces phase reversal of input signal, i.e., input signal, Vin and output signal, Vo are 180° out of phase with each other. Output voltage is given by Vo, d.c = Vcc - R cIc. Therefore, in the positive half-cycle, when the a.c signal voltage increases, the bias potential for the emitter junction also increases which in turn increases the base current. As a result the collector current is increased and hence the voltage drop across R c also increases. Since Vcc is constant, the output voltage VCE decreases. In other words, when Vin increases in the positive direction, Vo increases in the negative direction; implying that output is 180º out of phase with the input.
Semester 2 Reports (iii)
Experiment 3: Direct Coupling to load
Amplitude of input signal, Vin = 14 mV Amplitude of a.c component of output voltage, Vo = -1.3 V (Vo is negative due to 180 phase difference with respect to Vin) D.C component of output voltage, Vo = 3.5 V
Semester 2 Reports a.c voltage gain, Av, of amplifier = Vo.ac/ Vin = -1.3/ 0.014 = -92.9 Questions
1. Compare these values of A v and Vo,d.c with those obtain ed in experi ment 2. As compared to experiment 2, values of Av and Vo,d.c have decreased when direct coupling is used. The loaded voltage gain and Vo,d.c of the amplifier configuration in experiment 3 is less than the no-load gain (experiment 2) due to shunting and loading effects. Effect due to introduction of the load resistance R L of value 470 ohms, across the output terminals which caused a reduction in both Vo,a.c. and Vo,d.c. (iv)
Experiment 4: Capacitive Coupling (a.c coupling)
Amplitude of input signal, Vin = 14 mV Amplitude of a.c component of output voltage, Vo = -1.3 V (Vo is negative due to 180 phase difference with respect to Vin)
Semester 2 Reports D.C component of output voltage, Vo = 0 V a.c voltage gain, Av, of amplifier = Vo.ac/ Vin = -1.3/ 0.014 = -92.9 Questions
1. Compare these valu es of A v and Vo,d.c with those obtain ed in exp. 2 and 3. The voltage gain, Av remains unchanged in experiment 3 and 4 as the coupling capacitor passes the a.c signal to give little or no distortion only. It can be determined that coupling capacitor used in the amplifier blocks direct current c ausing D.C component of output voltage, Vo to be 0V. Therefore, Vo, d.c has significantly decreased due to capacitive coupling as compared to experiment 2 and 3. . 2. Summar ize the important points learn ed f rom these experiments To summarize, when the input signal is applied between base and emitter, and output between emitter and collector in the common-emitter amplifier, moderately low input impedance and a very high output impedance is generated, with a phase reversal between input and output. The common-emitter amplifier produces the highest power gain of all three amplifier c onfigurations as voltage gain is fairly high. Precautions:
Loose connections should be avoided. Before conducting the practical, the resistors and diodes sho uld be tested using multimeter. The power supply must be switched off when connections are altered. Circuit noise should be avoided by preventing contacts of the components’ leads with each other.
Semester 2 Reports
6. Analog Computing 6.1: Overview of experiment
This experiment is based on the construction of circuits using op-amps and resistors to perform analog computations such as multiplication, addition and integration. 6.2: Introduction
An operational amplifier is a high gain differential amplifier which has ver y high input impedance (typically a few mega-ohms) and low output impedance (less than 100Ω) as compared to an ideal op-amp which has infinite input impedance, zero output impedance, and an infinite voltage gain. Figure 6.1 below shows a basic op-amp.
Figure 6.0: Op-amp
The non-inverting (+) input produces an output that is in phase with the signal applied while the inverting (-) input produces an output that is o ut of phase with the signal applied. Therefore a phase difference of 180° is read at the output. 6.3: Theories concerning the experiment:
6.3.1Multiplication Consider the circuit below. Rf +12V V1
R1
-
V0
+ -12V
Figure 6.1: Opamp circuit performing multiplication
Semester 2 Reports
6.3.2 The Summing Amplifier:
Semester 2 Reports 6.3.3The integrator
6.4: Objective of experiment:
To construct simple circuits using op-amps to perform various computations such as multiplication, addition and integration. 6.5: Equipment Used:
081 IC(op-amp) DC power supply DC variable source 3* 10 kΩ , 1*22 kΩ resistors Voltmeter 10nF capacitor Signal generator Oscilloscope Connecting wires
6.6: Procedures: Experiment 1: Multiplication by a constant
1. The circuit is connected as shown in figure 6.3, using R 1 =10k and R 2 =10k.
Semester 2 Reports Rf
+12V R1
2
7
-
6
DC Variable
V1
3
source
+ -!2V
V0
4
Figure 6.4: Circuit to multiply a constant 2. The power supply is turned on and an input voltage of +4V is applied to V1 and Vo is recorded using a voltmeter. 3. V1 is varied and the output voltage Vo is recorded and verified. Table 6.1: values recorded for V1 and V0 V1 /V
Vo/V
+2
-2.07
+4
-4.03
+6
-6.02
+8
-8.01
+10
-9.86
Verified: Vo=-V1 4.
R f is replaced with a 22kΩ resistor in figure 6.3 a nd V1 is varied. The values obtained for Vo is then recorded in table 6.2. (shown below)
Semester 2 Reports Table 6.2: Values recorded when R f is varied. V1/V
Vo/V
Vo/V1(v)
2.3
-5.08
-2.21
4.1
-9.06
-2.21
4.5
-9.90
-2.21
5.0
-9.88
-1.976
6.1
-9.88
-1.62
Conclusion: The relationship V0 = - 2.2 V1 is confirmed for the first 3 values of V 1, as from 4.5 V the op-amp became saturated afterwards Experiment 2: Addition 1. The circuit is connected as shown in figure 6.4 using R 1 = R 2 = R f = 10kΩ. Rf
V1 V2
R1
R2
-
+12v V0
+
-12v
Figure 6.4: Addition Circuit The power supply is switched on and the value of Vo is recorded using a voltmeter.
Semester 2 Reports 2. A voltage of V1=+5V and V2=-3V is applied. Vo is measured. 3. part (2) was repeated using different values for V2= and therefore Vo was recorded using different values for V2. And the following results were recorded in the table 6.3 below. Table 6.3: Values recorded V1/V
V2/V
V0/V
+5.0
-3
-1.8
+5.0
-4.2
-0.8
+5.0
-6
-1.1
+5.0
-7
-2.5
+5.0
+8.1
3.2
+5.0
+11.0
+6.0
4. If the op-amp is not saturated and R1=R2=Rf, then Vo=-(V1+V2). The circuit will no longer perform the addition correctly if the op-amp is saturated. Experiment 3: Integration
1. The circuit is implemented as shown in figure 6.5 using R1=10kΩ, C=10nF.The power supply is turned on. C
R1
V1
12v
V0
+
-12v
Figure 6.5: Integrator circuit
2. A 2 pk-pk, 1 kHz sinusoid is applied at V1 and the output waveform obtained (figure 6.5) is observed on a CRO screen. The amplitude of V0 is measured and the phase difference relative to V1 is noted.
Semester 2 Reports
Figure 6.5: Output waveform for an integrator circuit Observation: Amplitude of V0=1.3V.The phase difference is /2. Conclusion: The waveform of V0 is a cosine curve. Input is a sine curve and output is a cosine curve.
3. when the frequency is increased , Vo decreases according to the following equation: Vo/V1=-1/XC (eq 5.1) Where X=j2∏f C-capacitance 4. A 2pk-pk 1kHz square wave is applied at V1. The following waveform is obtained.
Figure 6.6: Output waveform when input signal is a square wave Observation : By observing carefully, we see than for each positive half cycle of the input signal,
the output is a line with negative gradient and for the negative half cycle, the output is a line with positive gradient.
Semester 2 Reports Exercise
Design a cir cui t usin g two op-amps and some available resistors (f rom the set) to perform the given fu nction C u sin g voltages to r epresent in puts A and B . C=2.13A + 0.37B
Figure 6.7: Circuit to perform C=2.13 A + 0.37 B function For IC2
VO = - (10K/2.7K) B For IC1
Vo = - (10K/100K)((-10K/2.7K)B) =0.37B VO = - (10K/4.7K) A =2.13A C=2.13A+0.37B
