Effective AGC Amplifier Can Be Built At A Nominal Cost Aug 3, 1998 http://electronicdesign.com/analog/effective-agc-amplifier-can-be-built-nominal-cost Using the circuit presented here, you can construct a very inexpensive AGC amplifier with the following features: -
a dynamic dynamic range range greater than 50 50 dB; dB; negligible negligible distortion to to the output waveform; fast attack and slow decay; an adjustable output level from 0 to 1.2 V p-p; operation from a single 5-V supply; less than 1-mA current drain; and low cost (uses one half of a dual 8-pin op-amp package package at less than $2.50 in parts).
Better yet, if you need a second channel, the remaining half of the op amp can be used f or that circuit. Referring to the diagram, Q2 (a Pchannel JFET), coupled with R2 and the equivalent resistance of R3 and R4, form a voltage divider to the input signal source. With input levels below 40 mV p-p, the input is evenly divided between R2 (120k) and R3 ¦ ¦ R4 (120k). The output amplitude of U1A isn t large enough to turn on Q2, which acts as a positive peak detector. ’
The gate of the JFET is pulled to +5 V, pinching its channel off and creating a very high resistance from drain to source. This essentially removes it from the circuit. At input levels above 40 mV p-p, Q1 is turned turned on at the positive peaks of the output of U1A, lowering the JFETs gate to source voltage. The channel resistance decreases and attenuates the input signal to maintain the output of U1A at approximately 1.2 V p-p. The circuit, as shown, was tested with a sine-wave input ranging from 300 Hz to 30 kHz at 40 mV to 20 V p-p, a 54-dB range. It maintained the output level at 1.2 V p-p, ±0.5 dB, with no visible distortion when comparing it with the input waveform. With a 40 mV to 20 V p-p input signal, the amplitude of the signal across the JFET (VDS) measured less than 20 mV p-p. Other JFETs with VGS(OFF) of 5V or under, such as the t he 2N5019 or 2N5116, should work equally well in this circuit, although they haven t been tried. ’
To use JFETs with higher VGS(OFF), such as the 2N3993 (it was tried and worked equally well), increase the supply voltage to 12 V.
Hi I have this AGC circuit which I need to simulate. http://electronicdesign.com/site-fi...ctronicdesign.com/files/29/6272/figure_01.gif Could anyone please help me with a detailed circuit description as to how this AGC works. I don't want to simulate it blindly, without knowing how it works. The only description I found was this. http://electronicdesign.com/analog/effective-agc-amplifier-can-be-built-nominal-cost I need to understand why the output should remain constant at 1.2 Vp-p for different frequencies. And what should I change if I want to change the output level? Will be a great help. Thanks Eagerly awaiting a response. ---------------------------------------------------------------------------------------------------------------------------------Q1 detects peak voltage of the output. (Envelope detector) Lowpass filtered by R8 and C4. Q2 acts as a voltage-controlled resistance, but is linear only for small signal at its drain... R2/Q2 forms a voltage divider. You understand U1a as an AC-coupled amplifier, right? ---------------------------------------------------------------------------------------------------------------------------------If you want to change the output level, alter the gain of the op amp, or the voltage applied to Q1 npn, by a preset resistor to its base. ---------------------------------------------------------------------------------------------------------------------------------The output regulated peak voltage is basically equal to the Vbe of Q1. It is only slightly affected by the op amp gain. A resistor to Q1's base (series?) will also have only a small effect on the output voltage unless you make it large enough to starve the transistor base current. If you connect Q1's base to the output of the pot P1 then you can adjust the regulated output voltage with that. For example at a 50% pot wiper setting the op amp output will be about 2.5V pp. ---------------------------------------------------------------------------------------------------------------------------------Q1 detects peak voltage of the output. (Envelope detector). Lowpass filtered by R8 and C4. Q2 acts as a voltage-controlled resistance, but is linear only for small signal at its drain. R2/Q2 forms a voltage divider. You understand U1a as an AC-coupled amplifier, right? ---------------------------------------------------------------------------------------------------------------------------------Hi Thank you for your replies. Here are the things I don't understand to be precise: 1. How does the OPAMP LM358 get the negative supply at its inverting input (pin 2). I see a 10 uF capacitor and 470 ohm resistor (C2 and R5) in series there. It is not negative. In fact it is 2.5Vdc (5V/2). It comes from the output pin of the opamp (feedback) through R6.
2. What is the purpose of R1 and C1. C1 will block AC, I believe. But not sure how does that help. R1 makes sure that the input is at 0V. (No bias through Q2). Left end of C1 is at 0V; right end is at 2.5V, so is blocking DC while passing AC.
3. Why is there a voltage source of 5V required at R3||R4 (Voltage divider as per description) Pin 3 of the opamp is biased midway between gnd and 5V. Due to negative feedback at DC, that puts pin 1 and pin 2 at 2.5V, too.
4. What is the purpose of C3? Block DC; pass AC
5. R8 AND C4 make up a filter as pointed by one of the members in the post above. Again, how does that help and why is a voltage source needed (5V) The 5V pulls the gate of Q2 high (slowly); the NPN collector pulls it low (fast). The higher the gate voltage of Q2, the more the input signal is attenuated by the voltage divider consisting of R2 and Q2, which is how the AGC is accomplished. The low-pass filter time-constant has a fast attack, slow decay, and the decay time is long enough to pass the envelope of the input waveform (words if speech).
6. What is the purpose of R7? To overcome a defect in the LM358 that would otherwise cause cross-over distortion in the audio signal
---------------------------------------------------------------------------------------------------------------------------------When power is 5 volts maximum output amplitude of ~ 1.2V (Vout_max = Vcc-VbeDarl-Vs = 5V1.1-0.2V = 3.7V). The average level of the output voltage is half the supply voltage (for R3 = R4 = 240k)--> 3.7v2.5V=1.2V. To be able to produce more output voltage is necessary to increase the supply voltage. But it makes no sense at this fixed voltage. More input would give more harmonic distortion on the channel resistance of the FET.
