EEEB161 LAB EXPERIMENT 4 AND 5 COMBINATIONAL LOGIC CIRCUITS
LAB INSTRUCTOR SECTION DATE
MEMBERS NABIL AZMIL
: SHARIFAH AZWA BTE SHAAYA : 02 : 6TH JULY 2017
STUDENT ID
Objective The objective of this experiment is to construct a logic circuit based on a written specified problem. This includes deriving Boolean equations from a truth table, simplifying the Boolean equation into itβs simplest form, designing and simulating the circuits by using Quartus II and ModelSim-Altera and finally building the real logic circuit using the chips provided.
Introduction A project is planned in which a bicycle wheel LEDs lights up at a different speed. A tachometer is used to measure the rotational speed of the wheel and transmits the date into an ADC chip which will then decode the signal into an 8-bit data. The date is then decoded to 3bits data namely X, Y and Z. Each inputs of X, Y and Z defines the speed of the wheels, 000 being slow speed and 111 being a very high speed. These inputs will then be used to construct a logic circuit which will turn on the LEDs accordingly. 1. For inputs XYZ = 000, 001, 010, green LED, G will turn on. 2. For inputs XYZ = 010 until 110, red LED, R will turn on. 3. For inputs XYZ = 101, 110, 111 bluw LED, B will turn on. Karnaugh Map or KMAP is then used to find out the simplest Boolean expression for each of the outputs. This will then reduce the amount of logic gates that will be needed to construct the logic circuit compared to using canonical SOP or POS methods. KMAP will also reduce the human errors while simplifying the Boolean expressions. In KMAP the inputs are divided along the first row and the first column of the table. The remaining entries are then filled in with zeros and ones which will then be group into several groups of 2n where n=0, 1, 2, 3, β¦ This will result in groups of 1, 2, 4, 8, β¦ When the zeros are grouped, the simplified Boolean expression will look like canonical POS while grouping the ones will result in the Boolean expression to look like canonical SOP. It is important to group the terms into the optimal group (there shouldnβt be a redundant group). YZ
00
01
11
10
0
0
1
0
1
1
0
1
0
1
X I
II
πΉ = πΌ + πΌπΌ πΉ = πΜ
π + ππΜ
πΉ =πβπ Table 1.1 Example of KMAP and the Boolean equation when grouping ones 1
Procedures 1. From the information and conditions provided in the situation mentioned in the introduction, a truth table was constructed with inputs X, Y and Z and outputs G, R and B. This table is also used to validate the results. Inputs
Outputs
X
Y
Z
G
R
B
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
0
0
1
Table 1.2 Truth Table for inputs X, Y and Z and outputs G, R and B. 2. Then, 3 KMAPs are constructed each for the respective outputs. This is used to determine the Boolean expressions for each output and also the logic gates design. XZ X
01
00
11
10
0
1
1
0
1
1
0
0
0
0
πΊ πΊ πΊ πΊ
= πΜ
πΜ
+ πΜ
πΜ
= πΜ
(πΜ
+ πΜ
) (ππ) = πΜ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
Μ
= (π + ππ)
Table 1.3 Truth Table and Boolean equation for output G.
2
YZ
00
01
11
10
0
0
0
1
1
1
1
1
0
1
X
π
= ππΜ
+ πΜ
π + ππΜ
π
= ππΜ
+ πΜ
π + ππΜ
Table 1.3 Truth Table and Boolean equation for output R.
YZ
00
01
11
10
0
0
0
0
0
1
0
1
1
1
X
π΅ = ππ + ππ π΅ = π(π + π) Table 1.3 Truth Table and Boolean equation for output B. 3. The combinational logic circuit is then drawn using the Boolean equations obtained in the KMAPs above.
Figure 1.1 Schematic design for inputs X, Y and Z and outputs G, R and B. 3
4. The schematics is then tested for validity in Quartus II and ModelSim-Altera and the simulation is run. 5. The output waveform is then taken and compared with the truth table. 6. Once validated, a digital circuit is then built using different types of TTL components. 7. The output is observed and recorded and the output must be similar to the truth table.
Results
Figure1.2 Schematic in Quartus II.
Figure 1.3 Waveform output in ModelSim-Altera. 4
Figure 1.4 Construction of the logic circuit.
Inputs
Outputs
X
Y
Z
G (7)
R (6)
B (5)
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
0
0
1
Figure 1.5 Truth Table observed from the constructed logic circuit. 5
Discussion Referring to the truth table and schematic diagram, the number of AND gates used are 4, OR gates are 3 and NOT gates are 3. Therefore, the number of gate used tallies with the maximum number of gates provided by the chips; 7408 chip having 4 AND gates, 7404 chip having 6 NOT gates and 7432 chip having 4 OR gates. The output waveform obtained from ModelSim-Altera also tallies with desired outcome of the problem described in the introduction. In constructing the circuit, several problems were encountered due to human error in placing the wires and connection at the correct place. Several rounds of trouble shootings were done which includes testing the chip for its condition, repairing any short-circuited connections and also checking each and every wire connections. When the circuit repaired and corrected, the observation is then taken and recorded.
Conclusion In conclusion, the construction of the logic gates based on a written problem is successfully completed. Deriving Boolean equation from truth table and simplifying it by using KMAP was also done successfully. Simulating the schematic in Quartus II and ModelSimAltera helps to validate the result of the drawn circuit. Several troubleshooting methods were also practiced along the way to rectify the problems encountered during building the circuit. In doing so, the circuit has been found to give the correct desired output which satisfies the main problem described in the introduction.
Post Lab Question Letβs assume the lab has run out of 7402 2-input NOR chips. The lab technician offers 7427 3input NOR chips as alternative. Will you be able to produce the circuit with the same desired outputs using this chip? Explain. Show diagrams if necessary. Yes, the desired outputs will still be able to be produced. This is because, referring from the truth table below, both chips give out the same output when the same input is used.
X 0 0 1 1
7402 2-input NOR Input Output Y F 0 1 1 0 0 0 1 0
X 0 0 0 0 1 1 1 1
6
7427 3-input NOR Input Y Z 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1
Outpout F 1 0 0 0 0 0 0 0
