EE315B VLSI Data Conversion Circuits - Autumn 2013 Boris Murmann Stanford University
[email protected]
Table of Contents
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12
Introduction Sampling, Reconstruction, Quantization Spectral Performance Metrics Nyquist Rate DACs Sampling Circuits Voltage Comparators Flash ADCs SAR ADCs Pipeline ADCs Time Interleaving Oversampling ADCs and DACs Energy Limits in A/D Converters
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Introduction
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
B. Murmann
EE315B - Chapter 1
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Motivation (1)
This course
Analog Media and Transducers
Signal Conditioning
A/D Digital Processing
Signal Conditioning
D/A
Sensors, Actuators, Antennas, Storage Media, ...
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Motivation (2) •
Benefits of digital signal processing – Reduced sensitivity to "analog" noise – Enhanced functionality and flexibility – Amenable to automated design & test – Direct benefit from the scaling of VLSI technology – "Arbitrary" precision
•
Issues – Data converters are difficult to design • Especially due to ever-increasing performance requirements
– Data converters often present a performance bottleneck • Speed, resolution or power dissipation of the A/D or D/A converter can limit overall system performance
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A/D Converter ca. 1954
http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html B. Murmann
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Data Converter Applications (1) •
Consumer electronics – Audio, TV, Video – Digital Cameras – Automotive control – Appliances – Toys
•
Communications – Mobile Phones – Personal Data Assistants – Wireless Transceivers – Routers, Modems EE315B - Chapter 1
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Data Converter Applications (2) •
Computing and Control – Storage media – Sound Cards – Data acquisition cards
•
Instrumentation – Lab bench equipment – Semiconductor test equipment – Scientific equipment – Medical equipment
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Example 1
[Poulton, ISSCC 2003]
•
High performance digital oscilloscopes rely on extremely high performance ADCs
•
Example – 20 GSample/s, 8-bit ADC – 10 W Power dissipation
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Example 2
•
Schvan, ISSCC 2008
•
Time interleaved architecture using 160 (!) SAR ADCs for optical networks
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Example 3
•
A typical cell phone contains: – 4 Rx ADCs Dual Standard, I/Q – 4 Tx DACs Audio, Tx/Rx power – 3 Auxiliary ADCs control, Battery – 8 Auxiliary DACs charge control, display, ...
•
A total of 19 data converters!
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Example 4
[Mehta, ISSCC2005]
•
Low-cost, single chip solutions require embedded data conversion
•
Example: 802.11g Wireless LAN chip – 2x 11-bit DAC, 176 MSamples/s – 2x 9-bit ADC, 80 MSamples/s
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Trend Toward Lower ADC Energy -6
10
-8
P/f s [J]
10
-10
10
-12
10
ISSCC & VLSI 2006-2013 ISSCC & VLSI 1998-2005 20
30
40
50
60 70 SNDR [dB]
80
90
100
110
B. Murmann, "ADC Performance Survey 1997-2013," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html B. Murmann
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Course Objective •
Acquire a thorough understanding of the basic principles and challenges in data converter design – Focus on concepts that are unlikely to expire within the next decade – Preparation for further study of state-of-the-art "fine-tuned" realizations
•
Strategy – Acquire breadth via a complete system walkthrough and a survey of existing architectures – Acquire depth through a midterm project that entails design and thorough characterization of a specific circuit example in modern technology
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Staff and Website
•
Teaching assistant – Vaibhav Tripathi
•
Administrative support – Ann Guerra, Allen 207
•
Lecture videos are provided on the web, but please come to class to keep the discussion intercative
•
Coursework web page – http://coursework.stanford.edu/homepage/F13/F13-EE-315B-01.html
– Please visit the discussion forum regularly – Only enrolled students have full access
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Preparation •
Course prerequisites – EE214B or equivalent • Device physics and models • Transistor level analog circuits, elementary gain stages • Frequency response, feedback, noise
– Prior exposure to Spice, Matlab – Basic signals and systems – Basic probability •
Please talk to me if you are not sure whether you have the required background
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Analog Circuit Sequence
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Assignments •
Homework: (20%) – Handed out on Tue, due following Tue after lecture (1 pm) – Lowest HW score is dropped in final grade calculation
•
Midterm Project: (40%) – Transistor level design and simulation of a data converter sub-block (no layout) – Prepare a project report in the format and style of an IEEE journal paper
•
Final Exam (40%)
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Honor Code •
Please remember you are bound by the honor code – I will trust you not to cheat – I will try not to tempt you
•
But if you are found cheating it is very serious – There is a formal hearing – You can be thrown out of Stanford
•
Save yourself and me a huge hassle and be honest
•
For more info – http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/ honorcode.pdf
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Tools and Technology •
Primary tools – Cadence Virtuoso Schematic Editor – Cadence Virtuoso Analog Design Environment – Cadence SpectreRF simulator – You can use your own tools/setups “at own risk“
•
Getting started – Read tutorials and setup info provided in the CAD section of the course website
•
EE315A/B Technology – 0.18-µm CMOS – BSIM3v3 models provided under /usr/class/ee315b/models
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Reference Books •
M. Pelgrom, Analog-to-Digital Conversion, Springer, 2010
•
Gustavsson, Wikner, Tan, CMOS Data Converters for Communications, Kluwer, 2000
•
A. Rodríguez-Vázquez, F. Medeiro, and E. Janssens, CMOS Telecom Data Converters, Kluwer Academic Publishers, 2003
•
W. Kester, The Data Conversion Handbook, Newnes, 2005 http://www.analog.com/library/analogdialogue/archives/39-06/data_conversion_handbook.html
•
B. Razavi, Data Conversion System Design, IEEE Press, 1995
•
R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters, Wiley-IEEE Press, 2004
•
R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-toAnalog Converters, 2nd ed., Kluwer, 2003
•
J. G. Proakis, and D. G. Manolakis, Digital Signal Processing, Prentice Hall, 1995 EE315B - Chapter 1
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Course Topics
•
Ideal sampling, reconstruction and quantization
•
Sampling circuits
•
Voltage comparators
•
Nyquist-rate ADCs and DACs
•
Oversampled ADCs and DACs
•
Data converter performance trends and limits
•
Data converter testing, simulation techniques
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Sampling, Reconstruction, Quantization
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
EE315B - Chapter 2
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The Data Conversion Problem
•
Real world signals – Continuous time, continuous amplitude
•
Digital abstraction – Discrete time, discrete amplitude
•
Two problems – How to discretize in time and amplitude • A/D conversion
– How to "undescretize" in time and amplitude • D/A conversion B. Murmann
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Overview
•
We'll fist look at these building blocks from a functional, "black box" perspective – Refine later and look at implementations
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Uniform Sampling and Quantization •
Most common way of performing A/D conversion – Sample signal uniformly in time – Quantize signal uniformly in amplitude
•
Key questions – How much "noise" is added due to amplitude quantization? – How can we reconstruct the signal back into analog form? – How fast do we need to sample? • Must avoid "aliasing"
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Aliasing Example (1)
Amplitude
fs =
1 = 1000kHz Ts
fsig = 101kHz
Time
f v sig ( n ) = cos 2π ⋅ in ⋅ n fs
v sig ( t ) = cos ( 2π ⋅ fin ⋅ t ) t → n ⋅ Ts =
n fs
101 = cos 2π ⋅ ⋅n 1000
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Aliasing Example (2)
Amplitude
fs =
1 = 1000kHz Ts
fsig = 899kHz
Time
899 101 899 v sig ( n ) = cos 2π ⋅ ⋅ n = cos 2π ⋅ − 1 ⋅ n = cos 2π ⋅ ⋅n 1000 1000 1000
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Aliasing Example (3)
Amplitude
fs =
1 = 1000kHz Ts
fsig = 1101kHz
Time
1101 101 1101 v sig ( n ) = cos 2π ⋅ ⋅ n = cos 2π ⋅ − 1 ⋅ n = cos 2π ⋅ ⋅n 1000 1000 1000
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Consequence
•
The frequencies fsig and N·fs ± fsig (N integer), are indistinguishable in the discrete time domain
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Sampling Theorem •
In order to prevent aliasing, we need fsig ,max <
fs 2
•
The sampling rate fs=2·fsig,max is called the Nyquist rate
•
Two possibilities – Sample fast enough to cover all spectral components, including "parasitic" ones outside band of interest – Limit fsig,max through filtering
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Brick Wall Anti-Alias Filter
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Practical Anti-Alias Filter Desired Signal
Parasitic Tone Attenuation
Continuous Time 0
B
fs/2
0
B/fs
0.5
fs-B
fs
...
f
Discrete Time
•
f/fs
Need to sample faster than Nyquist rate to get good attenuation – "Oversampling"
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How much Oversampling?
[v.d. Plassche, p.41]
Alias Rejection Filter Order
fs/fsig,max
•
Can tradeoff sampling speed against filter order
•
In high speed converters, making fs/fsig,max>10 is usually impossible or too costly – Means that we need fairly high order filters
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Classes of Sampling •
Nyquist-rate sampling (fs > 2·fsig,max) – Nyquist data converters – In practice always slightly oversampled
•
Oversampling (fs >> 2·fsig,max) – Oversampled data converters – Anti-alias filtering is often trivial – Oversampling also helps reduce "quantization noise" • More later
•
Undersampling, subsampling (fs < 2·fsig,max) – Exploit aliasing to mix RF/IF signals down to baseband – See e.g. Pekau & Haslett, JSSC 11/2005
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Subsampling
•
Aliasing is "non-destructive" if signal is band limited around some carrier frequency
•
Downfolding of noise is a severe issue in practical subsampling mixers – Typically achieve noise figure no better than 20 dB (!)
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The Reconstruction Problem •
As long as we sample fast enough, x(n) contains all information about x(t) – fs > 2·fsig,max
•
How to reconstruct x(t) from x(n)?
•
Ideal interpolation formula ∞
x( t ) =
∑
x( n ) ⋅ g( t − nTs )
n =−∞
g(t ) =
•
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sin( πfs t ) πfs t
Very hard to build an analog circuit that does this…
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Zero-Order Hold Reconstruction •
The most practical way of reconstructing the continuous time signal is to simply "hold" the discrete time values – Either for full period Ts or a fraction thereof – Other schemes exist, e.g. “partial-order hold” • See [Jha, TCAS II, 11/2008]
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•
What does this do to the signal spectrum?
•
We'll analyze this in two steps – First look at infinitely narrow reconstruction pulses
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Dirac Pulses •
xd(t) is zero between pulses – Note that x(n) is undefined at these times ∞
xd ( t ) = x( t ) ⋅
∑
δ( t − nTs )
n =−∞
•
Multiplication in time means convolution in frequency – Resulting spectrum Xd ( f ) =
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1 Ts
n X f − Ts n =−∞ ∞
∑
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Spectrum
•
Spectrum of Dirac signal contains replicas of Vin(f) at integer multiples of the sampling frequency
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Finite Hold Pulse •
Consider the general case with a rectangular pulse 0 < Tp ≤ Ts
•
The time domain signal on the left follows from convolving the Dirac sequence with a rectangular unit pulse
•
Spectrum follows from multiplication with Fourier transform of the pulse sin( πfTp )
Hp (f ) = Tp
Xp (f ) =
πfTp
Tp sin( πfTp ) Ts
πfTp
⋅e
⋅e
− jπfTp
− jπfTp
n Xf − Ts n =−∞ ∞
∑
Amplitude Envelope EE315B - Chapter 2
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Envelope with Hold Pulse Tp=Ts 1 0.9 0.8 0.7 0.6 0.5
Ts
0.4
πfTp
abs(H(f))
Tp sin( πfTp )
0.3 0.2 0.1 0 0
0.5
1
1.5 f/fs
2
2.5
3
f/fs B. Murmann
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Envelope with Hold Pulse Tp=0.5·Ts 1 0.9 0.8
Tp=Ts
0.7 0.6 0.5
Ts
0.4
πfTp
abs(H(f))
Tp sin( πfTp )
Tp=0.5·Ts
0.3 0.2 0.1 0 0
0.5
1
1.5
2
2.5
3
f/fs f/f s
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Example 1
Spectrum of Continuous Time Pulse Train (Arbitrary Example)
0.5
0 0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
2
2.5
3
1
ZOH Transfer Function ("Sinc Distortion")
0.5
0 1
ZOH output, Spectrum of Staircase Approximation
original spectrum 0.5
0 0
0.5
1
1.5
f/fs
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Reconstruction Filter 1
•
Also called smoothing filter
•
Same situation as with anti-alias filter – A brick wall filter would be nice – Oversampling helps reduce filter order
0.9
Filter
0.8
Spectrum
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0
0.5
1
1.5
2
2.5
3
f/fs B. Murmann
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Summary •
Must obey sampling theorem fs > 2·fsig,max, – Usually dictates anti-aliasing filter
•
If sampling theorem is met, continuous time signal can be recovered from discrete time sequence without loss of information
•
A zero order hold in conjunction with a smoothing filter is the most common way to reconstruct – May need to add pre- or post-emphasis to cancel droop due to sinc envelope
•
Oversampling helps reduce order of anti-aliasing and reconstruction filters
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Recap
•
Next, look at – Transfer functions of quantizer and DAC – Impact of quantization error EE315B - Chapter 2
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Quantization of an Analog Signal Vq (quantized output)
Transfer Function
Slope=1
•
Quantization step ∆
•
Quantization error has sawtooth shape – Bounded by –∆/2, +∆/2
•
Ideally – Infinite input range and infinite number of quantization levels
•
In practice – Finite input range and finite number of quantization levels – Output is a digital word (not an analog voltage)
∆
eq (quantization error)
x (input) Error eq=q-x
+∆/2
-∆/2 x (input)
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Conceptual Model of a Quantizer
•
Encoding block determines how quantized levels are mapped into digital codes
•
Note that this model is not meant to represent an actual hardware implementation – Its purpose is to show that quantization and encoding are conceptually separate operations – Changing the encoding of a quantizer has no interesting implications on its function or performance EE315B - Chapter 2
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•
111 110 101 100 011 010 001 000
∆
Analog Input eq (quantization error)
Digital Output
Encoding Example for a B-Bit Quantizer
+∆/2
• http://www.analog.com/en/content/0 ,2886,760%255F788%255F91285, 00.html
•
-∆/2 •
FSR x (input)
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Example: B=3 – 23=8 distinct output codes – Diagram on the left shows "straight-binary encoding" – See e.g. Analog Devices "MT009: Data Converter Codes" for other encoding schemes
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Quantization error grows out of bounds beyond code boundaries We define the full scale range (FSR) as the maximum input range that satisfies |eq| ≤ ∆/2 – Implies that FSR=2B·∆ 28
Nomenclature •
Overloading - Occurs when an input outside the FSR is applied
•
Transition level – Input value at the transition between two codes. By standard convention, the transition level T(k) lies between codes k-1 and k
•
Code width – The difference between adjacent transition levels. By standard convention, the code width W(k)=T(k+1)-T(k) – Note that the code width of the first and last code (000 and 111 on previous slide) is undefined
•
LSB size (or width) – synonymous with code width ∆
[IEEE Standard 1241-2000]
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Implementation Specific Technicalities •
So far, we avoided specifying the absolute location of the code range with respect to "zero" input
•
The zero input location depends on the particular implementation of the quantizer – Bipolar input, mid-rise or mid-tread quantizer – Unipolar input
•
The next slide shows the case with – Bipolar input • The quantizer accepts positive and negative inputs – Represents the common case of a differential circuit
– Mid-rise characteristic • The center of the transfer function (zero), coincides with a transition level
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Digital Output
Bipolar Mid-Rise Quantizer
111 110 101 100 011 010 001 000 Analog Input -FSR/2
•
+FSR/2
0
Nothing new here…
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Bipolar Mid-Tread Quantizer In theory, less sensitive to infinitesimal disturbance around zero – In practice, offsets larger than ∆/2 (due to device mismatch) often make this argument irrelevant
•
Asymmetric full-scale range, unless we use odd number of codes
Digital Output
•
111 110 101 100 011 010 001 000 Analog Input FSR/2 + ∆/2
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0 FSR/2 - ∆/2
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Unipolar Quantizer Usually define origin where first code and straight line fit intersect – Otherwise, there would be a systematic offset
•
Usable range is reduced by ∆/2 below zero
Digital Output
•
111 110 101 100 011 010 001 000 0
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Effect of Quantization Error on Signal •
Two aspects – How much noise power does quantization add to samples? – How is this noise power distributed in frequency?
•
Quantization error is a deterministic function of the signal – Should be able answer above questions using a deterministic analysis – But, unfortunately, such an analysis strongly depends on the chosen signal and can be very complex
•
Strategy – Build basic intuition using simple deterministic signals – Next, abandon idea of deterministic representation and revert to a "general" statistical model (to be used with caution!)
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Ramp Input •
Applying a ramp signal (periodic sawtooth) at the input of the quantizer gives the following time domain waveform for eq 0.6
0.2 0
q
e (t) [∆]
0.4
-0.2 -0.4 0
50 100 Time [arbitrary units]
150
•
What is the average power of this waveform?
•
Integrate over one period eq2
T/2
1 = eq2 ( t )dt T −T∫/ 2
eq ( t ) =
∆ ⋅t T
∴ eq2
∆2 = 12
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Sine Wave Input 1
1 Vin V
0.8
q
0.6
0.6
0.4
0.4
0.2
0.2 eq(t) [∆]
[Volts]
0.8
0
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1 0
•
0.2
0.4 0.6 Time [arbitrary units]
0.8
1
-1 0
0.2
0.4 0.6 Time [arbitrary units]
0.8
1
Integration is not straightforward…
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Quantization Error Histogram • •
Sinusoidal input signal with fsig=101Hz, sampled at fs=1000Hz 8-bit quantizer Mean=0.000LSB, Var=1.034LSB2/12 120 100
Count
80 60 40 20 0 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0 0.1 0.2 0.3 0.4 0.5 0.6 e /∆ q
• •
Distribution is "almost" uniform Can approximate average power by integrating uniform distribution
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Statistical Model of Quantization Error •
Assumption: eq(x) has a uniform probability density
•
This approximation holds reasonably well in practice when – Signal spans large number of quantization steps – Signal is "sufficiently active" – Quantizer does not overload +∆ / 2
Mean
eq =
∫
−∆ / 2
Variance
eq2 =
+∆ / 2
∫
−∆ / 2
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eq ∆
deq = 0
eq 2 ∆
deq =
∆2 12
38
Reality Check (1) •
Input sequence consists of 1000 samples drawn from Gaussian distribution, 4σ=FSR Mean=-0.004LSB, Var=1.038LSB2/12 150
Count
100
50
0 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
•
0 0.1 0.2 0.3 0.4 0.5 0.6 eq/∆
Error power close to that of uniform approximation EE315B - Chapter 2
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Reality Check (2) •
Another sine wave example, but now fsig/fs=100/1000
•
What's going on here? Mean=-0.000LSB, Var=0.629LSB2/12 500
Count
400 300 200 100 0 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
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0 0.1 0.2 0.3 0.4 0.5 0.6 eq/∆
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Amplitude
Analysis (1)
fsig/fs=100/1000
Time
•
Sampled signal is repetitive and has only a few distinct values – This also means that the quantizer generates only a few distinct values of eq; not a uniform distribution
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Analysis (2) f v sig ( n ) = cos 2π ⋅ in ⋅ n fs
•
Signal repeats every m samples, where m is the smallest integer that satisfies m⋅
•
fin = integer fs
m⋅
101 = integer 1000
⇒ m = 1000
m⋅
100 = integer 1000
⇒ m = 10
This means that eq(n) has at best 10 distinct values, even if we take many more samples
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Signal-to-Quantization-Noise Ratio •
Assuming uniform distribution of eq and a full-scale sinusoidal input, we have
SQNR =
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Psig Pqnoise
=
1 2B ∆ 2 2 2
∆ 12
2
= 1.5 × 22B = 6.02B + 1.76 dB
B (Number of Bits)
SQNR
8
50 dB
12
74 dB
16
98 dB
20
122 dB
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Quantization Noise Spectrum (1) •
How is the quantization noise power distributed in frequency? – First think about applying a sine wave to a quantizer, without sampling (output is continuous time)
+ many more harmonics
[Y. Tsividis, ICASSP 2004]
•
Quantization results in an "infinite" number of harmonics
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Quantization Noise Spectrum (2) •
Now sample the signal at the output – All harmonics (an "infinite" number of them) will alias into band from 0 to fs/2 – Quantization noise spectrum becomes "white"
[Y. Tsividis, ICASSP 2004]
•
Interchanging sampling and quantization won’t change this situation
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Quantization Noise Spectrum (3) •
Can show that the quantization noise power is indeed distributed (approximately) uniformly in frequency – Again, this is provided that the quantization error is "sufficiently random" ∆2 2 ⋅ 12 fs
•
References – W. R. Bennett, "Spectra of quantized signals," Bell Syst. Tech. J., pp. 446-72, July 1948. – B. Widrow, "A study of rough amplitude quantization by means of Nyquist sampling theory," IRE Trans. Circuit Theory, vol. CT-3, pp. 266-76, 1956. – A. Sripad and D. A. Snyder, "A necessary and sufficient condition for quantization errors to be uniform and white," IEEE Trans. Acoustics, Speech, and Signal Processing, pp. 442-448, Oct 1977.
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Ideal DAC •
Essentially a digitally controlled voltage, current or charge source – Example below is for unipolar DAC
•
Ideal DAC does not introduce quantization error!
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Static Nonidealities •
Static deviations of transfer characteristics from ideality – Offset – Gain error – Differential Nonlinearity (DNL) – Integral Nonlinearity (INL)
•
Useful references – Analog Devices MT-010: The Importance of Data Converter Static Specifications • http://www.analog.com/en/content/0,2886,761%255F795%255F91286,00.html
– "Understanding Data Converters," Texas Instruments Application Report LAA013, 1995. • http://focus.ti.com/lit/an/slaa013/slaa013.pdf
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Offset and Gain Error •
Conceptually simple, but lots of (uninteresting) subtleties in how exactly these errors should be defined – Unipolar versus bipolar, endpoint versus midpoint specification – Definition in presence of nonlinearities
•
General idea (neglecting staircase nature of transfer functions):
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ADC Offset and Gain Error •
Definitions based on bottom and top endpoints of transfer characteristic – ½ LSB before first transition and ½ LSB after last transition – Offset is the deviation of bottom endpoint from its ideal location – Gain error is the deviation of top endpoint from its ideal location with offset removed
•
Both quantities are measured in LSB or as percentage of full-scale range Gain Error Dout
Dout
Ideal
Vin
Ideal
Vin
Offset B. Murmann
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DAC Offset and Gain Error •
Same idea, except that endpoints are directly defined by analog output values at minimum and maximum digital input
•
Also note that errors are specified along the vertical axis
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51
Comments on Offset and Gain Errors •
Definitions on the previous slides are the ones typically used in industry – IEEE Standard suggest somewhat more sophisticated definitions based on least square curve fitting • Technically more suitable metric when the transfer characteristics are significantly non-uniform or nonlinear
•
Generally, it is non-trivial to build a converter with very good gain/offset specifications – Nevertheless, since gain and offset affect all codes uniformly, these errors tend to be easy to correct • E.g. using a digital pre- or post-processing operation
– Also, many applications are insensitive to a certain level of gain and offset errors • E.g. audio signals, communication-type signals, ...
•
More interesting aspect: linearity – DNL and INL
B. Murmann
EE315B - Chapter 2
52
Differential Nonlinearity (DNL) •
In an ideal world, all ADC codes would have equal width; all DAC output increments would have same size
•
DNL(k) is a vector that quantifies for each code k the deviation of this width from the "average" width (step size)
•
DNL(k) is a measure of uniformity, it does not depend on gain and offset errors – Scaling and shifting a transfer characteristic does not alter its uniformity and hence DNL(k)
•
Let's look at an example
B. Murmann
EE315B - Chapter 2
53
ADC DNL Example (1)
B. Murmann
EE315B - Chapter 2
Code (k)
W [V]
0
undefined
1
1
2
0.5
3
1
4
1.5
5
0
6
1.5
7
undefined
54
ADC DNL Example (2) •
What is the average code width? – ADC with perfect uniformity would divide the range between first and last transition into 6 equal pieces – Hence calculate average code width (i.e. LSB size) as
Wavg = •
7.5V − 2V = 0.9167V 6
Now calculate DNL(k) for each code k using
DNL(k) =
W(k) − Wavg Wavg
EE315B - Chapter 2
B. Murmann
55
Result Code (k)
DNL [LSB]
1
0.09
2
-0.45
3
0.09
4
0.64
5
-1.00
6
0.64
•
Positive/negative DNL implies wide/narrow code, respectively
•
DNL = -1 LSB implies missing code
•
Impossible to have DNL < -1 LSB for an ADC – But possible to have DNL > +1 LSB
•
Can show that sum over all DNL(k) is equal to zero
B. Murmann
EE315B - Chapter 2
56
A Typical ADC DNL Plot
[Ahmed, JSSC 12/2005]
•
People speak about DNL often only in terms of min/max number across all codes – E.g. DNL = +0.63/-0.91 LSB
•
Might argue in some cases that any code with DNL < -0.9 LSB is essentially a missing code – Why ?
B. Murmann
EE315B - Chapter 2
57
Impact of Noise
[W. Kester, "ADC Input Noise: The Good, The Bad, and The Ugly. Is No Noise Good Noise?" Analogue Dialogue, Feb. 2006]
•
In essentially all moderate to high-resolution ADCs, the transition levels carry noise that is somewhat comparable to the size of an LSB – Noise "smears out" DNL, can hide missing codes
•
Especially for converters whose input referred (thermal) noise is larger than an LSB, DNL is a "fairly useless" metric
B. Murmann
EE315B - Chapter 2
58
DAC DNL •
Same idea applies – Find output increments for each digital code – Find increment that divides range into equal steps – Calculate DNL for each code k using
DNL(k) = •
Step(k) − Stepavg Stepavg
One difference between ADC and DAC is that DAC DNL can be less than -1 LSB – How ?
B. Murmann
EE315B - Chapter 2
59
Non-Monotonic DAC
DNL(3) =
=
Step(3) − Stepavg Stepavg −0.5V − 1V = −1.5LSB 1V
•
In a DAC, DNL < -1LSB implies non-monotinicity
•
How about a non-monotonic ADC?
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EE315B - Chapter 2
60
Non-Monotonic ADC
•
Code 2 has two transition levels ⇒ W(2) is ill defined – DNL is ill-defined!
•
Not a very big issue, because a non-monotonic ADC is usually not what we'll design for in practice…
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EE315B - Chapter 2
61
Integral Nonlinearity (INL) •
General idea – For each "relevant point" of the transfer characteristic, quantify distance from a straight line drawn through the endpoints • An alternative, less common definition uses a least square fit line as a reference
– Just as with DNL, the INL of a converter is by definition independent of gain and offset errors
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EE315B - Chapter 2
62
ADC INL Example (1) •
"Straight line" reference is uniform staircase between first and last transition
•
INL for each code is INL(k) =
T(k) − Tuniform (k) Wavg
•
Obviously INL(1) = 0 and INL(7) = 0
•
INL(0) is undefined
EE315B - Chapter 2
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63
ADC INL Example (2) •
Can show that
k −1
INL(k) = ∑ DNL(i) i =1
•
Means that once we computed DNL, we can easily find INL using a cumulative sum operation on the DNL vector
•
Using DNL values from last lecture, we find
B. Murmann
Code (k)
DNL [LSB]
INL [LSB]
1
0.09
0
2
-0.45
0.09
3
0.09
-0.36
4
0.64
-0.27
5
-1.00
0.36
6
0.64
-0.64
7
undefined
0
EE315B - Chapter 2
64
Result
B. Murmann
EE315B - Chapter 2
65
A Typical ADC DNL/INL Plot
[Ishii, Custom Integrated Circuits Conference, 2005]
•
DNL/INL signature often reveals architectural details – E.g. major transitions – We'll see more examples in the context of DACs
•
Since INL is a cumulative measure, it turns out to be less sensitive than DNL to thermal noise "smearing"
B. Murmann
EE315B - Chapter 2
66
DAC INL •
Same idea applies – Find ideal output values that lie on a straight line between endpoints – Calculate INL for each code k using INL(k) =
•
Vout (k) − Voutuniform (k) Stepavg
Interesting property related to DAC INL – If for all codes |INL| < 0.5 LSB, it follows that all |DNL| < 1 LSB – A sufficient (but not necessary) condition for monotonicity
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EE315B - Chapter 2
67
How to Measure DNL/INL in the Lab? •
DAC – Apply all input codes, measure output with a precision voltmeter
•
ADC – A little more tricky – One option is to build a servo loop that finds the code transitions • See e.g. Kester, page 5.36
– A more popular approach is histogram testing
B. Murmann
EE315B - Chapter 2
68
Basic Histogram Test Setup
Kester, p. 5.39
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EE315B - Chapter 2
69
Histogram Example
Kester, p. 5.40
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EE315B - Chapter 2
70
Sinusoidal Input Kester, p. 5.42
B. Murmann
•
Preferred over ramp or triangular test signals
•
It is easier much easier to generate a “high fidelity” sinusoid
•
The histogram now takes on a bathtub shape, which can be mathematically inverted to find the DNL
EE315B - Chapter 2
71
Correction for Sinusoidal pdf •
References – M. V. Bossche, J. Schoukens, and J. Renneboog, “Dynamic Testing and Diagnostics of A/D Converters,” IEEE TCAS, Aug. 1986 – IEEE Standard 1057 – Kester, Section 5.4
•
It turns out that is not necessary to know the exact amplitude and offset of the sine wave input – There exists some confusion about this…
•
The code on the next slide does all the required math to undo the bathtub shape
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EE315B - Chapter 2
72
DNL/INL Code function [dnl,inl] = dnl_inl_sin(y);
% transition levels
%DNL_INL_SIN
T = -cos(pi*ch/sum(h));
% dnl and inl ADC output % input y contains the ADC output
% linearized histogram
% vector obtained from quantizing a
hlin = T(2:end) - T(1:end-1);
% sinusoid % truncate at least first and last % Boris Murmann, Aug 2002
% bin, more if input did not clip ADC
% Bernhard Boser, Sept 2002
trunc=2; hlin_trunc = hlin(1+trunc:end-trunc);
% histogram boundaries minbin=min(y);
% calculate lsb size and dnl
maxbin=max(y);
lsb= sum(hlin_trunc) / (length(hlin_trunc)); % histogram
dnl= [0 hlin_trunc/lsb-1];
h = hist(y, minbin:maxbin);
misscodes = length(find(dnl<-0.9));
% cumulative histogram
% calculate inl
ch = cumsum(h);
inl= cumsum(dnl);
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73
DNL/INL Code Test % converter model B = 6;
DNL = +0.7 / -0.71 LSB, 0 missing codes (DNL<-0.9)
% bits
1
range = 2^(B-1) - 1;
th = -range:range;
% ideal thresholds
DNL [LSB]
0.5
% thresholds (ideal converter)
0
-0.5
th(20) = th(20)+0.7; % error -1 -30
0 code
10
20
30
10
20
30
0.8
% try fs/10!
= round(100 * 2^B / (fs / fx));
t = 0:1/fs:C/fx; x = (range+1) * sin(2*pi*fx.*t);
0.6 INL [LSB]
C
-10
INL = +0.76 / -0.063 LSB
fs = 1e6; fx = 494e3 + pi;
-20
0.4 0.2 0 -0.2 -30
-20
-10
0 code
y = adc(x, th) - 2^(B-1);
hist(y, min(y):max(y)); dnl_inl_sin(y);
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EE315B - Chapter 2
74
Limitations of ADC Histogram Testing •
Cannot detect non-monotonicity – The histogram does not capture in which order the codes occurred
•
Cannot detect erratic dynamics – E.g. 123, 123, …, 123, 0, 124, 124, … – Must look directly at ADC output to detect these
•
Similarly, random noise is not detected and improves DNL – E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …
•
Reference – B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution ADCs,” Electronics Letters, pp. 22312233, Nov. 1991
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EE315B - Chapter 2
75
Hiding DNL Problems in the Noise
•
INL suggests that there may be missing codes
•
But, DNL is "smeared out" by noise and does not show this
•
Always look at both DNL/INL
•
INL usually does not lie [Source: David Robertson, Analog Devices]
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EE315B - Chapter 2
76
Spectral Performance Metrics
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
B. Murmann
EE315B - Chapter 3
1
Dynamic Performance Metrics •
Time domain – Glitch impulse, aperture uncertainty, settling time, … – We'll look at these later, in the context of specific circuits
•
Frequency domain – Performance metrics follow from looking at converter or building block output spectrum • "Spectral performance metrics"
– Basic idea: Apply one or more tones at converter input • Expect same tone(s) at output, all other frequency components represent nonidealities
– Important to realize that both static (DNL, INL) and dynamic errors contribute to frequency domain non-ideality
B. Murmann
EE315B - Chapter 3
2
Alphabet Soup of Spectral Metrics •
SNR - Signal-to-noise ratio
•
SNDR (SINAD) - Signal-to-(noise+distortion) ratio
•
ENOB - Effective number of bits
•
DR - Dynamic range
•
SFDR - Spurious free dynamic range
•
HD – Harmonic distortion
•
THD - Total harmonic distortion
•
ERBW - Effective Resolution Bandwidth
•
IMD - Intermodulation distortion
•
MTPR - Multi-tone power ratio
B. Murmann
EE315B - Chapter 3
3
DAC Tone Test/Simulation Setup
B. Murmann
EE315B - Chapter 3
4
Typical DAC Output Spectrum
[Hendriks, "Specifying Communications DACs, IEEE Spectrum, July 1997]
B. Murmann
EE315B - Chapter 3
5
ADC Tone Test/Simulation Setup
•
Basic idea – Apply a clean sinusoid – Compute ADC performance metrics based on output spectrum
B. Murmann
EE315B - Chapter 3
6
Aside: How to Make a Clean Sinusoid in the Lab? BP Filter Amplitude Signal generator harmonics
0
fin
2fin
3fin
4fin
... ...
f
www.tte.com, or www.allenavionics.com
EE315B - Chapter 3
B. Murmann
7
Discrete Fourier Transform Basics •
DFT takes a block of N time domain samples (spaced Ts=1/fs) and yields a set of N frequency bins N−1
X(k) =
∑ x(n)e− j2πkn/N
n=0
•
Bin k represents frequency content at k·fs/N [Hz]
•
DFT frequency resolution – Proportional to 1/(N·Ts) in [Hz/bin] – N·Ts is total time spent gathering samples
•
A DFT with N=2integer can be found using a computationally efficient algorithm – FFT = Fast Fourier Transform
B. Murmann
EE315B - Chapter 3
8
Matlab Example clear; N
50
= 100;
fs = 1000;
40
x = cos(2*pi*fx/fs*[0:N-1]); s = abs(fft(x)); plot(s, 'linewidth', 2);
DFT Magnitude
fx = 100;
30
20
10
0 0
20
40
60
80
100
Bin #
B. Murmann
EE315B - Chapter 3
9
Normalized Plot with Frequency Axis N
= 100;
fs = 1000;
0
fx = 100; FS = 1; % full-scale amplitude
s = abs(fft(x)); % remove redundant half of spectrum s = s(1:end/2); % normalize magnitudes to dBFS % dbFS = dB relative to full-scale s = 20*log10(2*s/N/FS);
DFT Magnitude [dBFS]
x = FS*cos(2*pi*fx/fs*[0:N-1]);
-50 -100 -150 -200 -250
% frequency vector f = [0:N/2-1]/N;
plot(f, s, 'linewidth', 2);
-300 -350 0
xlabel('Frequency [f/fs]')
0.1
0.2 0.3 Frequency [f/fs]
0.4
0.5
ylabel('DFT Magnitude [dBFS]')
B. Murmann
EE315B - Chapter 3
10
Another Example 0
Same as before, but now fx=101
•
This doesn't look the spectrum of a sinusoid…
•
-10 DFT Magnitude [dBFS]
•
What's going on?
-20 -30 -40 -50 -60 -70 -80 -90 0
0.1
0.2 0.3 Frequency [f/fs]
EE315B - Chapter 3
B. Murmann
0.4
0.5
11
Spectral Leakage •
The DFT computes the spectrum of the periodic repetition of its input
•
A sequence that contains a noninteger number of sine wave cycles has discontinuities in its periodic repetition – Discontinuity looks like a high frequency signal component – Power spreads across spectrum
•
Two ways to deal with this – Ensure integer number of periods – Windowing
B. Murmann
EE315B - Chapter 3
12
Integer Number of Cycles 0 N
= 100;
-50 DFT Magnitude [dBFS]
cycles = 9; fs = 1000; fx = fs*cycles/N;
•
Usable test frequencies are limited to a multiple of fs/N
-100 -150 -200 -250 -300 -350 0
0.1
0.2 0.3 Frequency [f/fs]
0.4
0.5
EE315B - Chapter 3
B. Murmann
13
Windowing •
Spectral leakage can be attenuated by windowing the time samples prior to the DFT
•
Windows taper smoothly down to zero at the beginning and the end of the observation window
•
Time domain samples are multiplied by window coefficients on a sample-by-sample basis – Means convolution in frequency – Sine wave tone and other spectral components smear out over several bins
•
Lots of window functions to chose from – Tradeoff: attenuation versus smearing
•
Example: Hann Window
B. Murmann
EE315B - Chapter 3
14
Hann Window N=64; wvtool(hann(N))
Time domain
Frequency domain 50
1 0 Magnitude (dB)
Amplitude
0.8
0.6
0.4
-50
-100 0.2
0
10
20
30 40 Samples
50
-150
60
0
0.2
0.4
0.6
0.8
Normalized Frequency ( ×π rad/sample)
EE315B - Chapter 3
B. Murmann
15
Spectrum with Window N
0
= 100;
No window Hann window
fs = 1000;
-20
A
= 1;
x = A*cos(2*pi*fx/fs*[0:N-1]); s
= abs(fft(x));
x1 = x.*hann(N); s1 = abs(fft(x1));
DFT Magnitude [dBFS]
fx = 101;
-40 -60 -80 -100 -120 -140 0
0.1
0.2
0.3
0.4
0.5
f/fs B. Murmann
EE315B - Chapter 3
16
Integer Cycles versus Windowing •
Integer number of cycles – Test signal falls into single DFT bin – Requires careful choice of signal frequency – Ideal for simulations – In lab measurements, can lock sampling and signal frequency generators (PLL) • "Coherent sampling"
•
Windowing – No restrictions on signal frequency – Signal and harmonics distributed over several DFT bins • Beware of smeared out nonidealities…
– Requires more samples for given accuracy •
More info – http://www.maxim-ic.com/appnotes.cfm/appnote_number/1040 EE315B - Chapter 3
B. Murmann
17
Example •
Now that we've "calibrated" our test system, let's look at some spectra that involve nonidealities
N
= 2048;
cycles = 67; fs = 1000; fx = fs*cycles/N; LSB = 2/2^10;
%generate signal, quantize (mid-tread) and take FFT
•
First look at quantization noise introduced by an ideal quantizer
x = cos(2*pi*fx/fs*[0:N-1]); x = round(x/LSB)*LSB; s
= abs(fft(x));
s = s(1:end/2)/N*2;
% calculate SNR sigbin = 1 + cycles; noise = [s(1:sigbin-1), s(sigbin+1:end)]; snr = 10*log10( s(sigbin)^2/sum(noise.^2) );
B. Murmann
EE315B - Chapter 3
18
Spectrum with Quantization Noise 2048 point FFT, SNR=61.90dB 0
•
Spectrum looks fairly uniform
•
Signal-to-quantization noise ratio is given by power in signal bin, divided by sum of all noise bins
DFT Magnitude [dBFS]
-20
-40
-60
-80
-100
-120 0
0.1
0.2 0.3 Frequency [f/fs]
0.4
EE315B - Chapter 3
B. Murmann
0.5
19
SQNR 2048 point FFT, SNR=61.90dB
=
Signal Power Quantization Noise Power 1 VFS 2 2
-20
2
1 VFS 12 2N
2
=
3 2N ⋅2 2
= 6.02 ⋅ N + 1.76 [dB] = 6.02 ⋅ 10 + 1.76 [dB]
DFT Magnitude [dBFS]
SQNR =
0
-40
-60
-80
-100
= 61.9 dB -120 0
B. Murmann
EE315B - Chapter 3
0.1
0.2 0.3 Frequency [f/fs]
0.4
0.5
20
FFT Noise Floor 2048 point FFT, SNR=61.90dB 0
= −61.9 dBc − 30.1 dB = −92 dBc
•
Depends on FFT size
•
Plot is “useless” if FFT size is not specified
-20 DFT Magnitude [dBFS]
2048 Nfloor = −61.9 dBc − 10log 2
-40
-60
-80
-100
-120 0
B. Murmann
0.1
0.2 0.3 Frequency [f/fs]
0.4
EE315B - Chapter 3
0.5
21
DFT Plot Annotation •
DFT plots are fairly meaningless unless you clearly specifiy the underlying conditions
•
Most common annotation – Specify how many DFT points were used (N)
•
Less common options – Shift DFT noise floor by 10log10(N/2)dB – Normalize with respect to bin width in Hz and express noise as power spectral density • "Noise power in 1 Hz bandwidth"
B. Murmann
EE315B - Chapter 3
22
Periodic Quantization Noise Same as before, but cycles = 64 (instead of 67)
•
fx = fs⋅64/2048 = fs/32
•
Quantization noise is highly deterministic and periodic
•
2048 point FFT, SNR=65.09dB 0 -20
For more random and "white" quantizion noise, it is best to make N and cycles mutually prime – GCD(N,cycles)=1
DFT Magnitude [dBFS]
•
-40 -60 -80 -100 -120 0
0.1
0.2 0.3 Frequency [f/fs]
0.4
EE315B - Chapter 3
B. Murmann
0.5
23
Typical ADC Output Spectrum Fairly uniform noise floor due to additional electronic noise
•
Harmonics due to nonlinearities
•
Definition of SNR SNR =
•
-20
Signal Power Total Noise Power
Total noise power includes all bins except DC, signal, and 2nd through 7th harmonic – Both quantization noise and electronic noise affect SNR
B. Murmann
2048 point FFT, SNR=55.99dB 0
DFT Magnitude [dBFS]
•
-40 -60 -80 -100 -120 0
EE315B - Chapter 3
0.1
0.2 0.3 0.4 Frequency [f/fs]
24
SNDR and ENOB Definition SNDR =
•
Signal Power Noise and Distortion Power
Noise and distortion power includes all bins except DC and signal
•
2048 point FFT, SNR=55.9dB, SNDR=47.5dB 0
Effective number of bits ENOB =
SNDR(dB)-1.76dB 6.02dB
-20 DFT Magnitude [dBFS]
•
-40 -60 -80 -100 -120 0
0.1
0.2 0.3 0.4 Frequency [f/fs]
EE315B - Chapter 3
B. Murmann
25
Effective Number of Bits •
Is a 10-Bit converter with 47.5dB SNDR really a 10-bit converter? ENOB =
47.5dB − 1.76dB = 7.6 6.02dB
•
We get ideal ENOB only for zero electronic noise, perfect transfer function with zero INL, ...
•
Low electronic noise is costly – Cutting thermal noise down by 2x, can cost 4x in power dissipation
•
Rule of thumb for good power efficiency: ENOB < B-1 – B is the "number of wires" coming out of the ADC or the so called "stated resolution"
B. Murmann
EE315B - Chapter 3
26
Survey Data
SNRBits =
SNR(dB)-1.76dB 6.02dB
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on Selected Areas in Communications, pp. 539-50, April 1999
EE315B - Chapter 3
B. Murmann
27
Dynamic Range DR =
Maximum Signal Power ≥ SNRpeak Minimum Detectable Signal
SNR (dB) PEAK SNR
OVERLOAD
FULL SCALE 0dB DYNAMIC RANGE
MDS
B. Murmann
EE315B - Chapter 3
INPUT Input Power AMPLITUDE [dB] (dB)
28
SFDR Definition of "Spurious Free Dynamic Range" SFDR =
•
Signal Power Largest Spurious Power
Largest spur is often (but not necessarily) a harmonic of the input tone
2048 point FFT, SFDR=48.3dB 0 -20 DFT Magnitude [dBFS]
•
-40 -60 -80 -100 -120 0
0.1
0.2 0.3 0.4 Frequency [f/fs]
EE315B - Chapter 3
B. Murmann
29
SDR and THD •
Signal-to-distortion ratio
2048 point FFT, THD=-48.2dB 0
Signal Power SDR = Total Distortion Power
•
Total harmonic distortion THD =
•
•
Total Distortion Power 1 = Signal Power SDR
By convention, total distortion power consists of 2nd through 7th harmonic Is there a 6th and 7th harmonic in the plot to the right?
B. Murmann
DFT Magnitude [dBFS]
-20 -40 -60 -80 -100 -120 0
EE315B - Chapter 3
0.1
0.2 0.3 0.4 Frequency [f/fs]
30
Lowering the Noise Floor 65536 point FFT, THD=-48.3dB 0
Increasing the FFT size let's us lower the noise floor and reveal low level harmonics
-20 DFT Magnitude [dBFS]
•
-40 -60 -80 -100 -120 0
0.1
0.2 0.3 0.4 Frequency [f/fs]
EE315B - Chapter 3
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31
Aliasing 65536 point FFT, THD=-48.3dB
Harmonics can appear at "arbitrary" frequencies due to aliasing f1 = fx = 0.3125 fs f2 = 2 f1 = 0.6250 fs 0.3750 fs f3 = 3 f1 = 0.9375 fs 0.0625 fs f4 = 4 f1 = 1.2500 fs 0.2500 fs f5 = 5 f1 = 1.5625 fs 0.4375 fs
0 -20 DFT Magnitude [dBFS]
•
-40 -60 -80 -100 -120 0
B. Murmann
EE315B - Chapter 3
0.1
0.2 0.3 Frequency [f/fs]
0.4
0.5
32
Intermodulation Distortion
Amplitude
f1
f2
SECOND ORDER PRODUCTS
f2 - f1
THIRD ORDER PRODUCTS
2f1 - f2
2f2 - f1
f1 + f2
f
Frequency
•
IMD is important in multi-channel communication systems – Third order products are generally difficult to filter out EE315B - Chapter 3
B. Murmann
33
MTPR
Amplitude [dB]
0
MTPR
-20 -40 -60 -80 -100 -120 0.00E+00
4.00E+06
8.00E+06
1.20E+07
1.60E+07
2.00E+07
2.40E+07
2.80E+07
3.20E+07
Frequency(Hz) Frequency [Hz]
•
Useful metric in multi-tone transmission systems – E.g. OFDM
B. Murmann
EE315B - Chapter 3
34
Frequency Dependence (1) •
All of the above discussed metrics generally depend on frequency – Sampling frequency and input frequency
[Analog Devices, AD9203 Datasheet ]
B. Murmann
EE315B - Chapter 3
35
Frequency Dependence (2)
[Texas Instruments, ADS5541 Datasheet ]
B. Murmann
EE315B - Chapter 3
36
ERBW •
Defined as the input frequency at which the SNDR of a converter has dropped by 3dB – Equivalent to a 0.5-bit loss in ENOB
•
ERBW > fs/2 is not uncommon, especially in converters designed for sub-sampling applications
•
ERBW is only a useful metric when the SNDR is relatively flat initially and gracefully degrades at high frequencies
EE315B - Chapter 3
B. Murmann
37
Relationship Between INL and Harmonic Distortion (1) •
The INL of an ADC often takes on a quadratic or cubic “bow” – Meaning that the transfer function can be approximated by x+a2x2 or x+a3x3
•
The resulting harmonic distortion usually sets the low frequency SFDR
Output
Ideal Quadratic bow Cubic bow
Input
B. Murmann
EE315B - Chapter 3
38
Relationship Between INL and Harmonic Distortion (2) •
The expression below provides an analytical relationship between the peak INL due a cubic bow and the resulting HD3
•
The result provides a reasonable bound even if the INL is not perfectly cubic – Rule of thumb: HD ≅ -20log(2B/INL) – E.g. 1 LSB INL at 10 bits HD ≅ -60 dB
ଷ ≅ 20
2 3 3 ௫ 4
Example of a cubic INL [Lee, JSSC 12/2007]
B. Murmann
39
SNR Degradation due to DNL (1)
[Source: Ion Opris]
•
For an ideal quantizer we assumed uniform quatization error over ±∆/2
•
Let's add uniform DNL over ± 0.5 LSB and repeat math...
B. Murmann
EE315B - Chapter 3
40
SNR Degradation due to DNL (2) •
Integrate triangular pdf +∆
e =2∫ 2
0
•
e e2 ∆2 1 − ∆ ∆ de = 6
⇒ SNR = 6.02 ⋅ B − 1.25 [dB]
3dB
Compare to ideal quantizer +∆ /2
e2 ∆2 e = ∫ de = 12 ∆ −∆ /2 2
•
⇒ SNR = 6.02 ⋅ B + 1.76 [dB]
Bottom line: non-zero DNL across many codes can easily cost a few dB in SNR – "DNL noise" EE315B - Chapter 3
B. Murmann
41
Noise Figure of an ADC
2
2 Vin,rms =
Pin = B. Murmann
1 ˆ 2 1 VFS 1 V = = 1V 2 2 2 2 2
2 Vin,rms
R
=
1 1V 2 = 10mW = 10dBm 2 50Ω
EE315B - Chapter 3
42
Quantization Noise in 1Hz 2048 point FFT, SNR=61.90dB 0
-20
100MHz = 10dBm − 61.9dB − 10log 1Hz = −131.9
dBm Hz
DFT Magnitude [dBFS]
NPSD
fs = Pin − SQNR − 10log 2 1 Hz
-40
-60
-80
For comparison: -100
NPSD,Rsource
dBm = −174 Hz
-120 0
0.1
0.2 0.3 Frequency [f/fs]
EE315B - Chapter 3
B. Murmann
0.4
43
Spot Noise Figure (1)
F=
Total Noise at ADC Input Noise due to ADC ≅ Noise due to Source Resistor Noise due to Source Resistor
NF = 10log(F) = 174
dBm dBm − 131.9 = 43.1dB Hz Hz
• Ouch!
B. Murmann
EE315B - Chapter 3
44
0.5
Spot Noise Figure (2) fs dBm + Pin − SQNR − 10log 2 NF = 174 Hz 1 Hz 1 V 2 fs FS 2 dBm 3 2 2 2N = 174 + 10log − − 10log 2 10log Hz R 2 1 Hz
• Improve NF by increasing R (need a transformer), resolution (N) and fs B. Murmann
EE315B - Chapter 3
45
Real World Example
Analog Devices, Tutorial MT-006 B. Murmann
EE315B - Chapter 3
46
Nyquist Rate DACs
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
B. Murmann
EE315B - Chapter 4
1
Overview •
D/A conversion is typically accomplished through the division or multiplication of a reference voltage, current or charge
•
Basic configurations – Thermometer – Binary weighted – Segmented
•
Implementation choices – Resistive, capacitive, current steering – Nyquist rate, oversampling, PWM – …
•
Our discussion will focus mainly on high-speed current steering
B. Murmann
EE315B - Chapter 4
2
Resistor String DAC
VRE F
MSB
LSB
xxxxx
xxxxx
d0
d0
d1
d1
d2
d2
•
Simple, inherently monotonic
•
Small area up to ~8 bits
•
See e.g. Pelgrom, JSSC 12/1990
•
Unsuitable for highresolution, high-speed designs
OUT
B. Murmann
EE315B - Chapter 4
3
Thermometer DAC Using Switched Currents
B. Murmann
EE315B - Chapter 4
•
Inherently monotonic
•
Need large encoder with 2B-1 outputs – Impractical for large B (high resolution)
4
Thermometer DAC Principle 15
Output
0
14
14
13
13
13
12
12
12
12
11
11
11
11
11
10
10
10
10
10
10
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Input Code B. Murmann
EE315B - Chapter 4
5
Binary Weighted DAC
B. Murmann
EE315B - Chapter 4
•
No encoder needed
•
Monotonicity is not guaranteed
•
Consider transition 100000…. to 011111…. – 2B-1 source must match sum of others to within 1 LSB to make transition monotonic
6
Binary Weighted DAC Principle
MSB Transition Problem
B. Murmann
EE315B - Chapter 4
7
Implementation of Weighted Elements
B. Murmann
EE315B - Chapter 4
8
Segmented DAC
B. Murmann
•
Binary weighted section with Bb bits
•
Thermometer section with Bt = B-Bb bits
•
Typically Bt ~ 4…8
•
Reasonably small encoder
•
Easier to achieve monotonicity
EE315B - Chapter 4
9
Segmented DAC (2-2) Transition Problem Limited to LSB Section
B. Murmann
EE315B - Chapter 4
10
Static Errors (1) •
DNL and INL due to unit element mismatch
•
Systematic Errors – Contact and wiring resistance (IR drop) – Edge effects in unit element arrays – Process gradients – Finite current source output resistance
•
Systematic errors can be mitigated by proper layout and switching sequence design – See e.g. [Lin, JSSC 12/98], [Van der Plas, JSSC 12/99]
B. Murmann
EE315B - Chapter 4
11
Static Errors (2) •
In the best possible scenario, we are then limited by “random” errors, which are due to material roughness, randomness in etching, etc.
•
The distribution of random errors is usually well approximated by a Gaussian PDF (central limit theorem)
•
References – C. Conroy et al., “Statistical Design Techniques for D/A Converters,” IEEE J. Solid-State Ckts., pp. 1118-28, Aug. 1989. – P. Crippa, et al., "A statistical methodology for the design of highperformance CMOS current-steering digital-to-analog converters," IEEE Trans. CAD of ICs and Syst. pp. 377-394, Apr. 2002.
B. Murmann
EE315B - Chapter 4
12
Gaussian Distribution
f(x) =
−
1 2πσ
( x −µ )2 2 σ2
e
X=
x −µ σ
0.4
f(x)
0.3
0.2
0.1
0 -3
-2
-1
0 x/Xσ
1
2
3
EE315B - Chapter 4
B. Murmann
13
Yield (1) 2
P ( −C ≤ X ≤ +C ) =
1 2π
+C − X e 2
∫
−C
C dX = erf 2
1
P(-C C) P(-X ≤≤ xX≤ ≤+X)
0.8
0.6
0.4
0.2
0 0
0.5
1
1.5 X/σ
2
2.5
3
C
B. Murmann
EE315B - Chapter 4
14
Yield (2) C
P(-C ≤ X ≤ C) [%]
C
P(-C ≤ X ≤ C) [%]
0.2000
15.8519
2.2000
97.2193
0.4000
31.0843
2.4000
98.3605
0.6000
45.1494
2.6000
99.0678
0.8000
57.6289
2.8000
99.4890
1.0000
68.2689
3.0000
99.7300
1.2000
76.9861
3.2000
99.8626
1.4000
83.8487
3.4000
99.9326
1.6000
89.0401
3.6000
99.9682
1.8000
92.8139
3.8000
99.9855
2.0000
95.4500
4.0000
99.9937
EE315B - Chapter 4
B. Murmann
15
Example •
Measurements show that the current in a production lot of current sources follows a Gaussian distribution with σ = 0.1 mA and µ = 10 mA – What fraction of current sources is within ±3% (or ±1%) of the mean?
•
Relative matching ("coefficient of variation") σu =
σ ∆I 0.1mA = stdev = = 1% µ I 10mA
•
Fraction of current sources within 3% – C = 3 99.73%
•
Fraction of current sources within 1% – C = 1 68.27%
B. Murmann
EE315B - Chapter 4
16
Mismatch in MOS Current Sources ∆I = I1 − I2 ≅ −gm∆Vt + I1
∆β β
g ∆I ∆β ≅ − m ∆Vt + I1 I1 β β=
•
1 W µCox 2 L
σ∆Vt =
A Vt
σ ∆β =
WL
β
Aβ WL
Example – W=500µm, L=0.2µm, gm/ID=10S/A, AVt=5mV-µm, Aβ=1%-µm 2
2
S 5mV 1% σ ∆I = 10 ⋅ + = A 10 10 I
( 0.5%)2 + ( 0.1%)2
= 0.51%
1
EE315B - Chapter 4
B. Murmann
17
DNL of Thermometer DAC
DNL(k) =
Step(k) − Stepavg Stepavg
Ik − =
1 N ∑I N j =1 j N
≅
1 ∑I N j =1 j
Ik − I ∆I = I I
∆I stdev (DNL(k) ) = stdev = σu I
•
Standard deviation of DNL for each code is simply equal to relative matching (σu) of unit elements
•
Example – Say we have unit elements with σu = 1% and want 99.73% of all converters to meet the spec – Which DNL specification value should go into the datasheet?
B. Murmann
EE315B - Chapter 4
18
DNL Yield Example (1) •
First cut solution – For 99.73% yield, need C = 3 – σDNL = σu = 1% – 3 σDNL = 3% – DNL specification for a yield of 99.73% is ±0.03 LSB • Independent of target resolution (?)
•
Not quite right – Must keep in mind that a converter will meet specs only if all codes meet DNL spec, i.e. DNL(k) < DNLspec for all k – A converter with more codes is less likely to have all codes meet the specification – Let's see if this is significant
B. Murmann
EE315B - Chapter 4
19
DNL Yield Example (2) •
Let's say there are N codes, and assume that all DNL(k) values are independent, then – P(all codes meet spec) = P(single code meets spec)N – P(all codes meet spec)1/N = P(single code meets spec)
•
Lets look at two examples N=63 (6 bits) and N=4095 (12 bits) – 0.99731/63 = 0.99995708… – 0.99731/4095 = 0. 99999929929…
•
Can calculate modified confidence intervals using Matlab – For N=63, C = sqrt(2)*erfinv(0.99731/63) = 4.09 – For N=4095, C = sqrt(2)*erfinv(0.99731/4095) = 4.97
•
Refined result for 99.97% yield – N=63: DNL spec should be ±0.0409 LSB – N=4095: DNL spec should be ±0.0497 LSB
B. Murmann
EE315B - Chapter 4
20
DNL Yield Example (3) •
Getting a more accurate yield estimate for the preceding example wasn't all that hard – Unfortunately things won't always be that simple • E.g. in a segmented DAC, DNL(k) are no longer independent
•
The "typical" DAC designer tends to rely on simulations rather than trying to formulate "exact" yield equations – Get rough estimate using simple (often optimistic) expressions – Run "Monte Carlo" simulations in Matlab to find actual yield or to center specs – Still important to have a qualitative feel for what may cause discrepancies
EE315B - Chapter 4
B. Murmann
21
INL (1) INL(k) =
Iout (k) − Iout,uniform (k) Stepavg k
∑ Ij − =
=
j =1
k N ∑I N j=1 j
1 N ∑I N j =1 j
k
N∑ Ij =
j =1 k
∑ Ij + ∑ j =1
−k
N
Ij
j = k +1
A ⋅N −k A +B
A ⋅N A X var (INL(k) ) = var − k = N2 var = N2 var A +B A +B Y B. Murmann
EE315B - Chapter 4
22
INL (1) •
For a quotient of random variables X µ var ≅ X Y µY
2
σ2X σ2Y cov ( X, Y ) 2 + 2 − 2 µ µ µ µ X Y Y X
[Dennis E. Blumenfeld, Operations Research Calculations Handbook, Online: http://www.engnetbase.com/ejournals/books/book_summary/toc.asp?id=701]
•
After identifying the means (µ), variances (σ2) and covariance (cov) needed in the above approximation, it follows that k var (INL(k)) ≅ k 1 − σu2 N k σINL (k) ≅ σu k 1 − N EE315B - Chapter 4
B. Murmann
23
INL (2) 6 σINL (k)/σu
N=64 N=128 4
2
0
0
20
40
60
80
100
120
140
k
•
Standard deviation of INL is maximum at mid-scale (k=N/2) σINL ≅ σu
•
N N/ 2 1 1 = σu N ≅ σu 2B 1− 2 N 2 2
For a more elaborate derivation of this result see [Kuboki et al., IEEE Trans. Circuits & Systems, 6/1982]
B. Murmann
EE315B - Chapter 4
24
Achievable Resolution σ 2 σ B ≅ log2 4 INL = 2 + 2log2 INL σ σu u
•
Example: σINL= 0.1 LSB (at mid-scale code) σu
B
1%
8.6
0.5%
10.6
0.2%
13.3
0.1%
15.3
EE315B - Chapter 4
B. Murmann
25
INL Yield •
Again, we should ask how many DACs will meet the spec for a given σINL (worst code) – It turns out that this is a very difficult math problem
•
Two solutions – Do the math • G. I. Radulov et al., "Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch," IEEE TCAS II, pp. 146-150, Feb. 2007.
– Yield simulations •
Good rule of thumb – For high target yield (>95%), the probability of "all codes meet INL spec" is very close to "worst code meets INL spec"
B. Murmann
EE315B - Chapter 4
26
DNL/INL of Binary Weighted DAC •
INL same as for thermometer DAC – Why?
•
DNL is not same for all codes, but depends on transition
•
Consider worst case: 0111 … 1000 … – Turning on MSB and turning off all LSBs
(
)
(
)
(
)
2 σDNL = 2B −1 − 1 σu2 + 2B −1 σu2 = 2B − 1 σu2 14 4244 3 1424 3 0111...
•
1000...
8I
4I
2I
I
Example – B = 12, σu = 1% σDNL = 0.64 LSB – Much worse than thermometer DAC EE315B - Chapter 4
B. Murmann
27
σDNL (4-bit Example) 15
2 σ )22 σ( σDNL D NL //σ εu
10
5
0
0
2
4
6 8 DAC input code
10
12
14
code
B. Murmann
EE315B - Chapter 4
28
Simulation Example DNL and INL of 12 Bit converter (from converter decision thresholds) DNL [in LSB]
2 -1 / +0.1 LSB, avg=-9.3e-005, std.dev=0.035, range=1.4 -1.3
1 0 -1 -2
500
1000
1500
2000 bin code
2500
3000
3500
4000
INL [in LSB]
2 -0.8 / +0.8 LSB, avg=-1.1e-013, std.dev=0.37, range=1.6
1 0 -1
500
1000
1500
2000 bin code
2500
3000
3500
4000
EE315B - Chapter 4
B. Murmann
29
Another Random Run DNL and INL of 12 Bit converter (from converter decision thresholds)
DNL [in LSB]
2 1
-0.9 / +0.4 LSB, avg=-7.5e-005, std.dev=0.039, range=1.3
0 -1
500
1000
1500
2000
2500
3000
3500
4000
bin code
INL [in LSB]
2 1
-0.7 / +0.7 LSB, avg=3.3e-014, std.dev=0.33, range=1.3
0 -1
500
1000
1500
2000
2500
3000
3500
4000
bin code
• Peak DNL not at mid-scale! – Important to realize that this is just one single statistical outcome… B. Murmann
EE315B - Chapter 4
30
Multiple Simulation Runs (100) Overlay Plot
RMS DNL and INL
[Lin & Bult, JSSC 12/1998] EE315B - Chapter 4
B. Murmann
31
DNL/INL of Segmented DAC •
•
INL – Same as in thermometer DAC
Example: B=Bb+Bt=4+4=8
DNL – Worst case occurs when LSB DAC turns off and one more MSB DAC element turns on – Essentially same DNL as a binary weighted DAC with Bb+1 bits
B. Murmann
16I
8I
EE315B - Chapter 4
16I
4I
16I
2I
I
32
Comparison
Thermometer
σINL
≅ (worst case) σDNL (worst case) Number of Switched Elements
Binary Weighted
Segmented
1 σu 2B 2
≅ σu
≅ σu 2Bb +1 − 1
≅ σu 2B − 1
2B − 1
Bb + 2Bt − 1
B
EE315B - Chapter 4
B. Murmann
33
Example (B=12, σu=1%)
σINL
σDNL
(worst)
(worst)
Number of Switched Elements
Thermometer
0.32
0.01
4095
Binary Weighted
0.32
0.64
12
Segmented (Bb=7, Bt=5)
0.32
0.16
38
DAC Architecture
B. Murmann
EE315B - Chapter 4
34
Dynamic DAC Errors (1) •
Finite settling time and slewing – Finite RC time constant – Signal dependent slewing
•
Feedthrough – Coupling from switch signals to DAC output – Clock feedthrough
•
Glitches due to timing errors – Current sources won’t switch simultaneously
•
Dynamic DAC errors are generally hard to model!
B. Murmann
EE315B - Chapter 4
35
Dynamic DAC Errors (2) •
References – Gustavsson, Chapter 12 – M. Albiol, J.L. Gonzalez, E. Alarcon, "Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters," IEEE TCAS I, pp. 159-169, Jan. 2004 – Doris, van Roermund, Leenaerts, Wide-Bandwidth High Dynamic Range D/A Converters, Springer 2006. – T. Chen and G.G.E. Gielen, "The analysis and improvement of a current-steering DAC's dynamic SFDR," IEEE Trans. Ckts. Syst. I, pp. 3-15, Jan. 2006.
B. Murmann
EE315B - Chapter 4
36
Glitch Impulse (1) •
DAC output waveform depends on timing – Consider binary weighted DAC transition 0111… 1000…
ideal
10
Ideal
5
0 1
1.5
2
2.5
3
early
10
LSBs early, MSB late
5
0 1
1.5
2
2.5
3
late
10
LSBs late, MSB early
5
0 1
1.5
2 Time
2.5
3
EE315B - Chapter 4
B. Murmann
37
Glitch Impulse (2) •
Worst case glitch impulse (area): ∝∆t 2B-1
•
LSB area: ∝T
•
Need ∆t 2B-1 << T which implies ∆t << T/2B-1
B. Murmann
fs [MHz]
B
∆t [ps]
1
12
<< 488
20
16
<< 1.5
1000
10
<< 2
EE315B - Chapter 4
38
Commercial Example
B. Murmann
EE315B - Chapter 4
39
Implementation Example
[T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, “An 80-MHz 8bit CMOS D/A Converter,” IEEE J. of Solid-State Circuits, pp. 983-988, Dec. 1986.]
B. Murmann
EE315B - Chapter 4
40
Mitigating IR Drop
B. Murmann
EE315B - Chapter 4
41
Basic Differential Pair Switch
B. Murmann
EE315B - Chapter 4
42
Commonly Used Techniques •
Retiming – Latches in (or close to) each current cell – Latch controlled by global clock to ensure that current cells switch simultaneously (independent of decoder delays)
•
Make before break – Ensure uninterrupted current flow, so that tail current source remains active
•
Low swing driver – Drive differential pair with low swing to minimize coupling from control signals to output
•
Cascoded tail current source for high output impedance – Ensures that overall impedance at output nodes is code independent (necessary for good INL)
B. Murmann
EE315B - Chapter 4
43
Example Current Cell Implementation
[Barkin & Wooley, JSSC 4/2004]
B. Murmann
EE315B - Chapter 4
44
Constant Clock Load Latch Q
D MN1 INV1
INV2
QB
DB MN2 INV6
Capacitive load seen at CLK the same for all possible cases, H-L, L-H, H-H or L-L
MN3
INV3
INV7 CLKB
INV5
MN4
INV4
CLK Mercer, US patent ,7,023,255 4/4/2006
EE315B - Chapter 4
B. Murmann
45
High Performance DAC Examples (1) 100MHz 1GHz [Van den Bosch, JSSC 3/2001]
B. Murmann
EE315B - Chapter 4
46
High Performance DAC Examples (2)
[Schafferer, ISSCC 2004]
B. Murmann
EE315B - Chapter 4
47
High Performance DAC Examples (3)
[Schafferer, ISSCC 2004]
B. Murmann
EE315B - Chapter 4
48
High Performance DAC Examples (4)
[Lin, ISSCC 2009]
EE315B - Chapter 4
B. Murmann
49
Binary Weighted Charge Redistribution DAC CP (top plate parasitic)
+ 2N–1 C
8C
4C
2C
C
C VOUT
–
VRE F b1 (msb)
bN–3
bN–2
Vout =
•
bN–1
2B C B
2 C + Cp
bN (lsb)
B
⋅Vref ∑
bi
i i =1 2
Can redistribute charge onto OTA + feedback capacitor to mitigate gain error due to Cp
B. Murmann
EE315B - Chapter 4
50
Charge-based Pipeline DAC (1)
[Manganaro et al., "A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer," IEEE JSSC 11/2004]
B. Murmann
EE315B - Chapter 4
51
Charge-based Pipeline DAC (2)
(fclk=200MHz)
B. Murmann
EE315B - Chapter 4
52
Sampling Circuits
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
B. Murmann
EE315B - Chapter 5
1
Recap
•
How to build circuits that "sample"?
•
Ideal Dirac sampling is impractical – Need a switch that opens, closes and acquires signal within an infinitely small time
•
Practical solution – "Track and hold"
B. Murmann
EE315B - Chapter 5
2
Outline •
Elementary track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques – Clock bootstrapping – Bottom plate sampling
•
Settling and noise analysis in charge-redistribution track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
3
Ideal Track-and-Hold Circuit
B. Murmann
EE315B - Chapter 5
4
Signal Nomenclature time
Continuous Time Signal
T/H Signal ("Sampled Data Signal")
Clock
Discrete Time Signal
B. Murmann
EE315B - Chapter 5
5
Circuit with MOS Switch
“Pedestal Error”
B. Murmann
EE315B - Chapter 5
6
Nonidealities •
Finite acquisition time
•
Tracking nonlinearity
•
Signal dependent hold instant
•
Thermal noise
•
Clock jitter
•
Hold mode feedthrough and leakage
•
Charge injection and clock feedthrough
EE315B - Chapter 5
B. Murmann
7
Finite Acquisition Time •
Consider various input signal scenarios
1. Input is a sampled data signal, i.e. the output of another switched capacitor stage 2. Input is a slowly varying continuous time signal, e.g. the input of an oversampling ADC 3. Input is a rapidly varying continuous time signal, e.g. the input of a Nyquist or subsampling ADC
B. Murmann
EE315B - Chapter 5
8
Finite Acquisition Time – Case 1 • •
For simplicity, neglect finite rise time of the input signal Consider worst case – the output is required to settle from 0 to the full-scale voltage of the system (VFS) First order MOS switch model
τ = RC
(
⇒ Vout (t) = VFS 1 − e− t / τ
EE315B - Chapter 5
B. Murmann
) 9
Finite Acquisition Time – Case 1 − T Vout,err s = − VFSe 2
•
Ts /τ 2
= − VFSe−N
Typically think about settling error in terms of the number of settling time constants (N) required for ½ LSB settling in a B-bit system
− VFS e
N=
B. Murmann
−N
1 VFS ≤ 2 2B
Ts / 2 ≥ ln 2 ⋅ 2B τ
(
) EE315B - Chapter 5
B
N
6
>4.9
10
>7.6
14
>10.4
18
>13.2
10
Finite Acquisition Time – Case 2 & 3 •
Consider a sinusoidal input around “0”, and “0” also as the initial condition for Vout (for notational simplicity)
Vin (t) = A cos(ω t + φ ) Vout (t) = −
A cos(φ − θ)
−
e
t τ
2 2 1 +4ω τ 144 2444 3 initial transient
+
A cos(ω t + φ − θ) 14 +2444 ω 2 τ2 3 144 steady-state response
θ = atan(ωτ)
B. Murmann
EE315B - Chapter 5
11
Finite Acquisition Time – Case 2 & 3 •
At t=Ts/2, the error in the held signal consists of two parts
•
Residual error due to initial exponentially decaying initial transient term – In order to minimize this error, we need to chose N appropriately, as calculated for the step input scenario
•
Error due to magnitude attenuation and phase shift in the steady state term – This error depends only on the RC time constant and the input frequency; it cannot be reduced by extending the length of the track phase – How significant is the error due to the steady-state term?
B. Murmann
EE315B - Chapter 5
12
Finite Acquisition Time – Case 2 & 3 •
As an example, let’s compute the percent amplitude error for the N values derived previously (½ LSB, B-bit settling to a step) A A err =
B. Murmann
1 + ( ωτ )
2
−A = 1−
A
1 1 + ( ωτ )
2
1
= 1−
T /2 1 + 2πfin s N
2
1
= 1−
π f 1 + in N fs
B
N
Aerr (fin = fs/20)
Aerr (fin = fs/2)
6
4.9
0.052%
4.9%
10
7.6
0.021%
2.1%
14
10.4
0.011%
1.1%
18
13.2
0.007%
0.7%
EE315B - Chapter 5
2
13
Summary – Finite Acquisition Time •
Precise settling to an input step is accomplished within 5…13 RC time constants (depending on precision)
•
Precise tracking of a high-frequency continuous time input signal tends to impose more stringent requirements – Number to remember: ~1% attenuation error at Nyquist (fin=fs/2) for N ~10
•
In applications where attenuation is tolerable, the RC time constant requirements then tend to follow from the distortion specs – The larger the attenuation, the larger the instantaneous voltage drop across the (weakly nonlinear) MOSFET undesired harmonics – Let’s look at that next…
B. Murmann
EE315B - Chapter 5
14
Voltage Dependence of Switch ID(triode) = µCox
RON
dI D(triode) ≅ dVDS
RON =
•
V W VGS − Vt − DS VDS L 2
µCox
VDS → 0
−1
1
= µCox
W ( V − Vt ) L GS
1 W ( φ − Vin − Vt ) L
Two problems – RON is modulated by Vin (assuming e.g. φ=VDD=const.) – Transistor turn off is signal dependent, occurs when φ=Vin+Vt
B. Murmann
EE315B - Chapter 5
15
Track Mode Nonlinearity
[Razavi, Data Conversion System Design, p.16]
•
Output tracks well when input voltage is low – Gets distorted when voltage is high due to increase in RON
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EE315B - Chapter 5
16
Analysis ID ≅ K ( VGS − Vt ) VDS − C
K 2 VDS 2
dVout K 2 = K ( φ − Vout − Vt )( Vin − Vout ) − ( Vin − Vout ) dt 2
•
"All" we need to do is solve the above differential equation…
•
Can use Volterra Series analysis – General method that allows us to calculate the frequency domain response of nonlinear circuits with memory – See e.g. Stanford EE214
•
Luckily someone has already done this for us – See [Yu, TCAS II, 2/1999]
EE315B - Chapter 5
B. Murmann
17
Result HD3 =
Amplitude of third harmonic Amplitude of fundamental 2
2
fin π 1 A 1 A ≅ ⋅ ⋅ ωτ = 4 VGS − Vt 4 VGS − Vt fs N
•
VGS is the "quiescent point" value of the gate-source voltage; i.e. in the zero crossing of the sine input
•
For low distortion – Make amplitude smaller than VGS-Vt • Low swing bad for SNR
– Make 1/τ much larger than ω (input frequency) • Big switch may cost lots of power to drive, comes with large parasitic capacitances B. Murmann
EE315B - Chapter 5
18
Numerical Example •
Parameters – VDD = VCK = 1.8V – Signal is centered about VDD/2 = 0.9V – VGS-Vt = 1.8V-0.9V-0.45V = 0.45V – A = 0.2V – N = 0.5Ts/τ = 10 – fin = fs/2 2
1 0.2 1 π HD3 ≅ ⋅ = −42dB 4 0.45 2 10
•
Not all that great…
EE315B - Chapter 5
B. Murmann
19
Signal Dependent Sampling Instant (1) (φ)
[Razavi, Data Conversion System Design, p.17]
Tf
•
Must make fall time of sampling clock (Tf) much faster than maximum dVin/dt
B. Murmann
EE315B - Chapter 5
20
Signal Dependent Sampling Instant (2) •
Distortion analysis result (see Yu, TCAS II, 2/1999] HD3 =
≅
•
Amplitude of third harmonic Amplitude of fundamental 3 A ω Tf 8 VCK
2
Example: VCK = 1.8V, A = 0.5V, Tf = 100ps, ω = 2π100MHz 2
HD3 ≅
3 0.5 ⋅ 2π100 ⋅ 106 ⋅ 100 ⋅ 10−12 = −79dB 8 1.8
EE315B - Chapter 5
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21
Hold Mode Feedthrough [Razavi, Data Conversion System Design, p.17]
CDS
•
Want to make Rout as small as possible
•
Consider using a “T-switch” when hold-mode feedthrough is a problem (for low-speed applications)
•
Consider using half circuit cross coupling for high-speed applications
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EE315B - Chapter 5
22
Hold Mode Leakage Example:
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EE315B - Chapter 5
23
Gate Leakage Data
A. Annema, et al., “Analog circuits in ultra-deep-submicron CMOS,” IEEE J. Solid-State Circuits, pp. 132-143, Jan. 2005.
• •
In 65nm CMOS, gate capacitance droop rate is ~1V/µs (!) Issue is solved with high-k dielectrics in post-65nm technologies
B. Murmann
EE315B - Chapter 5
24
Thermal Noise (1)
•
Questions – What is the noise variance of the Vout samples in hold mode? – What is the spectrum of the discrete time sequence representing these samples? • Nearly white, provided that the number of settling time constants (N) is large (see EE315A for a derivation) EE315B - Chapter 5
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25
Thermal Noise (2) •
Sample values Vout(n) correspond to instantaneous values of the track mode noise process
•
From Parseval's theorem, we know that the time domain power (or variance) of this process is equal to its power spectral density integrated over all frequencies –
Further, given that the process is ergodic, this number must also be equal to the "ensemble" variance, i.e. the variance of a sample taken at a particular time
2 v out 1 = 4kTR ⋅ 1 + sRC ∆f
var [ Vout (n)] =
B. Murmann
2 v out,tot
∞
2
2
1 kT = ∫ 4kTR ⋅ df = 1 + j2πf ⋅ RC C 0
EE315B - Chapter 5
26
Alternative Derivation
•
The equipartition theorem says that each “degree of freedom" (typically a quadratic energy variable) of a system in thermal equilibrium holds an average energy of kT/2
•
In our system, the degree of freedom is the energy stored on the capacitor
1 1 Cv out 2 = kT 2 2 v out 2 =
kT C
EE315B - Chapter 5
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27
Implications of kT/C Noise •
Example: suppose we make the kT/C noise equal to the quantization noise of a B-bit ADC kT ∆ 2 = , C 12
• •
∆=
VFS 2B
⇒
2B C = 12kT V FS
2
For a given B, both C and R (via N on slide 19) are fully determined Example numbers for VFS=1V and fs=100MHz: B 8 10 12 14 16 18
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C [pF] 0.003 0.052 0.834 13.3 213 3,416
EE315B - Chapter 5
R [Ω] 246,057 12,582 665 36 1.99 0.11
28
Commercial Example
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EE315B - Chapter 5
29
How to Estimate Thermal Noise in the Lab? •
One option is to look at the measured SNR and back-calculate the thermal component by subtraction of quantization noise and DNL noise
•
Another (potentially better) option is to take a code histogram with “grounded input”
S. Ruscak and L. Singer, “Using Histogram Techniques to Measure A/D Converter Noise” http://www.analog.com/library/analogDialogue/ archives/29-2/cnvtrnoise.html
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EE315B - Chapter 5
30
Sampling Jitter •
In any sampling circuit, electronic noise causes random timing variations in the actual sampling clock edge – Adds "noise" to samples, especially if dVin/dt is large
∆Vin = Change in V in during ∆t
∆Vin ≅
dVin ⋅ ∆t dt
∆t = Sampling jitter
•
Analysis – Consider sine wave input signal – Assume ∆t is random with zero mean and standard deviation σt
EE315B - Chapter 5
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31
Analysis
E
{ } ∆Vin2
dV 2 dV 2 2 2 in in ≅ E ⋅ ∆t = E dt ⋅ E ∆t dt
{ }
2 d 1 2 ≅ E A cos [ 2π ⋅ fin ⋅ t ] ⋅ σ2t ≅ ( 2π ⋅ A ⋅ fin ) ⋅ σ2t 2 dt
௧௧ =
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1 ଶ 2 1 ଶ ଶ ௦ ⋅ ௧ଶ 2
EE315B - Chapter 5
=
1 ⋅ ௧ଶ
ଶ ௦
32
Result 1.E+11 1.E+10
fin [Hz]
1.E+09 σt = 0.1ps 1.E+08 σt = 1ps 1.E+07
σt = 10ps
1.E+06 1.E+05 10
20
30
40
50
60
70
80
90
100
110
120
SNR [dB] SNR aperture jitter [dB] B. Murmann
EE315B - Chapter 5
33
ADC Performance Survey (ISSCC & VLSI 97-12) Data: http://www.stanford.edu/~murmann/adcsurvey.html
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EE315B - Chapter 5
34
Why is it Hard to Achieve Low Jitter? • Inverters have little to no supply rejection • Example: – 1V supply, 20ps rise time – 100mV noise on the supply corresponds to about 2ps of jitter
Noisy VDD
Jitter Free Clock
Jittered Output Clock
• In addition, there is thermal amplitude noise (kT/C) that also translates into jitter
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EE315B - Chapter 5
35
How Well Can We Do? •
In today’s optimized designs, jitter numbers as low as 50 fsrms have been achieved, see e.g. Ali, JSSC 8/2006 – However, several hundred psrms are more common, especially in noisy SoC environments
•
Differential signaling can help (particularly at the chip boundary), but comes with diminishing returns due to reduced amplitude and signal slope (relative to inverters)
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EE315B - Chapter 5
36
Significance of Jitter
•
In light of the above reasoning, sampling jitter has become one of the main showstoppers for further improvements in the ADC speed-resolution product
•
Example – fin = 10GHz, σt = 300ps SNRjitter = 34.5dB (ouch!)
•
What saves us in many application is that the signal is not a sinusoid, but instead spread in some way across frequency
•
Proper analysis for applications that push the boundaries must therefore take the signal properties into account – Reference: Da Dalt, TCAS1, 9/2002
EE315B - Chapter 5
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37
Generalized Calculation •
Da Dalt showed that in general, the jitter SNR can be computed using the curvature of the signal’s autocorrelation function
௧௧ =
•
1 ௧ ⋅ ௧ଶ
௧ = −
′′ 0 0
Side note – In this result, the signal is assumed to be stationary – An extension for cyclostationary signals was provided by ElChammas, TCAS1, May 2009 • Useful for systems with simple signal constellations, such as NRZ
B. Murmann
EE315B - Chapter 5
38
Intuition
Gradual decay in autocorrelation Slow signal
Sharp decay in autocorrelation
Fast signal
EE315B - Chapter 5
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39
Example: High-Speed Link ߪ௧ଶ “White” Info Source
ݔ ܴ௫ ߬
TX
Channel h(t)
RX
ݕ ܴ௬ ߬
•
Rx is the autocorrelation function of the input signal (assumed to be white and stationary in this example)
•
Ry is the autocorrelation function of the signal at the sampler
ܴ௬ ߬ = ܴ௫ ߬ ∗ ℎ ∗ ݐℎ −ݐ ܴ௬ ߬ = ߜ ߬ ߪ௫ଶ ∗ ℎ ∗ ݐℎ −ߪ = ݐ௫ଶ ⋅ [ℎ ∗ ݐℎ −] ݐ ߬ ݓ B. Murmann
EE315B - Chapter 5
40
Example Chanel Frequency Response
Chanel Impulse Response
0 5
-10
4
-30
h(t) [V/ns]
S21 [dB]
-20
-40
fs/2
-50
3 2
-60 1 -70 -80 0
5
10 f [GHz]
15
20
0 4.4
4.6
4.8 Time [ns]
EE315B - Chapter 5
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5
5.2 41
Example Convolved Impulse Response
Second Derivative
x 10 0.12
-5
1 0.5
0.1
0 w''(τ) [1/ps2]
w(τ)
0.08 0.06 0.04
-0.5 -1 -1.5 -2
0.02 0 -1
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-2.5 -0.5
0 τ [ns]
0.5
1
-3 -0.5
EE315B - Chapter 5
0 τ [ns]
0.5 42
Example ௧ = −
ᇱᇱ 0 1 2.8 ⋅ 10ିହ 1 = = 2.3 ⋅ 10ିସ ଶ ଶ 0.12
0 1 = 46.8 ௧ ⋅ 300
௧௧ = 20 log •
Another way to think about this is to compute the sinusoid frequency that causes the same jitter noise ௦, =
•
(Better!)
1 = 2.4 2 ௧
Bottom line: the fact that the signal is wideband and filtered by the channel helps, but the jitter spec will still be “non-trivial”
B. Murmann
EE315B - Chapter 5
43
How to Measure/Quantify the Sampling Jitter of an ADC in the Lab? •
Use sinusoids as a test signal
•
Method 1: Leverage the known proportionalities and extract jitter estimate using an amplitude and frequency sweep – RMS jitter is noise proportional to input frequency – RMS is noise proportional to input amplitude – This works well when jitter is the dominant issue, and not masked by other nonidealities (like thermal noise)
•
Method 2: Leverage the fact that jitter causes cyclostationary noise – Jitter causes almost no noise near peaks of sinusoid, but lots of noise near zero crossing – “Noise beat” at twice the signal frequency
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EE315B - Chapter 5
44
Jitter Noise Beat [Aaron Buchwald] Can back calculate jitter noise by comparing variance at zero crossing with variance near peak (which is set by thermal and quantization noise)
B. Murmann
EE315B - Chapter 5
45
Jitter Estimation Based on Spectrum •
Reference – D.M. Hummels, W. Ahmed, W., F.H. Irons, "Measurement of random sample time jitter for ADCs," Proc. ISCAS, pp.708-711, May 1995. Spectrum of squared sequence contains a tone proportional to jitter
After removal of harmonics:
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EE315B - Chapter 5
46
Matlab Code % Jitter estimation technique proposed by Hummels, ISCAS 1995 % x is a vector that contains an integer number of cycles of a sampled sine wave function [sigma_jitter_est, sigma_noise_est, fsin] = estimate_jitter(x, show_plot) % take fft, remove DC, signal and harmonics N = length(x); s = fft(x); [sigamp, sigbin]=max(abs(s)); A_est = sigamp/N*2; cycles = sigbin-1; fsin = cycles/N; harmbins = 1 + abs([2:8]*cycles - N*round([2:8]*cycles/N)); sn=s; sn(1)=eps; sn(sigbin)=eps; sn(N+2-sigbin)=eps; sn(harmbins) =eps; sn(N+2-harmbins)=eps; % inverse fft, compute jitter and noise estimates xinv = ifft(sn, 'symmetric'); s_inv = abs(fft(xinv.^2)); jitterbin = 1 + abs(2*cycles - N*round(2*cycles/N)); sigma_jitter_est = sqrt(2*2*s_inv(jitterbin)/N/(2*pi*fsin)^2/A_est^2); sigma_noise_est = sqrt(s_inv(1)/N-2*s_inv(jitterbin)/N);
B. Murmann
EE315B - Chapter 5
47
Charge Injection and Clock Feedthrough
“Pedestal Error”
•
Analyze two extreme cases – Very large Tf (“slow gating”) – Very small Tf (“fast gating”)
B. Murmann
EE315B - Chapter 5
48
Slow Gating φ φH VIN + V T V IN t HOLD
φL VO VIN
ýV ∆V t toff
•
All channel charge has disappeared by toff without introducing error; it is absorbed by the input source EE315B - Chapter 5
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49
Slow Gating Model for t > toff Vout = Vin − ∆Vout Vout = Vin −
ε=−
Col ( Vin + Vt − φL ) = Vin (1 + ε ) + Vos Col + C
Col Col + C
Vos = −
Gain Error
•
Col ( Vt − φL ) Col + C
Offset Error
Example: C=1pF, φL=0V, Vt=0.45V, W=20µm, Col’=0.1fF/µm, Col=2fF ε = −0.2%
B. Murmann
Vos = −0.9mV
EE315B - Chapter 5
50
Fast Gating φ
φ
•
Channel charge cannot change instantaneously
•
Resulting surface potential decays via charge flow to source and drain
•
Charge divides between source and drain depending on impedances loading these nodes
φH VIN + VT Surface Potential
t
Qch ΨS
φL
t < to
VO V IN
ΨS
ýV ∆V
t > to
1
(1-α)Q chch 2Q
B. Murmann
t Ε
Ε
1
αQ ch 2 Qch
EE315B - Chapter 5
51
Charge Split Ratio Data
Tf RonC2
G. Wegmann et al., "Charge injection in analog MOS switches," IEEE J. SolidState Circuits, pp. 1091-1097, June 1987. Y. Ding and R. Harjani, "A universal analytic charge injection model," Proc. ISCAS, pp. 144-147, May 2000. B. Murmann
EE315B - Chapter 5
52
Interpretation •
RonC2 and Tf are usually comparable, or at least not more than an order of magnitude apart – This brings us into the range of 0.1…1 on the chart by Wegmann
•
This means that the charge split will in practice have some dependence on the impedances seen on the two sides of the transistor
•
Remember: Slightly more charge will go to the side with lower impedance
EE315B - Chapter 5
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53
Fast Gating Model for t > toff Vout = Vin − ∆Vout = Vin (1 + ε ) + Vos Vout = Vin −
Col 1Q ( φH − φL ) + ch Col + C 2 C
Assuming 50/50 charge split
Qch = − WLCox [ φH − Vin − Vt ] ε=
•
1 WLCox 2 C
Vos = −
Col 1 WLCox ( φH − φL ) − ( φH − Vt ) Col + C 2 C
Example: C=1pF, φH-φL=1.8V, Vt=0.45V, W=20µm, LCox=2fF/µm Col’=0.1fF/µm, Col=2fF ε = +2%
B. Murmann
Vos = −30.6mV EE315B - Chapter 5
54
Transition Fast/Slow Gating Fast gating
Slow gating
Fast gating
| ε|
Slow gating
|Vos|
TtFf
TtfF
•
|ε| and |Vos| decrease as the fall time of φ (Tf) increases and approach the limit case of slow gating
•
Unfortunately, high-speed switched capacitor circuits tend to operate in fast gating regime
EE315B - Chapter 5
B. Murmann
55
Impact of Technology Scaling
∆V ≅
1 Qch 2 C
1
R≅ µCox
•
T 1 = s = N ⋅ RC 2fs 2
W ( V − Vt ) L GS
=
L2 µQch
L2 ∆V ≅N fs µ
Charge injection error to speed ratio benefits from shorter channels and increases in mobility (e.g. due to strain)
B. Murmann
EE315B - Chapter 5
56
Outline •
Elementary track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques – Clock bootstrapping – Bottom plate sampling
•
Settling and noise analysis in charge-redistribution track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
57
Improvements •
Charge cancelation – Try to cancel channel charge by injecting a charge packet with opposite sign
•
Differential sampling – Use a differential circuit to suppress offset
•
CMOS switch – Try to balance the nonidealities of NMOS device with a parallel PMOS
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EE315B - Chapter 5
58
Charge Cancellation
∆Q1 = 0.5Qch1 + Qol1
S
L =L W =0.5W 1
∆Q2 ≅ Qch2 + 2Qol2 ≅ 0.5Qch1 + Qol1
2
∆Q1 − ∆Q2 ≅ 0
1
[Eichenberger and Guggenbűhl, JSSC 8/89]
•
Cancellation is never perfect, since channel charge of M1 will not exactly split 50/50 – E.g. if Rs is very small, most of M1’s channel charge will flow toward the input voltage source
•
Not a precision technique, just an attempt to do a partial clean-up
EE315B - Chapter 5
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59
Differential Sampling (1) φ VO1
+ VI1
C CH
VIC =
– VO2
+ VI2
VID = VI1 − VI2
C CH
VI1 + VI2 2
VOD = VO1 − VO2 VOC =
VO1 + VO2 2
VO1 = (1 + ε1 ) VI1 + VOS1 VO2 = (1 + ε2 ) VI2 + VOS2
–
ε +ε ε +ε VOD = 1 + 1 2 VID + ( ε1 − ε2 ) VIC + ( VOS1 − VOS2 ) ≅ 1 + 1 2 VID 2 2 + VOS2 ε1 + ε2 + VOS2 V V ε −ε ε +ε VOC = 1 2 VID + 1 + 1 2 VIC + OS1 VIC + OS1 ≅ 1+ 2 2 2 2 4 B. Murmann
EE315B - Chapter 5
60
Differential Sampling (2) •
Assuming good matching between the two half circuits, we have – Small residual offset in VOD – Good rejection of coupling noise, supply noise, … – Small common-mode to differential-mode gain
•
Unfortunately, VOD has essentially same gain error as the basic single ended half circuit
•
This also means that there will be nonlinear terms – Out simplistic analysis assumed that the channel charge is linearly related to Vin – This is true only to first order (consider e.g. backgate effect) • Expect to see nonlinear distortion along with gain error
EE315B - Chapter 5
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61
CMOS Switch φ VO
+ VIN
(
Qchp ≅ WpLpCox VIN − φL − Vtp
CH
φ
–
•
)
Assuming fast gating, 50/50 charge split and WnLn = WpLp 1 1 Qchn + Qchp C 2 ∆Vo ≅ 2 = ox C C
•
Qchn ≅ − WnLnCox ( φH − VIN − Vtn )
V − Vtp φ −φ VIN − H L + tn 2 2
Charges fully cancel e.g. for VIN = (φH-φL)/2 = VDD/2, and Vtn=|Vtp|, but there is still signal dependent residual injection
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EE315B - Chapter 5
62
On Resistance of CMOS Switch •
At least in principle, adding a PMOS can also help with the problem of signal dependent Ron in track mode – For increasing VIN, NMOS resistance goes up, PMOS resistance goes down φ VO
+ VIN
CCH
φ
–
R≅
1
1
W W µnCox ( VGSn − Vtn ) µpCox VGSp − Vtp L n L p
(
)
EE315B - Chapter 5
B. Murmann
63
Analysis R≅
1
1
W W µnCox ( VGSn − Vtn ) µpCox VGSp − Vtp L n L p
(
R≅
1 W W W W µnCox ( VDD − Vtn ) − µnCox − µpCox v in − µpCox Vtp L L L p L n n p
R≅
1 W µnCox VDD − Vtn − Vtp L n
(
• •
)
)
W W if µn = µp L n L p
Independent of Vin too good to be true! Missing factors – Backgate effect – Short channel effects
B. Murmann
EE315B - Chapter 5
64
Real CMOS Switch 100 NMOS PMOS NMOS || PMOS
R [Ω]
80 60 40 20 0 0
0.5
1 Vin [V]
1.5
•
Design – Size P/N ratio to minimize change in R over input range – Size P and N simultaneously to meet distortion specs
•
PMOS brings limited benefit unless the input signal range is large or centered near VDD
B. Murmann
EE315B - Chapter 5
65
Outline •
Elementary track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques – Clock bootstrapping – Bottom plate sampling
•
Settling and noise analysis in charge-redistribution track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
66
Clock Bootstrapping
+ VDD -
+ VDD -
Cboot
Cboot
VGS=VDD=const.
Vin A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999.
•
Phase 1 – Cboot is precharged to VDD – Sampling switch is off
•
Phase 2 – Sampling switch is on with VGS=VDD=const. – To first order, both Ron and channel charge are signal independent
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EE315B - Chapter 5
67
Waveforms
A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999.
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EE315B - Chapter 5
68
Circuit Implementation
Switch
A. Abo et al., “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-toDigital Converter,” IEEE J. Solid-State Circuits, pp. 599, May 1999
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EE315B - Chapter 5
69
Limitations •
Efficacy of bootstrap circuit is reduced by – Backgate effect – Parasitic capacitance between at top plate of C3
R≅
B. Murmann
Cpar
1 Cpar Cboot W µnCox VDD − Vin − Vtn [ Vin ] 1 424 3 Cboot + Cpar L n Cboot + Cpar Backgate effect
EE315B - Chapter 5
70
Alternative Implementation
Dessouky and Kaiser, "Input switch configuration suitable for rail-to-rail operation of switched opamp circuits," Electronics Letters, Jan. 1999.
•
Less complex, but Cpar tends to be larger due to two parasitic well capacitances EE315B - Chapter 5
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71
Performance of Bootstrapped Samplers •
Bootstrapped “top plate” sampling (as opposed to “bottom plate” – more later) tends to work very well up to ~10bit resolution
•
Example
[Louwsma, JSSC 4/2008]
B. Murmann
EE315B - Chapter 5
72
High-Speed Example without Bootstrap
[Choi and Abidi, JSSC 12/2001]
•
For lower resolution applications, it can be OK to drop the bootstrap circuit
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EE315B - Chapter 5
73
Bottom Plate Sampling •
What if we want to do much better, e.g. 16 bits?
•
Basic idea – Sample signal at the "grounded" side of the capacitor to achieve signal independent sampling
•
References – D. G. Haigh and B. Singh, “A switching scheme for SC filters which reduces the effect of parasitic capacitances associated with switch control terminals,” in Proc. IEEE Int. Symp. Circuits and Systems, 1983, pp. 586–589. – K.-L. Lee and R. G. Meyer, “Low-Distortion SwitchedCapacitor Filter Design Techniques,” IEEE J. Solid-State Circuits, pp. 1103-1113, Dec. 1985.
•
First look at single ended half circuit for simplicity
B. Murmann
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74
Bottom Plate Sampling Analysis (1) •
Turn M2 off "slightly" before M1 – Typically a few hundred ps delay between falling edges of φe and φ
•
During turn off, M2 injects charge ∆Q2 ≅
∆Q2
1 WLCox ( φH − Vtn ) 2
•
To first order, the charge injected by M2 is signal independent
•
Voltage across C VC = Vin +
B. Murmann
∆Q 2 C
EE315B - Chapter 5
75
Bottom Plate Sampling Analysis (2)
∆Q1 ≅
B. Murmann
•
Next, turn off M1
•
M1 will inject signal dependent charge onto the series combination of C and the parasitic capacitance at its bottom plate (Cpar)
•
Looks like, this is not much different from the conventional top-plate sampling? – But wait…
1 WLCox ( φH − Vin − Vtn ) 2
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76
Bottom Plate Sampling Analysis (3)
Q X = −CVin − ∆Q2 Charge injected by M2 (Signal independent)
•
Interesting observation – Even though M1 injects some charge, the total charge at node X cannot change!
•
Idea – Process total charge at node X instead of looking at voltage across C
•
The charge can be processed in two ways – Open-loop – Closed-loop (charge redistribution)
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77
Open-Loop Charge Processing Q X = −CVin − ∆Q2 φ1 Vin
φ2
VX = M1
QX ∆Q2 C = − Vin − C + Cp C + Cp C + Cp
C
(no term due to signal dependent charge!)
Vx
φ1e Cpar
φ1
M2
φ1e
φ2
•
Remaining drawback – Cpar (and buffer input capacitance) is usually weakly nonlinear and will introduce some harmonic distortion
B. Murmann
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78
Closed-Loop Charge Processing
•
Amplifier forces voltage at node X to “zero” – Means that charge at node X must redistribute onto feedback capacitor Cf EE315B - Chapter 5
B. Murmann
79
Charge Conservation Analysis Charge at node X during φ1:
Q X1 = −CVin − ∆Q2 + 0 ⋅ Cf
Charge at node X during φ2:
Q X2 = −Cf Vout
Q X1 = Q x2
Charge Conservation:
−CVin − ∆Q2 = −Cf Vout ∴ Vout =
•
∆Q2 C Vin + Cf Cf
Offset term due to signal independent injection from M2 can be easily removed using a differential architecture
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80
Clock Generation
[A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999]
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EE315B - Chapter 5
81
Fully Differential Circuit
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82
Analysis (1)
(
Q1m = −CVinp + ∆Q
Q2m = CVxm − Cf Vop − Vxm
Q1p = −CVinm + ∆Q
Q2p = CVxp − Cf Vom − Vxp
1)
Q1m = Q2m
2)
Q1p = Q2p
(
Vxm = Vxp
Vop + Vom 2
)
)
= Voc
EE315B - Chapter 5
B. Murmann
83
Analysis (2) •
Subtracting 1) and 2) yields Vop − Vom =
•
C ( Vinp − Vinm ) Cf
Adding 1) and 2) yields
(
)
(
)
(
−C Vinp + Vinm + 2∆Q = ( C + Cf ) Vxp + Vxm − Cf Vop + Vop Vxc =
•
)
Cf ∆Q C + V oc − V ic C + Cf C + C f C + Cf
Variations in Vic show up as common mode variations at the amplifier input – Need amplifier with good CMRR
B. Murmann
EE315B - Chapter 5
84
T/H with Common Mode Cancellation
S.H. Lewis & P.R. Gray, "A Pipelined 5 MSample/s 9-bit Analog-to-Digital Converter", IEEE J. Solid-State Circuits, pp. 954-961, Dec. 1987
•
Shorting switch allows to re-distribute only differential charge on sampling capacitors
•
Common mode at OPAMP input becomes independent of common mode at circuit input terminals (IN+/IN-)
•
Original idea: Yen & Gray, JSSC 12/1982 EE315B - Chapter 5
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85
Analysis (1) During 1
During 2 C
C V
C
C
V
V V
V
V
V C
V
C V C
C
•
Charge conservation at Vip,Vim and Vfloat
( Vip + Vim ) ⋅ C = ( Vfloat − Vxp ) ⋅ C + ( Vfloat − Vxm ) ⋅ C Vic = Vfloat − Vxc Vfloat = Vic + Vxc
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86
Analysis (2) •
Common mode charge conservation at amplifier inputs − Vic ⋅ C − Voc ⋅ Cf = − ( Vfloat − Vxc ) ⋅ C − ( Voc − Vxc ) ⋅ Cf − Vic ⋅ C = − ([ Vic + Vxc ] − Vxc ) ⋅ C + Vxc ⋅ Cf 0 = Vxc
•
Amplifier input common mode (Vxc) is independent of – Input common mode (Vic) – Output common mode (Voc)
B. Murmann
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Flip-Around T/H
[W. Yang et al., "A 3-V 340-mW 14-b 75-MSample/s CMOS ADC With 85-dB SFDR at Nyquist Input", IEEE J. Solid-State Circuits, pp. 1931-1936, Dec. 2001]
•
Sampling caps are "flipped around" OTA and used as feedback capacitors during φ2
•
Main advantage: improved feedback factor (lower noise, higher speed)
•
Main disadvantage: OTA is subjected to input common mode variations
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Sampling Network Design Considerations φ1-
M1-
φ1+ φ1
M1
•
M1- switches only needed to set common mode; M1 is actual sampling switch – Make M1 larger than M1-
•
Ideally turn off M1- before M1 – In practice, usually OK to turn off simultaneously
•
In track mode, the total path resistance is R(M3) plus bottom plate switch resistance – Since R(M3) is signal dependent, make its resistance small compared to that of bottom plate network
φ1+
φ1-
M1[Lin, Kim and Gray, JSSC 4/1991]
φ1φ1 φ1+ φ2 B. Murmann
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Schematic Entry and Layout of M1
•
Use antiparallel devices to implement M1 – Needed in simulation to guarantee circuit symmetry • E.g. BSIM model is not necessarily perfectly symmetric with respect to drain/source!
– Needed in layout to ensure symmetry in presence of drain/source asymmetry due to processing artifacts B. Murmann
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What Ultimately Limits Linearity? •
Track mode nonlinearity due to R=f(Vin) – Mitigate using clock bootstrapping and proper partitioning of total path resistance – Eventually, bootstrapping falls apart high frequencies, due to parasitics capacitances inside the bootstrap circuit
•
Mismatch in half-circuit charge injection due to R=f(Vin) – Bottom plate switches in the two half circuits see input dependent impedance; this creates input dependent charge injection mismatch – Bootstrapping helps; ultimately limited by backgate effect – This effect is often fairly independent of frequency (somewhat dependent on realization of top plate switch)
•
In high performance designs, can achieve ~80-100dB linearity up to a few hundreds of MHz EE315B - Chapter 5
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91
Capacitors Metal-Insulator-Metal (MIM)
Vertical Parallel Plate (VPP)
[Ng, Trans. Electron Dev., 7/2005]
[Aparicio, JSSC 3/2002]
•
Typically 1-2 fF/µm2 (10-20 fF/µm2 for advanced structures) – For 1 fF/µm2, a 10 pF capacitor occupies ~100µm x 100µm
•
Both MIM and VPP capacitors have good electrical properties – Mostly worry about parasitic caps – Series and parallel resistances are often not a concern
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Plate Parasitics Ideal Capacitor Symbol
Typical Integrated Circuit Capacitor
•
Node n1 is usually the "physical" top plate of the capacitor – Makes nomenclature very confusing, since this plate is typically used as the "electrical" bottom plate in a sampling circuit (in the context of "bottom plate sampling")
•
Typical values for a MIM capacitor – α=1%, β=10%
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93
Proper Connection of Capacitors
•
“Fat plate” is oriented away from virtual ground nodes to avoid reduction of feedback factor and reduce potential noise coupling
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94
Outline •
Elementary track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques – Clock bootstrapping – Bottom plate sampling
•
Settling and noise analysis in charge-redistribution track-and-hold circuit
•
Noise simulation example
B. Murmann
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95
Settling and Noise Analysis
Cf
φ2
φ1 Cs
Gm CL
B. Murmann
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96
First Order Amplifier Model
Piecewise linear half-circuit x
xd
o
od
2 x
n
gm v x for io = ID ⋅ sign ( v x )
o
o
gm v x < ID else
EE315B - Chapter 5
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97
Linear Settling (Small Input Step)
0
→Vofinal
t=0
-Vistep
(
v o (t) = Vofinal 1 − e − t / τ (ignoring feedforward zero)
•
Important parameter: Return factor or "feedback factor" β β=
B. Murmann
Cf Cf + Cs + Cx
EE315B - Chapter 5
98
)
Waveform Detail Static Error ε0
Dynamic Error εd(t) 1
V V o/V /V out o,ideal out,ideal
0.8
0.6
0.4
0.2
0 0
2
4
6
8
10
t/τ EE315B - Chapter 5
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99
Static Settling Error •
Ideal output voltage for t→∞ Vofinal,ideal = Vistep ⋅
•
Actual output voltage (from detailed analysis) Vofinal = Vistep ⋅
•
Cs T0 ⋅ Cf 1 + T0
T0 = β ⋅ gmro = β ⋅ avo
Define static settling error ε0 =
•
Cs Cf
Vofinal − Vofinal,ideal Vofinal,ideal
T −1 1 1 1 T + = =− ≅− 1 1+ T T
Example: T0=1000 0.1% static settling error
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Dynamic Settling Error
(
)
−t / τ − Vofinal v o (t) − Vofinal Vofinal 1 − e εdynamic (t) = = = −e − t / τ Vofinal Vofinal
N=
ts = − ln ( εd ) τ
εdynamic
N
1%
4.6
0.1%
6.9
0.01%
9.2
EE315B - Chapter 5
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101
Time Constant
β=
Cf C f + Cs + C x
R=
1 β gm
CLtot = CL + (1 − β ) Cf
τ=
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1 CLtot ⋅ β gm
EE315B - Chapter 5
102
Transconductor Current 0
→Vofinal
t=0
-Vistep
(
v o (t) = Vofinal 1 − e − t / τ
•
During linear settling, the current delivered by the transconductor is io ≅ −CLtot
•
dv o (t) V = −CLtot ofinal e− t / τ dt τ
Peak current occurs at t=0 io max = CLtot
Vofinal τ
EE315B - Chapter 5
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103
Slewing •
)
The amplifier can deliver a maximum current of ID – If |io|max > ID, slewing occurs io max = CLtot
CLeff
Vofinal >I 1 CLtot D ⋅ β gm
Vofinal > ID τ
⇒
gm 1 > βVofinal ID
•
Example: β=0.5, Vofinal=0.5V gm/ID > 4 S/A will result in slewing
•
Very hard to avoid slewing, unless − We are willing to bias at very low gm/ID (power inefficient) − Feedback factor is small (large closed-loop gain, CS/Cf) − Output voltage swing is small
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Output Waveform with Initial Slewing
(
v o (t) = ∆Voslew + ∆Volin 1 − e −(t −∆tslew )/ τ
v o (t) =
•
)
ID t = SR ⋅ t CLtot
Continuous derivative in the transition slewinglinear requires ∆Volin ID = τ CLtot
∆Volin =
τ ⋅ ID CLtot
EE315B - Chapter 5
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105
Dynamic Error with Slewing ∆t slew = ( Vofinal − ∆Volin ) ⋅
∆Voslew = Vofinal − ∆Volin
•
CLtot ID
Using the above result, we can now calculate the dynamic error during the final linear settling portion For t > ∆t slew :
(
− t −∆t slew ) / τ v o (t) = ∆Voslew + ∆Volin 1 − e (
(
)
)
− ( t −∆t slew ) / τ − Vofinal v o (t) − Vfinal ∆Voslew + ∆Volin 1 − e εd (t) = = Vfinal Vofinal
εd (t) = −
B. Murmann
∆Volin − ( t −∆t slew ) / τ e Vofinal
EE315B - Chapter 5
106
Noise Analysis
Cf
φ2
φ1 Cs
Gm CL
Noise due to switches
Noise due to amplifier and switches
EE315B - Chapter 5
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107
Tracking Phase (φ1)
C
•
Variable of interest is total integrated "noise charge" at node X, qx2
•
Cumbersome to compute using standard analysis – Find transfer function from each noise source (3 resistors) to qx – Integrate magnitude squared expressions from zero to infinity and add
•
Much easier – Use equipartition theorem
C V
X
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108
Tracking Phase Noise Charge •
Energy stored at node X is 1 q2x 1 q2x = 2 Ceff 2 Cs + Cf
C
•
C V
Apply equipartition theorem 1 q2x 1 = kT 2 Cs + C f 2
X
q2x = kT ( Cs + Cf )
•
Note that any additional parasitic capacitance at node X will increase the sampled noise charge!
EE315B - Chapter 5
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109
Redistribution Phase Noise 4kTRon ∆f α>1 excess noise factor
1 R≅ βGm 4kTRon1∆f
•
α
4kTγ ∆f Gm
In a proper design, Ron1 and Ron2 will be much smaller than 1/βGm, else the switches would significantly affect the dynamics, which would be very wasteful – It is much easier to design switches with low on-resistance than an amplifier with very large Gm
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Output Referred Noise Comparison 2
•
Ron1 noise referred to vo
C 2 N1 = 4kTRon1∆f ⋅ s ⋅ H( jω) Cf
•
Ron2 noise referred to vo
N2 = 4kTRon2 ∆f ⋅ H( jω)
Amplifier noise referred to vo
Na = α
2
2
•
C 4kTγ 2 ∆f ⋅ 1 + s ⋅ H( jω) Gm Cf
2
Cs 1 + Cf Na αγ = >> 1 N1 GmRon1 C 2 s Cf
•
2
Na αγ Cs = 1+ >> 1 N2 GmRon2 Cf
Amplifier noise dominates over noise due to Ron1, Ron2 EE315B - Chapter 5
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111
Total Integrated Amplifier Noise
1 βGm
R≅
α ⋅ 4kTγGm ⋅ ∆f v o2 1 1 = α ⋅ 4kTγ ⋅R ∆f βR jω CLtot v o2
B. Murmann
2
∞
1 R = ∫ α ⋅ 4kTγ ⋅ ∆f ⋅ βR 1 + jω RCLtot 0 EE315B - Chapter 5
2
df = αγ
1 kT β CLtot 112
Adding up the Noise Contributions φ2
φ1 q2x = kT ( Cs + Cf )
2 v o,1 =
Cs + C f kT = C2 C2f f q2x
kT Cs = 1 + C f Cf
2 v o,tot =
2 v o,2 ≅ αγ
1 kT β CLtot
kT Cs 1 kT 1 + + αγ Cf Cf β CLtot
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113
Noise in Differential Circuits •
In differential circuits, the noise power is doubled (because there are two half circuits contributing to the noise)
•
But, the signal power increases by 4x – Looks like a 3dB win? DRsingle
Vˆ 2 ∝ o kT C
DRdiff
2Vˆ ) ( ∝ o
2
kT C
2
=2
Vˆ o2 kT C
•
Yes, there’s a 3dB win in DR, but it comes at twice the power dissipation (due to two half circuits)
•
Can get the same DR/power in a single ended circuit by doubling all cap sizes and gm
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Outline •
Elementary track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques – Clock bootstrapping – Bottom plate sampling
•
Settling and noise analysis in charge-redistribution track-and-hold circuit
•
Noise simulation example
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SC Noise Simulation •
There are at least three ways to simulate noise in switched capacitor circuits
•
Basic .ac/.noise Spice simulations – Simulate noise in each clock phase separately • Activate φ1 switches, run .noise and integrate noise charge at relevant node over all frequencies and refer to output • Activate φ2 switches, run .noise and integrate noise over all frequencies at the output • Sum integrated noise from the two phases – This is analogous to the way we carried out the hand analysis
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SC Noise Simulation •
Periodic Steady State Simulation – First run PSS analysis to find the periodic operating point • Analogous to .op for .ac/noise – Next run PNOISE analysis • Computes total noise, taking all clock phases, noise aliasing, noise correlations, etc. into account
•
Transient Noise – Direct simulation of all noise sources using a transient simulation – Most physical way of simulating noise
EE315B - Chapter 5
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117
Example T/H Circuit •
Switches sized 5 times faster, i.e. N = 5∙10 = 50 Clp cl Clm cl
vic
vic
Cfm cf
p1
cs Csp
cs Csm
p1
voc vdd vocs
Cfp cf
vic
OTA Gm chosen such than (Ts/2) / τOTA = 10
vic
•
fs = 100 MHz, α = 2, γ = 1 Cs = Cf = 100 fF, CL = 500 fF, Cpar ≅ 0 B. Murmann
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.Noise Simulation (f1) •
*** Compute noise charge at node X and refer to output via Cf
•
en vno 0 vcvs vol =( cs*v(x,s) + cf*v(x,f) )/cf
•
.ac dec 100 100 1000Gig
•
.noise v(vno) vdummy
(showing half circuit for simplicity)
EE315B - Chapter 5
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119
PSD [V2/Hz]
.Noise Simulation (φ1) 10 10 10
-15
-20
-25
Integral [uVrms]
10
B. Murmann
6
2
x 10
10
4
6
8
10 10 Frequency [Hz]
10
10
10
12
-4
406µVrms
4 2 0 2 10
10
4
6
8
10 10 Frequency [Hz]
EE315B - Chapter 5
10
10
10
12
120
PSD [V2/Hz]
.Noise Simulation (φ2) 10 10 10
-15
-20
-25
Integral [uVrms]
10
4
2
x 10
10
6
8
10 10 Frequency [Hz]
10
10
10
12
-4
266µVrms
2 0 2 10
10
2 v out,tot = B. Murmann
4
4
6
8
10 10 Frequency [Hz]
10
10
( 406µVrms )2 + ( 266µVrms )2
10
12
= 485µVrms
EE315B - Chapter 5
121
PSS Simulation Setup
Set “tstab” if your circuit needs time to reach steady state (e.g. clock bootstrap circuits) Under “options” set “maxacfreq” to the highest frequency from which you expect noise to fold down
B. Murmann
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122
PSS Waveforms (Clocks) 4.75ns
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123
PNOISE Simulation Setup Numsidebands ≅ fmax/fs, where fmax is the maximum frequency from which you expect significant noise folding
“timedomain” means simulator computes spectrum of discrete time noise samples at the specified sampling instant
Sampling instant (4.75ns in this example)
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124
How to Chose Parameters • Maxacfreq must be set commensurate with the speed of the switches – Common pitfall: Use nice 1mΩ switches must consider noise from “DC to daylight” • In our example Maxacfreq ≅ 10 ⋅
1 10 = ⋅ N ⋅ fs 2πRonC π
Maxacfreq ≅ 3 ⋅ 50 ⋅ 100MHz = 15GHz
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125
How to Chose Parameters • In traditional PSS/PNOISE simulators (such as SpectreRF), simulation time increases rapidly for large values of Numsidebands • Berkeley Design Automation (BDA) Analog FastSPICE (AFS) automatically includes an infinite number of sidebands at significantly reduced simulation times
Numsidebands ≅
B. Murmann
Maxacfreq 15GHz = = 150 fs 100MHz
EE315B - Chapter 5
126
PNOISE Result (SpectreRF) Sampled Noise PSD
Integrated Noise
EE315B - Chapter 5
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127
Transient Noise Using BDA AFS •
Simulated 1000 samples
•
Only one critical setting: noisefmax = 15 GHz
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128
Comparison •
Very good agreement between hand calculation and all three simulation approaches
Method
φ1 Noise φ2 Noise Total Comment [µVrms] [µVrms] [µVrms]
Calculation
406
245
474
.NOISE
406
266
485
PNOISE
-
-
475
Somewhat smaller than .NOISE due to finite Maxacfreq and Numsidebands
TRAN NOISE
-
-
477
Somewhat smaller than .NOISE due to statistical fluctuations (can use more samples)
B. Murmann
Neglected switch noise during φ2 smaller value than .NOISE
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129
Advantages of TRAN NOISE • Takes advantage of rapid advancements in very fast, spice-accurate transient simulators (such as BDA AFS) – Can handle much larger circuits compared to PSS/PNOISE (PSS tends to have convergence issues for large circuits) • Intuitive inspection of waveforms • No need to combine noises manually – Compared to .ac/.noise simulation flow • Applicable also to non-periodic circuits
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Further Reading on Noise •
Basics – B. Murmann, "Thermal Noise in Track-and-Hold Circuits: Analysis and Simulation Techniques," IEEE Solid-State Circuits Magazine, vol. 4, no. 2, pp. 46-54, June 2012.
•
SC integrator noise analysis – R. Schreier, J. Silva, J. Steensgaard, and G.C. Temes, "Designoriented estimation of thermal noise in switched-capacitor circuits," IEEE TCAS1, vol.52, no.11, pp. 2358-2368, Nov. 2005.
•
Total integrated noise expressions for more complex OTAs (two-stage, etc.) – A. Dastgheib and B. Murmann, “Calculation of Total Integrated Noise in Analog Circuits,” IEEE TCAS1, vol. 55, no. 10, pp. 2988-2993, Oct. 2008.
•
Transient noise simulation example for a complete ADC – Lennart Mathe and David C. Lee, "Analog-to-Digital Converter Performance Signoff with Analog FastSPICE Transient Noise at Qualcomm," Berkeley Design Automation, www.berkeley-da.com.
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Summary – Sampling Circuits •
Three predominant implementation styles – Purely passive – Source follower T/H, up to ~9-10bit accuracy – Charge redistribution or flip-around architecture
•
In a typical, properly designed circuit only the most fundamental issues are significant – Jitter, kT/C noise
•
Charge injection is not a problem if properly handled – E.g., use bottom plate sampling
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Voltage Comparators
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
B. Murmann
EE315B - Chapter 6
1
Recap
•
Ultimately, building a quantizer requires circuit elements that "make decisions"
•
The most widely used "decision circuit" is a voltage comparator
B. Murmann
EE315B - Chapter 6
2
Preview - Flash ADC
2B-1
Dout
Vin 2B-1 Decision Levels
B. Murmann
EE315B - Chapter 6
3
Ideal Voltage Comparator
•
Function – Compare the instantaneous values of two analog voltages (e.g. an input signal and a reference voltage) and generate a digital 1 or 0 indicating the polarity of that difference – We essentially want to implement “infinite” gain
B. Murmann
EE315B - Chapter 6
4
How to Implement High Gain? •
Considerations – Amplification need not be linear – Amplification need not be continuous time if comparator is used in a sampled data system • Clock signal will tell comparator when to make a decision • We will focus on this case, since it is the predominant scenario
•
Implementation options to be looked at – Multi-stage amplification • E.g. cascade of resistively loaded differential pairs
– Regenerative latch using positive feedback • E.g. cross coupled inverters
EE315B - Chapter 6
B. Murmann
5
Input Signal Scenarios Sampled Data Input
Our focus
φ2
Continuous Time Input
B. Murmann
EE315B - Chapter 6
6
Cascade of Open-Loop Amplifiers
In each stage:
•
ωu =
gm ≅ const. Cgs
A 0 = gmR =
ωu ω0
ω0 =
ω 1 = u RC A 0
What is the best choice for a given gain requirement? – Single stage with lots of voltage gain (OTA)? – Only a few stages with moderate gain? – Lots of stages with low gain? EE315B - Chapter 6
B. Murmann
7
Step Response (1) •
When the input is a sampled data signal, we want to achieve the fastest possible amplification in response to an input step
Vout (s) = Vin (s)A(s) =
Vistep s
Av N
(1+ s ⋅ τ A ) 1/N
u
v
τu =
1 ωu
A v = AN 0
i t t − 1/N 1/N N −1 τ ⋅ A Vout (t) = Vistep A v 1 − e τu ⋅ A v ∑ u v i! i=0
A(t) B. Murmann
EE315B - Chapter 6
8
Step Response (2) 10
Step response A(t)
8
τd(N=3) 10(1-e-1)
6 4
N=1 N=3 N=5
2
Av*(1-e-1)
0 0
5
10
15
Time t/τu
•
Three stage amplifier wins! (for Av=10) EE315B - Chapter 6
B. Murmann
9
Delay versus Number of Stages
(
A( τd ) = A v 1 − e−1
)
⇒ τd
(numerically)
50 Av=10 Av=100 Av=1000
Delay time τd/τu
40
30
20
10
0
• •
2
4
6 8 10 N (Number of stages)
12
14
Using a single stage is a non-starter The optimum number of stages show a shallow minimum
B. Murmann
EE315B - Chapter 6
10
Optimum Number of Stages
Optimum number of stages
12 Numerical result ln(Av)
10 8 6 4 2 0 0 10
10
1
2
10 10 Av (Total gain)
3
10
4
10
5
Nopt ≅ ln(A v )
EE315B - Chapter 6
B. Murmann
11
Optimum Gain per Stage A0,opt (Optimum gain per stage)
5
4 3.5 3 2.5 2 1.5 1 0 10
Nopt ≅ ln(A v )
B. Murmann
Numerical result e
4.5
10
1
2
10 10 Av (Total gain) Nopt
e
3
≅ A v = A 0,opt
EE315B - Chapter 6
10
Nopt
4
10
5
⇒ A 0,opt ≅ e
12
Cascade of "Integrators" (1)
•
Intuition – Load resistors (in a cascade of open-loop amplifiers) shunt current away from load capacitance; this slows down amplification
•
Analysis using integrator stages
ω g v o1 = m vin = u vin sC s
v oN =
ωN u sN
vin
EE315B - Chapter 6
B. Murmann
13
Cascade of Integrators (2) Vistep ωN u N s s
Vout (t) = Vistep ⋅ ωN u
10
10
8
8 Step response A(t)
Step response A(t)
Vout (s) =
6
4 N=1 (with R) N=1 (integ)
2
6
4 N=3 (with R) N=3 (integ)
2
Av*(1-e-1) 0 0
B. Murmann
5
10 Time t/τu
tN N!
Av*(1-e-1) 15
0 0
EE315B - Chapter 6
5
10 Time t/τu
15
14
Cascade of Integrators (3) •
Cascade of integrators achieves faster amplification than cascade of resistively loaded stages
•
Delay time 1/N
τd = τu [(N!⋅ A( τd ))]
•
A( τd ) =
Vout ( τd ) Vinstep
Optimum number of stages approximately given by Nopt = 1.1ln [ A( τd )] + 0.79
•
[Wu, JSSC 12/1988]
Effective gain per stage is still relatively close to e=2.7183…
EE315B - Chapter 6
B. Murmann
15
Regenerative Sense Amplifier (Latch) Conceptual Circuit
t=0
Inverter Transconductance
[Figueiredo]
⋅ /
φ1: Set up initial condition (vOD0) φ2: Enable positive feedback B. Murmann
EE315B - Chapter 6
/
16
Simulation Example I4
I7
vdm vp ideal_balun vcm vm
vic
vip
vop
vim
vom
vp
vdm ideal_balun vm vcm
p2!
vid
M0 10u/0.18u
vod voc
M4 10u/0.18u p1!
vip
C3 cl
vid
vdc:vdd vdc:vic
M1 5u/0.18u
M3 5u/0.18u
C0 cl
V5 vdc:vid
B. Murmann
CL=100 fF
p2!
vic
V2
vop
p1 p1b p1e p1eb p2 p2b p2e clock_gen
p1!
vdd
V0
vim
vom
p1!
p2!
EE315B - Chapter 6
17
Transient Response Nodes vOP and vON for differential inputs of 1mV, 1µV, 1nV and 1pV
φ2 goes high
B. Murmann
EE315B - Chapter 6
18
Transient Response Differential Mode
Common Mode
EE315B - Chapter 6
B. Murmann
19
Transient Response (Log Scale)
= ⋅ భ/ = ⋅ మ/
B. Murmann
=
600ps 600ps − = = = 43
ln 10 6 ⋅ 2.3 ln
EE315B - Chapter 6
20
Comparison 10
Amplification A(t)
8
6
4 N=3 (with R) N=3 (integ) Latch
2
Av*(1-e-1)
0 0
•
5
t/τ t/τ Time
10
15
Latch is much faster than cascade of amplifiers/integrators
EE315B - Chapter 6
B. Murmann
21
Latch Gain
B. Murmann
A(τd)
τd/τ
10
2.3
100
4.6
1,000
6.9
10,000
9.2
EE315B - Chapter 6
22
"The" Architecture
•
Why bother using pre-amplification (Av)?
•
Pre-amplification may be used for several reasons – Lower offset (latch offset tends to be large) – Lower thermal noise – Attenuation of "kickback noise” – Separate input from output – Common mode rejection
B. Murmann
EE315B - Chapter 6
23
Basic Topology Examples (1) •
Class-A (constant current)
Figure from [Figueiredo, TCAS2, July 2006] B. Murmann
EE315B - Chapter 6
24
Basic Topology Examples (2) •
Class-AB – Input pair has constant bias, but latch draws current only while making a decision
Figure from [Figueiredo, TCAS2, July 2006]
B. Murmann
EE315B - Chapter 6
25
Basic Topology Examples (3) •
Fully dynamic – Draws (significant) current only while making a decision
Original paper: [Kobayashi, JSSC, April 1993]
Figure from [Figueiredo, TCAS2, July 2006]
B. Murmann
EE315B - Chapter 6
26
Offset in Latches vOP
vON
VOS,static
Inverter switching voltage: VS Initial common mode: VOC0
CLP
CLN
Load capacitor mismatch: ∆CL
•
Static offset (VOS) due to transistor mismatch (primarily Vt)
•
Dynamic offset due to load capacitor mismatch – For an analysis see Nikoozadeh, TCAS II, Dec. 2006 , ≅
1 Δ − 2
Example:
1 10 0.3 − 0.9 = 30 2 100
Minimize, if possible
EE315B - Chapter 6
B. Murmann
27
Input Referred Offset with Preamplification
σ2VOS = σ2VOS1 +
•
1 A 2v
σ2VOS2
Example: σVOS1=3mV, σVOS2=30mV, Av=10 σ VOS =
B. Murmann
( 3mV )2 +
1 10
2
( 30mV )2
EE315B - Chapter 6
= 4.2mV
28
Dealing With Offset •
Options depend strongly on the application context
•
May use an ADC architecture that inherently tolerates offset – More later
•
May use a relatively coarse tuning mechanism – E.g. tune offset to lie within ½ LSB at the 6-bit level
•
May have to apply precision techniques – Autozeroing, etc. (see EE315A), for high-end instrumentation
•
Simply use large transistors – Usually not power efficient
B. Murmann
EE315B - Chapter 6
29
Example: Coarse Offset Tuning •
The circuit below uses capacitve imbalance to tune the offset – An example of using a "bug" as a feature – See e.g. Van der Plas, ISSCC 2006
•
Watch out for PSRR degradation due to circuit imbalance
B. Murmann
EE315B - Chapter 6
30
Example: Precision Comparator [http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3956]
• •
Used in the AD7671, 16-bit, 1-MS/s successive approximation ADC Uses cascaded output series offset cancellation (see EE315A)
B. Murmann
EE315B - Chapter 6
31
Electronic Noise in Latch Comparators •
Class-A topology – Integrate noise at regenerative node over all frequencies and refer to the input α·kT/CL – See Opris, Electronics Letters, July 1997
•
Dynamic topology – Very hard to analyze due to the time variant behavior – See Nuzzo, IEEE TCAS1, July 2008 – Fortunately, the end result is not too far from class-A-like noise estimation in the decision point α·kT/CL
B. Murmann
EE315B - Chapter 6
32
Kickback
E.g. Flash ADC resistor ladder
Figure from [Figueiredo, TCAS2, July 2006]
EE315B - Chapter 6
B. Murmann
33
Kickback Mitigation Techniques Neutralization
Neutralization and Switch Isolation
Figures from [Figueiredo, TCAS2, July 2006]
B. Murmann
EE315B - Chapter 6
34
Kickback Mitigation Techniques
Extra switches act similar to cascodes
[Sundstrom, MIXDES 2007]
B. Murmann
EE315B - Chapter 6
35
Other Design Considerations •
Input capacitance and linearity of input capacitance – Consider e.g. loading of the input network in a flash ADC
•
Overdrive recovery – Consider a very large input, followed by a very small input of opposite polarity
•
Metastability – What if the input is so small that the comparator cannot decide in the given amount of time?
B. Murmann
EE315B - Chapter 6
36
Overdrive Recovery Test Latch activation 1
2
Comparator input
Preamp output
•
[Razavi, p. 183]
The test is passed when the latch output changes polarity in case 1, but not in case 2 EE315B - Chapter 6
B. Murmann
37
Metastability (1) •
The plot below shows the time needed to regenerate a given differential latch input to full logic swing 35 30
treg/τ
25
ݐ ܸ = ln ݒை ߬
20 15 10 5 0 -15 10
10
-10
10
-5
10
0
v
vOD0/V/VDD
B. Murmann
EE315B - Chapter 6
38
Metastability (2) •
What if the input is so small that we run out of time?
•
This is called a metastable state, i.e. at the end of the clock cycle there is no clear logic decision
•
The following logic gates will go into an erratic state that is hard to predict, and so we classify this outcome as an error
•
In the following analysis we will try to estimate the probability at which metastable states will occur
•
Application requirements vary widely – Error correction coding in certain communication sytems can absorb probabilities of up to 10-3 – High-speed wireline links (without coding) or instrumentation equipment may require probabilities better than 10-18
EE315B - Chapter 6
B. Murmann
39
Metastability (3) •
Assume that the maximum available time is tmax
•
The minum latch input we can regenerate is then , =
•
In case, we have a preamp, we can do slightly better , =
•
ೌೣ / 1 ೌೣ /
Now assume that the input is uniformly distributed over some range, and compute the probabily of seeing a metastable state PDF
, ೌೣ / = = , ,
-vID0,max +vID0,max -vID0,min +vID0,min B. Murmann
EE315B - Chapter 6
40
Mean Time to Failure •
In some applications it makes sense to think about metastability in terms of the mean time between metastable events – Mean time to failure (MTF)
2
MTF [days]
10
=
1 ⋅
0
10
fs=10GHz
fs=100MHz
-2
10
-18
10
-16
10
-14
10
-12
10
-10
10
Pmeta
EE315B - Chapter 6
B. Murmann
41
Example: Flash ADC •
In a flash ADC, there is always (exactly) one comparator that sees an input within ± ∆/2
•
The probability of seeing a metastable state within the array is therefore found using vID0,max = ∆/2 =
•
ೌೣ / ೌೣ / = 1 V Δ 2 2 2
The graph on the next slide plots an example – Sampling rate fs = 1GHz, tmax ≅ 1/2fs = 500ps – B = 6, Av =1, VFS = VDD
B. Murmann
EE315B - Chapter 6
42
Example: Flash ADC 0
10
-5
Pmeta
10
-10
10
-15
10
-20
10
10
• •
20
30
40 50 τ [ps]
60
70
80
The curve is incredibly steep in the region of Pmeta < 10-5 Very strong incentive to minimize τ as much as possible – Ultimitaley bounded by Cgg/gm = 1/ωT
B. Murmann
EE315B - Chapter 6
43
Metastability Detectors? • •
•
Why not build a clever logic circuit that detects the metastable state and overrides it with a valid logic state? This sounds good, but is difficult to do in reality – Logic gates look like "low pass filters" compared to a latch – A latch provides the maximum possible gain per unit of time; any gate delay added after the latch (that eats into the regeneration time) is counterproductive Most (if not all) metastability detector ideas proposed in literature tend to create new metastable states – Related article: R. Ginosar, "Fourteen ways to fool your synchronizer," 2003
B. Murmann
EE315B - Chapter 6
44
Comparator Examples (1) •
Mehr & Dalton, JSSC 7/1999
B. Murmann
EE315B - Chapter 6
45
Comparator Examples (2) •
Mehr & Dalton, JSSC 7/1999
B. Murmann
EE315B - Chapter 6
46
Comparator Examples (3) •
Schinkel, ISSCC 2007: "Double tail sense amplifier"
EE315B - Chapter 6
B. Murmann
47
Comparator Examples (4) •
Miyahara, ASSCC 2009
B. Murmann
EE315B - Chapter 6
48
Comparator Examples (5) •
Lee, JSSC, April 2011
EE315B - Chapter 6
B. Murmann
49
Comparator Examples (6) •
Tripathi, ESSCIRC 2013
τ ≅ 6ps
B. Murmann
EE315B - Chapter 6
50
Selected References (1) 1. Y. S. Yee, L. M. Terman and L. G. Heller, “A 1mV MOS Comparator,” IEEE J. of Solid-State Circuits, vol. SC-13, pp. 294-297, June 1978. 2. A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” IEEE J. of Solid-State Circuits, vol. SC-20, pp. 775-779, June 1985. 3. B. J. McCarroll, C. G. Sodini, and H.-S. Lee, “A High-Speed CMOS Comparator for Use in an ADC,” IEEE J. of Solid-State Circuits, vol. 23, pp. 159-165, Feb. 1988. 4. J.-T. Wu and B. A. Wooley, “A 100-MHz Pipelined CMOS Comparator,” IEEE J. SolidState Circuits, vol. 23, pp. 1379-1385, Dec. 1988. 5. B. Razavi and B. A. Wooley, “A 12-b 5-MSample/s Two-Step CMOS A/D Converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 1667-1678, Dec. 1992. 6. B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators,” IEEE J. Solid-State Circuits, vol. 27, pp. 1916-1926, Dec. 1992. 9.
M. Choi and A. A. Abidi, "A 6-b 1.3-GSample/s A/D converter in 0.35-µm CMOS," IEEE J. Solid-State Circuits, pp. 1847-1858, Dec. 2001.
10. I. Mehr and D. Dalton, "A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive readchannel applications," IEEE J. Solid-State Circuits, pp. 912-920, July 1999. 11. I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-MSample/s Nyquist-Rate CMOS ADC,” IEEE J. Solid-State Circuits, pp. 318-25, March 2000. 12. G.R. Couranz, and D.F. Wann, "Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region," IEEE Trans. Computers, vol. C24, no.6, pp. 604-616, June 1975. B. Murmann
EE315B - Chapter 6
51
Selected References (2) 9.
H. J. M. Veendrick, “The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate,” IEEE J. Solid-State Circuits, April 1980.
10. B. Zojer, et al., “A 6-bit/200-MHz full Nyquist A/D converter,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 780-786, June 1985. 11. K.-L.J. Wong and C.-K.K. Yang, "Offset compensation in comparators with minimum input-referred supply noise," IEEE J. Solid-State Circuits, pp. 837-840, May 2004. 12. A. Graupner, "A Methodology for the Offset-Simulation of Comparators," http://www.designers-guide.org/Analysis/comparator.pdf. 13. D. Schinkel et al., "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time," ISSCC Dig. Techn. Papers, pp. 314-315, 2007. 14. P.P. Nuzzo, et al., "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures, IEEE Trans. Circuits Syst. I, pp.1441-1454, July 2008. 15. B.S. Leibowitz, et al., "Characterization of Random Decision Errors in Clocked Comparators," Proc. IEEE CICC, pp.691-694, Sep. 2008. 16. Analog Devices, "Find Those Elusive ADC Sparkle Codes and Metastable States" http://www.analog.com/en/content/0,2886,760%255F788%255F91218,00.html 19. M. Miyahara and A. Matsuzawa, "A low-offset latched comparator using zero-static power dynamic offset cancellation technique," ASSC, pp. 233-236, Nov. 2008. 20. P.M. Figueiredo, "Comparator Metastability in the Presence of Noise," IEEE TCAS1, vol. 60, no. 5, pp.1286-1299, May 2013.
B. Murmann
EE315B - Chapter 6
52
Flash ADCs
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
EE315B - Chapter 7
B. Murmann
1
Nyquist ADC Architectures •
Nyquist rate – Word-at-a-time • Flash ADC • Instantaneous comparison with 2B-1 reference levels
– Multi-step • E.g. pipeline ADCs • Coarse conversion, followed by fine conversion of residuum
– Bit-at-a-time • E.g. successive approximation ADCs • Conversion via a binary search algorithm
SPEED
– Level-at-a-time • E.g. single or dual slope ADCs • Input is converted by measuring the time it takes to charge/discharge a capacitor from/to input voltage B. Murmann
EE315B - Chapter 7
2
ADC Survey (ISSCC & VLSI 1997-2013) Data: http://www.stanford.edu/~murmann/adcsurvey.html
10
Flash Folding Two-Step Pipeline
10
10
SAR Other 1000fs
in,hf
[Hz]
∆Σ 8
f
100fs 10
10
rms
rms
Jitter
Jitter
6
4
20
30
40
50
60
70 80 SNDR [dB]
90
100
110
120
hf
EE315B - Chapter 7
B. Murmann
3
Flash ADC Speed 7
Clock Speed [GHz]
6
Flash ADCs Microprocessors
5 4 3 2 1 0 1996
1998
2000
2002
2004
2006
2008
Year B. Murmann
EE315B - Chapter 7
4
Modern Flash ADC Architecture Vadc
Vadc Dout
T/H
•
Fast – Speed limited only by comparator decision High complexity, large input capacitance – Resolution tends to limited to 6 bits
•
B. Murmann
Wallace Encoder
CLK
Vin
Usually implemented as a fully differential circuit
EE315B - Chapter 7
5
Why Use a T/H? •
One reason: Timing offsets between comparators may cause “bubbles” in the thermometer code
Single bubble Double bubble Fast moving input
K. Uyttenhove, M.S.J. Steyaert, "A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS," JSSC, pp. 1115-1122, July 2003.
B. Murmann
EE315B - Chapter 7
6
Bubble Problem in a “Poor Man’s” Encoder
e.g. due to timing offset between two comparators
•
Correct output: 1000, actual output: 1110 (!)
B. Murmann
EE315B - Chapter 7
7
Bubble Tolerant Encoder
•
Protects against single bubbles
•
Reference: C. W. Mangelsdorf, “A 400-MHz Flash Converter with Error Correction,” IEEE J. Solid-State Circuits, pp. 184-191, Feb. 1990.
B. Murmann
EE315B - Chapter 7
8
Modern Solution: Wallace Encoder
B. Murmann
•
Simply a “ones adder”
•
F. Kaess, et al., “New encoding scheme for high-speed flash ADCs,” ISCAS 1997, pp. 5–8
•
Complexity used to be an issue in older technology; not a problem in sub-100nm CMOS
•
Number of adders needed for N bits:
EE315B - Chapter 7
9
Alternative (or Additional) Solution •
Still want to use a T/H, even if bubbles are not a problem – Simplified comparator design – Well-behaved input impedance – T/H need not be all that complex
Source follower T/H
Y. Tamba, and K. Yamakido, "A CMOS 6 b 500 MS/s ADC for a hard disk drive read channel,“ ISSCC 1999, pp. 324-325 B. Murmann
EE315B - Chapter 7
10
How about Metastability?
• • •
Different gates interpret metastable output X differently Correct output: 0111 or 1000, actual output: 1111 (!) Again, a simple encoder does not handle this very well
B. Murmann
EE315B - Chapter 7
11
Solution 1: Wallace Encoder
B. Murmann
•
Similar reasoning as with bubbles
•
Error due to metastable input is bounded by 1LSB
EE315B - Chapter 7
12
Solution 2: Latch Pipelining
• •
Use additional latches to create extra gain before generating decoder signals Usually too power hungry and area inefficient EE315B - Chapter 7
B. Murmann
13
Solution 2: Gray Encoding Thermometer Code
Gray
T1
T2
T3
T4
T5
T6
T7
G3
G2
G1
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
• G3
B. Murmann
Binary
G2
G1
EE315B - Chapter 7
Each Ti affects only one Gi – Avoids disagreement of interpretation by multiple gates
14
Efficient Implementation
•
Reference – C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,” IEEE J. Solid-State Circuits, pp. 1132-40 , Aug. 1996.
EE315B - Chapter 7
B. Murmann
15
Offset •
Typically want offset of each comparator <1/4LSB with high probability (“3 sigma”) – If we budget half of the input referred offset for the latch, the other half for the pre-amp, this means pre-amp offset must be <1/4LSB / sqrt(2) 3σVOS = 3
•
AVT WL
<
1 FSR 4 2 2B
E.g. 6-bit flash ADC, FSR=1V 3
AVT 1 1V < = 2.8mV WL 4 2 26
Huge! 2 2 2 A 3 18.4µm 3 ⋅ 4mV µm 2 VT WL > = 102µm = 18.4µm ⇒ W > = 0.18µm 2.8mV 2.8mV
B. Murmann
EE315B - Chapter 7
16
Re-cap of Options •
Simply use large devices – For each extra bit, need to increase width by 4x, also need to double number of comparators – Assuming constant current density, this means each additional bit costs 8x in power!
•
Dynamic offset cancellation (autozeroing, etc.) – Tends to cost speed
•
More commonly used – Offset averaging – Offset calibration – Incorporation of redundant comparators
B. Murmann
EE315B - Chapter 7
17
Offset Averaging (1)
R2/R1=1.3
[Kattmann & Barrow, ISSCC 1991] B. Murmann
EE315B - Chapter 7
18
σDNL/σ
Offset Averaging (2)
[Bult & Buchwald, JSSC 12/1997]
[Scholtens & Vertregt, JSSC 12/2002] B. Murmann
EE315B - Chapter 7
19
6-bit Flash ADC with Averaging [Choi & Abidi, JSSC 12/2001]
Averaging networks designed to reduce input referred offset by 3x
B. Murmann
EE315B - Chapter 7
20
Offset Calibration Using Global DAC
S. Sutardja, "360 Mb/s (400 MHz) 1.1 W 0.35μm CMOS PRML read channels with 6 burst 8-20× over-sampling digital servo," ISSCC Dig. Techn. Papers, Feb. 1999. EE315B - Chapter 7
B. Murmann
21
Calibration Using one DAC per Comparator
(Reset switches not shown) 8
Voutn
Voutp
φ Dcalp
CAL
Vlo Vhi
Vrefn
8
8
4
2
1
MUX/Encoder
φ
Vinp
Vinn
φ
Vrefp
CAL
Dcaln
Vlo Vhi
[M. El-Chammas, VLSI 2010]
B. Murmann
EE315B - Chapter 7
22
Offset Calibration at Start-Up
•
Out RefIn-
INC/ DEC
Start-up calibration is reasonably stable at flash ADC resolutions The correction circuit shown on the previous slide has a relatively low temperature dependence
AVG
Control Bits
Out
•
Output oscillates between one and zero as the input-referred offset converges to zero
t
Input-referred Offset
•
In+ Ref+
Offset = 0 t
B. Murmann
EE315B - Chapter 7
23
Tuning Range Issue (1) •
Ideally, the trim-DAC must bring the offset well within one LSB of the flash ADC
•
The required trim-DAC resolution can become unacceptably large if near minimum-size transistors (with large Vt mismatch) in the latest technology are used
•
A clever workaround is to utilize the error correction capability of the Wallace tree encoder (ones counter)
B. Murmann
EE315B - Chapter 7
24
Tuning Range Issue (2) [Verma, ISSCC 2013]
+ Vref0
0
-
Vref0 (eff)
+ Vref1
1
+
Vref2
2
-
Vref2 (eff)
+ Vref3
-
Vref1 (eff)
3 Vref3 (eff)
EE315B - Chapter 7
B. Murmann
25
Ones Counting is Equivalent to Reordering + Vref0
-
[Verma, ISSCC 2013]
2 Vref0 (eff)
+ Vref1
+
Vref2
+
Vref3
-
0
Vref1 (eff)
1 Vref2 (eff)
3 Vref3 (eff)
Reduced tuning range B. Murmann
EE315B - Chapter 7
26
Comparator Redundancy (1) •
Interesting idea: Do not worry about offsets at all, just provide enough levels that properly add up on average 90mW
900mW
Wallace Encoder
Paulus et al., "A 4GS/s 6b flash ADC in 0.13um CMOS," VLSI Circuits Symposium, 2004 B. Murmann
EE315B - Chapter 7
27
Comparator Redundancy (2) •
Another idea: Build a "sea of imprecise comparators", then determine which ones to use…
C. Donovan, M. P Flynn, "A 'digital' 6-bit ADC in 0.25-μm CMOS," IEEE J. Solid-State Circuits, pp. 432-437, March 2002. B. Murmann
EE315B - Chapter 7
28
Differential Pair Redundancy •
Idea: Have multiple input pairs and use the one you like [Chen, VLSI 2013]
B. Murmann
EE315B - Chapter 7
29
Details
B. Murmann
EE315B - Chapter 7
30
Performance Comparison [Chen, VLSI 2013]
B. Murmann
EE315B - Chapter 7
31
Calibration Using Reference String
[Park & Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," CICC 2006] B. Murmann
EE315B - Chapter 7
32
Details
[Park & Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," CICC 2006] B. Murmann
EE315B - Chapter 7
33
Measured Results
[Park & Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," CICC 2006] B. Murmann
EE315B - Chapter 7
34
Reducing Complexity •
Even with calibration, flash ADCs tend to hit a “wall” beyond 6 bits of resolution – Large calibration range – Large input capacitance – Complex encoder
•
Several techniques have been developed to “ease the pain” and potentially allow going beyond 6 bits (at the cost of some speed) – Interpolation – Folding, folding & interpolation – Subranging
EE315B - Chapter 7
B. Murmann
35
Interpolation •
Idea – Interpolation between preamp outputs
•
Reduces number of preamps – Reduced input capacitance – Reduced area, power dissipation
•
Same number of latches
•
Important “side-benefit” – Decreased sensitivity to preamp offset • Improved DNL
B. Murmann
EE315B - Chapter 7
36
Concept
[van de Plassche, p.118]
B. Murmann
EE315B - Chapter 7
37
Differential Implementation
VA + VB =0 2
B. Murmann
EE315B - Chapter 7
⇔ VA = −VB
38
Higher Order Interpolation • Resistors produce additional levels • Define interpolation factor as ratio ratio of latches and preamps • The example shown on this slide has M=8
[H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” IEEE J. of Solid-State Circuits, pp. 438-446, April 1993.
B. Murmann
EE315B - Chapter 7
39
Potential Issues with Interpolation •
Must ensure that "linear range" of adjacent preamplifiers overlaps – Sets upper bound on preamp gain
•
Resistor string reduces signal path bandwidth – Sets upper bound on interpolation factor, typically around 4
•
For interpolation factors >2, amplifier nonlinearity can limit the precision of zero crossings – See e.g. Van de Plassche, p.121
B. Murmann
EE315B - Chapter 7
40
Folding
MSB ADC
VIN
Digital Output LSB ADC Folding Circuit
• Main idea: Re-use comparator several times across the full scale range
B. Murmann
EE315B - Chapter 7
41
Simplest Variant [Verbruggen, JSSC, March 2009]
Folding circuit
B. Murmann
EE315B - Chapter 7
42
Creating Multiple Folds
•
Parameter K sets output common mode EE315B - Chapter 7
B. Murmann
43
Folder Output
Folder Output
0.5
Accurate only at zero-crossings
Ideal Folder CMOS Folder
0
-0.5 0
0.5
1
1.5
2
2.5
3
3.5
4
Lowdown
0.1
Most folding ADCs do not actually use the folds, but only the zero-crossings!
Error
0.05 0 -0.05 -0.1 0
0.5
B. Murmann
1
1.5
2 Vin / ∆
2.5
3
3.5
EE315B - Chapter 7
4
44
Multiple Folds Using Only Zero Crossings
B. Murmann
•
Way too complex, need one folder per decision in the fine ADC
•
Idea – Use interpolation to eliminate some of the folders
EE315B - Chapter 7
45
Interpolation
•
Same idea as discussed previously
B. Murmann
EE315B - Chapter 7
46
Complete Folding & Interpolating ADC
B. Murmann
EE315B - Chapter 7
•
3-bit coarse ADC
•
3-bit fine ADC – 2 folders with 4x interpolation 8 levels
•
We have therefore built a 6-bit ADC with only 16 comparators (instead of 63)
47
8-bit, 70 MS/s Folding and Interpolating ADC
[B. Nauta and G. Venes, JSSC. Dec. 1985]
B. Murmann
EE315B - Chapter 7
48
8-bit, 1.6 GS/s Folding and Interpolating ADC
[Taft et al., JSSC 12/2004]
B. Murmann
EE315B - Chapter 7
49
8b, 10GS/s Folding and Interpolating ADC
[Landolt, PRIME 2012] For Rohde & Schwarz Scope 0.25um SiGe BiCMOS 9 Watts
B. Murmann
EE315B - Chapter 7
50
Performance
EE315B - Chapter 7
B. Murmann
51
Subranging 4-bit Flash ADC
B. Murmann
2+2-bit Subranging ADC
EE315B - Chapter 7
52
8-bit, 1 GS/s Subranging ADC
Coarse ADC selects tap range for fine ADC [Chung, VLSI 2011] B. Murmann
EE315B - Chapter 7
53
Summary ― Flash ADCs & Extensions •
Today, flash ADC design boils down to an effective offset management approach – Calibration and/or redundancy
•
Extensions such as averaging, folding, interpolation and subranging can be used to alleviate the tradeoffs – But these techniques haven’t been popular in recent years – The reason may be the strong competition from pipelined and time interleaved architectures – More later…
B. Murmann
EE315B - Chapter 7
54
Selected References (1) Flash ADCs, Offset Averaging 1. K. Kattmann and J. Barrow, "A Technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters," ISSCC Digest of Technical Papers, pp. 170-171, Feb. 1991. 2. K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1mm2," IEEE J. of Solid-State Ckts., pp. 1887-1895, Dec. 1997. 3. M. Choi and A. A. Abidi, “A 6 b 1.3 Gsample/s A/D converter in 0.35µm CMOS,” IEEE J. Solid-State Circuits, pp. 1847–1858, Dec. 2001. 4. C. S. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s Flash ADC in 0.18-µm CMOS Using Averaging Termination,” IEEE J. of Solid-State Ckts., vol. 37, pp. 1599-1609, Dec. 2002. 5. X. Jiang, M-C. F. Chang, "A 1-GHz signal bandwidth 6-bit CMOS ADC with powerefficient averaging," IEEE J. of Solid-State Circuits, pp. 532- 535, Feb. 2005. Folding and Interpolating A/D Converters 6. R.C. Taft et al., "A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency," IEEE J. Solid-State Ckts., pp. 2107-2115 Dec. 2004. 7. B. Nauta and A. G. W. Venes, “A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter,” IEEE J. of Solid-State Circuits, pp. 1302-1308, Dec. 1995. B. Murmann
EE315B - Chapter 7
55
Selected References (2) 8. 9.
10.
11. 12. 13. 14. 15. 16.
M. P. Flynn and B. Sheahan, “A 400-MSample/s, 6-b CMOS Folding and Interpolating ADC,” IEEE J. of Solid-State Circuits, pp. 1932-1938, Dec. 1998. H. Pan, M. Segami, M. Choi, J. Cao, F. Hatori and A. Abidi, “A 3.3V, 12b, 50MSample/s A/D converter in 0.6mm CMOS with over 80dB SFDR,” ISSCC Digest of Technical Papers, pp. 40-41, Feb. 2000. M.-J. Choe, B.-S. Song and K. Bacrania, “A 13b 40MSample/s CMOS pipelined folding ADC with background offset trimming,” ISSCC Digest of Technical Papers, pp. 36-37, Feb. 2000. G. Hoogzaad and R. Roovers, “A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist ADC in 0.8 mm2,” IEEE J. Solid-State Circuits, pp. 1796-1802, Dec. 1999. K. Nagaraj, F. Chen, T. Le and T. R. Viswanathan, “Efficient 6-bit A/D converter using a 1-bit folding front end,” IEEE J. Solid-State Circuits, pp. 1056-1062, Aug. 1999. M.-J. Choe and B.-S. Song, “An 8b 100MSample/s CMOS pipelined folding ADC,” VLSI Symposium Digest of Technical Papers, pp. 81-82, Jun. 1999. K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1 mm2,” IEEE J. Solid-State Circuits, vol. 32, pp. 1887-1895, Dec. 1997. P. Vorenkamp and R. Roovers, “A 12-b, 60-MSample/s cascaded folding and interpolating ADC,” IEEE J. Solid-State Circuits, vol. 32, pp. 1876-1886, Dec. 1997. A. G. W. Venes and R. J. van de Plassche, “An 80-MHz, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing,” IEEE J. Solid-State Circuits, vol. 31, pp. 1846-1853, Dec. 1996.
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56
Selected References (3) 17. M. P. Flynn and D. J. Allstot, “CMOS folding A/D converters with current-mode interpolation,” IEEE J. Solid-State Circuits, vol. 31, pp. 1248-1257, Dec. 1996. 18. R. Roovers and M. S. J. Steyaert, “A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 31, pp. 938-944, Jul. 1996. 19. W. T. Colleran and A. A. Abidi, “A 10-b, 75-MHz two-stage pipelined bipolar A/D converter,” IEEE J. Solid-State Circuits, vol. 28, pp. 1187-1199, Dec. 1993. 20. J. van Valburg and R. J. van de Plassche, “An 8-b 650-MHz folding ADC,” IEEE J. Solid-State Circuits, vol. 27, pp. 1662-1666, Dec. 1992. 21. R. J. van de Plassche and P. Baltus, “An 8-bit 100-MHz full-Nyquist analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 23, pp. 1334-1344, Dec. 1988. 22. R. E. J. Van de Grift, I. W. J. M. Rutten and M. van der Veen, “An 8-bit video ADC incorporating folding and interpolation techniques,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 944-953, Dec. 1987. 23. R. E. J. van de Grift and R. J. van de Plassche, “A monolithic 8-bit video A/D converter,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 374-378, Jun. 1984. 24. R.C. Taft, et al., "A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency," ISSCC Digest of Technical Papers, pp.78-79, 79a, Feb. 2009.
B. Murmann
EE315B - Chapter 7
57
SAR ADCs
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
EE315B - Chapter 8
B. Murmann
1
Similarity Between Non-Flash ADC Architectures ε
Vin
Σ
Minimize
D/A
•
Dout
Most ADC architectures (other than flash) are based on minimizing the error between input and a D/A signal approximation – SAR ADC uses comparator to sense ε – Sigma-delta ADC minimizes ε via integration and feedback – Pipeline uses distributed DAC
B. Murmann
2
Successive Approximation Register ADC
•
Binary search over DAC output
•
High accuracy achievable (16+ Bits) – Relies on highly accurate comparator
•
Moderate speed (1+ MHz)
B. Murmann
EE315B - Chapter 8
3
High Performance Example
B. Murmann
EE315B - Chapter 8
4
Low Power Example
M.D. Scott, B.E. Boser, K.S.J. Pister, "An ultralow-energy ADC for Smart Dust," IEEE J. Solid-State Circuits, pp. 1123 -1129, July 2003. EE315B - Chapter 8
B. Murmann
5
Classical Implementation •
See e.g. [McCreary, JSSC 12/1975]
Bottom plate sampling
B
B
C1A = C1B = C B. Murmann
C2 = 2C
C3 = 4C
EE315B - Chapter 8
CB = 2B −1C 6
Sampling Phase (5-bit Example)
•
Total charge at node Vx after opening Sx Q = −Vin ⋅ 32C = −Vin ⋅ Ctotal
B. Murmann
EE315B - Chapter 8
7
Bit5 Test (MSB)
(
Q = −Vin ⋅ Ctotal = (Vx − Vref ) ⋅ 16C + Vx ⋅ 16C + Cp
)
Ctotal 1 ∴Vx = Vref − Vin ⋅ 2 Ctotal + Cp
•
Vx<0 ⇒ Vin>0.5Vref ⇒ Bit5=1
•
Vx>0 ⇒ Vin<0.5Vref ⇒ Bit5=0
B. Murmann
EE315B - Chapter 8
8
Bit4 Test (Assuming Bit5=0)
(
Q = −Vin ⋅ Ctotal = (Vx − Vref ) ⋅ 8C + Vx ⋅ 24C + Cp
)
Ctotal 1 ∴Vx = Vref − Vin ⋅ 4 Ctotal + Cp
•
Vx<0 ⇒ Vin>0.25Vref ⇒ Bit4=1
•
Vx>0 ⇒ Vin<0.25Vref ⇒ Bit4=0
B. Murmann
EE315B - Chapter 8
9
Challenges at High Resolution •
Capacitor mismatch – Use “self calibration” to obtain precision beyond raw technology matching [Lee, JSSC 12/84]
•
Minimum capacitor size, e.g. Cmin=10fF 216Cmin = 655pF – Solution: Implement "two-stage" or "multi-stage" capacitor network to reduce array size [Yee, JSSC 8/79] – Typically mandates some form of calibration
•
Ultimately, even with calibration, there is still a lower bound based on kT/C in the sampling phase – E.g. 16-bit resolution, Ctotal ~ 100pF required – How to drive such an ADC at high speeds?
B. Murmann
EE315B - Chapter 8
10
Recent Publication Trend 12
SAR ADC Papers at ISSCC and VLSI Symposium 10
Count
8
6
4
2
0 1996
1998
B. Murmann
2000
2002
2004 2006 Year
2008
2010
2012
EE315B - Chapter 8
2014
11
Recent Innovations in SAR ADCs •
Mostly focused on low-to-moderate resolution!
•
Use of extremely small unit capacitors (<1fF) – E.g. [Shikata, VLSI 2011] Energy efficient switching techniques – E.g. [Liu, VLSI 2010] Asynchronous operation – E.g. [Chen, CICC 2006] Incomplete DAC settling enabled by redundancy – E.g. [Liu, VLSI 2010] 100 MS/s, ~ 9.5 ENOB SAR ADC pipelining – E.g. [Lee, VLSI 2010] 50MS/s, ~10.5 ENOB Massive time interleaving – E.g. [Doris, ISSCC 2011] 2.6 GS/s, ~ 8 ENOB
• • • • •
B. Murmann
EE315B - Chapter 8
12
Small Metal Fringe Capacitors •
Want to minimize unit caps as much as possible for low-tomoderate resolution SAR ADCs 0.5fF unit capacitors
[Shikata, VLSI 2011]
13 13
B. Murmann
Asynchronous Timing
[Chen & Brodersen, JSSC 12/2006]
•
Key insight: At most one of the SAR decisions can be close to metastability; all others will be very fast
•
Asynchronous timing exploits this by allocating the most time to the “hardest” decision
B. Murmann
EE315B - Chapter 8
14
Energy Efficient Switching (1) •
Conventional switching scheme is wasteful in terms of energy
[Liu, JSSC 4/2010] [Liu, JSSC 4/2010]
EE315B - Chapter 8
B. Murmann
15
Energy Efficient Switching (2)
Top plate sampling First decision “free”
[Liu, JSSC 4/2010]
•
Total of 81% switching energy reduction
•
Caveat: Need comparator with good common-rejection B. Murmann
EE315B - Chapter 8
16
Constant Common Mode CDAC
[Kull, ISSCC 2013]
B. Murmann
EE315B - Chapter 8
17
Energy Efficient Switching (3) MSB cap split into two
[Ginsburg, ISCAS 2005]
• •
Key insight: Do not have to switch entire MSB cap for first DAC transition Total energy savings of 37% B. Murmann
EE315B - Chapter 8
18
Resistive DAC
[Wei, ISSCC 2011]
•
Multi-bit/cycle architecture yielding 8 bits at 400 MS/s EE315B - Chapter 8
B. Murmann
19
DAC Settling Errors
ε0(t)
t tdecision bk
Input -1 ≤ x ≤ +1
Σ
Σ
-
(conceptual model)
2-1
1 b0 1
-
b1 2-1
b2 2-2
Σ
B. Murmann
Register
EE315B - Chapter 8
Output x 20
Error in First Decision 1
1
k=0
2
3
x 0 x̂
-1
EE315B - Chapter 8
B. Murmann
21
Redundancy (Radix < 2) x
bk Σ
Σ
-
-
β-1
1 b0 1
Σ
-
β-2 b1
b2
β-1
β-2
b3
Register
β-3 Output x
Σ
ି
ࢼ<
ࢼି > ୀ
B. Murmann
EE315B - Chapter 8
22
Error in First Decision (β = 22/3) 1
k=0
2
1
3
4
x 0
x̂
Error ≤ ∆/2
Note that
ࢼି ൌ
-1
EE315B - Chapter 8
B. Murmann
23
Tolerable Error (β = 22/3) 1
k=0
1
2
3
4
Tolerable Error
x ∆/2
0
-1
B. Murmann
EE315B - Chapter 8
24
ൌઢ
First Hardware Implementation
Z. Boyacigiller, B. Weir, and P. Bradshaw, “An error-correcting 14b/20µs CMOS A/D converter,” in ISSCC Dig. Techn. Papers, Feb. 1981, pp. 62–63.
B. Murmann
EE315B - Chapter 8
25
Other Ways to Introduce Redundancy •
Radix = 2, but extra comparators – T. C. Verster, “A Method to Increase the Accuracy of FastSerial-Parallel Analog-to-Digital Converters,” IEEE Trans. on Electronic Computers, vol. EC-13, no. 4, pp. 471–473, Aug. 1964.
•
Radix = 2, but extra cycles – V. Giannini et al., “An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS,” in ISSCC Dig. Techn. Papers, Feb. 2008, pp. 238–239. – C.-C. Liu et al., “A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in ISSCC Dig. Techn. Papers, 2010, pp. 386–387.
B. Murmann
EE315B - Chapter 8
26
SAR ADC with Redundant Comparator +ok Σ
x Σ
Σ
-
+. ࢞ > ࢞ + ࢈ = ቐ−. ࢞ ≤ ࢞ − ࢋ࢙ࢋ
Σ
2-1
1
-ok
b0 1
b1
b2
2-1
= ൞
Register
2-2
ା
<− ࢋ࢙ࢋ
x
Σ
R. Vitek et al., “A 0.015mm2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correction,” in Proc. IEEE Custom Integrated Circuits Conference, Sep. 2012, pp. 1–4.
EE315B - Chapter 8
B. Murmann
27
Normal Operation 1
k=0
1
2
3
+o1 x
+o0
-o1
x̂
0 -o0
-1
B. Murmann
EE315B - Chapter 8
28
Error in First Decision k=0
1
x
1
2
3
x̂
+o0 +o1
0 -o1 -o0
-1
EE315B - Chapter 8
B. Murmann
29
SAR ADC with Redundant Step x
Σ
Σ
-
Σ
-
2-1
1 b0
-
2-2 b1
b2
2-1
1
bk
b3
2-2
c
Σ x
Register
= ܋ቐ+ઢ −ઢ
࢈ ≠ ࢈ ࢈ = ࢈ = +. ࢈ = ࢈ = −.
V. Giannini et al., “An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS,” in ISSCC Dig. Techn. Papers, Feb. 2008, pp. 238–239.
B. Murmann
EE315B - Chapter 8
30
Normal Operation 1
k=0
x 0
1
2
3
4
x̂
Characteristic crossing
-1
EE315B - Chapter 8
B. Murmann
31
Error in First Decision 1
k=0
1
2
x 0
3
4
x̂
-1
B. Murmann
EE315B - Chapter 8
32
Redundant Step – Alternate Method x
Σ
Σ
-
-
2-1
1 b0 1
Σ
bk -
2-1 b1
b1R
2-1
2-1
b2
Register
2-2
Σ x
C.-C. Liu et al., “A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in ISSCC Dig. Techn. Papers, Feb. 2010, pp. 386–387.
EE315B - Chapter 8
B. Murmann
33
Extra Levels •
The addition of the redundant step provides extra levels that help counter errors in previous decisions
b1R + b2 b2
+0.25+0.125 = 0.375
+0.125
+0.25-0.125 = +0.125
-0.125
-0.25+0.125 = -0.125 -0.25-0.125 = -0.375
B. Murmann
EE315B - Chapter 8
34
Normal Operation 1
k=0
1
2
2R
3
x 0
x̂
-1
EE315B - Chapter 8
B. Murmann
35
Error in First Decision 1
k=0
1
2
x 0
2R
3
x̂
-1
B. Murmann
EE315B - Chapter 8
36
Potential Speed Benefit of Using Redundancy
T. Ogawa et al., IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Feb. 2010.
•
Benefit is clearly significant at high resolution – However, one must carefully evaluate if redundancy helps significantly at low resolutions (e.g. 6-8 bits)
B. Murmann
EE315B - Chapter 8
37
Metastability in an Asynchronous SAR
Worst case input is near ±1/6 VFS
[Chen, JSSC 12/2006]
B. Murmann
EE315B - Chapter 8
38
Example: 8-bit SAR (1) • There are seven “easy” decisions, and one “hard” decision • It can be shown that the sum of the easy decisions will take anywhere between 25-33τ, depending on the input • For the hard decision, the input is within ±1LSB, and we can assume that it is uniformly distributed PDF
ܲ௧ = -LSB
ݒௗ, ܤܵܮ
+LSB ±vod0,min
ݐௗ ܸ ܸ 2 = ln = ln ≅ ln ߬ ݒௗ, ܲ௧ ⋅ ܤܵܮ ܲ௧ EE315B - Chapter 8
B. Murmann
39
Example: 8-bit SAR (2) Number of time constants to be allocated for the hard decision, given a desired metastability rate (B=8) 60
50
thard/τ
40
30
20
10
-20
10
-15
-10
10
10
10
-5
P meta B. Murmann
EE315B - Chapter 8
40
Example: 8-bit SAR (3) •
Continue using the following assumptions (design and technology dependent) – Total cycle time Ts = 1ns (1GS/s) – Sampling window = Ts/8 – Sum of DAC settling times = Ts/3 – Sum of logic delays = Ts/6
•
The time available for regeneration is treg,tot = (3/8)Ts = 375ps
•
The metastability rate estimate as a function of τ is
௧ೌೝ 2 eି ఛ
P୫ୣ୲ୟ ≅
ି
=2 e
௧ೝ, ି௧ೌೞ ఛ
ି
≅2 e
௧ೝ, ି(ଶହ…ଷଷ)ఛ ఛ
EE315B - Chapter 8
B. Murmann
41
Example: 8-bit SAR (4) 0
10
teasy=33τ teasy=25τ
-5
10
Pmeta
-10
10
-15
10
-20
10
4
5
6
7
8
9
τ [ps]
•
Incredibly steep tradeoff fast comparator is key
B. Murmann
EE315B - Chapter 8
42
Comparator Reset • •
Fast reset is just as as important as fast regeneration The design below ping-pongs between two comparators to increase the available reset time
[Kull, ISSCC 2013]
B. Murmann
EE315B - Chapter 8
43
Aside: Counter/Single-Slope ADC [Harpe, ASSCC 2010]
•
One of the oldest ADC architectures
•
Simply measure time it takes for a ramp to reach input voltage
•
Ramp can be generated using a counter + DAC or current source+capacitor
•
Slow, because counter range increases exponentially with bitresolution
B. Murmann
EE315B - Chapter 8
44
Pipeline ADCs
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
B. Murmann
EE315B - Chapter 9
1
Outline •
Background – History and state-of the art performance – Derivation from SAR architecture
•
Pipeline ADC basics – Ideal block diagram and operation, impact of block nonidealities
•
Ways to deal with nonidealities – Redundancy, calibration
•
CMOS implementation details – Stage scaling, MDAC design
•
Architectural options – OTA sharing, SHA-less front-end
•
Research topics
B. Murmann
EE315B - Chapter 9
2
Pipeline ADCs – An Old Idea (1956)
B.D. Smith, “An Unusual Electronic Analog-Digital Conversion Method,” IRE Transactions on Instrumentation, vol. PGI-5, pp. 155-160, June 1956. EE315B - Chapter 9
B. Murmann
3
Today’s Pipeline ADC Performance Range Data: http://www.stanford.edu/~murmann/adcsurvey.html
10
Flash Folding Two-Step Pipeline
10
10
SAR Other 1000fs
in,hf
[Hz]
∆Σ 8
f
100fs 10
10
rms
rms
Jitter
Jitter
6
4
20
30
40
50
60
70 80 SNDR [dB]
90
100
110
120
hf
B. Murmann
EE315B - Chapter 9
4
SAR ADC
x
bk Σ
Σ
-
Σ
-
β-1
1
β-2
b0
b1
b2
β-1
1
-
b3
β-2
Register
β-3 Output x
Σ
EE315B - Chapter 9
B. Murmann
5
SAR Pipeline (1) β
x Σ
Σ
-
b0 1
β-2
β Σ
-
b1
-
b2
β-1
β-2
b3
Register
β-3 Output x
Σ
B. Murmann
bk
EE315B - Chapter 9
6
SAR Pipeline (2) β
x Σ
β Σ
-
b0
bk Σ
-
b1
b2
β-1
1
-
b3
β-2
Register
β-3 Output x
Σ
EE315B - Chapter 9
B. Murmann
7
SAR Pipeline (3) β
x Σ
β Σ
-
b1
b0 1
Σ
-
-
b2
β-1
β-2 Σ
B. Murmann
EE315B - Chapter 9
b3 β-3 Output x
8
Observation •
Pipeline and SAR ADCs are mathematically equivalent (considering ideal components)
•
Therefore, not surprisingly, all variants of redundancy can also be incorporated in a pipeline ADC – It is just less obvious, and usually explained quite differently – More later…
EE315B - Chapter 9
B. Murmann
9
General Pipeline ADC Block Diagram Align & Combine Bits Dout Vin SHA
Stage 1
Stage n-1
Vin1
G11 G ADC
Vres1
Stage n
Each stage contains a T/H (not shown)
DAC D1
B. Murmann
EE315B - Chapter 9
10
Concurrent Stage Operation CLK
Align & Combine Bits D
V SHA
Stage 1
Stage 2
Stage 3
ACQUIRE
CONVERT
ACQUIRE
CONVERT
BUFFER
ACQUIRE
CONVERT
ACQUIRE
•
Stages operate on the input signal like a shift register
•
New output data every clock cycle, but each stage introduces ½ clock cycle latency
B. Murmann
EE315B - Chapter 9
11
Pipelining – An Old Idea
B. Murmann
EE315B - Chapter 9
12
Data Alignment
•
Digital shift register aligns sub-conversion results in time
•
Digital output is taken as weighted sum of stage bits
B. Murmann
EE315B - Chapter 9
13
Latency
[Analog Devices, AD9226 Data Sheet]
B. Murmann
EE315B - Chapter 9
14
Pipeline ADC Characteristics •
Number of components grows linearly with resolution – Unlike flash ADC, where components ~ 2B
•
Pipeline ADC trades latency for conversion speed – Throughput limited by speed of one stage • Enables high-speed operation
– Latency can be an issue in some applications • E.g. in feedback control loops
•
Pipelining only possible with good analog "memory elements" – Calls for implementation in CMOS using switched-capacitor circuits
B. Murmann
EE315B - Chapter 9
15
Stage Analysis • Ignore timing/clock delays for simplicity
D = Q(Vin )
B. Murmann
EE315B - Chapter 9
Vres = G ⋅ [Vin − Vdac ]
16
Unity Gain Quantizer Model
±
B. Murmann
1 1 2 LSB = ± 2 2 2B
EE315B - Chapter 9
17
Stage Model with Ideal DAC
D = Vin + εq
•
Vres = −G ⋅ εq
Residue of pipeline stage (Vres) is equal to (-gain) times subADC quantization error
B. Murmann
EE315B - Chapter 9
18
"Residue Plot" (2-bit Sub-ADC)
{-3/4, -1/4, 1/4, 3/4}
Sub-ADC Decision Levels B. Murmann
EE315B - Chapter 9
19
Pipeline Decomposition •
Often convenient to look at pipeline as single stage plus backend ADC
B. Murmann
EE315B - Chapter 9
20
Resulting Model res
in 1
qb
q out
b
G Dout = Vin + εq 1 − Gd
εqb + Gd
With Gd=G B. Murmann
EE315B - Chapter 9
21
Canonical Extension
εq( n −1) εqn G( n −1) G εq 2 G2 Dout = Vin + εq1 1 − 1 + 1− + n −1 1− + ... + n − 2 Gd( n −1) Gd 1 Gd 1 Gd 2 G G
∏
dj
j =1
∏
•
First stage has most stringent precision requirements
•
Note that above model assumes that all stages use same reference voltage (same full scale range) – This is true for most designs, one exception is [Limotyrakis 2005]
B. Murmann
EE315B - Chapter 9
dj
j =1
22
General Result – Ideal Pipeline ADC • With ideal DACs and ideal digital weights (Gdj=Gj)
εqn
Dout = Vin + n −1
n −1
⇒
BADC = Bn + ∑ log 2G j j =1
∏G j j =1
• The only error in Dout is that of last quantizer, divided by aggregate gain • Aggregate ADC resolution is independent of sub-ADC resolutions in stage 1...n-1 (!) • Makes sense to define "effective" resolution of jth stage as Rj=log2(Gj) B. Murmann
EE315B - Chapter 9
23
Questions •
How to pick stage gain G for a given sub-ADC resolution?
•
Impact and compensation of nonidealities? – Sub-ADC errors – Amplifier offset – Amplifier gain error – Sub-DAC error
•
Begin to explore these questions using a simple example – First stage with 2-bit sub-ADC, followed by 2-bit backend
B. Murmann
EE315B - Chapter 9
24
Upper Bound for Stage Gain Vin
Vres
G1 G
Σ
Σ
Σ
εqb
D
Db
εq B
{-1/2 … 1/2B} +1
G/2B Vres
2G/2B
2
-G/2B -1 -1
Dout = Vin +
0 Vin
εqb G
+1
εqb
Grows out of ±½ LSB bounds for G>2B EE315B - Chapter 9
B. Murmann
25
Issue with G=2B in
res 1
qb b q B
B
Overrange! res
qb in
•
Any error in sub-ADC decision levels will overload backend ADC and thereby deteriorate ADC transfer function
B. Murmann
EE315B - Chapter 9
26
Idea #1: G slightly less than 2B
•
Effective stage resolution can be non-integer (R=log2G) – E.g. R = log23.2 = 1.68 bits
•
See e.g. [Karanicolas 1993]
B. Murmann
EE315B - Chapter 9
27
Idea #2: G < 2B, but Power of Two
•
Effective stage resolution is an integer – E.g. R = log22 = 1 = B-1 – Digital hardware requires only a few adders, no need to implement fractional weights (see appendix)
•
See e.g. [Mehr 2000]
B. Murmann
EE315B - Chapter 9
28
Idea #3: G=2B, Extended Backend Range
• No redundancy in stage with errors • Extra decision levels in succeeding stage used to bring residue "back into the box" •
See e.g. [Opris 1998] EE315B - Chapter 9
B. Murmann
29
Variant of Idea #2: "1.5-bit stage"
•
Sub-ADC decision levels placed to minimize comparator count
•
Can accommodate errors up to ±¼
•
B = log2(2+1) = 1.589 (sub-ADC resolution)
•
R = log22 = 1 (effective stage resolution)
•
See e.g. [Lewis 1992]
B. Murmann
EE315B - Chapter 9
30
Summary on Sub-ADC Redundancy •
We can tolerate sub-ADC errors as long as – The residue stays "inside the box", or – Another stage downstream returns the residue "into the box" before it reaches last quantizer
•
This result applies to any stage in an n-stage pipeline – Can always decompose pipeline into single stage + backend ADC
•
In literature, sub-ADC redundancy schemes are often called "digital correction" – a misnomer in my opinion
•
There is no explicit error correction! – Sub-ADC errors are absorbed in the same way as their inherent quantization error • As long as there is no overranging… EE315B - Chapter 9
B. Murmann
31
Amplifier Offset Push
•
Amplifier offset can be referred toward stage input and results in – Global offset • Usually no problem, unless "absolute ADC accuracy" is required
– Sub-ADC offset • Easily accommodated through redundancy B. Murmann
EE315B - Chapter 9
32
Gain Errors
εqn G +∆ Dout = Vin + εq1 1 − 1 + ... + n −1 Gd 1 G
∏
dj
j =1
•
Want to make Gd1 = G1+∆ EE315B - Chapter 9
B. Murmann
33
Digital Gain Calibration (1) •
Error in analog gain is not a problem as long as "digital gain term" is adjusted appropriately
•
Problem – Need to measure analog gain precisely
•
Example – Digital calibration of a 1-bit first stage with 1-bit redundancy (R=1, B=2)
•
Note – Even if all Gdj are perfectly adjusted to reflect the analog gains, the ADC will have nonzero DNL and INL, bounded by ±0.5LSB. This can be explained by the fact that the residue transitions may not correspond to integer multiples of the backend-LSB. This can cause non-uniformity in the ADC transfer function (DNL, INL) and also nonmonotonicity (see [Markus, 2005]). – In case this cannot be tolerated • •
B. Murmann
Add redundant bits to ADC backend (after combining all bits, final result can be truncated back) Calibrate analog gain terms
EE315B - Chapter 9
34
Digital Gain Calibration (2)
Vres = G ⋅ [Vin − Vdac ] Db = Vres + εqb
EE315B - Chapter 9
B. Murmann
35
Digital Gain Calibration (3)
Step1: Step2:
1) Db( 1) = G ⋅ [Vin + 0.25] + ε(qb 2) Db( 2 ) = G ⋅ [Vin − 0.25] + ε(qb
1) 2) Db( 1) − Db( 2 ) = 0.5 ⋅ G + ε(qb − ε(qb
•
Can minimize impact of quantization error using – Averaging (thermal noise dither) – Extra backend resolution
B. Murmann
EE315B - Chapter 9
36
DAC Calibration
•
Essentially same concept as gain calibration – Step through DAC codes and use backend to measure errors
•
Store coefficients for each DAC transition in a look-up table
B. Murmann
EE315B - Chapter 9
37
Recursive Stage Calibration
•
First few stages have most stringent accuracy requirements – Errors of later stages are attenuated by aggregate gain
•
Commonly used algorithm [Karanicolas 1993] – Take ADC offline – Measure least significant stage that needs calibration first – Move to next significant stage and continue toward stage 1
B. Murmann
EE315B - Chapter 9
38
Calibration Hardware Example
[Chuang 2002]
B. Murmann
EE315B - Chapter 9
39
Alternative Schemes •
Other foreground calibration schemes – Calibrate ADC starting from first stage [Singer 2000] – Connect stages in a circular loop [Soenen 1995]
•
Background calibration – See e.g. [Ming 2001] – Makes sense primarily when calibration parameters are expected to drift • Capacitor ratios do not drift! • Background calibration is justifiable e.g. when drift in OTA open-loop gain is an issue
B. Murmann
EE315B - Chapter 9
40
Nonlinearity Compensation with Background Calibration
[Murmann 2003]
B. Murmann
EE315B - Chapter 9
41
Combining the Bits (1) •
Example1: Three 2-bit stages, no redundancy
Dout = D1 + B. Murmann
1 1 D2 + D3 4 16
EE315B - Chapter 9
42
Combining the Bits (2) D1 XX D2 XX D3 XX -----------Dout DDDDDD
• •
Only bit shifts No arithmetic circuits needed
EE315B - Chapter 9
B. Murmann
43
Combining the Bits (3) •
Example2: Three 2-bit stages, one bit redundancy in stages 1 and 2 (6-bit aggregate ADC resolution)
Vin
B1=3 R1=2
B2=3 R2=2
Stage 1
Stage 2
B3=2
Stage 3
“8 Wires“
??? “6 Wires“
Dout[5:0]
B. Murmann
EE315B - Chapter 9
44
Combining the Bits (4) Dout
1 1 = D1 + D2 + D3 4 16
B. Murmann
D1 XXX D2 XXX D3 XX -----------Dout DDDDDD
• •
Bits overlap Need adders (Still, no good reason for calling this "digital correction"...)
EE315B - Chapter 9
45
Combining the Bits (5)
•
For fractional weights (e.g. radix <2), there is no need to implement complex multipliers
•
Can still use simple bit shifts; push actual multiplication into lowresolution output – E.g. a 1x10 bit multiplication needs only one adder…
•
See e.g. [Karanicolas 1993]
B. Murmann
EE315B - Chapter 9
46
Outline •
Background – History and state-of the art performance – General idea of multi-step A/D conversion
•
Pipeline ADC basics – Ideal block diagram and operation, impact of block nonidealities
•
Ways to deal with nonidealities – Redundancy, calibration
•
CMOS implementation details – Stage scaling, MDAC design
•
Architectural options – OTA sharing, SHA-less front-end
•
Research topics EE315B - Chapter 9
B. Murmann
47
Stage Implementation
Flash ADC
"MDAC" SwitchedCapacitor Circuit
B. Murmann
EE315B - Chapter 9
48
Generic Circuit
Q
φ1:
Q = Vin ⋅ kCs
φ2 :
Q = Vres ⋅ Cf + Vrefp ⋅ mCs + Vrefn ⋅ ( k − m ) Cs
∴ − Vres =
( k − m ) Cs V kCs mCs Vin − Vrefp + refn Cf Cf Cf
= G ⋅ ( Vin − Vdac ) B. Murmann
EE315B - Chapter 9
49
Endless List of Design Parameters •
Stage resolution, stage scaling factor
•
Stage redundancy
•
Thermal noise/quantization noise ratio
•
OTA architecture – OTA sharing?
•
Switch topologies
•
Comparator architecture
•
Front-end SHA vs. SHA-less design
•
Calibration approach (if needed)
•
Time interleaving?
•
Technology and technology options (e.g. capacitors)
A very complex optimization problem!
B. Murmann
EE315B - Chapter 9
50
Thermal Noise Considerations •
Total input referred noise – Thermal noise + quantization noise – Costly to make thermal noise smaller than quantization noise
•
Example: VFS=1V, 10-bit ADC – Nquant=LSB2/12=(1V/210)2/12=(280µVrms)2 – Design for total input referred thermal noise ~280µVrms or larger, if SNR target allows
•
Total input referred thermal noise is the sum of noise in all stages – How should we distribute the total thermal noise budget among the stages? – Let's look at an example…
B. Murmann
EE315B - Chapter 9
51
Stage Scaling (1) •
Example: Pipeline using 1-bit (effective) stages (G=2)
•
Total input referred noise power 1 1 1 Ntot ∝ kT + + + ... C1 4C2 16C3
B. Murmann
EE315B - Chapter 9
52
Stage Scaling (2) C1/2 C1
Vin
C2/2 C2
Gm
C3/2 C3
Gm
Gm
1 1 1 Ntot ∝ kT + + + ... C1 4C2 16C3
• •
If we make all caps the same size, backend stages contribute very little noise Wasteful, because Power ~ Gm ~ C
EE315B - Chapter 9
B. Murmann
53
Stage Scaling (3) C1/2 C1
Vin
C2/2 C2
Gm
C3/2 C3
Gm
Gm
1 1 1 Ntot ∝ kT + + + ... C1 4C2 16C3
•
How about scaling caps down by 22=4x per stage? – Same amount of noise from every stage – All stages contribute significant noise – Noise from first few stages must be reduced – Power ~ Gm ~ C goes up!
B. Murmann
EE315B - Chapter 9
54
Stage Scaling (4)
[Cline 1996]
•
Optimum capacitior scaling lies approximately midway between these two extremes
EE315B - Chapter 9
B. Murmann
55
Shallow Optimum
[Chiu 2004]
Capacitor scaling factor = 2Rx
B. Murmann
x=1 ⇒ scaling exactly by stage gain
EE315B - Chapter 9
56
Practical Approach to Stage Scaling •
Start by assuming caps are scaled precisely by stage gain – E.g. for 1-bit effective stages: C/2 C
Vin
C/4 C/2
Gm
C/8 C/4
Gm
Gm
•
Refine using first pass circuit information & Excel spreadsheet – Use estimates of OTA power, parasitics, minimum feasible sampling capacitance etc.
•
Or, buy a circuit optimization tool…
B. Murmann
EE315B - Chapter 9
57
Stage Scaling Examples (1)
[Cline 1996] B. Murmann
EE315B - Chapter 9
58
Stage Scaling Examples (2) [Ishii 2005]
EE315B - Chapter 9
B. Murmann
59
How Many Bits Per Stage? •
Low per-stage resolution (e.g. 1-bit effective) – Need many stages + OTAs have small closed loop gain, large feedback factor • High speed
•
High per-stage resolution (e.g. 3-bit effective) + Fewer stages – OTAs can be power hungry, especially at high speed – Significant loading from flash-ADC
•
Qualitative conclusion – Use low per-stage resolution for very high speed designs – Try higher resolution stages when power efficiency is most important constraint
B. Murmann
EE315B - Chapter 9
60
Power Tradeoff is Fairly Flat!
[Chiu 2004] η = parasitic cap at output/total sampling cap in each stage (junctions, wires, switches, …)
•
ADC power varies by only ~2x across different stage resolutions! EE315B - Chapter 9
B. Murmann
61
Examples Reference
[Yoshioka, 2007] [Jeon, 2007]
[Loloee 2002]
[Bogner 2006]
Technology
90nm
90nm
0.18um
0.13um
Bits
10
10
12
14
Bits/Stage
1-1-1-1-1-1-1-3
2-2-2-4
1-1-1-1-1-1-1-1-1-1-2
3-3-2-2-4
SNDR [dB]
~56
~54
~65
~64
Speed [MS/s]
80
30
80
100
Power [mW]
13.3
4.7
260
224
mW/MS/s
0.17
0.16
3.25
2.24
•
Low power is possible for a wide range of architectures!
B. Murmann
EE315B - Chapter 9
62
Re-Cap •
Choosing the "optimum" per-stage resolution and stage scaling scheme is a non-trivial task – But – optima are shallow!
•
Quality of transistor level design and optimization is at least as important (if not more important than) architectural optimization…
•
Next, look at circuit design details – Assume we're trying to build a 10-bit pipeline • • • •
Recent technology, feature size ~0.18µm or smaller Moderate to high-speed ~100MS/s 1-bit effective/stage, using "1.5-bit" stage topology Dedicated front-end SHA
EE315B - Chapter 9
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63
1.5-Bit Stage Implementation [Abo 1999] ([Lewis 1992])
•
Cf is used as sampling cap during acquisition phase, as feedback cap in redistribution phase – Helps improve feedback factor (max. 1/3 → max. 1/2)
B. Murmann
EE315B - Chapter 9
64
Residue Plot
[Abo 1999]
B. Murmann
EE315B - Chapter 9
65
Stage 1 Matching Requirements
∝
•
Cs ∆C ≅ 1+ Cf C
Error in residue transition must be accurate to within a fraction of 9-bit backend LSB – Typically want ∆C/C ~0.1% or better
B. Murmann
EE315B - Chapter 9
66
Capacitor Matching •
0.1% "easily" achievable in current technologies – Even with metal sandwich caps, see e.g. [Verma 2006] • Beware of metal density related issues, "copper dishing"
– For MIMCap matching data see e.g. [Diaz 2003] •
What if we needed much higher resolution than 10 bits? – Digital calibration – Multi-bit first stage • Each extra bit resolved in the first stage alleviates precision requirements on residue transition by 2x • For fixed capacitor matching, can show that each (effective) bit moved into the first stage – Improves DNL by 2x – Improves INL by sqrt(2)x
• Multi-bit examples: [Singer 1996] [Kelly 2001] [Lee 2007]
EE315B - Chapter 9
B. Murmann
67
Typical Reference Generator [Brooks 1994]
External decoupling caps provide dynamic currents ⇒ Low power reference buffer
B. Murmann
EE315B - Chapter 9
68
Comparators •
Can tolerate large offsets and large noise with appropriate redundancy
•
Consume negligible power in a good design – 50-100µW or less per comparator
•
Lots of implementation options – Resistive/capacitive reference generation – Different pre-amp/latch topologies – …
EE315B - Chapter 9
B. Murmann
69
Comparator Examples Vin
[Chiu 2004]
[Mehr 2000] B. Murmann
EE315B - Chapter 9
70
OTA Design Considerations •
Static amplifier error = 1/(DC Loop Gain) – E.g. for 0.1% accuracy in first stage of 10-bit ADC, need loop gain > 60dB
•
Dynamic settling error – Typically want to settle outputs to ~1/8 LSB accuracy within 1/2 clock cycle
•
Thermal noise – Size capacitors to satisfy kT/C noise requirement
•
Start by picking an OTA topology that will deliver sufficient gain – Or think about ways to compensate finite gain error…
•
General references on OTA design – [Boser 2005], [Murmann, EE315A]
EE315B - Chapter 9
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71
Two-Stage Folded Cascode OTA 1V
[Ishii 2005] ~0.5V (1Vpp,diff)
•
Works down to VDD=1V with reasonable output swing
•
Gain ~ (gmro)3 ~ 103 = 60dB
•
Use gain boosting to achieve larger gain
B. Murmann
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72
How Fast Can We Go? (1) •
Non-dominant pole in two-stage amplifier hard to move past fT/5
•
For 73 degrees phase margin (optimum for fast settling), loop crossover frequency is 1/3 of non-dominant pole frequency
•
Settling linearly to 0.1% precision takes 7 loop time constants; typically budget ~10 time constants
•
Ideally, we'd have 1/2 clock cycle to settle linearly, but there is some time needed for slewing and non-overlap clock timing – Assume 60% of half cycle is available for linear settling
•
In summary
fCLK ,max =
fT 1 f 1 ⋅ 2π ⋅ 0.5 ⋅ 0.6 = T 5 3 10 80
EE315B - Chapter 9
B. Murmann
73
How Fast Can We Go? (2)
•
Technology
NMOS fT (at moderate VGS-Vt ~150mV)
fCLK,max = fT/80
0.35um
10GHz
125 MHz
0.18um
30GHz
375 MHz
90nm
90GHz
1.125GHz (?)
Sampling speeds of 200-300MHz are "easily" achievable in today's technologies – fT is no longer a showstopper – Speed ultimately constrained by power, power efficiency and/or clock jitter
B. Murmann
EE315B - Chapter 9
74
Switches [Ishii 2005]
•
Make switch RC ~ 10 times faster than OTA – Avoids speed degradation – Minimizes switch noise contribution • See e.g. [Schreier 2005]
– Avoids stability issues due to poles in feedback network •
Three choices for switches – Single N or P device – Transmission gate – Bootstrapped NMOS • For high swing nodes that require constant Ron
EE315B - Chapter 9
B. Murmann
75
Front-End SHA Need constant RON here to minimize signal dependent charge injection from S1N, S1P
Minimize Jitter!
S1P S1N
[Ishii 2005]
B. Murmann
EE315B - Chapter 9
76
Total Integrated OTA Noise (1) Cf
N1 = 1 +
g m11 + g m 31 ≅ 2...4 g m1
N2 = 1 +
g m 61 ≅2 g m51
Cs Cc
1 kT kT 2 Vod = 2 ⋅ γ ⋅ N1 + 2( γ ⋅ N2 + 1) β Cc CLtot Stage 1
β=
Cf Cf + Cs + Cgs1
Stage 2
ignore in first cut design
CLtot = CL + (1 − β ) Cf + Cparasitic EE315B - Chapter 9
B. Murmann
77
Total Integrated OTA Noise (2) •
Assuming γ=1, N1=N2=2 1 kT kT 2 Vod =4 ⋅ +6 β Cc CLtot
•
OTA noise partitioning problem – How should we split noise between stage1 and stage2 terms?
•
In this design example we'll use a 2/3, 1/3 split – This is yet another design/optimization parameter
•
With this assumption, we have 2 Vod = 18
B. Murmann
kT CLtot
Cc =
EE315B - Chapter 9
CLtot 3β
78
Stage 1 Noise
Cs2
Cs1=C1P+C2P
β=
Cs1 / 2 1 ≅ Cs1 + Cgs1 3
2 Vod ,1 = 18
1C CLtot = Cs 2 + 1 − s1 3 2
Vid2 ,1 =
kT Cs 2 + Cs1 / 3
kT 2 Cs 2 + Cs1 / 3
18 2
EE315B - Chapter 9
B. Murmann
79
SHA Noise β=
Cs 0 1 ≅ Cs 0 + Cgs1 2
Cs1
1C CLtot = Cs1 + 1 − s 0 2 2 Cs0
Design choice: Cs0 = Cs1 From sample phase (φ1)
2 2 Vod ,0 = Vid ,0 = 18
B. Murmann
kT kT kT + ≅ 16 Cs1 + Cs 0 / 4 Cs 0 Cs1
EE315B - Chapter 9
80
Noise Budgeting •
Total input referred noise budget, assuming VFS,diff=1V – Nthermal = Nquant=LSB2/12=(1V/210)2/12=(280µVrms)2
•
Reasonable "first cut" partitioning of input referred noise – SHA → 1/2 – Stage 1 → 1/4 – All remaining stages → 1/4 Vid2 ,0 = 16 Vid2 ,1 =
kT 1 2 = ( 280µVrms ) ⇒ Cs1 = 1.66 pF Cs1 2
9 kT 1 2 = ( 280µVrms ) ⇒ Cs 2 = 0.38 pF 2 Cs 2 + Cs1 / 3 4
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81
Capacitor Sizes
•
Cs0
1.66pF
Cs1
1.66pF
Cs2
0.38pF
Cs3
190fF
Cs4
85fF
Cs5
42.fF (minimum)
…
…
Cs10
42.fF (minimum)
/2 /2 /2
Now refine these numbers using simulation and Excel spreadsheet – Iterate over assumptions/design choices to optimize design
B. Murmann
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82
Reality Check [Honda 2007]
•
Not too far off from a practical design…
B. Murmann
EE315B - Chapter 9
83
Amplifier Sharing (1) [Min 2003]
•
B. Murmann
EE315B - Chapter 9
Limited power savings because amplifiers have different specs
84
Amplifier Sharing (2) [Kurose 2006]
•
Sharing of amplifiers is most efficiently done in a pair of converters that process I/Q signals
B. Murmann
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85
SHA-Less Architectures (1) •
Motivation – SHA can burn up to 1/3 of total ADC power
•
Removing front-end SHA creates acquisition timing mismatch issue between first stage MDAC & Flash
Sampler (MDAC)
[Chiu 2004]
B. Murmann
EE315B - Chapter 9
86
SHA-Less Architectures (2) •
Strategies – Use first stage with large redundancy; this can help absorb fairly large skew errors – Try to match sampling sub-ADC/MDAC networks • Bandwidth and clock timing
[Mehr 2000]
B. Murmann
EE315B - Chapter 9
87
Pipelined SAR
[Lee, JSSC, April 2011]
B. Murmann
EE315B - Chapter 9
88
Pipeline Cyclic ADC (1) β
x Σ
β Σ
-
Σ
-
b1
b0
b2
β-1
1
-
b3
β-2
β-3 Output x
Σ
EE315B - Chapter 9
B. Murmann
89
Pipeline Cyclic ADC (2) β Σ
x
-
Register b0 1
b1
b2
-1
-2
β
β
Σ
B. Murmann
EE315B - Chapter 9
b3 -3
β
Output x
90
Implementation Example
φ1 Vo1
C Vo1 = 1 + 5 Vo 2 C6
[Erdogan et al. JSSC 12/99]
φ2
Vo2
(
Vo 2 = Vip ± Vref
) CC4 3
EE315B - Chapter 9
B. Murmann
91
Discussion •
Advantages – Area efficient • Typically only one or two switched capacitor stages plus comparator
– Easy to calibrate • Need to measure only one coefficient (capacitor ratio)
•
Disadvantages – Slow • Need many clock cycles for a single conversion
– Sub-optimal power efficiency • Cannot scale stages like in a pipeline ADC • Noise and accuracy requirements decrease from MSB to LSB cycle, but invested circuit energy per cycle is (usually) constant
B. Murmann
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92
Selected References (1) •
General – S. Kawahito, "Low-Power Design of Pipeline A/D Converters," Proc. CICC, pp. 505-512, Sep. 2006.
•
Redundancy & Calibration – S. H. Lewis et al., "A 10-b 20-Msample/s analog-to-digital converter," IEEE JSSC, pp. 351-358, Mar. 1992. – A. N. Karanicolas et al. "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Of Solid-State Circuits, pp. 1207-1215, Dec. 1993. – E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs," IEEE TCAS II, pp. 143-153, Mar. 1995. – I. E. Opris et al., "A single-ended 12-bit 20 MSample/s self-calibrating pipeline A/D converter," IEEE JSSC, pp. 1898-1903, Dec. 1998. – L. Singer et al., "A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz," ISSCC Dig. Techn. Papers, pp. 38-39, Feb. 2000. – I. Mehr et al., "A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC," IEEE JSSC, pp. 318-325, Mar. 2000. – J. Ming et al., "An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration," IEEE JSSC, pp. 1489-1497, Oct. 2001. – S.-Y. Chuang et al., "A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined A/D Converter," IEEE JSSC, pp. 674-683, Jun. 2002. – J. Markus et al., "On the monotonicity and linearity of ideal radix-based A/D converters," IEEE Trans. Instr. and Measurement, pp. 2454-2457, Dec. 2005. EE315B - Chapter 9
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Selected References (2) •
Implementation – T. Cho, "Low-Power Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architecures, PhD Dissertation, UC Berkeley, 1995, http://kabuki.eecs.berkeley.edu/~tcho/Thesis1.pdf. – L. A. Singer at al., "A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter," VLSI Circuit Symposium, pp. 94-95, Jun. 1996. – A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Dissertation, UC Berkeley, 1999, http://kabuki.eecs.berkeley.edu/~abo/abothesis.pdf. – D. Kelly et al., "A 3V 340mW 14b 75MSPS CMOS ADC with 85dB SFDR at Nyquist," ISSCC Dig. Techn. Papers, pp. 134-135, Feb. 2001. – A. Loloee, et. al, “A 12b 80-MSs Pipelined ADC Core with 190 mW Consumption from 3 V in 0.18-um, Digital CMOS”, Proc. ESSCIRC, pp. 467-469, 2002 – B.-M. Min et al., "A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC," IEEE JSSC, pp. 2031-2039, Dec. 2003. – Y. Chiu, et al., "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” IEEE JSSC, pp. 2139-2151, Dec. 2004. – S. Limotyrakis et al., "A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC," IEEE JSSC, pp. 1057-1067, May 2005. – T. N. Andersen et al., "A Cost-Efficient High-Speed 12-bit Pipeline ADC in 0.18-um Digital CMOS," IEEE JSSC, pp. 1506-1513, Jul 2005.
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Selected References (3) – P. Bogner et al., "A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13um CMOS," ISSCC Dig. Techn. Papers, pp. 832-833, Feb. 2006. – D. Kurose et al., "55-mW 200-MSPS 10-bit Pipeline ADCs for Wireless Receivers," IEEE JSSC, pp. 1589-1595, Jul. 2006. – S. Bardsley et al., "A 100-dB SFDR 80-MSPS 14-Bit 0.35um BiCMOS Pipeline ADC," IEEE JSSC, pp. 2144-2153, Sep. 2006. – A. M. A. Ali et al, "A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter," IEEE JSSC, pp. 1846-1855, Aug. 2006. – S. K. Gupta, "A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture," IEEE JSSC, 2650-2657, Dec. 2006. – M. Yoshioka et al., "A 0.8V 10b 80MS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing," ISSCC Dig. Techn. Papers, pp. 452453, Feb. 2007. – Y.-D. Jeon et al., "A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS," ISSCC Dig. Techn. Papers, pp. 456-457, Feb. 2007. – K.-H. Lee et al., "Calibration-free 14b 70MS/s 0.13um CMOS pipeline A/D converters based on highmatching 3D symmetric capacitors," Electronics Letters, pp. 35-36, Mar. 15, 2007. – K. Honda et al., "A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques," IEEE JSSC, pp. 757-765, Apr. 2007. EE315B - Chapter 9
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Selected References (4) •
Per-Stage Resolution and Stage Scaling – D. W. Cline, "Noise, Speed, and Power Tradeoffs in Pipelined Analog to Digital Converters", PhD Dissertation, UC Berkeley, November, 1995, http://kabuki.eecs.berkeley.edu/~cline/thesis/thesis.pdf. – D. W. Cline et al., "A power optimized 13-b 5 MSamples/s pipelined analogto-digital converter in 1.2um CMOS," IEEE JSSC, Mar. 1996 – Y. Chiu, "High-Performance Pipeline A/D Converter Design in DeepSubmicron CMOS," PhD Dissertation, UC Berkeley, 2004. – H. Ishii et al., "A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS," Proc. CICC, pp. 395-398, Sep. 2005.
•
OTA Design, Noise – B. E. Boser, "Analog Circuit Design with Submicron Transistors," Presentation at IEEE Santa Clara Valley, May 19, 2005, http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm – R. Schreier et al., "Design-oriented estimation of thermal noise in switchedcapacitor circuits," IEEE TCAS I, pp. 2358-2368, Nov. 2005. – B. Murmann, "Thermal Noise in Track-and-Hold Circuits: Analysis and Simulation Techniques," IEEE Solid-State Circuits Magazine, vol.4, no.2, pp. 46-54, June 2012.
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Selected References (5) •
Capacitor Matching Data – C. H. Diaz et al., "CMOS technology for MS/RF SoC," IEEE Trans. Electron Devices, pp. 557-566, Mar. 2003. – A. Verma et al., "Frequency-Based Measurement of Mismatches Between Small Capacitors," Proc. CICC, pp. 481-484, Sep. 2006. – V. Tripathi and B. Murmann, "Mismatch Characterization of Small Metal Fringe Capacitors," CICC 2013.
•
Reference Generator – T. L. Brooks et al., "A low-power differential CMOS bandgap reference," ISSCC Dig. Techn. Papers, pp. 248-249, Feb. 1994.
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Time Interleaving
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
EE315B - Chapter 10
B. Murmann
1
Time-Interleaved ADC M times increased throughput!
[Ken Poulton]
M
[W. Black and D. Hodges, JSSC, Dec. 1980]
B. Murmann
EE315B - Chapter 10
2
Typical Timing
Sampling clocks of each ADC
•
Each ADC samples for 1/Mth of the period
•
Still need very high “acquisition bandwidth” in each ADC slice – No free lunch… EE315B - Chapter 10
B. Murmann
3
Why Time Interleaving? 70 TI SAR TI Pipeline TI Flash Other
SNDRHF [dB]
60 50 40 30 20 10 8 10
9
10
10
10
11
10
Sampling Rate [Hz] B. Murmann, "ADC Performance Survey 1997-2013," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html B. Murmann
EE315B - Chapter 10
4
How Many Channels? [El-Chammas, PhD Thesis, Stanford University, 2010]
Feasible Solutions
Secondary factors dominate the power (e.g. flash resistor ladder)
Shallow power minimum
•
A complex optimization problem! – Luckily, first order analyses show that the optimum is shallow EE315B - Chapter 10
B. Murmann
5
Time Interleaving Errors τ0 o0 G0
ADC0 Ts+τ1 o1
x(t)
ADC1
G1
y[n]
(N-1)Ts+τN-1 oN-1 GN-1
Gain
B. Murmann
ADCN-1
Offset
EE315B - Chapter 10
Timing Skew
6
Offset Errors
[Ken Poulton]
Signal independent noise pattern B. Murmann
EE315B - Chapter 10
7
Impact of Offset Errors
[Gustavsson, p.262]
σOS/FS
•
E.g. FS=1V, σOS=1mV ⇒ ENOB~9bits!
B. Murmann
EE315B - Chapter 10
8
Gain Errors
[Ken Poulton]
Very similar to amplitude modulation B. Murmann
EE315B - Chapter 10
9
Impact of Gain Errors
[Gustavsson, p.266]
σGain
•
E.g. σGain=0.1% ⇒ ENOB~10bits
B. Murmann
EE315B - Chapter 10
10
Timing Errors Very similar to PM, jitter
[Ken Poulton]
•
Can be analyzed like jitter, using curvature of signal autocorrelation (see earlier discussion) – Only difference is that a factor of N/N-1 shows up, since only N-1 channels are skewed – See [El-Chammas & Murmann, IEEE TCAS 5/2009] B. Murmann
EE315B - Chapter 10
11
Impact of Timing Errors [Gustavsson, p.267]
•
Above chart is for M=4 channels
•
E.g. fin=100MHz, phase skew=3ps ⇒ ENOB~9bits!
B. Murmann
EE315B - Chapter 10
12
Compensation of Interleaving Errors •
Gain and offset – Several relatively “simple” techniques exist – Can compensate in analog and/or digital domain
•
Timing skew – Much more difficult to handle, fully digital compensation often too complex for practical designs – Popular solutions • Measure errors in digital domain, compensate via adjustable delay lines typically incur a jitter penalty • Measure errors in digital domain, compensate by skewing equalizer taps – See overview paper by B. Razavi, CICC 2012
EE315B - Chapter 10
B. Murmann
13
Digital Detection and Correction
ADC0
y0[n]
Detection
Correction
~y1[n]
y1[n]
Sub-ADC output
B. Murmann
Digital Backend
x(t) ADC1
~y0[n]
Correction
EE315B - Chapter 10
Digitally corrected sub-ADC output
14
Digital Detection and Analog Correction
B. Murmann
EE315B - Chapter 10
15
Foreground vs. Background Calibration Foreground Calibration
Background Calibration
B. Murmann
EE315B - Chapter 10
16
Example: Fully Digital Gain Error Background Cal
[Tsai, TCAS1, 2/2009]
• A similar approach can be used for digital offset compensation B. Murmann
EE315B - Chapter 10
17
Example: Foreground Analog Gain & Offset Cal gain cntrl
comp offset cntrl
G2(0) 63 comp
6
µC Calibration Logic
Interleave 0
Decoder
5-bit
8-bit Calibration DAC
vga offset cntrl
G1(0) Flash other interleave (not shown) [Verma, ISSCC 2013] B. Murmann
EE315B - Chapter 10
Coarse nonlinearity compensation in G2(0) 18
Clock Generator
Sources of Timing Skew
•
All traces and all transistors have mismatch, which can easily result in ~10ps total timing skew for a complex clock tree [A. Agarwal, CICC 2008] EE315B - Chapter 10
B. Murmann
19
Minimizing Skew by Design
[Louwsma, JSSC 4/2008]
•
Global CML master clock times the sampling instants; local phase gating for each ADC
•
Skew ~0.5ps (!)
B. Murmann
EE315B - Chapter 10
20
Hiding the Timing Skew Using a Global T/H
•
Typically not feasible in ultra-high-speed converters
•
Successfully used in moderately high-speed designs – S. Gupta et al., “A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture “, JSSC 12/2006. – B. Setterberg et al., “A 14b 2.5GS/s 8-Way-Interleaved Pipelined ADC with Background Calibration and Digital Dynamic Linearity Correction,” ISSCC 2013. EE315B - Chapter 10
B. Murmann
21
Global Bottom Plate Sampling
[Gustavsson, TCAS1, 9/2000] X
•
B. Murmann
EE315B - Chapter 10
Big issue: parasitics at node X
22
Better: Local Re-Timing & Fine Tuning 3.5ps tuning range, 250fs steps
[Kull, VLSI 2013]
B. Murmann
EE315B - Chapter 10
23
Typical Delay Cell
• Causes a penalty in supply induced jitter manageable if delay range is small
K. Poulton et al., “A 4GSample/s 8b ADC in 0.35um CMOS”, ISSCC 2002 B. Murmann
EE315B - Chapter 10
24
Delay Control via Varactor DAC
Encoder Control Bits
EE315B - Chapter 10
B. Murmann
25
Measuring the Skew Using Aux ADC Auxiliary ADC
B. Murmann
MUX
…...
……..
[El-Chammas, VLSI 2010]
EE315B - Chapter 10
26
Clocking the Aux ADC 1
t 2
t 3
t
CAL 3
2
1
t
Period of φCAL is e.g. 17/8 period of φ1 - φ8 B. Murmann
EE315B - Chapter 10
27
“Blind” Estimation of the Skew
[Haftbaradaran, CICC 2007]
•
Assuming well-behaved input signal statistics, it also possible to detect the skew “blindly”
•
Key idea: pairwise signal correlations along the array must be equal, unless there is skew
B. Murmann
EE315B - Chapter 10
28
System-Level Absorption of Skew [Tsai, TCAS1, 2/2009]
•
Split equalizer into M paths and adapt coefficients separately
•
For complex equalizers typically found in ADC-based links, one must carefully evaluate if the power overhead is justifiable
•
Can also combine this idea with analog time skew control
B. Murmann
EE315B - Chapter 10
29
Hierarchical Interleaving
[Doris, JSSC 12/2011] B. Murmann
EE315B - Chapter 10
30
Quadrature Clocking
[Doris, JSSC 12/2011]
• •
Hierarchical interleaving with 4x split in first rank Drive the samplers directly with QVCO signal – Low jitter, small phase skew (need only small tuning range, if any)
B. Murmann
EE315B - Chapter 10
31
Examples (1)
[Greshishchev, ISSCC 2010]
•
160 SAR ADCs interleaved to resolve 6 bits at 40GS/s (!)
B. Murmann
EE315B - Chapter 10
32
Examples (2) [Kull, VLSI 2013] 8 Interleaved SARs, each running at 1.1GS/s 8.8GS/s, 50mW
B. Murmann
EE315B - Chapter 10
33
Examples (2) [El-Chammas & Murmann, VLSI 2010] 8x Interleaved 5-bit Flash 12GS/s, 81mW 65nm CMOS
B. Murmann
EE315B - Chapter 10
34
Examples (3)
[Setterberg, ISSCC 2013]
• • •
14b, 2.5 GS/s ADC, 80-dB linear up to 1 GHz input Employs 2 million logic gates for digital correction Power dissipation = 24 Watts B. Murmann
EE315B - Chapter 10
35
Examples (4)
[Danesh, VLSI 2011]
• •
128 single slope ADCs interleaved to resolve 7 bits at 1GS/s Power efficient (~26mW)
B. Murmann
EE315B - Chapter 10
36
Oversampling ADCs and DACs
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
B. Murmann
EE315B - Chapter 11
1
Overview •
Oversampling A/D conversion
•
Decimation filters
•
Oversampling D/A conversion
B. Murmann
EE315B - Chapter 11
2
Recap
•
Sampling theorem fs > 2fsig ,max
•
One good reason for sampling faster ("oversampling") – Can use lower order anti-alias filter
B. Murmann
EE315B - Chapter 11
3
Anti-Alias Filtering
B. Murmann
EE315B - Chapter 11
4
Quantization Noise Ne(f)
∆2/12
fB
fs/2
•
Recall that the "noise" introduced by quantizer is evenly distributed across all frequencies – Provided that quantization error sequence is "sufficiently random"
•
Idea: Let's filter out the noise beyond f=fB!
B. Murmann
EE315B - Chapter 11
5
Digital Noise Filter (1)
f B ∆2 ⋅ f s / 2 12
•
∆2 12
Total quantization noise at digital output is reduced proportional to "oversampling ratio" M=(fs/2)/fB
B. Murmann
EE315B - Chapter 11
6
Digital Noise Filter (2) •
Increasing M by 2x, means 3-dB reduction in quantization noise power, and thus 1/2 bit increase in resolution – "1/2 bit per octave"
•
Is this useful?
•
Reality check – Want 16-bit ADC, fB=1MHz – Use oversampled 8-bit ADC with digital lowpass filter – 8-bit increase in resolution necessitates oversampling by 16 octaves fs ≥ 2 ⋅ fB ⋅ M = 2 ⋅ 1MHz ⋅ 216 ≥ 131GHz
B. Murmann
EE315B - Chapter 11
7
Noise Shaping
•
Idea: "Somehow" build an ADC that has most of its quantization noise at high frequencies
•
Key: Feedback
B. Murmann
EE315B - Chapter 11
8
Noise Shaping Using Feedback (1)
Y ( z ) = E ( z ) + A ( z ) X ( z ) − A ( z )Y ( z ) = E (z)
A(z) 1 + X (z) 1+ A ( z ) 1+ A ( z )
= E ( z ) HE ( z ) + X ( z ) H X ( z ) 123 123 Noise Transfer Function
Signal Transfer Function
EE315B - Chapter 11
B. Murmann
9
Noise Shaping Using Feedback (2) Y (z) = E (z)
A(z) 1 + X (z) 1+ A ( z ) 1+ A ( z ) 1 424 3 1 424 3 Noise Transfer Function
Signal Transfer Function
•
Objective – Want to make STF unity in the signal frequency band – Want to make NTF "small" in the signal frequency band
•
If the frequency band of interest is around DC (0…fB) we achieve this by making |A(z)| >>1 at low frequencies – Means that NTF is <<1 – Mans that STF ≅ 1
B. Murmann
EE315B - Chapter 11
10
Discrete Time Integrator
V ( z ) = z −1U ( z ) + z −1V ( z )
v ( k ) = u ( k − 1) + v ( k − 1) z −1
V (z) U (z)
•
=
1− z
−1
=
1 z −1
z = e j ωT
"Infinite gain" at DC (ω=0, z=1)
EE315B - Chapter 11
B. Murmann
11
First Order “Delta-Sigma” Modulator
E(z) X(z) + -
z-1 1-z-1
Y(z) +
DAC
1 1 Y (z) = E (z) + X ( z ) z − 1 = E ( z ) 1 − z −1 + X ( z ) z −1 1 1 1+ 1+ z −1 z −1
(
•
)
Output is equal to delayed input plus filtered quantization noise
B. Murmann
EE315B - Chapter 11
12
NTF Frequency Domain Analysis He ( z ) = 1 − z −1
e j ωT / 2 − e − j ωT / 2 He ( j ω ) = 1 − e − j ω T = 2e − j ω T / 2 2
(
)
= 2e
−j
ωT 2
ωT j sin 2
ωT = 2 sin 2
−j e
ω T −π 2
f He ( f ) = 2 sin ( πfT ) = 2 sin π fs
•
"First order noise Shaping"
•
Quantization noise is attenuated at low frequencies, amplified at high frequencies EE315B - Chapter 11
B. Murmann
13
In-Band Quantization Noise (1) •
Question: If we had an ideal digital lowpass, what would be the achieved SQNR as a function of oversampling ratio?
•
Can integrate shaped quantization noise spectrum up to fB and compare to full-scale signal Pqnoise =
fB
∫
0
≅
fB
∫
0
f ∆2 2 ⋅ ⋅ 2 sin π 12 fs fs ∆2 2 ⋅ 12 fs
2
df
2
f ⋅ 2π df fs 3
∆ 2 π2 2fB ∆ 2 π2 1 ≅ ⋅ = ⋅ 12 3 fs 12 3 M 3
B. Murmann
EE315B - Chapter 11
14
In-Band Quantization Noise (2) •
Assuming a full-scale sinusoidal signal, we have
(
SQNR ≅
Psig Pqnoise
2
B 1 2 −1 ∆ 2 2 = 1.5 × 2B − 1 2 × 3 × M 3 = 2 2 2 ∆ π 1 π4 1 24 3 ⋅ Due to noise 12 3 M 3
)
(
)
shaping & digital filter
≅ 1.76 + 6.02B − 5.2 + 30 log( M )
•
[dB ]
(for large B)
Each 2x increase in M results in 8x SQNR improvement – 9dB (1.5bits) per octave oversampling
EE315B - Chapter 11
B. Murmann
15
SQNR Improvement •
Example revisited – Want 16-bit ADC, fB=1MHz – Use oversampled 8-bit ADC, first order noise shaping and (ideal) digital lowpass filter • SQNR improvement compared to case without oversampling is -5.2dB+30log(M)
– 8-bit increase in resolution (48dB SQNR improvement) would necessitate M≅60 •
Not all that bad!
B. Murmann
M
SQNR improvement
16
31dB (~5 bits)
256
67dB (~11 bits)
1024
85dB (~14 bits)
EE315B - Chapter 11
16
DAC Requirements
Y (z) = E (z)
A(z) 1 + X ( z ) − εDAC ( z ) 1+ A ( z ) 1+ A ( z )
•
DAC error is indistinguishable from signal – Means that DAC must be precise to within target resolution
•
For the previous example, this means that we need an 8-bit DAC whose output levels have 16-bit precision… EE315B - Chapter 11
B. Murmann
17
Solutions •
Trimming or calibration – Measure DAC levels during test or at power-up – Apply correction values to each level using auxiliary DAC
•
Dynamic Element Matching Algorithms – Shuffle DAC unit elements to obtain fairly precise "average" output levels – Two ways • Data independent shuffling • Data dependent shuffling
– Data dependent shuffling algorithms allow to push most of the DAC "noise" outside the signal band – See e.g. [Carley, JSSC 4/1989], [Galton, TCAS II 10/1997], [Vleugels, JSSC 12/2001] •
Single bit DAC
B. Murmann
EE315B - Chapter 11
18
Data Independent Shuffling (1)
Carley, L.R., "A noise-shaping coder topology for 15+ bit converters," IEEE JSSC, vol.24, no.2, pp.267-273, Apr. 1989.
B. Murmann
EE315B - Chapter 11
19
Data Independent Shuffling (2)
Carley, L.R., "A noise-shaping coder topology for 15+ bit converters," IEEE JSSC, vol.24, no.2, pp.267-273, Apr. 1989.
B. Murmann
EE315B - Chapter 11
20
Data Dependent Shuffling (1) •
•
Select elements such that each one is used (on average) the same number of times DAC errors quickly sum to zero; errors are pushed to high frequencies
R.T. Baird, and T.S. Fiez, "Improved ΔΣ DAC linearity using data weighted averaging ," IEEE ISCAS, pp.13-16, May 1995.
B. Murmann
EE315B - Chapter 11
Code 3
Code 4
Code 2
21
Data Dependent Shuffling (2)
B. Murmann
EE315B - Chapter 11
22
Single-Bit DAC •
A single bit DAC has only two output levels
•
Even if these two levels are imprecise, the errors will only affect gain and offset of the DAC and modulator – Tolerable in many applications
EE315B - Chapter 11
B. Murmann
23
Modulator with Single-Bit Quantizer (1) •
Model 1-bit code
•
Expected SQNR (from slide 15 with B=1) 2
SQNR ≅
Psig Pqnoise
1 ∆ 9 2 2 = 2 2 = 2 × M3 2π ∆ π 1 ⋅ 3 12 3 M
= −3.4 + 30 log(M )
•
[dB ]
E.g. M=128 ⇒ SQNR=60dB
B. Murmann
EE315B - Chapter 11
24
Modulator with Single-Bit Quantizer (2) •
Implementation example
[Schreier, p. 31]
•
Not all that great in terms of achievable SQNR, but sufficient for some applications – E.g. digital voltmeter • See [van de Plassche, pp. 469]
B. Murmann
EE315B - Chapter 11
25
Simulated Response
B. Murmann
EE315B - Chapter 11
26
Spectrum
[Schreier, p. 39]
f/fs
•
Looks like there is some noise shaping, but SQNR=55dB is lower than the expected 60dB
B. Murmann
EE315B - Chapter 11
27
Amplitude and Frequency Dependence [Schreier, p. 40] [M=256]
•
Erratic dependence on amplitude and frequency – Simple linear model fails to predict this behavior
•
Issue: Quantization error sequence is not "sufficiently random", as assumed in the beginning of this discussion
B. Murmann
EE315B - Chapter 11
28
Quantization Error in 1st Order Modulator
Input x(n)
0.5
0
Quantization error e(n)
-0.5 0
•
200
400
600
800
1000
200
400 600 Sample index n
800
1000
0.5
0
-0.5 0
A complicated, but deterministic function of the input
B. Murmann
EE315B - Chapter 11
29
Aside: Quantizer Gain •
Another issue is that the gain of the single bit quantizer is illdefined, but we assumed it to be unity in our analysis
•
The actual quantizer gain can be found from simulations, and then plugged back into the linear model for better agreement (and stability analysis using root locus, etc.)
•
References – Schreier, Sections 3.2 and 4.2 – S. Ardalan, and J. Paulos, "An analysis of nonlinear behavior in delta - sigma modulators," IEEE TCAS, vol.34, no.6, pp. 593-603, June 1987. – T. Ritoniemi, T. Karema, and H. Tenhunen, "Design of stable high order 1-bit sigma-delta modulators," Proc. IEEE ISCAS, pp. 3267-3270, May 1990.
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30
Tones •
Since the quantization error is correlated with the input, the shaped quantization noise contains spurious tones, some of which lie in the signal band
•
The linear model cannot predict these tones
•
It is generally difficult to predict tonal behavior for arbitrary inputs, even with a nonlinear model – Analytical results exist for DC and sine inputs, see e.g. • R.M. Gray "Spectral analysis of quantization noise in a singleloop sigma-delta modulator with DC input," IEEE Trans. Comm., pp. 588-599, June 1989. • R.M. Gray et al., Quantization noise in single-loop sigma-delta modulation with sinusoidal inputs," IEEE Trans. Comm., pp. 956-968, Sept 1989.
•
Interesting and intuitive to look at DC input as a worst case
B. Murmann
EE315B - Chapter 11
31
DC Input (1) •
E.g. x(n)=0 – Modulator generates an alternating sequence of 1s and 0s – Single tone at fs/2; no low frequency component
•
E.g. x(n)=0.001⋅∆/2 – Compared to previous example, only one in 1000 outputs will change – Output has period of 1000⋅T, and hence contains a low frequency, in-band component
B. Murmann
EE315B - Chapter 11
32
DC Input (2) •
For a DC input, the modulator output consists of discrete tones ("idle tones") with power and frequency given by ∆ sin ( πfkT ) Pk = πk
2
x fk = k DC + 0.5 fs ∆
where k is an integer, and
represents the fractional part of r (r modulo 1) •
Strongest tones occur for small k, due to reciprocal dependence
•
The plot on the following slide shows the total mean square error due to in-band idle tones as a function of DC input (M=16)
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EE315B - Chapter 11
33
MSE due to Idle Tones
X/∆
B. Murmann
EE315B - Chapter 11
34
Idle Tone Considerations •
Idle tones are known to be a significant issue in audio applications – The human ear can detect tones ~20dB below the thermal/quantization noise floor
•
If idle tones are an issue, there are several options for mitigating their impact – Larger oversampling ratio – Multi-bit quantizer and DAC – Dither • Superimpose a pseudorandom signal at the quantizer input to "whiten" quantization noise – See e.g. Chapter 3 of Delta-Sigma Data Converters by Norsworthy, Schreier & Temes.
– Overdesign by making quantization noise much smaller than electronic noise from integrators • Noisy integrator(s) help randomize quantization error sequence
– Higher order modulators • Naturally produce "more random" quantization error sequences B. Murmann
EE315B - Chapter 11
35
Higher Order Modulators •
Motivation: better SQNR for a given oversampling ratio, plus improved idle tone performance as a side benefit
•
Commonly used architectures – Single quantizer loop with higher order filtering • Essentially a logical extension to the first order noise shaping concept discussed previously
– Cascaded, multi-stage modulators • Contain a separate quantizer in each stage
B. Murmann
EE315B - Chapter 11
36
Higher Order Noise Shaping •
Lth order noise transfer function
(
HE ( z ) = 1 − z −1
L
)
EE315B - Chapter 11
B. Murmann
37
In-Band Quantization Noise Pqnoise =
fB
∫
0
≅
fB
∫
0
f ∆2 2 ⋅ ⋅ 2 sin π 12 fs fs ∆2 2 ⋅ 12 fs
f ⋅ 2π fs
∆ 2 π2L 2fB ≅ ⋅ 12 2L + 1 fs ∆ 2 π2L 1 ≅ ⋅ 12 2L + 1 M
•
2L
df
2L
df
2L +1
2L +1
For an Lth order modulator, every doubling of M results in an increase in SQNR of 6L+3dB (L+0.5bits)
B. Murmann
EE315B - Chapter 11
38
SQNR [dB]
SQNR with Single Bit Quantizer
EE315B - Chapter 11
B. Murmann
39
Building a Second-Order Modulator (1) •
General idea: Start with a first order modulator and replace quantizer by another first order loop
-1 -1
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-1 -1
EE315B - Chapter 11
40
Building a Second-Order Modulator (2) •
More general structure E(z) X(z) +
z 1-z
a1
-
+
a2
-
Y(z)
z 1-z
+
b
a a z −2 HX (z ) = 1 2 D (z)
(
D( z ) = 1 − z −1
B. Murmann
)
2
(
(1− z ) (z ) = −1
HE
)
+ a2bz −1 1 − z −1 + a1a2 z −2 = 1
2
D (z)
a = a2 = 1 and b = 2 e.g. for 1 a1 = 0.5,a2 = 2 and b = 1
EE315B - Chapter 11
41
Boser-Wooley Modulator (1) (Single-bit)
[Boser & Wooley, JSSC 12/1988]
•
a1=0.5 and b=1, but a2=0.5 (instead of 2)
•
Since the integrator is followed by a single-bit quantizer, a2 can be scaled to reduce swing requirements in second integrator
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EE315B - Chapter 11
42
Boser-Wooley Modulator (2)
EE315B - Chapter 11
B. Murmann
43
Performance of 2nd Order Modulator [Schreier, p.70]
•
Compared to first order modulator, SQNR is in "better" agreement with simple linear model
•
Improved idle tone performance
-20 O
-30
1st order
O -40
O O
-50
O
X
O
-60 X
-70
X
-80
2nd order
-90
X
-100
X
-110
X
-120 8
16
32
64
128
256
512
1024
Oversampling Ratio B. Murmann
EE315B - Chapter 11
44
Single Quantizer Modulators with Order >2 •
Most general (mathematical) filter decomposition
He ( z ) = L0 ( z ) =
B. Murmann
1 1 − L1( z )
Hx ( z ) =
Hx ( z ) He ( z )
L1( z ) = 1 −
L0 ( z ) 1 − L1( z ) 1 He ( z )
EE315B - Chapter 11
45
Stability •
Having more than two integrators in a feedback loop means that the loop can be unstable (criterion = BIBO)
•
From the diagram of the previous slide, it is clear that the stability of the loop mostly depends on L1(z), and therefore the characteristics of the NTF
•
How about the nonlinear transfer characteristic of the quantizer? – Unfortunately, there is no crisp mathematical result that would address this question for all possible configurations – One important, and general aspect of having a nonlinearity in the loop is that the stability becomes dependent on the signal (and also L0)!
•
In practice, designers rely on a combination of stability analyses using the linear model (!), established “heuristics,” and time domain simulations of the nonlinear model
B. Murmann
EE315B - Chapter 11
46
Stability Heuristics •
Single-bit – First order modulator is stable (bounded integrator output) with arbitrary inputs of less than ∆/2 in magnitude – Second order modulator is known to be stable with arbitrary inputs of less than ∆/20 in magnitude, and for "reasonable", slow varying inputs of magnitude <0.8·∆/2, integrator outputs are "likely" to stay within bounds – Lee's criterion: modulator is "likely" to be stable if max[He(ω)]<1.5
•
Multi-bit – A modulator with Nth order differentiation using an N+1 bit quantizer is stable for arbitrary inputs with amplitude less than half the quantizer input range (Schreier, p. 104) – … EE315B - Chapter 11
B. Murmann
47
The Cost of Stability (Single-bit)
M=40, L=6
Max. Input [∆/2]
[Norsworthy, pp.156]
max[He(ω)]
•
max[He(ω)]
Higher out of band gain means higher attenuation in the signal band and hence better SQNR – Unfortunately modulator becomes "less stable"
B. Murmann
EE315B - Chapter 11
48
Achievable SQNR
•
Diminishing return for order greater 5-6
EE315B - Chapter 11
B. Murmann
49
Topology Example: Single Feedback Loop
He ( z ) =
B. Murmann
1 1 + A( z )
Hx ( z ) =
A( z ) ≅ 1 in band of interest 1 + A( z )
EE315B - Chapter 11
50
Topology Example: CIFB Architecture
[Schreier, p. 115]
•
“Cascade of Integrators with Feedback”
•
All zeros of NTF lie at DC for this structure, i.e. HE(z) = (1-z-1)N
•
Can create complex conjugate zeros by adding feedback paths around pairs of integrators (cascade of resonators, CRFB structure)
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EE315B - Chapter 11
51
Typical Design Procedure •
"Cookbook design" – See e.g. Delta-Sigma Data Converters, by Norsworthy, Schreier & Temes, Sections 4.4 and 5.6 – Choose order based on desired SQNR and M – Design NTF using filter approximations (e.g. Chebyshev2) • Make sure to obey Lee's criterion
– Determine loop-filter transfer function and evaluate performance and stability using simulations – Determine implementation-specific coefficients – Scale coefficients to restrict integrator outputs to stay within available range (“dynamic range scaling") •
Delta-Sigma Toolbox for MATLAB (by Richard Schreier) – http://www.mathworks.com/matlabcentral/fileexchange – Look under "Controls" and find "Delsig" toolbox
B. Murmann
EE315B - Chapter 11
52
"Cookbook" NTF Design Example (1) % design parameters L=4;
% order
M=64; % oversampling ratio % stop-band attenuation; reduce if needed to make max(|He(w)|<1.5) Rstop = 80; [b,a] = cheby2(L, Rstop, 1/M, 'high'); % normalize to make He(z->inf)=1; needed for realizability % makes first sample of impulse response of He equal to 1 % makes first sample of impulse response of A equal to 0 % (must have at least one delay around quantizer) b = b/b(1); % check Lee's rule; want max(|He(w)|<1.5 ) NTF = filt(b, a, 1) [mag] = bode(NTF, pi)
EE315B - Chapter 11
B. Murmann
53
"Cookbook" NTF Design Example (2) Transfer function: 1 - 3.998 z^-1 + 5.995 z^-2 - 3.998 z^-3 + z^-4 -----------------------------------------------------1 - 3.247 z^-1 + 4.013 z^-2 - 2.231 z^-3 + 0.4699 z^-4 mag = 1.459
0
He [dB]
-20 -40 -60 -80 -100 10
B. Murmann
-3
-2
10 Frequency [f/f s]
EE315B - Chapter 11
10
-1
54
"Cookbook" NTF Design Example (3) % Loop filter transfer function A = inv(NTF) - filt(1,1,1) Transfer function: 0.7505 z^-1 - 1.982 z^-2 + 1.766 z^-3 - 0.5301 z^-4 --------------------------------------------------1 - 3.998 z^-1 + 5.995 z^-2 - 3.998 z^-3 + z^-4 % Check realizability a = impulse(A); a(1) ans = 0
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EE315B - Chapter 11
55
Commercial Example
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EE315B - Chapter 11
56
Cascaded Modulators
Analog In
x
Σ∆
DELAY
y
e
x
•
Σ∆
y
+
Σ
–
Digital Out
DIGITAL DIFFERENCE
Concept – Cascade of two or more stable (low order) modulators – Quantization error of each stage is quantized by the succeeding stages and subtracted in digital domain
B. Murmann
EE315B - Chapter 11
57
Second Order (1-1) Cascade
Y1(z) = z–1X(z) + (1 – z–1)E1(z) Y2(z) = z–1E1(z) + (1 – z–1)E2(z)
Y(z) = z–1Y1(z) – (1 – z–1)Y2(z) = z–2X(z) + z–1(1 – z–1)E1(z) – z–1(1 – z–1)E1(z) – (1 – z–1)2E2(z) Y(z) = z–2X(z) – (1 – z–1)2E2(z)
•
Second order noise shaping using two first order loops!
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EE315B - Chapter 11
58
Properties •
Order of overall noise shaping is equal to sum of modulator orders
•
No stability issues
•
Improved idle tone performance – Input of second stage is "noise like" – Remaining quantization error from second stage is very close to white noise
•
Cancellation of first stage quantization noise depends on matching between analog and digital signal paths – Hard to suppress first stage quantization error by more than 40dB – Mismatch will affect idle tone performance
EE315B - Chapter 11
B. Murmann
59
1-1-1 Cascaded Modulator (MASH)
1 z-1
1 z-1
1 z-1
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EE315B - Chapter 11
60
Mismatch Sensitivity
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EE315B - Chapter 11
61
2-1 Cascade
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EE315B - Chapter 11
62
Mismatch Sensitivity
EE315B - Chapter 11
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63
Circuit Level Considerations •
Finite OTA gain – Integrator leak – Dead zones – Nonlinearity
•
Electronic noise
•
OTA dynamic settling error, nonlinearity due to slewing
•
Capacitor voltage coefficients
•
Comparator hysteresis – Usually not a problem; simulations show that up to a few % hysteresis can be tolerated
•
Unwanted mixing effects – E.g. if Vref contains fs/2, out of band noise will be mixed down into signal band
B. Murmann
EE315B - Chapter 11
64
Integrator Analysis (1)
t/Ts
Qs
QI
n-1
Cs·Vi(n-1)
CI·Vo(n-1)
n-1/2
0
CI·Vo(n-1/2) = CI·Vo(n-1) + Cs·Vi(n-1)
n
Cs·Vi(n)
CI·Vo(n) = CI·Vo(n-1) + Cs·Vi(n-1)
n+1/2
…
…
EE315B - Chapter 11
B. Murmann
65
Integrator Analysis (1) •
Assuming that Vo is sampled during φ1, we have
CIVo ( n ) = CIVo ( n − 1) + CsVi ( n − 1) CIVo ( z ) = z −1CIVo ( z ) + z −1CsVi ( z ) ∴ •
Vo ( z ) Cs z −1 = Vi ( z ) CI 1 − z −1
Unfortunately, this ideal expression holds only for infinite amplifier gain – Let's look at impact of finite gain
B. Murmann
EE315B - Chapter 11
66
Finite Gain (1)
A
t/Ts
Qs
QI
n-1
Cs·Vi(n-1)
CI·Vo(n-1)·[1+1/A]
n-1/2
Cs·Vo(n-1/2)/A
CI·Vo(n-1/2)·[1+1/A] = CI·Vo(n-1)·[1+1/A] + Cs·Vi(n-1) - Cs·Vo(n-1/2)/A
n
Cs·Vi(n)
CI·Vo(n)·[1+1/A] = CI·Vo(n-1)·[1+1/A] + Cs·Vi(n-1) - Cs·Vo(n)/A
n+1/2
…
…
B. Murmann
EE315B - Chapter 11
67
Finite Gain (2) •
Again, assuming that Vo is sampled during φ1, we have C 1 1 CIVo ( z ) 1 + = z −1CIVo ( z ) 1 + + z −1CsVi ( z ) − s Vo ( z ) A A A 1 C z −1 1 − 1 + s A CI Vo ( z ) Cs g ⋅ z −1 ∴ ≅ = Vi ( z ) CI 1 Cs −1 1 − [1 − α ] ⋅ z −1 z 1− 1− A CI Vo ( z ) = [1 − α ] ⋅ z −1Vo ( z ) + g ⋅ z −1Vi ( z )
•
Finite gain results in "leaky integrator" – Some fraction of previous output is lost in new cycle
B. Murmann
EE315B - Chapter 11
68
Frequency Domain View •
Limited gain at low frequencies (ω→0, z →1)
H0 = H( z ) z =1 =
•
g g = ∝A 1 − [1 − α ] α
But noise shaping relies on high integrator gain at low frequencies…
B. Murmann
EE315B - Chapter 11
69
Required DC Gain
[Boser & Wooley, JSSC 12/1988]
•
Good practice to make OTA gain at least a few times larger than oversampling ratio
B. Murmann
EE315B - Chapter 11
70
Integrator Noise •
Noise splits into an input referred and output referred component – The two noise components are correlated – Luckily, only the input referred component is relevant • We’ll see that output noise is first-order shaped by the modulator
[Schreier, TCAS1, 2005]
EE315B - Chapter 11
B. Murmann
71
Integrator’s Input Referred Noise 2 = v in,tot
kT kT 1 kT 1 + + αγ Cs Cs 1 + 1 Cs 1 + x { x424444 1444 3 φ1
x = gm ⋅ 2Ron [Schreier, TCAS1, 2005]
φ2 Analysis of phi2 noise: Calculate noise charge left behind at Y after switch has turned off. Charges at X and Y are equal and opposite, so calculating charge on Cs accomplishes the task.
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EE315B - Chapter 11
72
Second-Order ∆Σ Modulator 2 v in,tot1
PSD(f)
PSD(f)
2 v in,tot2
f
f
fs/2
fs/2
Y(z) = 2 1 − z −1 z −1 N2(z)
Y(z) = z −2 N1(z)
(
)
EE315B - Chapter 11
B. Murmann
73
In-Band Noise PSD(f) PSD(f) Digital filter f
f fb
fs/2
+ fb
PSD(f)
fs/2
fs/2
+
f PSD(f)
OSR = f
fs / 2 fb
fs/2
B. Murmann
f fb
EE315B - Chapter 11
fs/2
74
In-Band Noise PSD(f)
PSD(f)
f
+
f
fs/2
2 vin,tot1 ⋅
fs/2
1 OSR
2 v in,tot2
π2 1 ⋅ 3 OSR3
Total in-band thermal noise at modulator input: 2 v in,tot
B. Murmann
=
2 ⋅ vin,tot1
1 π2 1 2 + vin,tot2 ⋅ OSR 3 OSR3 EE315B - Chapter 11
75
Example of a Continuous Time Modulator [Mitteregger, ISSCC 2006]
•
B. Murmann
4-stage amplifier with feedforward compensation – Impractical for SC circuits – Great for CT delta-sigma modulators
EE315B - Chapter 11
76
Multi-Mode Modulator [Ouzounov, ISSCC 2007]
B. Murmann
•
Delta-sigma ADCs are more amenable to BW and DR reconfiguration – Very hard to reconfigure pipelined ADCs
•
Great for flexible, multistandard wireless receivers
EE315B - Chapter 11
77
Decimation Filters •
References – J. Candy, "Decimation for Sigma-Delta Modulation," IEEE Trans. Communications, pp. 72-76, Jan. 1986. – Chapters 1 and 13 of Delta-Sigma Data Converters, by Norsworthy, Schreier, Temes. – B.P. Brandt and B.A. Wooley, "A low-power, area-efficient digital filter for decimation and interpolation," IEEE J. SolidState Circuits, pp. 679-687, June 1994. – E. Hogenauer, "An economical class of digital filters for decimation and interpolation," IEEE Trans. Acoustics, Speech and Signal Processing, pp. 155-162, Apr 1981.
•
Objectives – Remove out-of band quantization noise – Re-sample at lower frequency • Ideally at Nyquist rate
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78
Example Decimation Filter (M = 256)
fS Analog Input
11.3 MHz
Σ∆ Modulator
1-Bit
(2nd-Order)
11.3 MHz
fN 44.1 kHz
Digital Output (16 Bits)
Quantization Noise
Signal Noise
Frequency
•
Frequency
Frequency
Filter must attenuate spectral components around ± N·fN, – Otherwise they will alias onto signal after re-sampling
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EE315B - Chapter 11
79
Filter Requirements
•
Pass band 0…20kHz, transition band 20…24.1kHz (∆f=4.1kHz), stop band 24.1kHz…5.65MHz
•
A digital FIR filter that meets these requirements would require more than fs/∆f = 11.3MHz/4.1kHz ≅ 2800 coefficients – Impractical!
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EE315B - Chapter 11
80
Multi-Step Decimation •
Key idea: Don’t try to decimate down to fN in one step – Perform a gradual reduction of sampling rate + some filtering – E.g. Two-step decimation
•
Example: M1=64, fs/M1=176.4kHz
EE315B - Chapter 11
B. Murmann
81
Sinc Filter (1) •
A popular, low complexity choice for stage 1 is the so-called sinc-filter
•
From a time domain perspective, this filter simply computes the average of several samples y( n ) =
•
Frequency domain −N
H( z ) =
•
1 1− z N 1 − z −1
1 N −1 ∑ x (n − i ) N i =0
f sin πN fs 1 H( ω ) = f N π fs
− j π f ( N −1) e fs
Zeros at multiples of fs/N – Make N=M1 to attenuate alias components!
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82
Cascade of K Sinc Filters 0 -10 -20 -30 -40 -50 K=1
-60
K=2 -70 K=3 -80 -90 -100 0 f B fN
fs1 M1
2f s1 M1
3f s1 M1
Frequency
•
Higher order means better rejection – But also more in-band droop
•
Can show that for Lth order noise shaping, an (L+1)th order sinc filter is the best choice
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EE315B - Chapter 11
83
Sinc Filter Performance Noise penalty relative to "brick wall" filter
Droop
[Norsworthy, p.30]
[Norsworthy, p.31]
•
Only about 0.14 dB increase in baseband noise for decimation to an intermediate oversampling ratio of 4
•
If droop is undesired, it can be corrected downstream, using a separate post-emphasis filter
B. Murmann
EE315B - Chapter 11
84
Sinc Filter Performance (2) •
In addition to suppressing quantization noise, the filter must attenuate out-of-band signals present at the modulator input – Worst case freqeuncy is fs/M1-fB – E.g. 50dB for sinc3, and intermediate oversampling of 4x – Any additional desired rejection must come from analog filter at modulator input
[Norsworthy, p.31]
EE315B - Chapter 11
B. Murmann
85
Sinc Filter Implementation Numerator Section: X
1 – z -1
Y
+
X
Y
Delay Denominator Section: X
1 1 – z -1
Y
X
+
Y Delay
B. Murmann
EE315B - Chapter 11
86
Complete Filter Implementation THIRDORDER SINC FILTER
1 IN 11.3 MHz
20 176.4 kHz
FIRST HALFBAND FILTER (R=18)
M 1 = 64
22 88.2 kHz
SECOND DROOP 22 16 HALFBAND CORRECTION FILTER FILTER 44.1 (R=8) (R=110) kHz
M2 = 2
OUT 44.1 kHz
M3 = 2
0 Passband Ripple = ± 0.01 dB
-10 -20
[Brandt & Wooley, JSSC 6/1994]
-30 -40 Second Halfband Filter
-50 -60
First Halfband Filter
Third-Order Sinc Filter
-70 -80 -90 -100 0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (kHz) EE315B - Chapter 11
B. Murmann
87
Droop Correction
0.6 0.5 0.4 0.3
Droop-Correction Filter
0.2
First Halfband Filter
0.1 0.0 -0.1 -0.2
Second Halfband Filter
Third-Order Sinc Filter
-0.3 -0.4 -0.5 -0.6 0
2
4
6
8
10
12
14
16
18
20
22
FREQUENCY (kHz)
B. Murmann
EE315B - Chapter 11
88
Implementation
SINC FILTER INTEGRATORS
20
20
20
20
20
•
43 multiplications and 84 additions per output sample
•
Can use serial arithmetic to minimize hardware area – Since output rate is usually fairly low
Σ∆ Modulator Output
20
CLK (11.3 MHz) Processor Input
Virtual Addr. Logic 7 7 Addr
8 7
Data RAM
Addr
(128 x 22)
PROCESSOR
Coefficient/ Control ROM
R/W Dout
(256 x 22)
Din 22
13
22
Ctrl.
Filter Output
22-Bit Arithmetic Unit (AU)
EE315B - Chapter 11
B. Murmann
89
D/A Conversion Revisited TS yH (t) Time N-Bit Digital lnput Word x(kT) b1
b2
b3
y(t) Time
bN •••
Digital-to-Analog Interface
B. Murmann
x*(t)
Zero-Order Hold
EE315B - Chapter 11
yH (t) Lowpass y(t) Analog Output Filter
90
Frequency Spectra Magnitude
SpectralImage Images Spectral Bands (Dirac Reconstruction)
Baseband Signal
|X*(f)|
0
fS/2
fS
2fS
3fS
0
fS/2
fS
2fS
3fS
0
fS/2
fS
2fS
3fS
|P Z (f)|
|YH (f)|
Frequency
EE315B - Chapter 11
B. Murmann
91
Oversampling Magnitude
Spectral Image Bands Spectral Images
Analog Filter
|X(f)|
… fB
fN
2 fN
(a)
(M-2) fN (M-1) fN
M fN
Analog Filter
|XM (f)|
fB
(b)
fS = M f N
Frequency
•
Oversampling greatly reduces reconstruction filter requirements
•
How to create oversampled DAC input from a Nyquist rate signal?
B. Murmann
EE315B - Chapter 11
92
Interpolation (1) •
Can increase the sampling rate of a discrete time signal by a factor of M, by inserting M-1 zero-valued samples between the actual Nyquist rate samples ("zero stuffing") – Causes an M-fold periodic repetition of the baseband spectrum Image Bands Spectral Images
Nyquist-rate Input
… fB fS =fN
2 fN
After Zero Insertion
(M-2) fN (M-1) fN
M fN
… fB
fN
2 fN
(M-2) fN (M-1) fN fS =M fN
EE315B - Chapter 11
B. Murmann
93
Interpolation (2) •
Why is this a good idea?
•
Can remove images and get wide transition band to play with – Simple reconstruction filter – Possibility of noise shaping • Build a high resolution DAC using a low resolution D/A interface B
N
N
N
N
S
N
Digital M Lowpass Filter fB
fS =M fN
fB
fS =M fN
Interpolator Output
B. Murmann
EE315B - Chapter 11
94
Example DIGITA L
Digital 16 Input fN
Digital
Digital
16
Interpolator M f
ANALOG
Analog
1
Reconstruction
Noise N
Shaper M fN
Analog Output
Filter
1-bit D/A Interface
•
Digital noise shaper is essentially a digital sigma-delta loop – Shapes "truncation noise" that results from truncating 16-bit word to a 1-bit output EE315B - Chapter 11
B. Murmann
95
Spectra Spectral Images Digital Input
… fN
Interpolator Output
Noise Shaper Output
2 fN
(M-2) fN (M-1) fN
M fN
Baseband Signal
Truncation Noise Quantization Noise
M fN
M fN Analog Output Frequency B. Murmann
EE315B - Chapter 11
96
Example E(z)
16 +
Σ
X(z) –
18
+
Σ
19
+
Σ
z–1
+
1
z–1
Y(z)
To 1-bit D/A Interface
+ 18
Clipper +
Σ
[Su &Wooley, JSSC 12/94]
– 2
Y(z) = z – 2 X(z) + (1 – z –1 ) 2 E(z)
•
Clipper prevents second integrator from overflowing – Digital "wrap around" would cause large errors
EE315B - Chapter 11
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97
Semi-Digital Reconstruction (1) Digital Input 1 DIN
n -Bit Shift Register
z– 1
z– 1
...
z– 1 DIGITA L ANALOG
a1
a2
...
an
Σ
[Su &Wooley, JSSC 12/94] Analog Output, A OUT HFIR (z) = a1 z–1 + a2 z–2 + ... + an z–n
•
Attractive alternative to fully analog reconstruction filter – Build FIR filter with weighted analog outputs
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98
Semi-Digital Reconstruction (2) Digital Input
128-Bit Shift Register
DIGITA L ANALOG Weighted Current Sources a
a 1
... 2
a 128 Current-to-Voltage Conversion
I out
I out
A OUT ( z ) =
a1 z
–1
+ a2 z
–2
+ a3 z
–3
Analog Output
+
+ … + an z
–n
DIN ( z )
H (z)
•
Linear if H(z) is independent of DIN(z) EE315B - Chapter 11
B. Murmann
99
Measurement Results
Reconstruction Filter
Output 0 Noise Shaper Output Analog Output
Power Spectrum (dB)
– 20 – 40 – 60 – 80 – 100 – 120 – 140 – 160
1k
10k
100k
1M
Frequency (Hz)
B. Murmann
EE315B - Chapter 11
100
Energy Limits in A/D Converters
Boris Murmann Stanford University [email protected] Copyright © 2013 by Boris Murmann
EE315B - Chapter 12
B. Murmann
1
ADC Landscape in 2005 -6
10
-8
P/f s [J]
10
-10
10
-12
10
ISSCC & VLSI 1998-2005 20
30
40
50
60 70 SNDR [dB]
80
90
100
110
B. Murmann, "ADC Performance Survey 1997-2013," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html B. Murmann
EE315B - Chapter 12
2
ADC Landscape in 2013 -6
10
-8
P/f s [J]
10
-10
10
-12
10
ISSCC & VLSI 2006-2013 ISSCC & VLSI 1998-2005 20
30
40
50
60 70 SNDR [dB]
80
90
100
110
B. Murmann, "ADC Performance Survey 1997-2013," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html B. Murmann
EE315B - Chapter 12
3
Questions
•
How much more improvement can we hope for? What is the fundamental energy limit?
•
Will certain architectures continue to improve faster than others? Are there any architecture-specific limits?
•
Will CMOS process technology scaling play a significant role in future improvements?
•
How does absolute conversion speed affect energy consumption and the projected limits?
B. Murmann
EE315B - Chapter 12
4
Fundamental Limit
1 VFS 2 2 SNR = kT C
2
Pmin = CVFS fs ⋅ VDD
Emin =
VDD = VFS
Pmin = 8kT ⋅ SNR fs
[Hosticka, Proc. IEEE 1985; Vittoz, ISCAS 1990] EE315B - Chapter 12
B. Murmann
5
ADC Landscape in 2005 -6
10
-8
Energy [J]
10
-10
10
4x/6dB
-12
10
ISSCC & VLSI 1998-2005 Emin
-14
10
20
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30
40
50
60 70 SNDR [dB] EE315B - Chapter 12
80
90
100
110
6
ADC Landscape in 2013 -6
10
-8
Energy [J]
10
-10
10
4x/6dB
-12
10
ISSCC & VLSI 2006-2013 ISSCC & VLSI 1998-2005 Emin
-14
10
20
30
40
50
60 70 SNDR [dB]
80
90
100
EE315B - Chapter 12
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7
Normalized Plot 8
10
ISSCC & VLSI 2006-2013 ISSCC & VLSI 1998-2005 6
EADC/Emin
10
4
10
2
10
~10,000 ↓100x in 8 years
~100 ↓~2x in 8 years
0
10
20
B. Murmann
30
40
50
60 70 SNDR [dB]
EE315B - Chapter 12
80
90
100
110
8
Aside: Figure of Merit Considerations •
There are (at least) two widely used ADC figures of merit (FOM) used in literature
•
Walden FOM – Energy increases 2x per bit (ENOB) – Empirical
•
FOM =
Power ENOB
2
⋅ fsnyq
Schreier FOM – Energy increases 4x per bit (DR) – Thermal BW – Ignores distortion FOM = DR(dB) + 10log
P
EE315B - Chapter 12
B. Murmann
9
FOM Lines 10
Energy [J]
10
10
10
10
-6
-8
-10
-12
ISSCC & VLSI 1998-2005 ISSCC & VLSI 2006-2013 Emin
-14
Walden FOM = 10fJ/conv-step Schreier FOM = 170dB
20
•
30
40
50
60 70 SNDR [dB]
80
90
100
110
Best to use thermal FOM for designs with SNDR > 60dB
B. Murmann
EE315B - Chapter 12
10
Energy by Architecture 10
P/f s [J]
10
10
10
-6
-8
-10
Flash Pipeline SAR ∆Σ Other
-12
20
B. Murmann
30
40
50
60 SNDR [dB]
EE315B - Chapter 12
70
80
90
100
11
Flash ADC
Ecomp
B. Murmann
Eenc
EE315B - Chapter 12
12
Encoder • Assume a Wallace encoder (“ones counter”) • Uses ~2B–B full adders, equivalent to ~ 5∙(2B–B) gates
(
)
Eenc ≅ 5 ⋅ 2B − B ⋅ Egate
EE315B - Chapter 12
B. Murmann
13
Matching-Limited Comparator
Cc
Cc
C A 2VT = A 2VT c WL Cox
Offset
Cc =
A 2VT Cox + Cc min σ2VOS
Required capacitance
3σ VOS =
Simple Dynamic Latch Assuming Ccmin = 5fF for wires, clocking, etc.
Ecomp
σ2VOS ≅
B≅
1 Vinpp 4 2B
Confidence interval 3dB penalty accounts for “DNL noise”
SNR[dB] + 3 6
2 VDD 2B 2 2 ⋅ 2B − 1 ≅ 144 ⋅ 2 ⋅ Cox A VT ⋅ 2 + Cc min VDD 1 4 24 3 Vinpp Matching
(
)
Energy B. Murmann
EE315B - Chapter 12
14
Typical Process Parameters Process [nm]
AVT [mV-µm]
Cox [fF/µm2]
AVT2Cox /kT
Egate [fJ]
250
8
9
139
80
130
4
14
54
10
65
3
17
37
3
32
1.5
43
23
1.5
EE315B - Chapter 12
B. Murmann
15
Comparison to State-of-the-Art -6
10
-8
10
Flash ISSCC & VLSI 1997-2012 Eflash65nm Ecomp65nm
-10
Emin
[6]
P/f snyq [J]
10
[2]
[1]
-12
10
[5] [4]
[3]
-14
10
-16
10
15
20
25
[1] Van der Plas, ISSCC 2006 [2] El-Chammas, VLSI 2010 [3] Verbruggen, VLSI 2008 B. Murmann
30 SNDR [dB]
EE315B - Chapter 12
35
40
[4] Daly, ISSCC 2008 [5] Chen, VLSI 2008 [6] Geelen, ISSCC 2001 (!) 16
Impact of Scaling -6
10
Flash ISSCC & VLSI 1997-2012 Eflash250nm Eflash130nm
-8
P/f snyq [J]
10
Eflash65nm Eflash32nm Emin
-10
10
-12
10
-14
10
15
20
25
30
35
40
SNDR [dB]
EE315B - Chapter 12
B. Murmann
17
SC Delta-Sigma Modulator Assumptions
Model of first integrator
Closed-loop gain = ½ C
C /2
1
Infinite transistor fT (Cgs=0) Thermal noise factor (γ) equals 1
2
Bias device has same noise as amplifier device Linear settling only (no slewing)
β=
Ci Ci +
B. Murmann
Ci 2
=
2 3
Ceff = Ci (1 − β ) + CL =
EE315B - Chapter 12
1 2 Ci + CL ≅ Ci 3 3 18
SC Integrator Constraints 2
1 Vinpp 2 2 SNR ≅ kT 1 4 Ceff OSR
τ=
Thermal noise sets Ceff
Ceff T /2 Ts / 2 = s ≅ βgm 1 ln SNR ln εd
(
P = VDD
Settling time sets gm
)
gm
gm sets power
gm ID EE315B - Chapter 12
B. Murmann
19
Pulling It All Together Settling “Number 6474of 8τ”
Eint DT = 64 { ⋅ kT ⋅ SNR ⋅ ln Excess noise Finite β
(
VDD penalty
2 } VDD 1 1 SNR ⋅ ⋅ ⋅ V V gm DD 1 4inpp 24 3 ID { Supply
)
utilization Transconductor efficiency
• For settling with ~10 time constants and VDD=1V, gm/ID=1/(1.5kT/q), Vinpp=0.5V, we have
E୧୬୲ ≅ 200kT · SNR B. Murmann
EE315B - Chapter 12
20
Comparison to State-of-the-Art -6
10
[8] -8
[7]
P/f snyq [J]
10
-10
10
[1]
[2]
[4] [5]
[3]
[6] DT∆Σ ISSCC & VLSI 1997-2012 CT∆Σ ISSCC & VLSI 1997-2012 First Integrator EintCT
-12
EintDT
10
Emin
60
65
70
75
[1] Kauffman, ISSCC 2011 [2] Witte, ISSCC 2012 [3] Shettigar, ISSCC 2012 [4] Gealow, VLSI 2011
80
85 90 SNDR [dB]
95
100
105
[5] Chae, ISSCC 2008 [6] Pena Perez, ISSCC 2011 [7] Park, VLSI 2008 [8] Brewer, ISSCC 2005
EE315B - Chapter 12
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21
Overall Picture 10
P/f s [J]
10
10
-6
-8
Flash Pipeline SAR ∆Σ
-10
Other E
flash32nm,cal
E
10
-12
E E E
10
-14
20
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50
60 70 SNDR [dB] EE315B - Chapter 12
80
90
pipe sar CT∆Σ min
100
110
22
Discussion •
Today’s designs are very close to the predicted limits
•
The limit lines at high resolution are set by fundamental thermal noise and architectural circuit overhead – Technology scaling won’t help much
•
Sometimes it is even argued that technology scaling will deteriorate efficiency, due to low VDD – Let’s have a closer look at this…
EE315B - Chapter 12
B. Murmann
23
A Closer Look at the Impact of Technology Scaling As shown previously: 2
1 VDD 1 E∝ ⋅ ⋅ VDD Vinpp gm ID •
Low VDD hurts, but this is not the only factor
•
Designers have worked hard to maintain (if not improve) Vinpp/VDD in low-voltage designs
•
How about gm/ID?
B. Murmann
EE315B - Chapter 12
24
gm/ID Considerations (1) 30 180nm 90nm
gm/ID [S/A]
25 20 15 10 5 0 -0.2
• •
-0.1
0
0.1
0.2 0.3 VGS-Vt [V]
0.4
0.5
0.6
Largest value occurs in weak inversion ~(1.5⋅kT/q)-1 Range of gm/ID does not scale (much) with technology EE315B - Chapter 12
B. Murmann
25
gm/ID Considerations (2) 120
fT [GHz]
100
180nm 90nm
80 60 40 20 0 -0.2
• •
-0.1
0
0.1
0.2 0.3 VGS-Vt [V]
0.4
0.5
0.6
fT is small in weak inversion region Must look at gm/ID for given fT requirement to compare technologies B. Murmann
EE315B - Chapter 12
26
gm/ID Considerations (3) 30 180nm 90nm 45nm
gm/ID [S/A]
25
20
•
Example – fT = 30GHz – 90nm: gm/ID = 18S/A – 180nm: gm/ID = 9S/A
•
For a given fT, 90nm device takes less current to produce same gm – Helps mitigate, if not eliminate penalty due to lower VDD (!)
15
10
5 0
20
40 60 fT [GHz]
80
100
EE315B - Chapter 12
B. Murmann
27
ADC Energy for 90nm and Below 10
P/f snyq [J]
10
10
10
-6
-8
-10
-12
20
B. Murmann
ISSCC & VLSI 1997-2013 90nm and below 30
40
50
60 70 SNDR [dB] EE315B - Chapter 12
80
90
100
110
28
Efficiency versus Absolute Speed ௐ = 10
௦ · 2ாேை
ೞ ≅ ଶ
6
FOM W [fJ/conv-step]
2006-2013 1998-2005
10
10
4
2
0
10 4 10
10
5
10
6
10
7
10
8
10
9
10
10
f s [Hz] EE315B - Chapter 12
B. Murmann
29
Analysis 1 ∝ ∝ ை ௦
் =
3 ை 2 ଶ
∝ ் = · ௦ ௦
B. Murmann
Energy efficiency reduces with larger gate overdrive
But, large gate overdrive is needed for high transistor fT
fT is usually chosen as a multiple of the sampling rate
EE315B - Chapter 12
30
Conclusions (1) •
No matter how you look at it, today’s ADCs are extremely well optimized
•
The main trend is that the “thermal knee” shifts very rapidly toward lower resolutions – Thanks to process scaling and creative design
•
At high resolution, we seem to be stuck at E/Emin~100 – The factor 100 is due to architectural complexity and inefficiency: excess noise, signal < supply, non-noise limited circuitry, class-A biasing, …
•
This will be very hard to change – Scaling won’t help (much) – Some of the recent data points already use class-B-like amplification – Can we somehow recycle charge?
B. Murmann
EE315B - Chapter 12
31
Conclusions (2) •
At low resolutions, scaling will continue to help lower ADC energy
•
Scaling will especially help improve the efficiency of GS/s A/D converters – This is badly needed for high-speed data links (electrical and optical)
•
For non-incremental improvements, we must explore new ideas in signal processing that tackle ADC inefficiency at the system level – Compressed sensing – Finite innovation rate sampling – Other ideas?
B. Murmann
EE315B - Chapter 12
32
Example: Finite Innovation Rate Sampling of Ultrasound Signals Low BW after filtering
High BW
Analog Filter
Reconstruction
[Inspired by theoretical work of Prof. Yonina Eldar]
~100x reduction in sampling rate B. Murmann
EE315B - Chapter 12
33
