ECE 4141 VLSI Design Created by Ahmad Anwar Zainuddin and Dr. Anis Nurashikin Nordin Experiment 3: 1. To optimize the transistor sizing (W/L ratio) in CMOS NAND gate sizing using PSPICE.
CMOS Technology: 0.35um Instruction:
Design a 2 input CMOS NAND gate using the PSPICE parameters given below. The switching threshold must be VDD/2 with an acceptable tolerance of +/- 0.15V. CMOS NAND gate can be thought of as an equivalent inverter when the 2 inputs are shorted together.) The power supply voltage is 3.5V. THEORY
The two-input NAND gate shown in the figure 1 is built from four transistors. The seriesconnection of the two n-channel transistors between GND and the gate output ensures that the gate-output is only driven low (logical 0) when both gate inputs A or B are high (logical 1).The complementary parallel connection of the two transistors between VDD and gate-output means that the gate-output is driven high (logical 1) when one or both gate inputs are low (logical 0). The net result is the logical NAND function.
Figure 1: NAND gates using CMOS logic and it s truth table with reference resist or.
Procedures:
1. To optimize the transistor sizing (W/L ratio) in CMOS NAND gate, we can see how W/L ratio can affect the voltage transfer curve, curve, VTC. 2. To simplify the analysis, we can use two-input NAND gate instead of the four-input NAND gate. 3. Based on NAND truth table (Figure 1), WORST CASE for PMOS (pull up), where logic input (A=1,B=1) due high resistance (2R) .Hence, we perform the analysis for the WORST case situation when VIN = V OUT = V M since the maximum current flows through the gate at VM. 4. We assume the same current flows from PMOS and NMOS transistors to the output point
to achieve the MAXIMUM current flows during the PMOS and NMOS saturation modes as shown in figure 2. See the equation (1), (2), (3) and (4). 5. Normally, for an inverter the equation for saturation current is equation [1]:
(1)
(2)
(3)
Expressed in term of V M:
(4)
i. ii.
iii.
Based on equation [1], since μn≈2μ p therefore W p = 2W n to have the same current flowing in the inverter. The NAND gate can be described as shown in Fig. 2, where R P is active one PMOS is active, (A=0, B=1) or (A=1,B=0). Whilst, 2R N is active when (A=1,B=1). As a starting point, we can set W p = 2Wn.
Figure 2: Simplified reference NAND transistor – resistor equivalent circuit.
6. Set all NMOS transistors size (W/L) n to (0.7μm/0.4μm). To obtain the calculated PMOS width: Wp = 2 Wn = 2 x 0.7μ 0.7 μm = 1.4 μm.
Hence, the PMOS transistor size (W/L ) p is 1.4 μm/0.35 μm.
7. Run the simulation using calculated value in PSPICE and observe the VTC. V2
3.5
P1 W = {width} L = 0.35um
W = {width} L = 0.35um
PARAMETERS: width = 1.4u
M3
P1
M2 V
V1 = 0 V2 = 3.5 TD = 0 TR = 0.1m TF = 0.1m PW = 2m PER = 4m
0
V3 V
M1 W = 0.7um N1
0
V5
L = 0. 35um
3.5
0 M4 W = 0.7um N1
0
L = 0. 35um
0
4.0V
2.0V
V= 1.72V
0V 0V V ( M1 :g )
1. 0 V V( M3 : d)
2 .0 V
3. 0V
4. 0V
V_V3
VDD/2≠1.75V. However, the result is unacceptable since the VTC target, Vout/Vin ≠ VDD/2≠ 1.72V is beyond tolerance of +/- 0.15V.
8. Run the parametric sweep function. Set the value starting from 1.4 μm to 2.4μm, step size is 0.2μm.
Parametric sweep shows the varied PMOS width sizes from 1.4 μm to 2.4μ 2.4μm. 2.2μ 2.2μm of PMOS width size meets the target.
To verify the result, run the single VTC as shown below with optimized PMOS transistor (W/L) size 2.2μm/0.35μm. 8.
4.0V
2.0V
V= 1.75V
0V 0V V(M2:g)
1.0V V(M 3:d)
2.0V
3.0 V
4.0V
V_V3
2.2μ 2.2μm of PMOS width size indicates the nearest value to VDD/2=1.75V.
Homework 3: Dateline •
Soft copy on 28 October 2015.
•
Hard copy on 31 October 2015.
Question: Design and simulate a NOR gate device using PSPICE. Calculate the optimum size (W/L) for the PMOS and NMOS transistors.
