ULTRA ULTRA FAST FAST ACTING ELECTRONIC E LECTRONIC CIRCUIT BREAKER
CHAPTER 1 ABSTRACT
The steadily increasing population has more demand and consumption of electric energy in the market as raised and that of equipment’s used like electrical and electronics are also costlier. So to protect the electrical system from overload or short circuit here is one possibility, which is by ultrafast acting electronic circuit breaker. b reaker. A circuit breaker is automatic operated switch designed to shut down the power supply when overloaded. The tripping depends on the current passing through the CT’s which is connected in series with load. t uses the !C" microcontroller into which program is dumped for the operation. The unit is e#tremely fast and over comes the drawba drawback ck of therma thermall type type circui circuitt breaker breaker like $C% based based on a therma thermall bimetal bimetal lever"tr lever"trip ip mechanism which is very slow. &ere an electronic circuit breaker is designed which is based on the current sensing across a series element typically a CT 'current Transformer(. The current sensed which is compared against the preset value proportional to the voltage by comparator which is inbuilt in !C $icro controller to generate an output that drives a relay through a $)S*+T to trip the load very fastly.
CHAPTER 1 ABSTRACT
The steadily increasing population has more demand and consumption of electric energy in the market as raised and that of equipment’s used like electrical and electronics are also costlier. So to protect the electrical system from overload or short circuit here is one possibility, which is by ultrafast acting electronic circuit breaker. b reaker. A circuit breaker is automatic operated switch designed to shut down the power supply when overloaded. The tripping depends on the current passing through the CT’s which is connected in series with load. t uses the !C" microcontroller into which program is dumped for the operation. The unit is e#tremely fast and over comes the drawba drawback ck of therma thermall type type circui circuitt breaker breaker like $C% based based on a therma thermall bimetal bimetal lever"tr lever"trip ip mechanism which is very slow. &ere an electronic circuit breaker is designed which is based on the current sensing across a series element typically a CT 'current Transformer(. The current sensed which is compared against the preset value proportional to the voltage by comparator which is inbuilt in !C $icro controller to generate an output that drives a relay through a $)S*+T to trip the load very fastly.
CHAPTER 2 INTRODUCTION
n this this proec proectt electr electrica icall system system can be protec protected ted from from the over over load load conditi condition. on. ndust ndustria riall instruments or home appliances failures have many causes and one of the main causes is over load. The primary of the distribution transformer or any other transformer is designed to operate at certain specific current, if that current flowing through that instrument is more than the rated current, then immediately the System may burn because of over load, through this proect we are going to protect the system from over load condition. n this proect work for generating high current or over load current more loads are applied to the circuit- so that the current will be increased. henever the over current is drawn by load the circuit will be tripped. To trip the circuit we are using one relay which will be controlled through !C microcontroller. hen over load occurred the relay will trip the total circuit. And it will be monitored on the /C0. /C0 displays are used to display the status of circuit breaker. *or protection from over current condition first we have to measure the total load current. &ere we are using CT for measuring the load current and the output of CT is given to A0C for converting analog output of CT into digital data. &ence A0C output is given for monitoring purpose. hen current increases behind certain limit then we are going to trip the load by using relay. n this proect we are using 123v bulbs as a load. e are going to increase the load by increasing the number of bulbs )4. hen we )4 more bulbs it causes over load condition and microcontroller will detect that and it will trip the total load by using relay through $)S*+T which acts as switching circuit.
CHAPTER 3 BLOCK DIAGRAM
CHAPTER 4 COMPONENT DETAILS 4.1 Power su!" u#$% A power supply 'sometimes known as a power supply unit or !S5( is a device or o r system
that supplies supplies electrical electrical or other types of energy to an output load or group of loads. The term is most commonly applied to electrical energy supplies, less often to mechanical ones, and rarely to others.
Transforme
Rectier
Filter
Regulato
*ig6.7 %lock diagram of power supply 110VDC (AVERAGE VOLTAGE WITH AC
345V
115VA
TRANSFOR TRANSFOR MER
RECTIFIER BRIDGE
FILT ER
*ig 6.1 processing of power supply
REGULATO R
110VDC
The transformer steps up or steps down the input line voltage and isolates the power supply from the power line. The 8+CT*+8 section converts the alternating current input signal to a pulsating direct current. &owever, as you proceed in this chapter you will learn that pulsating dc is not desirable. *or this reason a */T+8 section is used to convert pulsating dc to a purer, more desirable form of dc voltage.
The final section, the 8+95/AT)8, does ust what the name implies. t maintains the output of the power supply at a constant level in spite of large changes in load current or input line voltages. 4ow that you know what each section does, let:s trace an ac signal through the power supply. At this point you need to see how this signal is altered within each section of the power supply. /ater on in the chapter you will see how these changes take place. An input signal of 77; volts ac is applied to the primary of the transformer.
The transformer is a step"up transformer with a turns ratio of 7<2. =ou can calculate the output for this transformer by multiplying the input voltage by the ratio of turns in the primary to the ratio of turns in the secondary- therefore, 77; volts ac > 2 ? 26; volts ac 'peak"to" peak( at the output. %ecause each diode in the rectifier section conducts for 7@3 degrees of the 23"degree input, the output of the rectifier will be one"half, or appro#imately 7B2 volts of pulsating dc. The filter section, a network of resistors, capacitors, or inductors, controls the rise and fall time of the varying signal- consequently, the signal remains at a more constant dc level. =ou will see the filter process more clearly in the discussion of the actual filter circuits. The output of the filter is a signal of 773 volts dc, with ac ripple riding on the dc. The reason for the lower voltage 'average voltage( will be e#plained later in this chapter. The regulator maintains its output at a constant 773"volt dc level, which is used by the electronic equipment 'more commonly called the load(. 6.7.7 S$&!e '( ower su!" )or *$+$%,! -$r-u$%s •
%rief description of operation< 9ives out well regulated ;D output, output current capability of 733 mA
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Circuit protection< %uilt"in overheating protection shuts down output when regulator C gets too hot
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Circuit comple#ity< Dery simple and easy to build
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Circuit performance< Dery stable ;D output voltage, reliable operation
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Availability of components< +asy to get, uses only ver y common basic components
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0esign testing< %ased on datasheet e#ample circuit, have used this circuit successfully as part of many electronics proects
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Applications< !art of electronics devices, small laboratory power supply
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!ower supply voltage< 5nregulated 0C @"7@D power supply
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!ower supply current< 4eeded output current ; mA
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Component costs< *ew dollars for the electronics components the input transformer cost
4.2 PIC M$-ro-o#%ro!!er PIC1/F0A
The !C microcontroller E73F is used to interface the energy measurement unit and 9S$ module. The !C microcontroller used here is !C7*@BBA.
Fe,%ures •
)nly 2; instructions are used.
•
All are single cycle instruction e#cept branch instruction.
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)perating at 0C G 13 $&H clock input.
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Timer"3 is an @"bit timerIcounter with @"bit prescaler.
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5niversal Synchronous Asynchronous 8eceiver Transmitter '5SA8T( with J"bit address detection.
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%rown " out detection circuitry for %rown"out 8eset '%)8(.
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7,333,333"eraseIwrite cycle ++!8)$ memory.
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0ata ++!8)$ retention greater then 63 years.
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!ower saving S/++! mode.
T$&er Mo*u!e
Counter mode is selected by setting bit T3CS 'option reg(. n counter mode, the timer" 3 will increment either on every raising or falling edge of pin 8A6IT3C/K. The timer3 source edge select bit, T3S+, determines the incrementing edge. Clearing bit T)S+ selects the raising edge. The prescaler is mutually e#clusively shared between the timer"3 module and atchdog timer. The prescaler value is not readable or writeable. hen no prescaler is used, the e#ternal clock input is same as the prescaler output. The synchroniHation of T3CK7 with the internal phase clock is accomplished by sampling the prescaler output on L1 and L6 cycles of the internal phase clocks. Therefore it is necessary for T3C/K to be high for at least 1Tosc and low at least 1Tosc.
U#$ers,! S"#-5ro#ous As"#-5ro#ous Re-e$er Tr,#s&$%%er 6USART7
The 5SA8T is two serial I) modules. The 5SA8T can be configured as a full duple# asynchronous system that can communicate with peripheral devices or as a half duple# synchronous system in master or slave mode. %it S!+4 i.e. 8CSTA and bit T8SC have to be set in order to configure pins 8CITMICK and 8CBI8MI0T as the 5SA8T. The 5SA8T module also has a multi"processor communication capability using J"bit address detection. The %89 support both the synchronous and asynchronous mode of the 5SA8T. t is dedicated @"bit baud rate generator. The S!%89 register controls the period of a free running @"bit timer. n
asynchronous mode, bit %89& controls the baud rate. n synchronous mode, bit %89& is ignored. t is advantageous to use high baud rate for low baud clocks.
USART $# As"#-5ro#ous Mo*e
n this mode the 5SA8T uses standard 4on"return"to Hero format. The most common data format is @"bit. The 5SA8T transmits and receives the /S% first. The transmitter and receiver functionality are independent, but use the same data format and baud rate. This mode is selected by clearing bit S=4C 'T8SA(.
n transmitter the TM8+9 register is loaded with data. The TS8 register is not loaded until the ST)! bit has been transmitted from the previous load. As soon as the ST)! bit is transmitted, the TS8 is loaded with new data from TM8+9 register. )nce the TM8+9 register transfer the data to the TS8 register, the TM8+9 register is empty and flag bit TM* is set. The interrupt can be enabledI disabled by settingIclearing"enabled bit TM+. *lag bit TM* will be set, regardless of the state of enable bit TM+ and cannot be cleared in software. t will reset only when new data is loaded into the TM8+9 register. hile flag bit TM* indicates the status of the TM8+9 register, another bit T8$T shows the status of TS8 register. The status bit T8$T is read only bit, which is set when the TS8 register is empty. Setting enable bit TM+4 enables the transmission. The actual transmission will not occur until the TM8+9 has been loaded with data and the baud rate generator '%89( has produced a shift clock. *irst loading the TM8+9 register then setting enable bit TM+4 can also start the transmission.
n reception the data is received on the 8CBI8M pin and drives the data recovery block. n the receiver side the data is received serially in shift register. The main block in receiver is receiver shift register '8S8(. After sampling the ST)! bit, the received data in the 8S8 is transformed to 8C8+9 register. f the transfer of data is completed, flag bit 8C* is set. The actual interruption can be enabled I disabled by settingIclearing enable bit 8C+. 8C* register is
cleared when the 8C8+9 has been read and is empty. 8C8+9 is a double"buffered register. t is possible for two bytes of data to be received and transferred to 8C8+9 **) and then shifted to the 8S8 register. )n the detection of the ST)! bit, if the 8C8+9 register is still full, the overrun error bit )+88 will be set. The word in the 8S8 will be lost. )verrun bit )+88 has to be cleared in the software. This is done by setting the receive logic. f the )+88 is set, transfer from the 8S8 register to the 8C8+9 is inhibited, and no further data will be received. t is essential to clear )+88 bit if it is set. *raming error bit is set if a stop bit is detected as a clear. %it *+88 and the Jth receive bit are buffered as the same way as the receive data.
RS 232 Co&&u#$-,%$o#
To allow compatibly among data communication equipment made by various manufacturers, an interfacing standard called 8S121 was set by the +lectronics ndustries Association '+A(. t was modified and called 8S121. t is most widely used for serial I) interfacing standard. This standard is used for communicating between !C microcontroller and 9S$ module. n this standard, a N7’ is represented by "2 to "7;D, while a N3’ bit is 2 to 1;D, making "2 to 2 undefined. *or this reason, to connect any 8S121 to a microcontroller system we must use voltage converter such as $AM 121 to convert the TT/ logic levels to the 8S121 voltage level, and vice versa.
4.4.1.3 I2C M,s%er Mo*e Re-e%$o#
!rogramming the 8eceive +nable bit, 8C+4, enables master mode reception. The baud rate generator begins counting, and on each rollover, the state of the SC/ pin changes 'high to lowI low to high(, and data is shifted into the SS!S8. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SS!S8 are loaded into the SS!%5*, the %* flag is set, the SS!* is set, and the baud rate generator is suspended from counting, holding SC/ low. The SS! is now in 0/+ state, awaiting the ne#t command. hen the C!5 reads the buffer, the %* flag is automatically cleared. The user can then send an
Acknowledge bit at the end of reception, by setting the Acknowledge Sequence +nable bit, ACK+4.
BF S%,%us F!,+
n a receive operation, %* is set when an address or data byte is loaded into SS!%5* from SS!S8. t is cleared when SS!%5* is read.
SSPO( ,#* 8COL S%,%us F!,+
n receive operation, SS!)D is set when @ bits are received into the SS!S8, and the %* flag is already set from a previous reception. f the user writes the SS!%5* when a receive operation is already in progress, then C)/ is set and the contents of the buffer are unchanged 'the write doesn’t occur(.
A-9#ow!e*+e Se:ue#-e T$&$#+
Setting the Acknowledge Sequence +nable bit, ACK+4, enables an Acknowledge sequence. hen this bit is set, the SC/ pin is pulled low and the contents of the Acknowledge data bit is presented on the S0A pin. f the user wishes to generate an Acknowledge, the ACK0T bit should be cleared. f not, the user should set the ACK0T bit before starting an Acknowledge sequence.
The baud rate generator then counts for one rollover period 'T%89(, and the SC/ pin is de"asserted high. hen the SC/ pin is sampled high 'clock arbitration( means, the baud rate generator counts for T%89. The SC/ pin is then pulled low. *ollowing this, the ACK+4 bit is automatically cleared, the baud rate generator is turned off, and the SS! module then goes into 0/+ mode.
S%o Co#*$%$o# T$&$#+
A ST)! bit is asserted on the S0A pin at the end of receive Itransmit by setting the Stop Sequence +nable bit, !+4. At the end of receive I transmit, the SC/ line is held low after the falling edge of the ninth clock. hen the !+4 bit is set, the master will assert the S0A line low. hen the S0A line is sampled low, the baud rate generator is reloaded and counts down to 3.
hen the baud rate generator times out, the SC/ pin will be brought high, and one T%89 'baud rate generator rollover count( later, the S0A pin will be de"asserted. hen the S0A pin is sampled high while SC/ is high, the ! bit is set. A T%89 later, the !+4 bit is cleared and the SS!* bit is set.
LCD Mo*u!e
The /C0 used is &066B@3 EJF. This used in parallel mode, which is connected to port"0 for data and port"+ for control signal of /C0. The &066B@35 dot"matri# liquid crystal display controller and driver /S displays alphanumeric. t can be configured to drive a dot" matri# liquid crystal display under the control of a 6"bit or @"bit microprocessor. Since all the functions such as display 8A$, character generator, and liquid crystal driver, required for driving a dot"matri# liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controllerIdriver.
A single &066B@35 can display up to one @"character line or two @"character lines. The &066B@35 is suitable for any portable battery"driven product requiring low power dissipation. The register of &066B@35 has two @"bit registers, an instruction register '8( and a data register '08(. The 8 stores instruction codes, such as display clear and cursor shift, and address information for display data 8A$ and character generator 8A$. The 8 can only be
written from the $!5. The 08 temporarily stores data to be written into 008A$ or C98A$ and temporarily stores data to be read from 008A$ or C98A$.
T,;!e 4.1 Re+$s%er Se!e-%$o#s RS
3
R<8
Oer,%$o#
3
8 writes as an internal operation 'display clear, etc.(
3
7
8ead busy flag '0%B( and address counter '0%3 to 0%(
7
3
08 writes as an internal operation '08 to 008A$ or 98A$(
7
7
08 read as an internal operation '008A$ or C98A$ to 08(
The /C0 module is first set in function set for @ M 1 lines by passing O2@P control word. Then it is to be set in entry mode set by command sets cursor move direction and display shift )4I)**. There are 6 possible functions set command 36, 3;, 3, and 3B. This command changes the direction the cursor moves by setting the address counter to increment or decrement. The display should be cleared by passing O37P control word. n Oentry setP mode, if we set 36 " 0isplay shift )** and decrement counter address. 3; G 0isplay shift )4 and decrement counter address. 3 G 0isplay shift )** and increment counter address. 3B G 0isplay shift )4 and increment counter address. To check the state of the busy flag and read the address counter 7. Set 8I !in of the /C0 &9& 'read from the /C0(
1. Select the instruction register by setting 8S pin /) 2. +nable the /C0 by Setting the enable pin &9& 4. The most significant bit of the /C0 data bus is the state of the busy flag '7?%usy,
3?ready to accept instructionsIdata(. The other bits hold the current value of the address counter. ON OFF CONTROL
The proposed system aims at performing automatic switching )4I)** operation of the street lights. Timed operations are done on the basis of programmed schedules using clock time. hen the clock time matches with the preprogrammed )4 time means the street lights turns )4. n the similar way when the clock time matches with the preprogrammed )** time means the street lights turns )**.
DS13 Des-r$%$o#
The 0S723B serial real"time clock '8TC( is a low"power, full binary"coded decimal '%C0( clock Icalendar plus ; bytes of 4D S8A$. Address and data are transferred serially through an 1C, bidirectional bus. The clockIcalendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adusted for months with fewer than 27 days, including corrections for leap year. The clock operates in either the 16"hour or 71"hour format with A$I!$ indicator. The 0S723B has a built"in power"sense circuit that detects power failures and automatically switches to the backup supply. Timekeeping operation continues while the part operates from the backup supply. 0s723B is used for the timing operations and the 4D8A$ in the 0S723B is used for storing the energy meter readings.
Fe,%ures
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8TC counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap"year compensation valid up to 1733.
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;"byte battery"backed 4D 8A$ for data storage.
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1"wire serial interface.
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Automatic power"fail detecting and switching circuitry. Consumes less than ;33nA in battery"backup mode
De%,$!e* Des-r$%$o#
The 0S723B E73F is a low"power clockIcalendar with ; bytes of battery"backed S8A$. The clockIcalendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adusted for months with fewer than 27 days, including corrections for leap year. The 0S723B operates as a slave device on the 1C bus. mplementing a STA8T condition and providing a device identification code followed by a register address obtain access. Subsequent register scan be accessed sequentially until a ST)! condition is e#ecuted. hen DCC falls below 7.1; # D%AT, the device terminates an access in progress and resets the device address counter. hen DCC falls below D%AT, the device switches into a low"current battery"backup mode. 5pon power"up, the device switches from battery to DCC when DCC is greater than D%AT 3.1D and recogniHes inputs when DCC is greater than 7.1; # D%AT.
RTC ,#* RAM A**ress M,
The 8TC registers are located in address locations 33h to 3Bh. The 8A$ registers are located in address locations 3@h to 2*h. 0uring a multi byte access, when the address pointer reaches 2*h, the end of 8A$ space, it wraps around to location 33h, the beginning of the clock space.
C!o-9 ,#* C,!e#*,r
The time and calendar information is obtained by reading the appropriate register bytes. The time and calendar are set or initialiHed by writing the appropriate register bytes. The contents of the time and calendar registers are in the %C0 format. The day"of"week register increments at midnight. Dalues that correspond to the day of week are user"defined but must be sequential 'i.e., if 7 equals Sunday, then 1 equals $onday, and so on.(. %it B of 8egister 3 is the clock halt 'C&( bit. hen this bit is set to 7, the oscillator is disabled. hen cleared to 3, the oscillator is enabled. The initial power"on state of all registers is not defined. Therefore, it is important to enable the oscillator 'C& bit ? 3( during initial configuration. The 0S723B can be run in either 71"hour or 16"hour mode. %it of the hours register is defined as the71"hour or 16"hour mode" select bit. hen high, the 71"hour mode is selected. n the 71"hour mode, bit ; is the A$I!$ bit with logic high being !$. n the 16"hour mode, bit ; is the second 73"hour bit '13 to12 hours(.
I2C D,%, Bus
The 0S723B supports the 1C protocol. A device that sends data onto the bu s is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock 'SC/(, controls the bus access, and generates the STA8T and ST)! conditions. The 0S723B operates as a slave on the 1C bus.
7. 0ata transfer may be initiated only when the bus is not busy. 1. 0uring data transfer, the data line must remain stable whenever the clock line is &9&. Changes in the data line while the clock line is high will be interpreted as control signals.
0epending upon the state of the 8I bit, two types of data transfer are possible<
1. D,%, Tr,#s)er )ro& , M,s%er Tr,#s&$%%er %o , S!,e Re-e$er
The first byte transmitted by the master is the slave address. 4e#t follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 0ata is transferred with the most significant bit '$S%( first.
2. D,%, Tr,#s)er )ro& , S!,e Tr,#s&$%%er %o , M,s%er Re-e$er
The first byte 'the slave address( is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a Onot acknowledgeP is returned. The master device generates the entire serial clock pulses and the STA8T and ST)! conditions. A transfer is ended with a ST)! condition or with a repeated STA8T condition. Since a repeated STA8T condition is also the beginning of the ne#t serial transfer, the bus will not be released. 0ata is transferred with the most significant bit '$S%( first. Oer,%$#+ &o*es
The 0S723B may operate in the following two modes< 1. S!,e Re-e$er Mo*e 68r$%e Mo*e7
Serial data and clock are received through S0A and SC/. After each byte is received an acknowledge bit is transmitted. STA8T and ST)! conditions are recogniHed as the beginning and end of a serial transfer. &ardware performs address recognition after reception of the slave address and direction bit.
The slave address byte is the first byte received after the master generates the STA8T condition. The slave address byte contains the B"bit 0S723B address, which is 7737333, followed by the direction bit '8I(, which for a write is 3. After receiving and decoding the slave address byte, the 0S723B outputs an acknowledgement on S0A. After the 0S723B acknowledges the
slave address write bit, the master transmits a word address to the 0S723B. This sets the register pointer on the 0S723B, with the 0S723B acknowledging the transfer.
The master can then transmit Hero or more bytes of data with the 0S723B acknowledging each byte received. The register pointer automatically increments after each data byte are written. The master will generate a ST)! condition to terminate the data write.
QSlave AddR Q8IRQord Add 'n(R S 111
3 A MMMMM MMM
Q0ata 'n(R
A MMMMM
A MMMMM
MMM
MMM
Q0ata 'n7(R A = MMMMM
S " Start A " Acknowledge 'ACK( ! " Stop $aster
Slave to
to slave
master
0ata Transferred 'M7 %ytes Acknowledge(
F$+ure 4.0 D,%, 8r$%e S!,e Re-e$er Mo*e
MMM
Q0ata 'nM(R A !
2. S!,e Tr,#s&$%%er Mo*e 6Re,* Mo*e7
The first byte is received and handled as in the slave receiver mode. &owever, in this mode, the direction bit will indicate that the transfer direction is reversed. The 0S723B transmits serial data on S0A while the serial clock is input on SC/. STA8T and ST)! conditions are recogniHed as the beginning and end of a serial transfer.
The slave address byte is the first byte received after the master generates the STA8T condition. The slave address byte contains the B"bit 0S723B address, which is7737333, followed by the direction bit '8I(, which is 7 for a read. After receiving and decoding the slave address the 0S723B outputs an acknowledgement on S0A.
The 0S723B then begins to transmit data starting with the register address pointed to by the register pointer. f the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The register pointer automatically increments after each byte are read. The 0S723B must receive a 4ot Acknowledge to end a read.
QSlave AddR Q8IR Q0ata'n(R S 111
7 A MMMMM
Q0ata'n7(R
A MMMMM
A MMMMM
MMM
MMM
MMM
S " Start A " Acknowledge 'ACK( ! " Stop A " 4ot Acknowledge '4ACK(
Q0ata'n1(R A = MMMMM MMM
Q0ata'nM(R A !
0ata transferred '#7 bytes acknowledge(- last data byte is followed by a not acknowledge 'a( signal(
$aster to slave
Slave
to master
VCC
F$+ure 4.> D,%, Re,* S!,e Tr,#s&$%%er Mo*e SQW/OUT
C
The circuit diagram for interfacing the !C microcontroller with the 0S723B is shown in *igure 6.J.
D SDA
SCL
F$+ure 4.1 DS13 I#%er),-e w$%5 PIC M$-ro-o#%ro!!er
?1 ,#* ?2 'Connections for Standard 21.B@ k&H LuartH Crystal(
The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance 'C/( of 71.;p*. M7 is the input to the oscillator and can optionally be connected to an e#ternal 21.B@k&Hoscillator. The output of the internal oscillator, M1, is floated if an e#ternal oscillator is connected to M7.
(BAT '%ackup Supply nput for Any Standard 2D /ithium Cell or )ther +nergy Source(
%attery voltage must be held between the minimum and ma#imum limits for proper operation. 0iodes in series between the battery and the D%AT pin may prevent proper operation. f a back up supply is not required, D%AT must be grounded. The nominal power"fail trip point 'D!*( voltage at which access to the 8TC and user 8A$ is denied is set by the internal circuitry as 7.1; # D%AT nominal. A lithium battery with 6@mAhr or greater will backup the 0S723B for more than 73 years in the absence of power at 1;C.
SDA 'Serial 0ata nputI )utput(
S0A is the data inputIoutput for the 1C serial interface. The S0A pin is open drain and requires an e#ternal pull up resistor.
SCL 'Serial Clock nput(
SC/ is the clock input for the 1C interface and is used to synchroniHe data movement on the serial interface.
(CC '!rimary !ower Supply(
hen voltage is applied within normal limits, the device is fully accessible and data can be written and read. hen a backup supply is connected to the device and DCC is below DT!, read and writes are inhibited. &owever, the timekeeping function continues unaffected by the lower input voltage. CURRENT TRANSFORMER
n electrical engineering, a current transformer 'CT( is used for measurement of electric currents. Current transformers, together withvoltage transformers 'DT( 'potential transformers '!T((, are known asinstrument transformers. hen current in a circuit is too high to directly apply to measuring instruments, a current transformer produces a reduced current accurately proportional to the current in the circuit, which can be conveniently connected to measuring and recording instruments. A current transformer also isolates the measuring instruments from what may be very high voltage in the monitored circuit. Current transformers are commonly used in metering and protective relays in the electrical power industry.
/ike any other transformer , a current transformer has a primary winding, a magnetic core, and a secondary winding. The alternating currentflowing in the primary produces a magnetic field in the core, which then induces a current in the secondary winding circuit. A primary obective of current transformer design is to ensure that the primary and secondary circuits are efficiently coupled, so that the secondary current bears an accurate relationship to the primary current. The most common design of CT consists of a length of wire wrapped many times around a silicon steel ring passed over the circuit being measured. The CT:s primary circuit therefore consists of a single :turn: of conductor, with a secondary of many tens or hundreds of turns. The primary winding may be a permanent part of the current transformer, with a heavy copper bar to carry current through the magnetic core. indow"type current transformers are also common, which can have circuit cables run through the middle of an opening in the core to provide a single"turn primary winding. hen conductors passing through a CT are not centered in the circular 'or oval( opening, slight inaccuracies may occur. Shapes and siHes can vary depending on the end user or switchgear manufacturer. Typical e#amples of low voltage single ratio metering current transformers are either ring type or plastic moulded case. &igh"voltage current transformers are mounted on porcelain bushings to insulate
them from ground. Some CT configurations slip around the bushing of a high"voltage transformer or circuit breaker, which automatically centers the conductor inside the CT window. The primary circuit is largely unaffected by the insertion of the CT. The rated secondary current is commonly standardiHed at 7 or ; amperes. *or e#ample, a 6333<; CT would provide an output current of ; amperes when the primary was passing 6333 amperes. The secondary winding can be single ratio or multi ratio, with five taps being common for multi ratio CTs. The load, or burden, of the CT should be of low resistance. f the voltage time integral area is higher than the core:s design rating, the core goes into saturation towards the end of each cycle, distorting the waveform and affecting accuracy.
USES
Current transformers are used e#tensively for measuring current and monitoring the operation of the power grid. Along with voltage leads, revenue"grade CTs drive the electrical utility:s watt" hour meter on virtually every building with three"phase service and single"phase services greater than 133 amps. The CT is typically described by its current ratio from primary to secondary. )ften, multiple CTs are installed as a stack for various uses. *or e#ample, protection devices and revenue metering may use separate CTs to provide isolation between metering and protection circuits, and allows current transformers with different characteristics 'accuracy, overload performance( to be used for the devices
RELA@ DRI(ER
Fe,%ures
S+D+4 0A8/49T)4S !+8 !ACKA9+
)5T!5T C588+4T ;33mA !+8 08D+8'33mA !+AK(
)5T!5T D)/TA9+ ;3D 4T+98AT+0 S5!!8+SS)4 0)0+S *)8
405CTD+ /)A0S )5T!5TS CA4 %+ !A8A//+/+0 *)8
&9&+8 C588+4T
TT/IC$)SI!$)SI0T/ C)$!AT%/+ 4!5TS 4!5TS !44+0 )!!)ST+ )5T!5TS T)
S$!/*= /A=)5T.
DESCRIPTION
The 5/41337A, 5/41331A, 5/41332 and 5/41336A are high voltage, high current darlington arrays each containing seven open collector darlington pairs with common emitters. +ach channel rated at ;33mA and can withstand peak currents of 33mA. Suppression diodes are included for inductive load driving and the inputs are pinned opposite the outputs to simplify board layout. The four versions interface to all common logic families
These versatile devices are useful for driving a wide range of loads including solenoids, relays 0C motors, /+0 displays filament lamps, thermal printheads and high power buffers. The 5/41337AI1331AI1332A and 1336A are supplied in 7 pin plastic 0! packages with a copper leadframe to reduce thermal resistance. They are available also in small outline package 'S)"7( as 5/413370I13310I13320I13360
.
LIUID CR@STAL DISPLA@
INTRODUCTION
A !$:u$* -r"s%,! *$s!," 'commonly abbreviated LCD( is a thin, flat display device made up of any number of color or monochrome pi#els arrayed in front of a light source or reflector. t is often utiliHed in battery"powered electronic devices because it uses very small amounts of electric power.
*ig J.7" /C0 $odule
O(ER(IE8
+ach pi#el of an /C0 typically consists of a layer of molecules aligned between two transparent electrodes, and two polariHing filters, the a#es of transmission of which are 'in most of the cases( perpendicular to each other. ith no liquid crystal between the polariHing filters, light passing through the first filter would be blocked by the second 'crossed( polariHer The surfaces of the electrodes that are in contact with the liquid crystal material are treated so as to align the liquid crystal molecules in a particular direction. This treatment typically consists of a thin polymer layer that is unidirectionally rubbed using, for e#ample, a cloth. The direction of the liquid crystal alignment is then defined b y the direction of rubbing. %efore applying an electric field, the orientation of the liquid crystal molecules is determined by the alignment at the surfaces. n a twisted nematic device 'still the most common liquid crystal device(, the surface alignment directions at the two electrodes are perpendicular to each other, and so the molecules arrange themselves in a helical structure, or twist. %ecause the liquid crystal material is birefringent, light passing through one polariHing filter is rotated by the liquid crystal heli# as it passes through the liquid crystal layer, allowing it to pass through the second polariHed filter. &alf of the incident light is absorbed by the first polariHing filter, but otherwise the entire assembly is transparent.
hen a voltage is applied across the electrodes, a torque acts to align the liquid crystal molecules parallel to the electric field, distorting the helical structure 'this is resisted by elastic forces since the molecules are constrained at the surfaces(. This reduces the rotation of the polariHation of the incident light, and the device appears gray. f the applied voltage is large enough, the liquid crystal molecules in the center of the layer are almost completely untwisted and the polariHation of the incident light is not rotated as it passes through the liquid crystal layer. This light will then be mainly polariHed perpendicular to the second filter, and thus be blocked and the pi#el will appear black. %y controlling the voltage applied across the liquid crystal layer
in each pi#el, light can be allowed to pass through in varying amounts thus constituting different levels of gray. The optical effect of a twisted nematic device in the voltage"on state is far less dependent on variations in the device thickness than that in the voltage"off state. %ecause of this, these devices are usually operated between crossed polariHer’s such that they appear bright with no voltage 'the eye is much more sensitive to variations in the dark state than the bright state(. These devices can also be operated between parallel polariHer’s, in which case the bright and dark states are reversed. The voltage"off dark state in this configuration appears blotchy, however, because of small thickness variations across the device. %oth the liquid crystal material and the alignment layer material contain ionic compounds. f an electric field of one particular polarity is applied for a long period of time, this ionic material is attracted to the surfaces and degrades the device performance. This is avoided either by applying an alternating current or by reversing the polarity of the electric field as the device is addressed 'the response of the liquid crystal layer is identical, regardless of the polarity of the applied field(. hen a large number of pi#els is required in a display, it is not feasible to drive each directly since then each pi#el would require independent electrodes. nstead, the display is multiplexed . n a multiple#ed display, electrodes on one side of the display are grouped and wired together 'typically in columns(, and each group gets its own voltage source. )n the other side, the electrodes are also grouped 'typically in rows(, with each group getting a voltage sink. The groups are designed so each pi#el has a unique, unshared combination of source and sink. The electronics or the software driving the electronics then turns on sinks in sequence, and drives sources for the pi#els of each sink. SPECIFICATION
mportant factors to consider when evaluating an /C0 monitor
Reso!u%$o# The horiHontal and vertical siHe e#pressed in pi#els 'e.g., 7316#B@(. 5nlike C8T
monitors, /C0 monitors have a native"supported resolution for best display effect. Do% $%-5< The distance between the centers of two adacent pi#els. The smaller the dot pitch
siHe, the less granularity is present, resulting in a sharper image. 0ot pitch may be the same both vertically and horiHontally, or different 'less common(. ($ew,;!e s$e < The siHe of an /C0 panel measured on the diagonal 'more specifically known as
active display area(. Reso#se %$&e < The minimum time necessary to change a pi#el:s color or brightness. M,%r$ %"e< Active or !assive. ($ew$#+ ,#+!e < 'coll., more specifically known as viewing direction(. Co!or suor% < &ow many types of colors are supported 'coll., more specifically known as color
gamut(. Br$+5%#ess < The amount of light emitted from the display 'coll., more specifically known as
luminance(. Co#%r,s% r,%$o < The ratio of the intensity of the brightest bright to the darkest dark. Ase-% r,%$o < The ratio of the width to the height 'for e#ample, 6<2, 7
LCD MODULE INTERFACING 8ITH MICROCONTROLLER
The /C0 $odule can easily be used with an @3;7 microcontroller such as the AT@JC13;7 included with the microcontroller beginner kit. The /C0 $odule comes with a 7 pin connector. This can be plugged into the breadboard as shown below.
*ig J.1 " /C0 nterfacing Circuit 0iagram
To connect the /C0 $odule to a standard 63 pin @3;7, use the pin names listed below to find the correct pin number on the @3;7 microcontroller. The e#ample programs below do not need to be modified to work with a 63 pin @3;7. 13;7
/C0 Connector
*unction
!in
4umber
4ame
U
/C0 Connector
13;7 *unction
!in
4umber
4ame
7
0ata /ine
7@, !7.
7
/C0 8S
B, !2.2
1
0ata /ine 7
72, !7.7
7;
0ata /ine ;
7B, !7.;
2
6
;
!ower
"
76
;D0C 4ot Connected 0isplay Adust
U
/C0 8eadIrite
, !2.1
72
0ata /ine 3
71, !7.3
71
0ata /ine 6
7, !7.6
0ata /ine B
7J, !7.B
77
/C0 +nable
@, !2.6
B
0ata /ine 1
76, !7.1
73
0ata /ine 2
7;, !7.2
@
9round
J
4ot Connected
Table J.7" /C0 Connector *unctions Connect /C0 !in 2 to Dcc '; Dolts(. Connect /C0 !in @ to 9round. Connect a ;73 ohm resistor between /C0 !in ; and ground. Connect a 1.1k ohm resistor from /C0 !in 1 and Dcc. Connect a 1.1k ohm resistor from /C0 !in 72 to Dcc.
MOSFET stands for metal o#ide semiconductor field effect transistor. t is capable of voltage
gain and signal power gain. The MOSFET is the core of integrated circuit designed as thousands of these can be fabricated in a single chip because of its very small siHe. +very modern electronic
system consists of D/ST technology and without $)S*+T, large scale integration is impossible.t is a four terminals device. The drain and source terminals are connected to the heavily doped regions. The gate terminal is connected top on the o#ide layer and the substrate or body terminal is connected to the intrinsic semiconductor . $)S*+T has four terminals which is already stated above, they are gate, source drain and substrate or body. $)S capacity present in the device is the main part. The conduction and valance bands are position relative to the *ermi level at the surface is a function of $)S capacitor voltage. The metal of the gate terminal and the sc acts the parallel and the o#ide layer acts as insulator of the state $)S capacitor . %etween the drain and source terminal inversion layer is formed and due to the flow of carriers in it, the current flows in $)S*+T the inversion layer is properties are controlled by gate voltage. Thus it is a voltage controlled device. Two basic types of $)S*+T are n channel and p channel $)S*+Ts. n n channel $)S*+T is current is due to the flow of electrons in inversion layer and in p channel current is due to the flow of holes. Another type of characteristics of clarification can be made of those are enhancement type and depletion type $)S*+Ts. n enhancement mode, these are normally off and turned on by applying gate voltage. The opposite phenomenon happens in depletion type $)S*+Ts.
W!"#$% P!#$&#' * MOSFET The working principle of $)S*+T depends up on the $)S capacitor. The $)S capacitor is the main part. The semiconductor surface at below the o#ide layer and between the drain and source terminal can be inverted from p"type to n"type by applying a positive or negative gate voltages respectively. hen we apply positive gate voltage the holes present beneath the o#ide layer e#perience repulsive force and the holes are pushed downward with the substrate. The depletion region is populated by the bound negative charges, which are associated with the acceptor atoms. The positive voltage also attracts electrons from the n source and drain regions in to the channel. The electron reach channel is formed. 4ow, if a voltage is applied between the source and the drain, current flows freely between the source and drain gate voltage controls the electrons concentration the channel. nstead of positive if apply negative voltage a hole channel will be formed beneath the o#ide layer.
4ow, the controlling of source to gate voltage is responsible for the conduction of current between source and the drain. f the gate voltage e#ceeds a given value, called the three voltage only then the conduction begins. The current equation of $)S*+T in triode region is "
here, un ? $obility of the electrons Co# ? Capacitance of the o#ide layer ? idth of the gate area / ? /ength of the channel D9S ? 9ate to Source voltage DT& ? Threshold voltage D0S ? 0rain to Source voltage.
CHAPTER '
SOFT8ARE DESCRIPTION EMBEDDED C I#%ro*u-%$o#
+mbedded c language is a basic C language designed for the embedded system for various microcontroller included in its library files. C is for desktop computers, embedded C usually is for microcontroller based applications.
C use the resource for desktop computer 'memory, )S, etc. ( embedded C use only
limited resource available in chip ' limited 8A$, 8)$, ports ,etc.( +mbedded C could be a subset of C. +mbedded C does the program for real time systems, which depends on the time.
A*,#%,+es $) e&;e**e* -
The advantages of embedded C are,
Absence of console 8estriction on code siHe The regular compile create )S dependent e#ecutable file where as a embedded computer create a file which are downloads to controller to realiHe the required task regular
compilers don’t give ace to all the resource directly so code efficient. Code written in embedded C is through not cross compatible but they are series compatible .it is very easier to maintain and co de written in C can be more productive. 3.1.3 Fe,%ures o) C )ne of the best features of C is that it is not tied to any particular hardware or system. This makes it easy for a user to write programs that will run without any changes on
practically all machines. C is often called a middle"level computer language as it combines the elements of high"
level languages with the functionalism of assembly language. To produce the most efficient machine code, the programmer must not only create an
efficient high level design, but also pay attention to detailed implementation. C is much more fle#ible than other high"level programming languages C is a structured language o C is a relatively small language o C has very loose data typing o o C easily supports low Glevel bit"wise data manipulation.
C is sometimes referred to as a Ohigh"level assembly languageP. hen compared to assembly language programming< Code written in C can be more reliable. o Code written in C can be more scalable. o Code written in C can be more portable. o Code written in C can be easier to maintain. o Code written in C can be more productive. o C retains the basic philosophy that programmers know what they are doing. C only requires that they state their intention e#plicitly. C program should be clear, concise, correct and co mmented A compiler is no more efficient than a good assembly language programmer, C is a means o
to an end and not an end itself KEIL ($s$o# IDE Oer$ew
The VDision 0+ from Keil combines proect management, make facilities, source code editing, program debugging, and complete simulation in one powerful environment. The VDision development platform is easy"to"use and helping you quickly create embedded programs that work. The VDision editor and debugger are integrated in a single application that provides a seamless embedded proect development environment. The VDision 0ebugger from Keil supports simulation using only your !C or laptop, and debugging using your target system and a debugger interface. VDision includes traditional features like simple and comple# breakpoints, watch windows, and e#ecution control as well as sophisticated features like trace capture, e#ecution profiler, code coverage, and logic analyHer.
S#+,-.#$ VDision provides everything you need to quickly develop high"fidelity simulations that help you test, debug, and prove the stability and quality of your software design.
%efore starting the VDision 0ebugger, select 5se Simulator from the !roect )ptions W 0ebug Tab to simulate programs in the debugger. Core Simulation The VDision Simulator allows you to debug programs using only your !C and device simulation drivers provided by Keil and various third"party developers. A good simulation environment, like VDision, does much more than simply simulate the instruction set of a microcontroller W it simulates your entire target system including interrupts, startup code, on"chip peripherals, e#ternal signals, and I). I#s%ru-%$o# S$&u!,%$o#
The
VDision
0ebugger
provides
complete instruction set simulation for all A8$B, A8$J, Corte#"$2, MC7#, C7#, ST73, 1;7, and @3;7 devices. hen debugging your program, op"codes are interpreted and e#ecuted as their corresponding instructions would be. =ou may view program disassembly in mi#ed mode or in assembly code.
All registers and flags are updated as each instruction e#ecutes. 8esults display in the 8egister Tab of the !roect orkspace. As you step through your program, affected registers are highlighted. nstruction timings are accurately simulated so you can easily determine how long a function or module takes to e#ecute. Timing is cycle"accurate for deterministic parts. I#%erru% S$&u!,%$o#
nterrupts are fully supported and properly simulated in the VDision 0ebugger. nterrupts are triggered and e#ecuted e#actly as they would be in a real target system.
An nterrupt System dialog bo# is designed specifically for each supported device. +ach interrupt source including all interrupt configuration options are displayed. =ou may use this dialog to interactively enable and disable interrupts, change the interrupt priority, enable or disable an interrupt request, and change the global interrupt flag. *urthermore, interrupt simulation enables you to set breakpoints within and stop program e#ecution inside an interrupt service routine. !eripheral Simulation
The VDision debugger simulates the on"chip peripherals of numerous microcontrollers. hen you select a microcontroller from the device database to configure your proect, VDision automatically configures the debugger:s peripheral simulator for you. ith its logical and timing simulation, it is possible to test an application before the target hardware is even completely designed. The simulator makes it easy to test hardware defects and critical situations which are difficult to debug with real hardware.
0IA Converter Simulation AI0 Converter AI0 Converter Simulation allows you to easily configure the AI0 Converter and simulate voltages are corresponding device pins. 0IA Converter 0IA Converter Simulation allows you to output analog voltages and monitor them using debugger scripts. I) !ort Simulation
I) !ort Simulation allows you convenient dialogs to configure and monitor I) port status. TimerICounter Timers and Counters are accurately simulated allowing your to control and measure events precisely. atchdog Timer atchdog Timer Simulation helps you determine how often and where to reset the watchdog in your application. CaptureICompare CaptureICompare Simulation allows you to view and change the configuration of the capcom units fond on many devices. Serial Communications Serial Communications Simulation provides a serial window and dialog that help you configure and communicate using your device:s on"chip 5A8T. CA4 Communication Simulation CA4 Communications Simulation provide dialogs for CA4 configuration and message logging. 0ebugger scripts may be used to generate CA4 bus traffic and respond to simulated message traffic.
XC Simulation
XC Communications Simulation allows you to configure XC and view messages sent and received. 0ebugger scripts may be used to generate and respond to XC messages. S! Communication Simulation S! Communications Simulation allows you to simulate master and slave S! devices. */AS& $emory Simulation */AS& $emory Simulation gives you access to all control registers of on"chip */AS&I++ memory. All memory contents may be viewed and modified in real"time. T,r+e% De;u++$#+
VDision provides several interfaces to target hardware debuggers 'like 5/4K and the variety of target monitors provided by Keil(. Additional hardware drivers are provided by target debugger hardware providers 'emulator companies(.
%efore starting the VDision 0ebugger, select the target driver from the !roect )ptions W 0ebug Tab to specify which target interface to use. S%,r%$#+ %5e ($s$o# De;u++er
hen you click the S%,r% De;u+ Sess$o# button on the toolbar, VDision starts the debugger using the appropriate simulation or target debug driver.
TAG I#%er),-e
The VDision 0ebugger supports several different YTA9"based debugging options. These options use a YTA9 'Yoint Test Action 9roup( interface which allows VDision to communicate with your target system.
Support is available for< •
The 5/4K1 5S%"YTA9 Adapter which supports A8$, Corte#"$2, MC7#, and V!S0 devices.
•
Third"party debuggers that comply with the A8$ 80 '8emote 0ebugger nterface(.
)nce you select the appropriate YTA9 debugger, VDision provides a dialog where you set the parameters specific to your target system.
T,r+e% Mo#$%or
The Target $onitor is a program 'provided by Keil( that you configure, compile, load, and run on your target hardware. t communicates 'usually via the serial port( with the VDision 0ebugger and allows you download and debug your programs in real time. The Keil $onitor comes pre" installed on many evaluation boards.
Several different Target $onitors are available. The monitor you use depends on the device and hardware configuration of your target system. The monitor driver is selected on the 0ebug Tab of the !roect )ptions 0ialog. The Settings button opens a dialog with numerous configuration options.
•
$)47 $)47 is a full"featured, license"free, royalty"free target monitor designed for debugging C7# or MC7#"compatible target systems with von 4eumann code memory.
•
$)41;7 $)41;7 is a full"featured, license"free, royalty"free target monitor designed for debugging 1;7"compatible target systems with von 4eumann code memory.
•
$)4;7 $)4;7 is a full"featured, license"free, royalty"free target monitor designed for debugging @3;7"compatible target systems with von 4eumann cod e memory.
•
$)42J3 $)42J3 is a full"featured, license"free, royalty"free target monitor designed for debugging target systems based on the 0allas Semiconductor 0S@3C2J3, 0S@3C633, or 0S;163.
•
MONADI
$)4A0 is a full"featured, license"free, royalty"free target monitor designed for debugging target systems based on the Analog 0evices A0uc@71 and compatible devices. •
*lash$)4;7 *lash$on;7 is a full"featured, license"free, royalty"free target monitor for debugging @3;7"compatible target systems that have either von 4eumann code memory or *lash memory.
•
S0;7 S0;7 'n"System 0ebugger( is a new debug monitor technology for @3;7 user programs. S0;7 consists of a configurable debug module that you link to your user programs to provide support for program testing via the @3;7 on"chip 5A8T.
F!,s5 Pro+r,&&$#+
*lash 0evice !rogramming is available within the VDision 0+. All *lash configuration options are stored with your proect.
Click the Dow#!o,* %o F!,s5 button on the toolbar to download your target program into the *lash memory of your target system. Two methods of *lash support are available< •
F!,s5
Pro+r,&&$#+
Us$#+
,
T,r+e%
Dr$er
A number of target debugger drivers are available for VDision. These drivers directly interface to target debugging hardware and support debugging programs running on target systems. The following drivers integrate support for *lash programming, as well. o
Analog 0evices $onitor 0river
o
+!$J33 +mulatorI!rogrammer
o
80 nterface '8emote 0ebugger for A8$ 0evices(
•
o
Silicon /abs 0ebug 0river
o
5/4K for A8$B, A8$J, Corte#"$2, ST V!S0, and nfineon MC@33 U MC7#
F!,s5
Pro+r,&&$#+
Us$#+
,#
E%er#,!
Too!
Third"party *lash programming tools, which typically run from the command prompt, are easy to integrate into the VDision environment. The *lash programming method is selected on the *lash tab in the !roect )ptions 0ialog.
F- P!%!-++#$% U#$% - T-!%. D!#!
5sing a target driver to program the *lash memory of your embedded target system requires that you select the appropriate *lash memory and its physical address range. This is required since there are many different algorithms for programming *lash memory. A large number of pre" configured programming algorithms are included with the Keil tools.
The procedure for creating algorithms to support new devices is well"documented. So, you can easily add support for new algorithms or devices.
F- P!%!-++#$% U#$% -$ E2.!$- T
CHAPTER / CONCLUSION
4ow A days the protection and control of equipment plays a very important role. To avoid electrical failure we use fast responding circuit breakers because of its considerable accuracy in fault detection and cut off" time, and also its smooth operation compared to conventional type. Fu%ure S-oe
The operating time of electromagnetic relay can be improved by using sophisticated electronic components. REFFERENCE
E7F8a kamal G$icrocontrollers Architecture, rogramming, nterfacing and System 0esign. E1F$aHidi and $aHidi G+mbedded Systems. E2F!C"$icrocontroller $anual G $icrochip. E6FA $ S Almadi U Y 9 Y Sloot review of Current limitting +++. E;FT. 9eni , 4akamar< high speed circuit %reaker for electric power system.
