ELEC3230 Notes - Switching Electronics R.E. Betz School of Electrical Engineering and Computer Science University of Newcastle, Australia. email:
[email protected] c 1999, 2000, 2001, 2002, 2003, 2004 Created: May 24, 1999 Revised: July 19, 2004
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Preface The notes in this document are for a course in the School of Electrical Engineering and Computer Science at the University of Newcastle, Australia. This course covers a number of topics that can be broadly grouped under the title of “switching electronics”. Electronic switching is the unifying factor that provides the theme for the course. The notes were written because the subject material covers such diverse areas as digital logic switching families, switched transmission lines and printed circuit boards, switch mode power supplies (SMPSs), and (to a lesser degree) converters. No single text book covers such material. The general approach of the course is to emphasise the practical aspects of switching and how design has to be changed to account for its effects. The theory behind many of these ideas is presented in detail in the appendices. This is particularly true in relation to switching in digital systems with transmission lines. The structure of the course is as follows. The first part will consider a variety of issues related to switching in digital systems. This will include a review of logic families and interfacing of different logic families. Then issues related to interfacing logic components on a printed circuit board will be considered. This will include noise issues, transmission line effects, terminations, cross coupling, printed circuit board layout, decoupling issues. The second section of the course will look at switch mode power supplies in their various forms. The main structures for switch mode power supplies will be considered. Again practical issues will be emphasised. Design of the magnetics for switching supplies will be considered, as well as some control issues. The control issues are only briefly considered due to the lack of background of some students doing the course. The final part of the course considers high powered converter and inverter topologies. At this stage there is only an introduction to high power switching devices, and a brief look at naturally commutate converters, mostly single phase. Eventually there will be a reasonable treatment of three phase naturally converters and forced commutated inverters (using thyristors as well as transistors).
Robert E. Betz – Newcastle, Australia, July 19, 2004.
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Revision History 1999 First version of the notes created for the 5 credit point subject ELEC322. Only included the digital switching and transmission line material. 2000 A major upgrade of the material to include switch mode power supplies, and some material on higher powered converters. This upgrade was necessary because the subject changed from ELEC322 to ELEC323, and doubled in credit points to 10. 2001 Prior to the issue of the notes, corrections were made to the notes from 2000. Added a chapter on the practical design of switch mode power supplies. Minor corrections and additions made to the notes through the course of 2001. March 2002 Minor corrections and additions made. July 2002 Made further minor typographical corrections. July 2003 Further typographical corrections, added section on capacitively coupled load terminations, fixed the equivalent circuit of the home brew probe. Added a new chapter to briefly introduce other power electronic circuits not already considered in the notes. Added the course outline, schedule, and Saber introductory exercise to the appendix. August 19, 2003 Made a few typo corrections as well as a change to an incorrect diagram. July 19, 2004 Made typo corrections and added extra remarks in relation to magnetic utilisation with push-pull converters. Also added an extra remark in relation to the derivation of the fact that harmonics do not contribute to real power. Corrected a few minor diagram errors. Added the assignments to the appendices.
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Contents List of Figures
xi
List of Tables
I
xix
Digital Systems
1 Logic Families 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . 1.2 Review of Logic Family Properties . . . . . . . . 1.2.1 A Brief History . . . . . . . . . . . . . . . 1.2.2 The CMOS Logic Family . . . . . . . . . 1.2.2.1 Logic Levels and Noise Margins 1.2.2.2 Fanout . . . . . . . . . . . . . . 1.2.2.3 Specific CMOS Logic Families . 1.2.3 Bipolar Logic Families . . . . . . . . . . . 1.2.3.1 Bipolar Logic Noise Margins . . 1.2.3.2 Fanout . . . . . . . . . . . . . . 1.2.3.3 Specific TTL Logic Families . . 1.3 Issues in TTL–CMOS Interfacing . . . . . . . . .
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2 2 2 2 3 6 9 9 10 12 12 13 13
2 Introduction to Digital Switching 16 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Relevant Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Propagation, Time and Distance . . . . . . . . . . . . . . . . . . 18 2.4 Lumped Versus Distributed Systems . . . . . . . . . . . . . . . . 18 2.5 Four Kinds of Reactance . . . . . . . . . . . . . . . . . . . . . . . 20 2.5.1 Ordinary Capacitance . . . . . . . . . . . . . . . . . . . . 20 2.5.2 Ordinary Inductance . . . . . . . . . . . . . . . . . . . . . 22 2.5.3 Mutual Capacitance . . . . . . . . . . . . . . . . . . . . . 28 2.5.3.1 Relationship between Mutual Capacitance and Crosstalk . . . . . . . . . . . . . . . . . . . . . . 28 2.5.4 Mutual Inductance . . . . . . . . . . . . . . . . . . . . . . 33 2.5.4.1 Relationship Between Mutual Inductance and Crosstalk . . . . . . . . . . . . . . . . . . . . . . 36 2.6 Speed of Digital Systems . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.1 dv/dt Effects . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.2 di/dt Effects . . . . . . . . . . . . . . . . . . . . . . . . . 41
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CONTENTS 2.6.3
2.6.4 2.6.5
2.6.6
Ground Bounce . . . . . . . . . . . . . . . . . . . . . . . . 2.6.3.1 Why Does Ground Bounce Occur? . . . . . . . . 2.6.3.2 How Does Ground Bounce Affect Circuits? . . . 2.6.3.3 Estimating Ground Bounce Magnitude . . . . . 2.6.3.4 Reducing Ground Bounce . . . . . . . . . . . . . Lead Capacitance . . . . . . . . . . . . . . . . . . . . . . Measurement Issues . . . . . . . . . . . . . . . . . . . . . 2.6.5.1 Rise Time and Bandwidth of CROs . . . . . . . 2.6.5.2 Self-inductance of CRO Probe Ground Clips . . 2.6.5.3 Mutual-inductance of CRO Probe Ground Clips 2.6.5.4 Loading Effect of CRO Probes . . . . . . . . . . Better Probing Techniques . . . . . . . . . . . . . . . . . 2.6.6.1 Home Brew 21:1 Probe . . . . . . . . . . . . . . 2.6.6.2 Low Inductance with Conventional Probes . . . 2.6.6.3 PCB Test Points . . . . . . . . . . . . . . . . . . 2.6.6.4 Shield Currents and Ground Loops . . . . . . .
3 Point-to-Point Wiring and Transmission Lines 3.1 Shortcomings of Point-to-Point Wiring . . . . . . . . . . . . . 3.1.1 EMI Radiation . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Uniform Transmission Lines . . . . . . . . . . . . . . . . . . . 3.2.1 Measurement of Distributed Parameters . . . . . . . . 3.2.2 Alternative Way of Deriving Characteristic Impedance 3.2.3 Physical Explanation of Reflections . . . . . . . . . . . 3.3 Modelling of Transmission Lines . . . . . . . . . . . . . . . . 3.4 Some Practical Effects in Transmission Lines . . . . . . . . . 3.4.1 Skin Effect . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Proximity Effect . . . . . . . . . . . . . . . . . . . . . 3.4.3 Dielectric Losses . . . . . . . . . . . . . . . . . . . . . 3.5 Termination of Transmission Lines . . . . . . . . . . . . . . . 3.5.1 General Effects of Source and Load Impedance . . . . 3.5.1.1 Load termination . . . . . . . . . . . . . . . 3.5.1.2 Source Termination . . . . . . . . . . . . . . 3.5.1.3 Very Short Line . . . . . . . . . . . . . . . . 3.5.2 Capacitive Terminations . . . . . . . . . . . . . . . . . 3.5.2.1 Equally Spaced Capacitive Loads . . . . . . 3.5.3 Multi-point Terminations . . . . . . . . . . . . . . . .
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44 44 45 47 47 48 49 49 51 57 59 62 62 66 66 69
73 . 73 . 75 . 76 . 77 . 77 . 79 . 80 . 82 . 83 . 83 . 86 . 87 . 87 . 89 . 93 . 93 . 95 . 96 . 97 . 100
4 Ground Planes and other Printed Circuit Board Issues 108 4.1 Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.1.1 Decoupling Capacitors and Power Planes . . . . . . . . . 110 4.2 Crosstalk Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.2.1 Path of Least Inductance . . . . . . . . . . . . . . . . . . 111 4.2.1.1 Crosstalk in Ground Planes . . . . . . . . . . . . 113 4.2.1.2 Crosstalk in Slotted Ground Planes . . . . . . . 114 4.2.1.3 Crosstalk in Two Layer PCBs . . . . . . . . . . 116 4.2.1.4 Crosstalk in with Power and Ground Finger PCBs118 4.2.1.5 A Note on Guard Traces . . . . . . . . . . . . . 119 4.2.1.6 Distributed Cross Coupling . . . . . . . . . . . . 119
CONTENTS
II
Switched Mode Power Supplies
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5 Fundamental Topologies 126 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.3 Taxonomy of Switch Mode Converters . . . . . . . . . . . . . . . 127 5.3.1 Step-down or Buck Converters . . . . . . . . . . . . . . . 127 5.3.2 Step-up or Boost Converters . . . . . . . . . . . . . . . . 129 5.3.3 Buck–Boost Converters . . . . . . . . . . . . . . . . . . . 130 5.3.4 C´ uk Converters . . . . . . . . . . . . . . . . . . . . . . . . 132 5.3.5 Full Bridge Converters . . . . . . . . . . . . . . . . . . . . 134 5.4 Basic Analysis of Switch Mode Converters . . . . . . . . . . . . . 136 5.4.1 Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.4.2 Basic PWM Generator . . . . . . . . . . . . . . . . . . . . 137 5.4.3 Simplified Analysis of the Buck Converter . . . . . . . . . 139 5.4.3.1 Continuous Conduction Mode . . . . . . . . . . 139 5.4.3.2 Boundary between Continuous and Discontinuous Conduction . . . . . . . . . . . . . . . . . . 141 5.4.3.2.1 Discontinuous Current with Constant Vd . . . . . . . . . . . . . . . . . . . . . 142 5.4.3.2.2 Discontinuous Current with Constant Vo .145 5.4.3.3 Output Ripple . . . . . . . . . . . . . . . . . . . 147 5.4.3.4 Simulation . . . . . . . . . . . . . . . . . . . . . 149 5.4.4 Simplified Analysis of the Boost Converter . . . . . . . . 151 5.4.4.1 Continuous Conduction Mode . . . . . . . . . . 152 5.4.4.2 Boundary between Continuous and Discontinuous Conduction . . . . . . . . . . . . . . . . . . 153 5.4.4.2.1 Discontinuous Current with Constant Vd . . . . . . . . . . . . . . . . . . . . . 156 5.4.4.3 Simulation . . . . . . . . . . . . . . . . . . . . . 159 5.4.5 A Brief Look at the Buck-Boost Converter . . . . . . . . 159 5.4.6 A Brief Analysis of the C´ uk Converter . . . . . . . . . . . 161 5.4.7 Full Bridge dc-dc Converter . . . . . . . . . . . . . . . . . 162 5.4.7.1 Bipolar Switching . . . . . . . . . . . . . . . . . 163 5.4.7.2 Unipolar Switching . . . . . . . . . . . . . . . . 166 5.4.8 Comparison of Basic Converter Topologies . . . . . . . . . 168 5.4.8.1 Switch Utilisation . . . . . . . . . . . . . . . . . 168 5.4.8.1.1 Buck Converter . . . . . . . . . . . . . 169 5.4.8.1.2 Boost Converter . . . . . . . . . . . . . 169 5.4.8.1.3 Buck-Boost Converter . . . . . . . . . . 170 5.4.8.1.4 Full Bridge Converter . . . . . . . . . . 171 5.4.9 Synchronous Rectifiers . . . . . . . . . . . . . . . . . . . . 173 5.4.10 Resonant and Soft-Switching Converters . . . . . . . . . . 173 5.4.10.1 Why One Should Not Use Resonant Converters 176 5.4.10.2 Why One Should Use Quasi-Resonant Converters 176
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CONTENTS 6 Switch Mode Power Supplies 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Isolated Converter Topologies . . . . . . . . . . . . . . . . . . . . 6.2.1 The Forward Converter . . . . . . . . . . . . . . . . . . . 6.2.1.1 Other Forward Converter Topologies . . . . . . . 6.2.1.1.1 Two Switch Converter . . . . . . . . . . 6.2.1.1.2 Push-Pull Converter . . . . . . . . . . . 6.2.2 The Flyback Converter . . . . . . . . . . . . . . . . . . . 6.2.3 Utilisation of Magnetics . . . . . . . . . . . . . . . . . . . 6.3 Introduction to Control Techniques for Switching Power Supplies 6.3.1 Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Protection Issues . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.1 Soft Start . . . . . . . . . . . . . . . . . . . . . . 6.3.2.2 Voltage Protection . . . . . . . . . . . . . . . . . 6.3.2.3 Current Limiting . . . . . . . . . . . . . . . . . . 6.3.3 Control Architecture of a Switch Mode Power Supply System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3.1 Voltage Mode Control . . . . . . . . . . . . . . . 6.3.3.2 Voltage Feed-forward PWM Control . . . . . . . 6.3.3.3 Current Mode Control . . . . . . . . . . . . . . . 6.3.3.3.1 Slope Compensation . . . . . . . . . . . 7 Introduction to Practical Design of Switch Mode Power plies 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Component Selection . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1.1 Values . . . . . . . . . . . . . . . . . . . . . 7.2.1.2 Resistor Types . . . . . . . . . . . . . . . . 7.2.1.3 Tolerance . . . . . . . . . . . . . . . . . . . 7.2.1.4 Selecting Values . . . . . . . . . . . . . . . 7.2.1.5 Maximum Voltage . . . . . . . . . . . . . . 7.2.1.6 Temperature Coefficient . . . . . . . . . . . 7.2.1.7 Power Rating . . . . . . . . . . . . . . . . . 7.2.1.8 Shunts . . . . . . . . . . . . . . . . . . . . 7.2.1.9 PCB Track Resistors . . . . . . . . . . . . 7.2.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . 7.2.2.1 Types of Capacitors . . . . . . . . . . . . . 7.2.2.2 Standard Values . . . . . . . . . . . . . . . 7.2.2.3 Tolerance . . . . . . . . . . . . . . . . . . . 7.2.2.4 ESR and Power Dissipation . . . . . . . . . 7.2.2.5 Aging . . . . . . . . . . . . . . . . . . . . . 7.2.2.6 dv/dt Rating . . . . . . . . . . . . . . . . . 7.2.2.7 Series Connection of Capacitors . . . . . . 7.2.3 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3.1 Schottky Diodes . . . . . . . . . . . . . . . 7.2.3.2 PN diodes . . . . . . . . . . . . . . . . . . 7.2.4 The BJT . . . . . . . . . . . . . . . . . . . . . . . . 7.2.5 The MOSFET . . . . . . . . . . . . . . . . . . . . . 7.2.5.1 Bi-directional Conduction . . . . . . . . . .
178 178 178 178 183 184 184 189 194 199 201 204 204 204 205 207 207 209 209 212
Sup218 . . . 218 . . . 218 . . . 219 . . . 219 . . . 219 . . . 220 . . . 220 . . . 220 . . . 221 . . . 221 . . . 222 . . . 223 . . . 223 . . . 224 . . . 224 . . . 225 . . . 225 . . . 225 . . . 226 . . . 226 . . . 226 . . . 226 . . . 227 . . . 229 . . . 229 . . . 230
CONTENTS
7.3
7.2.5.2 Power Losses . . . . . . . . . . . . . . . . . . . . 7.2.5.3 MOSFET Gate Resistors . . . . . . . . . . . . . 7.2.5.4 Maximum Gate Voltage . . . . . . . . . . . . . . 7.2.6 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . 7.2.6.1 Offsets . . . . . . . . . . . . . . . . . . . . . . . 7.2.6.1.1 Input Offset Voltage . . . . . . . . . . . 7.2.6.1.2 Input Offset Current . . . . . . . . . . . 7.2.6.1.3 Input Bias Current . . . . . . . . . . . 7.2.6.2 Limits on Resistor Values . . . . . . . . . . . . . 7.2.6.3 Gain-Bandwidth Product . . . . . . . . . . . . . 7.2.6.4 Phase Shift . . . . . . . . . . . . . . . . . . . . . 7.2.6.5 Slew Rate Limits . . . . . . . . . . . . . . . . . . 7.2.7 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.7.1 Hysteresis . . . . . . . . . . . . . . . . . . . . . . 7.2.7.2 Comparator Interfacing . . . . . . . . . . . . . . Introduction to Magnetics Design . . . . . . . . . . . . . . . . . . 7.3.1 Review of the Fundamentals . . . . . . . . . . . . . . . . 7.3.1.1 Ampere’s Law . . . . . . . . . . . . . . . . . . . 7.3.1.2 Faraday’s Law . . . . . . . . . . . . . . . . . . . 7.3.1.3 Inductance . . . . . . . . . . . . . . . . . . . . . 7.3.1.4 A Note on Units . . . . . . . . . . . . . . . . . . 7.3.1.5 The Three R’s . . . . . . . . . . . . . . . . . . . 7.3.1.5.1 Reactance . . . . . . . . . . . . . . . . 7.3.1.5.2 Remanence . . . . . . . . . . . . . . . . 7.3.1.5.3 Reluctance . . . . . . . . . . . . . . . . 7.3.2 The Ideal Transformer . . . . . . . . . . . . . . . . . . . . 7.3.3 Real Transformers . . . . . . . . . . . . . . . . . . . . . . 7.3.3.1 Core Materials . . . . . . . . . . . . . . . . . . . 7.3.3.2 Saturation . . . . . . . . . . . . . . . . . . . . . 7.3.3.3 Other Core Limitations . . . . . . . . . . . . . . 7.3.3.3.1 Curie Temperature . . . . . . . . . . . 7.3.3.3.2 Core Losses . . . . . . . . . . . . . . . . 7.3.4 Optimal Design Issues . . . . . . . . . . . . . . . . . . . . 7.3.5 Design of an Inductor . . . . . . . . . . . . . . . . . . . . 7.3.5.1 Key Magnetic Parameters . . . . . . . . . . . . . 7.3.5.1.1 Initial Permeability . . . . . . . . . . . 7.3.5.1.2 Effective Permeability . . . . . . . . . . 7.3.5.1.3 Amplitude Permeability . . . . . . . . . 7.3.5.1.4 Incremental Permeability . . . . . . . . 7.3.5.1.5 Effective Core Dimensions . . . . . . . 7.3.5.1.6 Inductance Factor . . . . . . . . . . . . 7.3.5.2 Details of Inductor Design . . . . . . . . . . . . 7.3.5.3 Issues in Forward Converter Transformer Design 7.3.5.3.1 Turns Ratio = 1:1 . . . . . . . . . . . . 7.3.5.3.2 Turns Ratio = 2:1 . . . . . . . . . . . . 7.3.5.3.3 Turns Ratio = 3:1 . . . . . . . . . . . . 7.3.5.3.4 Turns Ratio = 4:1 . . . . . . . . . . . . 7.3.6 Design of Manufacturable Magnetics . . . . . . . . . . . . 7.3.6.1 Wire Gauge . . . . . . . . . . . . . . . . . . . . 7.3.6.2 Wire Gauge Ratio . . . . . . . . . . . . . . . . .
xi 230 231 231 231 232 232 233 233 234 236 236 237 237 237 239 239 240 240 241 241 242 243 243 243 244 244 246 247 247 249 249 249 250 252 255 255 255 255 255 256 256 257 263 264 264 264 264 265 265 265
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CONTENTS 7.3.6.3 7.3.6.4 7.3.6.5 7.3.6.6 7.3.6.7 7.3.6.8
Toroidal Core Winding Limits Tape versus Wire Insulation . Layering of Windings . . . . . Number of Windings . . . . . Potting . . . . . . . . . . . . . Safety Requirements . . . . . .
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III Line Commutated Converters and High Power Inverters 269 8 Introduction to High Power Converter Technology 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 Applications of Power Converter Technology . . 8.2 Review of Power Semiconductor Devices . . . . . . . . . 8.2.1 Diodes . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Thyristors . . . . . . . . . . . . . . . . . . . . . . 8.2.2.1 Turn-on Transient . . . . . . . . . . . . 8.2.2.2 Turn-off Transient . . . . . . . . . . . . 8.2.3 Gate Turn-off Thyristors . . . . . . . . . . . . . . 8.2.3.1 Snubbers and GTO Thyristors . . . . . 8.2.3.2 GTO Turn-on . . . . . . . . . . . . . . 8.2.3.3 GTO Turn-off . . . . . . . . . . . . . . 8.2.4 Insulated Gate Bipolar Transistors (IGBTs) . . . 8.2.4.1 IGBT Operation . . . . . . . . . . . . . 8.2.4.2 IGBT Turn-on . . . . . . . . . . . . . . 8.2.4.3 IGBT Turn-off . . . . . . . . . . . . . . 8.2.5 Other Devices and Developments . . . . . . . . . 8.2.5.1 Power Junction Field Effect Transistors 8.2.5.2 Field Controlled Thyristor . . . . . . . 8.2.5.3 MOS-Controlled Thyristors . . . . . . . 8.2.5.4 New Semiconductor Materials . . . . .
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9 Line Frequency Uncontrolled Rectifiers 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Some Mathematical Preliminaries . . . . . . . . . . . . . . . . . . 9.2.1 Fourier Analysis of Repetitive Waveforms . . . . . . . . . 9.2.1.1 Measures of Waveform Distortion . . . . . . . . 9.2.1.2 Power and Power Factor . . . . . . . . . . . . . 9.3 The Half Wave Rectifier Circuit . . . . . . . . . . . . . . . . . . . 9.3.1 Pure Resistive Load . . . . . . . . . . . . . . . . . . . . . 9.3.2 Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . 9.3.3 Inductive Load with Back EMF . . . . . . . . . . . . . . . 9.4 The Concept of Current Commutation . . . . . . . . . . . . . . . 9.5 Practical Uncontrolled Single Phase Rectifiers . . . . . . . . . . . 9.5.1 Unity Power Factor Single Phase Rectifier . . . . . . . . . 9.5.2 Effect of Current Harmonics on Line Voltages . . . . . . . 9.5.3 Voltage Doubler Single Phase Rectifiers . . . . . . . . . . 9.5.4 The Effect of Single Phase Rectifiers on Three Phase, Four Wire Systems . . . . . . . . . . . . . . . . . . . . . . . . .
270 270 271 272 272 276 279 281 282 283 285 286 289 289 292 292 293 293 293 294 294 299 299 299 300 301 303 308 308 309 311 312 317 323 328 329 330
CONTENTS 9.6
xiii
Three Phase, Full Bridge Rectifiers . . . . . . . . . . . . . . . . . 332
10 Introduction to Other Power Electronic Devices and Applications 335 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 10.2 Inverters and Applications . . . . . . . . . . . . . . . . . . . . . . 335 10.2.1 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . 338 10.2.1.1 Space Vectors and PWM . . . . . . . . . . . . . 342 10.2.2 Dead-time Issues . . . . . . . . . . . . . . . . . . . . . . . 347 10.2.3 Some Inverter Applications . . . . . . . . . . . . . . . . . 349 10.2.3.1 Variable Speed Drives . . . . . . . . . . . . . . . 349 10.2.3.2 Grid Connected Applications . . . . . . . . . . . 350 10.3 Multilevel Converters and Applications . . . . . . . . . . . . . . . 352 10.4 Matrix Converters . . . . . . . . . . . . . . . . . . . . . . . . . . 352
IV
Appendices
353
A List of Course Materials B Course Outline B.1 Text . . . . . . . . . . . . B.2 Introduction . . . . . . . . B.3 Course Objectives . . . . B.4 Plagiarism . . . . . . . . . B.5 Special Consideration . . B.6 Changing Your Enrolment B.7 Support Services . . . . .
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C Course Schedule
355 355 355 356 357 357 357 358 359
D Introductory Exercise using Saber Simulator D.1 Introduction . . . . . . . . . . . . . . . . . . . . D.2 Circuit Schematic Capture . . . . . . . . . . . . D.3 Executing the Transient Analysis . . . . . . . . D.4 Plotting and Processing Results . . . . . . . . . D.4.1 Manipulating Results . . . . . . . . . . D.4.2 Fourier Analysis . . . . . . . . . . . . . D.5 A Practice Exercise . . . . . . . . . . . . . . . .
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361 361 362 366 367 368 371 372
E Assignment 1 375 E.1 How to Answer the Questions . . . . . . . . . . . . . . . . . . . . 376 E.2 Software Tools to Aid Report Production . . . . . . . . . . . . . 376 F Assignment 2 F.1 Introduction . . . . . . . . . F.2 Equipment Required . . . . F.3 The Experiments . . . . . . F.3.1 The Buck Converter F.3.2 Boost converter . . . F.3.3 Forward converter .
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383 383 385 385 385 386 388
xiv
CONTENTS G Review of Second Order Circuits G.1 Series RLC Circuits . . . . . . . G.1.1 Quality Factor . . . . . . G.1.2 Time Domain Response . G.2 Parallel RLC Circuits . . . . . . G.2.1 Quality Factor . . . . . .
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390 390 393 394 395 397
H Review of Transmission Lines H.1 Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . H.2 Solution of Transmission Line Equations for the Lossless Case H.2.1 Semi-infinite Transmission Line . . . . . . . . . . . . . H.2.2 Finite Transmission Line and Reflection Coefficient . . H.3 Reflection Diagrams . . . . . . . . . . . . . . . . . . . . . . . H.4 Time Harmonic Solutions for Lossy Lines . . . . . . . . . . . H.4.1 Solutions for Voltage and Currents . . . . . . . . . . . H.4.2 Semi-infinite Transmission Line . . . . . . . . . . . . . H.4.3 Finite Length Transmission Lines . . . . . . . . . . . . H.4.4 Line Input Impedance . . . . . . . . . . . . . . . . . . H.4.4.1 Lossless Line Input Impedance . . . . . . . . H.4.5 Transfer Function of a Lossless Transmission Line . . H.4.6 Thevenin Equivalent Circuit . . . . . . . . . . . . . . .
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399 402 403 408 409 412 415 417 418 421 422 424 424 425
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427 427 427 427 427 428 429 429 430 430 430 431 431 432 433 434 435 435
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Useful Formulae I.1 Introduction . . . . . . . . . . . . . . . . . . . . . . I.2 Useful Constants . . . . . . . . . . . . . . . . . . . I.3 Formulae . . . . . . . . . . . . . . . . . . . . . . . I.3.1 AWG Related Conversions . . . . . . . . . . I.3.2 Copper Plate Weight Formulae . . . . . . . I.3.3 Parallel Plate Capacitance . . . . . . . . . . I.3.4 Inductance of Circular Wire Loops . . . . . I.3.5 Inductance of Rectangular Loops . . . . . . I.3.6 Mutual Inductance of Two Loops . . . . . . I.3.7 Mutual Inductance of Parallel Transmission I.3.8 General Transmission Line Expressions . . I.3.9 Coaxial Transmission Line . . . . . . . . . . I.3.10 Single Wire Above a Ground Plane . . . . . I.3.11 Twisted Pair Transmission Line . . . . . . . I.3.12 Microstrip Transmission Line . . . . . . . . I.3.13 Symmetric Stripline Transmission Line . . . I.3.14 Offset Stripline Transmission Line . . . . .
Bibliography
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437
List of Figures 1.1 1.2 1.3 1.4 1.5 1.6 1.7
Block diagram of an enhancement mode n-channel MOSFET. Common circuit symbols for enhancement mode MOSFETs. . CMOS inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . Typical transfer characteristic for a CMOS inverter. . . . . . Noise margin and generic logic level definitions. . . . . . . . . Typical circuit for a TTL NAND gate. . . . . . . . . . . . . . Worst case logic levels with TTL loadings. . . . . . . . . . . .
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24
Approximate transmission line. . . . . . . . . . . . . . . . . . . . Time domain plots of voltages along a transmission line. . . . . . Voltage versus distance along a transmission line. . . . . . . . . . Examples of capacitive circuit waveforms. . . . . . . . . . . . . . Examples of inductance circuit waveforms. . . . . . . . . . . . . . Field reinforcement and cancellation with parallel conductors. . . Mutual coupling example between resistors. . . . . . . . . . . . . Equivalent circuit for mutual capacitive coupling example. . . . . Simulation plots for capacitor cross coupling. . . . . . . . . . . . Relevant capacitive coupling waveforms with resistors grounded. Example of mutual inductance in a digital system. . . . . . . . . Measurement setup for mutual inductance experiment. . . . . . . Physical configuration of resistors in inductive coupling experiment. Equivalent circuit for simulation of inductive mutual coupling. . Results of the inductive cross coupling simulation. . . . . . . . . Logic gate with a capacitive load. . . . . . . . . . . . . . . . . . . Inductive coupling waveforms with a 10pf load capacitance. . . . Schematic of an integrated circuit showing the lead inductance. . Example waveforms for an octal latch driving a capacitive load. . Logic package showing the capacitance between pins. . . . . . . . Composite rise time of an oscilloscope. . . . . . . . . . . . . . . . Equivalent circuit of CRO input probe. . . . . . . . . . . . . . . Bode plot of the transfer function of a CRO probe. . . . . . . . . Response of the CRO probe equivalent circuit with the input rise time of 1.8nsec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Response of the CRO probe equivalent circuit with the input rise time of 5.5nsec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . General configuration for probe lead pick up. . . . . . . . . . . . CRO probe equivalent circuit with no lead inductance. . . . . . . Source to probe input transfer function for a CRO probe. . . . .
2.25 2.26 2.27 2.28
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4 5 6 7 8 11 14 19 21 21 23 24 27 30 31 31 33 35 38 38 39 40 42 43 44 46 50 50 52 54 55 56 58 60 61
xvi
LIST OF FIGURES 2.29 2.30 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 3.1
CRO probe input impedance. . . . . . . . . . . . . . . . . . . . . A home brew 21:1 high speed probe. . . . . . . . . . . . . . . . . Equivalent circuit for the home brew probe. . . . . . . . . . . . . Speed-up circuit as applied to a CRO probe input. . . . . . . . . Ideal frequency response for a correctly compensate speed-up circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of wire connection to lower sense loop inductance. . . . . . . Low inductance probe connection. . . . . . . . . . . . . . . . . . Layout of a PCB embedded high frequency test point . . . . . . Noise pick-up due to shield currents. . . . . . . . . . . . . . . . . Differential probing to eliminate shield current effects. . . . . . .
61 63 63 67 67 68 68 69 70 72
3.21 3.22 3.23 3.24
Physical configuration of different types of common transmission lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Experimental set-up to measure transmission line distributed parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Voltage pulse in an ideal transmission line. . . . . . . . . . . . . . 80 Typical dimensions of PCB traces to produce 50Ω and 75Ω characteristic impedances. . . . . . . . . . . . . . . . . . . . . . . . . 81 Model of the transmission line using coupled LC sections. . . . . 83 Lenz’s Law explanation of the skin effect. . . . . . . . . . . . . . 84 Resistance of AWG 24 round wire (diameter = 0.02in) with frequency (reproduced from [1] page 158). . . . . . . . . . . . . . . 85 Example of the proximity effect in round conductors. . . . . . . . 86 Diagrammatic representation of the various reflected signals in a transmission line showing the acceptance, propagation and transmission transfer functions. . . . . . . . . . . . . . . . . . . . . . . 92 Load terminations: (a) Conventional termination, (b) Capacitive termination 1, (c) Capacitive termination 2. . . . . . . . . . . . . 94 Transmission line with a capacitive load in the middle. . . . . . . 96 Right angle track showing origin of additional capacitance. . . . 98 Chamfered track to match impedance around a right angle corner. 98 Transmission line with equally spaced capacitive loads. . . . . . . 99 Some possible multi-point configurations. . . . . . . . . . . . . . 100 Voltage just prior to line connection with mid line multi-point connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Termination voltage with a mid line multi-point connection. . . . 102 Waveform plots for a multi-point line with a single series termination and mid point line connection. . . . . . . . . . . . . . . . 102 Two multi-point lines branching from a Z0 /2 source terminator – the lines are of the same length. . . . . . . . . . . . . . . . . . 103 Two multi-point lines branching from a Z0 /2 source terminator – the lines are of different lengths. . . . . . . . . . . . . . . . . . 104 Multi-point splitter using resistive network. . . . . . . . . . . . . 105 Multi-point waveforms using the resistive “splitter” network. . . 105 Poorly designed gate daisy chain with end termination. . . . . . 106 Better design for a gate daisy chain. . . . . . . . . . . . . . . . . 107
4.1
Dimensions of two power planes. . . . . . . . . . . . . . . . . . . 109
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20
LIST OF FIGURES 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25
Approximate current flows with low and high frequency spectral content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Distribution of current in the ground plane when the currents have high frequency components. . . . . . . . . . . . . . . . . . . Two traces above a ground plane and the resultant current distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current paths with a slot cut in the ground plane of a PCB. . . . Current flow through connect hole grids. . . . . . . . . . . . . . . Layout of a two layer power plane. . . . . . . . . . . . . . . . . . Layout of a finger power and ground plane system. . . . . . . . . Guard trace configuration. . . . . . . . . . . . . . . . . . . . . . . Model for the coupling of a distributed transmission line. . . . . Mutual inductively coupled transmission lines with Tr = 210psec Waveforms for capacitively coupled transmission lines and Tr = 210psec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mutual coupling waveforms with both inductive and capacitive coupling and Tr = 210psec. . . . . . . . . . . . . . . . . . . . . .
xvii
112 113 114 115 115 117 118 120 120 122 123 124
Block diagram of the structure of a typical DC-DC converter. . . 127 A basic buck or step-down converter. . . . . . . . . . . . . . . . . 129 A basic boost or step-up converter. . . . . . . . . . . . . . . . . . 129 Two switch buck–boost converter. . . . . . . . . . . . . . . . . . 131 Single switch Buck–boost converter circuit. . . . . . . . . . . . . 132 The C´ uk converter. . . . . . . . . . . . . . . . . . . . . . . . . . . 133 C´ uk converter with the switch open. . . . . . . . . . . . . . . . . 133 C´ uk converter with the switch closed. . . . . . . . . . . . . . . . 134 Full bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . 135 Definition of the terms related to duty cycle. . . . . . . . . . . . 136 Waveforms in a sawtooth based PWM modulator. . . . . . . . . 138 Simple PWM generator circuit. . . . . . . . . . . . . . . . . . . . 138 Currents and circuit configurations for a buck converter. . . . . . 140 Current waveform at the point of discontinuous current in the inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Current waveform for a buck converter with discontinuous current.143 Voltage ratio of the buck converter for continuous and discontins Vd uous operation modes and constant Vd . NB. ILBmax = T8L . . . 144 Characteristics of the buck converter with constant Vo . NB. s Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 ILBmax = T2L Output voltage ripple for a buck converter. . . . . . . . . . . . . 148 Circuit used in simulation of the buck converter. . . . . . . . . . 150 Waveforms for a buck converter with D = 0.5, RL = 100, and continuous inductor current. . . . . . . . . . . . . . . . . . . . . . 150 Initial startup waveforms for a buck converter with D = 0.5, RL = 40kΩ, and discontinuous inductor current. . . . . . . . . . 151 Currents and circuit configurations for a boost converter. . . . . 152 Voltage ratio of a boost converter versus duty cycle. . . . . . . . 153 Current waveform on the edge of continuous current. . . . . . . . 154 Plot of the normalised continuous current boundary for the boost converter (Vo constant). . . . . . . . . . . . . . . . . . . . . . . . 155
xviii
LIST OF FIGURES 5.26 Current waveforms for the boost converter with discontinuous current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.27 Duty cycle versus normalised output current for the boost converter with constant Vo . . . . . . . . . . . . . . . . . . . . . . . . 5.28 Boost converter simulated using Saber . . . . . . . . . . . . . . . 5.29 Simulated waveforms for a boost converter with D = 0.5 and continuous current. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.30 Output of a boost converter in continuous current mode with several different duty cycles. . . . . . . . . . . . . . . . . . . . . . 5.31 Steady state currents and voltages in a C´ uk converter. . . . . . . 5.32 Waveforms for a full bridge converter with a bipolar switching strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.33 Waveforms for a full bridge converter with a unipolar switching strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.34 The input current into a buck-boost converter with a large input inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.35 Plot of switch utilisation for the common converter types. . . . . 5.36 (a) Conventional non-synchronous rectifier based boost converter. (b) Synchronous rectifier based boost converter. . . . . . . . . . . 5.37 A zero current switching (ZCS) resonant buck converter. . . . . . 5.38 A zero voltage switching (ZVS) resonant buck converter. . . . . . 5.39 A quasi-resonant forward converter. . . . . . . . . . . . . . . . . 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22
Basic circuit of the forward converter. . . . . . . . . . . . . . . . A practical forward converter. . . . . . . . . . . . . . . . . . . . . Equivalent circuit for a practical forward converter. . . . . . . . . Current waveforms for a practical forward converter. . . . . . . . Circuit diagram of a two switch forward converter. . . . . . . . . Push-pull forward converter. . . . . . . . . . . . . . . . . . . . . . Currents flowing in the push-pull forward converter with SW1 closed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents flowing in the push-pull forward converter with SW1 and SW2 open. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flux imbalance in the push-pull circuit. . . . . . . . . . . . . . . Connection between the Buck-Boost and Flyback converter. . . . Flyback converter with the switch closed. . . . . . . . . . . . . . Flyback converter with the switch open. . . . . . . . . . . . . . . The voltage, current and flux in the ideal Flyback Converter. . . Typical BH loop for a magnetic material. . . . . . . . . . . . . . Core excitation waveforms. (a) forward converter. (b) full bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of a typical switch mode power supply. . . . . . . Feedback circuit using a small forward converter. . . . . . . . . . Example of a simple bootstrap power circuit for a PWM generator chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap circuitry modified for increased hysteresis range. . . . Block diagram of the Unitrode high speed PWM generator. . . Operation of a constant current limit. . . . . . . . . . . . . . . . Operation of a foldback current limit. . . . . . . . . . . . . . . .
156 158 159 160 160 161 164 167 170 172 174 175 175 177 179 180 180 182 184 185 186 187 189 190 191 191 193 195 196 200 202 203 204 205 206 206
LIST OF FIGURES
xix
6.23 Conceptual diagram of a control system for a switch mode power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24 Linearised model of a switch mode power supply. . . . . . . . . . 6.25 Block diagram of a nested loop control system for a switch mode power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.26 Waveforms for tolerance band current control. . . . . . . . . . . . 6.27 Waveforms for constant “off” time control. . . . . . . . . . . . . 6.28 Waveforms for constant frequency with turn-on at clock time control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29 Open loop instability of current mode control. (a) stability with duty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stability with duty cycle > 0.5 and slope compensation. . . . . . . . . 6.30 Geometrical relationship of the current waveform slopes when there is a current perturbation. . . . . . . . . . . . . . . . . . . . 6.31 Inductor current response of current mode converter. . . . . . . . 6.32 Optimal slope compensation to eliminate RLC type oscillations. . 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16
207 208 209 211 212 213
214 216 216 217 222 227 227 228 232 234 235 236 238 239 241 243 245 247 253
7.23
Equivalent circuit model of a current shunt . . . . . . . . . . . . Method of voltage sharing for series capacitors. . . . . . . . . . . Reverse recovery in a converter secondary circuit. . . . . . . . . . Reverse recovery in a boost converter circuit. . . . . . . . . . . . Operational amplifier circuit for discussion of offsets. . . . . . . . Conventional inverting Op Amp circuit with a gain of 1000. . . . Inverting Op Amp circuit with alternative feedback network. . . Gain-bandwidth product of an Op Amp. . . . . . . . . . . . . . . Comparator with hysteresis. . . . . . . . . . . . . . . . . . . . . . Interfacing a comparator to an NPN transistor. . . . . . . . . . . A loop of wire enclosing an area of time varying flux density. . . A BH loop for a magnetic material. . . . . . . . . . . . . . . . . Circuit symbol for a transformer. . . . . . . . . . . . . . . . . . . Simplified model of a real transformer. . . . . . . . . . . . . . . . Ferrite choice (from [2]). . . . . . . . . . . . . . . . . . . . . . . . Initial permeability with respect to frequency for 2P iron powder Ferroxcube material (from [3]). . . . . . . . . . . . . . . . . . . . Incremental permeability as a function of magnetic field strength for 2P iron powder Ferroxcube material (from [3]). . . . . . . . . Core type selection table (from [3]). . . . . . . . . . . . . . . . . Core data for toroidal cores using powdered iron (from [3]). . . . Typical BH characeristic for 2P magnetic material (from [3]). . . Losses in 2P material with respect to flux density and frequency (from [3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Winding interleaving for high-dielectric isolation and good primary to secondary coupling. . . . . . . . . . . . . . . . . . . . . . A transformer design to satisfy safety requirements. . . . . . . .
8.1 8.2 8.3 8.4 8.5
The current-voltage characteristic of a diode. . . . Conceptual structure of a conventional diode. . . . Conceptual structure of a power diode. . . . . . . . Typical reverse recovery characteristic for a diode. Conceptual diagram of a thyristor. . . . . . . . . .
273 274 274 276 277
7.17 7.18 7.19 7.20 7.21 7.22
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253 254 257 259 260 261 267 268
xx
LIST OF FIGURES 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15
8.16 8.17
8.18 8.19 8.20 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18
Transistor model of the thyristor. . . . . . . . . . . . . . . . . . . Typical characteristic of a thyristor. . . . . . . . . . . . . . . . . Typical turn-on waveforms for a thyristor. . . . . . . . . . . . . . Typical thyristor turn-off waveforms. . . . . . . . . . . . . . . . . An example of a dc chopper circuit using a GTO thyristor . . . . Turn on waveforms for a GTO thyristor. . . . . . . . . . . . . . . Turn-off waveforms for a GTO thyristor. . . . . . . . . . . . . . . GTO thyristor circuit with additional “crowbar” SCR . . . . . . A schematic diagram of the basic structure of the IGBT. . . . . . The IGBT voltage and current transfer characteristics and circuit symbol: (a) output characteristic; (b) transfer characteristic; (c) and (d) n-channel IGBT circuit symbols. . . . . . . . . . . . . . . Current flows in the IGBT. . . . . . . . . . . . . . . . . . . . . . Equivalent circuits for the IGBT: (a) approximate equivalent circuit for normal operating conditions; (b) more complete equivalent circuit showing the parasitic thyristor. . . . . . . . . . . . . . Typical turn-on waveforms for an IGBT. . . . . . . . . . . . . . . Turn-off waveforms for an IGBT. . . . . . . . . . . . . . . . . . . Schematic and circuit symbol for the P-MCT. . . . . . . . . . . .
277 279 280 281 284 285 287 288 290
291 295
296 297 298 298
Line current waveform distortion. . . . . . . . . . . . . . . . . . . 301 Phasor relationship for complex power. . . . . . . . . . . . . . . . 304 Diagram of the normalised single phase power components with a 30◦ phase angle – the power is normalised by dividing by Vrms Irms .305 Half wave rectifier with a resistive load. . . . . . . . . . . . . . . 309 Half wave rectifier with an LR load. . . . . . . . . . . . . . . . . 309 Plots for a half wave rectifier with an LR load – L = 200mH and R = 50Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Half wave rectifier circuit with an inductor and back emf. . . . . 311 Plots for a half wave rectifier with an inductor and back emf as a load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Test circuit used for current commutation discussion. . . . . . . . 313 Circuit configurations during current commutation of the circuit in Figure 9.9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Plots of the currents in the test circuit of Figure 9.9 – vs = 50 sin ωt, Ls = 5mH, Id = 1 Amp. . . . . . . . . . . . . . . . . . . 316 A practical single phase rectifier. . . . . . . . . . . . . . . . . . . 317 Equivalent circuit of the single phase rectifier when the diodes are conducting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Waveforms for the practical single phase rectifier circuit of Figure 9.12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Input current and output voltage harmonics in a single phase rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Real and imaginary components of the harmonic phasors for the harmonics single phase rectifier harmonics plotted in Figure 9.14. 321 Single phase rectifier with input and dc link filters. . . . . . . . . 324 Circuit for the a single phase rectifier with current wave shaping boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
LIST OF FIGURES
xxi
9.19 Waveforms for a single phase rectifier with active current waveshaping – (a) the input current and voltage; (b) the boost converter input voltage and inductor current. . . . . . . . . . . . . . 9.20 Block diagram of the control system for a single phase rectifier with active current waveshaping. . . . . . . . . . . . . . . . . . . 9.21 Single phase rectifier showing the point of common coupling. . . 9.22 Single phase rectifier voltage doubler. . . . . . . . . . . . . . . . . 9.23 Single phase rectifiers loads in a three phase, four wire distribution system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.24 Basic three phase, six pulse, full wave rectifier circuit. . . . . . . 9.25 Waveforms of a three phase rectifier with a constant current source load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Definition of rectifier and inverter modes of operation [4]. . . 10.2 Generic power processing block [4]. . . . . . . . . . . . . . . . 10.3 Block diagram of a generic AC drive system. . . . . . . . . . 10.4 Specific implementation of an inverter. . . . . . . . . . . . . . 10.5 Single leg of inverter and the PWM waveforms. . . . . . . . . 10.6 Switch positions and the resultant voltage space vectors. . . . 10.7 Switching waveforms for double edge pulse width modulation. 10.8 Switching time determination. . . . . . . . . . . . . . . . . . . 10.9 Voltage limit hexagon. . . . . . . . . . . . . . . . . . . . . . . 10.10Inverter showing the initial and final current flow after a leg fired. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.11Example of dead-time induced switching error in an inverter. 10.12Generic non-battery based photo-voltaic supply system. . . . 10.13Some grid connected FACTS units offered by Siemens. . . . .
. . . . . . . . . . . . . . . . . . is . . . . . . . .
326 328 329 330 331 333 333 336 336 337 338 339 342 343 344 346 347 348 351 351
D.1 Simple single phase, half wave rectifier, with an LR load. . . . . . 362 D.2 Initial screen upon invoking SaberSketch. . . . . . . . . . . . . . 363 D.3 An example of a parts gallery screen. . . . . . . . . . . . . . . . . 364 D.4 The wire attributes window. . . . . . . . . . . . . . . . . . . . . . 367 D.5 An example of SaberSketch with the Saber guide toolbar activated.368 D.6 An example dc/transient simulation set-up window. . . . . . . . 369 D.7 The input-output table of the dc/transient analysis window. . . . 370 D.8 The initial SaberScope window. . . . . . . . . . . . . . . . . . . . 371 D.9 A signal plotted in SaberScope. . . . . . . . . . . . . . . . . . . . 372 D.10 An example of a waveform calculation in SaberScope. . . . . . . 373 D.11 Fourier analysis dialogues in Saber. . . . . . . . . . . . . . . . . . 373 E.1 Test Printed Circuit Board. . . . . . . . . . . . . . . . . . . . . . 380 F.1 F.2 F.3 F.4 F.5 F.6
Power circuit of switch experimental box. . . . . . . . . PWM control circuit for laboratory module. . . . . . . . Buck converter – Saber circuit. . . . . . . . . . . . . . . Conceptual PWM control circuit for the buck converter. Saber model of the boost converter. . . . . . . . . . . . Practical isolated forward converter circuit. . . . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
384 384 386 387 387 389
G.1 Series RLC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 391
xxii
LIST OF FIGURES G.2 Series RLC circuit pole positions. . . . . . . . . . . . . . . . . . . 392 G.3 Time response of a series RLC circuit with Q = 6.3. . . . . . . . 396 G.4 Parallel RLC circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 396 H.1 H.2 H.3 H.4 H.5 H.6 H.7
Two wire transmission line and a single element model. Semi-infinite transmission line with source . . . . . . . . Plot of pulse in the time and distance domains . . . . . DC voltage transient on a transmission line . . . . . . . Voltage reflection diagram . . . . . . . . . . . . . . . . . Terminated transmission line and the equivalent circuit Thevenin equivalent circuit of a transmission line . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
401 410 410 412 414 423 425
I.1 I.2 I.3 I.4 I.5 I.6 I.7
Parallel plate capacitor. . . . . . . . . . . . . . Coaxial cable cross-section. . . . . . . . . . . . Round wire suspended above a ground plane. . Configuration of twisted pair transmission line. Dimensions of a microstrip transmission line. . Dimensions of a symmetric stripline. . . . . . . Dimensions of the offset transmission line. . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
429 431 432 433 434 435 436
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
List of Tables 2.1 2.2 2.3 2.4 2.5
18 47 49 49
2.6 2.7 2.8
Propagation delays for electromagnetic fields in various media. . Typical switching characteristics of common logic families. . . . . Lead inductances of various logic packages. . . . . . . . . . . . . Inter-pin capacitance of common logic packages. . . . . . . . . . Rise time and Q for 10pF and 2pF capacitance probes for various inductances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductance and rise time of male coax connectors. . . . . . . . . Rise time of some coaxial cables. . . . . . . . . . . . . . . . . . . Rise time of home brew probe sense loop. . . . . . . . . . . . . .
3.1
Statistics for point-to-point wire wrap board . . . . . . . . . . . .
73
7.1 7.2 7.3 7.4
Resistor application selection guide Capacitor application guide . . . . Core materials and their uses. . . . Inductor specifications. . . . . . . .
9.1 9.2
Fourier coefficient formulae with symmetry. . . . . . . . . . . . . 301 Current harmonic amplitudes. . . . . . . . . . . . . . . . . . . . . 323
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. . . .
10.1 Switching combinations and associated phase and line-to-line voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Switching combinations and associated phase and phase-to-neutral voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 PWM firing times for various sectors . . . . . . . . . . . . . . . . 10.4 Voltage limit γ’s . . . . . . . . . . . . . . . . . . . . . . . . . . .
57 64 65 65
220 224 248 252
340 341 345 346
D.1 Number magnitude specifiers in Saber . . . . . . . . . . . . . . . 366 I.1
Useful constants . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
xxiv
LIST OF TABLES
Part I
Digital Systems
Chapter 1
Logic Families 1.1
Introduction
This chapter will consider various issues related to the switching aspects of the main digital logic families. Some consideration will be given to the internal operation of the main logic families, with particular emphasis on how the internal operation manifests itself in the terminal characteristics of logic devices. An understanding of logic families is important in order to reliably interface components coming from different types. In addition the switching characteristics of the different families have implications on the design of printed circuit boards and the noise induced on them.
1.2 1.2.1
Review of Logic Family Properties A Brief History
Much of the material presented in this section is based on the presentation in [5]. Electrically controlled digital logic circuits were first developed at Bell Laboratories in the 1930s, and were based on using relays. The relays were replaced in the 1940s with vacuum tubes, resulting in the worlds first electronic digital computer (known as Eniac). This machine had 18,000 vacuum tubes (and a similar number of logic gates) and consumed 140,000 Watts of power. The invention of the semiconductor diode and bipolar junction transistor allowed the development of smaller, faster, and more capable computers in the late 1950s. The basic concepts used in these machines were further refined and integrated into a more compact form in the 1960s with the invention of the integrated circuit. The development of the integrated circuit was very important in lowering the cost of computers, and at the same time increasing their capabilities. The 1960s saw the introduction of the first integrated-circuit logic families. A logic family is a collection of different integrated circuit chips that have similar input, output and internal circuit characteristics. This allows all the chips in the family to be easily interfaced with each other. The converse of this is that there may be incompatibility with integrated circuits from other families. The most successful bipolar logic family (i.e. based on the use of bipolar junction transistors(BJTs)) is transistor-transistor logic (TTL). This was first
logic families
TTL
4
MOSFETs
Logic Families introduced in the 1960s, and has now developed into several related logic families that are compatible with each other but differ in speed, power consumption and cost. The other major logic family is based on metal-oxide semiconductor field effect transistors (MOSFETs), more commonly known as the MOS transistor. These devices were actually invented 10 years prior to BJTs, but did not initially become popular due to fabrication difficulties. Many of these initial problems were solved by the 1960s and number of products become available based on this technology, although the performance lagged behind BJT based devices at this time. MOS transistor development continued through the early 1970s, and accelerated at the end of the 1970s and early 1980s with the development of large scale integrated (LSI) circuits, and particularly the microprocessor. The MOS transistor is also used in a closely associated technology known as CMOS (complementary MOS). The advantage of this configuration of MOS transistors is the low power dissipation that can be achieved. This is becoming increasingly important as integration densities escalate, since removing the internally generated heat from ICs is a problem when there are millions of transistors on a chip. By far the majority of electronic devices now produced use MOS transistors in a CMOS configuration. There is an equivalent set of SSI (small scale integrated) circuit devices using CMOS technology. These devices have similar capabilities to their TTL counterparts, and in many cases are designed to be input and output compatible with TTL. In fact most VLSI (Very Large Scale Integrated Circuits) are also designed to have TTL compatible inputs and outputs.
1.2.2
enhancement mode
source and drain
The CMOS Logic Family
Before considering CMOS itself, let us firstly briefly review the operation of the basic switching element in CMOS, NMOS and PMOS logic (the latter two of these will become obvious in the following discussion). Consider Figure 1.1, which shows a cross section of a MOS transistor. This diagram shows the basic structure of a n-channel enhancement mode MOSFET (known as an NMOS transistor). This is called an enhancement mode device because the application of the gate voltage enhances (or creates) a channel for the current to flow from the drain to the source. Unlike BJTs the current carriers in a MOSFET are the majority carriers (compared to minority carriers being the dominant current carrier in the BJT). This is achieved in the enhancement mode MOSFET by the gate voltage causing an “inversion” of the material under the gate so that a channel is formed which allows the majority carriers in the source well to flow to the drain well. This channel is shown schematically in Figure 1.1. Notice that the channel becomes wider towards the source where the effect of the voltage appearing across the gate insulation is larger and therefore is able to attract more carriers. The terms “source” and “drain” refer to the movement of the majority carriers in the device. In the case of the n-channel MOSFET shown in Figure 1.1 the source connection is where the electrons are generated in the device, and the drain is where they leave the device. In this particular device, if the voltage between the gate and source terminals (VGS ) is zero then the device will not conduct current. Under this condition there is a reverse bias diode between the
1.2 Review of Logic Family Properties
Induced n Channel
Drain VDD +
5
Gate +
Source VSS VGS
Depletion Region
Silicon Dioxide Insulation
n+
n+
p
Substrate
Figure 1.1: Block diagram of an enhancement mode n-channel MOSFET. drain and the substrate. If sufficient positive voltage is applied between these terminals then electrons are attracted under the gate area, and conversely holes are repelled. If a large enough voltage is applied then the material under the gate will change from p material to n material. Therefore there is an n-channel from the two n+ wells and electrons can then flow between the two. The MOSFET of Figure 1.1 has a p substrate. An alternative is to have a n substrate and p+ wells. These are known as PMOS transistors . In this case a p channel has to be enhanced with the application of the gate voltage, which implies that the gate voltage has to be negative compared to the substrate. If the substrate is connected to the source then if VGS is zero then no current can flow (due to a reverse biased diode being formed as in the case of the nchannel device), and if VGS < Vt , where Vt is a threshold voltage then current will flow. The circuit symbols commonly used for the n-channel and p-channel MOSFETs are shown in Figure 1.2. Notice that the inverted input to the pchannel MOSFET is signified in one of the symbols by an inversion circle. The MOSFETs discussed thus far are enhancement mode devices, and they require a voltage to be applied in order to turn the devices on. There are MOSFET devices that are “normally-on” devices – that is they conduct current without any applied voltage, and a voltage has to be applied to turn the device off. These are known as depletion mode MOSFETs as the applied voltage depletes an existing channel. Depletion mode devices found widespread use in early LSI technologies where they were used for providing pull-up resistors. However, all VLSI chip technology today is based on the CMOS circuit topology, which does not involve the use of depletion mode devices. Therefore the devices will not be considered any further. The main problem with the NMOS based technology was the power dissipation due to the voltage drop across the depletion mode MOS transistor based resistors in these designs.
PMOS transistor
threshold voltage
depletion mode
6
Logic Families
Drain Gate
Source Gate
Gate
Drain
Drain
{
Source
Source
n-channel
p-channel
Figure 1.2: Common circuit symbols for enhancement mode MOSFETs. The concept of the threshold voltage (Vt ) was mentioned above. This is the voltage which causes the MOSFET to conduct a significant current. From a digital logic viewpoint the voltage which “turns on” the device is very important. Fortunately the MOSFET designer has a number of techniques of controlling Vt [6]. In general the threshold voltage is a function of a number of parameters including the following: • gate material • gate insulation material • channel doping • impurities at the silicon-insulator interface • voltage between the source and substrate
Complementary Metal Oxide Semiconductor Transistor
Two common techniques used for adjusting the threshold voltage entail varying the doping concentration at the silicon-insulator interface through ion implantation, or using different insulator material for the gate. An example of the last approach is to use a layer of silicon nitride (Si3 N4 ), which has a relative permittivity of 7.5 compared to that of silicon dioxide (SiO2 ) which is 3.9. Use of this is equivalent to using a much thinner gate insulator, and hence the gate capacitance is increased meaning that for the same applied voltage more charge is accumulated under the gate. After our brief review of MOSFETs we will now return to the CMOS implementation of MOSFETs. The abbreviation CMOS stands for Complementary Metal Oxide Semiconductor transistor . It refers to a configuration of MOSFET transistors as shown in Figure 1.3. It is a totem pole structure in which the top transistor is a p-channel enhancement mode device, and the bottom device is a n-channel enhancement mode device.1 This structure is a basic inverter implemented in MOSFET technology. 1 The supply voltage is denoted as V DD for historical reasons. The first MOS circuits were based on NMOS devices where the drain was connected via a resistor to the positive supply. The VDD voltage is often called VCC .
1.2 Review of Logic Family Properties
7
VDD
p-channel Vout Vin
n-channel
Figure 1.3: CMOS inverter.
1.2.2.1
Logic Levels and Noise Margins
Logic levels and noise margins are one of the most important aspects of any logic family in relation to interfacing members of the family together, and the reliability of operation in the presence of noise. One of the most important characteristics of a CMOS inverter is the transfer characteristic . A typical characteristic is shown in Figure 1.4. Emphasis should be placed on the word typical, since the exact positioning and shape of this characteristic varies depending on the IC fabrication line, width to length ratios of the p and n transistors, doping levels, and random variations in the manufacturing process. However a manufacturer will guarantee certain characteristics of the circuits they manufacture.
noise margins
transfer characteristic
Figure 1.4 illustrates an aspect of digital systems that is not always appreciated – a digital inverter is essentially an analogue inverting amplifier, albeit a very high gain amplifier.2 Ideally the transition from the high to the low level would be vertical (i.e. infinite amplifier gain) and ViL and ViH would be equal. The noise margins of a digital device refer to the amount of electrical noise that can be tolerated on the output of a device before the input of a following device will see a high level as a low level, or vice-versa. The noise margins are closely related to the transfer characteristic in Figure 1.4. Noise margins are usually specified by two values – the low noise margin, N ML and the high noise margin, N MH . The following discussion is with reference to Figure 1.5, which shows the generic definitions of logic levels. We need to define a few of the variables in this figure:
2 The analogue amplifier properties of inverters are used when one constructs a crystal oscillator using a string of inverters
low noise margin, high noise margin
8
Logic Families Slope=-1 Vout
Supply current VDD
0.5VDD
VDD -Vtp VDD
Vtn ViL
Vin
ViH
Figure 1.4: Typical transfer characteristic for a CMOS inverter.
VIHmin = minimum HIGH input voltage VILmax = maximum LOW input voltage VOHmin = minimum HIGH output voltage VOLmax = maximum LOW output voltage Given these definitions we can now formally define the noise margins: N ML = |VILmax − VOLmax |
(1.1)
N MH = |VOHmin − VIHmin |
(1.2)
Therefore N ML is the difference between the highest low level voltage that the CMOS output produces and the highest input voltage that the CMOS input will still recognise as a low (i.e, any higher voltage cannot guaranteed to be seen as a low). Similarly N MH is the difference between the lowest output voltage that can be produced, and the smallest input voltage that is still recognised as a high input. As an example of typical values let us consider the HC-series CMOS family operating with a 5V supply voltage. VOHmin The minimum output voltage in the HIGH state is 4.9V. VIHmin The minimum input voltage recognised as a HIGH is 3.5V. VILmax The maximum input voltage recognised as a low is 1.5V. VOLmax The maximum output voltage in the LOW state is 0.1V. Using these values for the various voltage levels together with 1.1 and 1.2 one can see that N ML = 1.4V and N MH = 1.4V , which is not only symmetric
1.2 Review of Logic Family Properties
9
Output characteristics
Input characteristics
VDD Logical high output range
VOH
min
Logical high input range
NM H
VIH
min
Indeterminate region
VIL
max
VOL
max
NM L
Logical low output range
Logical low input range
VSS or GND
Figure 1.5: Noise margin and generic logic level definitions. but is also an excellent level of noise margin for a component working on a 5V supply voltage. An important point not mentioned in the above paragraph is that the output voltages (either min or max values) are specified under certain loading conditions, which are specified in the manufacturers data sheet. The load is specified in terms of currents:
loading conditions
IOLmax The maximum current that the output can sink in the the LOW state while still maintaining an output voltage no greater than VOLmax . IOHmax The maximum current that the output can source in the HIGH state while still maintaining an output voltage less than VOHmin . The inputs in CMOS circuits have a very low DC current loading, although the capacitive loading can be very important under transient conditions. A typical input current value for a HC-series CMOS gate is ±1µA. Many CMOS data sheets will contain values of IOLmax and IOHmax for both CMOS loads as well as TTL loads. In the case of TTL loads the noise margins are significantly degraded relative to CMOS loads. For example, if a TTL load is connected to HC-series CMOS devices output voltage limits are: VOLmax = 0.33V (compared to 0.1V with CMOS load), and VOHmin = 4.3V (compared to 4.9V with a CMOS load). The effect of these changes in output voltage levels is not obvious in quantitative terms until we consider the input performance of TTL logic. One can also consider the behaviour of the circuits with non-ideal inputs. This refers to a situation where the inputs are not clamped hard to the VSS or VDD supply rails. Therefore we can have a situation where both the transistors are both at least partially on, and therefore the outputs are created by a resistive dividing action. If there is a current sink or source load (such as a resistive load or a TTL input) then the situation is even more complicated in terms of calculating the output voltage level. In addition the output transistors of
non-ideal inputs
10
Logic Families the CMOS devices will also be consuming power under these conditions. If connected to a CMOS load there is virtually no current flowing when the logic levels are constant, and therefore there is little power dissipation. 1.2.2.2
fanout
low state fanout high state fanout overall fanout DC fanout AC fanout
The term fanout refers to the ability of a logic gate to drive a number of inputs without exceeding its worst case loading specifications. The fanout is clearly dependent on two things – the output drive capability and the loading of the inputs connected to the output. As an example consider fanout of HC-series CMOS. When driving CMOS inputs the IOLmax value is 20µA giving a VOLmax of 0.1V. The inputs for these CMOS components have a loading of ±1µA, which implies that 20 inputs can be connected to a low output without exceeding the maximum output voltage specification. This is called the low state fanout . Similarly the maximum high state output current is −20µA. 3 Therefore the maximum high state fanout is also 20. This symmetry between low state and high state fanout is not usual, and therefore the overall fanout is the minimum of the two fanout numbers.4 The fanout properties that we have just discussed is the DC fanout, since we are considering constant output values. However, in some cases the so-called AC fanout , which is largely determined by the capacitance of the inputs and the propagation that can be tolerated. This fanout restriction occurs due to the RC time constant issues associated with the resistance of the output stages of the CMOS devices and the input capacitance associated with the gate of the inputs. Clearly as the capacitance increases then the switching edges slow down. Therefore skew is introduced into the edges, and hence the propagation delay of signals is increased. In addition slow edges can cause problems in noisy environments.fine 1.2.2.3
4000-series
HC-series (high speed CMOS)
Fanout
Specific CMOS Logic Families
Let us now briefly look at some specific CMOS logic families. We have already briefly looked at the HC-series of components in the previous sections. However the first successful commercial CMOS family was the 4000-series . This family offered very low power dissipation compared to the TTL family, but on the downside it was very slow and was difficult to interface to TTL which was the most popular logic family at the time of its introduction. Consequently the 4000-series was supplanted by more advanced CMOS families which will be discussed in the remainder of this section. A brief note on the numbering of these components. A generic number for a CMOS IC takes the form “74FAMnn”, where the ‘74’ denotes a commercial component5 and the ‘FAM’ denotes the family of the component, and finally the nn denotes the particular part number. For example, we can have the following part numbers for CMOS 8 input NAND gates; 74HC30, 74HCT30, 74AC30, 74ACT30. The HC-series (high speed CMOS) of components were designed to work in a 3 The sign convention for currents in digital circuits is that current flowing into the device is positive 4 The fanout can be increased if one is willing to sacrifice noise margin. 5 ‘54’ denotes a military specification component
1.2 Review of Logic Family Properties CMOS only logic system. They offered higher speed and better drive capabilities compared to the 4000-series. The input logic levels were different than those for TTL, therefore interfacing this logic with TTL was problematic. The HCTseries on the other hand were designed to be compatible with TTL logic levels. Therefore the inputs would work at the same voltage levels as those for TTL gates. Introduced in the mid-1980s the AC-series (advanced CMOS) and the ACTseries (advanced CMOS TTL compatible) were very fast logic families that could source and sink even larger currents than TTL. As with the HC-series the difference between the two was that the ACT components were TTL input compatible. The typical AC-series components have a propagation time of 5nsec for a NAND gate, as compared to 18nsec for the HC-series components. The price paid for this extra performance is higher power dissipation per logic cell. In the 1990s another even faster CMOS logic family was introduced – the FCT-series (Fast CMOS, TTL compatible) . There are several different speed grades available. Compared to the AC-series this family had a significantly better speed-power product. The other point to note was that there are not individual gates in this family, but it tends to concentrate on chips with a complexity equal to a 74x138 decoder or larger.
1.2.3
TTL inverter is formed by simply eliminating one of the inputs in the NAND gate. can have more inputs by simply including more diodes
7 One
HCT-series
AC-series (advanced CMOS) ACT-series (advanced CMOS TTL compatible)
FCT-series CMOS, compatible)
(Fast TTL
Bipolar Logic Families
The bipolar logic families have a basic active unit consisting of a bipolar junction transistor. There are two broad groups within this family – the TTL group and the ECL group. We shall concentrate mainly on the former, since ECL (emitter coupled logic) tends to be esoteric and is only used in very high performance applications. Figure 1.6 shows the diagram of a two input low power Schottky (LS) NAND gate.6 Let us briefly discuss its major internal components. The input stage consists of four Schottky diodes and a resistor. Two of the diodes (D1X, D1Y ) together with the resistor R1 form an AND gate (note that in some implementations these are replaced by a multi-emitter Schottky transistor).7 The other two diodes (D2X, D2Y ) are there for protection from negative excursions of the inputs under transient conditions. The output of the input stage then feeds to the phase splitter stage. The purpose of this stage is to convert the single signal from the input stage into the two levels to successfully control the output stage. If any of the inputs are low (0V ) then the base voltage of Q2 is approximately 0.25V (the voltage drop across the input Schottky diode). Therefore the Q2 transistor is cutoff. Consequently the base of Q3 is connected to VCC via resistor R2 and will be turned on. This is turn will turn on Q4 which makes the output go high. Let us consider the situation where one of the inputs is 0.8V and the other is higher than this. Under this condition the voltage on the base of Q2 will be 0.8V + 0.25V = 1.05V . Due to the presence of Q6 it takes at least 1.2V to enable Q2 to turn on, therefore this will still be seen as a “low” input situation. If both input voltages are 2V then the input diodes are effectively cutoff, since the diode drops across the base-emitter junctions of Q2 and Q6 mean 6A
11
bipolar logic families
low power Schottky
12
Logic Families VCC = +5V R1 = 20kW
R2 = 8kW
R5 = 120W
D1X
Q3
X
Q4
D1Y Y
D3 Q2
R6 = 4kW
D4
Z
R3 = 12kW
D2X
D2Y
Q5 . kW R4 = 15
R7 = 3kW
[ [ [
Q6
Diode AND gate and input protection
Phase splitter
Output stage
Figure 1.6: Typical circuit for a TTL NAND gate.
push-pull totem-pole
that the voltage at the base of Q2 cannot rise much above 1.2V . Under this condition Q2 turns on. Depending on how hard it is on, the voltage on the base of Q3 will drop and that on Q5 will rise. Therefore Q3 will tend to turn off (and consequently so will Q4 ), and Q5 will be tending to turn on. The Q6 transistor is diverting current away from the base of Q5. This ensures that Q2 is turned on “hard” before there is enough current to turn Q5. This in turn ensures that the inputs really have to be at about 2V before this will happen. Clearly with inputs below 2V and above 0.8V it is difficult to say exactly what will happen. This is a grey area in the operation of TTL, and the specifications will not say what the output will be under these conditions. The output stage of TTL is a push-pull or totem-pole output. The top two transistors are configured as a Darlington Pair to provide sufficient current output and the dual diode drops across the base emitter junctions help prevent simultaneous turn on of Q4 and Q5. The diodes D3 and D4 are provided to discharge the stored charge in the Q4 transistor and a capacitive load, thereby improving speed.8 Remark 1.1 A totem-pole output stage is virtually the same as the output stage on the CMOS components. Consequently it also suffers from the problem that there is a time during switching transients that both the top and bottom transistors are on at the same time. Hence there is a spike of current that flows during this period, which results in extra noise in the digital system. The resistor R5 8 The Q4 transistor is an ordinary transistor since it cannot go into deep saturation when configured in the Darlington Pair.
1.2 Review of Logic Family Properties
13
helps to control the magnitude of this current. 1.2.3.1
Bipolar Logic Noise Margins
Using the same broad definitions as in Figure 1.5 we can define the TTL logic levels and noise margins as follows: VOHmin The minimum output voltage in the HIGH state, 2.7V for most TTL families.
TTL logic level and noise margins
VIHmin The minimum input voltage guaranteed to be recognised as a HIGH, 2.0V for all TTL families. VILmax The maximum input voltage guaranteed to be recognised as a LOW, 0.8V for most TTL families. VOLmax The maximum output voltage in the LOW state, 0.5V for most TTL families. Using (1.1) and (1.2) we can define the noise margin for TTL components as N MH = 0.7V and N ML = 0.3V . Therefore we have non-symmetric noise margins with this technology, resulting in the logic being more susceptible to noise in the low state than the high state. 1.2.3.2
Fanout
The fanout restrictions for TTL are more restrictive than those for CMOS due to the fact that substantial currents flow out of the inputs for TTL. The amount of current flow for a TTL component is different depending on whether the input is a high or low value: IILmax This is the maximum current that an input requires to pull it LOW. For a LS-TLL component a typical value is −0.4mA. 9 IIHmax This is the maximum input current required in a HIGH state. This is essentially the current that leaks through the reverse biased input diodes. Typical values for LS-TTL is +20µA. The other aspect to the determination of fanout is the output drive capabilities of the circuits. As with the inputs there is an asymmetry in the output drive of TTL: IOLmax The maximum output current that one can sink in the LOW state whilst still maintaining the VOLmax output voltage. Typical value is 8mA for LSTTL.10 IOHmax The maximum current that can be sourced in the HIGH state whilst maintaining a minimum output voltage of VOHmin . A typical value is −400µA for LS-TTL. If one examines the asymmetric input and output behaviour of TTL then it can be seen that the LOW and HIGH fanout are the same at 20.11 9 The
current convention is that current flowing into a TTL IC is positive. TTL can sink large amounts of current (as compared to sourcing current) it is known as current sinking logic. 10 Because
LOW and HIGH fanout
14
Logic Families Note 1.1 The asymmetric output of TTL can cause problems in some applications. For example if one wishes to drive a LED or relay then one cannot use current sourced from a TTL component to do this. One would have to arrange the circuit so that the current sinking capability can be utilised. Clearly there would be a problem driving high capacitance loads as well, since the switching edge would be rather slow under these circumstances.
pull-up resistor
Practical Issue 1.1 Unused inputs in TTL circuits should be tied to an appropriate logic level (as was the case with CMOS circuits). However, if an input should be tied HIGH it is better to tie it via a pull-up resistor . In theory this is not required, and we could tie the input directly to the VCC supply rail. However, if the input transiently goes above 5.5V then damage to the input may result. A pull-up resistor limits the current that can flow in this situation and prevents damage. The value of the resistor is also important as well since the inputs take a significant amount of current in the HIGH state. Therefore the resistor must be chosen so that the input is well within the range of the logic value required. One can also have a pull-down resistor. However the same overvoltage issue does not apply so a LOW input is often tied to the GND supply. A pull-down can be used if one wishes to drive the tied input in a testing situation, although one is sacrificing some noise margin in order to achieve this. For example a 1kΩ pull-down resistor would give a low voltage of approximately 0.4V. 1.2.3.3
propagation delays
As was the case with CMOS there are a number of families or groups of compatible components within the general TTL family. We shall not go through the original TTL family as it is no longer used, but instead briefly mention the contemporary families, which all use Schottky transistors, and vary in the internal resistor values and transistor feature sizes. This results in different speeds and speed-power products for the different families. Similarly to the CMOS logic numbering system those for TTL components have the generic form “74FAMnn”, where the “FAM” is one of “AS” – advanced Schottky, “ALS” – advanced low power Schottky, and “F” – fast TTL.12 The “F” components are positioned in terms of speed-power product between “ALS” and “AS”. Typical propagation delays for a NAND gate are: AS: 1.7nsec; ALS: 4nsec; F: 3nsec.
1.3
TTL loading
Specific TTL Logic Families
Issues in TTL–CMOS Interfacing
Although most designers attempt to design a circuit using one logic family, there are occasions when components from other logic families may be used. Under these circumstances it is important to understand the implications of connecting different logic families. The logic level specifications for each of the logic families are summarised in Figure 1.7. Note that these values are worst case values for TTL loading. In the case of the HC-series CMOS components we are assuming that the supply 11 Note that in mixed TTL circuits (i.e. LS, S, AS etc components), one must add up the individual input loadings to determine the fanout that can be achieved. 12 Low power Schottky (LS) components were for many years the technology of choice for TTL designs. However, both in speed and power performance ALS has largely replaced LS.
1.3 Issues in TTL–CMOS Interfacing
15
OUTPUTS
INPUTS 5.0
VOH
min
{
HC, HCT AC, ACT
LS, S, ALS, 2.7 AS
High Levels Low Levels
VOL
max
{
3.85
3.84 3.76
LS, S, ALS, 0.5 AS AC, ACT 0.37 HC, HCT 0.33
INDETERMINATE TTL LEVEL
HC, AC
LS, S, ALS, 2.0 AS, HCT, ACT HC, AC 1.35 0.8 LS, S, ALS, AS, HCT, ACT
{
VIH
{
VIL
min
max
0
Figure 1.7: Worst case logic levels with TTL loadings. is between 4.5V and 5.5V . By comparing the output max or min logic levels on the left side of this figure with the appropriate max or min value on the right side one can calculate the worst case DC noise margins for the various logic families. Furthermore, one can also calculate the noise margins when logic families are mixed. One interesting case of mixing logic families is TTL and HC-series CMOS. Recall that HC-series CMOS was not designed to be TTL compatible. The problems can be seen by looking at the HIGH level performance. HC-series CMOS is not guaranteed to see a HIGH until 3.85V is on the input, but TTL outputs are guaranteed to only produce 2.7V . Even the CMOS TTL compatible families will not produce enough voltage to trigger the HC-series CMOS input under TTL loading conditions. Even if they did there would be virtually no DC noise margin.
worst case noise margins
Practical Issue 1.2 If one had to interface a TTL output to a HC-series CMOS input then one way of achieving reliable operation would be to use a pull-up resistor. The value could be chosen so that the sink current specifications for the TTL would not be exceeded, and at the same time the fastest rise time would be achieved. The Low to HIGH switching edge would have two sections – a fast section when the output is driving it, and a slower stage as the pull-up resistor charges up the output. The success of this would depend on the load capacitance, since a larger capacitance may slow down the second section of the edge unacceptably. Another factor to consider is the fanout . This is especially true in the case of interfacing CMOS outputs with TTL inputs, since the latter source much more current than CMOS inputs when held in the LOW state. Each loading situation must be considered individually, and is dependent on the mix of logic types. For example, the 74HC or HCT output can drive 10 74LS but only two 74S loads. Note that we are assuming the VOLmax = 0.5V for this condition, and IOLmax = 0.8mA.
fanout
DC
16
Logic Families The last factor to consider is the capacitive loading of the inputs. This is especially important when using the HC-series of components, since there is about a 1nsec increase in rise times for every 5pF of load capacitance. Note 1.2 With CMOS logic it is possible that poor quality inputs (e.g. a HIGH input near 2V ) can result in both the top and bottom transistors being on to some extent. This results in a larger than usual current flowing through the output in steady state and therefore the IC may heat up considerably. Practical Issue 1.3 A price that one pays when mixing TTL with a CMOS design is the loss of noise margins. Therefore, if noise immunity is a major issue in a design then it is better to use a CMOS logic only design, and use the CMOS family that is designed to only work with other CMOS components (HC or AC-series), since these have the highest noise margins. Of course if one resorts to the HCT, ACT etc. families of CMOS then one immediately has the noise margins of TTL. The only benefits gained are in the power consumption area.
Chapter 2
Introduction to Digital Switching 2.1
Introduction
This chapter introduces some of the concepts and background material required to understand future chapters. In addition some rules of thumb will be introduced, and backed up where appropriate by simulations to demonstrate the particular effect that the rule relates to. This chapter essentially covers a variety of issues that tend to be left out of most digital systems courses. The chapter considers the effects that the rapid rise times of digital signals have on the operation of digital systems. Therefore the emphasis is on self induced “noise”, rather than externally induced noise. This noise takes to various forms from transmission line effects through to ground bounce and crosstalk. The approach when considering these issues is very practical, and where appropriate suggestions are made as to how a design can be altered to minimise problems related to high speed switching. Much of this chapter is based on [1] which is an excellent reference on high speed digital design.
2.2
Relevant Frequencies
One of the key issues in digital systems design is the relationship between the frequency content of digital signals and the properties of the lines that they have to propagate down. We shall look at the first of these issues in this section. To some people it seems strange that the frequency content of a digital signal is not related to the frequency of the digital signal. The frequency content we are interested in is related to the switching edge rate of rise . It can be shown that the power spectral content of a random digital waveform being clocked at some rate Fclock has a knee point at some frequency. If the frequencies above this knee point are ignored then this has very little effect on the time domain representation of the digital signal. There is a very simple formula to find out what the knee frequency is given the rise time of a digital signal [1]:
switching edge rate of rise
18
Introduction to Digital Switching
Fknee =
0.5 Tr
(2.1)
where: Fknee frequency below which most of the energy in digital pulses is concentrated Tr pulse rise time The ramifications of equation (2.1) are:1 1. If a circuit has a flat frequency response up to the Fknee then it will pass a digital signal practically undistorted. 2. The behaviour above Fknee of a digital circuit will have little effect on how it processes digital signals. Equation (2.1) can be used as a rule-of-thumb for determining whether one has to worry about high frequency effects in a digital system. Another interesting figure of merit that comes from the analogue electronics world is the relationship between the -3dB bandwidth and the rise time of a signal: F3dB ≈
K Tr
(2.2)
where: F3dB frequency at which the impulse response (i.e. the frequency response) rolls off by 3dB K depends on the type of pulse shape – 0.338 for gaussian pulses and 0.35 for single pole exponential decay Another measure of bandwidth that is used by some manufacturers is the equivalent noise bandwidth, or the RMS bandwidth.2 In this case the relationship is: Tr ≈
K FRMS
(2.3)
where: FRMS RMS bandwidth Tr rise time (10%-90%) K depends on the pulse shape – 0.361 for gaussian pulses and 0.549 for single pole exponential decay 1 The F knee frequency in (2.1) is only related to the rise time of the digital waveform, and not the clocked frequency of the waveform 2 The noise bandwidth of a frequency response H(f ), or the RMS bandwidth, is the cutoff frequency at which a box-shaped frequency response would pass the same amount of white noise energy as H(f ).
2.3 Propagation, Time and Distance
Medium Air Coax cable (75% vel) Coax cable (66% vel) FR4 PCB, outer trace FR4 PCB, inner trace Alumina PCB, inner trace
19
Delay (ps/cm) 33.5 44.5 51 55–71 71 94.5–106
Relative Dielectric constant 1.0 1.8 2.3 2.8–4.5 4.5 8–10
Table 2.1: Propagation delays for electromagnetic fields in various media.
2.3
Propagation, Time and Distance
Another very important aspect to the propagation of digital signals is the distance that a signal propagates and the time it takes to propagate this distance. As we shall see these quantities are very important in determining whether we can consider a digital system in terms of lumped parameters, or whether we have to consider the propagation paths as distributed transmission lines. Table 2.1 shows propagation delays for a variety of media encountered in digital systems.
propagation delays
Remark 2.1 Propagation delay increases in proportion to the square root of the dielectric constant of the surrounding media. Therefore a coaxial cable manufacturer will attempt to make the dielectric media have a dielectric constant as close to that of air as possible in order to minimise the propagation delay. Notice that the outer trace figure for the printed circuit board track has a faster propagation velocity as compared to the inner track. This is due to the fact that more of the field produced by the outer track is in air, and therefore √ the overall dielectric constant is lower (v = c/ reff ).
2.4
Lumped Versus Distributed Systems
Now that we have considered the frequencies that are relevant in a digital system via (2.1), and we understand that the digital waveforms propagate at different velocities depending on the media that the wave is travelling through. This then naturally leads to the concept of lumped versus distributed representations of a propagation medium. Whether we can consider a medium to be represented as a lumped circuit or as a distributed circuit depends on how “long” an edge is in the medium. This concept is best understood via an example. However, before doing this we will write down a few of the basic expressions for transmission lines. The expression for characteristic impedance is: Z0 =
L0 C0
where: L0 line inductance per unit length C0 line capacitance per unit length
(2.4)
lumped circuit distributed circuit characteristic impedance
20
Introduction to Digital Switching The total delay for the transmission line is calculated using the formula:
Td = l
L0 C0
total delay
(2.5)
where l length of the transmission line. Clearly this means that the velocity of propagation in the transmission line is: v=√
1 L0 C0
(2.6)
Note 2.1 Equation 2.5 √ is the total line delay. Therefore the delay per unit √ √ length is D = L0 C0 ⇒ L0 C0 = r /c.
length of the rising edge
As an input pulse to a transmission line is rising from a low value to a high value the pulse is actually travelling down the transmission line. Therefore we end up with the pulse distributed with respect to distance down the transmission line. The length of the rising edge of a pulse is: Tr D
lr =
(2.7)
Example 2.1 Consider a transmission line with the following parameters; L0 = 4.6nH/cm and C0 = 1.1pF/cm. This transmission line was approximated using a series of LC elements as shown in Figure 2.1. Note that there is no inductance in the ground. Therefore we are assuming that there is a ground plane sufficiently wide so that its inductance can be ignored. The simulations of the line were carried out in the simulation package called Saber . Let us firstly work out a couple of the parameters for the line before we examine the simulation plots. Using (2.4) we can determine that Z0 = 64Ω. Using (2.5) the line delay is Td = 782ps, and the delay per cm is 71ps. 4.6e-9 v_pulse initial:0 pulse:5 t_r:0.5ns
p1
4.6e-9
1.1e-12
p2
4.6e-9
1.1e-12
p3
4.6e-9
1.1e-12
p4
4.6e-9
1.1e-12
p5
4.6e-9
1.1e-12
p6
4.6e-9
1.1e-12
p7
4.6e-9
1.1e-12
p8
4.6e-9
1.1e-12
p9
4.6e-9
1.1e-12
p10
4.6e-9
1.1e-12
p11
1.1e-12
64
Length = 11cm
Figure 2.1: Approximate transmission line. Figure 2.2 shows a series of voltage versus time plots for the ‘p’ points from Figure 2.1. The initial input voltage has a rise time of 0.5nsec. Notice the successive delay of the signals further down the transmission line. The total delay can be visually seen to be approximately 800psec, which is very near the theoretical calculation of the delay. The length of the pulse rising edge down the transmission line is from (2.7) calculated as 7cm. After some processing of the voltage versus time plots of Figure 2.2 one can generate voltage versus transmission line distance plots for various times after the application of the voltage signal. Three of these plots are shown Figure 2.3. Notice that the voltage propagates down the transmission line, and at various times before the voltage eventually stabilises at 5V the voltage is not uniform
2.5 Four Kinds of Reactance
21
with distance along the line. Furthermore the length of the voltage edge is approximately 6cm (compared to the theoretical calculation of 7cm for an ideal transmission line). At 410psec the pulse has not risen to 5V because of the 500psec rise time of the input voltage (which is typical for a digital logic signal). As one looks at Figure 2.3 the question of what constitutes a transmission line comes to mind. In other words when does one have to consider a line to be behaving as a transmission line, and when can a circuit be considered as a lumped circuit. The normal rule of thumb used is that a circuit can be considered as a lumped circuit if the line length is l/6, where l is the length of the rising edge defined by (2.7). The meaning of this can be seen in Figure 2.3, where we look at a length of short line which is approximately l/6 in length. Notice that over this length of line that the voltage difference across the line is approximately 0.9V. Therefore the voltage differences at points along the short line are not nearly as large as for the longer line. However, the point where we say that these differences are small enough to ignore is to a large extent arbitrary. Remark 2.2 An ideal lumped circuit does not have any propagation delay. In othe words the input signal is the same at all points in the lumped circuit. Clearly no circuit behaves in this way, but if the circuit dimensions are small relative to the length of the rising edge then the circuit can be approximated as a lumped circuit.
2.5
Four Kinds of Reactance
Reactive effects are very important in relation to the operation of digital circuits. The reactive effects can be classified into four categories: • Ordinary capacitance. • Ordinary inductance. • Mutual capacitance. • Mutual inductance.
2.5.1
Ordinary Capacitance
The term ordinary capacitance refers to a capacitance between elements of the same circuit. This almost always means the capacitance between the positive part of the circuit and the ground point of the circuit. This capacitance can be the result of a circuit component (a capacitor) or is can be a parasitic effect between wires or wires and a ground plane. The following is a quick review, since electrical engineers should already be familiar with most of this material. Consider a circuit of the form shown in Figure 2.4. Capacitive effects can be recognised in a circuit by the following: 1. A step change in voltage across a circuit that is primarily capacitive results in an initially high current flow, limited only by the resistance in the circuit.
lumped circuit
22
Introduction to Digital Switching
Voltage source pulse
p1
p11
6.0
5.0
4.0
3.0
2.0
1.0
0.0
200p
400p
600p
800p
1n
1.2n
1.4n
1.6n
1.8n
2.0n
t(s) Td ª 800psec
Figure 2.2: Time domain plots of voltages along a transmission line.
6
5
Voltage (V)
4 906psec 3
602psec 410psec
2
1 Short line voltage differential 0
0
2
4
6 8 Position down the tx line (cm)
10
12
Short line - 1cm =71psec
Figure 2.3: Voltage versus distance along a transmission line.
2.5 Four Kinds of Reactance
23
2. As t → ∞ the current through the circuit approaches zero – i.e. the capacitor becomes an open circuit. 3. At t = 0+ the voltage across the capacitor is zero. 4. As t → ∞ the voltage across the capacitor approaches the applied circuit voltage. Most of the features in Figure 2.4 can be deduced from the basic equation for a capacitor: dvc (t) (2.8) ic (t) = C dt For a circuit such as that of Figure 2.4 one has an exponential rise in the voltage across the capacitor. Assuming a infinitely fast rise time for the input waveform the voltage across the capacitor and the current into the capacitor can be shown to be: vc (t) = V (1 − e− RC ) t V ic (t) = e− RC R t
(2.9) (2.10)
Of course the waveforms are more complex when one has a rise time on the input waveforms. Equation (2.9) can be used to find the approximate capacitance associated with a circuit by considering the time constant of a rising signal. Of course one must know the resistance in the circuit in order to do this. Note 2.2 Capacitive circuits at high frequencies contain a mixture of effects from inductance and capacitance. For example, the leads into a capacitor have some inductance. If a edge with a fast rise time is applied to a capacitive circuit, and if a oscilloscope of sufficient bandwidth is used then one will see a short inductive voltage “spike” at the beginning of the exponentially rising voltage across the capacitor.
2.5.2
Ordinary Inductance
The treatment here is similar to that in the previous section on capacitance. The following discussion is with reference to Figure 2.5. As can be seen from this diagram the inductor is essentially an open circuit at the switching transient. However, as time proceeds the inductor impedance drops and eventually the inductor is a short circuit, with the circuit current being limited by the resistance. The basic equations for an inductor are: vL (t) = L
di dt
(2.11)
With the inductor in the circuit of Figure 2.5 we can write the following expressions for the voltage across the inductor and the current through the inductor (assuming the the rise time of the input voltage is zero):
24
Introduction to Digital Switching
R
ic (t )
+ + V (t )
C -
Vc (t )
-
V (t )
Current decays to zero ic (t ) Voltage becomes V (t ) Vc (t )
Vc (t ) ic (t )
Initially short circuit
Starting to become an open circuit
Figure 2.4: Examples of capacitive circuit waveforms.
2.5 Four Kinds of Reactance
25
R
iL (t )
+
+ VL (t )
L
V (t )
-
-
V (t )
Current approaches
V (t ) R
iL (t )
Output voltage decays to zero VL (t )
Long-term impedance is zero
VL (t ) iL (t )
Inductor essentially open circuit here
Figure 2.5: Examples of inductance circuit waveforms.
26
Introduction to Digital Switching
vL (t) = V e− L tR V iL (t) = (1 − e− L ) R tR
area under the inductor voltage
(2.12) (2.13)
In order to evaluate the inductance of a circuit one could again use the time constant of the exponential rise of the current, or the exponential fall of the voltage. These measurements are often difficult to make accurately. A better technique is based on the area under the voltage response of the circuit. The validity of this method is shown via the following analysis. Consider the expression for the area under the inductor voltage :
∞
∞
vL (t)dt = L ∴
0 ∞
0
diL (t) dt dt
vL (t)dt = L(iL (∞) − iL (0))
(2.14) (2.15)
0
Therefore one can see that the area under the inductor voltage curve is equal to the total change in current through the inductor multiplied by the inductance value. Hence one can write: area (2.16) L= ∆iL where ∆iL = iL (∞) − iL (0). Equation 2.16 can be further refined if we use the fact that the resistance is known (as this test is usually carried out in a test circuit where we select the resistance). Therefore we can write:3 ∆IL =
∆VL R
where ∆V = vL (0) − vL (∞). This allows (2.16) to be written as: (area)R L= ∆VL
(2.17)
(2.18)
Practical Issue 2.1 Equation 2.18 allows a noise free evaluation of the inductance, as the area calculation effectively filters noise from the measurements. Note 2.3 Equation (2.18) is only valid when the circuit with the inductance has only a resistive element. If a capacitor, for example, is included then the expression does not give the correct result. Practical Issue 2.2 It is often useful to be able to guesstimate the inductance of a length of wire. The bottom line is that a wire loop has approximately 0.5–1 µ-henries of inductance per metre of length, or 5–10 nano-henries of inductance per centimetre. The variation is due to wire spacing, wire diameter and shape 3 Equation (2.17) implicitly depends on the fact that i (0) = 0 and i (∞) = V /R and L L vL (0) = Vin and vL (∞) = 0. Therefore ∆VL = Vin .
2.5 Four Kinds of Reactance
27
of the loop of wire. For loops with a large diameter the inductance is a weak function of the wire diameter (as one would intuitively reason). In order to place this guesstimate on a more sold theoretical footing let us consider the approximate inductance of a circular loop of wire with a loop radius of “a” and a wire radius of “R” [7]: L = µ0 a[ln
8a R
− 2]
(2.19)
Using this expression the inductance of a 1 metre circumference loop of 14 gauge wire is 1.07 µH; for 16 gauge wire it is 1.12µH and for 18 gauge wire it’s 1.16µH. Note the weak dependence of inductance on wire diameter. This is due to the natural log in the expression. For two parallel wires, spaced d metres apart, each wire with radius R and with line length l metres the inductance of the loops is [7]: L=
µ0 l π
ln
d −1 R
(2.20)
Applying this formula to the situation of parallel wires with l = 0.5metre and a wire-to-wire spacing d = 1cm, we get L0 = 0.485µH for 14 gauge wire; L0 = 0.53µH for 16 gauge wire; and L0 = 0.58µH for 18 gauge. Therefore the inductance is approximately 0.5µH per metre (or 5nH per cm) for the total wire length. When we have closely spaced wires we get partial field cancellation. For example if the wires are co-incident then we get total field cancellation (and no net current of course). This effect can be seen diagrammatically in Figure 2.6 where the field is reinforced in between the conductors, but cancels on either side of them. The area between the conducts obviously becomes smaller as the conductor spacing decreases, and would be zero if they are co-incident. Because the area decreases and more of the field lines are cancelled as the conductors are moved closer, then the inductance falls (as noted above). Another useful expression is for the inductance of a rectangular loop with dimensions of length “x” centimetre and width “y” centimetre and the wire has a diameter of “d” centimetre [1]: −9
L = 4 × 10
2y 2x x ln + y ln d d
(2.21)
where L inductance in Henry. The expression for the inductance of a round wire sitting above a ground plane (this is a good model for a wire wrap on a wire wrap board) is [1]: 4h nH L = 2x ln d
(2.22)
where h the height of the wire above the ground plane; d the diameter of the wire; x the length of the wire in centimetres.
28
Introduction to Digital Switching
Field reinforcement
Conductors
Field lines Field cancellation
Figure 2.6: Field reinforcement and cancellation with parallel conductors.
2.5 Four Kinds of Reactance
2.5.3
29
Mutual Capacitance
Mutual capacitance refers to the inevitable parasitic capacitance that exists between any two elements in a circuit. Voltages in one circuit can result in voltages and currents in the other circuit due to the coupling effect of this capacitive element. The physical mechanism of this interaction is the electric fields associated with the mutual capacitance. The current that flows through the mutual or parasitic capacitance of obeys the same circuit equation as the ordinary capacitance expression: im = Cm
dvAB dt
(2.23)
where: im current flowing through the capacitor. Cm the parasitic capacitance (Farads). vAB the voltage across the capacitance. Equation (2.23) is an exact value of the current flowing through the capacitor. However, under certain assumptions one can ignore the difference in voltages across the capacitor and assume that the current is due solely to the voltage change in circuit A or B. If we assume that circuit A is the circuit with the voltage change then the assumptions are: 1. The coupled current flowing in Cm is much smaller than the primary signal current in circuit A. Therefore the capacitance does not load circuit A. 2. The signal voltage coupled in circuit B is smaller that the signal on A. Therefore the small coupled voltage in B can be ignored and the voltage across the capacitor can be considered to be vA . Note that this is also making an assumption about the impedance to ground of circuit B. 3. The capacitor is a large impedance compared to the impedance to ground of circuit B. The noise voltage is calculated as the noise current im times this impedance. Other interactions with the functioning of the secondary circuit are ignored in this analysis. Remark 2.3 When the coupled noise voltage is less than 10% of the signal step size these approximations are accurate to about one decimal place. This is good enough to tell whether one has a problem with coupled noise. If the coupling is greater than 10% then a digital circuit probably won’t work anyway. 2.5.3.1
Relationship between Mutual Capacitance and Crosstalk
If ones knows the mutual capacitance (Cm ), the rise time of the interfering waveform (Tr ), and the impedance of the receiving circuit (RB ), then one can estimate the crosstalk as a fraction of the interfering waveform (vA ). Therefore one can write: ∆V dvA ≈ (2.24) dt Tr where ∆V the height of the driving waveform.
parasitic tance
capaci-
30
Introduction to Digital Switching Therefore the mutual capacitance current is: im ≈ Cm
∆V Tr
(2.25)
The crosstalk expression can now be written by realising that the capacitor current im flows through the circuit B impedance to ground, thereby generating a voltage equal to im RB . Therefore crosstalk is this voltage relative to the driving voltage: Crosstalk =
RB Cm RB im = ∆V Tr
(2.26)
In situations where there are multiple sources of crosstalk simply algebraically add together the crosstalk from all the sources to get the total crosstalk. One can develop an expression similar to that of (2.18) for the capacitance. Using (2.23) one can can write an expression for the integral of the current through the capacitor:4 ∞ ∞ dvA dt im (t)dt = Cm dt 0 0 ∞ 1 ∴ vRB (t) dt = Cm [vA (∞) − vA (0)] = Cm ∆V (2.27) RB 0 Rearranging (2.27) we can write: Cm = crosstalk
voltage area across RB RB ∆V
(2.28)
One can then substitute (2.28) into (2.26) to get the crosstalk . Example 2.2 This example comes from [1]. Consider the situation in Figure 2.7, which depicts two resistors on a FR-4 printed circuit board (which is a 0.063in thick epoxy board). Note that the board has a ground plane on the noncomponent side. We are interested in the coupling between the two 1/4 watt resistors R2 and R3 . R1 is on the board to terminate the driving signal from the pulse generator. Consider that the signal generator drives the a 2.7V signal with a rise time of 800ps. We can simulate this situation to get some idea of what would happen (in [1] experimental data is presented). An approximate circuit for the situation in Figure 2.7 is shown in Figure 2.8. This circuit has been implemented in the Saber simulation package. If we integrate the area under the voltage across the RB resistor then we should be able to estimate the coupling capacitance. Figure 2.9 shows the output of the simulation with the resistors in Figure 2.8 each being 25Ω and the mutual capacitance 0.4pF. Note the plot of the integral of the output voltage – its value is 54pV-sec. To work out the mutual capacitance we use this value in (2.28): 54 × 10−12 50 × 2.7 = 0.4pF
Cm =
4 We
will be using the fact that im (t) = vRB (t)/RB .
(2.29)
2.5 Four Kinds of Reactance
31
Therefore the calculation predicts the correct value for the capacitance. The cross coupling can be evaluated using (2.26): Crosstalk =
RB Cm (50 × 0.4pF ) = 0.025 = Tr 800ps
(2.30)
One interesting point about Example 2.2 that was not obvious is that it does not matter where one imagines the coupling capacitor to be in relation to the resistors. For example, if we imagine that the effective capacitor is connected as shown by the dashed capacitor in Figure 2.8 and we carry out the same simulation then for all practical purposes the plots we obtain as exactly the same as those obtained for the first case. This seems counter intuitive at first since in this configuration we have halved the amount of resistance in the circuit. There is little difference however because it is the effective impedance of the capacitor that is dominating the circuit. This dominance together with the ramping input voltage effectively makes the voltage source capacitor combination behave as a high impedance source – i.e. as an effective current source. Therefore the current flowing in the load resistance is not effected by the change in the overall circuit resistance.
To oscilloscope R3
RB = 50W Cm
From pulse generator 50W R1 = 50W
R2
Cm
R3
R2
0.063in
0.1in Solid ground plane Figure 2.7: Mutual coupling example between resistors. The effective impedance of the capacitor to the rise edge of the voltage can be roughly calculated by evaluating the frequency content of the edge using (2.2). Applying this to the test waveform we find that the frequencies in the
32
Introduction to Digital Switching
R3
{ {
50W
Cm
V
50W
Output voltage
Other parasitics
R2
Figure 2.8: Equivalent circuit for mutual capacitive coupling example.
Centre tap capacitor (25 Ohm) (V*sec)
60p
: t(s)
integ(output_voltage)
40p
(1.1558n, 53.944p)
20p 0.0 (A) : t(s) i(m)
0.002 0.001 0.0 -0.001 -0.002
(V) : t(s) output_voltage
0.08 0.06 0.04 0.02 0.0
(V) : t(s) input_voltage
4.0 3.0 2.0 1.0 0.0
0.0
500p
1n
1.5n
2n
t(s)
Figure 2.9: Simulation plots for capacitor cross coupling.
2.5 Four Kinds of Reactance
33
signal go to 437.5MHz – i.e. the -3db point in the signals frequency content. If we consider a sine wave at this frequency then the impedance magnitude of the coupling capacitor is (using the standard impedance expression):
Zceff =
1 ωCm
(2.31)
1 2π × 437.5 × 106 × 0.4 × 10−12 = 909Ω =
which is much greater than the total resistive component of 100Ω. Hence the current flow is governed totally by the rate of change of voltage across the capacitor. This can be checked by calculating this rate of change and using it in (2.8). Therefore we have: icm = Cm
dvcm dt
= 0.4 × 10−12 = 0.00135A
2.7 800 × 10−12 (2.32)
which is the same number as can be seen in the capacitor current plot of Figure 2.9. We can assume that all the voltage appears across Cm because of its relative impedance compared to the resistors. Note 2.4 The above example is implicitly using the assumptions list in Section 2.5.3. The low values of the resistors in the circuit compared to the effective impedance of the capacitor means that the current flowing through the parasitic element is small compared to main current flowing in the pulse generator section of the circuit. In other words the mutual capacitance does not load down the circuit. This is another way of reasoning that we can use the driving voltage as the voltage across the capacitor (instead of having to calculate the voltage). However, if the resistive impedances were significantly larger then we could no longer use this assumption. What happens if we ground the floating end of the R2 and R3 ? Looking at the situation intuitively, the voltage appearing at the mid point of R2 would be halved by voltage division. The current flowing through Cm capacitor would divide in circuit B in two directions. One path is directly to ground via one half of the R3 resistor , and the other is into the oscilloscope. Due to the relative magnitudes of the resistors current division results in 3/4 of the capacitor current flowing into the grounded resistor and 1/4 flowing into the oscilloscope. Therefore the voltage in the oscilloscope would be 1/8th of the original voltage. We shall test this reasoning via the simulation. Modifying the circuit as described we get the results shown in Figure 2.10. As can be seen from this figure the output voltage is approximately 1/8th that in Figure 2.9 verifying the heuristic discussion in the paragraph above. Note 2.5 If the coupling capacitance was to be calculated in this case then one has to halve the circuit A voltage (to account for the grounding in this circuit)
34
Introduction to Digital Switching and take into account the current division in circuit B. One cannot blindly apply the integration of the output voltage technique without accounting for the impedances in the circuits.
Centre tap cap-resistor to gnd (A) : t(s) 800u
i(m)
600u 400u 200u 0.0 -200u
(V) : t(s)
0.01 0.008 0.006 0.004 0.002 0.0
output_voltage
(V) : t(s)
3.0
input_voltage
2.0 1.0 0.0 0.0
500p
1n
1.5n
2n
t(s)
Figure 2.10: Relevant capacitive coupling waveforms with resistors grounded.
2.5.4
mutual inductance coupling mutual inductance
Mutual Inductance
Whenever we have current flowing in a circuit there is magnetic flux produced around the conductor. We can influence the magnitude of the flux density produced by changing the dimensions of the conductor and arranging the return current path so that we can get some cancellation effects. When the flux density produced by one conductor-current combination induces a voltage and/or current into another conductor that is not part of the same circuit then we say that we have mutual inductance coupling between the two circuits. The magnitude of the mutual inductance coupling is related to two variables – a coefficient called the mutual inductance between the circuits, and the time rate of change of current in the originating circuit. The mutual inductance coefficient measures the flux per unit current linking the coupled circuit, and has the units of Henries or volt-seconds/amp.
2.5 Four Kinds of Reactance
35
Remark 2.4 Two circuits with mutual inductance between them is analogous to a very small air cored transformer, where the originating circuit is the primary, and the coupled circuit is the secondary. As in the transformer situation, the mutual inductance coefficient has the same value regardless of which circuit is the primary. A mutual inductance Lm between circuit A and B injects a noise voltage vm into B proportional to the rate of change of current in circuit A according to the mathematical relationship: diA (t) (2.33) dt Remark 2.5 Equation 2.33 is exactly the same equation as the standard inductance equation. vm (t) = Lm
Remark 2.6 Equation 2.33 demonstrates the fact that rapid changes in the current in circuit A will induce substantial voltages in circuit B, even under conditions of very low Lm . Hence the importance in digital circuits. Practical Issue 2.3 In digital systems the mutual inductive coupling is usually larger than the capacitive mutual coupling. Figure 2.11 shows a typical situation in a digital circuit where mutual inductive coupling may occur. Notice that the voltage induced effectively appears in series with whatever voltage is being produced at the source end of circuit B. Depending on the direction of the current the induced voltage may add to the source voltage of circuit B, or it may subtract. Another fact that can be seen from the figure is that current in circuit B can influence the current in circuit A (using the same mutual inductance process). However, in the following analysis we shall make some assumptions so that these effects can be ignored.5 One can use (2.33) to carry out mutual inductance calculations in digital circuits under the following assumptions: 1. The voltage induced due to Lm is much smaller than the primary signal voltage. Therefore the presence of Lm does not load down circuit A. The noise voltage coupled to circuit B is always smaller than the signal voltage in digital products. 2. The coupled signal current in circuit B is smaller that the current in A. We can ignore the small coupled current in B and assume that the difference between the primary and secondary currents is iA . 3. Assume the secondary impedance is small compared to the impedance to ground of circuit B. The coupled voltage is added to the circuit B source voltage, and interactions of the coupled voltage with circuit B are ignored. Remark 2.7 The above assumptions, if true, mean that we can consider what is happening in circuit A without having the worry about the reciprocal effects from circuit B back into A. This greatly simplifies thinking about these effects, and gives answers that are accurate enough to allow one to find out if there is a mutual inductance coupling problem. The assumptions made in Section 2.5.3 in relation to mutual capacitance also allowed this to be done in that case. 5 These
are similar to the assumptions made in the capacitive coupling case.
assumptions
36
Introduction to Digital Switching Source of the changing current Circuit A iA (t ) RA Lm
+
vm (t )
-
Circuit B Low impedance
Coupled noise voltage from circuit A appears here
Figure 2.11: Example of mutual inductance in a digital system. Remark 2.8 Mutual inductance coupling differs from its capacitive counterpart in that voltages of differing polarities can be induced depending on the relative direction of the current in the primary circuit. The relative direction can be different depending on the physical layout of the circuit. The magnitude of the voltage is also very susceptible to the orientation of the primary and secondary circuits. Faraday’s Law
From Faraday’s Law we know that the voltage induced in a loop of wire due to a uniform magnetic flux density of B tesla is: v=
dφ d(BA) = dt dt
(2.34)
where A the area of the loop through which the magnetic flux density passes.6 Equation (2.34) clearly indicates that for a given flux density that the voltage induced in a coil is proportional to the area of the coil. Therefore, in order to keep the mutual inductance low the loop area of the secondary circuit should be kept as small as possible. The sensitivity of the induced voltage to the orientation of the sending a receiving circuits can also be seen. The flux density in (2.34), as mentioned previous is the component of the flux density that is orthogonal to the surface of the coil area. Therefore, if the flux density has a zero orthogonal component then the induced voltage would be zero. Practical Issue 2.4 An approximate expression for the mutual inductance between two loops can be obtained under the condition that the separation of loops is far enough to satisfy the following condition: 6 Note that we are assuming that the flux density is orthogonal to the surface of the loop in this expression.
2.5 Four Kinds of Reactance
37
d> d>
A1
(2.35)
A2
(2.36)
where A1 the area of loop 1 in cm2 , and A2 the area of loop 2 in cm2 and d the distance between the loops in cm. It is assumed that the loops are parallel to each other (i.e. the mutual inductance is maximised). The expression for the mutual inductance is therefore: Lm ≈
2A1 A2 d3
(2.37)
where Lm the mutual inductance in nano-Henry. The mutual inductance between two parallel wires suspended above a ground plane is given by:
Lm = L
1+
1 s 2
(2.38)
h
where: s separation of the two conductors h height of wires above the ground plane L self inductance of one of the wires 2.5.4.1
(2.39)
Relationship Between Mutual Inductance and Crosstalk
Given a known mutual inductance, a waveform rise time Tr , and a source impedance in the driving circuit A equal to RA we may estimate the crosstalk relative to the driving voltage vA . Following a procedure similar to that in Section 2.5.3.1 we can derive the following expressions for the mutual induced voltage and crosstalk. We shall assume that circuit A is resistively damped by RA , so the current in this circuit is essentially given by Ohms Law. This is the normal situation if the drive is into a transmission line that is terminated. Therefore using (2.24) and Ohms Law we can write: ∆V diA (t) = dt R A Tr
(2.40)
We can now calculate the mutually induced voltage appearing in circuit B: vm = Lm
∆V R A Tr
(2.41)
The final part of the derivation is the divide by ∆V to get the inductive crosstalk : Crosstalk =
Lm R A Tr
(2.42)
inductive crosstalk
38
Introduction to Digital Switching Practical Issue 2.5 Similarly to the capacitive coupling case there are usually multiple sources of coupling in practical situations. To calculate the inductive coupling in these cases estimate the mutual coupling from each of the individual sources and then add together the individual cross couplings to give the total. Example 2.3 This is a similar example to Example 2.2 for the capacitive cross coupling. The approach will be similar, in that we shall consider the coupling between two resistors. Figure 2.12 schematically shows the test circuit. The physical configuration of the resistors is shown in Figure 2.13. Notice that some lines of flux density emanating from the circuit A resistor link the circuit loop containing resistor B, and if these flux density lines change with respect to time then a voltage will be induced in circuit B (as shown in Figure 2.12). In this example we assume that the self inductance of the resistors is 10nH, and the mutual inductance between them is 1nH. The scope connection is assumed to have an impedance of RT , and consequently the induced voltage is divided between the RB resistor and the RT resistor. Usually the scope termination is 50Ω so the voltage across the scope input will be halved. In a manner similar to the estimation of the capacitance in the capacitive coupling situation we can estimate the inductance using (2.18). We shall setup a simulation of this example in the Saber simulator. The equivalent circuit is shown in Figure 2.14.7 A plot of the important variables in the simulation appear in Figure 2.15. Notice that the area of the voltage appearing across the load is 26.908pV-sec. Therefore substituting this into the area section of (2.18) with the value of the resistor R = 2RB = 100Ω and ∆V = 2.7V then we get Lm = 0.996nH ≈ 1nH.8 The inductive crosstalk can be calculated using (2.42) (remembering to use RB + RT for the resistance): Crosstalk =
1.0 × 10−9 = 0.0125 100 × 800 × 10−12
(2.43)
The crosstalk due to the capacitance in this situation is from (2.30) 0.025/8 = 0.003 (remember the grounded resistors result in an 8 fold reduction in the crosstalk). Hence the inductive crosstalk in this situation is four times the capacitive crosstalk. Note 2.6 If we were physically carrying out this experiment we would not only have the inductive coupling present, but we would also have capacitive coupling. Due to the way the capacitive coupling test was carried out in (2.2) we have very little inductive coupling (there is no through current in the components). Therefore, the capacitive coupling can effectively be separated from the inductive coupling. For this particular situation we could therefore subtract the capacitive area/8 (remember the resistors are grounded – see Example 2.2) from the area measured and then do the inductive calculation. 7 Note that one could easily solve this circuit analytically, but the simulation approach allows one to play with the values and ready obtain plots. Furthermore it is analogous to doing an experiment. 8 Note that we are using 2R in the expression since the voltage in the coil is being halved B due to the voltage division effect caused by the presence of the scope impedance.
2.5 Four Kinds of Reactance
39
Input From pulse generator
RA Lm
50W RB
+ v m 50W
To scope Output Figure 2.12: Measurement setup for mutual inductance experiment.
0.063in
RB
RA
0.1in Solid ground plane Flux density field lines
Flux density lines linking resistor B.
Figure 2.13: Physical configuration of resistors in inductive coupling experiment.
40
Introduction to Digital Switching
L = 10nH RB
50W
Lm = 1nH
RT
50W (Scope)
RA
50W
L = 10nH Tr = 800ps
50W
Figure 2.14: Equivalent circuit for simulation of inductive mutual coupling. Remark 2.9 We have included the derivative of the current in Figure 2.15. This is shown in order to allow comparison of this simulation with a later one where load capacitance has been included in the modelling. Practical Issue 2.6 In most high speed digital systems the inductive coupling is more significant than the capacitive coupling. The reason for this has not been answered in this section, but will be given in Section 2.6.2.
2.6
minimum output switching time
propagation delay
Speed of Digital Systems
In many discussions of digital systems there is a concentration on the propagation delay of the particular logic gates being used. However, many practical problems in digital systems are related to the minimum output switching time (i.e. the minimum time to switch from high to low or vice versa). As we have seen in previous sections of this chapter the problems crosstalk increases considerably with increased rate of change of switching edges. Generally speaking, logic families that have switching times much faster than their propagation delay are suffering problems related to fast switching edges without any advantage from a logic design viewpoint – the speed and timing of the system is governed by the propagation delay. Practical Issue 2.7 Given two logic families with identical propagation delays, the logic family with the slowest output switching times will be easier and cheaper to use. In recognition of these facts some more recent logic families now incorpo-
2.6 Speed of Digital Systems
41
Inductive coupling (A/s) : t(s) 80meg 60meg 40meg 20meg 0.0 -20meg
(880.7p, 65.891meg)
deriv(i(l.l1))
(A) : t(s)
0.06
i(l.l1)
0.04 0.02 0.0
(V*sec)
0.0 (2.0486n, -26.908p)
integ(output)
-20p -40p
(V) : t(s)
0.02
output
0.0 -0.02 -0.04
(V) : t(s)
4.0
input
2.0 0.0 0.0
500p
1n
1.5n
2n
: t(s)
2.5n
t(s)
Figure 2.15: Results of the inductive cross coupling simulation.
42
Introduction to Digital Switching rate circuitry to slow down the switching edges to acceptable levels.9 Prior to this the switching edges were largely uncontrolled. For example, a technology in the early 1980s for output drivers on high speed logic circuits was VMOS. These output devices had very fast switching times, but they made it extremely difficult to build a printed circuit board that would work.10
2.6.1
dv/dt Effects
It was mentioned in (2.1), repeated here for convenience, the spectral content of a digital signal is directly related to the rise time of the signals in the circuit: Fknee =
0.5 Tr
(2.44)
Therefore as the rise time becomes smaller, then the frequencies which the circuit has to cope with increase. Therefore, all data paths, integrated circuit packages and physically layout has to be able to function with frequencies up to this value. As noted in (2.26) and (2.42) both the capacitive and inductive crosstalk are inversely proportional to the rise time of the voltage (Tr ). Since crosstalk is a relative measure then it is independent of ∆V . Therefore the T10−90 edge time is the really important value and not ∆V .
2.6.2
capacitive loading component
di/dt Effects
In Sections 2.5.3 and 2.5.4 we were able to relate the dv/dt of the output waveforms to the di/dt of the currents using the simple approximation that the circuit was predominantly resistive. However, in practical digital systems the load on a logic element is not only resistive but also it also has a capacitive loading component.11 The capacitance present in digital systems has two components – the capacitive of the printed circuit board tracks themselves, and the capacitance of the input to the logic gates. Usually the latter of these two will be the dominant one.12 The presence of the load capacitance has an effect on the rate of change of current. To examine this effect consider a typical circuit shown in Figure 2.16. This shows a gate driving a combination resistor/capacitor load (i.e. a typical model for the input of a gate). The current i(t) flowing in the output line of the gate can be calculated as follows: i(t) =
v(t) R Resistive current
+
dv(t) C dt
(2.45)
Capacitive current
In order to calculate the effect that this current has on the inductances in the circuit we have to differentiate (2.45) with respect to time: 9 In fact circuitry of this nature was introduced in the MECL 10K family in 1971, but is wasn’t until 1990 that it was introduced into the more common FCT CMOS family. 10 This was especially true in the early 1980s as there were no such things as 4 layer printed circuit boards that included power supply planes. 11 It even has an inductive component if one considers the lead wiring. 12 This capacitance is due to the input transistor plus the input lead and package capacitance.
2.6 Speed of Digital Systems
43
i(t )
v(t )
R
C
Figure 2.16: Logic gate with a capacitive load.
1 dv(t) d2 v(t) di(t) = +C dt R dt dt2
(2.46)
Remark 2.10 Equation (2.46) shows that the rate of change of current when capacitance is present is a function not only of dv(t)/dt, but also of d2 v(t)/dt2 . Therefore if dv(t)/dt is increasing by a factor of two the rate of change of current (due to the capacitive component) will increase by a factor of four. Note that a constant ramp (i.e. dv(t)/dt =constant) has d2 v(t)/dt2 = 0, and therefore in this case there is no effect. Note 2.7 The squared dependence of di(t)/dt on the rate of rise of voltage when there is a capacitive load is one of the main reasons that inductive coupling is usually worse than capacitive coupling in digital circuits. We shall investigate the effect that the presence of capacitance has on the inductive cross coupling in circuit of Figure 2.14. The input waveform still has a rise time TR of 800p-sec. We shall add a 10pf capacitor to the RA resistor in this figure. For comparison Figure 2.15 shows the results when there is no capacitive loading in the circuit. The results of simulating the capacitive circuit appear in Figure 2.17. We can make several observations from Figure 2.17: • The fact that we have an LC circuit means that the circuit will ring. This can be seen in the oscillatory behaviour in the output voltage and the primary side inductor current. • The maximum rate of change of current in the circuit is of the order of 1.2 × 108 Amp/sec. Compare this to that in Figure 2.15, where we have a maximum di(t)/dt of 6.5 × 107 Amp/sec. • Because the di(t)/dt for Figure 2.17 is twice that of Figure 2.15 then the mutually coupled voltage into circuit B is approximately twice (as can be seen by comparing the two figures). These observations therefore confirm the assertions made in Practical Issue 2.6 and Note 2.7 that the presence of load capacitance significantly enhances the cross coupling due to mutual inductance.
44
Introduction to Digital Switching
(A/s) : t(s)
200meg
deriv(i(l.l1))
(A/s)
100meg 0.0
(A)
-100meg
(A) : t(s)
0.1 0.08 0.06 0.04 0.02 0.0
i(l.l1)
(V) : t(s)
(V)
0.04 0.02 0.0 -0.02 -0.04 -0.06 -0.08
output
(V) : t(s)
(V)
3.0
input
2.0 1.0 0.0 0.0
500p
1n
1.5n
2n
2.5n
t(s)
Figure 2.17: Inductive coupling waveforms with a 10pf load capacitance.
2.6 Speed of Digital Systems
2.6.3
45
Ground Bounce
Ground bounce is an inductive effect caused by the inductance of the leads in the packages used for integrated circuits. This phenomena causes glitches in the logic inputs whenever the device outputs switch from one logic state to another. 2.6.3.1
Why Does Ground Bounce Occur?
The following discussion is with reference to Figure 2.18 which is a schematic of a four pin integrated circuit with bonded wires. One transmit and receive circuit are shown. Suppose switch B is closed discharging the load capacitor C to ground. This results in a load current flowing around this loop. As this current increases and decreases there is a voltage induced across the lead inductance causing a voltage to be induced: vGN D = LGN D
didischarge dt
VCC
Totem pole output drivers
SW A vin
(2.47)
Output circuit
+ SW B
+ vGND
LGND Ground pin inductance
idischarge
C
Ground Plane Figure 2.18: Schematic of an integrated circuit showing the lead inductance. This induced voltage shifts the internal ground reference from the board ground plane. It is this phenomena that is called ground bounce. The voltage vGN D is usually small compared with the output voltage swing and does not significantly impair the transmitted signal. However, it can have dramatic effects on the reception of signals. Note 2.8 In Figure 2.18 we can see that the input circuit is sensing the input voltage relative to its own local ground rail (as emphasised by the differential amplifier representation of the input circuit). This situation is representative of the TTL logic family. Other logic families (e.g. ECL and GaAs) compare the
glitches
46
Introduction to Digital Switching input to VCC . CMOS circuits tend to compare inputs against a weighted average of VCC and ground. The other important issue in relation to the references is the reference for the outputs. In the case of TTL if the output is high then the output reference is VCC (since the bottom output transistor is open circuit), and when the output is low then the reference is the 0V rail. Note that the output reference does not necessary match the input reference, and this must be carefully considered when looking at the effects of noise on the ground and VCC rails. Consider the situation depicted in Figure 2.18. The input voltage seen on across the differential input amplifier is: = vin − vGN D vin
(2.48)
In this equation vGN D can be either positive or negative depending on the direction of the current through the ground lead inductance. From the point of view of the input the noise voltage across the lead inductance is effectively superimposed on the input voltage. If there is only one output switching then ground bounce should not cause a problem. However, in an IC with N outputs switching at the same time then the problem will get N times worse. Further exacerbation can occur if the N outputs are driving capacitive loads, since as noted in Note 2.7 the rate of change of current increases under these conditions. This leads to a double humped waveform in the ground bounce voltage, as can be deduced from the current derivative waveform in Figure 2.17 (since v = Ldi/dt). 2.6.3.2
self clocking
How Does Ground Bounce Affect Circuits?
Consider the situation of a set of octal D flip flops with an edge triggered clock input. The circuit has a setup time for data of 3nsec and a hold time of 1nsec. The propagation delay is 3nsec. The flip flops are driving a bank of 32 memory chips, each chip with an input capacitance of 5pf. Therefore the total capacitive loading on each of the flip flop outputs is 160pf. The following discussion is with respect to Figure 2.19. At time A the inputs to the flip flops are FF Hex. These inputs are clocked into the latches, and after the propagation delay they appear at the outputs. At time B the outputs have been changed to 00 hex and the clock then clocks this into the latches. However, due to the simultaneous switching of the outputs coupled with the large capacitance of the load there is a significant voltage induced across the ground lead inductance. This voltage is delayed by the 3nsec propagation time of the flip flop. However, if after the 1nsec hold time the inputs to the flip flops have changed to an arbitrary XX hex value then one could have a problem due to the glitch that the ground bounce places on the clock line into the flip flops. This glitch will latch the new value on the data lines into the flip flops, and hence an erroneous value is now stored. One would observe the correct value momentarily appearing on the outputs, followed by the incorrect value. Self clocking problems such as this can occur in DIP (dual inline packages) which has very fast output drivers connected to capacitive loads – for example large FCT latches. If these circuits are in surface mount packages then the problems are significantly reduced due to the lower lead inductance in these packages.
2.6 Speed of Digital Systems
Propagation delay Time A 3nsec
47
Time B Time C Time D After clock glitch outputs may switch to another state
Q outputs
FF
Data bus
FF
00
00
XX
XX
3nsec setup 1nsec hold Clock
VGND
Ground bounce noise
Clock - VGND
Glitch at Time D clocks XX into the latches
Figure 2.19: Example waveforms for an octal latch driving a capacitive load.
48
Introduction to Digital Switching
∆Vmax (V) T10−90 (ns)
74HCT CMOS 5 4.7
74AS TTL 3.7 1.7
10KH ECL 1.1 0.7
10G GaAs 1.5 0.15
NEL GaAs 1.0 0.05
Table 2.2: Typical switching characteristics of common logic families. 2.6.3.3
Estimating Ground Bounce Magnitude
One needs to know four things to estimate the ground bounce in a circuit: 1. The 10% to 90% switching time of the outputs. 2. The load capacitance or resistance. 3. The lead inductance to ground. 4. The output voltage swing. For a resistive load the voltage induced in the lead inductance is obviously: |vGN D | =
LGN D ∆V R T10−90
(2.49)
If we have a capacitive load, and assuming a gaussian shape for the derivative of the input step, then it is possible to show that the rate of change of current is [1]: d2 v dic ∆V = C 2 = 1.52C 2 dt dt T10−90
(2.50)
and hence the voltage induced is: |vGN D | = 1.52LGN D C
∆V 2 T10−90
(2.51)
Typical values for switching times and voltage swings for common logic families appear in Table 2.2. 2.6.3.4 package
multiple wires
ground
Reducing Ground Bounce
One can deduce from the previous discussion that ground bounce is primarily a function of the switching characteristics and the package which the IC is mounted in. For a given package one way to alleviate ground bounce is to slow down the output switching speeds. The FCT CMOS and 10K ECL families and newer bus drivers incorporate circuitry to slow down switching edges. Another strategy for reducing ground bounce is to lower the lead inductance. This can be achieved by using different package designs. If we consider the more conventional packaging technology one technique is to put multiple ground wires on the package. It is best to evenly space these around the package. If the grounds are all near each other, then going from one to two grounds halves the inductance. However, there is a diminishing return by increasing the number of grounds above this.
2.6 Speed of Digital Systems
internal reference
Some other components attack the problem by bringing out a separate wire for the internal reference. An example of a family that does this is the 10K ECL family. This separate pin does not carry the large ground currents and therefore does not suffer ground bounce. Differential inputs are an even more effective technique to achieve the same end. If one is prepared to embrace more radical packaging technologies then the lead inductance can be decreased considerably. The most promising techniques are wire bond, tape automated wire bond (TAB) and flip-chip. All of these techniques involve mounting the chip directly on the printed circuit board – i.e. the lead inductance has been eliminated by eliminating the package. Wire bonding is a technique akin to the bonding technique used in the current integrated circuit packages. The IC is placed back side down on the printed circuit board, and one the top side there are a number of small pads on the chip. Very fine wires are then bonded to these pads and then bonded to a corresponding connection on the printed circuit board. The IC and the wires are covered with a covering material and then the whole lot is hermetically sealed with a lid. This technique has the capability of hand production for small volumes. Tape bonding is an enhancement of the wire bonding technique. It uses a flexible circuit with wire tapes on it. This flexible circuit may have multiple layers, including a ground to control impedances. This is overlaid on the IC so that the wire tapes align with the IC pads (which have solder balls on them) and the printed circuit board connections. The tape wires are then reflow soldered to the IC and the printed circuit board and the whole lot sealed as in the wire bonded case. Therefore this technique improves on the wire bonding by providing a much faster technique of connecting the wires all at once. The multilayer capability also improves the signal transmission. The disadvantage of the technique is that the flexible circuit must be changed if there is any change to either the IC or the printed circuit board connection points. The flip-chip technique places solder balls on each chip attachment pad. The chip is then placed face down on the printed circuit board and directly reflow soldered in place. This technique is often using in ceramic multi-chip structures that incorporate advanced cooling techniques. The whole device is hermetically sealed. From the inductance viewpoint this technique is excellent, as the lead inductances are almost totally eliminated. However, from a mechanical and thermal viewpoint it has some deficiencies. The differing thermal expansion of the IC and the printed circuit board can cause undue stresses on the IC. The only compliance in the set up is the solder balls. Furthermore the IC can become hotter because it is held off the printed circuit board by the solder balls. The wire bond and tape bond techniques had the back of the IC contacting the printed circuit board (usually glued to it), this offering a heat sink. Table 2.3 shows typical values of the lead inductance for a variety of package types.13
2.6.4
Lead Capacitance
Stray capacitance between adjacent pins of logic packages can couple noise voltages into sensitive inputs. Consider the situation shown in Figure 2.20, where 13 Data
from [8].
49
wire bonding
tape bonding
flip-chip
50
Introduction to Digital Switching 14-pin plastic dual-in-line package (DIP) 68-pin plastic DIP 68-pin surface mount plastic leaded chip carrier (PLCC) Wire bonded to hybrid substrate Solder bump to hybrid substrate
8nH 35nH 7nH 1nH 0.1nH
Table 2.3: Lead inductances of various logic packages. 14-pin plastic dual-in-line package (DIP) 68-pin surface mount plastic leaded chip carrier (PLCC) Wire bonded to hybrid substrate Solder bump to hybrid substrate
4pF 7pF 1pF 0.5pF
Table 2.4: Inter-pin capacitance of common logic packages. mutual capacitance
CM is the mutual capacitance between the pins. One may compute the crosstalk in circuit 2 from the rising edge in circuit 1 by using the expression (2.26) and realising the RB value is 75/2Ω, since the transmission line and termination resistances are in parallel. Therefore we have: Crosstalk =
(37.5Ω)(4pF) RCM = 0.03 = Tr 5nsec
(2.52)
which is 3% cross coupling. This situation becomes significantly worse if the rise time decreases, or if the impedance of the circuit coupled to increases. One way of alleviating the problem with higher impedances is to add capacitance to the lines with the high impedance so that the impedance is lowered at high frequencies. However, whilst this may solve the capacitance cross coupling problem, it may exacerbate ground bounce problems in some circumstances. Table 2.4 shows the typical values for the inter-pin capacitances for common logic packages.14
2.6.5
Measurement Issues
This section will consider a few relevant issues related to the measurement of high speed digital signals. Most of these issues will be related to limitations and caveats associated with the use of cathode ray oscilloscopes (CROs) to observe signals in digital systems. 2.6.5.1
composite rise time
Rise Time and Bandwidth of CROs
The main limitations associated for CROs when used in digital systems are related to bandwidth issues. We have seen in previous discussion that bandwidth and rise time are intimately related (see (2.2 and (2.3)). In the case of an oscilloscope we have a cascade of different components – the probe (which has a frequency response), and perhaps several input amplifiers and finally the display system, all of which have a frequency response. As we just noted this also means that they have a corresponding rise time. It can be shown [1] that the composite rise time of a system composed of a number of components is (assuming gaussian 14 Data
from [8].
2.6 Speed of Digital Systems
51
Tr = 5nsec
Logic package 1
C M = 4pF VCC
Transmission line Z 0 = 75W
2
75W termination
Figure 2.20: Logic package showing the capacitance between pins. CRO Probe
Vertical amplifier G
t1
Input
t12 + t 22
t12 + t 22 + t 32
Composite response of probe and vertical amplifier
Response of the probe to input
Figure 2.21: Composite rise time of an oscilloscope.
pulses)15 : 1
Trcomposite = (T12 + T22 + · · · + TN2 ) 2
(2.53)
The concept behind this equation is shown in Figure 2.21. Consider the case of an RC low pass filter. The bandwidth of this circuit is: F-3dB =
1 2πRC
(2.54)
Substituting this expression into (2.2) we can write: 15 Although this is only exact with gaussian pulses, other pulse shapes give almost the same result.
52
Introduction to Digital Switching
0.35 F-3dB = (0.35)(2πRC) = 2.2RC
T10−90 =
(2.55)
Similarly we can write the following for the LR filter: T10−90 = 2.2
L R
and for the RLC filter (near critically damped): √ T10−90 = 3.4 LC
(2.56)
(2.57)
Example 2.4 This example is taken from [1]. A person buys an oscilloscope rated at 300MHz bandwidth with a probe at 300MHz bandwidth (both are −3dB bandwidths). How does this combination affect signals having a rise time of 2nsec? Assuming the pulses are gaussian in nature then we can compute the rise time of each of the components as: 0.338 = 1.1nsec 300M Hz = 2nsec
Trprobe/scope =
(2.58)
Trsignal
(2.59)
therefore the displayed rise time is: Trdisplayed = (1.12 + 1.12 + 2.02 )1/2 = 2.5nsec
(2.60)
Therefore this oscilloscope will display the 2nsec input signal as a signal with a rise time of 2.5nsec. 2.6.5.2
bandwidth of CRO probe
a
Self-inductance of CRO Probe Ground Clips
Once again we have inductance arising in the context of high speed operation of digital systems. However, in this case we are considering the measurement of the signals. One point to note at the outset is that the bandwidth of a CRO probe is defined when the probe is in a test jig with the probe grounded directly on its case. There is no ground wire employed when probe frequency response is measured. However, in practice digital designers usually use a plastic lead with an alligator clip on it to secure the CRO ground to the circuit ground under test. This ground lead has inductance associated with it, the specific value dependent on the length and configuration of this lead. Clearly the presence of this inductance will affect the frequency response of the probe, and we shall investigate this effect by considering the equivalent circuit shown in Figure 2.22. For a typical CRO probe the input capacitance Cin = 10pF and the input resistance is Rin = 10M Ω. The value of the source resistance of course depends on the source – for a TTL and CMOS the source impedance is approximately 30Ω and for ECL about 10Ω.
2.6 Speed of Digital Systems
53
Source resistance
{
RS
Probe input capacitance and resistance
+ vS
C in
To Rin scope
L
Figure 2.22: Equivalent circuit of CRO input probe. The presence of the inductance in the probe lead has several significant affects on the performance of the CRO. Firstly, the input circuit has a rise time associated with it. Recall (2.57) for the RLC rise time. In order to use this expression we need a representative value for the probe inductance. In order to obtain this assume that we have a earth clip loop of width 2.54cm (1in) and length 7.62cm (3in) with American Wire Gauge (AWG) 24 wire which has a diameter of 0.0508cm. Substituting these values into (2.21) we have:
2 × 7.62 2 × 2.54 L ≈ 4 2.54 ln + 7.62 ln 0.0508 0.0508 = 198nH ≈ 200nH
(2.61)
Therefore the intrinsic rise time of the probe is (assuming critical damping)16 , using (2.57): √ T10−90 = 3.4 LC = 3.4 (200nH)(10pF) = 4.8nsec
(2.62)
This rise time spells trouble. We calculated in (2.58) that the rise time of the CRO itself was 1.1nsec. Therefore the presence of the probe inductance has severely degraded the rise time (and hence bandwidth) of the measurement system. The other interesting aspect of the circuit shown in Figure 2.22 is that it is a resonant circuit. Therefore it will have a quality factor (given the symbol Q). 16 An overdamped circuit rise time is even slower than the critical damped rise time, but an underdamped rise time is faster at the expense of overshoot.
resonant circuit
54
Introduction to Digital Switching For a series circuit the expression for Q is (see Appendix G for a summary of second order series and parallel RLC circuits): 1 L Q= (2.63) RS C
transfer function
It should be noted that Q is the ratio of the total stored energy in the system to the energy lost per radian. A very high Q circuit for example would have a very low value of resistance, meaning that the losses are very low. Such a circuit would tend to resonant for long periods of time. In the particular case of the CRO probe it is clear that the Q will be very dependent on the source impedance of the particular logic gate driving the probe. Let us consider the frequency response of the probe circuit. Using simple circuit analysis one can deduce that the transfer function is:
Rin 1 vin = (2.64) LRin 2 in Rs +L vs Rs + Rin 1 + CinRRs +R s + CRin s in s +Rin If we plot this transfer function over the area of the frequency response of interest we get Figure 2.23. As one can see the peak of the resonance is very dependent on the value of the source resistance. Clearly if the input signal has energy at a frequency of approximately 700Mrad/sec (or 110MHz) then there is going to be some oscillations in the output. Therefore this limits the rise time to avoid oscillations to: 0.5 = 4.54nsec (2.65) Tr > 110MHz Note 2.9 This particular rise time limitation is purely a product of the particular lead inductance-input capacitance combination.
time domain response of the CRO probe
Let us consider the time domain response of the CRO probe equivalent circuit. Whilst one can analytically evaluate the response from the transfer function, a experimental/simulation approach has been opted for.17 A Saber simulation has been set up of the circuit, with the previously mentioned input parameters for the probe (Cin = 10pF, L = 200nH, Rin = 10M Ω) and the source resistance of 30Ω (which is equivalent to a TTL output source resistance). The plot of the input voltage to the CRO appears in Figure 2.24. As can be seen from Figure 2.24 the response seen by the CRO input is very oscillatory due to the presence of the LC circuit. Also note that with the resistance of the TTL source the Q in the circuit is quite high. In fact to get to a critically damped circuit the value of the source resistance has to be closer to 282Ω. With this value of resistance the rise time of the circuit is very near that calculated in (2.62). Practical Issue 2.8 The response of a CRO probe can have a very important effect on the observed waveforms. Remark 2.11 The scope ground undergo very large voltage excursions in Figure 2.24. It is this “ground bounce” that is the source of the scope display problems. 17 The simulation approach will be used repeatedly throughout these notes as it simulates carrying out a real practical experiment.
2.6 Speed of Digital Systems
55
5W 30W
30
Magnitude:dB
20 100W
10 0 -10 -20 -30 -40
0
Phase:deg
-50
-100
-150
10
8
10
9
Frequency (rad/sec)
Figure 2.23: Bode plot of the transfer function of a CRO probe.
10
10
56
Introduction to Digital Switching
Ground bounce (V) : t(s) 10.0
(output-scope_gnd)
(V)
8.0 6.0 4.0 2.0 0.0
(V) : t(s)
4.0
scope_gnd
(V)
2.0 0.0 -2.0 -4.0
(V) : t(s)
6.0
input
(V)
4.0 2.0 rise: 1.8377n 0.0 0.0
20n
40n t(s)
Figure 2.24: Response of the CRO probe equivalent circuit with the input rise time of 1.8nsec.
2.6 Speed of Digital Systems
57
The other interesting thing to look at with this circuit is what happens when we slow down the input edge. We calculated in (2.65) that if the rise time was greater than 4.5nsec that the circuit oscillations would become substantially smaller. If we redo the same simulation as shown in Figure 2.24 but with the rise time of the input equal to a 5.5nsec T10−90 rise time we get the plot of Figure 2.25. Notice that the oscillations are substantially less in this figure, and one could say that the scope is now producing a much more acceptable waveform. Ground bounce (V) : t(s) 8.0
(output-scope_gnd)
(V)
6.0 4.0 2.0 0.0
(V) : t(s)
1.0
scope_gnd
(V)
0.0 -1.0 -2.0
(V) : t(s)
6.0
input
(V)
4.0 2.0 rise: 5.5469n 0.0 0.0
20n
40n t(s)
Figure 2.25: Response of the CRO probe equivalent circuit with the input rise time of 5.5nsec. If we slow the edge even more then the overshoot continues to decrease. If the rise time is about 10nsec then the scope input waveform has virtually no overshoot. Remark 2.12 In summary, we can see from this section that the presence of the CRO probe ground lead and clip has dramatic effects on the effective rise time of the probe, and dramatically effects the observed waveforms – particularly in relation to the overshoot observed on the edges. Table 2.5 lists the Q and rise times for TTL logic and ECL logic. It is assumed that the source resistance for these logics are 30Ω and 10Ω respectively.
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Introduction to Digital Switching
10pF probe
2pF probe
Ground loop inductance (nH)
T10−90
QTTL
QECL
T10−90
QTTL
QECL
200 100 30 10 3 1
2.8 2.0 1.1 0.6 0.3 0.2
4.7 3.3 1.8 1.1 0.6 0.3
14.1 9.9 5.4 3.2 1.7 1.0
1.3 0.89 0.49 0.28 0.15 0.09
10.5 7.4 4.1 2.4 1.3 0.7
32.0 22.0 12.0 7.1 3.9 2.2
Table 2.5: Rise time and Q for 10pF and 2pF capacitance probes for various inductances.
2.6.5.3
electrical noise magnetic coupling
mutual
Mutual-inductance of CRO Probe Ground Clips
Another effect from having a probe lead connected is that it acts as a pick up for electrical noise . This noise cannot be distinguished from noise on the signal being observed. The main mechanism for this noise pick up is magnetic mutual coupling between the loop of the probe lead and another loop in the circuit being probed. The orientation of the two loops is important in determining the magnitude of the observed noise voltage – as noted in Section 2.5.4 if the areas of the loops are such that there is no component of the flux from one loop orthogonal to the area of the other loop then the mutually induced voltage is zero. In a practical situation the loop generating the interfering magnetic field is generally a loop consisting of printed circuit board tracks running to and from an integrated circuit that is driving some load (usually with some capacitance). Figure 2.26 illustrates this particular situation. As can be seen from the diagram some of the magnetic field produced by the signal and ground return current in a nearby integrated circuit is coupled to the loop represented by Loop B. If the orientation of the loops is such that this field is orthogonal to the area of Loop B then there will be a mutual inductance between the two loops and hence, depending on the rate of change of the magnetic flux density, a voltage will be induced in the CRO lead. One can get a rough estimate of the magnitude of the induced voltages in this situation by using (2.37) together with the rate of change of current and (2.11).
Example 2.5 Consider the situation where Loop A in Figure 2.26 is 0.7cm × 0.7cm and Loop B is 2.5cm × 7.5cm. The loops are separated by 5cm. If we
2.6 Speed of Digital Systems
59
Loop B
Magnetic field lines from Loop A to Loop B
Loop A
Return ground current
Signal current
Figure 2.26: General configuration for probe lead pick up.
60
Introduction to Digital Switching apply (2.37) then we can calculate: A1 A2 D3 0.49 × 18.75 =2 53 = 0.147nH
LM = 2
(2.66)
We shall assume that the circuit is feeding a capacitive load of 50pF, and the ∆V = 3.7V and the rise time Tr − 2nsec. Substituting this into the expression for the rate of rise of current with a capacitive load (2.50) we get di/dt = 7 1.52C ∆V Tr2 = 7 × 10 A/sec. We now all the components to calculate the coupled noise. Using (2.11) we can write: vnoise = LM
di = 0.147nH × 7 × 107 A/s = 12mV dt
(2.67)
The 12mV noise is fairly low. However, if we have a bus with a large number of lines conducting a similar amount of the current then the coupled noise could potentially be the (number of lines) × 12mV. Therefore, if one has a 32 line bus then the figure could be 0.384V, which is starting to become a problem when measuring voltages on TTL systems. Practical Issue 2.9 If one wishes to get some idea of the degree of magnetic pickup on a CRO lead then one can connect the alligator clip to the probe tip. Ideally one should see nothing on the CRO screen since the voltage being measured should ideally be zero. However, if the loop formed by the probe lead is orientated in various directions to a potential interference generating circuit then one would see voltages which are a consequence of magnetic coupling pick up. This can give one a subjective feel for the potential mutual coupling interference that would be present in measurements made on the system. Summary 2.1 In order to minimise the effects of the probe lead one should keep it as small as possible. If possible the earth shield on the probe should be shorted to the nearest ground point to the signal being measured using something like a knife blade. 2.6.5.4
important parameters
Loading Effect of CRO Probes
Probing a circuit, like many other measurement techniques, can actually change the circuit parameter being measured. In fact, sometimes in a circuit that is misbehaving, probing the circuit can load the circuit so that it will work correctly when the probe is there. The important parameters in determining the effect of probe loading are: • The knee frequency of the digital signal under test (equation (2.1)) • The source impedance of the circuit under test at the knee frequency • The input impedance of the scope probe at the knee frequency. To get some sort of a feel for the effects of various probes we shall consider the source to input transfer function and the CRO input impedance for the following probe parameters:
2.6 Speed of Digital Systems
61
1. Standard 10× probe with 10pF and 10M Ω input capacitance and resistance respectively. 2. A 10× FET active input probe with 1.7pF and 10M Ω input capacitance and resistance respectively. 3. A passive probe with 0.5pF and 1000Ω input capacitance and input impedance respectively. The equivalent circuit we are using is shown in Figure 2.27. Notice that there is no inductance in the ground of the circuit. This means that we are assuming the the ground shield of the probe is connected directly to the ground plane of the circuit under test (and the ground inductance is therefore negligible).
Source resistance
{
RS
Probe input capacitance and resistance
+ vin
vS
C in
Rin
To scope
-
Figure 2.27: CRO probe equivalent circuit with no lead inductance. The transfer function for Figure 2.27 can be written as: Rin 1 vin = Rs vs Rin + Rs 1 + sCin RRinin+R s
(2.68)
and similarly the input impedance transfer function can be written as: Zin (s) =
Rin 1 + sCin Rin
(2.69)
Plotting these transfer functions for the above mentioned probe parameters and Rs = 50Ω we get Figures 2.28 and 2.29. Remark 2.13 It can be seen from Figure 2.28 that the standard 10M Ω, 10pF probe causes a substantial roll-off in the source to probe input transfer function for rise times smaller then 3nsec.
62
Introduction to Digital Switching
1000W, 0.5pF
10MW, 17 . pF
10MW, 10pF
0
vin dB
-2 -4 -6 -8 -10
Phase:degs
0 -20 -40 -60 10
7
10
314ns
8
10
9
10
31.4ns 3.14ns Frequency (rad/sec) Rise Time
10
0.314ns
Impedance Magnitude (Ohms)
Figure 2.28: Source to probe input transfer function for a CRO probe.
10MW, 10pF
10MW, 17 . pF
1000W, 0.5pF
100,000 10,000 1000 100 7
10 314ns
8
10 31.4ns
9
10 3.14ns
Frequency (rad/sec) Rise time
Figure 2.29: CRO probe input impedance.
10
10 0.314ns
2.6 Speed of Digital Systems
63
Remark 2.14 The active FET probe and the very low capacitance passive probe have good frequency response characteristics, and will handle frequencies into the 500MHz plus range of operation (which corresponds to rise times of approximately 1nsec or less). Remark 2.15 The reason for the poor performance of the standard 10M Ω, 10pFf probe can be seen from Figure 2.29. The input impedance of the probe falls to levels of approximately 100Ω when the input signals have a rise time of approximately 3nsec. Therefore the input impedance is placing a substantial load on the circuit when there is a 50Ω source resistance (which is typical for a digital circuit). Practical Issue 2.10 For the loading to be small the input impedance magnitude needs to be approximately 10 times the source impedance. The most important component of a probes input when it comes to its loading effects at high frequencies is its capacitance.
2.6.6
Better Probing Techniques
We have seen in the previous subsections that the presence of lead inductance and input capacitance has significant effects on the measurement performance of CROs. The logical question to ask is “What can we do to get more accurate measurements in high speed digital systems?” The subsection will attempt to offer several answers to this question. 2.6.6.1
Home Brew 21:1 Probe
We have actually seen this solution in the previous section. Recall from Figures 2.28 and 2.29 that the 1000Ω, 0.5pF passive probe had very good frequency characteristics. The home brew probe that we are to look at has these parameters. Figure 2.30 shows the general configuration of the home made probe. If simply consists of a resistor in series with a 50Ω coaxial cable. The coax is connected to the 50Ω input of a high bandwidth CRO. Remark 2.16 The home brew probe approximates the circuit of Figure 2.31. Notice that in this probe the capacitance is parallel to the 1000Ω resistor, and this combination is in series with the input impedance of the50Ω coaxial cable. In addition there is the source resistance RS which represents the output impedance of the driving gate. The frequency response of this probe, instead of having a pole, has a zero and pole produced by 1000Ω in parallel with CS and in series with the gate output impedance RS . If CS is very small then the zero will be at a very high frequency. The CS capacitor is the parasitic capacitance across the 1000Ω resistor, and is usually ≤ 0.5pf. The fact that the frequency response contains a zero, is itself, a better characteristic. This will mean that the higher frequencies are emphasised, rather than attenuated. The total input impedance into this probe is 1000Ω + 50Ω = 1050Ω. The coax looks resistive, therefore the only capacitance is associated with the shunt
home brew probe
64
Introduction to Digital Switching
To 50W termination at scope 1000W 50W
I
Sense ground loop
Figure 2.30: A home brew 21:1 high speed probe.
Transmission line impedance CS RS
1000W
50W
Figure 2.31: Equivalent circuit for the home brew probe.
2.6 Speed of Digital Systems Type RG-58 BNC twist-on RG-58 BNC double-crimp RG-174 BNC double-crimp RG-8 N-type
65 Lconnector (nH) 1.0 0.5 0.5 0.2
T10−90% (nsec) 0.022 0.011 0.011 0.004
Table 2.6: Inductance and rise time of male coax connectors. capacitor between the ends of the resistor, which is typically about 0.5pF for a 1/4 watt resistor (this can be lowered by using a 1/8Watt resistor, but one must be careful about power dissipation with this). The input voltage is undergoing voltage division, and the ratio is: vscope =
50 vs = 0.048vs 50 + 1000
(2.70)
Therefore with the scope set to 50mV/div the vertical sensitivity is 0.05/0.048 = 1.04V/div. One can use the vertical sensitivity to tweak the vertical scaling to 1V/div if necessary. The advantages of this probe are: • The DC input impedance is 1050Ω with makes the loading on a 25-75Ω source small. • The shunt capacitance is very small meaning that the loading does not change dramatically until very high frequencies. • The rise time of the probe is very fast. Remark 2.17 The price one pays with this probe is that the voltage range is severely limited due to the high attenuation of the probe. This may be a problem with many analogue signals, but the most common digital signals have high enough voltage values that this is not a problem. The rise time of this probe is dominated by three factors: 1. The rise time of the BNC connector 2. The rise time of the coaxial cable 3. The rise time of the sense loop. One would not normally think of a connector having a rise time. For slow signals it effectively hasn’t a rise time, but at the frequencies being dealt with in high speed digital systems the rise time can be significant. The rise time arises from the series inductance introduced in the 50Ω at the point where the shield spreads out away from the centre conductor to connect to the BNC fitting. Table 2.6 shows the series inductance associated with several types of coax connectors and the T10−90% time constant that goes with these inductances. If the coax cable has to be terminated at the scope then one should ensure that a good quality termination is used, else there will be further rise time degradation. The next part of the propagation path of the signal in the probe is the coax cable itself. A coax cable has a frequency response – i.e. there is a frequency at
advantages of this probe
66
Introduction to Digital Switching which the attenuation in the cable is 3.3dB, this corresponding to the frequency knee point. Therefore we can apply (2.1) to find the rise time. However, in the case of coax cables this expression only works for short lengths of cable. Note that at high frequencies the attenuation is proportional to the square root of the frequency, and this fact can be used to interpolate between attenuation points in the cable manufacturers catalogues. Table 2.7 shows the rise time characteristics for some common cables.18 Feet 1 2 3 4 5 10 20 50
TRG-174 (nsec) 0.004 0.014 0.032 0.056 0.088 0.35 1.4 8.8
TRG-58 (nsec) 0.002 0.006 0.014 0.024 0.038 0.15 0.61 3.8
TTG-8 (nsec) 0.0002 0.001 0.002 0.004 0.006 0.025 0.10 0.64
Table 2.7: Rise time of some coaxial cables. The final section of the signal propagation path that we are interested in is the probe sense loop. This loop introduces inductance to the signal path, in a manner similar to that introduced by the probe lead in Section 2.6.5.2. However in this case the 1000Ω resistance dominates the impedance of this path and this decreases the influence of the inductance substantially. This can be seen quantitatively by considering the time constant of the loop, L/R. For a given L then the time constant is reduced for a large R. This effect can be seen in Table 2.8. Loop diameter (mm) 2.54 5.08 12.7 25.4 50.8 127.0 254.0
Lsense (nH) 3.9 11.4 31.0 80.0 200.0 500.0 1220.0
Tr nsec 0.01 0.02 0.06 0.17 0.42 1.1 2.6
Table 2.8: Rise time of home brew probe sense loop. rise time of our home brew probe
We are now in a position to calculate the rise time of our home brew probe. Assume that we have built a probe with 5 feet of RG-174 double-crimped BNC connector and a probe loop of 12mm. Considering Tables 2.6, 2.7 and 2.8 we can develop the expression for the rise time of the probe as: 2 2 + Tloop Trcomposite = (TBNC )2 + Tcable = (0.011)2 + (0.088)2 + (0.06)2 = 0.107nsec 18 These
(2.71)
figures are taken from [1], where the lengths are quoted in imperial measurements.
2.6 Speed of Digital Systems
67
The home brew probe has a very fast rise time. The rise time can be further improved by the use of a “speed-up capacitor”. This involves intentionally putting a capacitor in parallel with the input impedance of the coaxial cable. Therefore we have an equivalent circuit of the form shown in Figure 2.32. If we write the transfer function for this circuit we get:
Rin vin (s) (1 + sCs Rs ) = (2.72) Rs vs (s) Rin + Rs 1 + s(Cs + Cin ) RRin+R in s
“speed-up tor”
capaci-
Therefore there is a zero at an angular frequency of Cs Rs and a pole at (Cs + Cin )Rin Rs /(Rs + Rin ). The Cs capacitance is defined by the capacitance of the resistor Rs (which is the 1kΩ resistor for the home brew probe). The Cin capacitor is a capacitor that the user can introduce. Therefore by choosing the capacitor appropriately one can make the zero and the pole coincide, resulting in a pole zero cancellation. Theoretically the frequency response then becomes flat (which implies that the rise time is zero). Of course in reality the model of Figure 2.32 is not correct at all frequencies, and this cannot be achieved. However, a significant improvement can be obtained with the correct choice of capacitor. The capacitor value is chosen so that: (Cs + Cin )
Rin Rs = Cs Rs Rs + Rin
which after manipulation results in the Cin capacitor being: Rin + Rs −1 Cin = Cs Rin
(2.73)
(2.74)
If pole-zero cancellation is achieved then the frequency response of the speedup circuit would look like Figure 2.33. 2.6.6.2
Low Inductance with Conventional Probes
This section will investigate techniques that lower the inductance of the probe sense loop whilst using a conventional probe. One of the simplest techniques is to use a wire loop as shown in Figure 2.34 to directly connect the earth shield of the probe to the earth. Alternatively one can use the blade of a knife to connect the probe ground sheath to a close ground point (assuming that exposed ground points are available at a variety of convenient locations on the printed circuit board). A third alternative is to use a in-board connector designed for a specific probe as shown in Figure 2.35. Some oscilloscope manufacturers make such connectors. These techniques give probe sense loop inductances in the range of 3nH to 30nH depending on type and the craftmanship employed. 2.6.6.3
pole-zero cancellation
PCB Test Points
We have seen in the previous sections that a conventional probe can significantly influence the operation of a circuit being probed. The home brew probe to a
probe sense loop
68
Introduction to Digital Switching
CS
RS Rin
vS
C in
vin
Figure 2.32: Speed-up circuit as applied to a CRO probe input.
Magnitude dB 1 + sC S RS
Resultant response
LM R R OP NR + R Q
1 + s(C S + C in )
in
in
S
S
log10 f Figure 2.33: Ideal frequency response for a correctly compensate speed-up circuit.
2.6 Speed of Digital Systems
69
Curly wires Scope probe
Ground Signal Figure 2.34: Use of wire connection to lower sense loop inductance.
Scope probe
Sleeve
Insert into the PCB
Printed circuit board (PCB)
Figure 2.35: Low inductance probe connection.
70
test points
Introduction to Digital Switching large extent alleviated this problem, although the loading could still be important in certain applications. Another approach is to build correctly designed test points into a circuit a design time. These test points ensure that when the circuit is probe the loading does not change, and consequently the signals seen when probing will be exactly the same as the signals when the probe is not present. Figure 2.36 shows the general arrangement of an on-board probing set up. Effectively a home brew probe has been built onto the PCB, and the user can use a link to connect an on-PCB probe load to the signal, or connect the actual probe cable. Signal to other parts of the circuit Ground via
50W terminator
Pins shorted when there is no probing
50W line
Connect scope to these pins using Molex KK connector
1K resistor Ground via Molex KK Plug
RG-174 50W coax
To scope
Figure 2.36: Layout of a PCB embedded high frequency test point
2.6.6.4
shield voltage
Shield Currents and Ground Loops
When a CRO is connected to a digital system we connect two leads – the sense lead and a ground lead. The sense lead is usually the centre conductor of a coax cable and the ground lead is connected to the shield of the coaxial cable. Let us consider the ground lead – it is usually connected to the CRO ground and to the digital system ground. The CRO ground in turn is usually connected to the power supply ground via the ground wire in the power cable to the CRO. Figure 2.37 shows this configuration. In this figure the sense wire and shield connection are connected together at the digital system. With this configuration there would be no voltage registered on the scope if no shield current is present. If there is a current, then the voltage that is on the scope is the shield voltage, Vshield . The shield voltage is induced in the shield due to a shield current causing a resistive voltage drop across the resistance of the shield. This current results from the different ground potentials between the digital system and the scope. These different ground potentials can be caused by a variety of influences –
2.6 Speed of Digital Systems
71
Voltage due to shield voltage Sense and ground connected here Voltage drop across the shield Scope
Vshield vin
Digital System
Noise + voltage -
+ -
I - Shield current
Green wire safety ground
Figure 2.37: Noise pick-up due to shield currents. for example large currents flowing elsewhere in other equipment can cause such ground differences. Note 2.10 The shield voltages are a result of the shield resistance, and not the shield inductance. Because of the coaxial nature of the cable the inductance induced voltage in the shield and the sense conductor are the same, and therefore no difference voltage will appear at the CRO amplifier. However, the currents due to ground differences only flow in the shield, and this lack of balance between the shield and the sense conductor will result in a voltage at the CRO amplifier. If you wish to observe the shield voltage in a particular situation do the following: 1. Connect the scope ground and the probe tip together. 2. Move the probe near the circuit without touching anything. Any voltage you see here is due to magnetic pick-up in the sense loop as described in Practical Issue 2.9. 3. Cover the end of the probe with aluminium foil, shorting the tip directly to the probe’s metallic ground sheath. This reduces the magnetic pick-up to virtually zero. 4. Now touch the shorted probe to the logic ground. Any voltage you observe is the shield voltage. There are a number of ways of attempting to tackle the problem of shield noise. Of the solutions proposed below, some will work (to varying degrees) and others do not work at all. It should also be realised that the frequency range of the noise voltage has a bearing on which techniques will be successful in alleviating shield voltage problems. Possible approaches to eliminate shield voltage problems are:
eliminate shield voltage problems
72
Introduction to Digital Switching 1. Lower the shield resistance. This is often difficult to do as the probe is a commercial product. 2. Add a parallel impedance between the scope and the logic ground. This is attempting to cause the current to take this path instead of the shield path. Very difficult to get a good low inductance connection for this method. May work if the shunt is significantly shorter than the probe shield. 3. Turn off all parts of the circuit not under test. This will help determine if the noise is arising from these parts of the circuit or from somewhere else. Not always practical to do. 4. Put a large inductance in series with the shield. This can be achieved by putting 5 to 10 turns of the probe cable around a good high frequency magnetic core. If the noise is in the range of 100kHz to 10MHz this works well. For power supply frequencies the inductance is far too small, and for higher frequencies the magnetic core is no longer very effective. 5. Redesign the board with ground planes. This will reduce any voltages developed across the printed circuit board itself. However, will not prevent the shield voltage, just prevents printed circuit board voltage from being added to it. 6. Disconnect the scope safety ground. This works as far as the lower frequency shield currents are concerned (up to audio frequencies), but in turn results in a major safety issue. Don’t do this. At higher frequencies currents can flow through capacitors that may be connected from the chassis to the AC input wires, or alternatively across parasitic capacitances in the power supply
triaxial shield
7. Use a triaxial shield on the probe which is connected at one end to the scope frame and at the other to the digital system ground. The inner and outer shields are connected together at the scope and digital system. This works on the principle that the skin effect will cause high frequency currents to mostly flow through the outer shield rather than the inner shield. The inner shield has effectively become more inductive (the sense wire is similarly effected), hence the lower current. The lower shield current in the inner shield results in a lower voltage drop and therefore less noise voltage. In a way this is similar to the shunt strap technique, except that we are using skin effect to divert the current flow into the alternate path.
1:1 probe
8. Use a 1:1 probe instead of a 10:1 probe. This is because the 10:1 probe attenuates the signal we are measuring, but it does not attenuate the shield voltage (since it bypasses the attenuation circuitry in the probe).
differential probe
9. Use a differential probe arrangement. This is a very good technique but is a little complicated to set up. Differential probing works because it can ignore common mode voltages. The shield voltage can be made to appear as a common mode voltage if things are arranged correctly. Figure 2.38 shows the general arrangement for differential probing. Notice that the shields are connected together at both ends, but one end of the shield is not connected to anything. Therefore there cannot be a path for the shield
2.6 Speed of Digital Systems
73
current. With this configuration the input amplifiers each measure the noise voltage, but the subtraction of the two signals effectively eliminates this. Most dual or more channel CROs offer the option of being able to subtract the signals of two of the input amplifiers. Any differences between the amplifiers can be eliminated by tying the signal wires to a common point and then tweaking the gains until no signal is seen. Signal being measured
Probe shields tied together
Scope Sense loop 1 obe
Pr
Digital System + Noise voltage -
be
Pro
2
Ground strap
+ + -
+ S -
Green wire safety ground
Probe sense wire to digital ground
Figure 2.38: Differential probing to eliminate shield current effects. The twisting of the probe cables together is to ensure that any magnetic pick-up is the same on both cables, this then being seen as a common mode signal and being eliminated. The ground strap is necessary if the digital system is floating with respect to the true earth ground. It is to make sure that the voltage of the digital system does not float above the common mode range of the CRO input amplifiers. The effectiveness of the differential probe technique depends largely on the performance of the input amplifiers. The common mode rejection ratio of differential amplifiers is frequency dependent, and sometimes does not go to very high frequencies. However, this technique would be very effective at eliminating shield currents up to several hundred kilohertz without any difficulty for most CROs. High frequency rejection would dependent on the CRO amplifier common mode bandwidth.
74
Introduction to Digital Switching
Chapter 3
Point-to-Point Wiring and Transmission Lines This chapter is primarily concerned with transmission lines. However, prior to considering them we shall firstly contrast the transmission line approach against conventional point to point wiring, as carried out in a wire wrap board for example.
3.1
Shortcomings of Point-to-Point Wiring
The following example is taken from reference [1]. Please forgive the imperial units. The case study tells the story of a now famous Silicon Valley company that built a wire wrap prototype of its first high speed processor using TTL technology. This approach was clearly decided upon because of the flexibility offered by the use of wire wrap (it is comparatively easy to make changes), and the extra speed of getting a prototype built compared to building a printed circuit board. The basic statistics of the system are shown in Table 3.1. One of the first steps in deciding to use point-to-point wiring is to figure out whether one needs to consider transmission line effects. Let us apply (2.7) to work out the length of the rising edge of the input signals: lr =
2000psec Rise time (psec) = = 23.5in Delay (psec/in) 85psec/in
Board size Number of gates Number of nets Average net length Average net height above grd Wire size (AWG 30) Signal rise time Knee frequency
16in × 20in 600 2000 4in 0.2in 0.01in diameter 2.0nsec 250MHz (=0.5/2.0nsec)
Table 3.1: Statistics for point-to-point wire wrap board
(3.1)
76
Point-to-Point Wiring and Transmission Lines According to the Section 2.4 states that if line lengths are < lr /6 then we can consider the lines to behave as lumped circuits and distributed line effects can be ignored. In this particular case lr = 3.9in, therefore the designers thought that 4in was close enough to regard the line equivalent circuits to be lumped circuits, and transmission like effects would not be significant. The designers therefore mistakenly thought that the circuit would not ring because there would not be any transmission line effects. The reader of these notes will be aware that a lumped circuit can ring if it contains capacitive and inductive elements. This is not a sufficient condition for ringing though – the Q (known as the Quality Factor) of the circuit is crucial as to whether ringing will occur (see Appendix G for a definition and derivation of expressions for Q). If Q < 0.5 then the circuit is over-damped and no ringing will occur, if Q = 0.5 then the circuit will not ring, but it has the fastest step response without ringing (called critically damped), and if Q > 0.5 then the circuit will have overshoot and ringing. The larger the value of Q the greater the overshoot and the longer it takes for the ringing to die out. It was shown in Appendix G that the maximum overshoot in a second order circuit with Q > 0.5 is:
− Vovershoot =e Vstep
√
π 4Q2 −1
(3.2)
where Vstep the input step (in other words the expected steady state response). One can plug some numbers into this expression and we get for Q = 1 that the overshoot is 16%, for Q = 2 the overshoot is 44%. It should be noted that these are the figures obtained for an ideal step input. We shall see that the degree of ringing experienced by a circuit is a function of the rise time of the input signal and the natural ringing frequency of the circuit. In order to work out the equivalent circuit of the wire wrap wiring we need to know the inductance, capacitance and effective resistance of the wiring and IC drivers. The inductance of the wires can be calculated using (2.22) for a average net length: 4h 4 × 0.2in L = 2x ln = 2 × 2.54 × 4in × ln = 89nH (3.3) d 0.01in The other relevant parameters for this circuit are R = 30Ω (the typical output resistance of a TTL or CMOS gate – see Section 2.6.5.2), and a typical input capacitive load is C = 15pF. Therefore: 1 89nH L 1 = = 2.6 (3.4) Q= Rs C 30 15pF For an instantaneous step the overshoot can be calculated using (3.2) as: − √
Vovershoot = Vstep e
π 4Q2 −1
= 3.7e−0.616 = 2.0V
(3.5)
where Vstep = 3.7, assuming that this is being produced by a lightly loaded TTL output.
3.1 Shortcomings of Point-to-Point Wiring
77
The resonant and natural resonant frequency of this particular circuit are (see Appendix G): 1 1 √ √ = = 137.7MHz 2π 89nH × 15pF 2π LC 2 R 1 1 − = 2π LC 2L 30 1 1 − = = 135MHz 2π 89nH 2 × 89nH
Fresonant = Fnatural resonant
(3.6)
(3.7)
We know that for a resonant system to resonate one needs to be supplying energy at the frequency that the system wishes to resonant at (just think of a typical resonant system such as a swing – one must push it at the frequency at which the swing naturally swings). In this particular circumstance we know that a switching edge contains a wide spectral content up to 250MHz. Therefore there will be significant energy in the range of 135-138MHz to excite the resonance in the system. If one thinks a little further in the frequency domain, we know that: Fresonant = and: Fknee =
1 Tperiod 1 2Tr
(3.8)
(3.9)
If Tr = Tperiod /2 then: Fknee = Fresonant
(3.10)
Therefore if the rise time of the input is greater than half the period of the natural resonant frequency then the oscillations will be small. If, on the other hand, the rise time of the input is shorter than the natural resonant period then the oscillations in the circuit will be significant. In conclusion, the wire wrap board built by our Silicon Valley company had significant ringing problems.
3.1.1
EMI Radiation
EMI is an abbreviation for Electromagnetic Interference. It refers to the electromagnetic radiation that emanates from electrical circuitry. It is well known that circuits that have large loops with rapidly changing currents in them will radiate significant amounts of broadband radiation. Wire wrap inherently leads to relatively large loops. This is due to the distance that separates the wires from the ground plane (assuming there is one). It would be even worse if there is no ground plane, and the board is relying on other wire wrap nets to supply the return paths for currents. The net result in either case is that there is a significant loop area that the currents flow around. Transmission lines inherently provide very small loops that the currents flow around. The return currents will automatically tend to flow in the ground plane under the conductor. The conductor itself has a very small separation
Electromagnetic Interference
78
Point-to-Point Wiring and Transmission Lines from the ground plane, and this also limits the area and provides a degree of field cancellation. For example, if one has a track on a ground planed printed circuit board, with the track separated from the plane 0.005in, it will radiate 32dB less field energy per wire compared to the situation in a typical wire wrap board, where the wire is 0.2in above the ground plane. If one is building a wire wrap board it is very important to get the wires as close to the ground plane as possible. Unfortunately this is not always possible.
3.1.2
Crosstalk
We have previously discussed crosstalk in general (both capacitive and inductive – see Sections 2.5.3 and 2.5.4). The bottom line in relation to inductive mutual coupling was, that if one has conductors close together with large loop areas, then there will be significant coupling between them. The other main conclusion is that inductive coupling is usually more significant than capacitive coupling. In this particular case, as discussed in the previous section, the wiring loops are relatively large. Therefore one would expect significant mutual coupling. Let us now generate some numbers to verify this assertion. Assume that we have two average length wires on the board running parallel to each other. If we apply (2.38) we can write for the mutual inductance between the wires as:
1 Lm = L 2 1 + hs
1 (3.11) = 89nH 2 = 71nH 1 + 0.2 0.1 This value of mutual inductance is very high – it is not much different from the self inductance of the wire, which means that a lot of the flux density lines of one wire loop are linking to the other wire loop. To work out the crosstalk in this situation we need to use the expression (2.50) for di/dt when there is a capacitive load: 1.52∆V 1.52 × 5.7 di = 2 C= 15 × 10−12 = 1 × 107 A/s dt T10−90 (3.6 × 10−9 )2
(3.12)
Note that we are using 3.7V as a step TTL input, and then adding the maximum 2.0V overshoot. In addition the rise time of the signal is the rise time of this overshooting signal, which we are estimating to be the time to the initial maximum overshoot, which from (G.35) is 3.6nsec. The crosstalk is: vm Vsteady state
=
di Lm dt
Vsteady state
=
71 × 10−9 × 1 × 107 = 0.19 = 19% 3.7
(3.13)
Note that we have used the normal steady state value of the voltage in the denominator in this expression rather than the overshoot value. A crosstalk value of 19% is very large. In absolute terms this is 0.7V, which is almost the switching level of TTL. With this amount of crosstalk this circuit will not work. It should also be noted that the above calculations are for a single wire. If one has a bus system on the board then the crosstalk will be
3.2 Uniform Transmission Lines additive from each wire. This fact also leads one to realise that bundling wires together in bus structures so that they look nice on a wire wrap board is not a good idea. It is better to wire the wires directly from point to point so that there is a randomness to their relative orientation. With all the problems cited in this section in relation to the performance of this board it is not a surprise that the company in question never got it to work, and had to abandon this approach and build a prototype printed circuit board. Remark 3.1 The wire wrap circuit example above has been presented to show the pitfalls of point to point wiring. Given the fast rise-time of modern digital devices, point to point wire wrap wiring should no be used.
3.2
Uniform Transmission Lines
Appendix H derives in detail the transmission line equations for a lossless transmission line. In this section we shall look at the practical implications of transmission line phenomena on the performance of digital systems. Physically the transmission lines that we encounter in digital systems take one of the forms in Figure 3.1. The twisted pair configuration is called a balanced configuration, since the signal flows out on one wire and returns on the other. The other configurations are not balanced, since the return path has a different physical configuration than the the other signal path. In the case of ground plane based systems the ground plane is usually shared with a lot of other signal returns. In one considers the ideal transmission line as discussed in Appendix H then we can say that they have three basic properties: • They in infinite in extent in the positive and negative directions. • Signals which propagate along the line are undistorted – this implies that the line has an infinite frequency response. • Signals do not attenuate as they propagate – i.e. ideal lines are lossless. Remark 3.2 The properties of the ideal transmission line are fascinating. As shown in Appendix H transmission lines can be modelled as LC circuit elements, which normally form frequency selective networks. However, when they are connected together in a distributed fashion (as in a transmission line) then the delicate balance between the inductance and capacitance of the line leads to the effective impedance of the line appearing to be resistive. Because a resistor is not a frequency selective component then the line has an infinite frequency response.
3.2.1
Measurement of Distributed Parameters
One issue that was not considered in Appendix H was the measurement of the distributed parameters of an actual transmission line. A simple and reasonably accurate approach is shown in Figure 3.2. This diagram shows a 20cm length of RG-58/U coaxial cable. The capacitance of the cable is measured using a good capacitance metre. This value turns out to be 24nF. Note that the cable is open circuit in order to carry out this measurement. Similarly, in order to measure
79
80
Point-to-Point Wiring and Transmission Lines
Coaxial cable
Conductor
Microstrip
Dielectric
Outer jacket Outer shield
Ground plane
Inner dielectric Inner conductor
Twisted pair
Jacket (dielectric)
Ground plane
Stripline
Conductors
Ground plane
Dielectric
Conductor
Figure 3.1: Physical configuration of different types of common transmission lines.
3.2 Uniform Transmission Lines
81
the inductance of the cable we short circuit one end of the cable, and again using a good quality measurement bridge we are able to measure the inductance of the cable length. In this particular case this turns out to be 50.4nH. We can also measure the resistance of the cable with this configuration if we have access to a high sensitivity resistance bridge. To get the per unit length values simply divide by the length of the cable. L = 20cm Leave end of line open Measure capacitance here
C = 24pF C/cm = 1.2pF
L = 20cm Short out end of line
Measure inductance and/or series resistance here
L = 50.4nH L/cm = 2.52nH
Figure 3.2: Experimental set-up to measure transmission line distributed parameters.
3.2.2
Alternative Way of Deriving Characteristic Impedance
The characteristic impedance of a lossless transmission line was formally derived in Appendix H. However, in this section a more heuristic approach is used to derive the characteristic impedance. The following discussion is with reference to the situation portrayed in Figure 3.3. Figure 3.3 shows a pulse that is being transmitted down a transmission line. It is shown in Appendix H that the velocity of a pulse or waveform in a transmission line is: 1 (3.14) v=√ LC where L the inductance per unit length, and C the capacitance per unit length. At some position in the line denoted as X we have a delayed version of the input, and similarly at position Y√ . Therefore the time to transverse the distance Y − X is (Y − X)/v = (Y − X) LC. As the pulse moves from position X to position Y the capacitance of the transmission line has to be charged. The total capacitance of the line for this distance can be calculated as follows: CXY = (C)(Y − X)
(3.15)
where C the capacitance per centimetre, and therefore the total charge required to charge this capacitance is: q = CXY V = V C(Y − X)
(3.16)
82
Point-to-Point Wiring and Transmission Lines
Input voltage step
+ -
Delayed version of input at position X X Delayed version of input at position Y
(X-Y) Y
t0
t1
Time delay = t1 - t 0 = (Y - X ) LC
Figure 3.3: Voltage pulse in an ideal transmission line. We can work out the current required to charge this capacitance if we know the time that it takes for the waveform to traverse this region. As shown in Figure 3.3 this time is: √ (3.17) td = (Y − X) LC therefore: i=
q V C(Y − X) √ = td (Y − X) LC
To find the characteristic impedance we form the ratio of V /i giving: L R0 = C
(3.18)
(3.19)
Typical impedances range from 10Ω between the inner and outer shields of triaxial cable, to 300Ω for balanced cable used for television antennae. Figure 3.4 shows typical dimensions for 50Ω and 75Ω characteristic impedances on printed circuit boards. Refer to Section I.3.12 for the general equations to work out the characteristic impedance of microstrip and strip lines.
3.2.3
Physical Explanation of Reflections
As a wave travels down a transmission line Kirchoff’s Laws must apply at every single point. When the wave reaches the end of the line, these laws must still hold. If the line is terminated in its characteristic impedance then, as shown above, Krichoff’s Laws will hold, since the characteristic impedance is such that Kirchoffs Laws hold all the way along the line. Therefore, as far as the travelling wave is concerned the end of the line looks like an infinite length transmission line.
3.2 Uniform Transmission Lines
83
75W
50W
Microstrip
Microstrip
H
2H H
H
Stripline
Stripline
H
H 8
H
H 3
All substrates: FR-4; Er=4.5 R0 accuracy = 30%
Figure 3.4: Typical dimensions of PCB traces to produce 50Ω and 75Ω characteristic impedances.
However, if the line is terminated with a short circuit then we know that the voltage at this point must be zero. We also know that when the reflections on the line settle out (assuming that the line has some losses in it, as all real transmission lines do) then the voltage at any point on the line must be zero. Consequently, since the short circuit forces the zero terminating voltage, then a reflected wave is generated at the termination that has an equal an opposite polarity to the incident wave. The incident and reflected wave are added (since the system is linear and superposition holds) to give the resultant wave. The reflected wave flows back toward the source. Eventually the wave reflected from the end termination will reach the source. If the source is voltage source, then the voltage here must be fixed to the source voltage. Consequently then will be another inversion of the incident wave (which in this case is the reflected wave from the termination) to give a resultant voltage equal to the source voltage. Therefore, as with the end termination, the reflection is produced such that the end boundary condition is satisfied. The initial current flow into the transmission line is equal to Vs /R0 . The zero impedance at the end of the line means that the current is unconstrained – i.e. one can have any current flowing into this termination and still have no voltage appearing across the termination. Therefore it is the voltage constraint that determines what the reflected waveform is, and the current simply follows suit. The negative reflection results in doubling of the resultant current at the end termination, this eventually reaching the source where its value again increases, and a further reflection occurs. Consequently the current continues to build up in the line, and for an ideal line will go towards infinity as t → ∞. One can mount similar arguments if the end of the transmission line is terminated with an open circuit. In this case when the incident wave reaches the
84
Point-to-Point Wiring and Transmission Lines open circuit the current must be zero, where as the voltage is unconstrained. In order for the current to be zero there must be a current flow in the opposite direction to the incident current. This means that there must be an equal voltage pulse, but in the opposite direction, flowing down the line. Therefore the cumulative voltage at the end termination at this incident is twice the incident voltage pulse. The reflected voltage will produce an equal, but opposite direction current, flowing down the transmission line, and therefore the resultant current is zero. What happens after this is determined by the nature of the load. If the load appears as an AC short circuit, then the open circuit reflection will be reflected as per the short circuit reflection above so that the source voltage constraint is satisfied.
3.3
Modelling of Transmission Lines
The most accurate method of modelling a transmission line is to use a specialised finite element package designed to model electro-magnetic systems. One simply inputs the physical configuration of the line, generates a finite element grid, and then run the FE software to develop the magnetic and electric field patterns. The post-processing software allows one to calculate the inductance, capacitance, conductance and resistance per unit length of the line. This approach, however, is very complex and numerically intensive. A more practical method, that delivers good results if the correct parameters are used, is to model the transmission line as a set of lumped LC sections (or LCRG if one wants a more accurate model). Using this modelling approach one can use a circuit simulation package (like Spice or Saber ) as the simulator. For digital transmission lines the LC model is usually accurate enough. The question then arises as to how many sections one requires to accurately model the line. A rule of thumb is to use that there should be 10 or more segments over the length of the rising or falling edge on the line. If we assume that the line as a length of x, v is the propagation velocity, and Tr is the rise or fall time of the edge, then the above can be stated as [9]: x num of segments ≥ 10 (3.20) Tr v where Tr v is the length of the rising edge. The term Txr v is the number of rise edge lengths along the transmission line, and therefore we are ensuring that there are more than 10 segments for each of these. If the C and L parameters for the transmission line are given as the C or L per metre, then the segment values of these are: (x)(C/metre) num of segments (x)(L/metre) = num of segments
Csegment =
(3.21)
Lsegment
(3.22)
and so on for the R and G values if applicable. Figure 3.5 shows the Saber model of a terminated transmission line using coupled LC sections. The accuracy of this line is dependent on the rise time of the signal on the line.
3.4 Some Practical Effects in Transmission Lines p1 4.5nH 3.0V step
p2 4.5nH
1.1pF
p3 4.5nH
1.1pF
p4 4.5nH
1.1pF
p5 4.5nH
1.1pF
p6 4.5nH
1.1pF
p7 4.5nH
1.1pF
p8 4.5nH
1.1pF
85 p9
4.5nH
1.1pF
p10 4.5nH
1.1pF
p11 4.5nH
1.1pF
1.1pF
Figure 3.5: Model of the transmission line using coupled LC sections.
3.4
Some Practical Effects in Transmission Lines
In all the discussion thus-far we have considered the transmission line to be lossless. However, as in all room temperature conductors, those in transmission lines have resistance. Therefore the transmission is not lossless. Generally the implications of this loss on the transmission of pulses down the line is that they suffer attenuation and distortion. The latter point means that the line no longer has an infinite frequency response.
3.4.1
Skin Effect
As mentioned in the section above a normal transmission line has a distributed resistance. However, the real situation is a little more complicated, especially at high frequencies, due to the skin effect. The skin effect is due to an alteration in the distribution of current in conductors as frequency increases. At DC the current through a conductor is uniform across the cross-section of the conductor. However, at higher frequencies the current begins to crowd on the outside edge of the conductor, only penetrating a small distance toward the centre of the conductor. There is virtually no current flowing in the centre of the conductor. There are two ways of heuristically explaining this phenomena. One involves carrying out the following thought experiment. Imagine the conductor sliced length-wise into concentric cylinders. Because of symmetry arguments no current would flow between the cylinders, and all the current is considered to be flowing longitudinally down the wire. If one considers the inner most cylinder – its inductance will be larger than an outer cylinder due to its small diameter. Therefore the current will flow where the back emf in the wire is less, which is towards the outside of the wire. Another explanation (which I like because of its more fundamental explanation) is to consider the application of Lenz’s law inside the wire. Consider Figure 3.6. There is an increasing current flowing into the page, and the flux density lines produced by this current are shown. Because the flux density is increasing, and these lines are inside a conductive material, there will be Eddy currents induced in the conductor in such a way as to generate a field which opposes the one produced by the primary current. Consider the shaded area in the figure. The currents produced around this area to oppose the increasing flux that is orthogonal to it are shown as i1 , i2 , i3 , i4 on the loop. Note the directions of the currents. The current i2 along the outside of the conductor is in the same direction as the current primary initiating current, therefore it tends to reinforce. However, current i4 is in the opposite direction to the initiating current in the centre of the conductor. Therefore the current will be less here.
86
Point-to-Point Wiring and Transmission Lines Consequently there will be more current at the outer surface of the conductor compared to the centre. As the frequency of the current increases then the rate of change of the flux density increases and therefore the voltage induced internally in the wire increases, and consequently the crowding of the current on the outer surface of the wire increases. This effect can be considered to be happening on an infinitesimally small elements, therefore the currents i1 and i3 will cancel and there is no net current in the radial direction.
Area A
i3
i2
i4
Wire
i1
Flux density lines i
Figure 3.6: Lenz’s Law explanation of the skin effect.
skin depth
At high frequencies the average depth of the current penetration, called the skin depth, is quite shallow. The current density falls exponentially as we approach the centre of the conductor. The expression for the skin depth is: Skin depth =
2ρ ωµ
12 (3.23)
where: ρ the material resistivity ω the applied frequency in rad/sec µ the magnetic permeability of the conductor As one might well imagine the main effect of the skin effect it that the resistance of a wire increases with increased frequency. It should also be noted that the skin effect is the same for a round conductors as it is for square conductors. Skin effect begins to become significant for a round conductor when the skin depth becomes less than the radius of the conductor. This is the point where the AC resistance of the conductor will begin to rise. The rise is proportional
3.4 Some Practical Effects in Transmission Lines
87
to the square root of the applied frequency. For a flat rectangular conductor the critical depth is half the conductor thickness. An approximate expression for the resistance of a conductor at from DC to an arbitrary frequency is: 1
R(f ) = {(RDC )2 + [RAC (f )]2 } 2
(3.24)
where: RDC the DC resistance (5.4864 × 10−7 )(f ρr ) 2 = πd 1
RAC
(3.25)
where: d wire diameter in cm RAC the AC resistance in Ω/cm ρr relative resistivity compared to copper (Copper = 1.00) f frequency in Hz
(3.26)
One can get a feel for the magnitude of the resistance changes with skin effect from Figure 3.7.
Resistance (Ohm/in)
101
10 -1
10 -3
10 -5
10 -7 101
10 3
10 5
10 7
10 9
Frequency (Hz) Figure 3.7: Resistance of AWG 24 round wire (diameter = 0.02in) with frequency (reproduced from [1] page 158). Since skin effect is a surface phenomena then increasing the surface area should decrease the effect. This is what happens. Litz wire consists of multiple strands of very fine wire, each strand insulated from the others and woven in a specific weave pattern. This weave ensures that each individual wire is subject to
88
Point-to-Point Wiring and Transmission Lines similar magnetic forces which ensures equal currents flow in each of the strands. Litz wire is very useful up to frequencies of 1MHz. Beyond this it is very difficult to keep the currents in the strands balanced.
3.4.2
Proximity Effect
Another phenomena that occurs when high frequency currents flow through wires is the proximity effect. This effect causes the current to tend to crowd in the sections of each wire that are closest to the other wire – see Figure 3.8 for an illustration of this.
Current tends to crowd here
+
-
Figure 3.8: Example of the proximity effect in round conductors. When currents flow in the same direction in two parallel wires the wires experience a force that tends to pull the wires together. Similarly if the currents are in the opposite directions the wires tend to repel each other. These forces occur for all currents from DC upwards. This is not the proximity effect.1 The proximity effect only occurs when high frequency currents are present. The reasons for the effect are similar to those for the skin effect. The currents will tend to distribute themselves in the wire in order to lower the inductance of the loop of current. Clearly this will occur if the currents flow around the inside edge of the loop as opposed to the outside edge. Under this condition the currents experience less back-emf, this effect forcing the current distribution. The proximity effect at equilibrium is determined by the ratio of wire separation between centres, to the wire diameter. The effect is most pronounced when wires are nearly touching. The effect will increase the AC resistance above that from just the skin effect alone. Proximity effect, unlike the skin effect, tends to plateau at rather low frequencies. 1 Proximity
effect does not exert any physical forces on the wires.
3.5 Termination of Transmission Lines
3.4.3
89
Dielectric Losses
If one places fibre glass printed circuit board material into a microwave oven and turn in on the material will heat up. The same applies to many insulation materials. This heat is generated due to losses in the material. The dielectric materials used in transmission lines similarly are affected by the fields they are subjected to. The heat in this situation translates to signal attenuation (since it is the signal that is supplying the energy to cause the heating). For most printed circuit board materials the dielectric losses are negligible for digital frequencies below 1GHz. For higher frequencies the dielectric losses can begin to become appreciable, and other materials based on ceramic substrates may have to be used. For long wires the dielectric properties can be more critical. For example, typical PVC insulation used in telephone wire has measurable dielectric loss at 10MHz, and it continues to increase with increased frequency. Dielectric losses are usually lumped with the skin effect losses in an overall dB loss model of a line.2
3.5
Termination of Transmission Lines
Appendix H develops some of the theory behind transmission lines. This section will not repeat this theory but will consider some of the practical implications of it. One interesting way of looking at transmission lines is in the frequency domain rather than the time domain. An advantage of this approach is that it does not make a distinction between short lines and long lines – in other words one does not have to worry about the distinction between lumped circuits and distributed circuits as much. Let use consider the transfer function derived in Appendix H, (H.166), which is for a lossless transmission line. We shall repeat it here for convenience: − → Z0 ZL VL → = (Z Z + Z Z ) cos(βl) + j(Z 2 + Z Z ) sin(βl) − s 0 0 L s L Vs 0
(3.27)
where: l length of the transmission line √ ω ω β = ω LC = 1 = rad/m √ v LC
ωl = ωt ⇒ βl = v Since the line is lossless then we can simplify the expression for the characteristic impedance a little as there is no imaginary component to it. Therefore Z0 = R0 . Let us consider the situation where we are exciting the line with sinusoidal voltages under various termination conditions. Firstly let us consider the load 2 This is one reason that ADSL connections hace a restriction with respect to the distance that the subscriber is from the exchange. The transmission lines are conventional twisted pair phone lines.
90
Point-to-Point Wiring and Transmission Lines as a short circuit. Clearly if ZL = 0 in (3.27) then we get: − → V L =0 − → Vs
(3.28)
which is an obvious result. It is comforting that the transfer function expression gives the correct result. Now let use consider the load as an open circuit – i.e. ZL = ∞ and the source impedance Zs = 0. If these values are substituted into (3.27) then we get: → − 1 VL Z0 (3.29) → = Z cos(βl) = cos(βl) − 0 Vs → − → − If l = 0 then clearly V L = V s , which makes intuitive sense since one has a zero → − − → length line. Also note that if βl = π/2 then V L / V s = ∞.3 This corresponds to a quarter wavelength transmission line, since λ = 2π/β (see (H.130)). If → − − → βl = nπ where n = 1, 2, 3 · · · then we get V L / V s = ±1. This corresponds to a line that is multiples of half a wavelength on the transmission line. Let us consider an open circuit load and a source impedance the same as the characteristic impedance – i.e. will are considering the case where we have ZL = ∞ and Zs = R0 . If we let ZL → ∞ in (3.27) then we get: → − VL R0 (3.30) → = R cos(βl) + jR sin(βl) − 0 0 Vs therefore:
− → R0 V L =1 − = → Vs R0 cos2 (βl) + sin2 (βl)
(3.31)
Therefore the voltage at the load end of the line is the same as the voltage at the source. This is known as source or back matching, and intimately relies on the reflection being produced at the open circuited load end of the line. However, it should be realised that the waveform at the source end of the line will be distorted. Initially when the pulse is applied the voltage at the source end of the line will be: → − → − → → − Zin V s R0 V s 1− = = Vs (3.32) V sl = Zin + Zs R0 + R0 2 This initially launched voltage in the line will reflect totally at the load end → − of the line, and hence double in value which obviously brings it back to V s . However, the reflected wave will then propagate back to the source where it will be absorbed by the source impedance. The voltage at this point will then be → − V s. Now consider the situation where one has a source termination of Rs and a load termination of R0 . Substituting these values into (3.27) one can get: − → R0 V L (3.33) = − → V s Rs + R0 → − → − implies that if V s = , where is a very small value, then V L = ∞. Therefore the line is resonating. 3 This
3.5 Termination of Transmission Lines
91
i.e. the line is acting as a voltage divider. Finally, consider the situation where the load is forward or load matched – i.e. ZL = R0 and Zs = 0. Substituting these values into (3.27) one gets: − → V L − =1 → Vs
(3.34)
Therefore, as with the back termination one does not get any reflection, and therefore the transfer function is 1. If one considers the phasor form of the transfer function: − → VL 1 → = cos(βl) + j sin(βl) − Vs
(3.35)
one can see that there is a phase shift of − tan(βl) in the signal. This fact should be clear from a consideration of the physics of a signal propagating at a velocity down a line.
3.5.1
General Effects of Source and Load Impedance
It was shown in Appendix H that one can construct a relative transfer function (i.e. with unity initial amplitude) for an infinite or semi-infinite a transmission line of the general form: √ H(ω) = e−x (R+jωL)(G+jωC)
(3.36)
which can be written more succinctly as: H(ω) = e−x(α+jβ) = e−xγ
(3.37)
using the γ definition in (H.112). The H(ω) function describes the amplitude and phase of a sinusoidal waveform that is propagating down a transmission line, and an explicit form of the function can be seen in (H.121) (note that this equation also contains the initial amplitude whereas (3.37) doesn’t). The distance down the line is indicated by x. Remark 3.3 The correspondence between the H(ω) representation and the actual signals that propagate down the line can be more readily seen by the use of phasors. From Appendix H one can write: → − − → V 1 (x) = V 1 H(ω)
(3.38)
− → where V1 (x) denotes the voltage phasor at any point x down the transmission → − line, and V 1 denotes the input phasor voltage (at x = 0), which can be written as: → − (3.39) V 1 = V1 ejθV
92
Point-to-Point Wiring and Transmission Lines We can therefore expand the frequency domain expression into its time domain form as follows: − → V1 (x) = V1 ejθV e−xγ = V1 ejθV e−xα e−jxβ Using the definition of the phasor to time domain conversion: − → ⇒ v(t) = R{V1 (x)ejωt } = R{V1 e−xα ej(ωt−xβ) } = V1 e−xα cos(ωt − βx)
(3.40)
One can see from (3.40) that the voltage along the transmission line is a function of α and β, and hence γ. Equation (3.40) specifically shows that the amplitude of the voltage decreases as one travels down the line (i.e. decreases with x), and at any specific point x along the line the voltage varies with respect to time as a sinusoid. The above analysis shows that H(ω) captures all the information required to ascertain the variation of the voltage with respect to time and distance along the transmission line. The acceptance function for a transmission line is the transfer function relating the signal amplitude and phase at the beginning of the line to that of the source itself. Therefore the acceptance function is defined as: A(ω) =
Z0 (ω) ZS (ω) + Z0 (ω)
(3.41)
At the far end of the line a fraction of the attenuated signal that has propagated down the line emerges, and a fraction of the signal is reflected (note that both these depend on the load termination). The fraction of the signal that emerges (i.e. appears at the load) is called the transmission function and is defined as: 2ZL (ω) (3.42) T (ω) = ZL (ω) + Z0 (ω) which is derived from 1 + ρ, where ρ is the reflection coefficient. Remark 3.4 Note that the transmission function states the proportion of the signal that emerges across the load termination. For example, if ZL (ω) = 0 (i.e. the load termination is a short circuit) then clearly T (ω) = 0, which means that there is no signal across the load termination. If on the other hand the load is an open circuit then there is voltage doubling at the load and therefore the transmission function is 2. The reflection coefficient is the ratio of the reflected signal to the incident signal and was formally derived in Appendix H and will only be written here without proof for the load termination: ρL =
ZL (ω) − Z0 (ω) ZL (ω) + Z0 (ω)
(3.43)
3.5 Termination of Transmission Lines
93
Similarly the reflection at the source termination is: ρS =
ZS (ω) − Z0 (ω) ZS (ω) + Z0 (ω)
(3.44)
Let us now consider the situation when a signal is launched down a transmission line. Assume a per-unit input signal of 1, therefore the signal at the beginning of the line is A(ω). At the load end of the line (which is length l down the line) the signal would be A(ω)Hl (ω). Consequently the signal across the load is A(ω)Hl (ω)T (ω). We shall denote this initial emerging signal as: S0 (ω) = A(ω)Hl (ω)T (ω)
(3.45)
The incident signal on the load will in general reflect. This reflected signal is subjected to the attenuation function of the transmission line and a further reflection at the source end of the line. This second reflection then continues back down the transmission line and is again reflected at the load termination, and the process continues. As the reflections continue the reflected signals gradually decrease in amplitude (the rate depending on the size of the α parameter), eventually settling out. If we consider the second reflection, we can write the expression for the incident signal on the source termination as: [A(ω)Hl (ω)ρL (ω)]Hl (ω)
(3.46)
and therefore the reflected signal at the source is: A(ω)Hl (ω)[ρL (ω)Hl (ω)ρS (ω)]
(3.47)
This reflected signal then reaches the load termination again. It is again attenuated by travelling down the line. Considering only the signal emerging from the reflected signal we can write: S1 (ω) = A(ω)Hl (ω)[ρL (ω)Hl2 (ω)ρS (ω)]T (ω)
(3.48)
Figure 3.9 shows the series of reflections from the load and source terminations as the signal propagates up and down the transmission line. As discussed above this situation continues infinitely. For the nth emerging signal we can find that the expression is:4 Sn (ω) = A(ω)Hl (ω)[ρL (ω)Hl2 (ω)ρS (ω)]n T (ω)
(3.49)
The total emerging signal is the sum of the all the Sn values for n = 0, 1, 2, · · · , ∞. Therefore the final steady state value for the emerging signal is: (3.50) S∞ (ω) = Σ∞ n=0 Sn (ω) There is a closed form solution for this infinite sum: S∞ (ω) =
A(ω)Hl (ω)T (ω) 1 − ρL (ω)Hl2 (ω)ρS (ω)
(3.51)
4 Note that this expression is only for the component of the incident signal that emerges from the line. The total signal at this point is the addition of all the signals present – i.e. the initial signal plus all the subsequent incident signals resulting from the reflections.
94
Point-to-Point Wiring and Transmission Lines
H l (w )
A(w )
T(w )
ZS
Z0
+
H l (w )
r R (w )
Some signal reflecting off the load termination
H l (w )
Signal reflecting off the source termination r L (w )
Reflected signal suffers further attenuation down the tx line r R (w )
H l (w )
A(w )H l (w )T (w ) ZL
r L (w )
T(w )
A(w )H l (w )[ r L (w )H l2(w )r S (w )]T (w )
H l (w )
r L (w )
T(w )
A(w )H l (w )[ r L (w )H l2(w )r S (w )]2T (w )
Figure 3.9: Diagrammatic representation of the various reflected signals in a transmission line showing the acceptance, propagation and transmission transfer functions.
3.5 Termination of Transmission Lines
95
Equation (3.51) is the total frequency response function for the transmission line. The frequency response expressions calculated in Appendix H are for the initial incident waveform on the termination. Using (3.51)) we can now revisit the effects of different terminations in a more general setting. Using the expression T (ω) = 1 + ρL (ω) we can write (3.51) as: Hl (ω)A(ω)(ρL (ω) + 1) (3.52) S∞ (ω) = 1 − ρL (ω)ρS (ω)Hl2 (ω) If we assume that Hl (ω) is fixed (i.e. the cable parameters are fixed) then we can alter the ρL (ω) and ρS (ω) functions via the load and source termination values. Note that changing ρS (ω) also modifies A(ω). Using (3.52) it is possible to ascertain very quickly the effects of the two main termination types – load or end termination, and source termination. 3.5.1.1
Load termination
In this method of termination involves setting the terminating impedance to the characteristic impedance of the line. Therefore from (3.43) one can see that ρL (ω) = 0 and T (ω) = 1. Therefore (3.52) can be written as: Sload term = Hl (ω)A(ω)
(3.53)
As can be seen from this expression the input signal simply propagates down the line and none of the signal is reflected back along the line. The magnitude and phase of the signal is totally represented by the propagation characteristic of the line and the acceptance function at the input source to the line. For sensible terminations there should not be any ringing in the line since there are no delayed versions of the input signal propagating up and down the transmission line. Remark 3.5 Note that load terminations have the undesirable characteristic that if the driving voltage is high then power is being dissipated in the terminating resistor. This power can be quite high, since the terminating resistor for most PCB traces would be to the order of 80-200Ω. Remark 3.6 The power dissipation problem mentioned in Remark 3.5 can be overcome by using a series combination of a resistor and capacitor in the load termination. If the capacitor is chosen appropraitely, then it will be a short circuit at the frequencies that approach those in the switching edge. Therefore, these frequencies will see the characteristic impedance terminating resistor as the load, but the termination will be an open circuit at low frequencies. Consequently, there will be no power dissipation under constant output voltage conditions. Figure 3.10 shows a conventional load termination and two different types of capacitor based load terminations. 3.5.1.2
Source Termination
This technique sets the source impedance equal to the characteristic impedance of the transmission line. Therefore the source end reflection coefficient is set to zero – i.e. ρS (ω) = 0. This will prevent the second and subsequent reflections from occurring, but it will not prevent the initial reflection from the load.
96
Point-to-Point Wiring and Transmission Lines
vS
Z0
vS
Z0
Transmission line
(a)
C
(b)
VCC
C 2 2Z 0
(c)
vS
2Z 0
C 2
Figure 3.10: Load terminations: (a) Conventional termination, (b) Capacitive termination 1, (c) Capacitive termination 2.
3.5 Termination of Transmission Lines
97
The consequence of setting ρS (ω) = 0 is that A(ω) = 1/2, therefore the initial signal launched in the line is 1/2 the applied voltage. This can be compensated for at the load end by making the transmission function, T (ω) = 2 – this is achieved by making ZL (ω) = ∞. In other words one gets total reflection at the load, as well as a doubling of the incident wave. This means that the waveform at the load will be the applied waveform behind the source termination. This reflected waveform then travels back along the transmission line where it is totally absorbed at the source. Remark 3.7 The fact that the signal at the source end is initially 1/2VS can be a problem if one wishes to use the signal at this end or at points midway along the line. The signal is only usable at the load end of the transmission line using this approach. Note that this contrasts with load terminations, where output signals can be taken anywhere along the length of the line, since there are no reflections along the line. Remark 3.8 Source terminations do not have the problem mentioned in Remark 3.5 of constant power dissipation under high output voltage conditions. 3.5.1.3
Very Short Line
Another way of preventing reflections is to make the line so short that it can be considered to be a lumped circuit – i.e. the voltage and current distribution along the line can be considered to be uniform. If the line is short then this means that Hl (ω) ≈ 1, and hence (3.52) can be written as: A(ω)[ρL (ω) + 1] (3.54) Sshort line = 1 − ρL (ω)ρS (ω) One can now substitute the expressions for the reflection coefficients into this short line expression to obtain: Sshort line =
1
2ZL Z0 ZS +Z0 ZL +Z0 L −Z0 ZS −Z0 −Z ZL +Z0 ZS +Z0
=
ZL ZL + ZS
(3.55)
As can be seen from this expression the line does what we would hope it would do it it is short – nothing. The circuit behaves exactly as a lumped circuit. When can one consider that the transmission line essentially acts as a lumped circuit element – i.e. the transmission line must act like a wire which instantly conducts the voltage from one end to the other. The usual answer is that the line must be much shorter than one-sixth the electrical length of the rising edge of the signal. We can state this mathematically as follows: Length
1 Tr √ 6 LC
(3.56)
where the parameters are defined as: Tr rise time of the signal (sec) L line inductance (H/m) C capacitance (F/m) Length maximum line length (m)
(3.57)
98
Point-to-Point Wiring and Transmission Lines
3.5.2
Capacitive Terminations
Consider the situation shown in Figure 3.11, which shows a capacitor in the middle of the transmission line. The left hand transmission line effectively terminates at the capacitor. Therefore the effective terminating impedance at this point is the impedance of the capacitor in parallel with the impedance of the right hand transmission line.
Oncoming signal with sharp rise time
Z0
Z0
Reflected signal is a short bump - negative derivative of incoming signal
Ongoing signal is degraded in rise time.
Figure 3.11: Transmission line with a capacitive load in the middle. For simplicity we shall assume that the right hand transmission line is terminated with its characteristic impedance, therefore the line impedance seen looking right from the capacitor is Z0 .5 Using this assumption we can calculate the effect load impedance at the capacitor as follows: ZL (ω) = =
1 jωC Z0 1 Z0 + jωC
Z0 1 + jωCZ0
(3.58)
Using this load in the expressions for reflection coefficient we can write: ρC (ω) =
−jωCZ0 2 + jωCZ0
(3.59)
Examining the denominator of this expression one can see that the magnitude of the frequency component of the denominator is equal to the real component when: ωCZ0 = 2 ⇒ fC cut-off =
1 πCZ0
(3.60)
For frequencies at fC cut-off the reflection coefficient magnitude is 1/2, and the reflection is significant. For frequencies fC cut-off the reflection is almost total. 5 We could also assume that the line is terminated with an arbitrary termination, but the line is long enough that any reflections will arrive well after the immediate reflections from the capacitor.
3.5 Termination of Transmission Lines
99
This can be easily deduced by realising that as ω → ∞ then ρc (ω) → −1. The 2 in the denominator becomes irrelevant in relation to the frequency based terms. Therefore one should not use the transmission line with a capacitor attached to it in this fashion under this frequency condition. If we consider frequencies below fC cut-off then we can write the following approximation ρC (ω) = −jωCZ0 /2 = −CZ0 s/2. The complex frequency domain operator s is the Laplace transform for the derivative operator. Therefore the reflection coefficient is acting as a negative derivative operator, with the constant of differentiation equal to −C(Z0 /2). This observation allows us to estimate the amplitude of the reflected pulse as follows: | V− |= −C
Z0 ∆V 2 Tr
(3.61)
where | V− | the amplitude of the reflected pulse in volts, and the other variables have the normal definitions already established. One can see that the rise time of the signal is very important in determining the magnitude of the reflection. If the rise time is slow then the reflected signal may be negligible. The other aspect of interest in this circuit is the transmitted signal to the right hand section of the line. The normal expression for the transmission coefficient is: 1 (3.62) T (ω) = 1 + ρC (ω) = 1 + jωC Z20 This expression shows us that the capacitor acts as a first order low pass filter as far as the signal propagating past the capacitor is concerned. The time conrise time approximately stant of the filter is C(Z0 /2). Therefore the 10%-90% (remembering that the true rise time is Tr = Tr21 + Tr22 ): T10-90 = 2.2C
Z0 2
(3.63)
The net effect is that the rise time of the transmitted edge has been degraded by the presence of the capacitor. An interesting non-obvious case of single capacitive loading on a line occurs when tracks go through a 90◦ angle. This situation is illustrated in Figure 3.12. Ad can be seen from this diagram the effective increase of the line width as it turns the corner causes a discontinuity in the transmission line. It effectively adds a small capacitor to this point on the line. One way of overcoming this is to round the corner so that the line width stays the same, but this option may not be very easy to do depending on the layout software. Another alternative is to chamfer the corner as shown in Figure 3.13, and although it is not obvious, this will achieve the same result and it good for frequencies up to 10Ghz [10]. Note that 45◦ turns require no special treatment. 3.5.2.1
Equally Spaced Capacitive Loads
Consider the situation shown in Figure 3.14. This situation is typical of a bus system where one has a number of equally spaced integrated circuits sitting on the same lines (eg. a number of memory chips). The obvious question to ask in the case of the situation shown in Figure 3.14 is: “What is the effect of the capacitive loads on the performance of the transmission line?”. We have leady looked at the case where we have a single capacitor
100
Point-to-Point Wiring and Transmission Lines
Effective width larger w
w
w
Figure 3.12: Right angle track showing origin of additional capacitance.
0.57w 0.2w
w
0.2w
w
Figure 3.13: Chamfered track to match impedance around a right angle corner.
3.5 Termination of Transmission Lines
101
l cm RS
Z0
+ RL
CL
{
CL
N identical capacitive loads
Figure 3.14: Transmission line with equally spaced capacitive loads. on the line, and we saw that it can have a significant effect on the performance of line depending on the rise time of the signals sent down the line. The effects when we have evenly spaced capacitors depends largely on the spacing of the capacitors relative to the length of the edge of the signals propagating down the line. If the rising edge length exceeds the spacing of the loads then one can derive a simplified approximation for the behaviour of the circuit. If on the other hand the rising edge is of the order of or less than the spacing between the loads then we get the situation with the single capacitor at end of the nodes where the capacitors join the transmission line. Therefore there will be multiple reflections bouncing between these various nodes resulting in degraded signal quality on the transmission line. If we consider the situation where the rising edge is much longer than the spacing between the loads then several capacitors will be involved in determining the behaviour of a single edge. Therefore the capacitors are effectively smeared along the edge. This in effect means that the load capacitors effectively become part of the line capacitance. If we doubled the number of capacitors and halved their values and place these along the same length of line the performance of the line will not appreciably change. Therefore the capacitors can be thought of as continuously distributed capacitance in the form of pF/cm. Therefore the new distributed capacitance for the transmission line is: C = Cline +
N CL l
(3.64)
This new effective capacitance means that we will now have a new effective characteristic impedance for the line: L Z0 = (3.65) C One can see from (3.65) that Z0 will have a lower value than for an unloaded line. In fact it is quite easy to end up with very low characteristic impedances for the line, which makes them very difficult to drive effectively with normal bus drivers. The other problem that arises from this increase in effective capacitance is the √ delay. We know from (2.5) that the delay per unit length is LC . Hence for
102
Point-to-Point Wiring and Transmission Lines larger C then longer the delay is for the signals propagating down a line. This delay occurs regardless of whether we can drive the line or not. Depending on the situation it may be crucially important. For example, if we have a number of high speed memory chips forming the uniformly distributed load, and the transmission lines are the address lines, then the delay will cause a skew in the address information between the first chip on the transmission lines and the last chip. This skew effectively lessens the access time of the last chip on the line. For typical values of the SIMM module capacitances and the length of blocks of SIMMs, delays of the order of 5 to 10nsec would not be unusual.
3.5.3
Multi-point Terminations
Up to this point we have been considering a single line and the various termination options for this. However in a practical printed circuit board there are many instances where a single driver has to drive multiple lines. Obviously there are an arbitrary number of configurations that one can have, so we will consider the very simple case of a single driver driving two lines. Figure 3.15 shows several ways that someone may lay the tracks from the single driver. Problem with reflections here
Z0
Z0
Z0
Z0
Z0
(a) Z0
Z0
Z0
Z0
(b)
Problem with reflection here
Z0
Z0 Z0
Z0
(c) Z0
Z? Z0
(d)
Figure 3.15: Some possible multi-point configurations.
3.5 Termination of Transmission Lines
103
Configuration (a) in this diagram shows an end terminated situation where the second line is branched from the middle of the other line. This configuration will have a problem because of the reflections at the point where the second line is connected. The results of a simulation of this situation where the line parameters are L = 4.6nH/cm and C = 1.1pF/cm and each line is terminated with 64Ω are shown in Figure 3.16. Note the oscillations in the line. Figure 3.17 shows the voltage across the end termination of one of the two lines. Similar oscillations occur on this line due to the reflections from the mid point rereflecting from the source and re-entering the lines. Multi-point line (V) : t(s) 6.0
Node 5 on line
v(v_pulse.v_pulse1)
(V)
4.0
2.0
0.0 0.0
500p
1n
1.5n
2n
2.5n
3n
3.5n
4n
t(s)
Figure 3.16: Voltage just prior to line connection with mid line multi-point connection. If one changes the configuration to that of (b) in Figure 3.15 then we essentially have two separate transmission lines, since the voltage source effective decouples the lines. The disadvantage of this approach is the we are using end terminations which have high power dissipation properties. If we adopt the approach shown in Figure 3.15 (c) we get the results shown in Figure 3.18. As can be seen the performance is totally unsatisfactory. There are severe oscillations at all points on the lines. The problem is that the return reflections from the open circuited line ends are not correctly absorbed at the intersection point of the lines. Therefore this leads to further reflections and we end up with the complex waveforms shown. The oscillations are particularly bad in this case due to the magnitude of the reflections that one obtains from the open circuits at the ends of the lines. An alternative for a series termination that we might try is that shown in Figure 3.15 (d), where the line connection has been changed to be at the termination resistor, and the termination resistor is changed to Z0 /2. In this case we again get reflections from the open circuit end terminations, and under the circumstance that the two line lengths are the same these reflections arrive at the source termination together. The initial waveforms launched down the two lines will be 1/2V due to the parallel loading of the two lines and the voltage
104
Point-to-Point Wiring and Transmission Lines
End termination voltage (V) : t(s) 6.0
End termination voltage
v(v_pulse.v_pulse1)
(V)
4.0
2.0
0.0 0.0
1n
2n
3n
4n
t(s)
Figure 3.17: Termination voltage with a mid line multi-point connection.
Graph0 (V) : t(s) 6.0
v(v_pulse.v_pulse1)
(V)
4.0 2.0 0.0
(V) : t(s)
6.0
Line 2 end voltage
(V)
4.0 2.0 0.0
(V) : t(s)
6.0
Mid line voltage
(V)
4.0 2.0 0.0
(V) : t(s)
6.0
Line 1 end voltage
(V)
4.0 2.0 0.0 0.0
2n
4n
6n
8n
10n
t(s)
Figure 3.18: Waveform plots for a multi-point line with a single series termination and mid point line connection.
3.5 Termination of Transmission Lines
105
division by the presence of the Z0 /2 source terminator. The reflected voltages from the open circuit terminations at the end of each of the lines will reach the junction point at the same time (due to the equal line lengths) and hence one will get 1/2V + 1/2V = V volts at this point. A reflection does not result from this as because the return currents are able to be totally absorbed into the source terminator (because we have twice the return current and one half the normal source resistance). The plots for this situation are shown in Figure 3.19
Single source termination R=R0/2, equal line lengths (V) : t(s) 6.0
v(v_pulse.v_pulse1)
(V)
4.0 2.0 0.0
(V) : t(s)
6.0
Line 2 termination
(V)
4.0 2.0 0.0
(V) : t(s)
6.0
Line 1 termination
(V)
4.0 2.0 0.0 0.0
2n
4n
6n
8n
10n
t(s)
Figure 3.19: Two multi-point lines branching from a Z0 /2 source terminator – the lines are of the same length. If the two lines that split off are of different lengths the situation described above no longer applies. The reflections from the open circuit terminations will not arrive back at the junction at the same time and there will be a number of oscillations in the system due to this. This effect is shown in Figure 3.20. Here we have the source termination equal to Z0 /2 as in the previous case, but one of the lines is half the length of the other. Therefore the reflection from this line will arrive back at the junction much sooner from the shorter line, and hence there is a voltage difference at this point some of the return signal from one line flows into the other. One can see that the termination signals are no longer satisfactory. Therefore, in general, the technique of using a single source termination for a multi-point system is not going to give good signals. Note 3.1 It should noted that one cannot daisy chain gates off lines when one has source terminations, since the signal at intermediate points on the line will have a two step form. If one uses an end terminator the signal will have the correct form as it propagates down the line. Note 3.2 The use of end terminations of the form shown in Figure 3.15 is not usual in digital systems. The main problem is the drive required to drive the
106
Point-to-Point Wiring and Transmission Lines
Single source termination Rs=R0/2 and different length lines (V) : t(s) 6.0
v(v_pulse.v_pulse1)
(V)
4.0 2.0 0.0
(V) : t(s)
8.0
Line 2 termination
(V)
6.0 4.0 2.0 0.0
(V) : t(s)
8.0
Line 1 termination
(V)
6.0 4.0 2.0 0.0 0.0
2n
4n
6n
8n
10n
t(s)
Figure 3.20: Two multi-point lines branching from a Z0 /2 source terminator – the lines are of different lengths. termination. For example, not many gates would be capable of driving a 65Ω resistive termination to 4 Volts. In addition there is the issue of DC power dissipation in steady state in these terminations. Generally speaking the series termination is much more common. One can also use the split end termination (i.e. two resistors, one connected to +5V and the other to ground, with the parallel combination of the resistors equal to Z0 ), although these still have many of the problems of the single termination resistor. A common way of splitting two lines that is commonly used in communications applications is shown in Figure 3.21. This works on the principle that the impedance looking from the left hand line (which we will assume is the source line) is: Zin = Z0 /3 + (Z0 /3 + Z0 ) (Z0 /3 + Z0 ) = Z0 /3 + 2Z0 /3 = Z0
(3.66)
Therefore the impedance looking into the midpoint connection is the characteristic impedance of the line. Therefore there should be no reflection at the intersection point. It should be noted that the ends of the two lines at the right have to be terminated in the characteristic impedance of the line so that there are no reflections coming back to the junction point. For the reason cited above the technique is therefore not useful for digital systems. The other problem is that the signals are attenuated. If the signal on the left line is V, then the signals propagating down the right lines would be 2/3V. These effects can be seen in Figure 3.22.
3.5 Termination of Transmission Lines
107
Z0
Z0 3
Z0 3
Z0
Z0 3 Z0
Figure 3.21: Multi-point splitter using resistive network.
Waveforms with splitting network (V) : t(s) 6.0
v(v_pulse.v_pulse1)
(V)
4.0 2.0
(V)
0.0
(V) : t(s)
6.0 5.0 4.0 3.0 2.0 1.0 0.0
Just before split
(V) : t(s)
4.0
Line 2 termination
(V)
3.0 2.0 1.0 0.0
(V) : t(s)
4.0
Line 1 termination
(V)
3.0 2.0 1.0 0.0 0.0
2n
4n
6n
8n
10n
t(s)
Figure 3.22: Multi-point waveforms using the resistive “splitter” network.
108
Point-to-Point Wiring and Transmission Lines Remark 3.9 The branching technique of Figure 3.21 is used a lot in communications systems to cheaply split signals from antenna. For example, the splitter or diplexer used on home television is often based on this circuit. One needs a strong incoming signal in order to split it in this way. Remark 3.10 If one has PCB tracks then matching can be achieved by changing the design of the tracks. For example, if the characterisitc impedance of the source track is Z0 then the impedance of the branches can be made to be 2Z0 . This means that the impedance looking into the branch point from the source is Z0 . The two branch tracks do not have terminations, and the source is source terminated. Because the two branch lines do not have terminations there are reflections at the ends which will double the voltage (which was 12 V due to the source termination). These reflected waves then travel back down the branch lines to the line junction point, where they will re-reflect and be partially transmitted. If the branch lines are of the same length then the oscillations are not too bad, but if the lines are of different lengths then the branch reflections arrive at different times and the resultant waveforms are highly distorted. Practical Issue 3.1 If one has to branch tracks off each other then attempt to choose the track sizes to achieve the effect in the previous remark. In addition make sure that the branch tracks are symmetric as far as possible. In many practical circuit layouts one has to connect multiple ICs to a signal trace. An example of this is where there is a global clock line on a circuit board. In this situation it is impractical to run a separate terminated line from the clock source to all the receiving circuits. There are several things that can be done to make the layout feasible and to maintain the signal integrity.
Main transmission line path
These trace stubs appear as a capacitor in parallel with the receiver.
End termination
Figure 3.23: Poorly designed gate daisy chain with end termination. Figure 3.23 shows a set of gates daisy chained off a transmission line. The small stub traces to the gate inputs are short enough that they can be considered as lumped elements. Therefore they appear as extra capacitance in parallel
3.5 Termination of Transmission Lines
109
with the input capacitance of the gate. Consequently the edge of the signal is progressively degraded as it propagates down the transmission line. The other point to note about this circuit is that it is load terminated, as opposed to source terminated. Load termination is required in order to ensure that all the gates in the middle sections of the line receive a good quality signal without the two stage step that is present when there is a source termination.
{
From driver
Gate pins connected directly to the trace
Terminating resistor
Line extends beyond receiving gate
Figure 3.24: Better design for a gate daisy chain. Figure 3.24 shows the layout for a better design of a set of daisy chained gates. The relevant design features shown in this figure are that the gate inputs are connected directly into the track without any stub tracks. This keeps the added capacitance at the gate points to the input capacitance of the gate, without the added capacitance of the stub. Another point about the design is that the receiving gates should be positioned the same distance apart (or as near as one can get), the distance being significantly less that the length of an edge on the trace. This will ensure that the gate input capacitances appear as added transmission line capacitance, and will not lead to degraded edges, but just a different characteristic impedance. Finally, the last gate should be positioned before the end of the line, so that its input capacitance is seen as a part of the line, and not a capacitance across the terminating resistor. This will prevent reflections from a capacitance termination.
110
Point-to-Point Wiring and Transmission Lines
Chapter 4
Ground Planes and other Printed Circuit Board Issues This chapter will concentrate on issues related to the lay out of ground planes and tracks on printed circuit boards. These issues are very important if one is to get a printed circuit board that works with the high speed digital technology prevalent today. Ground and power planes in high speed digital systems perform three critical functions: • Provide stable reference voltages for exchanging digital signals. • Distribute power to all logic devices. • Control crosstalk between signals.
4.1
Power Planes
A power plane system is used in many modern printed circuit board designs. A power plane system consists of two parallel power planes, one being the positive supply plane and the other being the negative supply (or ground) plane.1 Consider the power planes shown in Figure 4.1. If one considers the two power planes as a lossless TEM mode transmission line then it is possible to show that the characteristic impedance of the plane is approximately: h η0 Z0 ≈ √ (4.1) r w where η0 ≈ 377Ω, the characteristic impedance of free space. This transmission line characterisation of the power planes is complex because of the problems of characterising the line with the terminal ports located anywhere on the plane. 1 The presence of two ground planes means that at a minimum one would usually have a four layer PCB – two layers for power distribution and two for signal distribution.
112
Ground Planes and other Printed Circuit Board Issues
Power planes
l h
w
Figure 4.1: Dimensions of two power planes. Example 4.1 Consider (4.1) with power planes of dimensions of w = 25cm and h = 0.075cm, the thickness being half the thickness of the typical epoxy fibre glass PCB board (FR-4), which has r = 4.7. The Z0 is 0.52Ω – the characteristic impedance is very low. Another interesting fact is that the velocity of a wave in the transmission line depends only on the dielectric for the material: 1 c v=√ =√ r L0 C0
(4.2)
where r the relative dielectric constant, c the speed of light, and L0 , C0 are the inductance and capacitance per unit length. This equation indicates that there is a fundamental relationship between the inductance and capacitance per unit length for a transmission line. Other relevant expressions are those for the capacitance and inductance for the planes: A wl = r 0 h h w C = r 0 ∴ C0 = l h C = r 0
(4.3)
Using this expression together with the characteristic impedance expression one can also calculate the inductance per unit length: L0 ⇒ L0 = Z02 C0 Z0 = C0
2 w η2 h r 0 ∴ L0 = 0 r w h h = η02 0 w h =µ (4.4) w
4.1 Power Planes
113
If we consider the line dimensions from the previous example we can calculate the effective inductance and capacitance per unit length:2 C0 = 4.7 × 8.854 × 10−14
25 0.075
= 0.138nF/cm
(4.5)
∴ CT = 25 × C0 = 3.5nF
(4.6)
L0 = 4π × 10−9 ×
0.075 25
= 38pH/cm
(4.7)
where l = 25cm. Remark 4.1 As one can see from the above numbers the power plane has a modest total capacitance and a very low inductance per unit length. The combination of the capacitance and the low inductance means that there will be very low transient voltage drops along the ground plane when a rapidly rising current is drawn from the plane.
4.1.1
Decoupling Capacitors and Power Planes
Of practical interest is where should decoupling capacitors be placed in relation to an electronic component on a power planed PCB. In order to answer this question we shall use the impedance expressions of (H.160), repeated here for convenience: ZL cos(βl) + jZ0 sin(βl) Zin = Z0 (4.8) jZL sin(βl) + Z0 cos(βl) If the line is terminated with a capacitor (which is meant to represent a decoupling capacitor) then ZL = 1/jωC. Let us substitute this into the expression above for the input impedance. To enable the expression to be simplified to a meaningful expression we can make a few approximations – we shall assume that C0 l C (which would usually be √ the case when the C is a decoupling capacitor), and |βl| 1 (where β = ω L0 C0 ) (which again would be the case for reasonable frequencies – < 500Mhz, and lengths) . Given these assumptions we can develop the following approximate expression for Zin : L0 L0 1 cos(βl) + j sin(βl) C0 jωC C0 Zin = (4.9) L0 1 C0 cos(βl) + j jωC sin(βl) Realising the the approximations cited above mean that: cos(βl) ≈ 1 and sin(βl) ≈ βl then we can simplify the expression to: Zin ≈ 2 0
= 8.854 × 10−14 ≈
1 jωC
+ jωL0 l
1+
1 F arads/cm, µ0 36π×109
C0 l C
= 4π × 10−9 H/cm.
(4.10)
114
Ground Planes and other Printed Circuit Board Issues and since C0 l/C 1 then 1 + C0 l/C ≈ 1 and hence we can write: Zin =
1 + jωL0 l jωC
(4.11)
which is simply a series LC circuit. Remark 4.2 Equation (4.11) shows that an inductance equal to L0 l is effectively in series with the decoupling capacitor. If one considers a PCB with the parameters calculated in the previous section (C0 = 0.138nF/cm and L0 = 38pH/cm) then the inductance with the capacitor at a distance of 2.5cm from the chip it decoupling is 95pH. This is very small compared to the package inductances for the capacitor and the chip leads (which are in the nH range). The main result is that the placement of the capacitor is not critical with respect to the chip it is decoupling. Therefore there is no need to constrain the placement and routing too much to get the capacitors close to the ICs. Remark 4.3 It is interesting to note that the power planes are themselves transmission lines. Therefore they should be subject to reflections as are the lines we have looked at previously, and this is what happens. If a pulse in injected (due to an IC pulling a current from the power planes) then the voltage and current propagate in every direction from the initiating point. When they reach the edge of the board then there is an open circuit termination and consequently a reflection would occur. Fortunately the magnitude of these reflections are small due to the small instigating pulse, and the fact that the decoupling capacitors also have an effect.
4.2
Crosstalk Issues
In the previous chapters we have already considered some of the crosstalk issues, related to the crosstalk between resistors mounted on a ground plane printed circuit board (PCB), inductive and capacitive coupling between short lines. It should be noted that the coupling issue between resistors on a printed circuit board is very relevant to the line termination of the previous chapter. In this particular case one can get significant coupling between the termination resistors, especially if they are arranged next to each other on a PCB.
4.2.1
Path of Least Inductance
At low frequency spectral content current flows along the path of least resistance through a printed circuit board, including the power planes. However, at high frequencies the current tends to still take the circuit path that resistors the flow of current least, but in this case the inductance (and not the resistance) is the major influence on the current path. These concepts are shown diagrammatically in Figure 4.2. Notice that the current for high frequency spectral content currents flow through the ground plane under the printed circuit board trace. This path minimises that inductance of the current loop (since the area of the loop is minimised).
4.2 Crosstalk Issues
115
Load Current flow
Driving gate
Low frequency current flow
Load
Current flow
Driving gate
High frequency current flow
Figure 4.2: Approximate current flows with low and high frequency spectral content.
116
Ground Planes and other Printed Circuit Board Issues An approximate relation for the return current density at a point D cm away from a signal trace is: I0 1 i(D) = (4.12) πH 1 + (D/H)2 where: where I0 total signal current, Amp H height of the trace above the circuit board, cm D perpendicular distance from signal trace i(D) signal current density, A/cm
(4.13)
Figure 4.3 shows the form of the distribution of the current under a trace. One may initially think that all the current would bunch up as tightly as possible under the trace. However the distribution of the current indicated in (4.12) is actually a balance of two opposing forces. If the current is bunched under the conductor then the inductance would increase as a thin wire carrying the same current has a higher inductance than a fat wire. Therefore, this would mean that the current would tend to widen. Opposing this is as the current widens across the ground plane the effective loop area starts to increase, and this tends to raise the inductance. Therefore this tends to bunch the current. The balance of these two effects leads to (4.12).
Current density at D is proportional to: 1 2 D 1+ H
W
FH IK
Trace
H
D
Ground plane
Figure 4.3: Distribution of current in the ground plane when the currents have high frequency components.
4.2.1.1
Crosstalk in Ground Planes
As noted in previous chapters the crosstalk between two conductors depends on their mutual capacitance and inductance. In digital circuits the mutual inductance is usually the larger of the two coupling mechanisms, therefore we shall concentrate on this for the rest of this discussion. Figure 4.4 shows two traces above a ground planed PCB, and the resultant current distribution under the current carrying trace. The theory behind mutual inductance between the conductors was considered in Section 2.5.4. The equation (2.38) was also postulated for the mutual inductance between two wires.
4.2 Crosstalk Issues
117 Current density at D is proportional to: 1 2 D 1+ H Trace
FH IK
W
H Ground plane
D
Figure 4.4: Two traces above a ground plane and the resultant current distribution. Notice the similarity between this expression and the current density expression (4.12). Because the returning current density and its associated local magnetic field strength drop off according to (4.12) then we may suspect that the cross-coupling will also drop off as: K (4.14) Crosstalk = 1 + (D/H)2 where K is related to the circuit rise time and the length of the interfering traces. This relationship can be verified experimentally. The main intuitive result is that for a fixed trace spacing the cross-coupling falls off with a 1/(1/H 2 ) relationship (remember that the current density has a constant in front of it with a 1/(1/H 2 ) variable). Therefore it is important that the traces are kept close to the ground plane. The other important factor is the separation of the traces. The cross-coupling falls with a 1/D2 relationship. Therefore it one wishes to minimise the coupling then kept the traces a long way apart. Clearly, overall it is the D/H relationship that is the important factor. 4.2.1.2
Crosstalk in Slotted Ground Planes
Slots appearing in the ground plane is a classic layout mistake. These slots usually occur when a layout person runs out of room on the regular routing layers and decides to cram in a trace on the ground plane layer. This is achieved by cutting a long slot in the ground plane and laying the trace in the slot. The effect of this practice can be seen in Figure 4.5. The return currents have to traverse around the slot thereby dramatically increasing the inductance of the traces that are generating the return current, and thereby slowing down the signal rise times. In addition an appreciable amount of current is flowing under an adjacent trace increasing the mutual inductance between the traces. Slotted ground planes can also occur unintentionally when putting connectors onto a PCB. Consider Figure 4.6 which shows the holes for a multi-pin connector. If the clear-out holes for the connectors pins are made too big then it is possible to form a virtual slot in the ground plane. One should always ensure that there is a path through a connector pin field.
118
Ground Planes and other Printed Circuit Board Issues
Slot in the ground plane
Return currents for AB trace B
A
C
D
Return current for CD trace
Figure 4.5: Current paths with a slot cut in the ground plane of a PCB.
Current has to flow around the connector area.
Cut-out holes for connector is too big.
Reduced cut-out holes allow current flow through the connector area.
Figure 4.6: Current flow through connect hole grids.
4.2 Crosstalk Issues
119
Remark 4.4 It should be noted that the width of the slot in the ground plane does not matter. It is the length of the slot perpendicular to the traces that counts as this determines the degree to which the current must divert to go around the slot. As a trace progressively gets closer to the end of a slot then the extra inductance decreases linearly with distance from the slot end. If a trace is close to a slot but does not run over the slot then the slot presence has virtually no effect. Remark 4.5 One can write down approximate expressions for the inductance added by slots. These will not be presented because one should not have slots in the ground plane at all. 4.2.1.3
Crosstalk in Two Layer PCBs
Sometimes for cost or manufacturing reasons one may wish to use a two layer board therefore it is relevant to consider how one may lay out the power and ground planes on such a board. The technique shown in Figure 4.7 achieves a two layer power grid system at the expense of more mutual inductance between traces, and generally higher trace inductances. It will work alright for lower speed designs such as low speed CMOS or LS-TTL designs, but it is unsuitable for high speed designs – there is no substitute for ground planes for these systems. The important point to note from Figure 4.7 is that the return current takes the least inductive return path from the load to the source. This often involves the current flowing through the positive power plane via the coupling capacitors. As can be seen from the figure the current will often traverse a number of capacitors on the way from the load to the source, therefore it is important that very low inductance and low impedance capacitors are used. The presence of the capacitors effectively make the power/ground grid a cross hatched ground system. The inductance of a single trace running across a cross hatched power/ground grid layout is approximately: X (4.15) L ≈ 2Y ln W where: where L inductance, nH X hatch width, cm W trace width, cm Y trace length, cm Remark 4.6 If two traces run between the same two cross-hatched members then the currents for both the traces will take the same path. The mutual inductance between the two traces will be L under this situation. If a second trace is offset by a good distance D, its mutual inductance with the first trace decreases with a denominator similar to that in (4.12), but with the cross hatch dimension replacing the term H: LM ≈
2Y ln(X/Y ) 1 + (D/X)2
(4.16)
120
Ground Planes and other Printed Circuit Board Issues
Y
Trace width W
X
X
GND
+5V
Current takes the lowest inductance path back to the source. Notice that the current travels along both the ground and power rails, transferring between then via the capacitors.
The ground tracks go under the positive supply tracks.
Figure 4.7: Layout of a two layer power plane.
4.2 Crosstalk Issues 4.2.1.4
121
Crosstalk in with Power and Ground Finger PCBs
An alternative to the power and ground grid design is a layout using the power and ground fingers. The basic layout of this is shown in Figure 4.8.
GND
Return current flows around the periphery of the board.
+5V Direct signal path
Figure 4.8: Layout of a finger power and ground plane system. This type of layout for two sided boards was prevalent in the early days of computing (e.g. the PDP-8 computer used this, as well as most of the wire wrap boards available 15 years ago). However, this type of layout is not really usable in modern equipment due to the large inductances of the traces and degree of crosstalk. The reason for this can be seen in Figure 4.8 – the return currents have to flow around the periphery of the board. Therefore the loop area of the current from the source driver to the source current return point is potentially very large. This same effect means that there are magnetic fields everywhere with this design, and such boards would not satisfy modern electro-magnetic emission standards. This effect also means that the cross coupling between traces will be very high.
122
Ground Planes and other Printed Circuit Board Issues The approximate loop inductance on a power and ground finger board is: X L ≈ 2Y ln (4.17) Y where: where L inductance, nH X board width, cm W trace width, cm Y trace length, cm Notice that making the trace width twice as large will have little effect on the inductance. Remark 4.7 One can probably get a board going using old logic families using this type of board design, but one would have little hope of getting modern logic to work with it. 4.2.1.5
A Note on Guard Traces
A technique used in analogue design to prevent coupling between signals is to place what is known as a guard trace between the lines that one wishes to minimise the coupling between. Figure 4.9 shows the basic configuration of a guard trace. The basic principle is Lenz’s Law. There is a coupling between the signal line an the guard trace. This induces a current in the guard trace that will oppose the field that is causing the current. Therefore the mutual field will tend to be cancelled. This lessens the field linking the second signal trace and therefore the mutual inductance is less. A guard trace is effective at reducing coupling. However, in a digital system where reasonable levels of crosstalk are acceptable, and where all the signal traces have similar current levels flowing through them, the separation required to put in the guard trace gives enough isolation (remember that crosstalk< 1/(1 + (D/H)2 )), therefore it is to a large degree pointless putting it in. In the case of analogue circuits very high noise immunity is required, and one can have high current conductors near very sensitive circuits. Under these conditions guard traces are very helpful. 4.2.1.6
Distributed Cross Coupling
The discussion thus far has concentrated on arguments using lumped circuit theory. In many situations this reasoning gives reasonable results, but in the case of long lines (relative to the switching edges) one must consider the distributed nature of the lines. Figure 4.10 shows a circuit approximation of couples distributed transmission lines sitting on a ground plane. What should happen with these lines? The mutual inductive coupling should result in voltages appearing across the inductive elements in line 2 (the line without the source). These voltages appear progressively down the line with respect
4.2 Crosstalk Issues
123
Signal trace 1
Guard trace
Signal trace 2
Figure 4.9: Guard trace configuration.
Driving signal
k
A CM LM
B CM
LM
LM
CM
LM
C
D
Positive polarity negative wave from transformer k
Negative polarity positive wave from transformer k
Figure 4.10: Model for the coupling of a distributed transmission line.
124
Ground Planes and other Printed Circuit Board Issues to time as the initial voltage step propagates down the line. Consequently two waves are injected into the line at each of the mutual inductances, one travelling in a positive direction down the line, and the other travelling in a negative direction down the line. The positive travelling wave (which is actually of negative polarity) is reinforced at every successive tap point since it travels in the same direction and at the same velocity as the instigating wave. On the other hand the negative direction travelling wave (which is of positive polarity) is not reinforced since it travels in the opposite direction to the instigating waveform. A new negative travelling wave occurs progressively at each of the taps down the transmission line. Therefore we end up with a set of waves which arrive at the source end termination in line 2 in succession, resulting in a long low pulse here. At the load end termination of line 2 the positive travelling pulses all arrive simultaneously resulting in a single larger pulse. Note that the simulation is only a discrete model of an completely distributed system, therefore the real line would look slightly different. Remark 4.8 The positive direction travelling pulse is negative because of the assumed polarity of the mutual coupling. We are assuming that the left hand side of the line 2 inductors are positive. Remark 4.9 Because line 1 is correctly terminated the mutual inductance has little effect on its performance. The coupling back from line 2 to line 1 due to the currents and voltage induced in line 2 is small due to the small currents and voltages present in line 2 relative to those in line 1. Figure 4.11 shows the effects of mutual inductance only on a transmission line. The pulse has a rise time of 210psec, the line length is 11cm, and the line parameters are L0 = 4.5nH/cm and C0 = 1.1pF/cm (i.e. Z0 ≈ 64Ω). Similarly to the previous section we assume that there is a capacitor connected between the various tap points of the transmission lines. The main difference between the capacitive coupling case and the inductive case is that both the positive and negative travelling waves created at each tap are of positive polarity. Apart form this the explanation of the waveforms is identical to the inductive case, and for the sake of brevity will not be repeated here. The waveform for the 210psec rise time case is shown in Figure 4.12. If both capacitive and inductive coupling are present then clearly on gets the combined effect of both. The load end effects of the mutual and capacitive coupling will cancel each other to some degree (since they are of opposite polarity). At the source end of line 2 the two effects will reinforce making this pulse larger than in only one of the effects is present. These statements are backed up by comparing Figure 4.11 and Figure 4.13. The source end reflection can often become a far end problem because the source end pulse is reflected at the source.
4.2 Crosstalk Issues
125
Mutual inductance 0.5nH, load terminated, Tr=210psec (V) : t(s)
(V)
0.2
l2.p5
0.0 −0.2
(V) : t(s)
(V)
4.0
L1.END
2.0
(V)
0.0
(V) : t(s)
0.2 0.0 −0.2 −0.4
L2.END
(V) : t(s)
(V)
4.0
v(v_pulse.v_pulse1)
2.0 0.0
(V) : t(s)
(V)
0.2
L2.SRC
0.0 −0.2 0.0
500p
1n
1.5n
2n
2.5n
3n
t(s)
Figure 4.11: Mutual inductively coupled transmission lines with Tr = 210psec
126
Ground Planes and other Printed Circuit Board Issues
Cap coupling− Tr=210psec (V) : t(s) 0.2
l2.p5
(V)
0.1 0.0 −0.1
(V) : t(s)
3.0
v(v_pulse.v_pulse1)
(V)
2.0 1.0
L1.END
0.0
(V) : t(s)
(V)
0.1
L2.SRC
0.0
−0.1
(V) : t(s)
0.4
L2.END
(V)
0.2 0.0 −0.2 0.0
1n
2n
3n
4n
5n
6n
t(s)
Figure 4.12: Waveforms for capacitively coupled transmission lines and Tr = 210psec.
4.2 Crosstalk Issues
127
Mutual and cap coupling, Tr = 210psec (V) : t(s)
(V)
0.2
l2.p5
0.0
(V)
−0.2
(V) : t(s)
0.2 0.1 0.0 −0.1 −0.2
L2.SRC
(V) : t(s)
(V)
4.0
L1.END
2.0 0.0
(V) : t(s)
(V)
0.1
L2.END
0.0 −0.1
(V) : t(s)
(V)
4.0
v(v_pulse.v_pulse1)
2.0 0.0 0.0
1n
2n
3n
4n
5n
t(s)
Figure 4.13: Mutual coupling waveforms with both inductive and capacitive coupling and Tr = 210psec.
128
Ground Planes and other Printed Circuit Board Issues
Part II
Switched Mode Power Supplies
Chapter 5
Fundamental Topologies 5.1
Introduction
This course part will not attempt to cover every issue related to the design and operation of switch mode power supplies – there is more than enough work in this area to fill a whole course by itself. Instead, the material shall seek to emphasise the main types of switch mode converter structures, their fundamental operational principles, the various areas where the different structures are useful, and finally aspects of the design and control of the switch mode converters. Before looking at the different structures for switch mode converters, we should firstly define what we mean by switch mode converters. Definition 5.1 Switch Mode Converters (SMCs) are converters which accept a DC input and generate a DC output. Switched mode converters are usually only operating at powers up to 10’s of kilowatts. The switched mode converter usually finds application as a power supply regulator in such items as computers, television sets, stereo systems etc., in fact almost all modern electronic consumer devices use some form of switch mode converter. One of the other areas of application of switch mode converters are aerospace systems, where weight is a very important consideration. The switch mode inverter, on the other hand accepts a DC input and generates an AC output. These are treated in their own section of this course, since these devices tend to find application in the high power industrial systems area, and are most often used for the control of electrical machines (although they are not exclusively used for this).
5.2
References
References to switch mode power supplies are often contained in texts on electronics and power electronics. There are some specialised book written on the design of switching power supplies. Tutorial references that readers may find useful are [4, 11–13]. One can find a lot of material in the IEEE Transactions on Industrial Electronics, and the IEEE Transactions on Power Electronics. This information
132
Fundamental Topologies tends to be of a more detailed nature on specific design issues with converters, or new converter topologies.
5.3
Taxonomy of Switch Mode Converters
There are literally hundreds of different circuit configurations for switch mode converters. However, one can classify most of the them into two basic categories: buck converters
• Step-down or buck converters.
boost converters
• Step-up or boost converters. Many of the other topologies that are in the literature are combinations of these two basic topologies. The basic layout of a SMC system is shown in Figure 5.1 below. The input to the converter is usually the mains. Since this is AC the first step is to convert this to DC via a rectifier. Notice that one can also feed DC, from a battery, directly in at the output point of the rectifier. The unregulated DC is usually filtered with a capacitor, before feeding the DC-DC converter electronics. The output of this stage then feeds the load.
Battery
AC line voltage Uncontrolled Filter DC-DC capacitor converter (1 or 3 diode rectifier DC DC DC phase) (unregulated) (unregulated) (regulated)
Load
Desired output voltage
Figure 5.1: Block diagram of the structure of a typical DC-DC converter. In the following diagrams the switches are assumed to be unidirectional. The direction of current flow is indicated by the arrow on the switch.
5.3.1 output voltage is always less than input voltage
Step-down or Buck Converters
The step-down or buck converter is distinguished by the fact that the output voltage is always less than the input voltage. This means, that regardless of the switching strategy, it is impossible to get the output at a higher voltage than the input. The distinguishing circuit feature of the buck converter is that one cannot get any current to flow in the circuit when the power device is turned on, if the output voltage is greater than or equal to the input voltage. Figure 5.2 shows a basic circuit for a buck converter. Before analysing the circuit, let us look at it heuristically to determine its basic operation. When the switch SW closes, current will flow to the resistive load via the inductor
5.3 Taxonomy of Switch Mode Converters
133
L. The capacitor C will charge up during this process. Note that there is a transient involved in the inductor current building up and the voltage being established on the capacitor. When the switch is opened the current through the inductor cannot stop instantly (if it does then the voltage across the inductor will become very large and the circuit will most probably be destroyed). The diode in the circuit will become forward biased, allowing the current in the inductor to continue flowing in the same direction (towards the load). During this phase of operation the energy that was stored in the field of the inductor during the switch on time is being transferred to the load. If the switch remains open for a long time the inductor current gradually decreases to zero, and at the same time the current drawn from the capacitor increases. If the switch is closed before the inductor current decreases to zero, then the current begins to increase again. Remark 5.1 Note that the maximum current that can flow through the inductor if the switch is left closed is Vd /RL . Remark 5.2 If the inductor current goes to zero then the converter is said to be operating in discontinuous mode. If it does not go to zero, then the converter is operating in continuous current mode. Generally speaking, it is desirable to operate the converter in one mode or the other, without a change of mode. Changes in mode can result in difficulties in controlling the output voltage of the converter. A change of mode can occur depending on load changes. Remark 5.3 If the filter were not present in Figure 5.2 then the output voltage would exactly mirror the input voltage – i.e. if the switch is opened an closed then the output would be a square wave voltage. The filter has to be designed so that the cutoff frequency is significantly below the switching frequency. If this is the case then the filter will reject most of the AC components present at the vod , so that the output voltage will essentially be a DC value equal to the average value of the voltage vod . Remark 5.4 One of the distinguishing features of this type of circuit is that when the switch is closed the input is connected to the output, but when the switch is open the input is disconnected from the output. Another distinguishing feature of the buck converter is that the inductor is not placed across the input voltage when the switch is closed. The inductor has a voltage imposed across it that is usually somewhat lower than the input voltage. This means that the inductor does not store all the energy being supplied by the input. Remark 5.5 If multiple output voltages are required then the buck converter as depicted here is not the topology to use. Other converters, such as the forward converter, that are related to the buck converter can be used. Remark 5.6 Since the switch is at the input to the converter, then the input current is discontinuous. Therefore the input filter to this circuit is more complicated compared to other converter types. Practical Issue 5.1 Driving the gate of a buck converter can be a problem. If we assume that the switching element is a n-channel MOSFET (as it would be
buck converter distinguishing features
134
Fundamental Topologies
Energy storage inductor
Low pass filter iL
SW
id
+
vod
Vd
L vL
-
io RL Load
C
Vo
Figure 5.2: A basic buck or step-down converter. for many designs), then the gate voltage often has to be 5V, and in some cases 10V above the supply voltage. This complicates the gate drive, since one has to fabricate the higher voltage using a transformer based gate drive circuit.
5.3.2 output voltage that is always greater than the input voltage
Step-up or Boost Converters
As the name implies, the boost or step-up converter has an output voltage that is always greater than the input voltage. The boost converter also has the added advantage that the output can isolated from the input (using transformer isolation). Figure 5.3 shows a conceptual diagram of a non-isolated boost converter. The basic operation mechanism is that when the switch is closed the load is isolated from the input by the diode, and current builds up in the inductor. This current build is effectively storing energy in the field of the inductor. When the switch is opened, the current in the inductor wishes to continue to flow in the same direction and with the same magnitude. Therefore the diode will turn on and the current will immediately flow into the filter capacitor and any connected load.
Energy storage
iL
+ Vd
io
L vL
SW
+ C
Vo
-
Figure 5.3: A basic boost or step-up converter.
5.3 Taxonomy of Switch Mode Converters
135
Remark 5.7 If the voltage on the capacitor is larger than the supply voltage, the inductor will produce what ever voltage is required so that Vd + vL = Vo . This is required in order for the current to continue to flow in the inductor. One can see that because the polarity of vL shown in Figure 5.3 always has to reverse for this situation, then the output voltage must always be greater than the input voltage (except under initial start-up conditions). Remark 5.8 The main feature of the boost converter is that current can flow through the switch regardless of the relationship between the input and output voltages. This usually occurs because the input to the circuit is disconnected from the output when the switch is closed. It is this feature that one must look for when one is trying to ascertain what category a particular topology falls into. When the switch is opened, the input is connected to the output because the diode switches on. Another distinguishing feature is that when the switch is closed the input voltage is placed across the inductor (so that it stores all the energy being supplied by the input), and when the switch is opened the inductor is placed in series with the load. and this stored energy is transferred to the load. Remark 5.9 In a boost converter the inductor fulfills an energy storage function, whereas in the buck converter the inductor forms a filtering function. Therefore, one can view the boost converter as not having a filter capacitor. This distinction is not very clear for the non-isolated converter, but when we look at isolated converters in the next chapter we shall see that there is a clear distinction. Remark 5.10 There is a maximum power that is practical to build for converters that rely on the energy storage principle. This is especially true for low input voltages. As we shall see in the next chapter a related converter is the flyback converter, which operates using the same principle, and hence suffers from the same power limitations. In order to cater for high power output with an energy storage converter, one needs to have a very small energy storage inductor (since E = 12 Li2 , and therefore the current contributes most significantly to the stored energy). It turns out that for powers much above 50W when the input voltage is low, the inductance becomes very small and is comparable with the parasitics of the circuit. Therefore, the circuit becomes very difficult to manufacture.
5.3.3
Buck–Boost Converters
The buck–boost converter seeks to combine the properties of the previous two converters. This converter type allows the output to be less than or greater than the input voltage. Furthermore, this type of converter also allows a negative polarity output to be generated. The most obvious way of generating a buck–boost converter is to cascade the buck and the boost converter. In practice, however, this is not usually done, since one can obtain the same performance from the system using a single switch arrangement. In this case one must really consider the circuit configuration to be a new one, and not a combination of the previous two.1 1 One must consider the buck-boost converter to be a configuration in its own right, since it is very difficult to see the separate buck or boost converters in the single switch circuits.
boost converter distinguishing features
136
Fundamental Topologies In order to understand the operation of this circuit let us firstly look at a two switch implementation. Figure 5.4 shows the conceptual circuit for this. In this circuit both switches are either closed at the same time, or they are open at the same time. If both the switches are closed, then the circuit takes on the classic boost converter configuration. If the output voltage is higher than the input voltage, current can still flow through the inductor. When both the switches are opened, then the inductor is positioned in the circuit as in the classic buck converter, and the current built up during the switch closed stage circulates via the diodes through the output capacitor. Remark 5.11 The key to the circuit of Figure 5.4 is that the switches effectively change the circuit configuration, from a boost circuit during the energy storage phase, to a buck circuit when energy is transferred to the load.
iL
SW1
+ Vd
L vL
io
SW2
C
Vo
RL
Figure 5.4: Two switch buck–boost converter. Figure 5.5 shows a simplified circuit for a buck-boost converter circuit using only one switch. The crucial change in this circuit is the swap of the inductor and the switch and the reversal of the diode as compared to the boost converter of Figure 5.3. The swapping of the inductor and the switch and reversing the diode means that the full input voltage is applied across the inductor when the switch is closed (as in the boost converter). This means that the inductor is essentially a energy storage element, as in the boost converter. However, when the switch is opened the input is no longer connected to the supply (as is the situation in the buck converter), and therefore the constraint that the output must be larger than the input is removed. The resultant voltage across the capacitor is simply related to the amount of energy stored in the inductor, and the current required by the load resistor. If one wishes to increase the output voltage then the switch is closed for a longer period of time, and it the voltage is to be decreased then the switch is closed for a shorter period of time. Remark 5.12 One can see from the above explanation that the operation of this circuit has characteristics of both the buck and the boost converter. Reiterating, the energy storage in the inductor is from the boost converter (when the switch is closed), and the disconnection of the input from the output when the switch is open is the same as the buck converter. One can therefore identify a buck–boost topology by looking for the fact that the inductor is placed across the supply and disconnected from the load during the
5.3 Taxonomy of Switch Mode Converters
id
137
SW +
Vd
vL L
iL
C
Vo
RL
io Figure 5.5: Single switch Buck–boost converter circuit.
energy storage phase when the switch is closed, and the inductor is disconnected from the supply and placed in the output circuit when the switch is opened. Remark 5.13 One should note that the voltages one can obtain from the buck– boost converter are related to the relationship between the load, the capacitor, and the inductor. Remark 5.14 The limitations on the performance of the buck-boost converter are very similar to those of the buck and the boost. In addition the presence of two diodes in the circulating current path can lead to inefficiency (even when Schottky diodes are used).
5.3.4
C´ uk Converters
This converters peculiar name arises from its inventor (pronounced Ch-ooo-k). It was arrived at by essentially forming a dual of the buck–boost converter. Similarly to the buck–boost converter it is capable of producing voltages that are larger and smaller than the input voltage, and the output voltage is negative relative to the same reference as the input voltage. One fundamental difference is that the primary storage element is a capacitor, as opposed to the inductor in the buck–boost converter. Figure 5.6 shows a basic C´ uk converter. This circuit is slightly more difficult to understand. Therefore we shall consider two situations: one when the switch is closed, and the other when the switch is open. Consider Figure 5.7, which shows the situation when the switch is open. For the sake of the discussion it shall be assumed that the current in the inductors is continuous. In this case the capacitor is charged by the current iL1 flowing from the input. The current iL2 flowing on the load side of the circuit continues to deliver energy to the load. Note that both iL1 and iL2 would be decreasing under this circuit condition.
138
Fundamental Topologies
iL
+ Vd
L1 vL 1
iL
vC 1 + -
1
-
2
L2 vL
-
C1
+
2
SW
Vo
C
RL
io
Figure 5.6: The C´ uk converter. The input current, iL1 , would be decreasing because the capacitor voltage is greater than the input voltage. This can be deduced from the fact that: v c1 = V d + V o
(5.1)
Remark 5.15 Equation (5.1) results from the fact that the average voltage across the inductors in the circuit must ve zero under steady state conditions – the total volt-seconds change across an inductor must be zero over a complete switching cycle under steady state conditions.
iL
1
+ Vd
L1 vL
1
iL
vC 1 + -
-
2
-
L2 vL
2
+ C
Vo
RL
io
Diode is short circuit
Figure 5.7: C´ uk converter with the switch open. Let us consider the situation when the switch is closed. The circuit under this condition is shown in Figure 5.8. Clearly the diode is reverse biased under this condition, and the input inductor, L1 is storing energy with the input voltage appearing across it. The current, iL2 is also flowing through the switch. This current to will be increasing with the capacitor voltage driving it. Therefore, the energy that has been stored in the capacitor is being transferred to the load. Remark 5.16 The important point to note about the operation of the C´ uk converter is that the capacitor C1 is the element that is actually transferring the
5.3 Taxonomy of Switch Mode Converters
iL
1
+ Vd
L1 vL
1
i L2
vC 1 + -
-
C1
139
-
L2 vL
2
+ C2
Vo
RL
io
Switch is closed circuit
Figure 5.8: C´ uk converter with the switch closed. energy to the output (and not the inductor as in the other converters that we have looked at). The inductors in the circuit are essentially performing a filtering function on the input currents. Remark 5.17 Examination of Figures 5.7 and 5.8 indicate that the switch simply transfers the capacitor from the input where it receives energy from the supply, to across the load where it supplies energy to the load. Remark 5.18 The capacitor in the C´ uk converter has to be able to handle high ripple currents.
5.3.5
Full Bridge Converters
This is the most complex of the converters, in terms of the number of semiconductor components, that we shall look at. It is also the most versatile, in that it can find application in everything from SMCs to dc-to-ac drives. We shall only be considering the former of these two applications. Figure 5.9 shows a conceptual diagram of the full bridge converter circuit. Notice that it has a total of eight semiconductors, with four of them being unidirectional switches. The application of a full bridge circuit depends on the control applied to the bridge. One of the most important properties of the full bridge is that it operates in all four quadrants of the io vo plane. This means that the converter can produce positive and negative output voltage and positive and negative current. The previous converters could only operate in one quadrant (positive or negative voltage, and only positive current). This fact also means that the full bridge converter can accept a dc input and produce an ac output (this mode of operation is known as inversion, and will not be discussed further at this stage). One can see from Figure 5.9 that the switches have diodes in parallel with them. This acknowledges the fact that the switches shown in the diagram are considered to be constructed of a technology that only conducts current in one direction. It also means that if a switch is closed and the current is in the reverse direction then the current will flow through the diode and not through the switch.
140
Fundamental Topologies Leg A
Leg B DC machine load
SWA+
DA+
SWB +
DB +
La i0
Vd
v 0 = v AN - v BN
v AN SWA-
Ra ea
DA-
SWB-
DB- v BN
+ -
N
Figure 5.9: Full bridge converter.
There are two main switching strategies that can be adopted using the full bridge inverter: • Bipolar switching. • Unipolar switching. Bipolar switching is the name given to the switching strategy when the A+ and B− are switched together, and the B+ and A− are switched together. Therefore the voltage applied to the load is ±Vd . There are no other voltages that can be applied. One can deduce that it the switching is such that 50% of the time the A+, B− is in force, and the remainder of the time the B+, A− state in in force, then the average voltage across the load is zero. By varying the switching around this the voltage can be varied from zero to Vd (when only A+, B− are in force) to −Vd (when only B+, A− are in force). Remark 5.19 The full bridge converter can only produce output voltages that are in the range of −Vd ≤ vo ≤ Vd . Unipolar switching, on the other hand, exploits another degree of freedom available in the full bridge to gain a lower current ripple in the output. One can also switch two devices in different legs but on the same rail. For example, one could switch the A+, B+ devices. This effectively places zero volts on the load, and allows the current to freewheel through one of the switches and the diode parallelling the other device. The mode of operation clearly changes the rate of change the current as compared to the bipolar switching mode.
5.4 Basic Analysis of Switch Mode Converters
5.4
141
Basic Analysis of Switch Mode Converters
In this section we shall do some basic analysis of the converters mentioned in the previous section. Before carrying out this analysis we shall firstly define the concept of duty cycle, also known as mark-space ratio. We shall also introduce the concept behind the development of the switching waveforms.
5.4.1
Duty Cycle
Consider Figure 5.10, which shows a switching waveform. The duty cycle of this waveform is defined as: D=
ton Ts
(5.2)
Considering the waveform in Figure 5.10 we can work out the average voltage SW
Vd
R
v0
v0
ON
OFF
Vd
V0
0
t t off
t on Ts
Figure 5.10: Definition of the terms related to duty cycle.
142
Fundamental Topologies produced: vave =
1 Ts
1 = Ts
Ts
vo dt 0
ton
Vd dt + 0
Ts
0dt ton
ton Vd Ts = DVd =
(5.3)
From (5.3) one can see that the average voltage is directly proportional to the duty cycle of the switching.
5.4.2
Basic PWM Generator
In the previous section we defined the concept of a duty cycle. The next question that arises is: “how does one generate the switched output in a manner that a desired average output voltage is produced?”. The simplest technique, that actually arose from the days of complete analogue PWM generators is to use a sawtooth or triangular waveform. This concept is shown schematically in Figure 5.11. One can see from Figure 5.11 that the slope of the sawtooth is: vst m= Ts Therefore one can say that: Vcontrol (5.4) ton = m Vcontrol = Ts (5.5) vst One can see from (5.5) that: D=
Vcontrol vst
and hence: vave = DVd = or
Vcontrol Vd vst
(5.6)
(5.7)
vave ∝ Vcontrol where the constant of proportionally is Vd /vst . Remark 5.20 Note that if Vd = vst then the constant of proportionality is one. Therefore the average output voltage is the same as the control voltage. In most PWM generators this is not the situation. The circuitry required to perform the PWM generation using the waveforms of Figure 5.11 is very simple. Figure 5.12 shows a conceptual diagram of the required circuit. Remark 5.21 The PWM generator circuit shown in Figure 5.12 is usually implemented using analogue circuitry. This can be done at a very low cost. It can also be implemented in a digital system.
5.4 Basic Analysis of Switch Mode Converters
143
Sawtooth waveform
v st
Vcontrol
ON
OFF
ton
toff
Vd
Ts
Figure 5.11: Waveforms in a sawtooth based PWM modulator.
Vdesired
+ Amplifier
V0
-
v control
+ Comparator
-
Sawtooth waveform Figure 5.12: Simple PWM generator circuit.
Switch control
144
Fundamental Topologies
5.4.3
Simplified Analysis of the Buck Converter
In this section we shall carry out a simplified analysis of the characteristics of the buck converter. The assumptions used are detailed later. However, one observation that can be made about the circuit is that the inductor/capacitor combination in Figure 5.2 effectively form a low pass filter. This filter filters out the harmonics in the switching waveform, which is of the form of Figure 5.10. For the filtering action to be effective, the -3db roll-off of the LC circuit has to be substantially lower than the switching frequency of the inverter (i.e. fs = 1/Ts ). This means that the effect of the switching on the output current is largely eliminated, and the switching current is essentially dc. This fact forms the basis of one of the assumptions made later. As mentioned Section 5.3.1 the buck converter can operate in continuous conduction mode or discontinuous mode. This term refers to the current in the inductor. In continuous mode, the current in the inductor never goes to zero, whereas in discontinuous mode the current will go to zero at some point in the switching time Ts . Let us now consider each of these modes separately. 5.4.3.1
Continuous Conduction Mode
We shall assume that the circuit is in steady state for the development of the expressions. If the circuit is in steady state then we immediately know that the sum of the volt-seconds applied across the inductor when the switch is closed plus the volt-seconds when the switch is open must equal zero.2 The waveforms and circuit configurations for the buck converter are shown in Figure 5.13. Note 5.1 The following analysis assumes that the capacitor voltage essentially remains constant over a complete PWM cycle. This in turn implies that the value of the capacitor is large enough that it can absorb the charge supplied from the inductor current without significant voltage rise. Remark 5.22 A consequence of the previous note is that over a complete cycle of the PWM the average current supplied by the inductor must be equal to the average current supplied to the load. If this were not the case then the capacitor voltage would continually rise or fall over time as the circuit operated, thereby violating the steady state assumption. Notation 5.1 The capitalised currents and voltages in Figure 5.13 and the following analysis refer to the average values of the currents, and not the instantaneous values. As stated above the average inductor voltage over the complete PWM interval has to be zero for steady state operation. Therefore, by inspection of the inductor voltage plot in Figure 5.13 we can say that the volt-seconds applied must be zero.3 Therefore: (Vd − Vo )ton = Vo (Ts − ton ) linear voltage gain
(5.8)
This expression can be rearranged to give: is true because λ = vdt, and the flux in the inductor must not increase over a complete period for the circuit to be in steady state. 3 Note the dc output voltage assumption appears in Figure 5.13 as the constant voltages over each of the switching intervals. 2 This
5.4 Basic Analysis of Switch Mode Converters
145
vL Vd -Vo
0
A t B
-V0 iL
Ts
IL
Io
0
t t on
t off
iL
iL
io Vd
+
L vL
-
io
C
Vo
Vd
+
L vL
-
C
Vo
Figure 5.13: Currents and circuit configurations for a buck converter. Vo ton = = D (duty cycle) Vd Ts
(5.9)
Remark 5.23 Keeping in mind the assumptions in the analysis, this (5.9) means that the output voltage varies linearly with the duty cycle, given a fixed input voltage. Remark 5.24 One could also obtain the relationship of (5.9) by averaging the vo voltage shown in Figure 5.10, realising that this voltage waveform is the form of the input waveform. The output is then obtained since the average input voltage has to be the same as the average output voltage for steady state to exist in the circuit (else the current through the inductor would be increasing or decreasing over a number of cycles.) By using conservation of energy one can also calculate the ratio of the input and output currents. Assuming that the circuit is essentially lossless, then we can say: (5.10) Pd = Po This can be clearly expanded as:
or
Vd Id = Vo Io
(5.11)
Io Vd 1 = = Id Vo D
(5.12)
Remark 5.25 As can be seen from (5.12) the buck converter acts the same as an electronic transformer when in continuous current mode.
146
Fundamental Topologies Remark 5.26 Even though the current iL is fairly smooth, the input current id is jumping from some peak value to zero every time the switch is opened. Depending on the source for the converter, the input may have to be filtered to smooth out these current fluctuations. 5.4.3.2
Boundary between Continuous and Discontinuous Conduction
In this section we shall establish the condition for the converter to move from continuous to discontinuous conduction. Discontinuous conduction occurs when the current iL goes to zero at or before the end of the control period. Consider the current waveform shown in Figure 5.14. One can formally work out that the average value of such a waveform is 12 iLpeak , which is also obvious using geometric arguments based on the fact that the waveform is made up of triangles. Therefore one can derive the following expression for the minimum average current that must be flowing in the circuit to sustain continuous conduction: ILB =
current required for continuous inductor current
1 1 DTs iL [(Vd − Vo )ton ] = (Vd − Vo ) = IoB = 2 peak 2L 2L
(5.13)
where ILB is the minimum average inductor current, and IoB the minimum output current value (remember the two are the same given the steady state assumption). Equation (5.13) can be further manipulated using the expression (5.9) to eliminate V0 , and assuming that Vd is constant, giving: ILB = IoB =
Ts Vd (D − D2 ) 2L
(5.14)
On can differentiate (5.14) to find the duty cycle for the maximum ILB for given Vd , Ts , D, and L: dILB Ts Vd = (1 − 2D) (5.15) dD 2L Clearly from (5.15), the maximum value occurs at D = that value is: Ts Vd ILBmax = 8L
1 2
Therefore using (5.14) (5.16)
Remark 5.27 Equation (5.14) defines the value of the average current required in the inductor to just allow continuous conduction. Therefore, the maximum value for this average current, which is the value defined in (5.16) occurs when the duty cycle is 1/2. This means that the onset of discontinuous current operation occurs first if the duty cycle is around this value (which implies that the output voltage is 12 Vd ), as the load current is decreased (i.e. one increases the load resistance value so that less current can flow). Remark 5.28 The previous remark implies that one can design the converter so that the minimum load current is larger than ILBmax in order to ensure continuous conduction (assuming that continuous conduction is the desired operation mode). Note that one of the main design parameters is the inductance value
5.4 Basic Analysis of Switch Mode Converters
iL
147
Current is zero here
peak
v L = (Vd -Vo )
iL
0
t I LB = I oB
-Vo t off
t on Ts
Figure 5.14: Current waveform at the point of discontinuous current in the inductor. itself. Another point to note is that the input voltage is a parameter in (5.16), so if this voltage varies over a range then this must be taken into consideration. Finally, the load of the system will define the load current required, and via the other considerations mentioned above it will define the parameters of the converter. There are two main cases to investigate in relation to discontinuous current – the constant Vd case and the constant Vo case. Let us now consider each of these. 5.4.3.2.1 Discontinuous Current with Constant Vd . In many applications the input voltage remains constant, and only the output voltage is varied. We are interested in what the voltage gain of the inverter is under the condition of discontinuous current. Note that we found that with continuous current the voltage gain of the converter was D, and hence it operated linearly. However, as we shall see if the converter operates in discontinuous mode then the voltage gain of the converter becomes non-linear. The following discussion is with reference to Figure 5.15. In order to calculate the voltage conversion ratio, we firstly start by using the volt-seconds condition – i.e. the total volt-seconds over a control interval must be zero for steady state operation: (Vd − Vo )DTs + (−Vo ∆1 Ts ) = 0
(5.17)
which leads to the following relationship for the voltage ratio: Vo D = Vd D + ∆1
(5.18)
The next relationship to establish is the value of the average current in the inductor under this condition depicted in Figure 5.15. We shall use a technique
voltage conversion ratio
148
Fundamental Topologies
iL
Current is zero here
peak
v L = (Vd -Vo )
I L = Io
iL
0
t
-Vo D1Ts
DTs
D2Ts
Ts Figure 5.15: Current waveform for a buck converter with discontinuous current. similar to that used for (5.13). We must firstly get an expression for the peak inductor current. It can be seen from Figure 5.15 that iLpeak can be written as: iLpeak =
Vo ∆1 Ts L
We are now a position to calculate the average inductor current over a period. This is most easily carried out by calculating the area under the iL current in Figure 5.15 for a complete control cycle and dividing by Ts . Therefore we can write: Io =
1 2 iLpeak (DTs
+ ∆1 Ts )
Ts
1 iL (D + ∆1 ) 2 peak 1 Vo ∆1 Ts = (D + ∆1 ) 2 L =
average inductor current discontinuous mode
(5.19) (5.20) (5.21)
Substituting for Vo using (5.18) one can manipulate (5.21) to give: Io =
1 Ts Vd D∆1 2 L
(5.22)
Clearly this can also be expressed in terms of the minimum load current that results in discontinuous conduction using (5.16) to give: Io = 4ILBmax D∆1
(5.23)
We can now find an expression for ∆1 in (5.18) by rearranging (5.23) to give: ∆1 =
Io 4ILBmax D
(5.24)
5.4 Basic Analysis of Switch Mode Converters
149
Substituting (5.24) into (5.18) and rearranging we get the final expression for the voltage ratio: Vo D2 = (5.25) Io Vd D2 + 1 4
ILBmax
Remark 5.29 The most notable feature of (5.25) is that the voltage ratio is now non-linear. In other words there is a non-linear gain through the converter. Clearly this complicates the design of the control. Furthermore, the onset of nonlinearity with the onset of discontinuous current would make the control even more difficult if the converter moved from continuous current to discontinuous current operation. Figure 5.16 is a plot of (5.25) in the discontinuous region, and (5.9) in the continuous region. Remark 5.30 As noted in the previous remark, the voltage ratio to duty cycle relationship for discontinuous operation can be seen, from Figure 5.16, to be very non-linear .
1
D =10 .
Boundary for onset of discontinuous current
D = 0.9 D = 0.8
0.8
D = 0.7
Vo 0.6 Vd
0.4
D = 0.6
DISCONTINUOUS CURRENT REGION
D = 0.5
CONTINUOUS CURRENT REGION
D = 0.4 D = 0.3 D = 0.2
0.2
D = 01 .
0
0
0.2
0.4
0.6
0.8
1 Io I LB
1.2
1.4
1.6
D = 0.0 1.8 2
max
Figure 5.16: Voltage ratio of the buck converter for continuous and discontinuous s Vd operation modes and constant Vd . NB. ILBmax = T8L
voltage ratio is now non-linear
150
constant output
Fundamental Topologies
voltage
5.4.3.2.2 Discontinuous Current with Constant Vo . In many applications the output voltage should be kept constant whilst the input voltage varies. An example of this type of application is a traditional switch mode power supply (SMPS), where the power supply should keep a constant voltage output despite variations of the mains supply voltage. If one uses (5.14) and the linear voltage ratio (5.9), one can calculate the value of the current at the edge of continuous current conduction in the inductor. Substituting for Vd in (5.14) one gets: Ts Vo (1 − D) 2L
ILB =
(5.26)
which clearly has a maximum at D = 0, giving: ILBmax =
Ts Vo 2L
(5.27)
Remark 5.31 Note that (5.27) is the expression for ILBmax in terms of Vo whereas the expression (5.14) is in terms of Vd . In (5.27) the assumption is that Vo is constant (held there by the control of D), and Vd is totally variable. Remark 5.32 Operation at D = 0 for a constant finite Vo is a mathematical artifact, since this would imply that Vd = ∞ (given that D = Vo /Vd ). Using (5.26) and (5.27) we can write: ILB = (1 − D)ILBmax
(5.28)
Using (5.18), (5.21), and (5.27) one can write the following expression (note that both (5.18) and (5.21) are valid regardless of the constraint on Vd or Vo ). Now from (5.18) we have: DVd (5.29) Vo = D + ∆1 Substituting into (5.21) one can write: Ts Vd D∆1 2L
Io =
(5.30)
Using (5.27) we can write: Ts ILBmax = 2L Vo
(5.31)
Substituting this into (5.30) we get: Io =
ILBmax Vd D∆1 Vo
(5.32)
Vo Io ILBmax DVd
(5.33)
which can be manipulated to give: ∆1 =
which can be substituted back into (5.18) and manipulated to give: Vo D= Vd
Io ILBmax 1 − VVdo
12 (5.34)
5.4 Basic Analysis of Switch Mode Converters
151
Remark 5.33 As can be seen from (5.34) the relationship between D and Vo /Vd is again highly non-linear. As in the constant Vd case, the control for constant Vo would be much simpler if on maintains operation in the continuous current mode.
1 Vd Vo Vd
0.8
Vo
CONTINUOUS CURRENT REGION
0.6 D 0.4
Vd Vo Vd
DISCONTINUOUS CURRENT REGION
Vo Vd Vo
0.2 Vd
0
Vo
0
0.2
0.4
0.6 Io I LB
= 125 . = 15 . = 2.0 = 3.0 = 4.0
= 5.0
0.8
1
1.2
max
Figure 5.17: Characteristics of the buck converter with constant Vo . s Vo . ILBmax = T2L
NB.
Remark 5.34 The ILBmax in Figure 5.17 is different from that in Figure 5.16. Figure 5.17 shows the inter-relationship between the duty cycle, load current and inverse voltage ratio for the buck converter. The non-linearity in the discontinuous current region of operation is very evident from the figure.
Remark 5.35 Figures 5.16 and 5.17 are actually equivalent. For example, at D = 0.5 in Figure 5.16 VVdo = 0.5 and ILB Io = 1. The corresponding max(D=0.5)
point in Figure 5.17 is
Vd Vo
= 2 (i.e.
Vo Vd
= 0.5), D = 0.5 and
Io ILBmax(D=0)
= 0.5.
152
Fundamental Topologies The latter can be seen from (5.27) and (5.16) as follows. From (5.16): Ts V o Ts Vd Vo = (using Vd = ) 8L D8L D Ts V o = (for D = 0.5) 4L 1 = ILBmax(D=0) 2
ILBmax(D=0.5) =
(5.35) (5.36) (5.37)
Correspondence can be found for all the other points. 5.4.3.3
voltage ripple
Output Ripple
In the analysis thus-far we have assumed that the capacitor is large enough that the voltage at the output does not change substantially. This was an approximation that made the analysis simpler, but in reality is not true. In many applications that ripple at the output is important – for example, in power supply applications many circuits cannot tolerate significant ripple. In order to get a feel for the voltage ripple we shall assume that the current is continuous. A further simplification is that the impedance of the capacitor is very much lower than the load resistance, and therefore we can assume that the ac component of the current ripple all flows into the capacitor, and the average current over a switching interval flows into the resistor. The following analysis is with reference to Figure 5.18. Remark 5.36 One can immediately see from Figure 5.18 that we are assuming that the ripple is small enough to be insignificant compared to the voltage across the inductor – hence the inductor voltages are drawn as piecewise constant. Remark 5.37 One could also carry out a complete circuit analysis for the buck converter and get very precise voltage ripple waveforms. The equations for this are straight forward, but just a little messy. The output voltage ripple expression can be developed using a capacitor charge approach: 1 1 ∆IL Ts ∆Q = (5.38) ∆Vo = C C 2 2 2 The next step is to get an expression for ∆IL . From the definition of the voltage across an inductor we can say the following: ∆IL =
vL ∆t L
(5.39)
Considering the off time, we can carry out the following calculations. If ∆t = toff , and we can write toff = Ts − ton , and ton = DTs (from (5.2)) then we get ∆t = toff = (1 − D)Ts . Using this expression, and the fact that vL = Vo we can write: Vo (1 − D)Ts (5.40) ∆IL = L
5.4 Basic Analysis of Switch Mode Converters
153
vL Ts Vd - vo
0
t -vo
iL
DI L 2
DQ
I L = Io
0
Ts 2
t
vo
Vo
DVo
0
t
Figure 5.18: Output voltage ripple for a buck converter.
154
Fundamental Topologies Substituting this expression into (5.38) we can write the following expression for the voltage ripple: Ts Vo (1 − D)Ts 8C L ∆Vo 1 Ts2 (1 − D) ∴ = Vo 8 LC ∆Vo =
(5.41) (5.42)
This expression can be further manipulated into a form that highlights the filtering requirements of the LC combination. Realising that: fc =
1 √ 2π LC
(5.43)
then (5.42) can be written as: ∆Vo π2 (1 − D) = Vo 2
fc fs
2 (5.44)
where fs = 1/Ts . Remark 5.38 Equation (5.44) emphasises that fact that making the filter pole of the LC filter circuit much smaller than the frequency of the PWM results in a lower output voltage ripple. Remark 5.39 Note that (5.44) indicates that the ripple is independent of the average inductor current (in continuous conduction mode). Therefore, keeping in mind the assumptions made in the analysis, the load on the inverter does not influence the amount of ripple. The most relevant of these assumptions in relation to this issue is that the capacitor impedance is much lower than that of the load. 5.4.3.4
Simulation
One can set up a computer simulation of the buck converter circuit. The particular simulator used for this exercise is the Saber by Analogy. The circuit set up in the simulator is shown in Figure 5.19. The switching device is modelled by a switch which has a very high off resistance, and a very low on resistance. The diodes in the circuit are essentially ideal, in that they have a zero turn on voltage. If the load is set at 100Ω, the switching duty cycle to 0.5, and the switching frequency to 100kHz, then the plot of Figure 5.20 results. Note that this low value of load resistance ensures that the current is continuous in the inductor. The plots shows the initial startup transient (that was missing from the steady state analysis that we have carried out above). Once the transient has died away then the output voltage settles to the 5 Volt level that is predicted from the theory. The inductor current settles to the load current, which is Io = 5/100 = 0.05 Amp. Notice that the capacitor current is essentially zero. If one magnifies the graph it can be seen that the capacitor is absorbing the ac currents resulting from the high frequency switching.
5.4 Basic Analysis of Switch Mode Converters
155
prbit_l4
prbit_l4
BIT STREAM
BIT STREAM
sw1_l4
switch_output_voltage
v_o
100
pwld
pwld
10
v_dc
sw1_l4
50e-3
100e-6
40000
Figure 5.19: Circuit used in simulation of the buck converter.
(A) : t(s)
(A)
0.2
Capacitor cur
0.0
-0.2
(A) : t(s)
0.4
Inductor cur
(A)
0.2
0.0
-0.2
(V) : t(s)
10.0
v_o
8.0
(V)
6.0 4.0 2.0 0.0 0.0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
0.225
t(s)
Figure 5.20: Waveforms for a buck converter with D = 0.5, RL = 100, and continuous inductor current.
156
Fundamental Topologies Remark 5.40 One can also simulate the performance of the buck converter if there is discontinuous current flow in the inductor. However, the simulation time required for the system to go into steady state is very long due to a problem with the initial transient. This phenomena can be seen in Figure 5.21 which shows the currents for a 50% duty cycle and a load resistance of 40kΩ. Notice that we get an initial LC transient which leaves the capacitor with a charge of approximately 9 Volts (i.e. about twice the applied average voltage of 5 Volt). Once this voltage has appeared on the capacitor it can only dissipate via the load resistor. Therefore the time for the voltage to decay to the steady state value is of the order of 4 to 5 seconds. Remark 5.41 The slow transient that is evident in Figure 5.21 would not occur in a practical discontinuous mode buck converter. It occurs in the example case because the converter control is open loop. In a practical converter the duty cycle is varied depending on the error between the output voltage and the desired output voltage, so as to force the output voltage to the desired.
(A) : t(s)
(A)
0.2
Capacitor cur
0.0 (0.11243, 167.57u)
-0.2
(A) : t(s)
(A)
0.2
Inductor cur
0.0 (0.11243, 70.099u) -0.2
(V) : t(s)
10.0
v_o
8.0
(V)
(0.11243, 8.8035) 6.0 4.0 2.0 0.0 0.0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
0.225
t(s)
Figure 5.21: Initial startup waveforms for a buck converter with D = 0.5, RL = 40kΩ, and discontinuous inductor current.
5.4.4
Simplified Analysis of the Boost Converter
In a manner similar to the analysis of the buck converter we shall also analyse the basic properties of the boost converter. The converter analysed is that shown in Figure 5.3. As with the buck converter there are two cases to consider – the continuous inductor current case, and the discontinuous inductor current case.
5.4 Basic Analysis of Switch Mode Converters 5.4.4.1
157
Continuous Conduction Mode
The following discussion is in relation to Figure 5.22. Using the same approach as with the buck converter, we can say that in steady state that the time integral of the voltage across the inductor over a complete switching period is zero. Therefore, by inspection of Figure 5.22 we can write: Vd ton + (Vd − Vo )toff = 0
(5.45)
Rearranging this gives the voltage ratio of the converter:
boost converter voltage ratio
Vo Ts 1 = = Vd toff 1−D
(5.46)
Assuming a lossless circuit we can say that Pd = Po , and hence: Vd Id = Vo Io
(5.47)
which can be rearranged to give the current ratio of the converter:
boost current ratio
Io = (1 − D) Id
(5.48)
vL Vd
0
A t B
Vd -Vo iL
Ts
IL
0
t t on
t off
iL
iL
io Vd
+
L vL
-
C
io Vo
Vd
+
L vL
-
C
Vo
Figure 5.22: Currents and circuit configurations for a boost converter. Remark 5.42 Equation (5.46) indicates that the voltage ratio goes to infinity if D = 1. This arises from the fact that the steady state assumption means via (5.45) that the output voltage becomes increasingly large as D → 1.
158
Fundamental Topologies Remark 5.43 Equation (5.46) indicates that the voltage ratio is not linear for a boost converter. A plot of the voltage ratio is shown in Figure 5.23. Note the very large increase in the voltage ratio as D → 1. In reality this increase does not occur. The analysis that lead to (5.46) involved ideal components. However, if one includes resistance in the inductors and capacitors, and accounts for the very poor switch utilisation under large duty cycles, then as D → 1, then Vo /Vd → 0, and not ∞. 100 90 80 70 60 Vo 50 Vd
40 30 20 10 0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
D (Duty Cycle)
Figure 5.23: Voltage ratio of a boost converter versus duty cycle.
5.4.4.2
inductor current continuous current boundary
Boundary between Continuous and Discontinuous Conduction
The following discussion is with reference to Figure 5.24. This figure shows the current waveform at the edge of continuous conduction. Following an analysis technique similar to that for the buck converter, we can write that the average value of the inductor current at this boundary is: 1 iL 2 peak 1 Vd = ton 2 L Ts V o = D(1 − D) 2L
ILB =
(5.49) (5.50) (5.51)
5.4 Basic Analysis of Switch Mode Converters
159
Equation (5.51) can be further manipulated by realising that the inductor current and the input current in this converter are the same (i.e. id = iL ). Therefore using (5.48) we can say that Io = (1 − D)IL , and hence: IoB =
iL
Ts Vo D(1 − D)2 2L
(5.52)
output current continuous current boundary
peak
Current is zero here v L = Vd
iL I LB t
0
Vd -Vo t off
t on Ts
Figure 5.24: Current waveform on the edge of continuous current. If we consider that the output voltage of the boost converter is kept constant, then one can differentiate (5.51) and equate to zero to get the value of D = 0.5 for the maximum value of inductor current at the edge of continuous conduction. This value of current is: Ts Vo (5.53) ILBmax = 8L Similarly, one can differentiate (5.52) and equate to zero to get the maximum value of IoB at D = 1/3. The value of IoB is: IoBmax =
Ts Vo 2 Ts Vo = 0.074 27 L L
(5.54)
Both ILB and IoB can be expresses as follows in terms of their maximum values: ILB = 4D(1 − D)ILBmax 27 D(1 − D)2 IoBmax IoB = 4
(5.55) (5.56)
If we normalise (5.51) and (5.52) using (5.53) we can get the plot shown in Figure 5.25.
maximum inductor continuous current boundary maximum output continuous current boundary
160
Fundamental Topologies
I LB
1
max
0.9 I LB
0.8 0.7 I oB
0.6
max
= 0.59I LB
max
I I LB
0.5 max
0.4
I oB
0.3 0.2 0.1 0
0
0.1
0.2
0.3 1 3
0.4
0.5
0.6
0.7
0.8
0.9
1
D
Figure 5.25: Plot of the normalised continuous current boundary for the boost converter (Vo constant).
5.4 Basic Analysis of Switch Mode Converters
161
Remark 5.44 Figure 5.25 can be interpreted in the following way. If the current in the inductor is less than ILB then the converter will begin to operate with discontinuous inductor current. This translates to the output current being less than IoB , since the inductor current is not the output current for this type of converter. Notice that the largest value of the continuous output current boundary occurs at D = 0.33, which does not correspond to the point where the largest value of the continuous inductor current boundary occurs. This is due to the fact that the inductor current does not linearly relate to the output current. Remark 5.45 Figure indicates that for continuous current flow in the inductor, either keep the inductor current above ILB , or the output current above IoB . If the output is above IoB , then IL is above ILB , and vice-versa. 5.4.4.2.1 Discontinuous Current with Constant Vd . We shall assume that Vd and D remain constant as the output load varies. Under normal operating conditions there would be a controller that would vary D so as to maintain Vo constant despite load variations. However, the above assumptions allow an easier understanding of the discontinuous current condition. The following discussion is with reference to Figure 5.26 which shows the current under the discontinuous current condition.
iL
Current is zero here
peak
v L = Vd
IL
iL
0
t
Vd -Vo D1Ts
DTs
D2Ts
Ts
Figure 5.26: Current waveforms for the boost converter with discontinuous current. The integral of the voltage over one control interval must be equal to zero for the circuit to be in steady state. Therefore we can write the following equation: Vd DTs + (Vd − Vo )∆1 Ts = 0 Vo ∆1 + D ∴ = Vd ∆1
(5.57) (5.58)
discontinuous voltage ratio
162
Fundamental Topologies Again using the fact that the converter is assumed to be lossless, then we can say Pd = Po , and hence the current ratio under discontinuous operation is: Io ∆1 (5.59) = Id ∆1 + D If we consider Figure 5.26, and using the fact that the current waveform can be broken down into a number of triangles, we can calculate the average input current. The peak current is: Vd DTs L and hence the average input current can be deduced to be: iLpeak =
discontinuous average input current
Vd DTs (D + ∆1 ) 2L Using (5.59) one can write the average output current expression as: Ts Vd Io = D∆1 2L Id =
discontinuous average output current
(5.60)
(5.61)
(5.62)
We can use (5.58), (5.62) and (5.54) to get an expression for the duty cycle in terms of the voltage ratio and the output current. From (5.54) we can write: Ts 27 = IoBmax L 2Vo
(5.63)
and from (5.58) one can write: ∆1 =
discontinuous duty cycle
Vo Vd
D −1
(5.64)
Substituting both of these into (5.62) and manipulating one can get the expression: Io 4 Vo Vo D= −1 (5.65) 27 Vd Vd IoBmax Using (5.65) we can develop a plot of D versus Io /IoBmax for various Vo /Vd . The normal operating mode would be that Vo is constant, and Vd is varying. The development of this plot is slightly complicated due to the fact that the Io /IoBmax for discontinuous current is a function of the duty cycle. Using (5.56) and (5.65) it is possible to get the following expression for the limit on the duty cycle for discontinuous conduction, for a given value of Vd /Vo : 2 1 1 −4 2 − 1 (1− 2 − 1 (1− 1 ) ± 1 x x x x) Dlim = (5.66) 2 where x = VVdo . The negative of the two solutions gives a value of D in the valid range of 0 → 1. This sets the limit on the D values, and therefore a limit on the Io /IoBmax range via (5.56). The characteristics of the boost converter with a constant Vo are shown in Figure 5.27. Remark 5.46 One can see from Figure 5.27 that the duty cycle has a highly non-linear relationship to the output current in the discontinuous region of operation. Once outside this region the duty cycle is constant for a particular voltage ratio output.
discontinuous current ratio
5.4 Basic Analysis of Switch Mode Converters
163
1
Vd Vo
0.9
Vd
0.8
Vo
0.7
= 0.25
CONTINUOUS CURRENT REGION Vd
0.6
Vo
D 0.5
= 0.5
DISCONTINUOUS CURRENT REGION
0.4
Vd
0.3
Vo
0.2
Vd Vo
0.1 0
= 0.1
0
0.2
0.4
0.6 Io I oB
0.8
1
= 0.75 = 0.9
1.2
max
Figure 5.27: Duty cycle versus normalised output current for the boost converter with constant Vo .
164
Fundamental Topologies 5.4.4.3
Simulation
To complete this section on the boost converter we shall construct a simulation of the circuit shown in Figure 5.28. The circuit simulated has the switch output switch closed, therefore the load resistance is approximately 100Ω. The voltage output of the circuit, inductor current, load current, and energy stored in the output capacitor and with a 50% duty cycle is shown in Figure 5.29. Notice that the output voltage is 2Vd , as one would predict from (5.46). After the initial startup transient the energy in the capacitor settles to a dc value, indicating that the circuit is now in steady state. The inductor current is essentially constant, which means that the current being pulled from the supply is very close to constant. The effect of applying several different duty cycles when there is continuous conduction is shown in Figure 5.30. Again the simulation output conforms almost exactly to the predicted values of the output using (5.46). prbit_l4 BIT STREAM
prbit_l4 BIT STREAM
v_dc
10
100
sw1_l4
50e-3
v_o
sw1_l4
pwld
100e-6
40000
Figure 5.28: Boost converter simulated using Saber .
5.4.5
buck-boost ratio
voltage
buck-boost current ratio
A Brief Look at the Buck-Boost Converter
We shall not carry out a complete analysis of the buck-boost converter. We can consider the buck-boost converter can be considered to be a cascade of a buck converter and a boost converter. Therefore, assuming that both converters are operated with the same duty cycle, that the current conduction is continuous, then the output voltage ratio is simply the cascade of the two expressions already derived for the buck and boost converters: D Vo = Vd 1−D
(5.67)
As with the previous converters, if we use the lossless converter assumption we can get the current ratio for the buck-boost converter as: Io 1−D = ID D
(5.68)
5.4 Basic Analysis of Switch Mode Converters
165
(J) : t(s) 0.04
(J)
Cap energy 0.02
0.0
(A) : t(s)
(A)
0.4
I_o
0.2
0.0
(A) : t(s)
0.8 Inductor cur
(A)
0.6 0.4 0.2 0.0
(V) : t(s)
(V)
40.0
v_o
20.0
0.0 0.0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
0.22
t(s)
Figure 5.29: Simulated waveforms for a boost converter with D = 0.5 and continuous current.
(V) : t(s) 60.0
v_o;D=0.5
v_o;D=0.8 50.0 v_o;D=0.2
(V)
40.0
30.0
20.0
10.0
0.0 0.0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
0.225
t(s)
Figure 5.30: Output of a boost converter in continuous current mode with several different duty cycles.
166
Fundamental Topologies Equation (5.67) can easily be shown to hold for the single switch version of the converter as in Figure 5.5. The situation with discontinuous current is more complex, and cannot be considered to be a cascade of the individual converters under this condition.
5.4.6
A Brief Analysis of the C´ uk Converter
The following analysis is with reference to Figures 5.6, 5.31, 5.7 and 5.8. It is assumed in the following analysis that the voltage on the capacitor VC1 is constant. This implies that the capacitor is fairly large. vL
1
Vd
ON
0
t OFF
Vd -VC = -Vo 1
vL
2
VC -Vo 1
ON
0
t
OFF -Vo
iL
1
IL
1
0
t
iL
2
IL
2
0
t (1 - D )Ts (= t on )
DTs (= t off )
Figure 5.31: Steady state currents and voltages in a C´ uk converter. Under the constant VC1 and steady state operation assumptions, the integral of the voltages across the inductors must be zero. Therefore we can write: Vd DTs + (Vd − VC1 )(1 − D)Ts = 0 ∴ V C1
1 Vd (for L1 ) = 1−D
(5.69) (5.70)
5.4 Basic Analysis of Switch Mode Converters
167
and (VC1 − Vo )DTs + (−Vo )(1 − D)Ts = 0 1 ∴ VC1 = Vo (for L2 ) D
(5.71) (5.72)
Using (5.70) and (5.72) we can write: Vo D = Vd 1−D
C´ uk voltage ratio (5.73)
As with the previous converter analysis, if we assume that the converter is lossless, then we can develop the current ratio: Io 1−D = Id D
(5.74)
Remark 5.47 Equations (5.73) and (5.74) are the same as those for the buckboost converter. One can calculate the current and voltage ratios using an alternate technique based on the charge transferred by the capacitor. This technique is illuminating in that it emphasises the fact that it is the capacitor that is storing the energy that is being transferred from the source to the load. It shall be assumed that the inductors, L1 and L2 , are large enough that the ripple in the currents can be ignored – i.e. iL1 = IL1 and iL2 − IL2 . If the circuit is in steady state then the total charge delivered to the capacitor over a complete control interval is zero. This can be expressed mathematically as follows: IL1 (1 − D)Ts − IL2 DTs = 0 IL Io 1−D ∴ 2 = = IL1 Id D
(5.75) (5.76)
Using the lossless argument once again (Po = Pd ), then one gets: Vo D = Vd 1−D
5.4.7
(5.77)
Full Bridge dc-dc Converter
We shall now consider the calculation of the output voltage ratio and currents for the full bridge dc-dc converter. As was previously noted, this converter is capable of producing both ac and dc outputs, but in this analysis we shall only consider dc output. The following discussion is with respect to Figure 5.9. Assuming that the switches are switched in such a way that the current is continuous in the load, then the output voltage is only a function of the switch states. Let us consider Leg A in Figure 5.9. If switch SWA+ is closed and if io is positive then the current will flow through SWA+ . If io is negative then the current will flow through DA+ . In either case, the Leg A load connection is connected to the positive rail of the dc supply. Therefore: vAN = Vd (for SWA+ on and SWA− off)
(5.78)
C´ uk current ratio
168
Fundamental Topologies Remark 5.48 The assumption stated above essentially means that one of the switches in a leg is switched on at a particular instant of time. As we shall see later, if both switches are open in a leg, then the output voltage is no longer a function of the switch states, but depends on the direction of the load current from the leg. The alternative switching position for Leg A is SWA+ off and SWA− on. In this case a positive current flows through DA− and a negative current through SWA− . Hence in both cases the Leg A load connection is connected to the negative of the supply, which is also the reference point for the voltage measurements. Therefore: (5.79) vAN = 0 (for SWA− on and SWA+ off) Remark 5.49 Expressions (5.78) and (5.79) indicate that the output voltage is dependent only on the status of the switches, and not on the direction of the current. Given Remark 5.49 then the output voltage of Leg A averaged over a complete switching cycle Ts , depends only on the input voltage Vd and the duty ratio of SWA+ . Therefore the average Leg A voltage is: VAN =
Vd ton + 0 · toff = Vd · duty cycle of SWA+ Ts
(5.80)
Similar arguments apply to Leg B. Therefore VBN is: VBN = Vd · duty cycle of SWB+
(5.81)
independent of io . Given VAN and VBN , then we can calculate the output voltage for the converter as follows: (5.82) Vo = VAN − VBN Equation (5.82) is a general expression for the output voltage. It was mentioned in Section 5.3.5 that there are two main strategies for arranging the switching in full bridge converters. We shall now investigate these strategies in detail. 5.4.7.1
Bipolar Switching
This is a switching strategy where the top switch in one leg is closed and the bottom switch in the other leg is closed. Therefore the switches are grouped as diagonal pairs in Figure 5.9. In a manner similar to that shown in Section 5.4.2, the PWM for bipolar switching is implemented conceptually by comparing a reference voltage with a triangular waveform. We can work out the output voltage of the converter with this type of switching with the aid of Figure 5.32. In the bipolar converter the basic algorithm is that when the control voltage is greater than vtri then SWA+ and SWB− are turned on. If the control voltage is less than vtri then SWA− and SWB+ are turned on. The logic behind this switching algorithm, is that the triangular switching waveform can be considered to be a scaled version of the integral of the leg waveform with respect to the
5.4 Basic Analysis of Switch Mode Converters
169
v tri
V$tri
v control
t
A Ts / 2
t1
t1
Ts
v AN Vd
10
01
01
10
10 t
B
v BN Vd
10
01
10
01
10 t
C
vo = v AN - v BN Vd Vo
10
D
01
10
01
10
t
-Vd
I o + ve io
E
Io SWA + D ASWB - D
B+
DA +
SWA +
DB -
SWB -
t
SWA-
I o - ve
SWB +
io
F
t
-I o SWA + SWA-
DA +
SWA +
SWB - SWB +
DB -
SWB -
DADB +
Figure 5.32: Waveforms for a full bridge converter with a bipolar switching strategy.
170
Fundamental Topologies voltage reference point. Therefore, for a particular leg voltage one has to simply find the scaling factor for the control voltage or the triangular wave. From Figure 5.32A we can see that: 1 vtri = Vˆtri Ts t
(5.83)
4
At the switching time t1 one can see that vtri = vcontrol . Substituting this into the above expression we can write: t1 =
vcontrol Ts Vˆtri 4
(5.84)
Again referring to Figure 5.32A we can see that the total on time for Leg A of the inverter is: 1 (5.85) ton = 2t1 + Ts 2 Leg A duty cycle
Leg B duty cycle
We can now use (5.2) to give the duty cycle for the SWA+ and SWB− switch pair: ton 1 vcontrol = D1 = (5.86) 1+ Ts 2 Vˆtri The duty cycle for the SWB+ − SWA− leg (i.e. leg B) is therefore: D2 = (1 − D1 )
(5.87)
Vo = D1 Vd − D2 Vd = (2D1 − 1)Vd
(5.88)
Using (5.82) we can write:
full bridge bipolar output voltage
which becomes, substituting (5.86) : Vo =
Vd vcontrol = kvcontrol Vˆtri
(5.89)
Remark 5.50 Equation 5.89 indicates that the output voltage is linear with respect to the control voltage. This makes the control of the converter fairly simple. Remark 5.51 From Figure 5.32 it can be seen that the voltage across the load is bipolar in nature, hence the name of this switching strategy. It should also be noted that the fact that the voltage is going from positive to negative will result in higher ripple in the output current, as compared to any strategy that keeps the voltage unipolar. Remark 5.52 From (5.88) it can be seen that as the duty cycle D1 is varied from 0 to 1 the output voltage varies from −Vd to Vd . This variation is independent of the direction of the current, although different switching components are responsible for the conduction of the current depending on the current direction. This can be seen from Figure 5.32E and F, where the various conduction devices are shown.
5.4 Basic Analysis of Switch Mode Converters 5.4.7.2
171
Unipolar Switching
An alternative switching strategy to the bipolar strategy is the unipolar strategy. This switching strategy takes into account another degree of freedom as compared to the bipolar strategy. The basic idea of this switching strategy is to keep the voltage across the load unipolar if the desired voltage is unipolar. This is achieved by the voltage switching from Vd to 0. Examination of Figure 5.9 indicates that there are two basic strategies for obtaining unipolar operation. For example, assuming that the current direction is positive, then one can have switch SWB− switched on, and then open and close SWA+ depending on the average voltage that one desires. This would result in the voltage across the load going from Vd with SWA+ closed, and 0 with SWA+ open (and hence SWA− closed). The other strategy is to switch leg B. For example, assuming the same current direction, one could open SWB− (and hence close SWB+ ), the current then circulating through via SWA+ and DB+ . Both of the above switching strategies are employed in the switching algorithm drawn in Figure 5.33. One could use a switching scheme similar to that of the bipolar case, where one has a unipolar control voltage. In this case only one of the two switching patterns could be easily incorporated. This would result in a larger output voltage for unipolar switching as compared to bipolar switching. Both of the switching strategies could be used however, if one has the bipolar control voltage shown in Figure 5.33. The switching times are determined as follows: (5.90) SWA+ closed if: vcontrol > vtri and SWB+ closed if: − vcontrol > vtri i.e. vtri < −vcontrol
(5.91) (5.92)
This switching strategy allows both the positive and negative parts of the triangular waveform to be utilised. The net result of switching using this strategy is shown in Figure 5.33C. As compared to the bipolar strategy, or a unipolar strategy where only one of the switching options are used, the switching frequency has effectively been doubled without actually changing the switching frequency of the switches themselves. Remark 5.53 The effective doubling of the switching frequency means that the ripple in the current using the unipolar strategy is less than the ripple using the bipolar strategy. Examination of the waveforms in Figure 5.32B and C and Figure 5.33B and C indicate that the duty cycles are the same for the unipolar case and the bipolar case (the VAN and VBN waveforms are the same in both cases). Rewriting these for convenience: 1 vcontrol +1 (5.93) D1 = 2 Vˆtri and (5.94) D2 = 1 − D1 Clearly then in this case the output voltage is exactly the same as that of the bipolar case – i.e.:
full bridge duty cycle
full bridge unipolar output voltage
172
Fundamental Topologies
v tri
V$tri
v control
t
A t1
t1
-v control
t1
t1
t1
Ts
v AN Vd
10
00
10
11
00
10
10
11 t
B
v BN Vd
10
00
11
10
10
00
10
11 t
C
vo = v AN - v BN Vd Vo
D
10
2t 1
00
2t 1
10
11
10
00
10
11
t
-Vd
I o + ve DA + SWA + SWB D B-
E
io
Io
t
SWA + SWB -
SWADA-
DB -
SWB -
I o - ve
SWADB -
F
-I o
io
t SWA + SWB -
DA + DB DA-
DA +
SWB -
DB -
Figure 5.33: Waveforms for a full bridge converter with a unipolar switching strategy.
5.4 Basic Analysis of Switch Mode Converters Vo = (2D1 − 1)Vd =
Vd vcontrol Vˆtri
173
(5.95)
Remark 5.54 Because of the effectively higher switching frequency of the unipolar strategy, it is the preferred method of switching for these types of converters.
5.4.8
Comparison of Basic Converter Topologies
In this section we shall attempt to compare the basic converter topologies introduced in this chapter. This comparison is somewhat limited, as there are a great many topologies that fall into these general categories of those introduced, that in particular applications have advantages over others. Nevertheless this somewhat theoretical comparison is beneficial in that it highlights some of the fundamental structural differences between the converters, and in addition introduces some of the metrics used for carrying out comparisons. One of the first points to notice about most of the converter structures that we have looked at is that they produce unipolar output voltages. There is one exception to this – the full bridge converter. In addition to the unipolar operation, all except the full bridge converter can only handle current in one direction; into the load. Therefore the buck, boost, buck-boost and C´ uk converters are said to operate in one quadrant of the io vo operation plane. The full bridge converter on the other hand can operate on all four quadrants of the io vo plane. 5.4.8.1
Switch Utilisation
One of the important metrics of power electronic devices is the switch utilisation. This refers to how well a particular converter topology uses the voltage and current ratings of the semiconductor switches used. If a switch is poorly utilised then a larger semiconductor switch must be used for a given power output for the converter. This corresponds to more expensive switches. In order to calculate the switch utilisation for the previous converters we firstly need a few assumptions: 1. The average current is at its rated value of Io . The ripple in the current can be ignored. 2. The output voltage is ripple free and is at a constant rated value of Vo . 3. The input voltage is allowed to vary and the duty cycle is varied by a control algorithm to keep the output voltage at its fixed rated value. Given these assumptions the peak switch voltage VT and current IT are calculated. The switch peak power rating is then calculated as PT = VT IT . The switch utilisation is then calculated as: Po (5.96) Us = PT where Po = Vo Io . Remark 5.55 The low ripple assumption used in the following analysis implicitly allows one to remove the particular value of inductance used in the circuit from the switch utilisation expressions – i.e. the expressions are circuit value independent. It also serves to simplify the analysis whilst still capturing the essential character of the expressions.
switch utilisation definition
174
Fundamental Topologies Let us now consider the switch utilisation of the generic converter types that we have considered in this chapter. 5.4.8.1.1
Buck Converter
The peak voltage across the switch is: VT = Vd
(5.97)
This can be written in terms of the output voltage using (5.9) allowing the peak switch voltage to be written as: Vo (5.98) D Examination of Figure 5.2 reveals that the peak current through the switch must be the same as the average load current, since when the switch is closed the two currents have to be the same (via the no inductor current ripple assumption). Therefore: IT = Io (5.99) VT =
buck converter switch utilisation
Using these two expressions for VT and IT we can write the expression for the switch rating power: Vo Io (5.100) PT = VT IT = D Therefore: Po Vo Io Us = (5.101) = Vo Io = D PT D 5.4.8.1.2 Boost Converter A similar analysis for the boost converter can also be carried out. Again the basic equations for the voltage ratio, (5.46), and the current ratio, (5.48) can be used. The key to getting the switch utilisation in this case is to realise that the average input current id and the inductor current iL are the same. Since we are assuming that the inductor is large enough that there can be little ripple in the inductor current, then the switch current must also equal the inductor current. The same assumption also means that we can replace the instantaneous currents with their average values (since they will be the same). Therefore id = Id and iL = IL . We can therefore write: IT = Id
(5.102)
Using (5.48) we can relate the Id and Io , therefore we have: Io (5.103) 1−D From Figure 5.3 one can see that the peak voltage across the transistor is the output voltage – i.e.: VT = Vo (5.104) IT = Id =
allowing the switch peak power to be written as: PT = VT IT = boost converter switch utilisation
Vo Io 1−D
(5.105)
and the switch utilisation as: Us =
Po Vo Io =1−D = Vo Io PT 1−D
(5.106)
5.4 Basic Analysis of Switch Mode Converters
175
5.4.8.1.3 Buck-Boost Converter The determination of the switch utilisation for the buck-boost converter is a little more complicated than the previous cases. This complication occurs due to the fact that the average current ID is not the peak current value flowing through the switch device (as was the case in most of the above). This occurs due to the fact that the switch disconnects the input from the output. The waveform for the input current (which is also the switch current in this case) is shown in Figure 5.34. Note that the constant value of the current from 0 to DTs is due to the large inductance assumption. It can be seen that that average input current is: iD DTs ID = = iD D (5.107) Ts and therefore the peak current through the switch is: iD =
ID D
(5.108)
Input current
iD ID
t DTs
(1 - D )Ts
Figure 5.34: The input current into a buck-boost converter with a large input inductance. Using (5.68) and (5.108) we can write: IT = iD =
1 1−D
Io
(5.109)
The maximum voltage across the switch (from Figure 5.5) can be seen to be: VT = Vd + Vo
(5.110)
176
Fundamental Topologies and using (5.67) we can write: VT =
1−D Vo Vo + Vo = D D
(5.111)
Using (5.109) and (5.111) we can now write the peak switch power: PT = VT IT = buck-boost utilisation
switch
1 Vo Io D(1 − D)
(5.112)
and hence the switch utilisation factor is: Us =
Po = D(1 − D) = D − D2 PT
(5.113)
The C´ uk converter has the same switch utilisation as the buck-boost converter. 5.4.8.1.4 Full Bridge Converter When we consider the switch utilisation for the full bridge converter we shall look at SWA+ and then divide the result by four, because there are four switches in this converter. In other words we require fours times the amount of semiconductor material in this converter, and hence we consider then the peak power is divide across these four devices. Remark 5.56 The division of the single switch utilisation is a technique for saying that the converter is using more silicon than other converters. However, it should be noted that each individual switch has to satisfy the peak power prior to being divided by four. From Figure 5.9 it is obvious that the peak voltage across a switch is: VT = Vd
(5.114)
Similarly it is clear that the peak current is the load current: IT = Io
(5.115)
PT = VT IT = Vd Io
(5.116)
Therefore the peak switch power is:
We need to get the output power. Since we have expressed the peak switch power in terms of Vd we need to get the output power in terms of this as well. This can be achieved by using (5.89) in conjunction with (5.86) which allows us to write: (5.117) vcontrol = Vˆtri (2D1 − 1) and hence: Vo = Vd (2D1 − 1)
(5.118)
and therefore the output power is: Po = Vo Io = Vd (2D1 − 1)Io
(5.119)
5.4 Basic Analysis of Switch Mode Converters
177
Therefore the switch utilisation for SWA+ is: USWA+ = full bridge switch utilisation
Po = (2D1 − 1) PT
(5.120)
In order to get the final value we divide then single switch value by four: Us = 0.5D1 − 0.25
(5.121)
The best way to get an overall comparison of the switch utilisation for the various converters is to plot the switch utilisation versus duty cycle for them. This plot is shown in Figure 5.35. Remark 5.57 One can see from Figure 5.35 that the buck-boost converter, the C´ uk and the full bridge converter do not have good switch utilisation as compared to the buck or the boost converter. Therefore, where possible it is better to use these converters, since a lower cost switch can be used for a given application.
1 0.9 Boost
Buck
0.8 0.7 0.6 Po PT 0.5 0.4
Buck-boost and Cuk Full bridge
0.3 0.2 0.1 0
0
0.1
0.2
0.3
0.4
0.5 D
0.6
0.7
0.8
0.9
1
Figure 5.35: Plot of switch utilisation for the common converter types. Remark 5.58 If both higher and lower voltages than the supply are required then one has to use either the buck-boost or the C´ uk converters. A significant advantage of the C´ uk converter is that the front end of the converter looks like that of the conventional boost converter. Therefore it shares the property of this inverter that the input current is reasonable constant, and hence the filtering of the input is significantly simplified as compared to the buck-boost converter where
178
Fundamental Topologies the input (and output) currents are highly discontinuous. Similarly the output current of this converter can also be kept almost constant. A disadvantage of the C´ uk converter is that the capacitor has to have a high ripple current capacity. Remark 5.59 The full bridge converter should only be used if four quadrant operation is required.
5.4.9
Synchronous Rectifiers
In a switching power supply is being used in very low voltage applications the drop of voltage across the rectifier diodes can be significant. This voltage drop obviously results in less efficiency from the converter. In some of the more demanding applications efficiency takes precedence over other considerations. One halfway solution to the efficiency problem is to use of Schottky diodes for the rectifier. These devices have an “on” voltage of approximately 0.2 volt, as compared to the 0.6–0.7 volt of the conventional diode. However, in the very demanding applications this drop is still too much. The solution employed is the use of the so-called synchronous rectifier. This uses a MOSFET instead of the diode. The reader should be aware that a MOSFET has a conventional diode intrinsically built into its structure. This is not the diode that is being used in the synchronous rectifier. The synchronous rectifier uses the fact that a MOSFET is a symmetric structure, and consequently conducts current from the Drain to the Source and vice-versa. This means that when the internal diode is reverse biased the MOSFET is not turned on (thereby operating as a reverse biased diode). But when the diode is forward biased the MOSFET is turned “on”. This effectively shorts out the internal diode since the “on” voltage of a MOSFET is significantly lower than the “on” voltage of the internal diode. This is due to the fact that the MOSFET essentially functions as a resistance when turned “on” hard, and the “on” state resistance of many modern MOSFETs is very very low – of the order of 10−3 mΩ. This principle is shown in Figure 5.36 which shows a conventional boost converter circuit with and without a diode rectifier. One feature in Figure 5.36 is the parallel Schottky diode with the MOSFET. This diode is required to carry the current when the bottom MOSFET turns “off”, and the rectifier MOSFET is “off”. This gap is required so that shoot through from the load cannot occur (and from the supply for the buck converter). The body diode of the MOSFET should not be allowed to carry this current because of the very high reverse recovery time. Remark 5.60 One other advantage of using synchronous rectifiers is that one can make sure that there is continuous conduction under all load conditions. This occurs because the current can flow in either direction through the inductor with a series MOSFET as opposed to a diode.
5.4.10
Resonant and Soft-Switching Converters
These notes will not look at resonant converters in any detail. These types of converters are not in the mainstream of converter technology at this time, and in fact some people think that they are a fad [13]. Nevertheless one should know what they are and what are their limitations.
5.4 Basic Analysis of Switch Mode Converters
+V
+V
(a)
179
Synchronous rectifier
(b)
Figure 5.36: (a) Conventional non-synchronous rectifier based boost converter. (b) Synchronous rectifier based boost converter. A resonant converter is a converter that intentionally has a resonant LC tank circuit as a fundamental part of its operation. This tank circuit is excited by the switching of the converter, so that the resonance is maintained during operation. There are a variety of different topologies to achieve this operation. The reason for having this resonance is that if the switching of the main power devices occurs at the time when the voltage across, or the current through the device is zero. This means that the power dissipated in the device ideally is zero. Consequently it is possible to increase the switching frequency of the converter, without incurring excessive losses in the switching devices. In order to have some idea of the configurations of a resonant converters consider Figures 5.37 and 5.38. Figure 5.37 shows a resonant buck converter that is designed to switch when the current through the switch reaches zero. Figure 5.38 is a resonant buck converter which switches when the voltage is zero across the switch. We shall not look at the details of the operation of these (for details look in [4, 12]), but one can see that both circuits have the extra LC components represented by Cr and Lr . These are the components that represent the resonant circuit that is used to assist the switching of the power devices. Remark 5.61 We shall see that the concepts used in resonant converters are actually very old. These ideas were originally used in forced commutated silicon controlled rectifier (SCR) circuits from as far back as the 1960s. Before considering the pros and cons of resonant converters we need to distinguish between them and the so-called soft switching converters (a name often
180
Fundamental Topologies
SW
Lr
Lf
Io Vd
+
Cr
-
Cf
D
RL
Figure 5.37: A zero current switching (ZCS) resonant buck converter.
Cr Dr
SW
Lr
Lf
Io Vd
+ -
D
Cf
Figure 5.38: A zero voltage switching (ZVS) resonant buck converter.
RL
5.4 Basic Analysis of Switch Mode Converters
181
used in the literature to mean a resonant converter). Soft switched converters are also known as quasi-resonant converters. A resonant converter is one in which the power waveforms (current and voltage) are sinusoidal, and switching occurs when the voltage and/or current go through zero. Therefore the switching losses (ideally) should be zero. The quasi-resonant converter on the other hand is intermediate between the resonant converter and the conventional PWM converter. The circuit of these converters is so arranged that it creates a tank circuit for a portion of the switching period so that the switch transitions are nearly lossless. 5.4.10.1
Why One Should Not Use Resonant Converters
Resonant converters have several problems in practice. The first major one is that the switching frequency is a function of the load. This causes problems in the design of the EMI filters. A more serious problem is that it is common to use the parasitic capacitances as one of the elements in the resonant tank circuit. This makes is virtually impossible to build units that behave the same on the production line. The obvious solution to the problem is to parallel the parasitics with a capacitor that swamps its effects. However, this has the effect of lowering the oscillation frequency of the tank circuit, which is the whole objective of having the resonant converter in the first place. In addition to the above problems, resonant converters still have problems with large line voltage changes, short-circuited or unloaded outputs, and component tolerances in general. They also operate mainly at higher peak transistor currents for the same output power compared to conventional PWM inverters, and in some configurations at larger voltage stresses. 5.4.10.2
switching frequency is a function of the load parasitic capacitances
Why One Should Use Quasi-Resonant Converters
Before discussing the benefits of using these converters it may be beneficial to review the operation of a quasi-resonant converter. Consider Figure 5.39, which is a conceptual diagram of a quasi-resonant forward converter. Notice that the main difference between this converter and that of Figure 6.1 is the addition of the capacitor across the switch. The presence of the capacitor across the switch forms an LC circuit together with the magnetising inductance of the transformer. When the switch is opened, the voltage across the capacitor is zero. The current through the magnetising inductance will continue flowing into the capacitor, and a resonant ring begins. This ring will continue until the voltage on the capacitor falls back to the supply voltage. At this point the voltage on the magnetising inductance will be positive at the dot end of the primary. This will cause the diode rectifier in the secondary to turn on, and the remainder of the energy stored in the magnetising inductance is transferred to the load. One can see that the quasi resonant converter essentially forms a zero voltage switching (ZVS) device, since the voltage across the capacitor cannot change instantaneously when the switch is opened. One must be sure to choose the LC components so that the LC ring is complete before the start of the next control interval. However, this is not too limiting, and there is usually a reasonable range of components that can be chosen.
zero voltage switching
182
Fundamental Topologies
D1
L +
N1
N2
D2
vL
iL
C
RL
Vo
Vd
SW
C SW
Vd
t Switch voltage
Figure 5.39: A quasi-resonant forward converter. Another possible problem is the presence of a charged capacitor across the switching device when it is turned on. However, a few calculations for practical situations show that the energy dissipated in a MOSFET switch due to this is very small. The major advantage of the quasi-resonant converter is the fact that it essentially works the same as the standard hard switched PWM converters, and the switching rate is determined by the PWM controller chip. Therefore the design of the filtering and EMI circuits is greatly simplified compared to frequency wild converters such as many of the pure resonant designs.
Chapter 6
Switch Mode Power Supplies 6.1
Introduction
In the previous chapter we looked at some fundamental topologies for switch mode converters. In this chapter we shall build on this basic information by considering some topologies that are used for commonly available switch mode power supplies (SMPSs). Towards the end of the chapter we shall consider some aspects of the control of these power supplies.
6.2
Isolated Converter Topologies
The converters presented in the previous chapter were all non-isolated converters. However, in practice isolated converters are very common. This is due to the fact that these converters do offer electrical isolation, but more importantly that allow the simple production of a number of voltages that are all electrically isolated. In this section the isolated converters will be related back to the basic topologies of the previous chapter. We do not look at all possible isolated topologies, since there are far too many to do this. Instead we concentrate on the basic types, from which all the others have common features. The fundamental principles of operation are emphasised.
6.2.1
The Forward Converter
Figure 6.1 shows the basic idealised circuit for the forward converter. The forward converter is derived from the buck converter shown in Figure 5.2. The connection between the two converters is not obvious at a first glance. One may recall that the main distinguishing feature of the buck converter is that when the switch is closed the input is connected to the output. In the case of the forward converter this is not literally true due to the isolation of the transformer. However, when the switch is closed the secondary side of the transformer is reflected to the primary, so in effect this connection exists.
simple production of a number of voltages
184
Switch Mode Power Supplies When the switch in the buck converter is opened then the input is disconnected from the output. In the forward converter this occurs due to the fact that the voltage across the transformer reverses (because of the trapped flux in the transformer), and the diode D1 is reversed biased and disconnects the load from the transformer secondary. Remark 6.1 The above-mentioned trapped flux in the magnetising inductance of the transformer is a new problem that does not exist in the conventional buck converter. If one were to operate the forward converter as described in the paragraph above then the switch would be destroyed by the very high voltages created as the flux in the magnetising flux attempts to maintain the current through the open switch.
D1
L +
N1
N2
D2
vL
iL
C
RL
Vo
Vd
SW
Figure 6.1: Basic circuit of the forward converter. practical converter
forward
Figure 6.2 shows a practical forward converter circuit. In this circuit we introduce a third winding to transfer the energy trapped in the magnetising inductance back to the supply. This winding plays no part when the switch is turned on, but when the switch is turned off and the voltage across the magnetising inductance reverses then, due to the turn direction of the third winding, diode D3 turns on and current flows back into the supply. This limits the rate at which the flux collapses in the magnetising inductance, and therefore the voltage induced by this collapse is controlled. The operation of the circuit can be better understood by referring to the equivalent circuit in Figure 6.3. This circuit is based on using the concept of the ideal transformer that does not require any mmf to operate.1 Ignoring the leakage inductances, the flux is stored in the Lm inductance. When the switch is closed current builds up in this inductance, and at the same time current, i1 flows into the transformer. The voltage v1 appears across the magnetising inductance, and this is reflected via the transformer voltage ratio to winding 2 1 The transformer has a magnetic structure with infinite permeability and consequently the coupling between the windings is one. This also implies that the primary winding has infinite inductance.
6.2 Isolated Converter Topologies
185
D1
L
N3 N2
-
vL
+
N1
iL
D2
RL
C
Vo
Vd D3
SW
Figure 6.2: A practical forward converter.
Ideal transformer i3 Ll1
i2
i1
Ll 2
L
D1
N3
Lm
im v 1 N 1
+ N2
D2
vL
iL
C
RL
Vd
v sw
D3
SW
Figure 6.3: Equivalent circuit for a practical forward converter.
Vo
186
influence of leakage inductance
Switch Mode Power Supplies (the secondary). Similarly the current i1 is reflected as i2 in winding 2 via the transformer current ratio. This current then feeds the load via the output LC filter. When the switch is opened then the current im flowing in the magnetising inductance cannot stop instantaneously. As can be seen from the equivalent circuit the current can flow in a loop via the ideal transformer. The dot relationship between the primary and ternary winding means that the voltage Vd appears across the ternary winding. This voltage is reflected to the primary winding voltage as v1 = −Vd . This implies that vsw = 2Vd . Therefore, the presence of the third winding keeps the voltage across the switch to a reasonable and controllable value, and essentially returns the energy trapped in the magnetic field of the magnetising inductance to the supply. The above discussion omitted the influence of the leakage inductance. Unfortunately the presence of leakage disrupts the ideal operation. If we again consider Figure 6.3, we can see that the leakage inductance carries im + i1 , and therefore it would store the energy 12 Ll1 (im + i1 )2 . As with the magnetising current this stored energy will attempt to maintain the current in the same direction. Therefore when the switch is opened a large voltage can be produced across this inductance, which would also result in a high vsw voltage. Even for fairly small values, the voltage produced could result in the destruction of the switch. Remark 6.2 In order to minimise the leakage inductance the primary and ternary winding are often bifilar wound – i.e. they are both wound on the same arm of the transformer. The secondary may not be wound like this as large voltage isolation between the primary and secondary is often very important. Remark 6.3 In order to catch any voltage spikes associated with the leakages one may need some “snubbers” across the switch. Remark 6.4 The wire used for the ternary winding can be much smaller gauge than the secondary winding as it only has to carry the magnetising current of the transformer. Now let us consider the operation of this forward converter in a little more detail. Assuming for the moment that we are dealing with the ideal forward converter as depicted in Figure 6.1, and assuming that the transformer is ideal. If the switch is turned on, then there will be current flowing through the transformer primary, and hence the secondary. Since the voltage ratio of a transformer is: N2 v2 = (6.1) v1 N1 then we can deduce that: vL =
N2 Vd − Vo N1
for 0 < t < ton
(6.2)
which is a positive value, causing iL to increase in value. When the switch is turned off then the diode D1 is reverse biased, effectively disconnecting the transformer from the remainder of the secondary side
6.2 Isolated Converter Topologies
187
circuit. The trapped energy in the filter inductor causes the diode D2 to turn on, allowing current to circulate. In this case the inductor voltage is: vL = −Vo
for ton < t < Ts
(6.3)
which is negative, resulting in a decreasing current in the filter inductor. If one integrates the inductor voltage over one complete period and equate to zero one gets: Vo N2 = D (6.4) Vd N1 Remark 6.5 One can see from (6.4) that the voltage ratio is the same, in principle, as that for the buck converter. However, whilst a buck converter can only produce voltages less than the input voltage, the forward converter can produce voltages that are greater than the input voltage with an appropriate turns ratio for the transformer. As we have previously noted, in a practical forward converter one must account for the energy trapped in the magnetising inductance. Let us now consider how this requirement alters the operational range of the converter output voltages. The following discussion is with reference to Figures 6.3 and 6.4. When v1 Vd
t -
N1 N3
tm
Vd
t off
t on Ts isw
i1
im
t i1 = im
iL
t
Figure 6.4: Current waveforms for a practical forward converter. the switch is closed then: v1 = V d
for 0 < t < ton
(6.5)
forward converter voltage ratio
188
Switch Mode Power Supplies and the current through the magnetising inductance, im , increases at a linear rate (as can be seen in Figure 6.4). When the switch is opened at time ton , the imton must instantaneously keep flowing. This is achieved via the primary coil of the ideal transformer. Note 6.1 The capacity for the magnetising current to flow through the primary of the ideal transformer is due to a property of transformers. The circuitry connected to the secondary winding of the transformer is reflected (via a turns ratio relationship) to the primary. Therefore, the current is actually flowing in the secondary circuit, but reflects in such a way as to create the illusion that it is flowing in the primary. From this point of view Figure 6.3 is a little deceptive. When the switch is opened, as previously mentioned, the voltage induced in winding 2 is such that the diode D1 is reversed biased, thereby disconnecting the secondary circuit. At the same time, diode D3 turns on due to the voltage induced in winding 3. Therefore this winding effectively becomes the secondary under this condition. Under this condition the currents flowing in the circuits are: i1 = −im , i2 = 0 and i3 becomes (from the normal current ratio for an ideal transformer): N1 im (6.6) i3 = N3 During the time tm , when the i3 current flows, the voltage across the transformer primary is: N1 for ton < t < ton + tm (6.7) v1 = − V d N3 since Vd is the voltage across winding 3. When the transformer demagnetises, then im = 0 and v1 = 0. The time can be obtained by realising that the time integral of the voltage across the magnetising inductance must be zero over a complete time period (for steady state operation). Considering Figure 6.4 one can see that: Vd DTs −
Forward converter maximum duty cycle
N1 V d tm = 0 N3 tm N3 ∴ = D Ts N1
(6.8) (6.9)
If the transformer has to be totally demagnetised before the start of the next control interval, then the maximum value of tm /Ts = 1 − D. Therefore the maximum duty cycle, using (6.9) is: N3 Dmax N1 1 = 3 1+ N N1
(1 − Dmax ) =
(6.10)
∴ Dmax
(6.11)
Remark 6.6 Equation (6.11) indicates that the maximum duty cycle is 0.5 if N1 = N3 (a common choice in many designs). 6.2.1.1
Other Forward Converter Topologies
We shall not go into detail into the other forward converter topologies, but shall simply show the basic design and highlight a few pertinent properties. Only a subset of the available of forward converter topologies will be presented.
6.2 Isolated Converter Topologies
189
6.2.1.1.1 Two Switch Converter This topology is shown in Figure 6.5. In this converter each of the switches are turned on and off simultaneously. Consequently each switch only has to stand a maximum voltage of Vd /2. One of the other nice features of the circuit is that the magnetising and leakage currents can flow via the diodes to the supply, thereby eliminating the ternary winding on the transformer, and negating the requirement for snubbing across the switches. A Dmax = 0.5 limitation applies to this converter.
SW1
Vd
N1
N2
Vo
SW2
Figure 6.5: Circuit diagram of a two switch forward converter.
6.2.1.1.2 Push-Pull Converter This topology is shown in Figure 6.6. The salient feature of this topology is the centre tap transformer used. One of the main limitations of the previous forward converters was that the duty cycle was limited to a maximum value of 0.5. This limitation occurred due to the need to demagnetise the transformer prior to the start of the next switching cycle. The push-pull form of the forward converter effectively allows one to get a full duty cycle range, at the cost of a more elaborate transformer and two switching devices. We shall spend a little more time investigating this circuit because a few important concepts can be gleaned from this that are of use in Power Electronics and circuits in general. One can see from Figure 6.6 that only one half of the transformer is active at any one time, since only one of the switches is turned on at any one time. For example, if SW1 is closed then current will flow from the supply via the top half of the primary through SW1 . This will result in a voltage developing across the top half of the secondary winding consistent with the dot convention of the windings. The resultant current flows via diode D1 to the load. If SW2 is closed (then SW1 is open) a similar pattern occurs. In this case the current flows from the source via the bottom half of the primary through SW2 . The dot convention with this half of the primary in relation to the secondary
190
Switch Mode Power Supplies D1
Vd
N1
N2
N1
N2
L
C
RL
Vo
D2
SW1
SW2
Figure 6.6: Push-pull forward converter. means that diode D2 is forward biased (and D1 is reverse biased). Therefore again current flows to the load. The diode arrangement on the secondary is a conventional full wave rectifier circuit. As with the previous cases one ends up with magnetic energy trapped in the magnetising inductance of the primary. In this particular case the other half of the primary winding that is not conducting current when the corresponding switch is closed corresponds to the ternary winding shown in Figure 6.2. The two halves of the primary essentially form an autotransformer. If we operate the circuit so that there is a period of operation when both of the switches are off, then a question that immediately arises is “what happens to the trapped magnetic energy in the core of the transformer?”. This turns out to not be an easy answer in the sense that the solution takes a deal of insight into how transformers work. We shall consider the operation of the circuit if both switches are in the off state using two approaches – the first is the conventional equivalent circuit approach, and the second is based on realising that the total mmf in the circuit cannot change instantaneously. Consider the situation where switch SW1 has been closed and then it has been opened. Switch SW2 is left open. When SW1 was closed then the top half of the secondary transformer would be positive, and consequently the diode D1 is forward biased. We shall assume that the filter inductor L is large enough that the current iL is constant. Hence the current iL flows through D1 . When SW1 is opened then there is flux in the core of the transformer. This flux must be maintained by a current. This current is often called the magnetising current, and it is assumed to flow through a “fictitious” circuit element called the magnetising inductance. This element is usually placed in the primary side of a transformer. From Figure 6.7 one can see that the current flowing through SW1 is composed of two components – the load current (with the appropriate turns ratio) and the magnetising current. Normally the magnetising current is small compared to the load component. We are assuming that the transformer is ideal –
6.2 Isolated Converter Topologies
191
i.e. it does not require any mmf to magnetise it. The magnetising current is flowing through the magnetising inductance to produce the flux that is present in any “real” transformer. When SW1 is opened then we have the situation shown in Figure 6.8. On the primary side of the transformer there are two main effects to consider. The current shown in Figure 6.7 flowing through the leakage inductance of the primary (Ll ) wishes to continue flowing. Therefore a voltage is developed across the leakage in an effort to achieve this. This voltage appears in conjunction with the supply voltage across SW1 – this is voltage vLl +Vd in Figure 6.8. A snubber is often required across the transistors to cope with this voltage spike. Ideal transformer
Vd
N2
Ll
N2 N1
SW1
i L + im
N1
im
iL
Lm Vd
D1
N2
L iL
Vd
N1
N2 N 1
N1
N2 N2 V N1 d
C
RL
Vo
D2
Diode is open circuit.
Figure 6.7: Currents flowing in the push-pull forward converter with SW1 closed. The second salient point on the primary side of the circuit is that the current flowing through the magnetising inductance cannot be changed instantaneously. Therefore a voltage would normally develop across the magnetising inductance in an effort to maintain this current. This voltage has a polarity with the positive on non-dotted terminal of the top half of the transformer. However, this is coupled by the ideal transformer to the secondary. This would produce a positive voltage on the non-dotted terminals of the secondary. Consequently the diode D2 would become forward biased. Diode D1 also remains forward biased as well, meaning that the (constant) iL current splits between D1 and D2 . This then provides a path for the magnetising current to flow. If this circuit was a normal push-pull inverter circuit then the diode across SW2 would turn on and clamp the voltage across the top half of the winding to Vd . However, the presence of the full wave rectifier circuit on the secondary side of the circuit changes this “normal” scenario. One point that is not obvious in Figure 6.8 is why does the current iL split between the two secondary windings? When D2 becomes forward biased why doesn’t D1 become reverse biased? The answer to these questions is that the constant load inductor current prevents this from happening. If D1 attempts
192
Switch Mode Power Supplies Ideal transformer
Vd
Ll
+
vL
iL
l
im
+ SW1
D1
im
v L +Vd
Lm
2
N1
N2
N1
N2 i L
-
N1 N2
L
im
iL
C
RL
Vo
iL
2
+
N1 N2
im
l
D2
Both diodes short circuit
Figure 6.8: Currents flowing in the push-pull forward converter with SW1 and SW2 open. to turn off, then the load current would immediately be diverted into the lower half of the secondary. This would mean that a voltage would be induced in this part of the winding (since a rate of change of flux in the core would result) such that diode D2 would turn off, and D1 would turn on. Therefore the stable situation is that shown in Figure 6.8. Note that due to the dots on the secondary, the iL /2 current in each half of the windings would produce fluxes that cancel each other. Therefore the only component of flux producing current is the magnetising component reflected into the secondary which circulates around the loop comprising the two diodes and the transformer secondaries. Another way of reasoning this is to realise that when SW1 is opened the reflected iL current must become zero. Consequently the effective iL current through the secondary of the transformer must also be zero (else we cannot have zero reflected iL on the primary side). Given that iL is held constant by the filter inductor, the only way that this can be achieved is if there is net zero flux produced by the secondary winding due to iL . This is achieved by D1 and D2 both being on, since this results in flux cancellation in the secondary winding. There is an alternative way of reasoning the splitting of the inductor current between the two secondary windings. This technique is simple, and can be applied to very complex coupled winding situations. For the moment consider the transformer to be ideal – i.e. the magnetising inductance is infinite. With SW1 closed all the current flowing in the primary is reflected into the secondary. In terms of mmf, an ideal transformer does not require any mmf to set up the flux in the core. Therefore we have: N1 i1 + N2 iL = 0
(6.12)
i.e. no net mmf in the transformer. When SW1 opens the net mmf in the core cannot change instantaneously, as this would imply that there is a change in the flux in the core (which has
6.2 Isolated Converter Topologies
193
to remain at zero because it is an ideal transformer). The current in the load inductor is constant, therefore this current must split between the two secondary windings so that the flux produced by one is cancelled by that produced by the other, thereby keeping the flux in the core zero. In terms of mmf, when the switch is opened i1 = 0, therefore the second term in the mmf expression must also be zero. This occurs if the other term is 12 N2 iL + (− 12 N2 iL ), which implies the above-mentioned splitting of the currents. The overall result of D1 and D2 being on simultaneously is that the secondary windings are short circuited. This value is mirrored to the primary, and its voltage will be zero (if D1 and D2 are ideal). It can be shown that the voltage ratio [4] for this converter is: Vo N2 =2 D Vd N1
(6.13)
where 0 < D < 0.5. Therefore, even though the range of the duty cycle is limited to 0.5, the output voltage can achieve values as if the duty cycle has a range from 0 to 1. Remark 6.7 One potential problem with the push-pull converter is that the switches are subject to maximum voltages of 2Vd . For low voltage applications this is of little consequence, but for mains line applications with 240VAC this means that the devices will be subject to minimum voltages of 700V. Therefore, 1000V MOSFETs are required to ensure that there is sufficient over voltage capacity. Remark 6.8 One of the potential problems with the push-pull circuit is that small differences in the timing of the duty cycles of the two switches can lead to offsets in the flux of the transformer. These timing differences can occur because of differences between the turn-on times of the transistors, or differences in the speeds of the firing circuits. Consider Figure 6.9 which shows a typical BH curve for a ferro-magnetic material. As the ideal push-pull circuit operates it normally moves from B1 to B2 via the hysteresis loop shown. If the “on” transistor is driving the flux density to B2 , and its on-time is a little less than the other transistor, then the flux density may not quite get to B2 , but instead only gets to B2a . Therefore, when the other device turns on it will drive the flux density to a value a little higher than B1 , B1a . This process will continue, and the maximum flux density B1a will creep up higher on the BH characteristic. If the process continues then the core will saturate at the higher flux densities and the magnetising inductance of the core will become very small and excessive currents will flow through the transistor that is on when this occurs. This often results in transistor failure. Current mode control is often used to fix this problem. MOSFET transistors also help, as they have a positive temperature coefficient, and as they heat up more of the voltage is dropped across the device, thereby robbing volt seconds from the magnetising inductance. The resistance of the primary also helps via a similar mechanism. Practical Issue 6.1 One very nice feature of the push-pull converter is that both of the transistors are referenced to the same ground rail. This simplifies the drive circuits for transistors as compared to other topologies where one has transistors floating at different voltage levels.
push-pull ratio
voltage
194
Switch Mode Power Supplies
B
Loop with flux imbalance Normal operation loop
B1a B1
H B 2a B2
B1 = B 2
Figure 6.9: Flux imbalance in the push-pull circuit.
6.2.2
The Flyback Converter
The Flyback converter is an isolated converter that is derived from the buckboost converter described in Section 5.3.3 of the previous chapter. Figure 6.10 diagrammatically shows this connection. Recall from Section 5.3.3 that the important properties of the buck-boost were that when the switch is closed it performs similarly to a boost converter, with the input disconnected from the output and the current flowing through an inductor storing energy. When the switch is opened then the energy stored in the inductor is then transferred to the secondary winding, and in the process of doing this the energy storage inductor effectively becomes the filter inductor in the load section of the circuit. This inductor connects the input to the output when the switch is open. If we compare the buck-boost shown in Figure 6.10 with the Flyback converter, then we can see that the magnetising inductance of the transformer carries out the same function as the storage inductor in the traditional circuit. During the phase when the switch is closed current flows through the magnetising inductance. During the time the output circuit is disconnected from the input because the diode is reversed biased. When the switch is opened, the current through the magnetising inductance wishes to keep flowing in the same direction. It therefore produces a positive voltage on the non-dot end of the primary, resulting in a corresponding positive voltage on the non-dot end of the secondary. Consequently the diode in the secondary becomes forward biased, and the magnetising current in the primary is reflected (via the turns ratio) in the secondary. This current flows into the output capacitor. In effect the magnetising inductance in the primary has been reflected into the secondary, and it performs the same function as the filter inductor in the classical buck converter circuit. Now let us consider the operation of the Flyback converter in more detail. Again we shall assume steady state operation, and the output voltage is consid-
6.2 Isolated Converter Topologies
195
Vo N1 Vd
N2
Vo
Vd
SW
Flyback Converter
Buck-Boost Converter
Figure 6.10: Connection between the Buck-Boost and Flyback converter. ered constant. We shall look in some detail at the variation of the flux in the core, since it is the flux that stores the energy that is transferred to the load. One can calculate the flux in an inductor by using Faraday’s Law: N dφ dt 1 t ∴ φ(t) = vL (τ )dτ + φ(0) N 0 vL =
(6.14) (6.15)
In the case when the switch is closed, as shown in Figure 6.11, there is a constant voltage of Vd applied across the magnetising inductance, Lm . The secondary side of the circuit may as well not be there, since the diode in the secondary effectively disconnects the load from the primary. The load current Io is supported by the capacitor. It is therefore important that the capacitor be large enough to support the current and voltage appropriately during the switch “on” period. Equation (6.15) can therefore be written as: φ(t) = φ(0) +
Vd t N1
for 0 < t < ton
(6.16)
and clearly the peak flux in the magnetising inductance at the end of the “on” period is: Vd ton (6.17) φˆ = φ(0) + N1 At the end of the time ton the switch is opened. Because the current flowing in the magnetising inductance cannot change instantaneously, or alternatively the total mmf in the transformer cannot change instantaneously, then a voltage is induced on the secondary (the polarity determined by the dot convention), in such a manner as to turn on the diode in the secondary. The circuit configuration then changes to that shown in Figure 6.12. As can be seen from the figure a voltage of Vo is produced across the secondary so that the diode turns on. The 1 voltage N N2 Vo is produced across the primary, with a polarity that will cause the magnetising current to decrease. Another way to look at this is to realise that the secondary circuit is reflected to the primary by the transformer, and therefore the magnetising current can flow in this reflected circuit.
flyback peak flux
196
Switch Mode Power Supplies
Diode reverse biased iD = 0
im Lm
v1 N 1
N2
Io
RL
C
Vo
Vd
N2 N1
v1 =
N2 N1
Vd
SW
Figure 6.11: Flyback converter with the switch closed.
Diode forward biased iD
N1
im Lm
N 2 Vo
Io
C
RL
Vd
v1 =
N1 N2
Vo
SW open Figure 6.12: Flyback converter with the switch open.
Vo
6.2 Isolated Converter Topologies
197
During the “off” stage of operation, the flux in the transformer core will decrease from the peak value calculated in (6.17). Therefore the time evolution of the flux during this time is again given by applying Faraday’s Law: φ(t) = φˆ −
N1 N2 Vo
(t − ton ) N1 Vo ∴ φ(t) = φˆ − (t − ton ) for ton < t < Ts N2
(6.18) (6.19)
From (6.19) one can deduce, using (6.19) and (6.17), that the flux at the end of the control interval: Vo (Ts − ton ) N2 Vd Vo = φ(0) + ton − (Ts − ton ) N1 N2
φ(Ts ) = φˆ −
flyback flux at Ts
(6.20) (6.21)
We are again assuming that the system is in steady state, therefore the flux at the beginning and end of a control interval must be the same. This means that: φ(Ts ) = φ(0)
(6.22)
which, using (6.21) allows us the write: φ(0) +
Vd Vo ton − (Ts − ton ) = φ(0) N1 N2 Vd Vo ∴ ton = (Ts − ton ) N1 N2
Rearranging this, and using (5.2) we can write: D Vo N2 = Vd N1 1 − D
(6.23) (6.24) flyback voltage ratio (6.25)
Remark 6.9 The voltage ratio in (6.25) is identical to the voltage ratio calculated for the buck-boost converter, as shown in (5.67). The currents flowing in the circuit under the switch “on” and “off” conditions are shown in Figure 6.13 Let us calculate the currents flowing in the Flyback converter. This analysis basically follows the same procedure as the calculation of the magnetising flux. Assume that the current at the beginning of a control interval has an initial value of im (0). Therefore during the ton period the magnetising and switch current is: Vd t for 0 < t < ton (6.26) im (t) = im (0) + Lm As with the flux, the peak magnetising current at the end of the “on” period is: ˆim = im (0) + Vd ton Lm
(6.27)
Remark 6.10 Note that ˆim is also the peak current flowing through the switch.
peak magnetising and switch current
198
Switch Mode Power Supplies
v1 Vd
0 -
N1 N2
t
Vo t off
t on f
Ts
f$ f(0)
t iD
N2 N1
im Io
t
Figure 6.13: The voltage, current and flux in the ideal Flyback Converter.
6.2 Isolated Converter Topologies
199
During the “off” period the switch current is obviously zero. During this time the voltage across the magnetising inductance is of a polarity so that the current decreases. The current during this period is: im (t) = ˆim −
N1 N2 Vo
Lm
(t − ton )
(6.28)
The current in the diode during this period is simply a scaled version of the inductor current (by the transformer turns ratio). i.e.:
N1 N1 N1 ˆ N2 Vo iD (t) = im − im (t) = (t − ton ) (6.29) N2 N2 Lm Using the equations that we have derived it is now possible to get the peak magnetising current in terms of the load current and voltage and the duty cycle. This is an important equation for this type of converter, since the peak magnetising current needs to be known so that saturation of the core can be avoided, and the switches can be sized. The first step is to work out the average expression for the diode current, which is also equal to the average load current (in steady state). Taking the average of (6.29) and rearranging we can get the expression for the peak current in terms of the average load current and the output voltage: N1 V o N2 Io 1 ˆim = N2 + (1 − D)Ts (6.30) N1 (1 − D) 2 Lm The peak voltage across the switch can be seen to be the supply voltage plus the voltage produced by the transformer: vsw = Vd +
N1 Vo N2
(6.31)
which can be written, using (6.25), as: vsw =
6.2.3
Vd (1 − D)
(6.32)
Utilisation of Magnetics
One important factor in the performance of converters is the utilisation of the magnetic material. Converters such as the boost and flyback converter are storing energy in the magnetic field and then transferring this stored energy to the load when the switching device is turned off. A converter such as the forward converter is transferring energy via direct transformer action – the stored energy is a nuisance in that it has to be transferred somewhere when the power device is turned off. Despite this two different modes of operation, both these converter types are only magnetising the core in one direction. The full bridge converter, on the other hand, is really a variant of the forward converter, but it is different in that the core is magnetised on both directions during normal operation. This bidirectional magnetisation has implications on the utilisation of the core material.
flyback diode current
peak switch current
200
Switch Mode Power Supplies One of the main motivations for the use of SMPSs is their low weight and volume. Therefore it is essential that the magnetic material is well utilised to achieve these objectives. Consider Figure 6.14 which shows a typical BH curve for a magnetic material. The flux density Bm is the maximum flux density that can be achieved when the material is saturated. The flux density Br1 is the remnant flux density when the core is not being subject to an mmf. B
Original magnetic material (no air gap)
Bm
Br 1 Br 2
H Magnetic material with air gap
Figure 6.14: Typical BH loop for a magnetic material. Figure 6.15 shows the excitation waveforms for a forward converter with a feedback winding such that N1 = N3 (Figure 6.15(a)), and a full bridge converter (Figure 6.15(b)) with the same primary turns. The voltage v1 is the voltage across the primary winding. We shall assume that both converters are operating with D = 0.5. ∆Bmax is the excursion of the flux density from the average value of the flux density. Note 6.2 It should be noted that the use of a full bridge converter in this mode is entirely artifical. Under a duty cycle of 0.5 the average output voltage of this converter is zero. The output could be used to drive a transformer connected to a rectifier to get a different output voltage. If a modulation strategy using zero voltage application is used then control of the DC output voltage could be obtained. The reason for the artifical D = 0.5 restriction is that this will force the flux in the core (under appropriate start up conditions) to be bidirectional. Remark 6.11 A better converter to use for this example is the push-pull converter. This converter can perform all the functions of the full bridge if a DC output is required, only involves two switches, and can be made to operate with symmetric bidirectional flux in the core of the transformer (with modified firing of the switches using a combination of current control and zero voltage application). Let us consider the expression for the maximum deviation of the flux density away from the average value. We know from Faraday’s Law, (6.14), and the
6.2 Isolated Converter Topologies
201
v1
v1
Vd
Vd
0
t t on
0
t t on
t off
-Vd
t off
-Vd
DB
DB
(DB )max
0
(DB )max
t Ts (=
0
t
1 ) fs Ts (=
(a)
1 ) fs
(b)
Figure 6.15: Core excitation waveforms. (a) forward converter. (b) full bridge converter.
202
Switch Mode Power Supplies relationship φ = BAc , where Ac the area of the core, that flux density can be written as: ton 1 B= v1 dτ + B(0) (6.33) N1 Ac 0 We are interested in the total change in B from whatever initial condition there is. We shall call this ∆B. This allows us to ignore the initial condition B(0) in the following evaluation.2 Assuming that D = 0.5 (which implies that ton = Ts /2), and v = Vd then we can write: T2s 1 Vd dτ N1 Ac 0 Vd Vd Ts = = 2N1 Ac 2N1 Ac fs
∆B =
(6.34) (6.35)
This value corresponds to the peak value of the flux in Figure 6.15(a). To evaluate the average value we calculate the area under the ∆B curve and divide by the time (since in Figure 6.15(a) the ∆B waveform is triangular). Therefore using (6.35) the expression for ∆Bave is: ∆Bave = =
Vd 2N1 Ac fs
Ts 2
Ts Vd 4N1 Ac fs
for D = 0.5
(6.36) (6.37)
We can now find ∆Bmax , the maximum deviation of the flux from the average flux, by subtracting (6.37) from (6.35) to give: ∆Bmax = Maximum flux excursion.
Vd 4N1 Ac fs
for D = 0.5
(6.38)
which is valid for both converters. A little earlier we mentioned that we had ignored the initial value of the flux density, but in the footnote we noted that this would be important. Referring to Figure 6.14, one can see that when there is no excitation of the core that the remnant flux density is Br . Therefore this point on the BH characteristic is the starting point for any unidirectional flux excursion – i.e it is the initial condition B(0) in (6.33). Therefore, using the definitions in Figure 6.14 the forward converter flux excursion ∆Bmax becomes: ∆Bmax =
1 (Bm − Br ) 2
(6.39)
i.e. the flux excursion is limited by the remnant flux density in the core. Because the flux is starting off with the Br offset, then the flux cannot undergo large flux excursions. In the case of the full bridge converter, the flux undergoes symmetric flux density excursions about the zero flux density point in Figure 6.14.3 Therefore 2 Note the the initial condition is very important when it comes to evaluating the magnetic utilisation, as we shall see. 3 This is achieved because of the switch drive circuits are designed to produce these flux excursions. Note that it is not intrinsic in the design of these converters that this would happen.
6.2 Isolated Converter Topologies
203
∆Bmax is limited only by the saturation flux of the core – i.e.: ∆Bmax = Bm
(6.40)
What are the implications of these differences in the maximum flux density that can be achieved with these converters? These can be gleaned by considering (6.38) in the light of the above comments. Rearranging (6.38) we get: Ac =
Vd 4N1 (∆B)max fs
(6.41)
We can see from this expression that if ∆Bmax is large then Ac can be smaller. Therefore, given the same applied voltages, duty cycle and switching frequency, and for the same number of turns on the primary, the full bridge converter will have a significantly smaller core for the magnetics as compared to the forward converter. Remark 6.12 Equation (6.41) assumes that fs is the same and N1 is the same under the condition of smaller core cross-sectional area. However, as can be seen from (7.23) in the following chapter, reproduced here for convenience: L=
µN12 Ac lc
(6.42)
where lc is the magnetic path length of the core, the inductance of the core is much less. This should also be obvious from the definition of inductance: L=
N1 BAc λ = i i
(6.43)
If Ac is smaller, then for the same current i the B will be the same (via Amperes Law), and therefore λ will be smaller. Therefore implicit in (6.41) is the fact that the current is allowed to increase when we have the smaller core area, since the same voltage is applied by the converter across the winding for the same time, but the inductance is less. Remark 6.13 As can be gleened from Remark 6.12 there is a trade-off for the reduced size magnetics under the condition specified – for the same power output we have a larger magnetising current, therefore higher losses, and larger switching devices. Remark 6.14 The fact that one does not have to demagnetise the core in the push-pull converter means, without considering the maximum flux density issue, one can produce more power from the same magnetic core. The effective maximum duty cycle is 1, whereas for the forward converter it is 0.5 (depending on the relative turns ratio of the ternary winding). Remark 6.15 In general a bidirectional flux density change type of converter uses the magnetic material more effectively than a unidirectional flux density converter. Remark 6.16 One can see from (6.39) that the maximum excursion of the flux in the forward converter is limited by the remnant flux in the core. Therefore
204
Switch Mode Power Supplies one way to utilise the magnetics better in these types of converters is to reduce the remanence. This can be achieved by putting an air gap in the core. This to a large degree linearises the core operation, and also dramatically lowers the remnant flux density. This effect is shown diagrammatically by the dashed BH characteristic in Figure 6.14. Under the condition of identical duty cycle, identical turns in the primary winding and identical core area (i.e. the magnetising inductance of both cores is the same), then flux in the cores is: Forward converter: Bmax = Bave + ∆Bmax + Br
(6.44)
(2∆Bmax )Ts 2Ts = 2∆Bmax + Br
Bave = ∴ Bmax
(6.45) (6.46)
For the push-pull converter, assuming appropriate control (i.e. current control), then: Bave = 0
(6.47)
∴ Bmax = 0 + ∆Bmax = ∆Bmax
(6.48)
Therefore the push-pull converter has less than half the peak flux density in the core. This would means that the core losses in this converter would be lower than the the forward converter (see below on core losses). The other issue that can limit the utilisation of magnetic cores in switching power supplies are core losses. The general expression for the core loss per unit volume or weight is of the form: b
Core Loss density = kfsa [(∆B)max ]
(6.49)
where the k, a, and b are determined from the particular material. One can see from this expression that the core losses are a complex function of frequency of switching and the maximum flux density excursion. If, for example, the switching frequency is increased, then the maximum flux density becomes less, with everything else the same. Therefore, depending on the specific values of a and b, the overall losses will be smaller. Also the total core volume will be smaller, since the maximum flux density is less. On the other hand, the switching losses in the active devices will increase with increased frequency. One can see that the optimisation of the core losses must be carried out for each specific device.
6.3
Introduction to Control Techniques for Switching Power Supplies
Now that we have looked in detail at several idealised converter topologies suitable for switching power supplies, we shall now look at overall topological and control issues. Due to the varying background of the students doing this subject we shall not delve deeply into the control issues, but instead, an overview of the
6.3 Introduction to Control Techniques for Switching Power Supplies
205
concepts involved will be presented. There are many references on issues related to the control of switching supplies, both in books and in several of the IEEE Transactions, namely Power Electronics, Industrial Electronics, and Industry Applications. Some of the books on these issues are [4, 12, 13]. Before looking at the control issues, we shall consider some broader topological and practical issues of switching supplies. Consider Figure 6.16 which is a block diagram of a typical switching power supply (from [4]). Isolation barrier DC-DC power convertion Rectifier and filter
Mains Supply AC
EMI filter
HF Power Transformer
Switches
Rectifier and filter Vo
DC
HF Signal Transformer PWM Controller
Base and gate drive circuitry Small Mains Transformer
Error Amplifier DC
Rectifier and filter Feedback circuitry
Vo -ref
Figure 6.16: Block diagram of a typical switch mode power supply. As can be seen from Figure 6.16 we have looked at the detail of the dc-dc conversion section of the power supply in the first part of this chapter. The lower half of the diagram is related to sensing of the feedback signals and the control circuitry. The important point to note here is that the feedback signals have to be isolated from the input if we are to have an isolated power supply. This complicates the design of the supply considerably. The circuit of Figure 6.16 is a conceptual diagram of one way of designing the isolated feedback. In this configuration the control circuitry and PWM generation is on the output side of the isolation. The other alternative is to have this circuity on the supply side of the isolation, and only the output voltage is feedback in an isolated fashion. The relative merits of the control circuitry on the supply side and the output side are not clear cut. Having the control circuitry on the output side (as in Figure 6.16) has the advantage that one is transmitting pulsed signals (basically firing pulses) across the isolation. This would also allow one to use an optocoupler instead of a signal transformer. On the negative side the base drive circuitry is a little more complicated. If the PWM and control circuitry is on the supply side then the base drive
feedback isolation
206
Switch Mode Power Supplies circuitry is usually a little simpler compared to the output side circuitry. On the negative side, getting the output voltage and/or current in an isolated fashion can be difficult. One technique is to use a voltage-to-frequency converter on the output side, and a frequency-to-voltage converter on the supply side. Some power supplies attempt to use opto-couplers in a linear mode of operation. However, opto-couplers are an inherently non-linear device, and this is difficult to do. To complicate the issue even further they are subject to temperature variations. One rather nice and simple technique of getting isolated feedback variables with the control on the supply side is the circuit shown in Figure 6.17 which was proposed in [13]. This circuit uses a small forward converter to transfer the analogue voltage value of the output voltage across the isolation barrier. The BJT is connected to the output of the main power converter, and is turned off and on by the pulsating voltage here. This then operates a low power forward converter that transfers the main converter output voltage via the transformer to main converter primary reference. The small transformer would have a turns ratio so that the output voltage is higher than the main converter output voltage. By doing this any voltage drop across the rectifying Schottky diode is insignificant. One crucial aspect of the performance of this circuit is that the duty cycle of the main converter (which is used to control the small feedback forward converter) does not affect the output voltage. This is achieved because the output circuit is a peak detector, and the precise duty cycle does not affect the peak detected. The peak is related to the output voltage of the main converter. The forward feedback converter output voltage is then resistive divided to give a voltage that is appropriate for the error amplifier. It is claimed that this circuit is capable of giving an accuracy of 2% and has a bandwidth that is controlled by the RC time constant of the capacitor/resistive divider network at the output of the feedback circuit.
6.3.1
Start-Up
Another interesting practical aspect of a SMPS is how to start it up. The dilemma takes the form of a chicken or egg argument – one needs power to start the switching, and one needs switching to get power. The solution to this problem could take the form of that shown in Figure 6.16, where we have a separate power transformer for the control logic. Power is therefore immediately available for the PWM and feedback circuitry when the main power is applied. However, in many situations this would be considered to be an expensive solution. Another much lower cost solution is to use a control logic power winding, a resistor and a capacitor [13]. This is suitable for converters where the control logic is referenced to the primary. A circuit for this is shown in Figure 6.18. Initially the transformer section of the circuit is inoperative. When power is applied to the power supply the unregulated DC supply comes on-line. Consequently the electrolytic capacitor in Figure 6.18 will charge up. The zener diode is to limit the voltage to a value safe for the PWM generator IC. The PWM generator now has enough voltage to operate. Unfortunately many PWM generator ICs only have a small hysteresis band of operation around the nominal voltage of operation. For example, the UC3825 PWM generator IC by Unitrode Semiconductor Products (now owned by Texas Instruments ) operates with voltages from 9 Volts to a maximum of
6.3 Introduction to Control Techniques for Switching Power Supplies Isolation barrier
207
Main converter output Vo
P
S
R1
S
R2
v feedback
P
P
S Feedback circuitry Forward converter
Figure 6.17: Feedback circuit using a small forward converter.
30 Volts. There is a 400mV hysteresis around the 9 Volt minimum voltage. Therefore, once the circuit starts operating (at 9 Volts) then it will continue to operate until the voltage falls to (9 - 0.4) Volts. This implies that the capacitor voltage in Figure 6.18 cannot fall by the 0.4 Volt hysteresis value during the time that the main power circuit starts to supply power to the PWM generator. If the voltage does fall by this amount then the PWM generator will stop working, and the resistive charging process will cause the cycle to repeat. The circuit will therefore operate in a type of limit cycle. In order to make the onset of limit cycle behaviour less likely during startup of the power supply, one needs to create a larger hysteresis in the operating supply of the PWM IC. The PWM IC is designed limited to a certain hysteresis, so the increased range must be obtained by circuitry external to the chip. Figure 6.19 shows one way of achieving this [13]. This circuit effectively allows the capacitor to charge up to a higher voltage before the PWM IC is allowed to operate. The capacitor charges up as described for Figure 6.18. When the voltage on the capacitor reaches a value equal to the value of the breakdown voltage of zener Z2 plus the threshold voltage of the MOSFET, then the MOSFET will turn on. This then allows the PNP transistor to turn on and voltage is applied to the PWM IC, which begins to operate. The resistor RG feeds back voltage to the gate of the MOSFET so that it will remain on, even if the voltage across zener Z2 drops below its threshold voltage. The feedback will remain active while the voltage on the gate of the MOSFET remains above the threshold voltage. As a specific example of the operation of this circuit, consider zener Z2 to be
improved power start-up circuit
208
Switch Mode Power Supplies
Unregulated DC supply Initial charging resistor
Vcc
+
PWM Generator Chip
Power winding when running Figure 6.18: Example of a simple bootstrap power circuit for a PWM generator chip.
12 Volt and the gate threshold of the MOSFET to be 2 Volt. Therefore when the voltage on the capacitor reaches approximately 14 Volt, zener both Z2 and the MOSFET will be on. Consequently the PNP will turn on, and the 14 Volt on the capacitor will appear on the Vcc pin of the PWM IC. The capacitor will then begin to discharge. The PWM IC will continue to operate until the capacitor voltage falls below its minimum operating voltage, which in the case of a UC3825 is 9 Volt. Therefore, the circuit has created a voltage hysteresis for 14 − 9 = 5 Volt. Remark 6.17 The increased hysteresis created by the circuit shown on Figure 6.19 means that the capacitor can be a smaller size and still be able to keep the PWM IC running long enough to allow the auxiliary winding to start to supply the power to the PWM IC. Remark 6.18 The charging resistor shown in Figures 6.18 and 6.19 is constantly connected on the circuit. Therefore, even when the switch mode supply is running, it will still dissipate power. However, this resistor can be made quite large so that the power dissipated can be made small – the charging time of the capacitor is not that important (within reason). The resistor is no longer really supplying the current in the turn on phase, as it was with the previous circuit. Alternatively one can use auxiliary circuitry to switch the resistor out, thereby allowing a smaller resistor to be used.
6.3 Introduction to Control Techniques for Switching Power Supplies Unregulated DC supply Initial charging resistor
Hysteresis circuit
Vcc
+
Z1
Power winding when running
RB
Z2
RG
RG
1
PWM Generator Chip
2
Figure 6.19: Bootstrap circuitry modified for increased hysteresis range.
6.3.2
Protection Issues
6.3.2.1
Soft Start
Soft starting refers to generating voltage output very slowly when power is first applied. This is required because when power is first applied the control circuitry will apply the maximum duty cycle to the power stage. This can result in excessive current flow in the components which can be potentially destructive. In order to prevent this a special mode of operation is required so that the duty cycle ramps up from a very small value to the value required by the control circuitry. Soft starting is also used to recover a SMPS from fault conditions. Soft starting is handled internally in most PWM ICs, therefore it does not require any specific action by a designer. 6.3.2.2
Voltage Protection
Most SMPS integrated control circuits have a pin which can be connected to an external circuit. This circuit will generate a voltage into the pin of the IC when the input voltage rises above a certain value. Most ICs also contain circuitry that detects under voltage conditions. Internally the shutdown circuitry usually stops the internal latch from functioning and sets the outputs into a non-driving state. A block diagram of the Unitrode 1825 switch mode PWM generator chip is shown in Figure 6.20. Notice that the “Output Inhibit” is activated for low
209
210
Switch Mode Power Supplies voltage to the chip itself, as well as from the Ilim/SD input (i.e. pin 9). The later is activated by external circuitry to detect over voltage/under voltage to the power circuit. BLOCK DIAGRAM
U DG-92030-2
3/97
Figure 6.20: Block diagram of the Unitrode high speed PWM generator.
6.3.2.3
Current Limiting
Current limiting is included in most PWM control ICs to protect the power supply under short circuit conditions. There are two types of current limiting: • Constant current limiting. • Foldback current limiting. constant limit
current
Constant current limiting, as the name implies, is a form of current limit where the current can only go to a particular value and then it will not increase any more, regardless of the load. Therefore, even under short circuit conditions the current will not increase appreciably above this limit value. This concept is shown in a V0 I0 diagram in Figure 6.21. One point to note about this diagram is that the voltage at the output of the converter can be appreciable under this condition, depending on the impedance of the load. Remark 6.19 The constant current limit may not be satisfactory in many applications, since the limit current may, over time, result in the thermal rating of the inductor or transformer windings being exceeded. Therefore, if such a limit is to be used, then one must ensure that the windings and power devices can support the limit current indefinitely.
foldback limit
current
A slightly different limit is the foldback current limit. This limit is motivated by the desire of reducing the currents flowing in abnormal short circuit or near short circuit conditions. The operation of this current limit philosophy is shown
6.3 Introduction to Control Techniques for Switching Power Supplies
Vo
Load lines Vo, rated
RL = R1
Vo1 RL = R2
Vo2
I o, rated
Io
I limit
Figure 6.21: Operation of a constant current limit.
in Figure 6.22. In this case when the current reaches a limit value of Io, limit then the current limit drops with the output voltage. Therefore under short circuit conditions the current is reduced to a much lower value than in the previous case. The power that is being supplied to the external circuit under this condition is not nearly as high as in the constant current limit situation. Remark 6.20 The foldback current limit does not solve the overheating problem mentioned in the previous remark. If the circuit is operating at Io, limit then the problem is the same as in the constant current limit case.
Vo
Load lines Vo, rated
RL = R1 RL = R2 Vo1 Vo2 I o, foldback
I o,rated
I o,limit
Figure 6.22: Operation of a foldback current limit.
Io
211
212
Switch Mode Power Supplies Most PWM ICs implement a two stage current limit. The current through the switch is fed through a sense resistor, and the fed into the current limit pin of the PWM IC. If the voltage on this pin reaches a certain value the switch turn on pulse is turned off until the next control cycle. Therefore the current limiting is carried out on a switching interval basis. If the voltage goes higher and reaches a second limit, then the controller stops switching and restarts in soft start mode. The power supply can then oscillate in this mode until the short or the fault is rectified. Current limiting is actually a little more complicated than has been made out so far. Consider the situation when one has a converter with a transformer and multiple output windings. If the current sensing is set up on the primary, then the current limit has to be set for the current pulled under full load from all the windings. However, if all the secondaries, except one, are unloaded, then if there is a short on this winding the full current of the inverter can go through this winding before there is a trip. This situation could result in the destruction of this winding, or destruction of the rectifier components on this winding. There is no easy way out of this problem. Probably the most economical solution is to sense the current limit of each winding individually, and then take the output of these limit circuits and “OR” them together. This forms the trip signal to the PWM chip.
6.3.3
Control Architecture of a Switch Mode Power Supply System
6.3.3.1
Voltage Mode Control
Figure 6.23 shows a conceptual diagram of a SMPS system from a control perspective (as opposed to an implementation perspective). The compensating amplifier is shown with generic feedback components Z1 and Z2 . These components can contain reactive circuit elements, which allow a variety of different transfer functions to be set up in the feedback loop. Compensating amplifier Zf
Vd
Zi
+
vc
PWM Controller
d
Power stage and output filter
vo
Vo,ref
Figure 6.23: Conceptual diagram of a control system for a switch mode power supply.
6.3 Introduction to Control Techniques for Switching Power Supplies
213
In general the main objective of the control system of Figure 6.23 is to control the output voltage to be a specific value under varying load conditions. In order to design the feedback compensation, one needs to obtain a model of the system suitable for control analysis. This is achieved by using an approach called state space averaging. This allows one to obtain a state space model of the system, accounting for the switching in the circuit in an average sense [4]. We shall not look at the detail of the process. The net result of this modelling process is that one can obtain a small signal linearised model of the converter and its control of the form shown in Figure 6.24. This figure shows each of the converter components as a transfer function. In this form one can apply standard classical control system design techniques to the system. v~ (s ) T1 (s ) = ~c vc (s )
~ d (s ) Tm (s ) = ~ vc (s ) v~o,ref (s )+
S -
v~err (s ) Compensating error amplifier
v~c (s )
PWM controller
v~ (s ) Tp (s ) = ~c d (s )
~ d (s )
Power stage and output filter
v~o (s )
Figure 6.24: Linearised model of a switch mode power supply. Whilst switching power supplies seem to be very simple circuits, their operation from a control viewpoint is more complex than one might initially expect. Consider, for example, the flyback and boost converter. Because these two converters store energy in the magnetic field of an inductor before transferring it to the load they exhibit an effect caused by having a right half plane zero in their transfer function. Such systems are known as non-minimum phase systems. For the non-control literate reader, a right half plane pole corresponds to a response that tends to go in the wrong direction to correct a disturbance. Consider the following example of a right half plane zero effect. If we have a flyback converter, and there is a sudden decrease in the output voltage due to an increased output load on the converter. The natural reaction of the control system is to increase the duty cycle, D, so that more energy is transferred to the load to restore the voltage. However, due to the above-mentioned energy storage operation principle of this converter, the initial increase in the duty cycle can result in a further decrease in the output voltage. This is due to the fact that increasing D instantaneously delays the next delivery of energy from the magnetic field to the load, as compared to what would have happened if there had been no change in D. One can see that if the feedback is very high bandwidth then this will result in a further increase in D, and the process will repeat. We effectively have positive feedback. Of course the process will stop when we get to the limit of the duty cycle (this is a non-linear effect that is not accounted for in our linear explanation). The presence of a right half plane zero
non-minimum phase
214
Switch Mode Power Supplies in these converters limits the control bandwidth of these types of converters. Figure 6.23 shows a basic diagram for a switch mode control system. Many real systems actually use a hierarchical control system consisting of two nested control loops. The inner most of the control loops is a current control loop, and the outer control loop is the traditional voltage control loop. The advantages of using the current control loop will be discussed in detail in a following section. Suffice to say that the disturbance rejection properties of the controller are improved using this structure. A block diagram of this hierarchical control system appears in Figure 6.25. Notice that the voltage vc appears as a current reference to the section of the circuit that controls the current. Switching signal H (s ) G(s )
vo,ref
+
S
vo,err
Voltage loop feedback compensator
vc
Comparator and latch
Power stages and output filters
vo
iL
iL vo
Figure 6.25: Block diagram of a nested loop control system for a switch mode power supply.
6.3.3.2
input disturbance rejection
Voltage Feed-forward PWM Control
All of the diagrams for control of the SMPSs thus-far have relied totally on feedback control. However, in the case of input voltage fluctuations one can feedforward the change of input voltage to the controller so that it can be accounted for before it would affect the output. This is usually achieve in practice by feeding the input voltage into the PWM IC. This chip usually accounts for the supply variation by altering the amplitude of the triangular waveform that is used internally to generate the PWM. One can see from (5.7) that if vst is increased (corresponding to an increase in the peak of the triangular waveform) then the duty cycle decreases. Therefore if this value is controlled by the input voltage then it is possible to get near perfect input disturbance rejection. 6.3.3.3
Current Mode Control
Current mode control is a term used in the SMPSs literature to refer to a nested loop control system, such as that depicted in Figure 6.25, where the inner loop controls the inductor current, and the outer loop controls the output capacitor voltage. There are a number of very good reasons for complicating the control structure of the addition of the current control loop: • Switch current limiting. It was mentioned in Section 6.2.1.1.2 that one of the problems with the push-pull converter was that small differences in the
6.3 Introduction to Control Techniques for Switching Power Supplies
215
switching times of the switching devices could cause eventual saturation of the transformer. Employing current mode control the peak switching currents in the two switches of such converters can be balanced so that this phenomena does not occur. Note that the current mode control in this situation would be from each of the two switches. • Simplified converter dynamics. Current control effectively removes the pole introduced by the output inductor. This simplifies the dynamics of the converter system, effectively allowing the bandwidth of the control loop to be increased (because of the increased gain and phase margin achieved). This is especially useful in converters that have a right half plane zero in their response. • Simplified paralleling of converters. The presence of the current control loop allows the possibility of paralleling of several SMPSs, with each power supply contributing the same amount of current to the load. This is achieved by feeding each of the supplies with the same control voltage. • Automatic voltage feed-forward. The desirable properties of voltage feedforward are implicitly achieved when current mode control. If the input voltage increases, the current will reach the current limit sooner. Therefore the duty cycle will decrease with out the delay of waiting for the voltage to vary at the output. In a current mode controlled SMPS, as depicted in Figure 6.25, the control voltage vc , which is derived from the error between the desired output voltage and the actual output voltage, represents a desired inductor output current, or a switch current. This is achieved in a number of different ways [4]: 1. Tolerance band control. 2. Constant “off” time control. 3. Constant frequency control with turn-on at clock time. Let us look at how each of these schemes works in a little more detail. In tolerance band control the inductor current is kept within a band, and the control voltage is effectively controlling the average value of the current. The width of the band is a design parameter, and by choosing it the designer is also influencing the switching frequency of the converter (which is also related to other parameters of the converter). Tolerance band control is essentially a classical hysteresis or bang bang type of control strategy. The operation of tolerance band control is depicted in Figure 6.26. The ∆iL value is one of the design parameters for the controller. If ∆iL is very small then, for the same converter parameters, the frequency of switching will be much larger. One can also see that if the load current is larger (which corresponds to a larger slope on the current sawtooth) then the frequency will be higher. Therefore the switching frequency is also a function of the load. These properties are an undesirable property of this type of controller. Another problem with the tolerance band controller is that it only really works properly in continuous mode operation. If the current becomes discontinuous, then the desired average inductor current can become negative. If the current is discontinuous then the lower switch on limit would have to be zero – the circuit has to be designed
tolerance band control
216
Switch Mode Power Supplies
vc
iL
Di L / 2
Di L / 2
t
t on
Switch turns on
IL
t off
Switch Switch turns turns off on
Figure 6.26: Waveforms for tolerance band current control.
constant “off ” time control constant frequency with turn-on clock time control
subharmonics
to handle this. If the controller is not specially designed, the controller will respond to driving the inductor current to zero, and it will then stay there. There is also a problem of very high switching frequencies at low current values, this corresponding to a very small hysteresis band. Constant “off” time control controls the peak current in the inductor. In this strategy the control voltage specifies the maximum or peak current. When this peak current is reached the switch is opened for a fixed period of time. It is then closed again and the process repeats. This situation is depicted in Figure 6.27. This control strategy also suffers from the problem that the switching frequency is dependent on the load and the converter parameters. The constant-frequency with turn-on at clock time control is the control strategy most commonly used. This is due to the fact that the switching frequency is user definable in the strategy. One is effectively trading off the ripple control achievable with tolerance band control for the constant switching frequency. This allows one to control more accurately the losses in the switching devices, and makes the design of the output filter much simpler. Figure 6.28 shows the waveforms that occur with this control. The switch is closed at a time determined by a clock signal. The switch remains on until the current limit is reached, and then it turns off until the beginning of the next control period. The process then repeats. The fact that the switch only turns on at the beginning of a clock pulse means that the frequency is fixed by the clock period (which of course is user definable). There is a problem with straight current mode control that we have not mentioned in the discussion thus-far. If the converter duty cycle exceeds 50% the converter output will possibly oscillate at a subharmonic of the switching frequency – specifically at half the switching frequency. This occurs because the current control loop works by turning off a switch when the current reaches a particular value. It is possible if the duty cycle is larger than 50% that the current will not return to the value at the beginning of the control interval.
6.3 Introduction to Control Techniques for Switching Power Supplies
217
vc
iL
I$L
t on
Switch turns on
t
t on t off Switch turns off Switch turns on
t off
Constant t off
Figure 6.27: Waveforms for constant “off” time control. Therefore in the next control interval the current will reach the desired value sooner (since it is starting off with an offset). Therefore the switch will turn off sooner than it otherwise would, and consequently the “off” time will be longer. Therefore at the end of this interval the current may be lower than the desired value. This would result in the control deciding to turn the switch on longer, since we are now starting from a negative offset compared with the correct value if this phenomena were not occurring. One can see that the period of the oscillation caused by this jitter in the duty cycle results in a frequency that is half the switching frequency. In addition to the subharmonic oscillation problem, one also has a form of open loop instability with current mode control [14]. The following discussion is with reference to Figures 6.29(a), (b) and (c). Consider Figure 6.29(a) shows the effect of a perturbation of the inductor current (dashed line) away from the nominal current (the solid line). Notice that the perturbation dies away in this case. The effective duty cycle changes due to the way that current mode control works. Figure 6.29(b) shows a similar situation, but in this case the duty cycle is larger than 0.5. One can see that instead of the error between the nominal inductor current and the perturbed version getting less, it actually increases with each successive control interval. Therefore, there is effectively positive feedback in this case. 6.3.3.3.1 Slope Compensation Many of the problems with current mode control can be overcome by using the technique called slope compensation. This technique involves adding a sawtooth waveform to the current feedback wave-
open loop instability
218
Switch Mode Power Supplies
vc
iL
I$L
t on t off
Ts
Clock
t
t on t off
Ts
Clock
Clock
Constant period between clock pulses Figure 6.28: Waveforms for constant frequency with turn-on at clock time control.
6.3 Introduction to Control Techniques for Switching Power Supplies
iL
Ve
m2 m1
Di 0
Di L
t (a) Duty cycle < 0.5
D
Ve
m1
m2
Di 0
Di L
t (b) Duty cycle > 0.5
D
Compensated voltage reference Ve
-m
m1
m2
Di 0
t D
(c) Duty cycle > 0.5, slope compensation
Figure 6.29: Open loop instability of current mode control. (a) stability with duty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stability with duty cycle > 0.5 and slope compensation.
219
220
Switch Mode Power Supplies form, or alternatively subtracting a sawtooth from the voltage error signal fed to the current mode controller comparator. Figure 6.29 shows the effect of slope compensation. In this case the sawtooth waveform is subtracted from the error voltage, Ve coming from the voltage error amplifier. This effectively forms a new reference for the current control section of the loop. In this case, even though the duty cycle is larger than 0.5 the perturbed current returns to the nominal current (as was the case for D < 0.5). The added ramp has a constant value, and therefore the sensitivity of the feedback to variations in the current measurement becomes less. To understand how this works one can look at the extreme case when the current in the load is very low and the ramp is added to the current measurement. In this situation the control voltage from the error amplifier is being compared to the slope compensation voltage, and hence the circuit is essentially operating in the normal triangular wave comparison mode of voltage control. Therefore, the addition of the slope compensation brings in some features of voltage control into the current mode loop, and under the situation of low currents it effectively behaves as voltage control (and therefore would have the dynamics of voltage control). Let us consider this situation in a little more detail. One can see from Figure 6.30 that the current perturbation error at the beginning of a control interval, ∆i0 , is related to the current perturbation error at the end of the next control interval, ∆i1 , as follows: m2 ∆i1 = −∆i0 (6.50) m1 Remark 6.21 Equation (6.50) shows that if |m2 | > |m1 | then |∆i1 | > |∆i0 | – i.e. the error has increased after one control interval. This situation would continue. This situation correlates to D > 0.5, since for the circuit to be in steady state, i at the beginning of the interval, must be equal to the value at the end. This implies that |m2 | > |m1 |. Therefore the two conditions are synonymous. As mentioned above the compensation can be carried out by adding the slope compensation waveform to the current, or subtracting from the voltage. The techniques can be shown to be equivalent. Therefore, assuming that we are adding to the current we can modify (6.50) by adding the slope compensation to give: m2 + m ∆i1 = −∆i0 (6.51) m1 + m If the duty cycle is near 100% then the slope m1 ≈ 0. Furthermore, we wish that ∆i1 < ∆i0 for the error to be decreasing over successive control intervals. Using these facts we can write the following: m2 + m −∆i0 (6.52) < ∆i0 m1 + m m2 + m ∴− <1 (6.53) m1 + m 1 (6.54) implying m > − m2 2
6.3 Introduction to Control Techniques for Switching Power Supplies
m2
m1
Di 0
Di1
t
x=
Di 0
x=
m1
-Di1 m2
Figure 6.30: Geometrical relationship of the current waveform slopes when there is a current perturbation. Remark 6.22 Equation 6.54 shows that the slope of the ramp that must be added to the current or subtracted from the voltage error must be greater than half the magnitude of the down slope of the inductor current. If one considers (6.51), and consider it to be a discrete iterative expression, then the inductor current behaves as though it is an underdamped RLC circuit. This is shown in Figure 6.31. This RLC response can be damped out (akin to critical damping) by choosing m = −m2 . The effect of this is shown graphically in Figure 6.32.
Din = -Di(n -1)
Fm GH m
2 1
I + m JK +m
t
1T
2T
3T
4T
5T
Figure 6.31: Inductor current response of current mode converter.
221
222
Switch Mode Power Supplies
Ve
-m = m 2
m2
Dio
m1
t
Figure 6.32: Optimal slope compensation to eliminate RLC type oscillations.
Chapter 7
Introduction to Practical Design of Switch Mode Power Supplies 7.1
Introduction
In this chapter we shall briefly look at the most important aspects of the physical component design of a switch mode power supply (SMPS). The approach taken is a very practical one, with some theory where appropriate. The design of a switch mode power supply, like most electronics design, is complicated because of the large number of design trade-offs that are available. This fact means that this presentation is far from exhaustive, nevertheless the salient issues in making design choices will be emphasised. The design of SMPSs is complicated even further by the fact that virtually all SMPS’s use magnetics in their design. Consequently much of this chapter will be concerned with the design of these magnetics. The first section of this chapter will consider issues related to the selection of the electronic components of a SMPS. The second section of the chapter will look in some detail at the design of SMPS magnetics. Much of the material in this chapter is closely based on [13].
7.2
Component Selection
The information on the selection of components for SMPSs is usually material that ends up in vendor’s application notes (if one is lucky), or in the mind of a designer. This information therefore is often very inaccessible to a new designer, and is often attained by many disappointing design exercises. In this section we shall attempt to highlight some of these hard-to-find selection criteria for a variety of components: resistors, capacitors, Schottky diodes, rectifier diodes, BJTs, MOSFETs, op amps, and comparators.
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Introduction to Practical Design of Switch Mode Power Supplies
7.2.1
Resistors
The resistor is probably the most ubiquitous of all electronic components. Consequently most electronic designers don’t pay a lot of attention to details other than its value and power rating. 7.2.1.1
Values
There is a practical maximum value for a resistor that is used on a PCB. This practical limit occurs for several reasons: • Large resistor values are not commonly available (although they can be obtained for specialised applications). • If a very large value of resistor is used, then the resistance across the PCB between the resistor legs may be comparable or less than the resistor value. Therefore the resistor is ineffective. • Using large resistor values makes the circuit very susceptible to electrical noise. A large value of resistance means that very small capacitively coupled currents can result in large coupled voltages. Remark 7.1 Don’t use large values of resistance in your designs if at all possible. Even values of 220kΩ can cause significant noise pickup problems, especially in switching applications which are inherently noisy in any case. 7.2.1.2 carbon composite
metal film
wire wound
Resistor Types
Obviously choosing the correct resistor for the job is necessary in electronics design. There are several resistor choices, depending on the application. The oldest style of common resistor is the carbon composite resistor. One can usually tell these resistors by the large size for their power rating. One may still find these resistors in a hobbyist store, but for professional circuit design they are no longer used, as there are much smaller, lower cost, and more reliable resistors available.Another interesting point about carbon resistors is that the preferred values made were far fewer than the more modern resistors (only 12 per decade). The most commonly used resistor today is the metal film resistor. These are available in a wide range of values, and low to moderate power ratings (several watts).As noted in the previous paragraph, there are a lot more preferred values in these resistors (48 to 96 values per decade, depending on tolerance). For higher power rating applications there are several choices. The wire wound resistor is the one that most people would be familar with (a heating radiator element is an extreme form of this type of resistor). They are generally available in power ratings from 1W to approximately 1kW (and sometimes larger values for special applications such as regeneration banks in large inverter systems). One problem with wire wound resistors is that they have high inductance, which makes a conventional wire wound resistor unsuitable for high frequency applications. Fortunately, it is possible to wind the resistor with equal turns in two different winding directions so that the inductance can almost be eliminated (the flux produced from each winding direction cancels). Variable
7.2 Component Selection
shunt
225
resistance wire wound resistors are called Rheostats. These are most commonly used in laboratories for experiments, rather than in commercial products. Another common type of resistor used for current sensing applications is the current shunt. This resistor type usually has a very low, but precisely known value. One can detect the voltage across the resistor, and then use Ohm’s Law to deduce the current through the shunt. The shunt itself is made of metals that have a very low temperature coefficient. A low cost shunt can be created using a PCB track itself. This should only be considered where cost is the primary consideration, since the accuracy of such a shunt is not very good. It should be noted that shunts provide a non-isolated measurement of current. In many applications this is all right, but in other applications where isolation is important then additional measures must be used to gain isolation of the measurement. Table 7.1 summarises these comments. Type
Suggested Applications
Carbon composite Metal film Wire wound (inductive) and rheostat Wire wound (non-inductive) Shunt PCB track
Not commonly used anymore General purpose – replace carbon Used for high power load resistors Used in high frequency applications Used for measuring large currents Used for low cost measurement of currents
Table 7.1: Resistor application selection guide
7.2.1.3
Tolerance
One important attribute of a resistor is its accuracy. Many years ago the “garden variety” resistor had a tolerance of 5%, and the exotic resistors had a tolerance of 1%. These days the default tolerance of resistors is 1%, and at slightly higher price one can have resistors with 0.1% tolerance. 7.2.1.4
Selecting Values
In many designs the specific value of a resistor does not matter (although in some it does as well). If this is the case then only the ratio between resistors is important. Therefore, in order to minimise the number of components that need to be ordered it is better to try an choose the same values of resistor where possible. For example, if sections of the circuit rely on resistor ratios, then choose one resistor out of the two to be say, 10kΩ. One can then choose the other to satisfy the ratio requirement. 7.2.1.5
Maximum Voltage
Voltage ratings are not a parameter that immediately comes to mind when thinking of resistors. However, in the case of surface mount resistors, the spacing between the ends of the resistor means that voltage rating must be considered. In SMPS circuits one can be dealing with voltages anywhere from 10s of volts
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Introduction to Practical Design of Switch Mode Power Supplies to 100s of volts, and at the top end of this range resistor voltage rating can be important. 7.2.1.6
Temperature Coefficient
Most modern metal film resistors have a very small temperature coefficient of the order of 50–250ppm/◦ C. Wire wound resistors however, depending on the material they are made from, can exhibit substantial changes of resistance with temperature. This is especially a problem with these resistors, since by definition they will undergo large temperature changes. Shunt resistors, as mentioned in Section 7.2.1.2, are purpose designed to exhibit very low temperature coefficients. They also usually have a very low value so that power dissipation is low in the resistor, and hence temperature rise is kept to a minimum. 7.2.1.7
half power operation
Power Rating
All resistors have a maximum power rating. However, a resistor should not be operated at its maximum power rating, since it is severely stressing the component. This severe stress usually results in a high failure rate of components. In order to ensure high reliability of resistors it is recommended that a resistor, at worst, is operated at half its nameplate power rating. It is probably better to be even more conservative than this and operate the resistor at approximately 1/3rd of its power rating. Practical Issue 7.1 Select resistor power ratings so that they are operating at approximately 1/3rd of the device specified power rating.
pulsed power The above comments are implicitly for continuous power dissipation. However, one can modify them in relation to pulses of power, especially for wire wound resistors. Manufacturers of these resistances will sometimes give a table of pulsed powers for pulses of less than 100msec. Practical Issue 7.2 Power ratings for non-wire wound resistors should be strictly adhered to. It is alright to have power pulses up to the maximum rating of the resistor for short durations (say less than 100msec) providing the repetition rate is not too high. Rheostat A Rheostat is a variable power resistor, as opposed to a Potentiometer which is a variable signal level resistor. Rheostats usually consist of a wire wound resistor that has a sliding contact. The power rating for the device is for the whole resistor. Therefore if the sliding contact is halfway along the resistor, so that only half the resistor is being used, then the power rating is half the nameplate value (so that the maximum temperature of each of the wire turns is the same as for the full resistor). One must be particularly careful with using these resistors on a voltage source, as it is easy to move the slide around so that the maximum power rating of the active section of the Rheostat will be exceeded. One can put a current meter in the circuit to make sure that the current rating of the device is not exceeded as adjustments are made, or alternatively another resistor can be put in series with the Rheostat to prevent overload.
7.2 Component Selection 7.2.1.8
227
Shunts
Whilst a shunt is a resistor, it is not used for the normal application of the resistor, which is to somehow limit current flow. With a shunt one wishes to impede the current flow as little as possible. A shunt is generally constructed of a near zero coefficient metal such as manganin, attached to heavy duty terminal blocks made of brass. Shunts come in a variety of sizes, ranging from very low current shunts, up to shunts that can handle thousands of amps. Typically a shunt is designed to produce either 50mV or 100mV at its rated current. Shunts are generally used if one wishes to measure low frequency or DC currents. In AC applications, current transformers are often used instead since they offer isolation. Remark 7.2 It should be noted that the use of shunts in high power Power Electronic applications is not very common these days. For example, it is not common for shunts to be used to measure the currents in inverter systems. Instead Hall Effect transducers are used, since they have good frequency response and offer isolation. Consider a 100A shunt with a 100mV output. This means that the resistance of the shunt is 100mV / 100A = 1mΩ. In addition to the resistance of the shunt there is a parasitic inductance. For a 1in shunt, this inductance is of the order of 10–20nH. If we assume 20nH, then we have an AC model for the shunt as shown in Figure 7.1. Obviously the impedance of this circuit is Rshunt +jωLshunt which is frequency dependent. Clearly there is a zero in the impedance frequency response, and hence above a certain frequency the voltage across the shunt will increase due to the effect of the inductance.
Rshunt
Lshunt
Figure 7.1: Equivalent circuit model of a current shunt inductance effects We found above that the value of resistance for a shunt is usually low. Therefore, even though the parasitic Lshunt is low, the frequency at which the zero occurs can also be relatively low. If we use the specific values from the previous paragraph, then we have that the zero in the impedance occurs when ωLshunt /Rshunt = 1 which gives f = 1mΩ/(2π × 20nH) = 8kHz. In many real applications for shunts the currents will contain frequencies above 8kHz, and hence one would be getting erroneous current readings. Remark 7.3 One way to raise the frequency at which the impedance zero occurs with the shunt is to raise the resistance of the shunt. However, in high current applications this is not feasible. An alternative strategy is to lower the inductance of the shunt by making it from stacked layers of metal, instead of a single piece. There are practical limits on how far this can be taken. A control person would immediately think of another solution to the shunt frequency response problem – try and arrange a pole-zero cancellation so that
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Introduction to Practical Design of Switch Mode Power Supplies infinite frequency response can be obtained. The obvious way to do this is to place a capacitor in parallel with the shunt – i.e. in parallel with the equivalent circuit of Figure 7.1. The impedance function with the capacitor can be easily sown to be: Rshunt + jωLshunt (7.1) Zeq = (1 − ω 2 Ccomp Lshunt ) + jωCcomp Rshunt where Ccomp the compensating capacitor value. If we make the assumption in (7.1) that ω 2 Ccomp Lshunt 1 then: Zeq ≈
Lshunt ) Rshunt (1 + jω R shunt
1 + jωCcomp Rshunt
(7.2)
Clearly for pole zero cancellation we require: Ccomp Rshunt =
Lshunt Rshunt
(7.3)
which means that: Ccomp =
Lshunt 2 Rshunt
(7.4)
Substituting in the values for the 1mΩ shunt one gets: Ccomp =
20nH = 20, 000µF (1mΩ)2
(7.5)
Clearly this is not a practical value of capacitance. Fortunately there is a way to achieve the same effect in the op amp amplifier circuit that is required to amplify the current shunt voltage signals. The value of capacitance used in this circuit are much more reasonable values (usually in the nF range) [13]. 7.2.1.9
PCB Track Resistors
If one is looking for a budget priced version of the shunt one can use the resistance of a PCB track. This type of shunt will have poor accuracy because it relies on the accuracy of the track width and thickness, and the temperature coefficient for copper is very poor (0.4%/◦ C). However, this type of current sense can be used for overcurrent protection. Practical Issue 7.3 The resistance of a trace is approximately given by the formula [13]: length (1 oz. copper) (7.6) R = 0.5mΩ width at room temperature. Two-ounce copper has half this value.
7.2.2
Capacitors
Just as there are different types of resistors, there are different types of capacitors. In any design it is usually not possible to use just one type of capacitor – the correct capacitor technology must be used for the application.
7.2 Component Selection 7.2.2.1
Types of Capacitors
Capacitor types are defined by their construction technology. The main types of capacitors in common use are: Electrolytic This is one of the most common types of capacitors used for large capacitance. There are a variety of choices available, with the most common being the aluminium electrolytics. These capacitors can have very large values – well into the millifarad range, and many hundreds of volts. Note that these capacitors are physically very large. There are also tantalum electrolytic capacitors, which are available in solid and wet varieties. These capacitors tend to have maximum sizes that are smaller than those attainable in the aluminium electrolytic variety, but they have better high frequency performance. A distinguishing feature of all electrolytic capacitors is that they have a polarity. Ceramic These are the flat, disc like capacitors that home hobbyists would be familar with. They are used for timing and bypass purposes. They are available in values from a few picofarads to 1µF. New in this range of capacitors are the multilayer ceramic (MLC) variety, which have very low effective series resistance and larger maximum values (several hundred microfarads) as compared to the older ceramics. Plastic These capacitors can withstand very high dv/dt across them, particularly the polypropylene variety. They are used in circuits such as quasiresonant SMPSs. Another variety, Polystyrene, are more specialised, and are used where very low leakage is required, such as in sample-hold applications.
Type
Suggested Applications
Aluminium Electrolytic Tantalum Electrolytic Ceramic Multilayer ceramic Plastic
Used when large capacitance needed. Low frequencies. Bulky. Use for moderate capacitances. Medium frequencies. Less bulk. Timing and bypass applications. High frequency bypass, low leakage applications. Use for high dv/dt applications. Low leakage current applications.
Table 7.2: Capacitor application guide The information in the above description is summarised in the Table 7.2. 7.2.2.2
Standard Values
Capacitors do not have the same range of values as modern resistors do – in fact the preferred values are basically the same as those available in the old carbon resistor ranges: 1.0, 1.2 1.5, 1.8, 2.2, 2.7, 3.3, 4.7, 5.6, 6.8, 8.2. Note that 5.6 and 8.2 are not always available. One can get away with this crudely spaced set of values because the tolerances for capacitors are generally not all that accurate anyway. Also, in many applications, it is the value of a capacitor in relation to a resistor that is the
229
230
Introduction to Practical Design of Switch Mode Power Supplies important quantity. Therefore, one can adjust the resistor to get the desired result. Practical Issue 7.4 Just as large resistor values should be avoided, one should also avoid the use of capacitor values less than approximately 22pF. The reason for this is that capacitance exists between any parallel plates, and consequently parasitic capacitances on a PCB can swamp out the designed low values of capacitance. 7.2.2.3
Tolerance
The tolerances on capacitors are usualy very poor – typically ±20%. Electrolytic capacitors can have even worse tolerances than this. The other variable to consider is the temperature range that the capacitor will operate over. The capacitance value can vary substantially with temperature, e.g. some types of capacitors can loose 80% of their capacitance at -40◦ C. 7.2.2.4
ESR and Power Dissipation
The equivalent series resistance (ESR) of a capacitor is a very important variable, since it determines the performance of the capacitor in many applications, and is also closely related to the power dissipation in the capacitor. Most manufacturers quote the ESR at 100 or 120Hz. The reason for this is that they imagine that the capacitor is being used in power supply smoothing applications. These values of ESR are useless in determining the ESR at say 100kHz (which is necessary in power electronics applications). Therefore, if you are using a capacitor in a power electronic application with high frequency currents, make sure that you have a relevant value of ESR. Remark 7.4 The ESR resistive can have a very important effect on the voltage ripple from a capacitor. For example, if one is pulling 1 Amp of ripple current at 100kHz from a capacitor, and the ESR is 100mΩ, then there is 100mV of ripple introduced by the voltage drop across this internal resistance. Therefore, if one requires 50mV of ripple maximum, then one would need at least two capacitors in parallel, and we have not even taken into account the amount of capacitance required to supply the charge to the load. The situation in relation to the ESR could be even worse if the capacitor has to operate over a wide temperature range. 7.2.2.5
Aging
Aging of capacitors, especially in relation to electrolytics, can be very important. Electrolytic capacitors may have a life time figure associated with a certain temperature of operation. Values could be 1000 hours, 2000 hours, or even better 5000 hours. When a capacitor approaches its design age the capacitance decreases, and the capacitor will be out of specification. In the worst circumstances the capacitor may fail. Fortunately, for every 10◦ C drop in temperature, a capacitors life doubles. For example, is a capacitor is rated at 2000 hours at 85◦ C, then if it is operated at an average temperature of 25◦ C, then it will last 2000 × 26 = 128, 000 hours, or 16 years.
7.2 Component Selection Remark 7.5 The use of the average temperature the capacitor is subjected in the above calculation is important. 7.2.2.6
dv/dt Rating
There are two forms of dv/dt rating for capacitors depending on the application and the technology of the capacitor. Electrolytic capacitors, for example, usually have a rating on the amount of rms ripple current that they can tolerate. This rating is related to the average i2 R lose in the ESR resistor, and the thermal properties of the capacitor package. Metallised plastic capacitors used in resonant and quasi-resonant converters have a dv/dt rating. In these applications these capacitors can sometimes be subject to very rapid rates of change of voltage across them. This in turn leads to very large current flows via the expression i = C(dv/dt). These large peak currents can cause instantaneous heating in the capacitor, which can result in the destruction of the capacitor if the rating is exceeded. Remark 7.6 Depending on the application the ripple current or the dv/dt rating may be important. Ripple current tends to be the appropriate measure when the capacitor is being used in an application where the voltage across the capacitor is relatively constant. dv/dt is relevant with the voltage across the capacitor undergoes large and rapid transients. 7.2.2.7
Series Connection of Capacitors
Sometimes capacitors are series connected in order to get the required voltage rating. However, if precautions are not taken one will find that one of the capacitors will be supporting more of the voltage than the other. This is due to the fact that the capacitance of so-called identical capacitors are not the same. Since the same current flows into each capacitor, then one will inevitably have a higher voltage than the other. The way to force better sharing of the voltage across the capacitors is to parallel resistors with the capacitors, as shown in Figure 7.2. This arrangement will keep the capacitor voltages equal at DC, but depending on the values of the resistors and capacitors, there may be some degree of imbalance in a situation where there is a large ripple.
7.2.3
Diodes
There are two main types of diodes used in SMPS circuits – normal restifier diodes, and Schottky diodes. We shall see in Section 8.2.1 that there are special PN junction diodes required for very high powered applications, but we shall not be considering these here. 7.2.3.1
Schottky Diodes
Schottky diodes are constructed using a metal-semiconductor junction, as compared to a normal diode which has a semiconductor-semiconductor PN junction. The special property of the Schottky diode is that it does not have the charge storage problems that normal PN diodes have. Consequently these diodes will turn off almost instantly when a reverse voltage is applied to them. The other
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Introduction to Practical Design of Switch Mode Power Supplies
+
+
Figure 7.2: Method of voltage sharing for series capacitors. advantage if the Schottky diode, as compared to the PN diode, is that the forward voltage drop is much lower – approximately 0.2V for the Schottky, and 0.6V for the PN diode. There are a few caveats associated with Schottky diodes – they can only operate at fairly low voltages, up to about 100V; the higher voltage Schottky diodes tend to have a forward voltage that is approaching a PN diode; the internal space charge capacitance of a high voltage Schottky diode can be high, thus resulting in reverse current when the capacitance is charging as the diode is reverse biased. 7.2.3.2
reverse recovery
PN diodes
These are the conventional diodes. They are available in many different types, from “slow” rectifer diodes, to ultrafast signal diodes. The latter are more akin to the diodes used in SMPS circuits. The ultrafast refers to the reverse recovery characteristics of the diode. The fast diodes have the ability to get the stored minority charge out of the diode very rapidly when the device is reverse biased. Whilst the stored charge is disappearing the diode is able to conduct current in the reverse direction. This phenomenon is known as reverse recovery. v +
-
i Forward current
-
v +
i Reverse recovery current
Figure 7.3: Reverse recovery in a converter secondary circuit. Reverse recovery can have a variety of effects from poor converter efficiency,
7.2 Component Selection
233
Forward current
+
Reverse recovery current Figure 7.4: Reverse recovery in a boost converter circuit. to destruction of power devices. These two situations are illustrated in Figures 7.3 and 7.4. In Figure 7.3 one can see that when the voltage across the diode reverses, the diode will conduct current for a short period of time. This current could potentially be very large since the impedance opposing it would be small, and the voltage driving it large (a combination of the output filter capacitor voltage in series with the voltage appearing across the secondary of the transformer winding, which would now aid the reverse current flow). Clearly this situation is not good for converter efficiency, and the rapid rate of change of the reverse flowing current through the diode would result in a lot of EMI being produced. Figure 7.4 is a basic schematic of the boost converter circuit. When the MOSFET turns on energy is stored in the inductor, and the diode is reverse biased. When the MOSFET turns off the current has to continue flowing, and the diode immediately becomes forward biased. The current then flows through the the load and its filters. The reverse recovery problem occurs in the next event. The MOSFET again turns on to store more energy in the inductor. However, because the inductor has been forward biased it has stored minority carriers in it. When it becomes reverse biased, these minority carriers result in the diode conducting reverse current as well as it did when forward biased. The only limitation to the current flow is the impedance of the circuit, which is very low in this case. Consequently, in some circumstances the MOSFET may receive too much current and destory itself. Even if this does not happen there will be excessive power dissipated in the device, and large amounts of EMI generated. Practical Issue 7.5 Most converters will use either ultrafast diodes, or Schottky diodes to prevent reverse recovery problems. Remark 7.7 Synchronous rectifiers are a very low loss rectifier emplying a
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Introduction to Practical Design of Switch Mode Power Supplies MOSFET. Even with these devices a Schottky diode is placed in parallel with the MOSFET to take the instantaneous currents that need a path when the MOSFET is not on during the forward bias period. The body of a MOSFET has a parasitic diode around the device, but this diode is very slow. A Schottky diode in parallel with the device prevents the internal diode from being used. Remark 7.8 Ultrafast diodes themselves generate a lot of EMI. This occurs because an ultrafast diode still has reverse recovery current, the ultrafast bit being that it only last for a short period of time. However, as the diode rapidly decreases the reverse current, it generates a very rapid rate of change of current, and consequent EMI.
7.2.4
The BJT
I shall not spend much time on describing the practical issues of using Bipolar Junction Transistors (BFTs), since they are not commonly used today. For small to medium power SMPSs MOSFETs have large enough current and voltage range for most applications. For very high power applications, Insulated Gate Bipolar Junction Transistors (IGBTs) are more commonly used. We shall not look at these devices here since they will be described in detail in Section 8.2.4. Power BJT transistors were the device of choice for SMPS applications some 15 to 20 years ago. They are not used today because of the difficulty in using the devices. For example, power BJT transistors have a very low current gain (typically known as the β of the device), especially in higher voltage applications. This means that considerable current must be supplied to the base of the device if there is a large current from the collector to emitter. This may not be a problem for small converters, but it is an issue at larger powers. The consequence of this high current is a complex and expensive base drive circuit. A second problem is the voltage drop across the device. Even when a transistor is turned hard on the collector to emitter voltage is approximately 0.2 volt. Therefore the power lost in the device is approximately ic vce . A MOSFET on the other hand would have a much lower voltage drop, and therefore much lower power loss. A final problem with the BJT is turning the device off. As with the diode, the BJT is a minority carrier device. Therefore it also suffers from charge storage problems. Consequently, when the device is turned off it will continue to conduct current from the collector to the emitter until the stored charge disappears. Special base drive circuitry must be used to get rid of the stored charge as quickly as possible.
7.2.5
The MOSFET
As mentioned in Section 7.2.4, the MOSFET is by far the most common transistor used in SMPS systems. There are two main types of MOSFETs used – n-channel devices (the most common ones), and p-channel devices – useful in certain situations. The n-channel device turns on when there is a positive voltage exceeding the threshold voltage, between the source and gate of the device. The p-channel device is the dual of this, and turns on when the gate has a voltage that is negative compared to the source. If the source of the p-channel
7.2 Component Selection device is connected to the positive supply rail of a system, then the device can be turned on by simply connecting the gate to ground. Remark 7.9 One could consider the p-channel MOSFET to be a device that turns on with an active low signal, whereas the n-channel device requires an active high signal. Remark 7.10 The n-channel device is more commonly used because the resistance of these devices is less for the same size die. Consequently the cost for a given current rating is less. 7.2.5.1
Bi-directional Conduction
It should be noted that MOSFETs can conduct current in both directions – i.e. from drain to source, and source to drain. We have seen this fact used in synchronous rectifiers in Section 5.4.9. 7.2.5.2
Power Losses
There are three sources of losses in MOSFETs used in switching applications: Conduction losses These are the losses in the MOSFET resistance when it is on. The calculation of this loss is simple – P = I 2 RDSon . However, one should be aware that the MOSFET has a positive temperature coefficient, so as the device heats up its RDSon increases based on the typical expression: (7.7) R(T ) = R(25◦ C) × 1.0078e(T −25) Therefore to calculate the power, one must first work out an initial power using the 25◦ C value of RDSon , and then work out the temperature rise (using the package thermal resistance), and recalculate the power. This procedure is carried out iteratively until the power value converges to a value.1 Gate Charge Losses This is not really a loss in the MOSFET, but a lose in the gate drive circuitry driving the MOSFET. This is due to the fact that the gate of a MOSFET looks like a capacitor. Therefore in order to get the voltage of the gate to rise quickly a substantial current must momentarily flow into the gate. Many data sheets give the total charge to bring the gate voltage to a certain voltage level, Qg . If the voltage level you are using is different then a reasonable approximation is to multiply the Qg data value by the ratio of your voltage to the data sheet voltage. The power can then be calculated by using P = Qg V fs where fs is the switching frequency. Switching Losses This is a loss that is dissipated in the MOSFET itself. When a hard switching converter is turned off there is a period of time where the MOSFET is conducting a substantial current and is supporting a substantial voltage. During this period there is substantial power dissipation in the device. Clearly the more times the device is switched per 1 Usually this calculation only requires one or two iterations. The thermal resistance is a poorly known parameter, and if convergence does not occur then one is probably dissipating too much power.
235
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Introduction to Practical Design of Switch Mode Power Supplies unit time, then the more average power will be dissipated in the device. In order to roughly calculate the losses due to switching one can assume that as the device turns off or on that the voltage rises or falls as a linear function of time. Whilst this is happening the current through the device is more or less constant. Therefore the expression for the power dissipation for one on-off event would be the average voltage times the current – i.e. P = Ipk Vpk ts /2, where ts is the time for the on-off switching event. Therefore the total power dissipated over a one second interval (i.e. the total energy dissipated in the device per second) is the energy dissipated per switching event multiplied by the number of switching events per second – i.e. P = Ipk Vpk ts fs /2 Remark 7.11 By calculating the conduction and switching losses, and using the thermal resistance of the MOSFET package one can come up with an estimate of the temperature rise of the device. This estimate is a good measure of whether the device is going to run hot or cool. 7.2.5.3
MOSFET Gate Resistors
You should always put a resistor in series with the gate of a MOSFET. This is required because the gate capacitance in series with the gate lead inductance forms a high Q series LC resonant circuit. These circuits can oscillate at frequencies in the 100s of MHz range. They result in excessive heating of the MOSFET and the emission of copious EMI radiation from the circuit. The inclusion of the gate resistor provides the necessary damping to lower the Q of the resonant circuit so that any oscillations are damped out quickly. Practical Issue 7.6 If you have two MOSFETs in parallel you should put an individual resistor in series with each of the gates. If a single resistor is shared between two gates then oscillations can occur between the two MOSFET gates. 7.2.5.4
Maximum Gate Voltage
Some designers decide to make the gate-source voltage very high in order to get the gate voltage past the threshold voltage of the MOSFET in the minimum time. If the gate-source voltage exceeds approximately 20 volt, then the MOSFET is likely to be damaged. To turn a device on the most important thing is to have a very low impedance gate drive so that the current can be sourced to charge up the gate capacitance.
7.2.6
Operational Amplifiers
Operational amplifiers are used extensively in SMPS control systems. We have briefly considered control aspects of SMPS in Section 6.3. This discussion however, did not consider some of the practical issues involved in using Op Amps. These practical issues are related to the non-ideal behavious of Op Amps. Much of the following discussion is relevant to general usage of Op Amps, and is not particular to their use in SMPSs.
7.2 Component Selection 7.2.6.1
237
Offsets
There are two main types of offsets in Op Amps: 1. Input Offset Voltage. This is effectively a voltage between the + and − terminals of the Op Amp. It is a result of manufacturing differences between the electronics of the input circuitry of the Op Amp. The offset voltage is usually a small value – i.e. mV or µV. 2. Input Offset Current. The input impedance of a real Op Amp is not infinity. Therefore current will flow into the terminals. Due to manufacturing tolerances, the current in the + and − terminals can be different. The input offset current is very small in absolute terms – usually of the order of nAmp. Considering the small values for the offset voltage and current one migh be tempted to say; “What is the problem?”. The problem with the offsets is due to the fact that an Op Amp has a very high open loop gain, which is usually greater than 106 . Therefore, if one has, say a 2mV offset voltage at the input, then the output would be 2 × 10−3 × 106 = 2 × 103 . Most Op Amps operate on a power supply of 12 to 15 volt. Therefore the offset voltage would result in the output of the Op Amp being saturated to the supply rail. The immediate retort to the above paragraph is that Op Amps are never operated in open loop, but have feedback around them that lowers the effect gain. However, even with feedback, the gain can still be quite high, resulting in significant output offset voltage. Similar arguments can be mounted with offset current when there are resistances in series with the inputs.
+ LM2902 -
100k 9.09k
10k
Figure 7.5: Operational amplifier circuit for discussion of offsets. 7.2.6.1.1 Input Offset Voltage The following discussion is with reference to the circuit of Figure 7.5. This shows a typical Op Amp circuit, with the noninverting input shorted to ground. If the Op Amp was ideal then the output voltage would be zero under these conditions. However, the offset voltage for a LM2902 Op Amp is approximately 2mV. This means that there is effectively
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Introduction to Practical Design of Switch Mode Power Supplies 2mV between the + and − terminals. The gain of the amplifier is 10 in this case, making the output with a zero input voltage equal to ±2mV ×10 = ±0.02 volt. In many applications this may not be a problem. However, if the gain was 1000 then the output offset would be 2 volt, which is clearly unacceptable. Remark 7.12 Note that the output offset due to input offset voltage is not a direct function of the resistors used, but is related to the gain of the amplifier. 7.2.6.1.2 Input Offset Current The following discussion is also with respect to Figure 7.5. In this case we shall assume that the offset voltage is zero. Because the inputs to a real Op Amp take slightly different currents, then the voltage at each of the input pins can be slightly different due to the differeing voltage drops across the resistors. For example, in the case of the LM2902, the difference between the input currents can be as much as 5nA. Therefore the voltage difference between the two terminals can be 9.09 × 103 × 5 × 10−9 = 45µV. This voltage, in turn, is amplified by the gain of the amplifier to give 450µV output voltage. As with the offset voltage case, in many applications this is not serious, but if the gain is high, or very high precision is required, then the effect of the input current offset may cause significant output voltage offset. Remark 7.13 The effects of input current offset occur simultaneously with input voltage offset, therefore the output offsets have to be added together. Remark 7.14 Input current offset will become more pronounced if larger resistance values are used. Remark 7.15 More expensive amplifiers are laser trimmed internally in order to lower the input offset current. 7.2.6.1.3 Input Bias Current The input bias current is the current that flows into the input terminals even if there is no input offset current effect. The input bias current can cause offset problems if the resistances in the input terminal leads are mismatched. In the case of Figure 7.5 we have been careful to choose the resistors so that the effective resistance through which the bias currents flow is the same. However, if there is a mismatch in the resistance values due to resistor tolerances, or alternatively due to other external circuit considerations, then there will be different voltage drops across the input circuit resistors. This results in the generation of different voltages on the input pins to the Op Amp. As a specific example, if we assume that the resistor to ground from the non-inverting terminal is 19.09kΩ, and the input bias current for the LM2902 is 90nA, then the difference in the resistance seen by the two bias currents is 10kΩ. Consequently the bias current offset voltage is V = 90nA×10kΩ = 900µV. This voltage in turn is amplified by the amplifier gain of 10, giving an output offset of 9mV. Remark 7.16 Clearly, one should try and get the resistance in series with the Op Amp inputs to be the same values to eliminate the effect of bias currents on the output.
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239
Summary 7.1 Given the above discussion, we can develop and expression for the output offset: (7.8) V = [Vos + Ios R + Ib ∆R]Acl where Vos the input offset voltage, Ios the input offset current, Ib the input bias current, R the average value of the input resistors, ∆R the difference between the values of the resistors, and Acl the closed loop gain of the amplifier. Remark 7.17 One can see from (7.8) that in order to minimise the output offset one must: • Keep the resistor values as small as feasible to minimise the effect of the Ios current. • Make sure the input resistor values are closely matched so that ∆R ≈ 0 . • Choose an amplifier with a very small Vos . Note that a low Vos Op Amp often has a lower gain-bandwidth product. 7.2.6.2
Limits on Resistor Values
10MW 10kW +
10kW
Figure 7.6: Conventional inverting Op Amp circuit with a gain of 1000. It has been previously mentioned in Section 7.2.1.1 that it is not desirable in general to choose large values of resistors. In Op Amp circuits there is often a temptation to do this when one is endeavoring to get a high gain feedback amplifier. Let us consider the specific example circuit shown in Figure 7.6. This is a conventional inverting Op Amp circuit, and the resistors have been choosen so that the feedback gain of the circuit is 1000. The other requirement is that the input impedance of the circuit is 10kΩ. Consequently the feedback resistor is 10MΩ. This value of resistor is far too large to be practical. Besides the problem that it will pick up a lot of electrical noise, it may not even be effective since the leakage impedance across the PCB is probably lower than this value.2 2 If one did not have the input impedance constraint then a smaller value for the input resistor could be choosen so that the feedback resistor would be less than or equal to 1MΩ.
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Introduction to Practical Design of Switch Mode Power Supplies
R2
R4 R3
R1 vin
+
vo
R1
Figure 7.7: Inverting Op Amp circuit with alternative feedback network.
An alternative circuit that can be used in this situation is shown in Figure 7.7. In this case the feedback voltage is lower by the inclusion of the voltage divider network comprised of R3 and R4 . This result of this network is that the output voltage has to be higher in magnitude than it otherwise would be to get the full input current (vin /R1 ) to flow through the R2 resistor. The benefit that one obtains is that there is much more freedom to choose the resistors so that one can keep reasonable values and obtain the required gain. If one calculates the gain of the Op Amp circuit of Figure 7.7 then it can be shown that it is: R2 R4 + R3 R4 + R2 R3 vo =− (7.9) vin R1 R3 Let us consider the specific example of a gain of 1000. If we assume that the input resistance of the circuit has to be 10kΩ, then this makes R1 = 10kΩ. Let us then choose R3 = 1kΩ, which will result in a significant voltage division effect through the feedback network without having the other resistor values too large. We still have two other resistor values to choose – R2 and R4 . Let us arbitrary choose R2 = 100kΩ. The denominator of (7.9) now has a value of 10MΩ, which means that the numerator must have a value of 1010 Ω to achieve the required 1000 gain. The only unknown now is R4 . Substituting the known values into the numerator expression of (7.9), and equating to 1010 , one can calculate that R4 = 98kΩ. Therefore, to summarise, the resistor values are: R1 = 10kΩ, R2 = 100kΩ, R3 = 1kΩ, and R4 = 98kΩ. We have achieved the required gain from the circuit without having to resort to any resistor values greater than 100kΩ. This would reduce the noise pick of this amplifier circuit considerably. Remark 7.18 A similar feddback resistor arrangement can be used for inverting amplifiers. However, in this case one is not constrained by the input impedance requirement, and therefore one has more freedom to choose the resistors in the conventional non-inverting feedback amplifier.
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241
Gain (dB)
Aol
Gain bandwidth product
Acl
log f
0
fol-3db
fcl-3db
funity
Figure 7.8: Gain-bandwidth product of an Op Amp. 7.2.6.3
Gain-Bandwidth Product
Consider Figure 7.8 which shows a typical frequency response of an amplifier. The open loop gain, Aol , of the amplifier is very high – a gain greater than 106 is normal. However, the open loop frequency response rolls off at a very low frequency, usually 1 to 2 Hz. Since Op Amps are not designed to be used in open loop this is not a concern. Eventually the open loop gain of the amplifier goes to one. The frequency at which this occurs is the gain-bandwidth product of the amplifier. This figure is a constant for the amplifier. Therefore, if one applies feedback around the amplifier, this will lower the gain to say Acl . Therefore the roll-off frequency of the amplifier will be increased. The frequency of the -3db roll-off multiplied by the gain at this point is equal to the gain-bandwidth product. Therefore Aol fol−3db = Acl fcl−3db = funity . The importance of the gain-bandwidth product is that it indicates whether one can simultaneously achieve the gain and bandwidth specifications from an Op Amp circuit design. There are many different Op Amps available, with widely varying gain-bandwidth products. In SMPS applications one can find that high gains are required to moderate bandwidths – for example a gain of 300 and an bandwidth of 20kHz. In this case one would need an amplifier with a gain-bandwidth product of 300×20×103 = 6MHz. Whilst this is a very modest gain-bandwidth product for a discrete Op Amp, it may actually be larger than that of an integrated Op Amp that is inside a PWM IC. The effect of exceeding the gain-bandwidth product of the amplifier on the performance of the SMPS system may be poor disturbance rejection, or even worse instability (due to excessive phase shift in the feedback). 7.2.6.4
Phase Shift
Phase shift is related to the frequency response of the amplifier circuit shown in Figure 7.8. It is well known from control theory that at the -3dB point
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Introduction to Practical Design of Switch Mode Power Supplies of a single pole frequency response the phase shift from input to output is −45◦ . At approxmately a decade above this the phase shift has converged to approximatley −90◦ . In an Op Amp circuit the situation is often more complicated than this due to the effects of internal compensation within the Op Amp itself. This can result in even more phase shift due to the introduction of more poles in the higher frequency areas of the frequency response. The only way to accurately determine the phase shift characteristics of an Op Amp is to actually meaure them over the frequency range of interest. It is not always true that amplifier with higher gain-bandwidth product will have less phase shift. Remark 7.19 Excessive phase shift through an error amplifier in a feedback loop can result in a degraded phase margin. The result on the performance is ringing when there are step changes in the system, or marginal stability. 7.2.6.5
Slew Rate Limits
Slew rate limits are a non-linear effect related to the current limitations on the output stages of an Op Amp. Any Op Amp has a maximum rate at which the output can change. This is different from the gain-bandwidth product where one is assuming that the high frequency signals are very small in amplitude, and therefore do not encounter slew rate limit problems. Consider the situation where an Op Amp circuit is being driven by a sine wave. The maximum rate of change of the sine wave occurs when it goes through zero. The slope of the sine wave at that point is given by its derivative, Vm ω cos ωt, evaluated when ωt = nπ, n = 0, 1, 2 · · · . One can see that the maximum slope increases with both frequency and amplitude of the sine wave. Therefore, if the amplitude is increased at a given frequency then it may be possible to exceed the slew rate limit of the amplifier. If one had an amplifier of gain 10, with a 1 V p-p input sine wave input, then the output would be 10 V p-p. If the frequency of the input is 200kHz, then the maximum rate of change of the output would be 10 × 2 × π × 200 × 103 = 12.6V/µsec. Many low power Op Amps cannot slew their output this fast. When the slew rate limit is hit, the output tends to increase as a straight line at the slew rate. The slew rate becomes important in high-bandwidth SMPSs. When there is a rapid tranient at the output, the error amplifier will see a large input. If the output slew rate of this amplifier is hit, then it will effectively introduce a phase lag in the feedback. This can result in poor distrubance rejection. It could also affect phase margins.
7.2.7
Comparators
A comparator is a special type of Op Amp specialised for comparison applications. In relation to voltage and current offsets the same principles apply to the comparator. 7.2.7.1
Hysteresis
Almost always whenever a comparator is being used it should incorporate hysteresis in the input. This is to prevent false triggering and potential oscillation
7.2 Component Selection
243
of the device.
Vref -
vo
+
vin R1
R2 Figure 7.9: Comparator with hysteresis. Figure 7.9 shows a comparator circuit with hysteresis established by the judicious application of positive feedback. If one carries out a little analysis on this circuit then one can see: R1 R1 v+ = vin 1 − (7.10) + vo R1 + R2 R1 + R2 where v+ the voltage on the ‘+’ terminal of the comparator. To understand how this works, let us consider a specific example. Assume that R1 = 1k Omega and R2 = 100kΩ, which means that R1 /(R1 + R2 ) ≈ 0.01. Under this condition: v+ = 0.99vin + 0.01vo (7.11) If v+ < v− , then vo = −V , the negative supply voltage. If this is substituted into (7.11) and the expression is rearranged, then for v+ = Vref we have: vin =
Vref + 0.01V 0.99
(7.12)
Therefore the input voltage, vin , has to be greater than the reference approximately by 0.01V (it is actually a little more than this). At this input the comparator would switch so that the output voltage would become +V . We can then repeat (7.12) for this case and get: vin =
Vref − 0.01V 0.99
(7.13)
As we can see the input voltage has to be less than the reference voltage, again by approximately 0.01V for the comparator to reach the switching state. Therefore we have implemented classic hysteresis by the process, with the hysteresis band being approximately 0.01V around the nominal reference voltage.
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Introduction to Practical Design of Switch Mode Power Supplies 7.2.7.2
Comparator Interfacing
Comparators that have a single supply rail often don’t pull the output right down to the dround rail when the output should be zero. This can have a dramatic effect if the device is driving a BJT or a logic gate. For example, some comparators are only guaranteed to have a low output of approximately 0.6-0.7 V when sinking 6mA of current. Practical Issue 7.7 If the comparator output does not pull to near zero at the current level the output will be operating at, then the output voltage under the low condition must be accounted for when calculating the resistors for hysteresis.
+V
+V +
10kW
Figure 7.10: Interfacing a comparator to an NPN transistor. Figure 7.10 shows a technique for interfacing a comparator to a NPN transistor. If the comparator only pulls down to say 0.7V, then the 0.7V drop across the diode will ensure that the transistor is still off. The 10kΩ resistor ensures that the base of the transistor is firmly connected to ground when the diode is turned off. For the comparator to turn the transistor on the output needs to be greater than 1.4V.
7.3
Introduction to Magnetics Design
The design of magnetics for a real application is a complex task. there are many application specific decisions that have to be made – the core material, core style, type of conductor etc. There is usually no corect answer, since the particular solution that a designer ends up with depends on the criteria used to decide the optimal solution. The following discussion is far from an exhaustive treatise on the design of magnetic for SMPSs. The presentation closely follows that in [13], and will concentrate on some of the main practical issues. A more detailed treatment of the design on magnetics for SMPSs can be found in [12].
7.3 Introduction to Magnetics Design
7.3.1
245
Review of the Fundamentals
Before looking a the specifics of SMPS magnetics design, it may be opportune to review the fundamental concepts and expressions that are required. 7.3.1.1
Ampere’s Law
The law that connects the magnetic field intensity and mmf produced. It also connects the magnetic field intensity and the flux produced. The normal integral equation for Ampere’s Law in a physics or electromagnetics text is: F =
H · dl
(7.14)
where boldfacing means that the quantity is a vector, and F the mmf in Ampere-turns, H the magnetic field intensity vector in Ampere-turns/metre, and dl an incremental path length vector. The direction of the H vector is the same as the direction of the flux vector in a isotropic medium. The direction of the magnetic flux density vector, B, can be determined by other techniques, but is defined for practical purposes by the right hand rule. Let us consider the application of (7.14) to a single strand of wire. We know apriori that the F value in this case is I, the current being carried in the wire. Since the H and dl vectors are coincident around a circular path of integration (since the H vector is in the same direction as the B vector), and the total path length is 2πr, then one can conclude that: H=
I 2πr
(7.15)
where r the radius of the path of integration. Remark 7.20 Equation (7.15) implies that the magnetic field intensity can be defined as: mmf F NI H= = = (7.16) l l l The relationship between Ampere’s Law and the magnetic field intensity is defined by the follwoing: B = µr µ0 H = µH (7.17) where µr the relative permeability, and µ0 the permeability of free space. Equation (7.17) allows Ampere’s Law to be recast into a flux density form: F =
1 µ
B · dl
(7.18)
In certain circumstances Ampere’s Law can be used to evaluate the magnetic field intensity, and under some circumstances the magnetic flux density. Fortunately, the design of transformers is one of the applications where the geometry is constrained in such a way that Ampere’s Law can be successfully applied in a simple fashion.
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Introduction to Practical Design of Switch Mode Power Supplies 7.3.1.2
Faraday’s Law
Faraday’s Law is one of the fundamental laws of electricity. It was originally determined experimentally, and later derived from the more fundamental Maxwell’s equations, and subsequently from relativity theory. Every electrical engineer should know Faraday’s Law, but we will restate it here for completeness. Figure 7.11 shows a typical situation where Faraday’s Law is active. Here B(t)
Area A
v(t)
Figure 7.11: A loop of wire enclosing an area of time varying flux density. we have a loop of wire, and orthogonal to the surface of the loop there is a time varying flux density, B(t).3 A voltage, v(t) is generated between the ends of the wire under this circumstance. Faraday’s Law tells us the magnitude of the voltage under this condition: v(t) =
dφ dB dλ =N = NA dt dt dt
(7.19)
where λ the flux linkage, φ the flux, and N the number of turns of the coil. 7.3.1.3
Inductance
We know from Ampere’s Law that a wire produces magnetic field intensity, and consequently magnetic flux density. The inductance of a coil is a number that tells us something about how well the physical configuration of the coil produces flux density. For example, if a coil has more turns on it then it would have more inductance, if a coil has a large area then its inductance is larger, and it a coil is wrapped around a high permeable core material then its inductance will be higher. In all these situations, a higher inductance indicates that the coil is better at producing flux. The fundamental definition of inductance is: L=
dλ di
(7.20)
3 If the magnetic flux density vector is not orthogonal to the surface area, then it is the component that is that contributes to the Faraday voltage effect.
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247
In the case of linear magnetic materials (i.e. the flux density varies linearly with the current through the coil) this expression can simply be written as: L=
λ I
(7.21)
Remark 7.21 A verbal definition of inductance is that it is the flux linkage produced though the coil per unit current flowing through the coil. Remark 7.22 Equation (7.20) is evaluated around some point of operation. Strictly speaking this definition is called the incremental inductance, since it is operating point dependent (i.e. dependent on the values of λ and i). Equation (7.21) can be used to develop the expression for the inductance in terms of the physical parameters of a coil. From (7.21) one can write: N AB Nφ = I I NI Since B = µH = µ l µN 2 A ∴L= l L=
(7.22)
(7.23)
where l the length of the magnetic path. Remark 7.23 One can see from (7.23) that the inductance is defined entirely in terms of the physical characteristics of the coil. Note that the inductance is related to the square of the coil turns. Remark 7.24 In the case of a high permeability material as the coil the length of the magnetic path is easy to determine in (7.23). One can develop Faraday’s Law in terms of inductance using the flux form of Faraday’s Law and (7.22). From (7.22) one can write: N AB = Li
(7.24)
where the lower case i indicates that the current is changing. Substituting this into (7.19) one can easily see that: v=
dLi di = L for L constant dt dt
(7.25)
which is the familiar voltage relationship from circuits. Remark 7.25 Note that the L constant is not correct when the core material in a ferro-magnetic material which saturates. 7.3.1.4
A Note on Units
Unfortunately the area of magnetics is permeated with inconsistent units. This situation exists for largely historical reasons. Most of the unit confusion occurs between the mks system of units, and the cgs system. Just to make things even more confusing imperial units are also sometimes thrown in as well. Wherever possible I will use mks units in these notes.
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Introduction to Practical Design of Switch Mode Power Supplies 7.3.1.5
The Three R’s
In magnetic circuits three terms beginning with the letter R are often used – Reactance, Remanence and Reluctance. We shall briefly review these (most electrical engineering students should already know what they are). 7.3.1.5.1 Reactance This is a quantity similar to resistance that is used when a circuit contains reactive elements such as inductors and capacitors. The reactance can be used in a generalised form of Ohm’s Law. For an inductor the magnitude of the reactance is Zl = 2πf L where f is the frequency of the voltage across or the current through the inductor. The voltage across the inductor is related to the reactance by Vl = Zl I, where Vl and I are AC phasors. A similar situation occurs with capacitance, where the magnitude of the reactance is Zc = 2πf1 C . If both resistance and reactance are both present, the impedance magnitude is: (7.26) |Z| = R2 + Z 2 where Z is the generic impedance of the reactive element.
B Bm
Br
H
Figure 7.12: A BH loop for a magnetic material. 7.3.1.5.2 Remanence Figure 7.12 shows a BH loop for a ferro-magnetic material. Notice that if the H is applied so that b = Bm and then driven back to zero there is some remenant flux still in the core. The level of this flux is the remanence of the core, and varies depending on the material. If the core is air, then the remanence is zero. Remark 7.26 Remanence is important as it relates to core utilisation and losses. For example a core with high remanence used in a uni-fluxed SMPS will have a lower core utilisation. If use in a flux reversing type of SMPS the hysteresis losses will be high.
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7.3.1.5.3 Reluctance Reluctance is often used in circuit analogies of magnetic systems. Reluctance can be used in a way that is analogous to resistance in conventional circuit theory. Just as with resistance, the reluctance of a “magnetic circuit” is related to the physical attributes of the circuit. One way of developing the magnetic circuit analogy is to consider the mmf in a similar way to voltage is considered in a conventional circuit. This makes some intuitive sense because one can consider that the mmf is the driving force that produces the flux. We can subsitute (7.16) into (7.17) to give: B = µH =
µN I l
(7.27)
Multiplying both sides of (7.27) by the area of the core, A, gives: φ = BA =
µAN I l
(7.28)
This expression can be rearranged to make the mmf the subject of the expression: l φ (7.29) F = NI = µA From (7.29) we can then identify the reluctance term as: l µA
(7.30)
F = Rφ
(7.31)
R= Therefore (7.29) can be written as:
where the flux, φ, is analogous to the current in a conventional circuit. Remark 7.27 “Magnetic circuit” analogies are particularly useful in transformer applications because the magnetic paths are very well defined and their reluctances are known. Remark 7.28 Notice that the reluctance defined in (7.30) obeys the same intuition as resistance of wires. For example, if one doubles the cross-section of the core (i.e. doubling A) then the reluctance drops, just as resistance would if a wire diameter is doubled. Similarly, if the length of the core is increased then the reluctance increases. A similar effect also occurs with resistance.
7.3.2
The Ideal Transformer
It is beyond the scope of these notes to give a full treatise of transformers. Therefore we shall concentrate on the basic properties that are required to understand their design and operation in SMPS applications. We shall begin be considering the ideal transformer, since this is a useful concept to understand the operation of transformers. In addition, ferro-magnetic cored transformers are a reasonable approximation to the ideal transformer. Figure 7.13 shows the conventional circuit symbol for an iron cored transformer. The primary winding is the winding that is being driven by the source, and the secondary winding is usually connected to a load of some description.
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Primary coil
Secondary coil
N1 turns
N 2 turns
Core Figure 7.13: Circuit symbol for a transformer. The dots on the ends of the coils indicate the way that the wire is wound on the core. If current is injected into the lead at the dotted end of the primary winding, then the flux produced in the core will have the same direction as that produced by the secondary winding if current is injected into its dotted terminal. From a voltage viewpoint, if a positive voltage appears on the dotted terminal of one of the windings, then a positive voltage will appear on the dotted terminal of the other winding. An ideal transformer is a transformer that has a core material of infinite permeability. This means that no mmf is required to set up a flux in the core, since the reluctance of the core is zero (regardless of its length or area). The infinite permeability has the implications that there will be no leakage flux in the transformer – i.e. all the flux produced by the primary winding will link to the secondary winding. We can calculate some of the basic properties of ideal transformers by applying Faraday’s Law using the properties mentioned in the previous paragraphs. Consider the voltage on the primary side of the transformer: v1 = N1 A1
dB1 dt
(7.32)
dB2 dt
(7.33)
Similarly for the secondary we can write: v2 = N2 A2
Since both windings are wound on the same transformer core, then A1 = A2 . Furthermore, since there is no leakage of flux density from the primary to the secondary (and vice-versa), then B1 = B2 . Consequently we can write: dB2 v1 dB1 v2 = = = dt dt N1 N2
(7.34)
Remark 7.29 Notice that the implication of (7.34) is that the volts/turn of the transformer are constant for both the primary and the secondary.
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Since the ideal transformer requires not mmf to establish flux in the core, we can write: N1 i1 + N2 i2 = 0 (7.35) which implies: i1 i2 =− N2 N1
(7.36)
Remark 7.30 Equation (7.36) could also be deduced using conservation of energy together with (7.34): v1 i1 + v2 i2 = 0 (7.37) Using (7.34) one can write: v2
N1 i1 + v2 i2 = 0 N2 N1 ∴ i1 = −i2 N2 i1 i2 or =− N2 N1
(7.38)
Remark 7.31 The negative sign in (7.38) indicates that the secondary current direction is opposite to the primary current direction. Remark 7.32 The implications of (7.34) and (7.38) are that if the voltage is stepped up between the primary and the secondary then the current steps down (and vice-versa).
7.3.3
Real Transformers
Real transformers do not have core materials composed of infinite permeability material. The relative permeability of iron based laminations is in the range of 1000-2000. Many of the power based core materials, which are widely used in SMPS applications, have permeabilities in the low hundreds range. The consequence of having finite permeability core materials is that not all the flux that is produced by one winding is linked to the other winding. Another consequence is that it takes mmf to produce flux in the core, since the core has reluctance to be overcome. Models of real transformers are often based on taking the ideal transformer and adding some extra elements around it to account for the non-ideal behaviour. Consider the flux required in the core to induce voltages in the secondary winding. If the secondary winding is open circuit, and if we apply a voltage to the primary, then the voltage across the primary is related to the rate of change of flux in the primary inductance. A small proportion of the primary flux does not link the secondary winding, and this is called the leakage flux. The inductance associated with this flux is called the leakage inductance. Most of the flux produced by the primary links to the secondary winding, and this is called the magnetising flux, and the inductance associated with it is called the magnetising inductance. If the secondary winding has a circuit connected to it, then the voltage induced in the secondary by the magnetising flux will cause a current to flow in this circuit. Consequently there will be flux produced by the secondary winding.
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Introduction to Practical Design of Switch Mode Power Supplies Ideal transformer Magnetising inductance
Lm
Ll
Leakage inductance
Figure 7.14: Simplified model of a real transformer. This flux will be in such a direction in the core that it will tend to cancel the magnetising flux. However, the flux in the primary is fixed by the applied voltage and its frequency (via Faraday’s Law), therefore this cancellation of flux will result in more current being drawn from the primary circuit to compensate for the cancelled flux. This is effectively the load current on the secondary being reflected back into the primary circuit. These arguments lead to the diagram of Figure 7.14. Notice that the magnetising inductance effectively shunts current away from the ideal transformer. Therefore the magnetising current is “wasted” in the sense that it does not contribute to the output current.4 Similarly, the leakage inductance will support voltage across it, and this voltage does not appear across the primary of the ideal transformer, and will therefore not be transformed to the secondary. 7.3.3.1
Core Materials
As mentioned in the previous section real core materials have finite permeability. In addition they also exhibit properties such as saturation, eddy current and hysteresis losses. These practical issues manifest themselves in different ways in different applications. Table 7.3 summarises that main types of materials available, and their relative merits and uses. 7.3.3.2
Saturation
Saturation is a phenonmena in ferro-magnetic cores which causes the permeability of the core to change from the normal high value to a value near the permeability of air as the flux density in the core increases. Another way of stating this is that when the core saturates an increase in the current in the winding around the core results in only a very slight increase in the flux density in the core. Saturation is usually a phenonmena that one is wishing to avoid, since the incremental inductance of the core decreases dramatically as the core saturates. 4 The magnetising current is usually large so that the magnetising current is only a few percent of the load current of the transformer.
7.3 Introduction to Magnetics Design
Material
Consideration
Air
Pro Air core magnetics cannot saturate. Con The relative permeability of air is one, so one cannot get large inductances. Furthermore, the leakage of an air core transformer would be very high. Usage Primarily find application in rf circuits. Not used in SMPS applications. Pro Ferrite magnetic materials are very widely used in both electronic and SMPS applications. They have very high permeability and therefore can be used to produce large values of inductance. These materials are usually relatively low cost. A variety of different materials are available for different frequency bands (to help control the losses).
Ferrite
Con Ferrites usually saturate hard. Poorly controlled initial permeability.
Molyperm (MPP)
Usage Ferrites are often used in power transformers and noise filters. Pro Soft saturation. Wide variety of different permeabilities, and there values are well controlled by the manufacturer. Con Higher losses than ferrites at a particular switching frequency. Usage Used for inductors and noise filters at high DC currents. Pro Lower cost than MPP cores.
Powdered iron
Con Slightly harder saturation than MPP, and lower permeability generally than MPP.
Steel laminations
Usage Same applications as MPP where cost is a more important consideration than size. Pro Very high saturation flux density, allowing the production of very high inductances. Con Comparatively expensive, heavy. Saturates hard, and has high losses, especially at high frequencies. New amphorous iron overcomes some of the deficiencies in relation to losses. Usage Low frequency transformers, power inductors.
Table 7.3: Core materials and their uses.
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Introduction to Practical Design of Switch Mode Power Supplies If the core inductance is restricting current flow in the circuit, then this decrease in inductance could result in a catastrophic increase in the current. There are two types of saturation associated with cores – hard saturation, and soft saturation. Hard saturation refers to a rapid saturation – i.e. a small increase in the flux density results in a very rapid change in the permeability. Ferrites and steel laminations fall into this category. Soft saturation is where there is not a clearly defined saturation flux density, but instead the permeability changes gradually with increased flux density. MPP cores display this saturation characteristic. Remark 7.33 A core is said to be saturated if the current flow in the winding of the core has reduced its permeability to 20% of its permeability at very low currents. 7.3.3.3
Other Core Limitations
7.3.3.3.1 Curie Temperature This is the temperature where the core looses all its magnetic properties. When the core reaches that temperature the thermal agitation of the core domains is so severe that the domain alignment is destroyed, and hence the permeability of the material decreases. Once this starts then there is a form of positive feedback occurring, and the collapse of the field continues. As the field collapses the domains have less field to keep them aligned, and therefore the thermal agitation becomes even more dominant. For many of the magnetic core materials the Curie temperature is of the order of 200◦ C. This temperature is so high that the wire insulation and bobbin materials would be damaged it it were reached. Some inductors may not have a bobbin, and employ special high temperature wire insulation. In this case the Curie temperature could be an important limitation. 7.3.3.3.2 Core Losses Changing flux in any ferro-magnetic material results in losses in the material. These losses are in two different forms – Eddy current losses, and hysteresis losses. Eddy current losses are due to induced current in the core by the changing flux. These currents result in resistive losses. A general expression for Eddy current losses is [15]: ˆ 2 W/m2 (7.39) pe = ke ω 2 B where ke is a constant related to the particular type of material. The expression for hysteresis loss is [15]: ˆn ph = kh ω B
(7.40)
where kh and n are emphircal constant dependent on the type of material. Typical values of n are 1.5 < n < 2.5 for conventional lamination steel materials. Remark 7.34 Notice from (7.39) that the Eddy current loss is dependent in a squared sense on the applied frequency, whereas hysteresis loss in only linearly dependent on the frequency. Theefore it is very important to have a high resistivity for the core material in high frequency applications. The bonded type core materials such as ferrite, MPP, and iron powder to designed to achieve this.
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Let us assume that we have a magnetic structure, such as an inductor, that is driven by a sinusoidal voltage source. It is easy to show that the maximum flux density in the magnetic structure is: ˆ= B
V N Aω
(7.41)
where V the amplitude of the sinusoidal voltage source, and ω its frequency. N and A are the turns of the coil and area of the core respectively. ˆ is to be made Remark 7.35 One can immediately see from (7.41) that if B smaller, then N or A must be made bigger. Consider the situation where the power loss in the core of our magnetic structure is less than the total copper losses. Based on (7.39) and (7.40) we can see that we must increase the peak flux density experienced by the core, given that the excitation frequency is fixed, and the core dimensions are fixed. From Remark 7.35 one can deduce that this means that the number of turns wound onto the core must be decreased. This will result in a lower inductance for the core, and hence for a fixed supply voltage, a larger peak current. Therefore, even though the wire resistance would have dropped, the higher rms current into the core will result in higher copper losses.
7.3.4
Optimal Design Issues
It can be shown that minimum power loss is obtained in a combined electrical/magnetic structure if: • The core losses are equal to the copper losses. • The primary copper loss is equal to the secondary copper loss. Remark 7.36 The core losses equal to copper losses equality for minimum overall losses applies equally well to electrical machines as to inductors and transformers. Remark 7.37 Core losses equal to copper losses equality for minimum losses is analogous to the maximum power transfer theorem in circuit theory. You may recall that this theorem says that the load resistance should be equal to the source resistance for the maximum power to be transferred to the load from the source. Therefore, in this case one has the same losses in the source resistance and the load resistance.5 Assuming that one has a transformer type of structure, consider the following scenario. The power loss in the magnetics is less than that in the copper. Therefore, we wish to increase the power loss in the core and reduce the losses in the copper. The power losses in the core can be increased if the number of turns on the primary winding are decreased. This can be seen if we assume that 5 In the case of maximum power transfer one is trying to maximise the power. In electrical/magnetic systems the power is minimised.
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Introduction to Practical Design of Switch Mode Power Supplies the structure in being driven at a voltage source: v(t) = V sin ωt 1 v sin ωt dt (from Faraday’s Law) ∴ B(t) = NA V = cos ωt N Aω ˆ= V ⇒B N Aω
(7.42)
which is the same as the expression mentioned in (7.41). Remark 7.38 Equation (7.42) shows that the peak flux density in the core is increased if the number of turns in the coil are lowered. If the number of turns in the primary coil are lowered, then the length of the copper wire is lowered, and hence the wire resistance. If the turns in the primary is lowered, then the turns of the secondary are lowered to maintain the same turns ratio. If we maintain the same amount of copper under this condition, then we can increase the diameter of the wire, this again decreasing the resistance of the primary and secondary windings. These two effects mean that the overall losses of the secondary will be reduced, since maintaining the same turns ratio meaning that the secondary current would not change.6 One can mount a similar argument if the losses in the core are larger than the copper losses. In this case the turns on the primary are increased. To help keep the primary and secondary winding losses approximately the same one should allocate similar area to the primary and secondary windings. If the secondary has more turns, it must have proportionately smaller wire. If there are multiple secondaries, allocate their winding area by output power (higher getting more winding area). If one is designing an inductor, then the magnetic losses can be traded off against the copper losses by adjusting the cross-section of the core. For example, if the magnetic losses are low, then they can be increased by decreasing the core cross-section and therefore increasing the flux density. The total losses in the core are related to the losses per unit volume, and of course the volume of the core. If the cross-sectional area is decreased then the core volume drops in proportion to the decrease. The flux density increases in proportion to the decreased area. However, the total losses will increase since the losses per unit volume are related to the peak flux density squared. Example 7.1 Assume that the core cross-section of the typical transformer core has been halved. This will mean that the volume of the core has been halved. The result of the area increase, assuming that the mmf is the same and the core is not saturated, is that the peak flux density will double. The Eddy current losses ˆ 2 , therefore the losses per unit per unit volume in the core are proportional to B volume increase by 4. The total losses would therefore by 1/2 × 4 = 2 times those before the change in core area. 6 Note that in this discussion we are assuming that the losses in the primary due to the magnetising current can be neglected. The losses due to this component of the current actually increase with the reduction in the number of turns of the primary.
7.3 Introduction to Magnetics Design
7.3.5
257
Design of an Inductor
In this section we shall proceed through the practical design of an inductor. The reason for this is that this is the simplest magnetic structure that is useful in a SMPS design. For example, inductors are required in the buck converter for the output filter. In the following design we shall be referring to graphs from [2, 3], which is a data manual and selection guide for products by Ferroxcube, formerly Philips. The specifications for the inductor are shown in Table 7.4.
Parameter
Specification
Inductance DC current Max power dissipation Operation frequency Average voltage
35µH 2 Amp 300mW 250kHz 10V
Table 7.4: Inductor specifications. From Table 7.4 we need to calculate a few other values that will aid in the selection of a core material. We know from the maximum power dissipation specification that: R<
300 × 10−3 Pmax = = 0.075Ω 2 I 22
(7.43)
Remark 7.39 Equation (7.43) does not account for losses in the magnetic material. Therefore this value is simply an upper bound on the winding resistance. Let us check to see if we can consider this application to be a DC inductor application. The input voltage to the buck converter is 15V and the output voltage is 5V. Using (5.3) one can deduce that the duty cycle is 33% or 1/3. The switching period, T , is 4µsec. Using the circuit expression for the voltage across an inductor we can write: di =
10 × 4µsec × VL dt = L 35µH
1 3
= 0.381Amp pk-to-pk
(7.44)
Remark 7.40 The di in (7.44) is relatively small compared to the DC current of 2A, therefore the inductor can be considered to be fulfilling the function of the DC choke. Remark 7.41 The implication of (7.44) is that the permeability of the magnetic material should be fairly low to prevent the magnetic system from saturating. The other alternative is that a high permeability core be used with an air gap. Given that the inductor can be considered a DC power inductor (or a DC choke) one can consult [2] to find out what magnetic types are suggested for this application. The relevant table from [2] is shown in Figure 7.15. This suggests that the 2P range of iron powder cores are suitable for this application, since the operating frequency is less than 500kHz. One could also choose the
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Introduction to Practical Design of Switch Mode Power Supplies
Figure 7.15: Ferrite choice (from [2]).
Figure 7.16: Initial permeability with respect to frequency for 2P iron powder Ferroxcube material (from [3]).
7.3 Introduction to Magnetics Design
Figure 7.17: Incremental permeability as a function of magnetic field strength for 2P iron powder Ferroxcube material (from [3]). 3C range of cores – these cores have much higher initial µi compared to the 2P range. Since the inductance that we desire is not very high then we can afford to use a low permeability material. Another advantage of this is that one would not have to consider introducing a air gap to prevent core saturation. Figure 7.16 shows the initial permeability for a selection of different 2P iron powder materials with respect to frequency of operation. Notice that the relative permeability of the 2P90 material ia approximately 90 over the frequency range of interest. Another important, and related figure, is Figure 7.17, which shows the incremental permeability of the material versus magnetic field strength. The incremental permeability is the permeability of the material for small variations of the magnetic field strength on a DC bias field. This is precisely the situation that occurs in a filter inductor of the type we are designing. Given that we have decide to use a 2P type material from Ferroxcube, we firstly have to make an estimate of the number of turns required to obtain the desired inductance. An important parameter supplied by the core manufacturers is the AL value. This value is the inductance per turn for a particular core. Therefore, if we assume the initial value of permeability then we can come up with a first estimate of the number of turns required. Another important value that we have not considered as yet is the size of the core we are to use – for any given material there are a number of different core sizes. Factors that influence the core size are the wire diameter and number of turns required,7 and the maximum flux density that is allowed in the core. 7 The combination of the wire size influence the core size to the extent that the core must be big enough to physically allow the windings to fit on the core.
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Introduction to Practical Design of Switch Mode Power Supplies 7.3.5.1
Key Magnetic Parameters
A few notes on key parameters that appear in the data sheets and selection guides for magnetics would be opportune at this juncture. The following discussion is based on the parameters described in [3]. Note that we will not describe all the parameters in these sheets, but will concentrate on those that are most useful for the job at hand. 7.3.5.1.1 Initial Permeability This is the relative permeability at very low magnetic field intensity. It is formally defined as: µi =
1 ∆B µ0 ∆H
(7.45)
where ∆H → 0. 7.3.5.1.2 Effective Permeability This is the effective permeability of the material when an air gap has been introduced in the magnetic circuit. Its value is dependent on the initial permeability of the material and the effective air gap. The expression for the effective permeability is: µe =
µi 1 + µlieG
(7.46)
where: G the air gap length. le the effective magnetic circuit length. This expression is only valid for relatively small air gaps. For larger air gaps fringing effects will raise the value of µe above that calculated by the above expression. 7.3.5.1.3 Amplitude Permeability This is relationship between the flux density and field intensity at high field strengths with the presence of a bias field. The expression is: ˆ 1 B µa = (7.47) ˆ µ0 H Clearly the value of this parameter depends on the applied field strength due to the non-linear nature of the materials. 7.3.5.1.4 Incremental Permeability This is the small signal permeability when it is superimposed on a DC biased field. It is formally defined as:
1 ∆B µ∆ = µ0 ∆H
(7.48) HDC
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7.3.5.1.5 Effective Core Dimensions Many magnetic cores have irregular shapes. In order to allow design calculations on these structures the manufacturers supply a set of effective dimensions for the core. These effective dimensions are the dimensions of the toroidal core that will produce the same magnetic properties of the original core. The effective dimensions supplied are Ae the effective cross-sectional area, le the effective length of the core material, and Ve the effective volume of the core.8 Given the above values then the effective reluctance of the core can be written as: le Re = (7.49) µAe In many data sheets (e.g. in [3]) (7.49) is usually written as: 1! Re = µ
l A
(7.50)
" l where the term A is known as the core factor. Using the core factor one can calculate the inductance of the core using the following expression:9 L=
N2 Nφ = = I Re
µ0 N 2 " l 1 µe
(7.51)
A
If the magnetic structure is being driven by a sinusoidal source then it is simple to show that the peak flux density in the core is: ˆ= B
Vˆ N ωAe
core factor
peak flux with sinusoidal excitation
(7.52)
If the driving waveform is a square wave with a peak of V volts, then the peak flux density is given by: ˆ = πV (7.53) B 2N ωAe
peak flux with square wave excitation
Similarly the peak magnetic field intensity can be worked out using the effective length: ˆ = NI H (7.54) le
peak magnetic field intensity
Remark 7.42 The above calculations assume that Ae is uniform throughout the material. However, in many magnetic structures this is not the case. Therefore the peak flux density is calculated using the minimum cross-section area Amin . Most cores are designed so that Ae ≈ Amin so that there is no significant increase of flux density due to the physical core design. 7.3.5.1.6 Inductance Factor The inductance factor for a core is the inductance of a single turn coil for the particular core. This is related to the 8 All
the measurements are assumed to be in MKS units. that we are using the expression N I = φRe from magnetic equivalent circuits [16].
9 Note
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Introduction to Practical Design of Switch Mode Power Supplies magnetic properties of the core – i.e. namely the permeability. The definition of the inductance factor can be simply obtained from (7.51): AL =
1 µ0 µe 4π × 10−7 µe = " l = Henry " l Re A A
(7.55)
Usually AL is quoted in terms of nH, therefore (7.55) is written as: 1256.7µe AL = " l nH
(7.56)
A
The inductance factor is obviously related to the total inductance by the expression: L = N 2 AL (7.57) which means that for a given desired inductance the number of turns can easily determined by rearranging (7.57) to give: L N= (7.58) AL 7.3.5.2
Details of Inductor Design
Figure 7.18: Core type selection table (from [3]). Now that we have reviewed some of the key parameters that are required to understand magnetics data sheets we can now return to the design of the inductor. The material was previously chosen to be Ferroxcube 2P. The next step is to choose a core type and size. We shall use a toroidal or ring core. One can see from the table in Figure 7.18 that this is a favourable choice for this application. Many manufacturers provide tables to aid in the selection of a particular core. These tables not only allow a first guess at the core selection material,
7.3 Introduction to Magnetics Design but also suggest a specific core. This then gives one an initial core size to base a design on.10 This initial core selection for cores that have a DC current through the windings is often based on a graph that uses the energy stored in the core – i.e. 12 LI 2 . The L and I terms in this expression are both related to the size of the core, L via the core length and area, and the current by size of the area to put the windings in. Figure 7.19 shows the core size data and AL parameters for Ferroxcube iron powder 2P cores. Unfortunately the Ferroxcube selection guide does not have such a table for the iron powder cores. We shall select an initial core from the table in Figure 7.19 and then calculate the number of turns required. We shall use this, together with the specification on the power dissipation to work out the amount of area required in the centre of the core for the winding. Depending on the result of this we may have to select another core. One other criteria for the selection of the core that was not previously mentioned was that one would generally want the core to be as small as possible, since this usually correlates to minimum cost. Let us arbitrarily choose core TN17/9.8/4.4 2P90 from Figure 7.19. As can be seen from this figure AL = 42, therefore using (7.58) one can get: 35 × 10−6 = 28.9 turns (7.59) N= 42 × 10−9 This has to be rounded up to an integer number of turns, so let’s make it 29 turns. The next thing to consider is the amount of wire required for this. The turns have to be wound around the toroid, so that the copper passes through its centre. The size of the centre of the toroid places a limit on the number of turns for any gauge of wire used. Taking into consideration the difficulties of winding the core, as well as the amount of space taken by wire insulation, the typical winding fill factor is 45–50% – i.e. only 45–50% of the available space for the winding can practicably be used. To select the wire we need to consider the amount of current that it has to conduct, and the amount of power that will be dissipated in its resistance. The skin effect should not be that important in this case since the high frequency AC currents are relatively small compared to the DC current flow. A first selection of the wire can be made from a wire table. We shall use the table printed in [13], which is itself a reprint of a table produced by Magnetics Inc. in their literature.11 One candidate size is AWG18 wire, which nominally has a current capacity of 2.17 Amp. The resistance of the wire per metre is 0.02096Ω/m, and its wire area (including insulation) is 9.83 × 10−3 cm2 , or 9.83 × 10−7 m2 . Referring to Figure 7.19 we can work out the length that the wire has to go around the core (approximately) as 19.5mm or 0.0195m. However, this value doesn’t take into account the fill factor which effectively extends the length of each turn. An approximate expression for the length of a turn for a toroidal core is [13]: (7.60) lt = D + 2H where D and H are as defined in Figure 7.19. Using (7.60) the length of a turn is 0.0181 + 2 × 0.0053 = 0.0287m. 10 Often this initial selection may prove to be inadequate in some detail. The designer may have to choose a larger or smaller core dependent on the nature of the inadequacy. 11 The Magnetics Inc Web site, http://www.mag-inc.com, has a free program that can be downloaded for the design of filter inductors.
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Introduction to Practical Design of Switch Mode Power Supplies
Figure 7.19: Core data for toroidal cores using powdered iron (from [3]).
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Using the number of turns calculated in (7.59) we can calculate the resistance as 29×0.0287×0.02096 = 0.01744Ω. Therefore the power loss in the windings is approximately I 2 R = 4 × 0.01744 = 70mW. This is well within the specification of less than 300mW total power loss, and leaves 230mW for the core losses. The other issue to examine is whether the wire can be wound on the core – i.e. will it fit in the hole in the centre. The total wire area, including the insulation, is 29 × 9.83 × 10−7 = 2.85 × 10−5 m2 . The total area available in the centre of the core is πd2 /4 = 6.65 × 10−5 m2 . A fill factor is 0.5, therefore the area available for the wire is 0.5 × 6.65 × 10−5 = 3.325 × 10−5 m2 . Therefore it is possible to wind the wire on the core. Remark 7.43 One must also take into account the thickness of the wire. If wire is too thick then there will be trouble bending it around the core. In addition, the act of bending it around the core may also fracture the core, since ferrite and iron powder materials are very brittle. We now need to check the core flux density. This can easily be done using (7.51) and the Ae value from Figure 7.19 to give: B=
LI 35 × 10−6 × 2 = = 152mT N Ae 29 × 15.8 × 10−6
(7.61)
Remark 7.44 The maximum flux density is not related to the losses in this situation, since it is primarily a constant flux density which does not cause losses. However, there is a ripple in the voltage across the inductor, that results in a ripple in the inductor current, and consequently an AC component sitting on top of the DC flux density. It is this component of the flux that is relevant to the loss calculations. Remark 7.45 The DC flux density is important because of the effect that it has on the permeability of the material.
Figure 7.20: Typical BH characeristic for 2P magnetic material (from [3]).
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Introduction to Practical Design of Switch Mode Power Supplies If we consider the BH characteristic for the 2P materials (from [3]) shown in Figure 7.20 one can see that the flux density level is far below saturation. Figure 7.21 shows the losses for 2P material at various peak flux densities and frequencies. These plots are very difficult to read with any accuracy. The best approach is to form an equation for the relevant line on the graph.
Figure 7.21: Losses in 2P material with respect to flux density and frequency (from [3]). The equation for a line on the graph is of the form: Pv = aB x
(7.62)
where a and x are unknowns to be found. Since we have two unknowns then we need two independent equations to find them.12 Considering Figure 7.21 we can write the following two expressions by examining the 200kHz curve: 28 × 103 = a × (4 × 10−3 )x −3 x
800 × 10 = a × (20 × 10 3
)
(7.63) (7.64)
Multiplying (7.63) by (800×103 )/(28×103 ) and equating to (7.64) we can write: 800 a × (4 × 10−3 )x = a × (20 × 10−3 )x 28
(7.65)
Cancelling out the common expressions, and taking logarithms of both sides of this expression we can write: log(28.57) + x log(4 × 10−3 ) = x log(20 × 10−3 )
(7.66)
which can be solved to give x = 2.0829. We can then subsitute this into either (7.63) or (7.64) to give a = 2.766×109 . The resultant equation can be multiplied 12 Even using this technique it is difficult to get accurate results since it is hard to read off the points to develop the simultaneous equations.
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by 250/200 = 1.25 to account for the fact that it has been derived for a frequency of 200kHz (this is a crude extrapolation). Therefore the resultant expression for the losses is: 3 (7.67) Pv = (3.4575 × 109 )B 2.089 W/m at a frequency of 250kHz.13 We are now in a position to calculate the losses. However, before doing this we must calculate the AC component of the flux density in the material (as noted earlier). Recall from (7.44) that the current ripple through the inductor is 0.381 Amp. Therefore the AC magnetic field intensity is: ˆ AC = N IAC = 29 × 0.381 = 274.85A/m H le 0.0402
(7.68)
Assuming that the core relative permeability stays at 90 then we can work out the peak to peak flux density as a result of the ripple current: ˆAC = µ0 µe H ˆ AC = 4π × 10−7 × 90 × 274.85 = 0.031Tesla B
(7.69)
ˆ value from (7.69) in (7.67) to give We can now work out the losses by using the B 3 Pv = 2.439e6W/m . For the volume of material in the core (Ve = 635×10−9 m3 ) the loss is Pv Ve = 1.54W. This power dissipation is outside the specification for the inductor by a factor of 5 times. Therefore we must go back to the drawing board with this design.14 In order to lower the losses in the core we need to go to a larger core size. Let us try the TN24/15/7.5 core. We shall quickly go through the same design process as carried out above. In this case the AL = 61nH, and consequently: 35 × 10−6 N= = 23.95 turns (7.70) 61 × 10−9 Therefore we will make the turns equal to 24. Given the turns we can now work out the maximum AC flux density variation as: LIAC (35 × 10−6 )(0.381) BAC = = 0.0169 Tesla (7.71) = N Ae (24)(32.8 × 10−6 ) Substituting this into (7.67) gives Pv = 690, 162 W/m3 . Therefore the total power dissipation is PT = Pv Ve = 690, 162 × 1895 × 10−9 = 1.3 Watts. This is less than in the previous case, but is still approximately 4 times the specification. One might suspect that we will have trouble satisfying the specification from the small change in the losses for the change in the core. Indeed, if one chooses the largest core in Figure 7.19, TN33/20/11, we will still have trouble satisfying the specification. If this is carried out the core losses are of the order of 0.7 Watts, which is still twice the specification. The question is now what can we do. If we are to stick with the frequency of operation we need to find a core material with lower core losses. However, 13 This expression is only going to give a ball park figure for the losses. To get accurate values measurements must be taken. 14 The above design closely follows that in [13] which uses a similar permeability and size core. However, the resultant losses found in [13] are approximately 1/10th those found above. The Lenk analysis uses a complex mix of units, so I am assuming that there has been an error in one of the units conversions. I have been unable to find an error in the design calculations above.
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Introduction to Practical Design of Switch Mode Power Supplies if the frequency of operation is part of the design mix then we can make this lower. This will also have the effect of increasing the ripple in the current, so the inductance value would have to be varied to allow this specification to be satisfied. Let us briefly consider a drop in the frequency to 100kHz. If we want the same ripple of 0.38 Amp in the 2 Amp DC current then the inductance value can be found to be 87µH using (7.44). The turns can nw be found to be 32 turns using (7.58) and the value for AL = 87nH (for the TN33/20/11 core). Therefore BAC = 0.012 Tesla using (7.71) with the new values. Reading off the approximate value for the losses per m3 from Figure 7.21 we can see that it is approximately Pv = 70W/m3 . The core volume is 5200 × 10−9 m3 , and hence the total core losses are PT = Pv Ve = 0.364 Watts. This is still outside the original specification in relation to the losses, but it is much closer than those calculated previously. A further improvement can be made in relation to the losses by lowering the frequency further, but the number of turns required to achieve the higher inductances mean that check would have to be made to see if there is enough winding area. Remark 7.46 The fundamental problem with the above design is that the material chosen has too high a power dissipation per unit volume. The specification is much easier to satisfy if a lower loss material is chosen. For example, the 2P material we chosen has a lose of approximatley 200kW/m3 at 10mT flux density. The 3C material by the same manufacturer has losses so low (of the order of 1 rightarrow 2 kW/m3 ) that the manufacturer has not plotted them below approximately 10mT. Therefore the specification would have been satisfied if this, or a similar low loss material had been chosen at the outset. For example, in [13] the same design is carried out using MPP material manufactured by Magnetics Inc.. This material has a loss of 18.2kW/m3 at 10mT flux density. In this design the core losses turn out to be 140mW. Remark 7.47 The frequency of operation of this inductor would mean that Litz wire should probably be used. This would change the wire area calculations above. The skin effect at 250kHz needs to be considered. In fact if the frequency is above 50kHz the skin effect must be considered. 7.3.5.3
Issues in Forward Converter Transformer Design
We shall not go through a complete design of a forward converter transformer, but instead we shall highlight a few of the major issues that need to be considered. We shall do this in the context of the paper design. The following is based on an example in [13]. The basic design of a forward converter is shown in Figure 6.2. The input voltage to the forward converter is 48VDC, and the output voltage is 5VDC at 100 Watts. This implies that the output current is Io = 100/5 = 20 Amps. This is obviously a very high current, therefore it is important that the resistive losses are kept low for efficiency reasons. This means that the number of turns on the secondary should be low, and the wire should be a thick gauge. Let us consider the issues involved in selecting the turns ratio for the transformer.
7.3 Introduction to Magnetics Design 7.3.5.3.1 Turns Ratio = 1:1 This would imply that when 48VDC is applied across the primary there is 48VDC across the secondary (ignoring the leakage inductance of the transformer). The problem with this voltage is that one cannot obtain Schottky diodes above about 45 volt with a low forward voltage drop. One would require a diode with a voltage rating significant higher than 48 volt, therefore the forward voltage drop will be high. Remark 7.48 For high current outputs forward voltage drop is important. The loss is Vf Io , and this is being dissipated in the rectifer diode, or the free-wheeling diode. One can use synchronous rectifiers to overcome this problem, but this requires a significant increase in the complexity of the circuit due to their drive and control requirements. For the diode loss reason given above the choice of a 1:1 turns ratio is not a good one. 7.3.5.3.2 Turns Ratio = 2:1 The primary has twice the turns of the secondary, meaning that there is 24VDC on the secondary. This means that the duty cycle of the converter is approximately Vout /Vsec = 0.21. The current through the primary of the transformer (assuming that there is a constant 20 Amp current in the load) is 0.5 × 20 = 10 Amp. This quite a bit of current for a MOSFET switch. The losses in the MOSFET are approximately 102 × RDSon × 0.2. These losses may result in an expensive MOSFET, or alternatively a large heat sink. 7.3.5.3.3 Turns Ratio = 3:1 In this case the secondary voltage is 16 volt and the primary current is approximately 7 Amp. The duty cycle is 0.31. Therefore the losses are 72 × RDSon × 0.31, which is substantially lower than in the previous case. 7.3.5.3.4 Turns Ratio = 4:1 The secondary voltage in this case is 48V DC/4 = 12V DC. Therefore the duty cycle is Vout /Vsec = 5/12 = 0.42. This duty cycle is very close to the limit cycle of many of the popular PWM ICs (which are limited to duty cycles of 0.45). If there is any variation in the input voltage, and if the diode drops are accounted for, then it is possible for this limit to be hit. The conclusion of the above turns ratio scenarios is that a turns ratio of 3:1 is probably the best one to choose. The remainder of the design of the forward transformer involves the choice of the core material and the magnetising current. The magnetising current is important, since this current does not contribute to the load current, but does contribute to the losses in the converter. The magnetising inductance is also important from the point of view of losses in the core. Fortunately, lowering the magnetising current involves increasing the primary turns (whilst maintaining the 3:1 turns ratio), which in turn also lowers the flux density in the core (for a fixed input voltage). There is a limit to how far this can be taken, since the more turns requires more copper in both the primary and secondary. Hence this impacts on the size of the transformer.
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7.3.6
Design of Manufacturable Magnetics
Magnetic components are usually custom made in a factory, unlike most other electrical components which are mass produced in an automated fashion. This means that when we design some magnetics for a product that will be mass produced we need to take into consideration how easy it is to manufacture, and also how repeatable the specifications will be in a manufacturing environment. 7.3.6.1
Wire Gauge
The general rule in relation to wire gauge is simple – don’t select wire that is too thick or too thin. Practical Issue 7.8 It is best to limit the wire gauges to a maximum of #20 (i.e. 7.91 × 10−7 m2 ) and an minimum of approximately #38 (i.e. 0.132 × 10−7 m2 ). For wire gauges thcker than #20 some machine cannot wind the cores, and above #18 there is a risk of fracturing the core as the wire is wound around it. Wire gauges thinner that #38 can still be machine wound, but it is difficult to build prototype cores with wire this thin – it is as thin as a human hair. Therefore it is best to use #38 wire even if you can get away with thinner wire. Another aspect of wire gauge to consider is that one should try and limit the number of different wire gauges being used. This will allow some volumeof-purchase economies to be obtained. 7.3.6.2
Wire Gauge Ratio
If you are winding different wires onto a magnetic structure, and these are layered on top of each other, then try and keep the wire gauges close together. This helps prevent the thinner wire from finding its way into the crevices of the thick wire – the different windings do not form nice layers. When this happens it can effect the leakage and coupling of the magnetic circuit. Practical Issue 7.9 Try to keep the wire gauges in a magnetic structure within 10 of each other. 7.3.6.3
Toroidal Core Winding Limits
If a toroid is going to be machine wound then the only limit on the windings is the size of the winding area and the size of the wire. However, if one is to hand wind these cores there is a practical limit set on a human’s ability to concentrate and count. Practical Issue 7.10 Hand winding a toroidal core is a real pain. If one is going to wind a prototype one by hand it is best the keep the number of turns below approximately 200. It is very easy to forget the number of turns on the core (even for this number).
7.3 Introduction to Magnetics Design 7.3.6.4
Tape versus Wire Insulation
For safety reasons tape is often used between the primary and secondary windings of a transformer. When there are high voltage differences between the primary and secondary a flanged bobbin may be used, which divides the winding area into two pieces with a piece of plastic. In many designs there is substantial voltages between the secondaries. Therefore insulation is required between these to prevent arcing. In the case of high voltage secondaries there may need to be insulation between the layers of the same secondary winding. Practical Issue 7.11 Adding tape insulation layers should be avoided if possible. The tape takes up a lot of area, and even more importantly it usually must be put on by hand. Remark 7.49 In many cases it may be better to go to thicker and higher class wire insulation instead of using tape. It is less labour intensive and can lead to a more compact design. 7.3.6.5
Layering of Windings
The windings should be wound from the left of the bobbin to the right and then back from the right to the left for each of the layers (except for a toroid). The windings should take into account where the connection pins are, and should be designed so that a winding does not terminate half way up the bobbin. If this does happen then one would have to take the end connection to the top or bottom of the bobbin to connect to the end pins. Any other layer will then have a lump in it where it goes over the top of this end connection. Practical Issue 7.12 One should take into account where windings will end when selecting the wire gauge. One should ensure that the winding does not terminate in the middle of layer. The other issue in relation to the windings is the coupling. The windings should be bifilar wound in order to maximise the coupling and minimise the leakage inductances if there are no safety considerations. In order to do this the wires should be twisted together. This is often carried out with multiple secondary windings to improve the cross-regulation. The primary and secondary windings should be interleaved if possible. This enhances the inter-winding coupling from primary to secondary, and also helps in relation to cross-regulation with respect to multiple secondary windings. Figure 7.22 shows the basic structure of an interleaved winding transformer that has also been designed to achieve good isolation between the primary and secondary windings. 7.3.6.6
Number of Windings
Magnetic coupling issues limit the number of windings that can be practically wound on a core. In addition the layering becomes more difficult. Finally, most winding bobbins only have 8 to 12 pins available for the end connections. Practical Issue 7.13 Most magnetic designs should be limited to a maximum of four to six windings.
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Introduction to Practical Design of Switch Mode Power Supplies High dielectric sleeving
Primary winding Secondary winding
Mylar tape
Primary winding Bobbin
Figure 7.22: Winding interleaving for high-dielectric isolation and good primary to secondary coupling. 7.3.6.7
Potting
Potting is the process of filling up a volume surrounding a magnetic structure with a thermally conductiove compound for the purpose of improving heat removal by providing a better thermal path. It also strengthens the structure, and prevents the incursion of environment factors that may affect the life of the magnetic structure. The potting can also be utilised to provide mechanical mounting points for the structure. There can be some problems with potting – it makes the unit heavier, the shrinkage of the potting mix as it cures can result in changes to air gaps in gapped cores, and some magnetic materials (e.g. MPP) are strain sensitive, and their permeability can change as the potting shrinks. 7.3.6.8
Safety Requirements
If one has high voltage and low voltage windings wound on the same core then it is important from a safety perspective to ensure that the high voltages can never get to the low voltage windings. Figure 7.23 shows a transformer design which satisfies requirements for isolation. There is a 2mm creepage distance from the end of the insulation tape to ensure that the windings can never come into contact. In addition, leads that pass through other windings must have a high voltage insulation rating. The windings are insulated from the core material. All these requirements take up space, therefore a transformer satisfying these requirements will be larger.
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273
Insulation layer Creepage distance (4mm)
Insulating tape
Core
High voltage sleeving
Secondary Primary Figure 7.23: A transformer design to satisfy safety requirements.
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Introduction to Practical Design of Switch Mode Power Supplies
Part III
Line Commutated Converters and High Power Inverters
Chapter 8
Introduction to High Power Converter Technology 8.1
Introduction
This part of the course is an overview of power electronics that is focussed on high power applications. The previous two parts of the course were primarily concentrating on very low power digital switching, and small to medium power switching primarily related to dc-dc power supplies. The term high power is not a precise term, and the distinction between switch mode power supplies and some of the circuits in the following chapters are blurred. It will be assumed that the circuits in the following chapters are used for power levels greater than 1.5 to 2kW, with the top power levels being open ended. For example, the power electronics used in high voltage dc power transmission can be handling many hundreds and possible thousands of megawatts. The other feature that distinguishes many of the circuits in the higher power area are that they rely on natural commutation to turn off the power devices – this means that they cannot be explicitly turned off using a gate signal, but rely in certain external circuit conditions to cause them to turn off. The subject material for a course on this topic is huge, and more than enough to fill an entire course in its own right. Therefore we shall be looking briefly at a subset of the possible topics, concentrating on the fundamental converter types and operational principles. Specifically we shall look at the power devices that are used in the high power area, since they have a large influence on the circuits, topologies and applications. The next major part is on the line frequency uncontrolled and phase controlled rectifiers and inverters. Next we look at hard switched dc-ac inverter technologies. The final part will consider the application of these devices in electric machine drive systems. There are many references for this work, but the primary ones used for this course are [4, 11, 17, 18].
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8.1.1
Applications of Power Converter Technology
Power electronics is becoming increasingly important in the modern world. The ability to control and transform power to forms suitable for particular applications is fundamental for the operation of any technological society. The increasing emphasis on efficiency is spawning even more activity in the Power Electronics area, as new techniques are needed to minimise the production of green house gases. The developments in the power semiconductor area are allowing the application of power electronics in areas that, only a few years ago, were impossible. Examples of modern applications of power electronic converter systems are: • Electric vehicle propulsion systems. These systems are one of the very high profile applications of modern power electronics. They incorporate innovative electrical machines coupled with inverter, computer and battery/generator technologies. • Electronic washing machines. A current example of is the Fisher-Paykell Smartdrive washing machine, which utilises a direct drive 48 pole permanent magnet motor driven by a computer controlled inverter. The Maytag Neptune washing machine in the US uses an electronically controlled switch reluctance machine. • Photovoltaic (PV) grid interfaces. In order to convert the power produced by photovoltaics into a form suitable for domestic use or to export into the grid, power electronic conversion is required. The application of clever control techniques can optimise the amount of power that can be supplied for given illumination levels. • High voltage dc transmission (HVDC) systems. These systems allow large amounts of power to be transferred in undersea cables. For example, the power connection between the north and south islands of New Zealand use a HVDC link. Similarly for connections from Norway and mainland Europe. HVDC links are also used to isolated the dynamics of large power supply systems. For example a HVDC link is used for the NSW to Queensland interconnection so that there is not interaction between the two different grid systems. • Frequency wild wind and hydro power applications. Conventional wind turbines rotate at a constant speed regardless of the wind speed. In order to extract maximum energy from the wind variable pitch blades are used. However, if the turbine is allowed to vary in speed (without the complex variable pitch bladed) then it is possible to extract even more energy from the wind. By interposing an inverter system between the generator and the grid supply, it is possible to do this, since the inverter converts the frequency wild input into the grid frequency output. The same issues apply to hydro turbines. • Power system static VAR compensators. These are power electronic devices that are able to supply the VARs required for inductive loads on power systems. They are commonly used to improve power factor and to aid in the stability of the power system.
8.2 Review of Power Semiconductor Devices • Active filters. Modern power electronic devices on the power supply grid can generate harmonics into the grid supply. These can cause problems with other devices connected onto the grid. An active filter is another power electronic device that is capable of cancelling out the harmonics produced by these other devices. • Flywheel and superconductor energy storage. These two storage techniques will possibly be important in future energy systems. Power Electronics plays a pivotal role in the operation of these systems, as it is required in order to get energy into and out of the energy storage system. • Aerospace power systems. Power electronics, because of the weight savings, play an important role in the power systems for both aircraft (civilian and military) and space systems. These applications of power electronics tend to be the leading edge of the technology. • Uninterruptible power supplies (UPS). These are power electronic systems that allow battery systems to be used as power backup for mains operated systems in critical applications. • Load proportional modulated air conditioning systems. Instead of turning air conditioning compressors on and off to maintain a desired average temperature, and inverter driven compressor motor provides variable continuous output. The saving are due to the fact that the compressor output does not match the energy input for a considerable time after the compressor is first started. Energy savings up to 30% are achievable using this technique. • Electronic fluorescent lamp ballast. These ballasts are based purely on a high frequency inverter of some type (no magnetic components). They offer energy savings over magnetic ballasts. Furthermore, external light compensation can also be incorporated into the design. The above examples are only a selection of the industrial and residential applications of power electronics. This technology is not always obvious to the user, but is being incorporated into a larger variety of products. Therefore an understanding of at least the basics of the technology is essential for the modern electrical engineer.
8.2
Review of Power Semiconductor Devices
At this point it is beneficial to review the current state of semiconductor devices used for high power applications. This is required because the operation of many power electronic circuits is intimately tied to the behaviour of various devices.
8.2.1
Diodes
Figure 8.2 shows the basic conceptual diagram for a diode. This diagram is valid for a general purpose diode, but power diodes have a different structure in order to improve the voltage blocking capability of the device and at the same time keep the on-state resistance as low as possible.
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Introduction to High Power Converter Technology The iv characteristics of conventional and power diodes are much the same, and a generic diagram is shown in Figure 8.1. Note the offset voltage of approximately 1 volt. It is this voltage that leads to the majority of the power dissipation. Also note the slope on the characteristic as the voltage across the device increases above 1 volt – this represents the effects of the bulk resistance of the device. Whilst the 1 volt offset is virtually intrinsic in the operation of the diode, the bulk resistance contribution to the power losses can be minimised by changing the doping of the semiconductor materials. The breakdown voltage, vBD , is a very important parameter in power diodes. Much of the design of these diodes is related to improving vBD .
iD
v BD » 1V
vD
Figure 8.1: The current-voltage characteristic of a diode. Figure 8.3 shows the conceptual structure of a power diode. Note that the main difference between this structure and that of Figure 8.2 is that there is a n− region interleaved between the normal p+ and n+ regions. This region is known as the drift region, and under reverse bias is the region where the depletion region lies. At first the presence of the n− region in the device would seem to be a little silly, since it must add to the bulk resistance of the device. Under certain circumstances this is indeed true, but by careful control of the doping profiles this effect can be minimised. This region is in the device to improve the voltage blocking capability. We shall not look at the equations that prove this, but heuristically the reason is that if one supports a voltage over a longer distance, then the volts per metre must be smaller than if the voltage is supported over a shorter distance. Therefore, when the device is in reverse bias, the depletion region almost exists entirely in the n− region1 , and consequently the electric field in the semiconductor material is lowered because of its length. As mentioned previously the problem with having the n− region would appear to be that the bulk resistance of the diode would appear to increase. This 1 The
depletion region supports the reverse voltage.
8.2 Review of Power Semiconductor Devices
Anode
Anode
281
Cathode
p+
Cathode
n+
Figure 8.2: Conceptual structure of a conventional diode.
Anode
Anode
p+
Cathode
n-
n+
Cathode
Wd Drift Region
+
vD iD
-
}
Forward bias voltage and current directions
Figure 8.3: Conceptual structure of a power diode.
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Introduction to High Power Converter Technology is true depending on how the diode is designed. There are two forms of structure in Figure 8.3: 1. The non-punch through diode. 2. The punch through diode.
non-punch through diode
The non-punch through diode refers to a diode where the depletion region lies entirely in the n− region under reverse bias. Therefore the depletion region does not punch through the n− region. Other the other hand the punch through diode has a the n− region a little narrower and more lightly doped. This structural change has two effects: 1. The same length n− region can support a larger reverse voltage.
punch diode
through
reverse recovery
2. The bulk resistance of the device is lower than that of a non-punch through diode. We shall not concentrate on the former effect, suffice to say that his is achieved by keeping the peak electric field intensity lower in the device [4]. The lower bulk resistance is achieved because of a conductivity modulation effect, this occurring because there is injection of carriers into the n− material not only from the p+ material, but also from the n+ material during forward bias. These extra carriers create in the n− region lower the bulk resistance of the region in forward bias. The other important property of diodes, and especially power diodes, is the reverse recovery. This refers to an effect when the diode can conduct a reverse current for a small period of time under reverse bias, after it has been forward biased. This effect is due to stored minority carriers that accumulate in the device under forward bias conditions. These carriers must be removed before the device can block voltage, and it is the removal of these carriers that constitutes the reverse recovery current. Figure 8.4 shows a typical reverse recovery characteristic of a diode. Initially the diode is forward biased and carries a forward current (i.e. anode to cathode). However as the current goes to zero it continues to flow in the reverse direction through the diode as the charge is removed from the device. Eventually all the minority carriers are removed, and the current then starts to decrease as the reverse voltage rises across the device. During this phase the depletion regions are being established. Eventually all the charge has been removed and the diode then stops conducting and it supports the full reverse voltage. The shaded area represents the total stored charge removed from the device. Remark 8.1 Charge storage and the associated reverse recovery has important practical consequences in power electronic circuits.
fast recovery
Alterations can be made to the semiconductor additives in power diodes in order to minimise the reverse recovery time. These diodes are known as fast recovery diodes. The recovery time of a normal diode can be 4 to 6µsecs, whereas a fast recovery power diode can have a recovery time of 1 to 2µsecs. Unfortunately fast recovery diodes have a relatively large forward voltage drop (≈ 1.5 volt). The other main type of diode that is used in power electronic applications is the Schottky diode. Because this diode uses a metal-semiconductor junction as
8.2 Review of Power Semiconductor Devices
283
iD
Reverse recovery time
t rr
Diode begins to support reverse voltage t
Qrr
Charge storage removal
Depletion region formation
Figure 8.4: Typical reverse recovery characteristic for a diode. the basis for the diode it does not have a charge storage problem. Furthermore, the forward turn-on voltage of the device is much lower than a conventional diode – of the order of 0.2 to 0.3 volt. One is tempted to ask the question “why aren’t Schottky diodes used everywhere in power electronics?”. The answer to this is that the Schottky diode cannot support large reverse voltages, and therefore is only suitable for low voltage applications (up to approximately 100 volt).
8.2.2
Thyristors
The thyristor, or silicon controlled rectifier (SCR) is essentially a controlled turn-on diode in terms of its external characteristics. They are the oldest of the semiconductor power electronic switches (invented in 1957 at General Electric research labs), but nevertheless, because of their characteristics, they will have continuing application in power electronics. They also have the highest power rating out of all the power electronic devices. Figure 8.5 is a conceptual diagram of a thyristor’s structure and its circuit symbol. Notice that the device is a three terminal structure, with the addition of a gate terminal. This diagram also shows that the device is a three junction structure, consisting of what appears to be two diodes in series. It should be noted that this linear semiconductor diagram is not really representative of how the device is physically laid out in silicon. To understand how the device works one can develop the approximate model
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Anode
Cathode Gate
J1
iA
J2 -
Anode
iK +
(n ) n1
p1
J3
p2 (n ) n2
Gate
Cathode
iG
Figure 8.5: Conceptual diagram of a thyristor. for the device shown in Figure 8.6. This diagram shows that the thyristor consists of a feedback structure consisting of a PNP and an NPN transistor. From ones knowledge of the behaviour of the transistor one can see that if a current is fed into the gate (terminal G) then transistor Q2 will turn on. This will result in the PNP transistor, Q1 turning on. Because the collector of Q1 is connected to the base of Q2, the current from Q1 forms the base current for Q2. If the current gain around the loop of the two transistors is greater than one then the initial turn gate current can be removed and the device will remain on.
Anode J1
i B1
Q1
J2
iC 2 Q2 J3
Cathode
iK
iA , iE 1
iC 1
iB 2
iG
Gate
iE 2
Figure 8.6: Transistor model of the thyristor. Under blocking conditions one wants the gain around the loop consisting of the two transistors to be less than one. This corresponds to α1 + α2 being small (which means that the transistor current gain product β1 β2 < 1), where α1,2 = iC1,2 /iE1,2 , . This is the normal state of the transistor. The thyristor is turned on by changing the effective α’s for the two transistors. This is achieved by changing the depletion region across the J2 junction,
8.2 Review of Power Semiconductor Devices which effective modulates the width of the bases of the two transistors. Therefore as a larger positive voltage is applied at the anode with respect to the cathode, the depletion region grows. Eventually the α’s will get to a point where the leakage currents across the junctions are enough to supply a current which will begin the regenerative process. This will cause the thyristor to turn on without any gate current. The voltage that has to be applied across the device to cause this to happen is known as the forward break over voltage. If a gate current is applied it is possible to cause the device to enter the positive feedback region prior to the forward break over voltage. The gate current causes carriers to be injected across J3 and diffuse to the depletion region at J2 . Here they are swept by the electric field of the depletion region into n1 . The result is that the depletion region at J2 widens to account for the minority carriers injected. This is due to the fact that more donor atoms have to be uncovered to account for the electrons injected from p2 . The net result is that the effective bases of the two transistors narrow, and consequently the α’s increase. Once these reach the critical value then the positive feedback will again occur and the device will latch on. The main point to note is that the gate current has achieved this at a lower voltage than the break over voltage. If the gate current is higher, then the lower the forward voltage can be when the device will latch on. The above discussion is captured in the iv characteristic of a generic thyristor shown in Figure 8.6. There are several points to note about this characteristic. If the gate current is zero, and a forward voltage is applied, then if the voltage reaches the level of vBO the thyristor begins to conduct. This is known as the break-over voltage. Once the device begins to conduct, the voltage across the device falls to a low level dependent on where the load line crosses the forward characteristic. Similarly if the thyristor is reverse to a level of vRW M , the maximum reverse working voltage, then the device will begin to conduct (as will a diode if reverse breakdown occurs). The vRW M voltage usually has about the same magnitude as the vBO voltage (by design). The most interesting aspect of the thyristor characteristic is the fact that the effective vBO voltage can be lowered by the application of a gate current. It is this fact that makes the thyristor behave as a switch. Once the device has “broken over” the device enters a negative resistance region prior to entering the forward on-state region. For the device to enter the forward on-state condition a minimum current, iH , must be flowing through the device. This is known as the holding current. If this current cannot be sustained then the device will re-enter the forward blocking state. Remark 8.2 Thyristors are still the device of choice for very high power applications. They are capable of withstanding very high voltages (of the order of 6-7kV) and can conduct currents in the range of 2-3kA. Remark 8.3 Another important characteristic of the thyristor is that the gate current does not have to be maintained after the current through the device reaches the holding current. However, on the downside, the gate current cannot be used to turn the device off. The device can only be turned off if the external circuit conditions allow the current in the device to fall below the holding current.
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forward break over voltage
holding current
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iA
Forward on-state
Increasing iG iG = 0 iH i BO
v RWM
vH
v BO
v AK
Forward blocking state
Figure 8.7: Typical characteristic of a thyristor.
There are two external aspects of the transient performance of these devices that are practically very important – the turn-on and turn-off limitations.
8.2.2.1
Turn-on Transient
Figure 8.8 shows a typical turn-on transient for a thyristor. There are several points that can be made about this diagram. After the gate pulse is applied there is a delay before the thyristor turns on (td ). This is due to the time that it takes the minority carriers to build up in the p2 material shown in Figure 8.5. After td the device starts to enter positive feedback and begins to turn on. The current in the device builds up with a slope of diA /dt, this being determined by the voltage and the external circuit inductance. Notice that during this period the voltage across the device is starting to fall quite rapidly, but there is still a substantial voltage across the device. Consequently there can be substantial power dissipation in the device during this phase. After the rise time period has finished there is a further period of voltage drop across the device known as the spreading time, ts . This is the time required for the current density to become even across the device cross-section. The diA /dt time is important, since if a maximum value is exceeded the device can be damaged. This damage occurs because there is uneven current distribution in the thyristor during turn on, and if the current is increasing too quickly hot spots may develop in the device (because there is not enough time for the current to spread adequately over the cross-section of the device).
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iG
t iA
di A dt
IA
t v AK
t td
tr
ts
Figure 8.8: Typical turn-on waveforms for a thyristor.
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Turn-off Transient
To turn-off a thyristor it must be reverse biased by actions of the external circuit for a minimum period of time. In general this minimum time is considerably longer than the turn-on time. Figure 8.9 shows a typical turn-off transient. The current decreases at a rate of diR /dt, this rate being determined by the external circuit. As with a diode, the stored minority carriers in the four regions of device result in current flowing in a reverse direction through it. The voltage across the device remains positive until either the junction J1 or J3 become reverse biased. Usually J3 becomes reverse biased first, this occurring at time t2 in Figure 8.9. At this point the voltage across the device starts to have a reverse voltage across it. The J3 junction cannot support a very large reverse voltage (20-30 volt) due to the high doping levels in the n2 and p2 junctions. Therefore this junction goes into avalanche breakdown. However shortly after the t2 the J1 junction starts to become reverse biased, and at this point the current through the device starts to decrease. iA
t rr di R dt t1
irr 4
t2
t3
t
irr
v AK dv F dt
t v REV
Turn - off time tq
Figure 8.9: Typical thyristor turn-off waveforms.
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The large reverse over-voltage is due to the effects of external inductances in the circuit. As the current through the device becomes zero, then the reverse voltage across the device becomes the steady state reverse voltage as imposed by the external circuit. In power diodes when the reverse recovery current reaches some nominal value of irr /4, then the device was said to have turned off. However, in the case of the thyristor there is still a substantial number of minority carriers in the interior n1 and p2 regions. If a forward voltage is then applied to the device at a rate of change of dvF /dt then a forward current can again occur as these carriers recombine and are swept through the device by the growing forward fields in the device. This current can produce an effect similar to the reapplication of a gate pulse, and the device can once again turn on. In order to prevent the device from turning on with the application of a forward voltage the following precautions must be taken: 1. If the device has been forward biased then it must be held in reverse bias for a minimum time of tq , a time specified by the manufacturer. This time is at least several minority carrier line times long. 2. The rate of change of the reapplied voltage, dvF /dt, must be kept below a certain value specified by the manufacturer. Remark 8.4 The maximum dvF /dt for slow thyristors is of the order of 100V/µsec. For devices intended for high frequency operation the dvF /dt is of the order of several thousand volts per µsec.
8.2.3
Gate Turn-off Thyristors
The Gate Turn-off Thyristor (GTO) is essentially a thyristor that can be turned off by the application of a negative gate current. This makes the usage of the GTO in dc supply situations much simpler, as compared to the thyristor.2 There are significant internal structure changes made to the thyristor in order to make it behave as a GTO. We shall not consider these in detail in this course. The GTO works essentially the same as the thyristor. Therefore we shall concentrate on the mechanism that effects the turn-off. If one considers Figure 8.6 it can be seen that: iB2 = α1 iA − iG
(8.1)
where iG is the negative of the normal gate current. From Figure 8.6 it is clear that by increasing iG one can bring Q2 out of saturation. The collector current for the Q2 transistor, iC2 , is given by: iC2 = (1 − α1 )iA
(8.2)
using KCL at Q1 . In order for the structure to turn off we need the following so that Q2 can no longer supply the necessary current to keep the total loop gain greater than one: iC2 (8.3) iB2 < β2 2 If a thyristor is used in a dc supply application it must be turned off using a forced commutation technique. These techniques will be considered in a later section.
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Introduction to High Power Converter Technology where β2 = α2 /(1 − α2 ). Using (8.1), (8.2) and (8.3) one can develop that following expression: iA (8.4) iG > βt off where the parameter βt off is the turn off gain given by: βt off =
α2 α1 + α2 − 1
(8.5)
Remark 8.5 From (8.4) one can see that the βt off value should be as large as possible to keep the iG value as small as possible. This implies that α2 → 1 and α1 should be small. Therefore the semiconductor regions in the GTO are designed to achieve this objective. 8.2.3.1
Snubbers and GTO Thyristors
Consider the circuit shown in Figure 8.10. This is a step down converter using a GTO and the switching element. There are several points that should be noted about this diagram: • The circuit symbol for the GTO (as compared to that of the thyristor). • The Ls on inductor and associated parallel resistor and diode form a turnon snubber3 circuit.
turn-on snubber
• The Cs off capacitor,associated resistor Rs off , and diode Ds off , form a turn-off snubber circuit. The Lσ inductance is an unwanted parasitic inductance. The turn-on snubber is required to protect the GTO from the large currents that can flow through it because of the reverse recovery of the freewheeling diode Df w , which is usually a slow device at the power levels that GTOs are used at. The presence of the series inductance Ls on limits that rate of rise of the current through the GTO. The resistor and diode components that are in parallel with Ls on are to dissipate the energy stored in Ls on when the GTO is turned off. These should be designed so that the energy in the inductor is dissipated before the next turn on of the GTO. When the GTO is turned off the voltage across the device would go to Vd almost instantaneously without the presence of a turn-off snubber. If the dv/dt across the device is too large then it will turn on, as was the case for the thyristor. The purpose of the snubber is to ensure that this cannot occur, since the voltage across Cs off cannot change instantaneously.
turn-off snubber
Remark 8.6 The use of a turn-off snubber with the GTO is absolutely essential. If the device is turned on prior to all the internal stored charge being dissipated, then there is a very poor distribution of the turn-on current, resulting in local heating and possible destruction of the device. This occurs because of the particular internal construction of the GTO. The presence of the turn-off snubber prevents the “automatic” re-turn-on of the device when the voltage rises across it too quickly. 3 A snubber circuit is an auxiliary circuit that is designed to protect the main switching element from excessive current or voltages.
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Load current
D fw
iL
Turn-on snubber
Rs_on
Vd
Cd
+
Parasitic inductance
Ls_on D s_on
Ls
D s_off
Rs_off
GTO
+
C s_off
Turn-off snubber Figure 8.10: An example of a dc chopper circuit using a GTO thyristor
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GTO Turn-on
We shall briefly look at what is required to turn on a GTO. Consider Figure 8.11. The turn-on is instigated by a pulse of gate current. The diG /dt and the peak iG should be large so that the device turns on rapidly and the current distributed evenly in the device. The gate pulse should last of the order of 10µ seconds or so to ensure that the turn-on process is complete. After this period a small gate current should be maintained to ensure that the device does not turn off again under low anode current conditions.4 This current is often known as the “backporch” current. iG
t w1
“Backporch” current iGT t
0 iA td
0
t
v AK
0
t
vGK
0
t
Figure 8.11: Turn on waveforms for a GTO thyristor. The other point to note in Figure 8.11 is the effect of the series inductance Ls on on the anode current during turn-on. Notice that diA /dt is limited by 4 This unwanted turn-off condition could also damage the device due to uneven distribution of the current in the device if there is a sudden increase in anode current.
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this inductance so that the current is distribute evenly across the device, and the voltage across the device is shared with the inductor during turn-on. This inductor also stops the otherwise large reverse recovery currents in the circuit. The reverse recovery actually results in the current overshoot represented by the overshoot during turn-on. 8.2.3.3
GTO Turn-off
Next we briefly consider the turn-off waveforms for the GTO. It should be noted that the effect of the snubbers cannot be ignored for the GTO, since it is essential that they are used under normal operation (as mentioned in Remark 8.6). In order to turn the GTO off then the gate current must be negative. The magnitude of this current is approximately 1/5 to 1/3 of the anode current being turned off. Therefore in high power applications this current can be substantial in magnitude. Fortunately the duration of the current is short. Figure 8.12 shows the waveforms during turn-off. The negative diG /dt should be kept as large, but it should not be made too large or undesirable tail currents occur in the anode current, and there is the possibility of device destruction. Therefore the diG /dt should be kept within the specifications supplied by the device manufacturer. The diG /dt value can be controlled by the design of the inductance in the gate drive circuit and the negative voltage applied to turn-off the device. During the time interval t1 , the growing negative gate current is removing charge stored in the two regions of the device. When enough of this is removed the regenerative action is stopped, and the device starts to turn-off (i.e. the anode current begins to fall). The growing difference between the anode current and the constant load current io flows into the snubber capacitor. There is a rapid rise of the voltage across the GTO due to the parasitic inductance of the snubber circuitry (this stray inductance has to be kept to the absolute minimum to kept this voltage small). After time t2 enough carriers have been swept out of the device for the gate-cathode junction to regain its reverse blocking capability. As the gate-cathode junction recovers it reverse blocking capability, the voltage across it starts to go negative, and the negative gate current starts to decrease. The inductance in the gate circuit tries to keep the gate current constant, and this results in avalanche breakdown of the gate-cathode junction during the time t3 – i.e. the gate-cathode junction is operating as a zener diode. This breakdown serves to remove further minority charge from the device. The t3 interval should be kept below a manufacturer specified value to prevent destruction of the gate-cathode junction. After the t3 period there is a continuation of anode current flow as the final stored charge is removed from the device. This is known as the anode tail current, and flows for time ttail . During this time the voltage across the device is growing at the rate of: dvAK io ≈ (8.6) dt Cs and contributes a lot to the turn-off losses in the device. Remark 8.7 A GTO should not be turned on too soon after it has been turned off because of the potential for poor current sharing in the device due to residual charge storage. The same applies for turn-off after turn-on.
GTO minimum on and off times
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iG
iGT
t
0
iA
t tail
t4
io
t
0 v AK t2 t1
dv dv < dt dt
Vd max
t
0 vGK
Inductive spike due to parasitic L in the snubber circuit. t
0 t3
vGG-
Figure 8.12: Turn-off waveforms for a GTO thyristor.
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Remark 8.8 If the anode current becomes too large there is the possibility that the gate current may not be able to turn the device off (there is a limit to the magnitude of the gate current, determined by the semiconductor properties of the device). This is a particular problem under short circuit conditions, since this is an abnormal condition that would not be designed for. Remark 8.9 Over-current protection can be achieved by using a “crowbar” to blow the fuse in the circuit if the current becomes too large. This concept is shown in Figure 8.13. The SCR across the dc link is fired, resulting in a short circuit on the link, and consequently the fuse will blow and protect the circuit. If the GTOs are used in an inverter structure then all the devices in the inverter can be fired simultaneously to carry out the same function. It should be noted that in Figure 8.13 we have not included the turn-on snubber. It is this snubber that gives the SCR the extra time to turn-on prior to the GTO destroying itself. Remark 8.10 One problem with the crowbar protection technique is that the presence of a fuse in the dc link introduces inductance in this part of the circuit. This can result in significant over-voltages when the main GTO is turned off.
Crowbar SCR
Short circuit
Fuse
Load
Figure 8.13: GTO thyristor circuit with additional “crowbar” SCR
Remark 8.11 There are several variants to the classical GTO that are being championed by different manufacturers. For example, Asea-Brown-Boveri (ABB) has the IGCT - the Integrated Gate Commutated Thyristor. This is essentially a modified GTO with tightly coupled gate drive circuitry built onto a card with the GTO power device. It is a high power device – 4.5kV and 3kA. The onboard GTO has low conduction losses and does not require a turn-off snubber. The better gating allows higher switching frequencies as compared to standard GTOs (of the order of 1000Hz). Rockwell/Allen-Bradley have a similar device called the SGCT – the Symmetrical Gate Commutated Thyristor.
turn-off failure under short circuit conditions
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8.2.4
Insulated Gate Bipolar Transistors (IGBTs)
One of the more recent devices that has become pervasive in the lower to medium power area is the IGBT – the Insulated Gate Bipolar Transistor. This device is essentially a specialise MOSFET – in fact the input is a MOSFET input. The main advantage of these devices is that they can be easily turned off by controlling the devices gate, but unlike the GTO this turn-off process does not require large currents. The basic structure of the n-channel IGBT5 is shown in Figure 8.14. One can see that the structure of the device is nearly identical to the MOSFET, the only major difference being the presence of the p+ injection layer. It is the presence of this layer that results in the injection of minority carriers into the device, and leads to the operation of the device being something like a MOSFET fed bipolar transistor. The advantages of the device are: • The result of the injection of minority carriers in the device is that it can carry much larger currents as compared to the MOSFET, since the current is carried in more than the channel of the device. • The presence of a lengthy diode junction in the device allows it to have a significantly larger forward blocking voltage as compared to the MOSFET. • The injection of carriers into the device means that the on-state losses for this device are lower than those of a comparable power MOSFET. Remark 8.12 One could consider the IGBT to be a “super” MOSFET. In many IGBTs the MOSFET part of the device carries the majority (up to 90%) of the current in the device (this is to help prevent a large amount of minority carrier storage from occurring, which slows down the turn-off of the device). The n+ layer between the p+ drain layer and the n− drift region is not essential for the operation of the device. As with the diode considered earlier, one can have punch-through and non-punch-through IGBTs. The n+ layer is required for the punch-through devices to prevent the J2 space charge region from going all the way to the p+ drain region. The presence of the n+ layer can significantly improve the operation of the IGBT. Remark 8.13 In Figure 8.14 there is a parasitic SCR shown. This is an undesirable feature of the structure, and design efforts must be made to ensure that the loop gain of the SCR is not greater than one so it does not turn on. The circuit symbol for the IGBT appears in Figure 8.15(c) and (d). Note that the symbol in (c) is very nearly the same as that for the n-channel MOSFET, except that there is an arrow on the drain connection indicating the direction of the current due to the injection of carriers here. Figure 8.15(d) shows a symbol that is emphasising the similarity of IGBT with the NPN bipolar transistor. 8.2.4.1
IGBT Operation
We shall briefly consider the salient points of IGBT operation. The following discussion is with reference to Figure 8.16. 5 The
layer types are all reversed for a p-channel device
8.2 Review of Power Semiconductor Devices Source
Gate
SiO2
SiO2 n
+
297
n
+
Body region
p
J1 J2
Ls J1
n
-
n+
Drain drift region Buffer layer
p+
Injecting layer Parasitic SCR Drain
Figure 8.14: A schematic diagram of the basic structure of the IGBT.
Figure 8.16(a) shows the current flows in the device when it is turned on. When the gate voltage exceeds the threshold voltage an inversion layer forms beneath the gate of the IGBT. This channel shorts the n+ to the n− layer, as occurs in the MOSFET. The current flow through this channel also results in holes being injected from the p+ region into the n− region. These holes move across the n− drift region via drift and diffusion via a number of paths. These carriers reach the p body region (not necessarily where the channel is) and then are swept through to the source via recombination at the source metallisation. The junction of the n− region and the p region is called the collector region, since is operates the same as the collector region in a thick PNP transistor. The connection between the layers and parasitic transistors is shown in Figure 8.16(b). Notice that the injection layer, denoted as the p+ layer, acts as an emitter in a BJT transistor, emitting or injecting holes into the n− base region of the device. As current flow through the IGBT there are voltage drops in the device due to the bulk resistance of the semiconductor materials used. These are shown in Figure 8.16 as dashed resistors. These resistance values are important for two different reasons; (i) if the resistances are too high then the device will dissipate more power; and (ii) if the voltage drops are too high in the resistances then parasitic thyristor in the IGBT may turn on. Figure 8.17(a) and (b) shown an equivalent circuit for the IGBT. Figure 8.17(b) is more complete, showing the parasitic thyristor, and the body spreading resistance. If the body spreading resistance is too high then the current gain of the thyristor may become greater than one, and consequently the thyristor will turn on. Once this happens then the device no longer behaves as an IGBT, and power must be remove across the device to turn it off. Needless to say, much design effort has gone into ensuring that the parasitic IGBT does not turn on.
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iD
Increasing vGS
v RM v DS
v DS brk
(a) » 0.7 V
iD
Drain Drain Gate
Gate
Source vGS th
vGS
Source (c)
(d)
(b)
Figure 8.15: The IGBT voltage and current transfer characteristics and circuit symbol: (a) output characteristic; (b) transfer characteristic; (c) and (d) nchannel IGBT circuit symbols.
8.2 Review of Power Semiconductor Devices 8.2.4.2
IGBT Turn-on
Typical turn-on waveforms for the IGBT are shown in Figure 8.18. These waveforms are very similar to those for a power MOSFET.6 We are assuming that the voltage to the input of the IGBT circuit is the voltage waveform vGG . The voltage across the gate-source of the IGBT is vGS . Note from Figure 8.18 that this voltage is essentially an exponential, due to the input capacitance of the IGBT, coupled with the gate resistor (which is to limit the current flowing into the gate of the IGBT to safe levels). The time period td(on) is the time required for vGS to reach a voltage where the device starts to turn on. From this point the current through the device rises as it starts to turn on harder. Eventually vDS is of the order of vGS and the current stabilises at a value determined by the external circuit. As vDS starts to fall a significant amount of current starts to flow through the Cgd capacitance. This is due to the fact that there is a changing voltage across the capacitor, and that the value of the capacitance increases considerably as the space charge region width decreases (effectively decreasing the plate separation in a parallel plate capacitor) and the stored charge in the device starts to increase. Consequently the rise of vGS flattens out as this capacitance is charged, this being the result of the extra current being drawn through the gate resistor. Eventually vGS restarts its exponential rise again when vDS ≈ vGS , stopping when its value reaches vGG . The vDS waveform during the tf v2 time in Figure 8.18 is usually observed in IGBTs. It is due to two effects – the above-mentioned increase in Cgd as vDS falls (which also occurs in power MOSFETs), and the slower turn-on of the PNP section the IGBT (as compared to the MOSFET portion), which delays the associated conductivity modulation due to the injected carriers. 8.2.4.3
IGBT Turn-off
The waveforms for the turn-off of the IGBT are shown in Figure 8.19. The rise in the voltage vDS before iD drops is typical of all step down converter circuits. This occurs because the load is considered to be effectively a current source, and therefore it continues to supply current into the switch device until the voltage on the switch side of the load reaches the supply. At this point the diode across the load will start to turn on and take the load current. The initial part of the vGS turn-off transient, td(off) , occurs because of the time constant associated with the RG (Cgd2 +Cgs ) time constant of the MOSFET part of the IGBT.7 As the drain-source voltage vDS starts to rise, the Miller effect of Cgd2 starts to take effect. This temporary arrests the decrease of vGS during the interval trv . When vDS stabilises then this effect stops. The decrease of vGS now continues, but with a time constant of RG (Cgd1 + Cgs ), which is smaller than previously due to the change on the value of Cgd caused by the widening of the space charge region in the device. During all the phase so-far the IGBT is behaving as a MOSFET. 6 Note that the waveforms for turn-on and turn-off are for the IGBT in a step down chopper circuit of the type shown in Figure 8.10, except that the main power device has been replaced by the IGBT and there are no snubbers. 7 R is the gate resistor that is included in the circuit to limit the gate currents to reasonable G levels.
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Introduction to High Power Converter Technology The major difference between the IGBT turn-off and the power MOSFET turn-off is observed in the drain current waveform which has two distinct time intervals. During the tf i1 time the MOSFET is turning off. The second time interval tf i2 is due to the stored charge in the n− region of the device. Since the MOSFET is off there is no way that these carriers can be swept out of the device by a negative drain current. Consequently these carriers diminish by recombination. The punch-through IGBT attempts to minimise this effect by having a small carrier lifetime in the n+ region. This results in an electron concentration gradient from the n− region to the n+ region, thereby sweeping the electrons from the device.8 The non-punch-through IGBT attempts to minimise the tail off current by redesigning the IGBT so that the majority of the current is carried by the MOSFET. This minimises the stored charge. At the time of writing these notes IGBTs are in a rapid state of development. Currently the most advanced devices are capable of withstanding approximately 6kV, and can conduct several thousand amperes. The turn-off times for these devices are of the order of 1µsec of less. For medium power systems IGBTs are currently the device of choice.
8.2.5
Other Devices and Developments
Thus far we have concentrated on the devices that are the most important ones in terms of current practice. However there is also significant work going on into new devices that still have not reached the commercial stage. We shall briefly mention some of these. 8.2.5.1
Power Junction Field Effect Transistors
This device is also sometimes known as the static induction transistor (SIT). It is effectively a JFET transistor with geometry changes to allow the device to withstand high voltages and conduct high currents. The current capability is achieved by paralleling up thousands of basic JFET cells. The main problem with the power JFET is that it is a normally on device. This is not good from a start-up viewpoint, since the device can conduct until the control circuitry begins to operate. Some devices are commercially available, but they have not found widespread usage. 8.2.5.2
Field Controlled Thyristor
This device is essentially a modification of the SIT. The drain of the SIT is modified by changing it into an injecting contact. This is achieved by making it a pn junction. The drain of the device now becomes the anode, and the source of the SIT becomes the cathode. In operation the device is very similar to the JFET, the main difference being quantitative – the FCT can carry much larger currents for the same on-state voltage. The injection of the minority carriers in the device means that there is conductivity modulation and lower on-state resistance. The device also blocks for reverse voltages due to the presence of the pn junction. 8 It is desirable to have long carrier life times in the n− region so that the bulk resistance is kept low in this region when the device is on.
8.2 Review of Power Semiconductor Devices 8.2.5.3
MOS-Controlled Thyristors
The MOS-controlled thyristor (MCT) is a relatively new device which is available commercially. Unfortunately, despite a lot of hype at the time of its introduction, it has not achieved its potential. This has been largely due to fabrication problems with the device, which has resulted on low yields. Figure 8.20 is an equivalent circuit of the device, and its circuit symbol. From Figure 8.20 one can see that the device is turned on by the ON-FET, and turned off by the OFF-FET. The main current carrying element of the device is the thyristor. To turn the device on a negative voltage relative to the cathode of the device is applied to the gate of the ON-FET. As a result this FET turns on, supplying current to the base of the bottom transistor of the SCR. Consequently the SCR turns on. To turn off the device, a positive voltage is applied to the gate. This causes the ON-FET to turn off, and the OFF-FET to turn on. The result is that the base-emitter junction of the top transistor of the SCR is shorted, and because vBE drops to zero. volt it turns off. Consequently the regeneration process that causes the SCR latching is interrupted and the device turns off. The P-MCT is given this name because the cathode is connected to P type material. One can also construct an N-MCT, where the cathode is connected to N type material. 8.2.5.4
New Semiconductor Materials
Silicon is presently the only material that is widely used for the fabrication of the power semiconductors (and integrated circuits for that matter). The reason for this is the ease with which large and very pure crystals can be grown with Silicon. However, there are other materials that have superior properties as compared to Silicon, especially in high power/high voltage applications. Gallium Arsenide (GaAs) is a well used material, especially in high frequency applications, where its very high carrier mobility allows higher frequency devices to be constructed. In addition it has a higher bandgap than Silicon, which means that it can support higher voltages than Silicon, and can be operated at higher temperatures (460C and compared to 300C for Si). Silicon Carbide is a material which is currently attracting a lot of research. It has a significantly larger bandgap than Si (2.9eV as compared to 1.12ev for Si), has excellent thermal conductivity (approximately 3 times that of Si), and can operate at temperatures of 600C, with a maximum operating temperature of 1240C. The breakdown electric field strength is approximately 10 times that of Si, meaning that it can withstand significantly higher voltages. SiC devices are probably on 3 to 5 years from commercialisation. Diamond is the ideal material for power semiconductors. It can operate at very high temperatures (similar to SiC), it can withstand fields approximately 100 times larger than Si, it has thermal conductivity 5 times larger than SiC (and therefore 15 times larger than Si), and it has electron mobility approximately twice that of Si. Unfortunately there is much research to be done before we see commercial diamond based power electronic devices (15-30 years). One can see that there are many exciting developments occurring in the area of power electronic devices. These new devices then open up new applications, that previously were not feasible.
301
302
Introduction to High Power Converter Technology
Source
Gate Channel
i
SiO2
SiO2
-
n
+
n
+
-
p
Drift region resistance
nn+
p
+ + + +
+
i
Drain
+ + + +
}
Minority carrier injection
}
Collector region
}
Minority carrier injection
Lateral body spreading resistance
(a) Source
Gate
i
SiO2
SiO2 n
+
n
p
+
nn+
p
+
i
Drain (b)
Figure 8.16: Current flows in the IGBT.
8.2 Review of Power Semiconductor Devices
Drift region resistance
Gate
303
Drift region resistance
Drain
Drain
Gate
Source Source
(a)
Body region spreading resistance
(b)
Figure 8.17: Equivalent circuits for the IGBT: (a) approximate equivalent circuit for normal operating conditions; (b) more complete equivalent circuit showing the parasitic thyristor.
304
Introduction to High Power Converter Technology
vGS / vGG
vGG
vGS
t
0 iD
td(on)
Io
t t ri
v DS Vd
v DS (on)
t t fv1
t fv 2
C gd
Rg
v DS vGG
vGS
Definitions
C gs
Figure 8.18: Typical turn-on waveforms for an IGBT.
8.2 Review of Power Semiconductor Devices
vGS / vGG
305
vGG
vGG vGS ,I
vGS
o
vGS(th)
t
0 iD
Io
td(off)
t fi 2
}
MOSFET current
}
BJT current
0 t rv
t
t fi1
v DS Vd
t
0
Figure 8.19: Turn-off waveforms for an IGBT.
Anode A Gate G
OFF-FET K ON-FET Cathode Figure 8.20: Schematic and circuit symbol for the P-MCT.
306
Introduction to High Power Converter Technology
Chapter 9
Line Frequency Uncontrolled Rectifiers 9.1
Introduction
The power input into most power electronic devices is derived from 50/60Hz ac sine wave supplies provided by the electricity authorities. This supply generally is converted into a dc supply before being used or converted into another form. The traditional and simplest way of achieving the ac–dc conversion is via an uncontrolled rectifier based on diodes. Such rectifiers only allow power to flow from the ac to the dc side. The vast majority of power electronic applications currently use such rectifiers to do the ac–dc conversion, although this situation may change in the future due to mains harmonic requirements (which are difficult to meet using conventional rectifiers). This chapter shall look at the basic operation single phase and three phase uncontrolled rectifiers. Some analysis will be carried out (based on the assumption of ideal diodes) to ascertain the harmonic performance of the various rectifiers. Before doing this there is some concepts that we will need to introduce.
9.2
Some Mathematical Preliminaries
One of the characteristics of diode rectifier circuits is that the produce nonsinusoidal currents in the ac mains. Therefore consideration of non-sinusoidal waveforms is relevant to carrying out analysis of these types of circuits. Much of the analysis is carried out assuming that the circuits are in steady state, and then calculating the Fourier components in the current (and in some cases the voltage) waveforms. We shall therefore quickly review Fourier analysis as applicable to power electronic waveforms.
308
Line Frequency Uncontrolled Rectifiers
9.2.1
Fourier Analysis of Repetitive Waveforms
In general, a non-sinusoidal waveform, f (t), which repeats with an angular frequency of ω, can be expressed as [19]: ∞ !
∞ ! 1 fn (t) = a0 + {an cos(nωt) + bn sin(nωt)} f (t) = F0 + 2 n=1 n=1
(9.1)
where F0 = 12 a0 corresponds to the average value of the waveform (or the dc component), and the coefficients in (9.1) are: 1 2π f (t) cos(nωt) d(ωt) (9.2) an = π 0 1 2π bn = f (t) sin(nωt) d(ωt) (9.3) π 0 Note that the F0 term is calculated if the harmonic number starts from 0 instead of 1 – i.e.: 2π 1 1 1 T F0 = a0 = f (t)d(ωt) = f (t)dt (9.4) 2 2π 0 T 0 which is the average value of f (t) as noted previously. Each component of the waveform can therefore be written as: fn (t) = an cos(nωt) + bn sin(nωt) which can be simplified using the following trigonometric identity: A cos θ + B sin θ = A2 + B 2 cos(θ ± φ)
(9.5)
(9.6)
where tan φ = ∓ B A . Since via (9.6) equation (9.5) can be written as a cos function, then we can eliminate the frequency component of the waveform and write the expression as a phasor: → − (9.7) F n = Fn ejφn where:
a2n + b2n √ 2 (−bn ) tan φn = an
(9.8)
Fn =
(9.9)
In many situations in power electronics the waveforms do not have a dc component. This coupled with the symmetry that is present can considerably simply the generation of the Fourier coefficients. These are shown in Table 9.1 for several of the common symmetries. If the definition of the rms value1 of a waveform f (t) is applied to the function when expressed in terms of its Fourier components, it can be easily shown that the rms amplitude is: # $ ∞ ! $ F = %F02 + Fn2 (9.10) n=1 1 Definition
of the rms value of a quantity is xrms =
1 T
T 0
x(t)2 dt.
9.2 Some Mathematical Preliminaries Symmetry Even Odd Half-wave
Condition Required f (−t) = f (t) f (−t) = −f (t) f (t) = −f (t + 12 T )
Even quarter-wave
Even and half-wave
Odd quarter-wave
Odd and half-wave
309 Fourier Coefficients π an = π2 0 f (t) cos(nωt) d(ωt) bn = 0 π an = 0 bn = π2 0 f (t) sin(nωt) d(ωt) an = bn = 0 for even n π an = π2 0 f (t) cos(nωt) d(ωt) for odd n 2 π bn = π 0 f (t) sin(nωt) d(ωt) for odd n π/2 4 f (t) cos(nωt) d(ωt) for odd n π 0 an = 0 for even n bn = 0 for all n an = 0 for all n π/2 4 f (t) sin(nωt) d(ωt) for odd n π 0 bn = 0 for even n
Table 9.1: Fourier coefficient formulae with symmetry.
9.2.1.1
Measures of Waveform Distortion
Consider Figure 9.1 which shows the voltage and current waveforms in a situation where a power electronic device is connected to the grid supply [4]. The current waveform shows significant distortion.2 The voltage on the other hand is shown without distortion, since it usually does not display the same amount of distortion as the current. This is the case because the voltage distortion arises from the current causing a voltage drop across the line impedances.3 vs
v, i
is is1
i dis
0
wt
f1
Figure 9.1: Line current waveform distortion. Let us assume that the supply voltage can be represented as: vs (t) =
√ 2Vs sin ω1 t
(9.11)
2 The distortion in this current waveform is typical of that one would expect from a diode rectifier connected to the grid. 3 The undistorted voltage assumption makes the analysis simpler in this section.
310
Line Frequency Uncontrolled Rectifiers The input current is represented by its Fourier components: is (t) = is1 (t) +
∞ !
isn (t)
(9.12)
n=1
where: is1 the fundamental line current isn the harmonic components of the line current We can write (9.12) in an expanded form as follows: is (t) =
√
2Is1 sin(ω1 t − φ1 ) +
∞ ! √ 2Isn sin(ωn t − φn )
(9.13)
n=1
where: φ1 the phase angle of the fundamental
(9.14)
Is , Isn rms value of the relevant harmonic
(9.15)
The rms value of the current can be calculated using the general expression noted in footnote 1. If expression (9.12) is substituted into this, the crossproduct terms all integrate to zero due to the orthogonality property of cos and sin functions. The rms current therefore becomes: # $ ∞ ! $ 2 2 % Isn (9.16) Is = Is1 + n=1
total harmonic distortion
The total distortion of waveforms in general is usually measured by a parameter called the total harmonic distortion, which is abbreviated as the THD. The distorted component of the current is essentially all the components of the current except the fundamental component. Therefore using the time domain expressions for the currents we can write the distortion component as: idis (t) = is (t) − is1 (t) =
∞ !
isn (t)
(9.17)
n=1
This current is shown schematically in Figure 9.1. Therefore, using (9.16), the rms value of the distortion section of the current can be written as: # $! $∞ 2 =% 2 Idis = Is2 − Is1 Isn (9.18) n=1
The THD of the current defined as: Idis I s1 2 Is2 − Is1 = 100 × I # s1 $! $ ∞ Isn 2 % = 100 × Is1
%THD = 100 ×
n=1
(9.19) (9.20) (9.21)
9.2 Some Mathematical Preliminaries 9.2.1.2
311
Power and Power Factor
Clearly the purpose of a power electronic system is to convert electrical energy in different ways to allow energy (or power) to be effectively and efficiently used. Therefore it is relevant to briefly review the concept of power, and then to look at a generalisation of the concept of power factor to systems with non-sinusoidal waveforms. Let us begin with single phase power expressions. Consider the following time domain expressions for current and voltage flowing into some arbitrary network: v = V cos ωt i = I cos(ωt + θ)
(9.22) (9.23)
Using the definition of instantaneous power we can write: P = vi
(9.24)
= [V cos ωt][I cos(ωt + θ)] = V I cos ωt[cos ωt cos θ − sin ωt sin θ] = V I cos2 ωt cos θ − V I cos ωt sin ωt sin θ 1 Using cos2 ωt = [1 + cos 2ωt] one can write 2 V I cos θ [1 + cos 2ωt] − V I sin θ cos ωt sin ωt P = 2
(9.25) (9.26) (9.27) (9.28) (9.29)
Using the trig relation: cos ωt sin ωt =
1 sin 2ωt 2
we can modify the last term of (9.29) as follows: VI V I cos θ [1 + cos 2ωt] − sin 2ωt sin θ 2 2 VI VI VI = cos θ + cos θ cos 2ωt − sin θ sin 2ωt 2 2 2
P =
(9.30) (9.31)
Using cos(x + y) = cos x cos y − sin x sin y, this can be written as P =
V I cos θ 2 Average Real power
+
VI cos(2ωt + θ) 2
(9.32)
Oscillatory component
The oscillatory power component represents the power flowing into and out of the storage element of the particular circuit.4 The average real power component essentially causes an offset in this oscillation component so that there is an average value of power over a complete cycle. The other way of representing the power expression for sinusoidal steady state systems is in the form of the complex power: 4 As we shall later this component consists of two different parts, one belonging to the real power and the other to the imaginary power.
complex power
312
Line Frequency Uncontrolled Rectifiers − → →− − → S =V I∗
(9.33)
→ where ‘∗’ represents the complex conjugate, and the − x means that x is a phasor. Let us assume that: → − (9.34) V = Vrms ejα → − (9.35) I = Irms ejβ where Irms and Vrms represent the current and voltage RMS values. Substituting (9.35) and (9.34) into (9.33) we can write: → − S = Vrms Irms cos θ + jVrms Irms sin θ
(9.36)
where θ = α − β.5 Equation (9.36) is broken up into two components: P = Vrms Irms cos θ Q = Vrms Irms sin θ
(9.37) (9.38)
One can see the vector relationship of these components in Figure 9.2. Notice that the use of the complex conjugate in the complex power expression means that the angle used is effectively the angle of the voltage phasor with respect to the current, despite the fact that the convention is that the currents phase is measured relative to the voltage.6 Imag
P = VI cosq
r I V cosq
r V
q =a -b b a
Real
V sinq
Q = VI sinq
Figure 9.2: Phasor relationship for complex power. The correspondence between (9.37) and the average real power component of (9.32) is easy to see. However, the correspondence between (9.38) and the 5 The
angle θ is the angle from the current vector to the voltage vector. → − − →− → is possible to define complex power as S = I V ∗ . In this case the angle is the current with respect to the voltage in the power expression. The meaning of the sign of the complex power changes with this definition. 6 It
9.2 Some Mathematical Preliminaries
313
oscillatory power part of (9.32) is not immediately obvious. Clearly Q is related the component of the voltage that is orthogonal (in a temporal sense) to the current, multiplied by that current. This correspondence is more easily seen by manipulating (9.29) into the form: P =
V I cos θ V I cos θ + cos 2ωt − 2 2
V I sin θ sin 2ωt 2
(9.39)
Reactive power component
Real power component
where V and I are the peak values of the voltage and current. We can see from this expression that the real power actually oscillates (with the oscillation being unipolar), and has an average value of (V I/2) cos θ. The reactive power component on the other hand does not have an offset term and its average value is zero. The amplitude of this term is equal to the Q term in the complex power expression. Therefore the reactive power component corresponds to power that is flowing into the circuit and out again per half cycle of the fundamental voltage (or current). These components are shown in Figure 9.3 for a phase angle of 30◦ . This plot is of the normalised power, the normalisation factor being Vrms Irms . Notice the reactive power component has no average dc component. 2 Real power
1.5
Total power
Normalised power
Average power
1
Reactive power
0.5
0
-0.5 0
1
2
3
4
5
6
7
q [rad]
Figure 9.3: Diagram of the normalised single phase power components with a 30◦ phase angle – the power is normalised by dividing by Vrms Irms . Remark 9.1 The presence of reactive power is generally undesirable because it contributes to the current in the circuit (and therefore the size of the conductors required) without carrying any average power to the load. Remark 9.2 With an inductive load the current lags the voltage (or the voltage leads the current). Therefore in the complex power expression the angle θ is
314
Line Frequency Uncontrolled Rectifiers positive, and consequently Q is positive. Therefore an inductive load absorbs reactive power, which is given the units of VARs (Volt Ampere Reactive). This is called absorbing lagging VARs. Conversely, a capacitive load results in the current leading the voltage (or the voltage lags the current). Therefore in this case the θ angle is negative, and therefore a capacitive load draws negative VARs from the supply (called leading VARs). It can also be said that the capacitor supplies positive VARs to the supply.
three phase real and reactive power
Let us now briefly consider the concept of three phase real and reactive power. We shall assume that the phase currents and voltages in a star connected system are:7 ⎫ va = V cos ωt ⎪ ⎪ ⎪ ⎪ vb = V cos(ωt + 2π ) ⎪ 3 ⎪ ⎬ 2π vc = V cos(ωt − 3 ) (9.40) ia = I cos(ωt + θ) ⎪ ⎪ ⎪ 2π ⎪ ib = I cos(ωt + 3 + θ) ⎪ ⎪ ⎭ ic = I cos(ωt − 2π + θ) 3 These voltages and currents can be multiplied together to give the three phase power expression: P = va ia + vb ib + vc ic 2π 2π 3V I cos θ V I cos θ + (cos 2ωt + cos(2ωt − ) + cos(2ωt + )) = 2 2 3 3 2π 2π V I sin θ (sin 2ωt + sin(2ωt − ) + sin(2ωt + )) (9.41) − 2 3 3 Terms two and three in (9.41) are zero because the cosine and sine terms each add to be zero. Therefore the power expression becomes: 3V I cos θ (9.42) 2 which is simply three times the average power in (9.39) (as one would expect). P =
Remark 9.3 The interesting aspect about the three phase real power is that it is constant – i.e. the total real power flowing into a three phase system is constant despite the fact that the individual powers in the phase are oscillating. Let us consider the last part of (9.41). Rewriting this term one can see that: V I sin θ V I sin θ 2π 2π − sin 2ωt = ) + sin(2ωt + ) (9.43) sin(2ωt − 2 2 3 3
power factor
which means that the reactive power in one phase is being absorbed by two other phases. Therefore the reactive power is cycling around between the three phases, and hence is not seen on the external three phase power (although there is obviously still the single phase reactive power there in each of the individual phases). The reactive power of three phase systems is considered to be the reactive power of an individual phase, whereas the real power of a three phase system is three times the real power of an individual phase. Now that we have consider the concepts of real and reactive power for single and three phase systems, let use now revise the concept of power factor for sinusoidal systems. We know from (9.37) that the real power is: 7 The
star connection means that there are no zero sequence currents flowing.
9.2 Some Mathematical Preliminaries
315
P = Vrms Irms cos θ
(9.44)
where θ is the angle from the current to the voltage phasor. If the current and the voltage were in phase then the power is obviously Vrms Irms . This is the maximum possible power. It is also known as the apparent power in a system where there is a phase difference between the voltage and the current. The power factor is a measure of how close the actual real power is to the apparent power – i.e.: P (9.45) PF = cos θ = Vrms Irms The next step is to generalise the power factor expression to the case where the current is not sinusoidal. We begin with the basic definition of average power: T1 T1 1 1 P = p(t) dt = vs (t)is (t) dt (9.46) T1 0 T1 0 where T1 is the period of the fundamental waveform. Remark 9.4 Mathematical preliminary: Using cos θ cos nθ = 12 cos(θ + nθ) + 1 2 cos(θ − nθ), where n = 2,3,. . ., one can write: 2π 2π 1 [cos((n + 1)θ) + cos((1 − n)θ)] dθ (9.47) cos(θ) cos(nθ) dθ = 2 0 0 2π 2π 1 = cos(n + 1)θ dθ + cos(1 − n)θ dθ (9.48) 2 o 0 2π 2π sin(n + 1)θ sin(1 − n)θ 1 + (9.49) = 2 n+1 1−n 0 0 sin0 sin(1 − n)2π sin 0 1 sin(n + 1)2π − + − = 2 n+1 n+1 1−n 1−n (9.50) =0
(9.51)
Note that if n = 1, then (9.47) becomes: 2π cos(θ) cos(θ) dθ = 0
2π
cos2 θ
(9.52)
0
2π
1 [cos 2θ + cos 0] dθ 2 0 2π sin 2θ 1 2π = + [θ]0 2 2 0
=
= 2π
(9.53) (9.54) (9.55)
Remark 9.5 Remark 9.4 above shows that the product terms involving different frequencies integrate over the fundamental frequency to zero, whereas terms at the same frequency integrate to give a non-zero term. Substituting in (9.11) for vs and (9.13) for is , and noting from Remark 9.4 that the the integral of the cross-product terms are zero, we can write: T1 √ √ 1 2Vs sin ω1 t · 2Is1 sin(ω1 t − φ1 )dt = Vs Is1 cos φ1 (9.56) P = T1 0
generalised factor
power
316
Line Frequency Uncontrolled Rectifiers Remark 9.6 Equation (9.56) shows that the harmonic currents DO NOT contribute to the average (real) power drawn from the source. Therefore, one can consider that the harmonics contribute to the reactive power drawn from the source. This is the basis for the generalisation of the concept of power factor. We can generalise the power factor expression by realising that the apparent power is simply: (9.57) S = Vs Is where Vs and Is are the true rms values of the voltage and the current (i.e. the rms value of a non-sinusoidal current). Therefore, using the same approach as that for sinusoidal quantities we can write: P (9.58) S Therefore, substituting in the definitions into this expression we can write: PF =
PF =
Vs Is1 cos φ1 Is1 = cos φ1 Vs Is Is
(9.59)
Remark 9.7 From (9.59) one can see that with a non-sinusoidal current source that the sinusoidal power factor is modified by the term Is1 /Is – i.e. the fundamental current rms value divided by the total current rms value. Therefore, as the harmonics increase, the rms value of the current will increase, but the fundamental will not. Therefore the power factor will decrease. The normal power factor expression is given a new name in this context – it is called the displacement power factor (DPF): DPF = cos φ1
(9.60)
Therefore the power factor with the non-sinusoidal current is: PF =
Is1 DPF Is
(9.61)
Using (9.21) it is possible to write the power in terms of the total harmonic distortion: 1 DPF (9.62) PF = 1 + THD2i
9.3
The Half Wave Rectifier Circuit
We shall start our study of uncontrolled rectifiers by looking at the simplest possible rectifier circuit – a single diode rectifier.
9.3.1
Pure Resistive Load
The simplest possible load for the simplest possible rectifier is a pure resistive load. The circuit and input and output current and voltages and shown in Figure 9.4. The operation of this circuit is very straight forward and does not warrant much further discussion. In addition, this circuit is not generally used because of the very high ripple in the output voltage and current. Because the output load is a pure resistance there is not output filter, and consequently the output voltage is not a very good dc voltage at all.
9.3 The Half Wave Rectifier Circuit v diode + -
317
i
+ vs
vd
R
-
v s , vd
i
v diode i, vd
v s , v diode
t
Figure 9.4: Half wave rectifier with a resistive load.
9.3.2
Inductive Load
The case of a half wave rectifier with a inductive-resistive load is more interesting than the previous case. With inductance in the load the current is more filtered than the previous case. The following discussion is with reference to the circuit shown in Figure 9.5. The output plots have been generated by putting the circuit of Figure 9.6, with L = 200mH and R = 50Ω, into the Saber , and running the simulation. The first point that one notices in Figure 9.6 is that
+ + vs
v diode
-
+
vL
-
iL
L
+ R
v out
-
-
Figure 9.5: Half wave rectifier with an LR load. the current continues to flow even when the source voltage has gone negative. When the energy stored in the inductor reaches zero then the current stops flowing. If the resistor value is made smaller then the current will flow further into the negative half cycle. If the resistance was zero then the current would continue to flow for the whole of the negative half cycle. Let us analyse the situation in Figure 9.6. At t = 0 then the diode becomes forward biased and current begins to flow. Assuming an ideal diode then the
318
Line Frequency Uncontrolled Rectifiers
t1
t2
t3
0.8 0.6
(A)
iL 0.4 0.2 0.0 -0.2
Due to simulation numerics
60.0
vs
v out
vL
40.0
(V)
20.0
Area A 0.0
Area B
-20.0 -40.0
v diode
-60.0 0.0
0.005
0.01
0.015
0.02 t(s)
0.025
0.03
0.035
0.04
Figure 9.6: Plots for a half wave rectifier with an LR load – L = 200mH and R = 50Ω.
9.3 The Half Wave Rectifier Circuit
319
circuit whilst the current is flowing is: vs = Ri + L
di dt
(9.63)
At time t1 the current through the inductor reaches its peak value, since from t = 0 to t1 , vL = vs −vout is positive. Notice that after t1 vL becomes negative as the source voltage decreases, and hence the current through the inductor starts to decrease. At time t2 vs becomes negative. However, the current through the inductor continues in the same direction due to the stored energy in the inductor. Eventually at t3 the energy in the inductor is exhausted and the current drops to zero. Because the current is zero at t = 0 and t3 , we can use the inductor current equation to write: 1 t3 vL dt = 0 (9.64) ∆i = i(t3 ) − i(0) = L 0 since i(0) = i(t3 ). This means that the total area under the voltage curve across the inductor is zero (which it must be for the circuit to be in steady state). The integral in (9.64) can be written as follows: t3 t1 vL dt + vL dt = 0 (9.65) 0
t1
which means that: Area A − Area B = 0
(9.66)
Remark 9.8 To get the exact times for t1 , t2 and t3 one needs to solve (9.63).
9.3.3
Inductive Load with Back EMF
Another case of interest is the inductor feeding a back emf scenario. This is shown schematically in Figure 9.7. The voltage source Ed could represent a large capacitor, for example. The result of the presence of this voltage source is that the turn-on time for the diode is change as compared to the previous case.
+ +
v diode -
+
vL
-
iL
L +
vs
-
Ed
-
Figure 9.7: Half wave rectifier circuit with an inductor and back emf. One can see the difference in the performance of the circuit from the Saber simulation plots shown in Figure 9.8.
320
Line Frequency Uncontrolled Rectifiers
(V)
t1
t2
t3
20.0 0.0 -20.0 -40.0 -60.0 -80.0 -100.0 0.2
v diode
(V)
(A)
iL
0.0
-0.2 60.0 40.0 20.0 0.0 -20.0 -40.0 Area A Area B -60.0 0.0 0.005 0.01
Ed
0.015
0.02 t(s)
vL
0.025
vs
0.03
0.035
0.04
Figure 9.8: Plots for a half wave rectifier with an inductor and back emf as a load. One can see from Figure 9.8 that the inductor current iL has much the same shape as that shown in the Figure 9.6, but the magnitude of the current in smaller. This is an obvious result, since the voltage that can increase the current through the inductor is much smaller in this case because of the Ed voltage. In addition the time for the current to build up is also smaller. The other notable difference between this case in that of Figure 9.6 is that the diode reverse voltage is substantially larger in this case.
9.4
The Concept of Current Commutation
Before looking at a practical single phase rectifier circuit we shall briefly look at the concept of current commutation in power electronic circuits. Although we shall be looking at this in terms of naturally (or self) commutated circuits, the same principles also apply to force commutated circuits. Up until this point we have not had to consider commutation issues because we have been dealing with a single diode circuit. Current commutation refers to the transfer of the current in a circuit from one power electronic device to another, as one device starts to turn off and the other turn on. In the case of a diode circuit the turn on occurs because the device becomes forward biased, and the turn off because a device becomes reverse biased. If one is dealing with an ideal circuit, then the current would transfer instantaneously from one device to another, but if there is inductance in the circuit then this does not occur instantaneously. In order to study current commutation consider the test circuit in Figure 9.9.
9.4 The Concept of Current Commutation
+
vL
321
D1
-
Ls is
+ vD
vs
vd
D2
1
Id
-
v s , vd is
vd
t
Waveforms with Ls = 0
Figure 9.9: Test circuit used for current commutation discussion.
322
Line Frequency Uncontrolled Rectifiers The following discussion is with respect to Figure 9.10. Prior to t = 0 the input voltage vs < 0, and therefore the diode D2 is conducting the output current Id . At t = 0 vs becomes positive and the diode D1 becomes forward biased and turns on. However, due to the inductance Ls the current iD1 does not instantly go to Id . The rise in the current in Ls is limited by the value of Ls and the voltage across it. Eventually the current in Ls will rise to the value if Id . During this rise the current iD2 will be falling at the same rate as the increase in iD1 , so that the current to the current source is maintained at Id . When iD1 = Id then the commutation process is complete, and the current iD2 = 0, turning off D2 . i D1
+
vL
-
D1
Ls
+ vs
is
-
D2
Id
Id
vd = 0
Id
vd = v s
i D2
(a) During commutation is = I d
+ vL = 0
-
D1
Ls
+ vs
is
D2
-
(b) After commutation
Figure 9.10: Circuit configurations during current commutation of the circuit in Figure 9.9. Let us analyse this situation as little more closely. Consider the situation when the input voltage vs initially becomes greater than zero. The voltage on the load side of the inductor is zero because D2 is on. Therefore the current across the inductor is: vL =
√
2Vs sin ωt = Ls
dis dt
0 < t < tc
where tc the time when commutation is complete.
(9.67)
9.4 The Concept of Current Commutation
323
We can rearrange (9.67) and integrate both sides to give: √
2Vs
tc
sin ωt dt = Ls 0
which becomes: Aθc =
Id
dis
(9.68)
0
√ 2Vs (1 − cos ωtc ) = ωLs Id
(9.69)
where Aθc the volt-second area under the inductor voltage. Rearranging this expression we can write: ωLs Id cos θc = 1 − √ 2Vs
(9.70)
where θc ωtc , the commutation angle. Remark 9.9 Equation (9.70) confirms our previous assertion that if Ls = 0 then the commutation occurs immediately the diode D1 turns on – i.e. cos θc = 1 ⇒ θc = 0. Also note that as Ls increases the commutation angle increases (as one would intuitively expect), and as Id increases the angle increases due to the fact that it will take longer before iD1 = Id . Remark 9.10 Another interesting effect of the commutation is that the average voltage produced at the output of the circuit is lower due to commutation notches. These “notches” result in sections of vs not appearing at the output. Waveforms for the commutation of the current are shown in Figure 9.11. These waveforms are the outputs of a Saber simulation. These plots clearly show the commutation notches in the output voltage, vd . The commutation notches appear as the voltage across the Ls inductor. The area of these commutation notches, where the horizontal axis is θ = ωt, was evaluated in the expression (9.69). The plots of Figure 9.11, however, are on the time axis. Therefore, under this condition it can be shown that the expression for the area under the inductor notch is Ls Id (the ω term is omitted). Examination of the notch integral plot of Figure 9.11 shows that the area is 0.0050081 – in other words Ls , which it should be since Id = 1. It is clear from Figure 9.11 that the commutation notches lower the output voltage. We can calculate voltage loss analytically. Firstly we can calculate the average output voltage as follows: Vd0
1 = 2π
0
π
√ √ 2 2 Vs = 0.45Vs 2Vs sin ωt d(ωt) = 2π
(9.71)
In the case where one has commutation notches then the average voltage can be calculated as: π√ 1 Vd = 2Vs sin ωt d(ωt) (9.72) 2π θc This expression can be rewritten as the average voltage with Ls = 0 minus the
commutation notches
324
Line Frequency Uncontrolled Rectifiers
(V*sec) : t(s)
(V*sec)
0.006
Notch Area
0.004 (0.020805, 0.0050081) 0.002 0.0
(V) : t(s)
20.0
Comm notches vL
(0.020007, 0.10216)
(V)
10.0 0.0 -10.0
(0.020807, -0.022068)
-20.0
(A) : t(s)
Inductor current i L , is
(A)
1.0
0.5
0.0
(V)
(V) : t(s) 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0
Output vd
vs
vD
1
Output vd 0.0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
t(s)
Figure 9.11: Plots of the currents in the test circuit of Figure 9.9 – vs = 50 sin ωt, Ls = 5mH, Id = 1 Amp.
9.5 Practical Uncontrolled Single Phase Rectifiers
325
average voltage of the commutation notches: π√ θc √ 1 1 Vd = 2Vs sin ωt d(ωt) − 2Vs sin ωt d(ωt) 2π 0 2π 0 area Aθc = 0.45Vs − 2π ωLs = 0.45Vs − Id 2π
(9.73) (9.74) (9.75)
Remark 9.11 From equation (9.75) one can see that the loss of output voltage is: ωLs area Aθc = Id (9.76) ∆Vd = 2π 2π
9.5
Practical Uncontrolled Single Phase Rectifiers
We have now carried out some preliminary analysis on half wave rectifiers to develop some techniques to analyse rectifier circuits. We shall now apply these techniques to a practical single phase rectifier. These circuits are very important, as they form the front end of almost all switch mode power supplies used in domestic and computing applications. Remark 9.12 The prevalence of the single phase rectifier in computer based equipment is becoming a problem in power systems due to the harmonics that they inject into the power supply. This results in poor power factor, and can lead to heating problems in other pieces of equipment, and occasionally causing false triggering of frequency controlled equipment on the network. The circuit which is the subject of this section is shown in Figure 9.12. This is typical of a rectifier used in a linear or switch mode power supply. id
Ls
+
Rs
is Cd
vs
+
vd
Rload
-
Figure 9.12: A practical single phase rectifier. If we assume that the current id is discontinuous due to the capacitor voltage resulting in the current going to zero before the end of the half cycle of the input
326
Line Frequency Uncontrolled Rectifiers voltage (similarly to the waveforms for the circuit in Section 9.3.3), then we don’t have to worry about the current commutation from one diode to another. We shall generate the analytical equations for the circuit under these conditions. We shall not solve the equations, as this is a little complicated, but the solutions are obtainable. If there is current commutation in the circuit then the solutions get a little more complicated. Whilst the diodes are conducting the equivalent circuit is as shown in Figure 9.13. Applying KVL to this circuit we can write the following differential equation: did + vd vs = Rs id + Ls (9.77) dt Similarly one can also apply KCL to the circuit to give: id = Cd
vd dvd + dt Rload
(9.78)
Rearranging we can write the following matrix expressions when the diode is conducting:
did dt dvd dt
=
s −R Ls
1 Cd
Ls
− L1s
− Cd R1load
Rs
id vd
+
1 Ls
(9.79)
vs
0
id
+ Cd
vs
+
vd
Rload
-
Figure 9.13: Equivalent circuit of the single phase rectifier when the diodes are conducting. During the time when the diodes are off (i.e. when the energy in Ls has been expended and vs < vd ), the capacitor is discharging into the load resistor. Therefore there is an exponential decay of the output voltage. The expression for this time is (using KCL): Cd
vd dvd + =0 dt Rload dvd vd ⇒ =− dt Cd Rload
(9.80) (9.81)
Remark 9.13 Using equations (9.79) and (9.81) one can solve for the complete analytical solution for the currents and the voltages in this circuit.
9.5 Practical Uncontrolled Single Phase Rectifiers
327
We shall not attempt to solve (9.79) and (9.81), but instead we shall simulate the circuit of Figure 9.12 using Saber . The plots in Figure 9.14 are the output waveforms of this circuit. In particular notice the vert “spikey” current flowing into the rectifier, and the ripples on the output voltage due to this, and the discharge time when all the diodes are off and the output is disconnected from the input.
40.0
(V) : t(s)
80.0
vd
60.0
(A) : t(s)
is (V)
(A)
20.0 40.0
0.0 20.0
-20.0
0.0 (V) : t(s)
60.0
vs 40.0
(V)
20.0 0.0 -20.0 -40.0 -60.0 0.0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
t(s)
Figure 9.14: Waveforms for the practical single phase rectifier circuit of Figure 9.12. If one evaluates that harmonics on the current waveform the plot shown in Figure 9.15 is obtained. One can see that the output voltage has a dominant dc component (as it should) which has an amplitude of approximately 47 volts. There is also a harmonic at 100Hz corresponding to the fundamental of the ripple on the dc output voltage. The main harmonic in the current is at 50Hz, but there are also significant harmonics at 150, 250 and 350Hz as well (i.e. the 3rd, 5th and 7th harmonics). One can treat each of the harmonics in the current as a phasor (as in (9.7)). The amplitudes of the real and imaginary components of these phasors can be found using the waveform analysis tools in Saber , and these are plotted in Figure 9.16. In Figure 9.16 one can see the amplitude of the fundamental real and imaginary harmonics – a1 = −0.40077 and −b1 = −4.6573.8 Therefore using the 8 In Saber the b coefficient is called the imaginary coefficient. It is the negative of the actual b coefficient as appears in a normal Fourier series. Hence we have written the coefficient
328
Line Frequency Uncontrolled Rectifiers
Mag(A) : f(Hz) 6.0
is
Mag(A)
4.0
2.0
0.0
Mag(V) : f(Hz)
60.0
vd
Mag(V)
40.0
20.0
0.0 0.0
50.0
100.0
0.15k
0.2k
0.25k
0.3k
0.35k
0.4k
0.45k
0.5k
0.55k
0.6k
0.65k
0.7k
f(Hz)
Figure 9.15: Input current and output voltage harmonics in a single phase rectifier.
9.5 Practical Uncontrolled Single Phase Rectifiers
329
Fourier components generated before 140msec and 180msec Re(A) : f(Hz) 1.0
is
Re(A)
0.0
(50.0, -0.40077) -1.0
-2.0
Im(A) : f(Hz)
4.0
is
2.0
Im(A)
0.0
-2.0
-4.0 (50.0, -4.6573) -6.0 0.0
50.0
100.0
0.15k
0.2k
0.25k
0.3k
0.35k
0.4k
0.45k
0.5k
0.55k
0.6k
0.65k
0.7k
f(Hz)
Figure 9.16: Real and imaginary components of the harmonic phasors for the harmonics single phase rectifier harmonics plotted in Figure 9.14.
330
Line Frequency Uncontrolled Rectifiers definitions associated with (9.7) one can see that: F (1) =
a21 + b21 = 4.4745 Amp
φ1 = tan−1
−b1 = 265.08◦ = −94.92◦ a1
(9.82) (9.83)
Comparison of (9.82) with the fundamental shown in Figure 9.15 indicates that the value appears to be correct. The phase in (9.83) is the phase of a cos waveform (which is the time domain representation of a phasor). The harmonics in Figure 9.15 and Figure 9.16 were taken by looking at the input current over two fundamental periods of the input voltage starting at 120msec and ending at 180msec. This was done so that the rectifier was operating in steady state, and the transients that can be seen in Figure 9.14 would not affect the harmonic analysis. This also means that the phase in (9.83) is with respect to the voltage input waveform. Consequently we can use the value in (9.83) to get the phase (and hence power factor) of the current fundamental. Realising that the time domain form of the phasor is: fn (t) = Fn cos(nω1 t + φn )
(9.84)
one can write the time domain expression for the fundamental current as: i1 (t) = I cos(ω1 t + φ1 ) = 4.47 cos(100πt − 94.92◦ )
(9.85) (9.86)
Using the trigonometric identity cos(x) = sin(x + 90◦ ) then we can write: i1 (t) = 4.47 sin(100πt − 4.92◦ )
(9.87)
Hence there is a phase shift of the fundamental from the input voltage of −4.92◦ . Consequently, from (9.60) we can see that the DPF is: DPF = cos φ1 = cos(−4.92◦ ) = 0.996
(9.88)
Remark 9.14 From a fundamental current view point the power factor of the system is very good. The presence of harmonics is the main contributor to poor power factor. The non-sinusoidal power factor is defined by (9.61). Therefore if we can calculate the rms value of the non-sinusoidal current then we can calculate the non-sinusoidal power factor. From Figure 9.15 one can see that the harmonics amplitudes and rms values are as shown in Table 9.2. Using (9.21) we can now calculated the THD for the input current waveform. Calculating the distorted current using (9.18) we get:
Idis
# $ 13 $! 2 = 3.1076 =% Isn n=1
as −b1 .
(9.89)
9.5 Practical Uncontrolled Single Phase Rectifiers Harmonic 1 3 5 7 9 11 13
Amplitude 4.6775 3.6788 2.1911 0.87625 0.30301 0.29773 0.18
331
RMS value 3.3054 2.6013 1.5493 0.6196 0.2143 0.2105 0.1273
Table 9.2: Current harmonic amplitudes. Therefore the input current THD is: Idis Is1 3.1076 = 100 × 3.3054 = 94%
THD = 100 ×
(9.90)
Remark 9.15 The value in (9.90) shows that the harmonic distortion of the input current is quite high. We can now also calculate the non-sinusoidal power factor using (9.59): Is1 cos φ1 Is 3.3054 × 0.996 = 3.1076 + 3.3054 = 0.513
PF =
(9.91)
Remark 9.16 From (9.91) one can see that the power factor is very low. Compare this to the DPF which is 0.996. Therefore the presence of the harmonics in the input current waveform is a major contributor to the poor power factor of this circuit. Remark 9.17 Single phase full wave rectifiers such as depicted in Figure 9.12 are present in large numbers on the power supply grid (e.g. in computer power supplies). Therefore the cumulative affect of this could result in a very poor overall power factor. Techniques for improving the power factor of this rectifiers are now being used.
9.5.1
Unity Power Factor Single Phase Rectifier
The requirement for unity power factor (which implies low harmonic content) for single phase rectifiers connected to the grid has spurred research into techniques to modify the standard single phase full wave rectifier. One of the standard techniques to filter supply current waveforms is to use passive filters at the input of rectifier. These passive filters usually consisted of combinations of L or LC components. An example of a circuit with this type of filtering is shown in Figure 9.17 [4]. This particular circuit has filters at the ac input and the dc output. The input filter is a classic ‘T’ low pass filter.
332
Line Frequency Uncontrolled Rectifiers This filter basically filters out the higher order harmonics in the input current. The filter in the dc link needs a little explanation. Clearly it is also a low pass filter, and appears to have the classic π structure. The choice of the size of the components is important from another point of view. The capacitor Cd1 is chosen to be small so that there is considerable ripple in the vd1 voltage. This causes the current to flow in smoother fashion from the supply via the diodes. The extra ripple in vd1 is then filtered via the low pass filter formed by Ld and Cd . The Cd capacitor is much larger than Cd1 . Ld
id
Lf 1
+
Lf 2
is Cf
vs
+
C d1
+
vd1
Cd
+
Rload
vd
-
Figure 9.17: Single phase rectifier with input and dc link filters.
Remark 9.18 The passive circuits have a limited capacity to smooth the input current. The filtering achieved is capable of improving the power factor the acceptable levels. However there are some shortcomings: 1. The output voltage is lowered due to the presence of the inductors. 2. There is an obvious disadvantage in the cost of the filters, size, losses and dependence of the output voltage on the load current drawn. The limitations cited in Remark 9.18 have led to the investigation of active current shaping techniques to improve the power factor of the rectifiers. These techniques also have the advantage that they extend the range of operation of the rectifier – i.e. the input voltage can vary but the output voltage will stay constant. For any current shaping circuit to be of practical use it has to have the following attributes: • The current shaping circuit should be of low cost and small size. • It should enable the input power factor to be near unity. • The circuit should be simple to control. • It should allow the rectifier to provide the correct voltages under overvoltage as well as under-voltage conditions. Given these specifications the obvious circuit to provide this functionality is the boost converter. This circuit is the most suitable for the following reasons:
9.5 Practical Uncontrolled Single Phase Rectifiers
333
1. The circuit is capable of producing an higher voltage at the output than at the input. Therefore as the input voltage falls the output voltage can be kept constant. 2. If the converter is set-up to provide an output voltage, that is say 10% higher than the nominal peak input voltage, then the circuit can cope with over-voltages of up to 10% without altering the output voltage. 3. The boost converter configuration maintains a continuous current through the input inductor (if operating is continuous conduction mode). Therefore the current can be kept continuous through the diodes on the circuit. This intrinsically allows better input power factor to be achieved. Remark 9.19 Note that the buck converter is in general not suitable for this application because the input current is highly discontinuous. This is due to the fact that the switch in the circuit disconnects the output of the diodes in the rectifier from the input to the converter during normal operation. Figure 9.18 shows the basic structure of a single phase rectifier with a boost converter for current shaping. Boost converter
Ld
id
i load
iL
Ls
+
ic
Rs
is
vs
vs
Cd
+
Rload
vd (> v s )
-
Figure 9.18: Circuit for the a single phase rectifier with current wave shaping boost converter. As can be seen from Figure 9.18 the circuit is simply a conventional rectifier followed by a conventional non-isolated boost converter. The boost converter is usually controlled so that the output voltage is approximately 10% higher than the nominal rated voltage of the rectifier. This allows the circuit to work correctly if the supply is up to 10% higher than the nominal voltage. One implicitly gets a circuit that can operate with low voltages because of the boost converter. How low the voltage can go depends on the design of the boost converter and the load current and voltage required. The key to the operation of the unity power factor rectifier is the control of the boost converter. Before considering the general principles of the control we firstly need to clarify the requirements for the control. If we want unity power
334
Line Frequency Uncontrolled Rectifiers factor, than we need a sinusoidal input current which is in phase with the input voltage and does not have any significant harmonics. The desired waveforms are shown in Figure 9.19(a) and (b). One can see that the waveforms in the boost converter section of the circuit are sinusoidal in nature. vs
is
wt
(a) vs iL
wt
(b)
Figure 9.19: Waveforms for a single phase rectifier with active current waveshaping – (a) the input current and voltage; (b) the boost converter input voltage and inductor current.
Remark 9.20 Examination of the waveforms in Figure 9.19 indicate that there will be a ripple voltage on the output filter capacitor (as there is in the conventional rectifier). The capacitor has to be designed to be large enough to keep this ripple below acceptable limits. Ignoring power losses in the boost converter we can apply some basic analysis to the circuit of Figure 9.18 with the waveforms of Figure 9.19. Define Vˆs = √ √ 2Vs , and Iˆs = 2Is – i.e. Vs and Is are the rms values of the voltage and the current. Clearly the instantaneous power flowing into the circuit is (using sin2 x = 12 (1 − cos 2x)): pin (t) = Vˆs sin ωtIˆs sin ωt = Vs Is − Vs Is cos 2ωt
(9.92)
which is similar to (9.32), except that this was calculated for cos waveforms with a θ phase difference between them.
9.5 Practical Uncontrolled Single Phase Rectifiers
335
If we assume that the output capacitor is large then the voltage ripple across it will be minimal, and consequently the output power can be written as: pd (t) = Vd id
(9.93)
where Vd the average output voltage = vd . The current flowing into the load and the capacitor is: id (t) = Iload + ic (t)
(9.94)
Assuming that the switching frequency is very high then the inductor can be negligibly small. This allows one to use the simplifying assumption that on an instantaneous basis that: (9.95) pin (t) = pd (t) and therefore we can write: Vs Is − Vs Is cos 2ωt = Vd id (t) Vs Is Vs Is ∴ id (t) = Iload + ic (t) = − cos 2ωt Vd Vd
(9.96) (9.97)
One can see from this expression that: Id = Iload = ic (t) = −
Vs Is Vd
Vs Is cos 2ωt = −Id cos 2ωt Vd
(9.98) (9.99)
Even though the assumption was made that the voltage across the capacitor was constant, we can use (9.99) to get an approximate value of the voltage ripple across the capacitor: 1 Id sin 2ωt (9.100) ic (t) dt = − vd,ripple (t) ≈ Cd 2ωCd Remark 9.21 From (9.100) it can be seen that if Cd is made large then vd,ripple can be arbitrarily small. The key to the correct functioning of this circuit is the control. Two control loops are required in order to achieve the required control – a voltage control loop so that the output voltage stays are the correct value despite load variations, and a current control loop to provide the input current waveshaping. These two loops have to work cooperatively. We have previously encountered both voltage and current control loops, arranged in a hierarchical or nested structure, in relation to switched mode power supply control. A similar arrangement is used here, the main difference being the desired reference value for the current. Figure 9.20 shows a block diagram of the basic structure of the control for the unity power factor single phase rectifier. This block diagram is almost the same as that shown in Figure 6.25. The major difference is the inclusion of the multiplier of the error by the absolute value of the supply voltage, which results in a sinusoidal rectified inductor current reference waveform. This is then fed to the current control algorithm. The current control algorithm can be
336
Line Frequency Uncontrolled Rectifiers
vs e = Vd* -Vd ,measured
Vd*
PI Regulator
Vd,measured
´
i L*
Current mode control
Switch control signal
i L,measued
Figure 9.20: Block diagram of the control system for a single phase rectifier with active current waveshaping. implemented in a variety of ways (see Section 6.3.3.3), but the most common technique is the “constant frequency with turn-on at clock time” controller. With this control strategy the net result is that the sinusoidal reference current amplitude is modulated by the output voltage error – the larger the voltage error the larger the amplitude of the sinusoidal current pulse. Some other points to note about this circuit: 1. A resistor in series with the Ld inductor is often used to limit the inrush current at start-up. This resistor is usually shorted out by a SCR (large voltage drop with this though), a relay or a MOSFET once the circuit starts to operate normally. 2. A small filter capacitor is usually placed across the output of the diode bridge to prevent the switching noise from entering the grid supply. 3. The output filter capacitor only has to be about half the size of that in an uncontrolled rectifier, for the same ripple. Therefore the active rectifier circuit saves on weight and space. 4. The energy efficiency of a typical active current controlled signal phase rectifier is 96%. An uncontrolled conventional rectifier has an efficiency of approximately 99%.
9.5.2
Effect of Current Harmonics on Line Voltages
We have seen in Section 9.5 that the single phase rectifier can produce many harmonics in the current. In the subsequent analysis of the power factor of the circuit it was assumed (for simplicity reasons) that the voltage was unaffected by the presence of these harmonics. However, in a real network this is not the case. Consider the circuit shown in Figure 9.21. Here we can see a conventional single phase rectifier connected to the grid supply via a source resistance and inductance. Note that the inductance is divided into two sections, the section between them being the so called “point of common coupling” (PCC). The PCC is the nearest point to the rectifier where other equipment can be connected to the grid supply. Note that there is an additional inductance, representing the inductance of the grid supply, between the PCC and the grid supply voltage source. It is the inductance of this impedance that causes the current harmonics
9.5 Practical Uncontrolled Single Phase Rectifiers
337
to affect the supply voltage seen by other devices connected to the grid supply. The voltage across other equipment at the PCC is: Point of common coupling (PCC) id
Ls2
Ls1
is
+ vs
Rs
v PCC
Cd
+
vd
Rload
-
Other equipment connected to the supply
Figure 9.21: Single phase rectifier showing the point of common coupling.
vP CC = vs − Ls1
dis1 dt
(9.101)
where vs is assumed to be an ideal sinusoidal voltage source. The current is1 contains the harmonic currents of the single phase rectifier (as well as the harmonics drawn by the other equipment). These harmonics will cause a voltage drop across the Ls1 inductance. This drop can be considerable, since the impedance of an inductor increases with increased frequency. One can break the current into a sinusoidal component and the distorted components as follows: ! dish dis1 (9.102) vP CC = vs − Ls1 − Ls1 dt dt h=1
Clearly the fundamental component is: vP CC1 = vs − Ls1
dis1 dt
(9.103)
and the distortion component is: vP CCdis = −Ls1
! dish dt
(9.104)
h=1
9.5.3
Voltage Doubler Single Phase Rectifiers
The circuit shown in Figure 9.22 is sometimes used in cost conscious commercial products to produce voltage doubling without the use of a transformer. Depending on the position of the switch the rectified dc voltage is either approximately the peak of the sinusoidal input voltage, or alternatively it is twice this peak voltage.
338
Line Frequency Uncontrolled Rectifiers
C1
D1
Double pos
D2
vac
vd C2
Figure 9.22: Single phase rectifier voltage doubler.
If the switch is closed then on a positive half cycle of the input voltage current flows via D1 , capacitor C1 , and the switch back to the supply. On the negative half cycle the current flow via the switch, capacitor C2 and diode D2 back to the supply. The result is that the two capacitors have the peak supply voltage across them, and their voltages sum. If the switch is open, then the circuit behaves as conventional bridge rectifier.
9.5.4
The Effect of Single Phase Rectifiers on Three Phase, Four Wire Systems
In large commercial buildings the primary loads are of a single phase nature, even though the building as a whole is supplied with a three phase power system. These single phase loads are usually distributed as evenly as possible between each of the three phases and the neutral of the system, as shown in Figure 9.23. If the loads on the system are linear loads then such a strategy will lead to a neutral current that is approximately zero. However, if the loads are largely single phase rectifiers, the non-linear nature of these loads can lead to substantial neutral currents. Assume that the diode rectifiers in each of the phases are identical. We can therefore write the currents in the phases as a combination of the fundamental and harmonics currents (which are the odd harmonics, since, as shown previously, the even harmonics are zero): ia = ia1 +
∞ !
iah
(9.105)
h=2k+1
=
∞ ! √ √ 2Ish sin(ωh t − φh ) 2Is1 sin(ω1 t − φ1 ) +
(9.106)
h=2k+1
In a similar manner to (9.106) one can write the other currents in the phases
9.5 Practical Uncontrolled Single Phase Rectifiers
ia
ib
a b n
ic
c
in
Single phase rectifier loads
Figure 9.23: Single phase rectifiers loads in a three phase, four wire distribution system.
339
340
Line Frequency Uncontrolled Rectifiers (assuming they are of similar form): ib =
√
2Is1 sin(ω1 t − φ1 − 120◦ ) +
∞ ! √
2Ish sin(ωh t − φh − 120◦ h)
h=2k+1
(9.107) ic =
√
2Is1 sin(ω1 t − φ1 − 240◦ ) +
∞ ! √
2Ish sin(ωh t − φh − 240◦ h)
h=2k+1
(9.108) Applying Kirchhoff’s current law to Figure 9.23 we can write: in = ia + ib + ic
(9.109)
If one substitutes (9.106), (9.107) and (9.108) into (9.109) then all the nontriplen and fundamental harmonics add to be zero. The triplen harmonics on the other hand add to give: in = 3
∞ !
√ 2Ish sin(ωh − φh )
(9.110)
h=3(2k−1)
which can be written in rms terms as: ⎛ In = 3 ⎝
∞ !
⎞1/2 2 ⎠ Ish
(9.111)
h=3(2k−1)
Therefore the third harmonics add together in the neutral, and the neutral current therefore becomes: (9.112) In = 3Is3 The third harmonic current in the lines can be quite significant with single phase rectifier loads, and consequently the neutral current can be large. In fact under conditions of highly non-linear loads, the neutral current can be as much as √ 3Iline . Therefore, the neutral should be a conductor that can at least carry as much as the lines.
9.6
Three Phase, Full Bridge Rectifiers
Whilst single phase rectifiers predominate in domestic and computer rectification applications, industrial rectification is carried mainly with three phase rectifiers. This is due to their lower voltage and current ripple, and their higher power carrying capabilities. These devices naturally balance the loading on each of the phases, and therefore do not require any planning action in this respect. Furthermore, no triplen harmonics can flow in these circuits since there is no neutral connection. The fundamental circuit for the conventional six pulse three phase rectifier is shown in Figure 9.24. In order to understand the operation of this device we shall firstly look at a simplified model of its operation. Assume that the load is not modelled as an
9.6 Three Phase, Full Bridge Rectifiers
341
id D1
a
D3
D5
Ls
+ b
ia
Ls
+
n
Cd
c
+
Rload
vd
ib
Ls
+ ic D4
D6
D2
Figure 9.24: Basic three phase, six pulse, full wave rectifier circuit.
Graph0 (A) : t(s) i(v_sin.phase_c)
(A)
5.0
0.0
-5.0 (A) : t(s) i(v_sin.phase_b)
(A)
5.0
0.0
-5.0 (A) : t(s) i(v_sin.phase_a)
(A)
5.0
0.0
-5.0 (V) : t(s) 400.0
v(v_sin.phase_a)
(V)
200.0 0.0
v(v_sin.phase_b)
-200.0 v(v_sin.phase_c) (V) : t(s)
-400.0
(V)
600.0
output_voltage
400.0 200.0 0.0 0.0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
t(s)
Figure 9.25: Waveforms of a three phase rectifier with a constant current source load.
342
Line Frequency Uncontrolled Rectifiers RC as in Figure 9.24, but as a constant current sink. This is an approximation to a highly inductive load. The plots of the phase currents and output voltages of this converter are shown in Figure 9.25. As can be seen from this diagram, the output voltage consists of 6 segments per input voltage period. Therefore this rectifier is often known as a six pulse rectifier.
Chapter 10
Introduction to Other Power Electronic Devices and Applications 10.1
Introduction
This chapter briefly introduces several other high power, power electronic switching devices and applications that are industrially important. The presentation here is brief and introductory in nature, and by no means comprehensive. It is intended to introduce the student to other power electronic circuits, hitherto not considered, and some of their applications. The applications chosen are, hopefully, those that are interesting to the readers. Thnose who wish to research into any of the circuits and applications presented are encouraged to follow up the topics in the references. The remainder of this chapter will consider the following: • Inverters and applications • Multilevel converters and applications • Matrix converters
10.2
Inverters and Applications
In the previous chapter we briefly considered rectifiers. A rectifier is the name given to a power electronic device which accepts AC voltage at its input, and “rectifies” this to DC voltage at the output. The power flow is considered to be from the AC to the DC side. The term rectifier refers to the operational function of the power electronic hardware, but not the configuration of the hardware. This distinction is demonstrated by the cycloconverter. The cycloconverter uses power electronic hardware that is virtually the same as that of a phase controlled rectifier and generates AC output voltages from AC input voltages. Power can flow bidirectionally in these devices.
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Introduction to Other Power Electronic Devices and Applications
Rectifier mode P
AC
DC
CONVERTER
P Inverter mode Figure 10.1: Definition of rectifier and inverter modes of operation [4]. An inverter, is the dual of the rectifier, in that it accepts DC input and generates an AC output – i.e. power flow is from the DC to the AC side of the power electronic device. As with the rectifier, this definition does not define the hardware configuration, since it is possible to have the same hardware acting as an inverter and rectifier. The above is summarised in Figure 10.1. Consider, for example, the rectifier considered at the end of Chapter 9, i.e. Figure 9.24. In this circuit that main electronic components are diodes. Diodes can only conduct current in one direction. Therefore, if the output voltage is only allowed to be one polarity, then power cannot be transferred from the DC side to the AC side of the converter, as current cannot flow in the reverse direction through the diodes. It is this fact that defines this circuit to be a rectifier.
Input
Converter 1
Converter 2
Output
Energy Storage Element
Figure 10.2: Generic power processing block [4]. Many power electronic systems have the configuration shown in Figure 10.2. Converter 1 transforms the input to DC. There is a storage element that is able to accept the energy. Converter 2 then converters to DC to the desired output. The energy storage element is typically a capacitor or inductor. Its presence means that the instantaneous input power does not have to equal to instantaneous output power, thereby providing a degree of decoupling of the input from the output, and allowing a degree of independence in the control and operation of the two converters. Figure 10.3 shows a less abstract version of Figure 10.2 for one form of an
10.2 Inverters and Applications
345 DC link
AC
Converter 1
+
Converter 2
AC
AC Motor
Utility
Figure 10.3: Block diagram of a generic AC drive system.
AC drive system. Notice that in this particular case to energy storage element is a capacitor. Both the input and the output is AC. Therefore, in this application there is inherently an inversion process, since one way or another power must go from the DC to AC side. In many actual implementations of Figure 10.3 Converter 1 is a rectifier, and Converter 2 is an inverter. This means that power can only flow from the utility to the motor, and not in the reverse direction since the rectifier cannot transfer power back to the utility. Depending on the details of the implementation of Converter 2, it is possible that it can act as a rectifier, and power can from the motor (which is now acting as a generator, the mode being called regeneration) back to the DC link. In this case the capacitor can accept the energy, but one must be careful to ensure that not too much energy is transferred, else the capacitor will experience over-voltage and be destroyed. If a motor is going to be regenerating for a significant percentage of time during operation, then both Converter 1 and Converter 2 need to be able to act as both a rectifier and an inverter. If this is the situation then regenerated energy can be transferred back to the utility supply, and the capacitor voltage can be controlled to remain within bounds.
Remark 10.1 It is possible to further classify inverters based on the type of technology used to implement the inverter – forced commutated converters, resonant link converters. We shall not look a these differences in detail here. Figure 10.4 shows a specific implementation of an inverter. The main difference between this and Figure 9.24 is that the diodes in the circuit are in parallel with a switch. Most modern small to medium power inverters these days use IGBTs as the switch. The arrows on the switches in Figure 10.4 indicate that this is the direction that current can flow through the switch. The presence of the parallel switches across the diodes makes a major difference to the operation of this circuit. By appropriate switching of the six switches an AC voltage (in an average sense) can be synthesized on the three phase outputs of the inverter. The presence of the diodes, of course, means that the circuit can always operate as a rectifier. In fact, this very circuit is now coming into use as the rectifier front end to large drive systems. Its ability to allow bidirectional power flow means that this rectifier allows a fully regenerative system.
346
Introduction to Other Power Electronic Devices and Applications Artificial ground
DC link
3 phase AC load
R
vag
Z
a DC
+
b g
c
Z vbg
n
Z vcg
R
Figure 10.4: Specific implementation of an inverter.
10.2.1
Pulse Width Modulation
Thus far we have only considered one form of the hardware for an inverter. In order for an inverter to work, there has to be a strategy for controlling the switches. In section 5.4.2 we considered how to generate a Pulse Width Modulation (PWM) strategy to produce a desired average output voltage. This was based on the use of a triangular carrier wave intersecting with the desired waveform. The essentials of this technique are shown in Figure 5.11 on page 138. The same technique can be used for three phase systems. If we consider just one leg of the three phase converter of Figure 10.4, then the technique outlined in section 5.4.2 can be applied directly. When the reference waveform exceeds the triangluar waverform then the top switch in the leg is turned on, and the bottom leg off. When the reference waveform is less that the triangular waveform, then the bottom transistor is turned on and the bottom transistor is turned off. The waveforms produced when the centre of the DC link is used as the reference point for the voltage are shown in Figure 10.5. Remark 10.2 Note that the fact that the load is referenced to the centre of the DC link allows true AC voltage and AC current to be applied to the load. This is similar to the situation in the three phase inverter. In the case of a three phase inverter to see how the waveforms appear is a little more complex, and not quite as obvious. As in the single leg case one needs to establish a reference point to define the voltages, and similarly the mid point of the DC link is often chosen. Therefore, if the top switch of a leg is closed (meaning that the bottom switch is open) then the voltage on the phase output terminal is 12 VDC where VDC is the total voltage across the DC link. Similary if the bottom switch is closed (meaning that the top switch is open), then the voltage on the phase output terminal is − 21 VDC . Therefore, the output of a single leg has two values. Therefore with three legs we have 23 = 8 possible unique output voltage combinations, corresponding the 8 different possible switching combinations.
10.2 Inverters and Applications
347
DC link
+
Modulator
+
Z
e
Reference waveform Carrier waveform
Approximate fundamental
Figure 10.5: Single leg of inverter and the PWM waveforms.
348
Introduction to Other Power Electronic Devices and Applications A notation that we shall use is that the leg switching states are represented by a binary value – a ‘1’ denotes that the top switch of a leg is closed, and the bottom switch is open, and a ‘0’ denotes that the top switch is open and the bottom switch is closed. Therefore, the possible switching combinations, with the phase leg voltages with respect to the mid link ground point (denoted as “g”), and the line-to-line voltages across a three phase load (such as that in Figure 10.4) are shown in Table 10.1. Switch pattern abc 000 001 010 011 100 101 110 111
vag − 12 VDC − 12 VDC − 12 VDC − 12 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC
vbg − 21 VDC − 21 VDC 1 2 VDC 1 2 VDC − 21 VDC − 21 VDC 1 2 VDC 1 2 VDC
vcg − 12 VDC 1 2 VDC − 12 VDC 1 2 VDC − 12 VDC 1 2 VDC − 12 VDC 1 2 VDC
vab 0 0 −VDC −VDC VDC VDC 0 0
vbc 0 −VDC VDC 0 0 −VDC VDC 0
vca 0 VDC 0 VDC −VDC 0 −VDC 0
Table 10.1: Switching combinations and associated phase and line-to-line voltages. Remark 10.3 Note from Table 10.1 that the line-to-line voltages always add together to be zero (similar to line-to-line voltages in a sinusoidal three phase system). Remark 10.4 Note also from Table 10.1 that two of the switching states lead to zero line-to-line voltages. These two states correspond to all the top switches on, or all the bottom switches on. These switching combinations lead to a short circuit across the three phases. The phase voltages – i.e. van , vbn , vcn are also of interest. Let us consider switching state 001 as an example. In this case we have: vab = van − vbn = 0 vbc = vbn − vcn = −VDC
(10.1) (10.2)
vca = vcn − van = VDC
(10.3)
One can immediately see from (10.1) that van = vbn . However, these equations are not independent, and therefore one cannot solve for the phase voltages. If one considers the three phase load to be a passive one of the form shown in Figure 10.4, then one can write, unisng Kirchoff’s voltage law, the following expressions: va = ia Z + vn vb = ib Z + vn
(10.4) (10.5)
vc = ic Z + vn
(10.6)
Adding these equations together we can write: vag + vbg + vcg = (ia + ib + ic )Z + 3vn
(10.7)
10.2 Inverters and Applications
349
Because the load is star connected then we know that: ia + ib + ic = 0
(10.8)
and hence (10.7) becomes: (10.9) vag + vbg + vcg = 3vn 1 (10.10) ∴ vn = (vag + vbg + vcg ) 3 Using (10.10) one can therefore write the following expressions for the phaseto-neutral voltages: 2 1 1 van = vag − vn = vag − vbg − vcg (10.11) 3 3 3 2 1 1 vbn = vbg − vn = vbg − vag − vcg (10.12) 3 3 3 2 1 1 (10.13) vcn = vcg − vn = vcg − vag − vbg 3 3 3 Using equations (10.11), (10.12) and (10.13) together with the values for the voltages vag , vbg and vcg in Table 10.1 one can write all the values for the phase voltages that can be produced by the inverter. These appear in Table 10.2. Switch pattern abc 000 001 010 011 100 101 110 111
vag − 12 VDC − 12 VDC − 12 VDC − 12 VDC 1 2 VDC 1 2 VDC 1 2 VDC 1 2 VDC
vbg − 12 VDC − 12 VDC 1 2 VDC 1 2 VDC − 12 VDC − 12 VDC 1 2 VDC 1 2 VDC
vcg − 12 VDC 1 2 VDC − 12 VDC 1 2 VDC − 12 VDC 1 2 VDC − 12 VDC 1 2 VDC
van 0 − 31 VDC − 31 VDC − 32 VDC 2 3 VDC 1 3 VDC 1 3 VDC 0
vbn 0 − 31 VDC 2 3 VDC 1 3 VDC − 31 VDC − 32 VDC 1 3 VDC 0
vcn 0 2 V 3 DC − 13 VDC 1 3 VDC − 13 VDC 1 3 VDC − 23 VDC 0
Table 10.2: Switching combinations and associated phase and phase-to-neutral voltages. Remark 10.5 Adding together equations (10.11),(10.12) and (10.13) one gets: van + vbn + vcn =
2 1 1 (vag + vbg + vcg ) − (vag + vbg + vcg ) − (vag + vbg + vcg ) 3 3 3 (10.14)
∴ van + vbn + vcn = 0
(10.15)
Therefore the phase voltages always add to be zero, regardless of the applied voltages, when the three phase load is passive. It can be shown that this also applies if there are three phase sinusoidal voltage sources in the load as well. Remark 10.6 The neutral voltage of the three phase load moves around relative to the ground at the mid point of the DC link. Consider the extreme cases of switching patterns 000 and 111. For 000, using (10.10) and substituting for the voltages from Table 10.2 one can see that vn = − 12 VDC . Similarly for the case of 111 we get vn = 12 VDC . Therefore the neutral voltage has moved around by VDC . These large voltage excursions in the neutral can cause bearing currents to flow when electrical machines are the load on the inverter.
350
Introduction to Other Power Electronic Devices and Applications 10.2.1.1
Space Vectors and PWM
If an electrical machine is used as the load on an inverter, then space vectors can be used to represent the phase voltages. These pahse voltages are appearing across the phases of the machine. Almost all AC machines are wound so that their windings are sinusoidally distributed in space. This fact allows a “space vector” concept to be used to represent currents, fluxes, mmfs, and voltages in the machine. Refer to [4, 20] for more detail. In this concept, currents, voltages, fluxes and mmfs are considered to be sinusoidally distributed in space. As an example, if one has a sinusoidally distributed winding in an AC machine, and this winding is fed with a DC current, then the mmf is sinsusoidally distributed around the periphery of the AC machine. Remark 10.7 It can be shown that if we have three phase sinusoidally spatially distributed windings, fed with three phase temporal sinusoidal currents, then one ends up with a spatially sinusoidally distributed resultant mmf that moves around the machine at the electrical supply frequency. This can be represented as a single vector that is rotating with an angular velocity of ω (the electrical supply frequency).
C
B
A va vb vc
V dc
V 3 (010)
3 V 4 (011)
4
(110) V 2 2 V7 (111) (000) V8
A
B
C
1 (100) V 1 6
5 V 5 (001)
(101) V 6
Figure 10.6: Switch positions and the resultant voltage space vectors. The reason for introducing the space vector concept here is because it is convenient to use this concept to represent the output voltages for an inverter. Figure 10.6 shows the space vector diagram for the various switch positions for the inverter. The length of the space vector corresponds to the maximum
10.2 Inverters and Applications
351
phase-to-neutral voltage for each phase – i.e. 23 VDC . Notice that there are six active vectors that can be spaced around a machine every 60◦ electrical. Remark 10.8 Although the space vector concept comes about because of the spatial properties of machine windings, it is often used in situations where this does not exist. For example, in Figure 10.3 we have a passive load consisting of impedances, and we can use the space vector concept to represent the voltages on this circuit. I will not, in this brief introduction, go into detail as to why this can be done, suffice to say that it is due to the very close relationship between space vectors and temporal phasors in circuits. Space vectors can be used as a basis for a different type of PWM, called Space Vector PWM (SVPWM). The basis of this PWM strategy is the realisation that three phase temporal sinusoidal voltages lead to a spatially rotating voltage vector in a three phase sinusoidally wound machine (as noted previously). However, with an inverter we do not have infinitely variable voltages that we can apply to each phase, and therefore we can switch the inverter so that at any instant of time we can, in an average sense, produce a desired voltage vector.
T T/2
T/2
10 0
1
1
1
1
1
1
0 A
10 0
0
1
1
1
1
0
0 B
10 0
0
0
1
1
0
0
0
t 0 t1
t2
t0
t0
t2
t1 t 0
C
Figure 10.7: Switching waveforms for double edge pulse width modulation. In order to develop a PWM strategy using space vectors let us define α as the duty cycle for a vector. Consider Figure 10.7 which shows the switching waveforms to generate a particular voltage vector. One can see from this diagram that the same switching pattern is generated symmetrically around the centre of the PWM period. By reading vertically one can determine the switching states for this switching sequence – they are 000, 100, 110, 111, 111, 110, 100, 000 – i.e. we are switching between vectors V8 , V1 , V2 , V7 , and then the reverse. The vector nomenclature appears in Figure 10.6. As one can imagine this would lead to an average vector somewhere in between V1 and V2 , the length of the vector being controlled by the duration of the zero vectors V7 and V8 . The duty cycle for each of the vectors is simply the total time of the vector divided by the control period time T . For example, the duty cycle for the V1 vector is:
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Introduction to Other Power Electronic Devices and Applications
2t1 (10.16) T Similary one can defined the duty cycle for V2 . Using this notation, if only this vector and the zero vector was switched during an interval of T then the average voltage vector magnitude produced over the interval is α1 VDC volts. α1 =
Note 10.1 Space vectors are defined (for reasons that I shall not elaborate on here) as 23 the amplitude of the resultant vector in the machine. For a three phase machine this means that the maximum voltage vector magnitude is the same as the peak voltage that occurs across the phases. It is this correspondence of the voltage vectors with the phase voltages that is one of the main reasons for using this convention. Remark 10.9 A further comment on note 10.1 – one can resolve the space vector onto three axes 120◦ apart and get the instantaneous value of the voltage on the respective three phase axes. The same logic applies to the current vector.
q V2
Desired voltage vector 1
aq 2t 2 60 o
ad
d V1
2t 1 Figure 10.8: Switching time determination. One of the very convenient features of vectors is that one can take orthogonal components of them – i.e. one can not only resolve the vectors onto the 120◦ axes but one can also resolve them onto 90◦ axes. Consider the situation depicted in Figure 10.8. This shows a desired voltage vector. Note that we have not considered what limits there are on the length of the voltage vector that can be produced by this system. We do know that the limit if the voltage vector lies on one of the natural vectors that can be produced by the inverter is 23 VDC . One can consider the vector in Figure 10.8 is a normalised vector (i.e. divided by 23 VDC ), and hence αd and αq are the normalised orthogonal projections onto
10.2 Inverters and Applications
Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6
Condition for sector √ αd > 0; αq ≥ 0; αq < 3αd √ αq > 0; αq ≥ 3 |αd | √ αd < 0; αq ≥ 0; αq < 3 |αd | √ αd < 0; αq < 0; αq > 3αd √ αq < 0; |αq | ≥ 3 |αd | √ αd > 0; αq < 0; |αq | < 3αd
353 Firing order V8 V1 V2 V7 V7 V2 V1 V8
T 4
T 4
V8 V3 V2 V7 V7 V2 V3 V8 V8 V3 V4 V7 V7 V4 V3 V8 V8 V5 V4 V7 V7 V4 V5 V8
T 4 T 4
T 4
(1
(1 + (1 + T 4
V8 V5 V6 V7 V7 V6 V5 V8 V8 V1 V6 V7 V7 V6 V1 V8
t0 (1 − αd −
(1
(1 −
αq √ ) 3 2αq − √3 ) α αd − √q3 ) αq αd + √3 ) 2α + √3d ) α αd + √q3 )
T 2 T 2
t1 (αd − α
( √q3 − αd ) αq T √ 3 α T − √q3
T 2
(αd +
a set of orthogonal dq axes. If we apply vector V1 for 2t1 seconds, and V2 for 2t2 seconds then the desired normalised vector, in an average sense, is obtained. It is possible to show, from the geometry of this situation, that for a given set of normalised orthongal vectors αd and αq the switching times for the vectors in sector 1 of the PWM star are: =
t2
=
t0
=
T αq (αd − √ ) 2 3 αq T √ 3 T αq (1 − αd − √ ) 4 3
(10.17) (10.18) (10.19)
where the various t values are defined in Figure 10.7. If a similar analysis is carried out for all the sectors then one can get a complete set of switching times as shown in Table 10.3. Another important aspect that was eluded to earlier was that there is limiting of the resultant space vectors. For example, one cannot ask for αd = 1 and αq = 1, since this would be asking for a resultant space vector that is larger than that which can be obtained given the vectors that the inverter can produce. If one applies the expressions from Table 10.3 to such a situation then this problem manifests itself by the condition [21]:
or:
2t2 2t1 + >1 T T
(10.20)
αq αd + √ > 1 3
(10.21)
in the case of sector 1 limiting. Clearly (10.20) means that the total switching time of the active vectors exceeds the total control period. It can be shown that the limitations imposed by the available firing times result in a hexagon limit. This is shown in Figure 10.9. If a desired vector exceeds the limit hexagon, then it has to be limited to the hexagon [21]. If the times are to be scaled so that they add to give one, then we require: 2t1 2t2 + γ =1 (10.22) T T or: γ=
1 αd +
α √q 3
αq √ ) 3 αq √ ) 3
− T2 (αd +
Table 10.3: PWM firing times for various sectors
t1
αq √ ) 3
(10.23)
t2 αq T √ 3
αq T √ ) 2 (αd + 3 α T − 2 (αd + √q3 ) αq T √ ) 2 (−αd + 3 αq T √ ) 2 (αd − 3 α T − √q3
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Introduction to Other Power Electronic Devices and Applications
Limit hexagon Limit circle V3 (010)
V4 (011)
V (110)2
2 V7 (111) (000) V8 5
3 4
1 6
(001) V5
(100)V 1
(101) V6
Figure 10.9: Voltage limit hexagon. Remark 10.10 Note that the use of the γ on both the total times means that the angle of the resultant vector is preserved. The new limited firing times for sector 1 are now: 2t1lim 2t2lim
= =
2t1 γ 2t2 γ
(10.24) (10.25)
The 1/γ values for all the sectors are summarised in Table 10.4. Remark 10.11 Space vector based PWM is particular amenable to implementation in digital form. This can be contrasted with carrier wave based PWM, which was originally devised for analogue implementation. Of particular importance is that this technique does not involve the solution of any transcendental equations, and it does not involve the use of any trigonometric functions. Sector 1 2 3 4 5 6
1/γ α αd + √q3 2αq √ 3
α √q 3
− αd α −(αd + √q3 ) 2α
− √3q α αd − √q3
Table 10.4: Voltage limit γ’s
10.2 Inverters and Applications
355
Remark 10.12 Another interesting feature of space vector PWM is that the maximum amplitude of the fundamental that can be produced by the technique is larger, by approximately 15%, than that produced by carrier based sinusoidal PWM. A similar effect can be obtained in sinusoidaly PWM by putting a third harmonic in the reference waveform.
10.2.2
Dead-time Issues
An important practical issue that arises with “totem pole” inverter legs is the problem of “shoot through”. This term refers to the phenomena of both the top and bottom device being momentarily on when there is a switching transition from the top to the bottom device, or vice-versa. Remark 10.13 The “shoot through” problem also exists in low power digital circuits. One may recall from Chapter 1 that CMOS and TTL both suffer from “shoot through”. In the case of digital systems the shoot through is a very short period of time, and the power levels involved are low. Consequently the problem can be tolerated. However, in high power inverter systems the devices will fail if “shoot through” occurs. Shoot through is overcome by making sure that the outgoing device is turned off before the incoming device turns on. This is achieved in practice by manipulating the device signals that turn the devices on and off. Phase A Leg
Phase B Leg
Phase C Leg
+
Initial current Final current
ia i
DC Bus Input/Output
ib
i
}
ia f ib
Three Phase Input/Output
f
-
Figure 10.10: Inverter showing the initial and final current flow after a leg is fired. The turn off of a power device is not instantaneous due to the phenomena of charge storage in the devices. In order to give the device time to turn off before turning on the other device in the a small delay (typically of the order of 3 to 4µsecs for todays IGBT devices) is allowed between the turning off of one device and the truning on of the other. This delay results in a different voltage being applied to the machine compared to that being demanded by the control. This is due to the fact that the dead-time delay results in a shift of the switching edges. The dead-time error problem is a little more complicated than I have outlined above. The presence of the dead-time switching delay is actually variable
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Introduction to Other Power Electronic Devices and Applications
{
Top
Leg A switching
On Off On
Bot Off
Dead - time Td
{
Top
Leg A currents
Bot
{
Top
Leg B switching
ia i
Desired switching point and actual switching point
0
ia f = ia i
0
On Off On
Bot Off
Dead - time Td
{
Top
Leg B currents
Actual switching point
0 ib
i
0
Bot i = i b b f
i
Desired switching point
Figure 10.11: Example of dead-time induced switching error in an inverter.
10.2 Inverters and Applications depending on the direction of the current through the inverter leg. The following discussion is with reference to Figures 10.10 and 10.11. Figure 10.10 shows two legs of an IGBT based inverter, with the current flowing out of leg A and into leg B. Figure 10.11 shows the effects of the current direction on the actual time of switching. As can be seen when current flows out of a leg (i.e. leg A) the actual time of switching is the desired time of switching. Therefore the deadtime of the inverter does not cause a problem. However, when current is flowing into a leg (i.e. leg B) then the switching time is delayed by the dead-time. Therefore, if one wishes to compensate for the dead-time so that correct switching always occurs, one should sense the current direction and compensate the switching time as appropriate. However, because the compensation of the switching time has to occur in the control interval before the interval it is going to be applied, then there is the possibility that the current direction may be incorrect. This situation only occurs around the times that the fundamental current is about to change direction. The result of incorrect compensation is that the cross-over of the current through zero may be considerably distorted – even more than if compensation is not being applied. This issue has not been resolved.
10.2.3
Some Inverter Applications
In this subsection we shall consider some of the applications for inverters. The presentation is by no means exhaustive, and the more common applications will be highlighted. 10.2.3.1
Variable Speed Drives
One of the most common applications of inverters are in AC variable speed drives. These drives are most commonly based on the use of induction machines. Figure 10.3 shows the generic layout of an AC drive. As mentioned in section 10.1 Converter 1 in this figure is often a uncontrolled three phase rectifier (although if the supply is single phase then one could have a single phase rectifier). Converter 2 is a conventional inverter, much as shown in Figure 10.4. At low powers and voltages the power devices in the inverter can be MOSFETs. At small to medium powers, the IGBT has become the device of choice. The range of operation of the IGBT is extending all the time in terms of the currents and voltages that can be handled. At the time of writing these notes IGBTs are available with maximum voltages of 6kV, and current capabilities in the thousand of amps range. Variable speed AC drives are becoming ubiquitous devices these days. They can be found in anything from domestic air conditioners, washing machines and microwave ovens, right through to large drives in power station bag houses and rolling mills. If better power sources are found, then AC drives will become very prevalent in vehicular transportation. They are currently widespread in train transportation. The main driving factors towards the increasing use of inverters are: 1. The simultaneous arrival of low cost high performance microprocessors, as well as reliable, robust and reasonable cost power electronic devices in the since the mid 1990s.
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Introduction to Other Power Electronic Devices and Applications 2. The refinement of the control algorithms for AC machines allowing high performance from AC drives. 3. A community demand for more efficient use of energy. Let us briefly consider a few of the applications mentioned above. It is not uncommon to hear in advertisements for air conditioners that they are inverter air conditioners. The inverter in these air conditioners are being used to drive the compressor in a variable speed mode. Normally an air conditioner is driven in an on-off mode, controlled by a thermostat. The reason for going to a variable speed mode is that the compressor is much more efficient in this mode. When a compressor starts for the next 30 to 60 seconds it is not really pumping any heat, but simply compressing the refrigerant. If the compressor is being started and stopped on a regular basis this non-productive time will be a significant part of the total operating time of the compressor. Under variable speed operation the thermostat simply controls the speed of the compressor, but it does not stop. Therefore the refrigerant does not have to be re-compressed, since it does not decompress whilst the compressor is running, albeit more slowly. Inverter air conditioners can be up to 30% more efficient as compared to the traditional onoff air conditioner (depending on operating cycle of the on-off air conditioner). Another domestic applicance that now has an inverter in it is the microwave oven. The inverter is used to supply variable voltage to the magnetron, and therefore get true variable power instead of pulsed on-off 100% power as in a conventional oven. This is main motivated by better cooking performance at low power levels. In actual fact the so-called inverter circuit in a microwave oven is more like a flyback switch mode power supply circuit. The switch mode supply can be operated at high frequency, and therefore allow a smaller high frequency transformer to be used. In addition, the output voltage and/or current can be controlled allowing completely variable, constant power from the magnetron. 10.2.3.2
Grid Connected Applications
As the power electronic devices improve in voltage rating, grid connected applications of inverters are becoming more common. The classic example of the use of an inverter in a grid connected application is interfacing photo-voltaics to the grid. In a photo-voltaic interface, the solar cells are producing DC voltage which either has to be converted into AC to feed the utility grid, or converted to AC to supply domestic AC appliances. Both of these are classic inverter applications. In some situations the output of the solar cells will firstly be fed to a bank of batteries for storage. It is then the DC in the batteries that is converted to AC. In other situations, the DC from the solar cells may be fed directly into the grid without the intermediate batteries (see Figure 10.12). This is the situation that is common for non-remote properties that are connected to the main utility grid supply. The inverter is its associate controller can either deliver power to the grid, or take power from the grid, depending on the insolation falling on the solar cells. In the case of remote properties, there in many cases will not be a utility supply, and the inverter would be powering the household appliances. A more industrial application of inverters is the static var compensator (SVC). A compensator is a device that can be connected to the power system to provide voltage support for the supply, especially at the end of long
10.2 Inverters and Applications
359
Controller
AC
DC Photo-voltaic solar cells
Inverter
Utility supply
Domestic load
Figure 10.12: Generic non-battery based photo-voltaic supply system.
Static Synchronous Series Compensator (SSSC) Statcom
Unified Power Flow Controller (UPFC)
Back-to-Back Statcom
Figure 10.13: Some grid connected FACTS units offered by Siemens.
360
Introduction to Other Power Electronic Devices and Applications transmission lines. This is achieved by the compensator being a variable capacitor. Traditionally this was achieved by using a synchronous machine, and varying the excitation to vary the apparent capacitive load represented by the machine. Later banks of switchable capacitors were used, the switching being achieved by thyristors. More recently a traditional inverter has been used. This circuit has the significant advantages over the previous techniques – injects less harmonics into the supply, very rapid bumpless changes can be achieved, can compensator for general power factor (i.e. can perform an active filter function). Figure 10.13 shows some variants of the static compensator (STATCOM) offered by the Siemens company. Some of these devices do more than simple static var compensation, and are capable of real poer flow control as well as reactive power flow control. AC transmission systems that include these power electronic devices are known as Flexible AC Transmission Systems (FACTS).
10.3
Multilevel Converters and Applications
To be completed.
10.4
Matrix Converters
To be completed.
Part IV
Appendices
Appendix A
List of Course Materials The supplementary course materials for the course for 2003, which are issued as separate documents, are: 1. The course handout (slightly varied version included in notes). 2. The course schedule (included in notes). 3. A Saber tutorial sheet (included in notes). 4. Assignment/Laboratory 1 (included in notes). 5. Assignment/Laboratory 2 (included in notes). 6. Exam 2000 (with solutions). 7. Exam 2001 (with solutions). 8. Exam 2002 (with solutions). These materials are handed out in class. They are also available from the following website: http://www.eecs.newcastle.edu.au/users/staff/reb
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List of Course Materials
Appendix B
Course Outline B.1
Text
These notes written by the Lecturer. Further information and clarification of issues presented in the course can be found in the references listed in the Bibliography at the end of these notes.
B.2
Introduction
This subject covers a wide variety of issues related to switching in electronic systems. The issues range from switching in digital systems to switching in switch mode power supplies and high power converters. The emphasis throughout the course will be on practical design related issues. The switching in digital systems will consider issues such as: logic families and their interfacing, signal propagation in digital systems, transmission lines and digital systems, cross talk mechanisms, printed circuit board issues, interboard cabling and measurement techniques. The switch mode power supply section of the course will consider the standard buck and boost switch mode configurations, and various combinations of these types. The presentation will necessarily be brief, but where possible relevant practical issues will be highlighted. Practical design issues will also be considered.1 The final section of the course is on high power line commutated converters and hard switched inverters. This section will begin with an introduction to the semiconductor devices used at these power levels, since these dictate the types of applications for this equipment. The basic operation principles of single phase and three phase converters will be presented. There will be a brief introduction to the concepts power factor and harmonic control in rectifier circuits. Some other power electronic devices and their applications will be introduced. 1 Due to time considerations, the chapter on the practical design of switch mode power supplies will not be part of the course.
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Course Outline
B.3
Course Objectives
This course has the following objectives: 1. To give the student a basic understanding of digital logic families and interfacing between different logic families. 2. To demonstrate the importance of switching edge times on the design of digital systems. 3. Students should understand the various digital line termination techniques, and how to apply them in practical design. 4. To give an understanding of the various cross talk mechanisms, how to identify them, and how to minimise them in practice. 5. Establish the basic principles behind good ground plane design for printed circuit boards. 6. Understand the non-ideal behaviour of passive components when used in high speed digital systems, and how design must be changed to account for this behaviour. 7. Establish the parameters of the non-ideal behaviour of wiring interconnect and how design must be compensated to account for this. 8. Give a basic understanding of the fundamental switch mode converters. 9. Investigate the comparative performance of different switch mode topologies. 10. Very basic understanding of the control strategies for switch mode power supplies. 11. Introduction of the semiconductor components used in high powered line commutated converters and hard switched inverters. 12. Basic analysis of the converters. 13. Consideration of power supply quality issues in rectifier circuits.
Assessment The subject will have two assignment/labs worth a total of 40% of the final mark. There is a mid semester quiz worth 10%. The examination at the end of the semester contributes the remaining 50% to the final mark. The assignments are intended to be done individually, although discussion of concepts and approaches with colleagues is permissible. Assignments that are copied will be given zero.
B.4 Plagiarism
B.4
Plagiarism
A student plagiarises if he or she gives the impression that the ideas, words or work of another person are the ideas, words or work of the student2 . Plagiarism includes: • copying any material from books, journals study notes or tapes, the web, the work of other students, or any other source without indicating this by quotation marks or by indentation, italics or spacing and without acknowledging that source by footnote or citation; • rephrasing ideas from books, journals, study notes or tapes, the web, the work of other students, or any other source without acknowledging the source of those ideas by footnotes or citations; or • unauthorised collaboration with other students that goes beyond the discussion of general strategies or other general advice. Plagiarism is not only related to written works, but also to material such as data, images, music, formulae, websites and computer programs. Aiding another student to plagiarise is also a violation of the Plagiarism Policy and may invoke a penalty. For further information on the University policy on plagiarism, please refer to http://www.newcastle.edu.au/policy/academic/general/academicintegrity policy new.html
B.5
Special Consideration
A candidate who claims that – study during the year or preparation for an examination; or study during the year or preparation for an examination; or attendance at or performance in an examination has been affected by illness, disability or other serious cause, may report the circumstances in writing, supported by medical or other appropriate evidence to program co-ordinator and request that they be taken into account in the assessment of the examination results of that candidate. Such request shall be made on the prescribed form. For further information on the University policy on Special Consideration/Special Examinations and Appeals, please refer to http://www.newcastle.edu.au/policy/academic/adm prog/exams.htm
B.6
Changing Your Enrolment
HECS Census Dates (last dates to withdraw without financial or academic penalty) are for Semester 1 – March 31, and for Semester 2 – August 31. If you don’t want to continue with the course then make sure you withdraw prior to these dates. To change your enrolment online, please refer to http://www.newcastle.edu.au/study/enrolment/change-enrol.html 2 “Plagiarised”
from the official University of Newcastle policy on plagiarism.
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Course Outline
B.7
Support Services
The Faculty Student Services Office is located on the entry level of building EF. If you have issues with enrolment then they can provide valuable advice. For other issues there is a Faculty “Omsbudsmen” who can provide assistance. His name is Dr Karl Bretreger located in room EA122. Other support services are offered by the The Dean of Students, Professor Anne Graham, located on Level 3 of the Student Services building. For more detail on the student support services offerd in the University Student Support Unit, refer to: http://www.newcastle.edu.au/intranet/student/support-services/index.html
Appendix C
Course Schedule Week
Dates
1
19/7–23/7 L: 19/7 L:21/7
2
26/7–30/8 L:26/7 L:28/7
3
2/8–6/8 L:2/8 L:4/8
4
9/8–13/8 L:9/8 L:11/8
5
16/8–20/8 L:16/8 L:18/8
Event
Handout Saber tutorial exercise
Assign 1/Lab 1 out
continued next page
Lecture Material Properties of digtal logic – CMOS, TTL. Interfacing of logic families, fanout, logic levels. Introduction to digtal switching. Digital knee frequency, transmission lines, kinds of reactance,capacitive cross coupling, inductive coupling, inductive di and dt crosstalk, dv dt effects, ground bounce, measurement issues. Brief review of second order circuits and transmission lines, point to point wiring and transmission lines in difital systems, reflections, termination techniques, distributed cross coupling, skin and proximity effects. Diode terminations, uniformly loaded lines, printed circuit board design, multi-layer boards, decoupoing issues, what is a good capacitor?, vias, zoning issues. Fundamental switch mode topologies – buck, boost,. C´ uk
370
Course Schedule
Week 6 7
10
Dates 23/8–27/8 L:23/8 L:25/8 30/8–3/9 6/9–10/9 L:6/9 (No lecture!) L:8/9 13/9–17/9 L:13/9 L:15/9 20/9–24/10 L:20/9 L:22/9 27/9–8/10
11
12
13
continued from previous page Event Lecture Material Full bridge converters, analysis of basic converter topologies. Directed reading on conNo lectures this verter topology analysis. week! Comparison of topologies. 1 2
hr Quiz
Switch mode power supplies, isolated converter topologies. Introduction to control techniques for switching power supplies.
Assign 1 in Assign 2 out
Introduction to high power switching devices.
Mid-semester break
No lectures
11/10–15/9 L:11/10 L:13/10 18/10–22/10 L:18/10 L:20/10 25/10–29/10 L:25/10 L:27/10
Review of Fourier analysis, generalised power factor Basic rectifier circuits,Single phase unity power factor rectifiers Three phase rectifiers, review of course
1/11-5/11
Stuvac Assign 2 in
8/11– 26/11
Exam period
No lectures
Appendix D
Introductory Exercise using Saber Simulator D.1
Introduction
Saber1 is a software simulation program. Its main attribute is that it allows the simulation of mixed mode systems – i.e. one can have continuous time analogue circuitry, digital circuits, continuous and discrete time transfer functions, magnetic systems (such as electrical machines and magnetic actuators), mechanical systems, and hydraulic systems all in the same simulation. This is unusual since most simulation packages cannot readily handle this mix of systems. They tend to be more specialised – i.e. only for electronic circuits, only for power systems, digital simulation packages etc. Simulation packages are very useful for the simulation of electronic systems, since the models of electronic components behave nearly the same as the actual component. In some circumstances simulation is almost mandatory, since a poor design can result in immediate catastrophic failure of the real circuit. An example where this is often true is in the area of power electronics. The Saber simulator consists of four major components: • SaberSketch: This provides a means to graphically enter a schematic to be simulated. • SaberGuide: To some degree this component is hidden, since it provides the connection between SaberSketch and the Saber Simulator. • Simulator: This module is the actual simulation engine. It is activated via SaberGuide. • SaberScope: This is the back end postprocessing section of the Saber system. SaberScope allows the user to process the files produce by the Saber simulator and produce new files of results, but more importantly it allows the user to generate graphs of the results. In this introductory exercise we shall be using the Saber simulator for circuit simulation. The circuit to be simulated is a very simple one, but it is able to 1 Saber
is a registered trademark for Avant!
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Introductory Exercise using Saber Simulator
vd
i
L
vL
R
vR
vS
Saber ground node Figure D.1: Simple single phase, half wave rectifier, with an LR load. demonstrate many of the features of the software. In order to minimise the simulation times we shall be using idealised components from the Saber parts library. If one wanted to work out the power dissipation in semiconductor components then the more realistic real component libraries would have to be used, but use of these makes the simulation times considerably longer. The circuit to be simulated is shown in Figure D.1. It is a simple single phase half wave rectifier circuit. The only complication is that it has a load that includes inductance.
D.2
Circuit Schematic Capture
The first step in the circuit simulation process is to capture the circuit schematic. This is achieved by using the SaberSketch section of the Saber suite. Figure D.2 shows the initial screen that appears when SaberSketch is invoked (via the Start menu).2 The sequence of steps to follow to set-up a design are as follows. Create the design: This is achieved by selecting the File→New→Design pulldown menu. If we wanted to open an existing design then one would use 2 The drawing area is shown in white in this figure. This has been done to prevent toner wastage when this document is printed.
373
{
D.2 Circuit Schematic Capture
Zooming controls
Grid control
Select to draw a line
Invoke SaberGuide
Parts menu
Figure D.2: Initial screen upon invoking SaberSketch. Open→Design, and then navigate to the desired file. Often if SaberSketch starts it will load the last design file automatically. Place parts on the schematic: The next step is to place the desired components on the blank schematic. The is achieved using the Parts Gallery button. When clicked-on this opens up another window which allows one to select the parts folder to be used. The folder that you will use for this exercise is the Analogy Parts Library. If one double-left-clicks on this then the contents of the Available Categories window will change to a selection of component categories. One can select a category, eventually ending up with a listing of individual parts in the Available Parts list scroll window. An example of this window is shown in Figure D.3, which shows the content of the Inductors & Coupling component category. To place a component in the schematic one selects a particular component from the Available Parts window and then click-on Place. The component will then appear in the middle of the schematic window. An alternative is to left-click-on the part and then go the to schematic window and click the middle mouse button (if there is one).3 One can also access the Parts Gallery via using the right mouse button selecting Get Parts→Parts Gallery, or from the Schematics main menu. As a specific example, if we want to place a diode on the schematic 3 Only
works if a mouse driver that recognises the middle mouse button is installed.
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Introductory Exercise using Saber Simulator
Figure D.3: An example of a parts gallery screen. then one navigates to the Analogy Parts Library→Electronic→Semiconductor Devices→Diodes category. From the Available Parts window select the Diode, Ideal (PWL) component and then press Place. If you look at the schematic you will find a green diode in the middle of it. The green colour indicates that the component is selected. If a component is selected then it can be dragged around the schematic to position it where one likes by moving the cursor pointer over it (the component then changes to red), pressing the left mouse button, and then dragging to the desired location. Set a parts properties: Once a part is on the schematic then its properties can be set. This is carried out by double-left-clicking on the part (one can also get the properties of the part by right clicking and then selecting the Symbol Properties on the drop-down menu). One can also obtain help on a part by selecting the Help drop-down menu from the properties screen. The Help explains the meaning and range of values for all the properties listed for the part. The properties window contains three columns – Property Name, Property Value and a set of round buttons on the right that denote the visibility of the property on the schematic. The latter two of these can be altered by the user. The Property Value fields can contain undef, or *req*. The undef field usually means means that the value is undefined, but the part will execute correctly with some underlying default value. However, in many cases this does not make sense. For example the resistor component has undef for its value, and clearly one would wish to set the value of a resistor in a particular circuit. If an undef value has to be defined the simulator will let you know when you try to run the simulation. The *req* field
D.2 Circuit Schematic Capture means that there are no default values defined, and it is mandatory to define a value. The values of the components can be entered in two main number formats. Saber uses a set of multiplier factors which are shown in Table D.1. One can of course use whole numbers, and also scientific notation if desired – e.g. 25e-4 for 0.0025. It should be noted that the ref property name contains a unique name for the part on the schematic. Sometimes if a part is copied on the schematic this name is not changed appropriately (this appears to be a bug in the software). Therefore one gets duplicate part references, and consequently the simulation fails. One has to manually change the ref name if this occurs.4 The visibility field allows one to nominate whether the property value (the visibility button is half on), or the property name and property value (the visibility full on), are to be displayed on the schematic. If the button is “off” then nothing about that property is displayed on the schematic. In a manner similar to the placement of the diode all the other components are placed on the schematic. The wires that join the components are drawn by moving the cursor over one of the component node points. The cursor will change to a cross-hair and pressing and holding the left mouse button will allow a wire to be drawn. There is a grid that wires and components lie on, which makes drawing the lines very simple. If for some reason the cursor does not change (for examples one is drawing a line not connected to a component, then the wire drawing tool can be selected (see Figure D.2). A wire which does not terminate on a component node can be terminated by double-left-clicking at the point where one wishes to stop the wire. Place a Saber ground node: A schematic must contain a ground reference designator for the simulator to be able to function. This symbol is called Ground (Saber Node 0) in the parts library. This ground symbol can be located in a number of places in the parts library tree. The ground is connected to the point in the schematic from which all the voltages in the design will be measured. Wires: We have already mentioned how to draw wires on the schematic. One can also select a wire and delete it by pressing delete on the keyboard, or right clicking and selecting Delete Wire on the drop-down menu. One can also alter the properties of a wire by right-clicking on the selected wire and selecting Attributes... on the drop-down menu (see Figure D.4 for an example of the Attributes... window). For example, one can change the name of a wire in the Name field in the window, and then select whether this name should be displayed on the schematic (which is often very handy for documentation reasons). Repeat the above steps until the complete circuit shown in Figure D.1 has been drawn. At this point we are now ready to start the simulation phase of the exercise. 4 A part can be copied by selecting the component and then moving the cursor to the place where one wishes to have the duplicate component, and then clicking the middle mouse button.
375
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Introductory Exercise using Saber Simulator Name femto pico nano micro milli kilo mega
Scientific Notation 10−15 10−12 10−9 10−6 10−3 103 106
Saber shortcut f p n u m k meg
Table D.1: Number magnitude specifiers in Saber
D.3
Executing the Transient Analysis
In order to carry out the simulation of a design one now has to invoke the simulator. This is achieved by pressing the SaberGuide button (see Figure D.2). One then gets the screen shown in Figure D.5. Note the new toolbar at the top of the screen. This toolbar allows one to control the Saber simulator from the SaberSketch window. The main tool used in SaberGuide is the DC/Transient button shown in Figure D.5. If one clicks on this button then the window shown in Figure D.6 appears. The parameters circled should be filled out so that the end time and time step of the simulation are set-up, and the simulator will automatically open SaberScope upon the completion of the simulation. One can see that there are a number of other tabs on the window. In more sophisticated simulations some of these may have to be used. The only other one that we shall look at in this simulation is the Input Output tab, which is shown in Figure D.7. The circled quantities have been altered from the default values. These alterations cause to simulator to save all the signals in the design, and all types of variables (across variables (i.e. voltages) and through variables (i.e. currents)).
Remark D.1 One can also select specific signals for the simulator to save. This is essential in large simulations otherwise the output files produced by the simulator are huge. The signals can be selected using the Browse Design... selection from the Input Output→Signal List→Select sub-menu. Note that the simulator has to be running to carry out this function, therefore it is necessary to start a simulation and stop it (using the Stop button), and then reenter this menu to carry out this function. Once all this information has been filled out then one simply clicks OK at the bottom of the window and the simulation will begin. It firstly netlists the design, and if this is successfully completed it will work out the dc starting condition, and then finally start the transient analysis. A rotating icon in the top right corner of the Saber window indicates that the simulator is running. When it finishes, which is very fast in the case of this simulation, the simulator will automatically open up SaberScope to allow the results of the simulation to be post-processed.
D.4 Plotting and Processing Results
Figure D.4: The wire attributes window.
D.4
Plotting and Processing Results
If SaberScope has not been set to automatically open then it can be opened manually via the Results→View Plotfiles in Scope... menu item. If SaberScope opens automatically it loads the plot file just generated by the simulator (because of the setting made in the DC/Transient screen), and then displays the plot file opened in the Signal Manager window, and the signals in this plot file in a second window named after the plot file. The SaberScope opening window is shown in Figure D.8. Notice in the Diode LR cct.tr signal window that some of the signals have a “+” next to them. This means that if one double-left-clicks on them then another more detailed signal list will expand from this root. One can then select one of these signals to plot, and then left-click the Plot button. Figure D.9 shows the inductor component expanded, and the i(m) signal plotted. Remark D.2 From Figure D.9 one can see the advantage of naming signals with meaningful names, as opposed to the default names given to the signals by Saber. The default names in the signal list window do not make much sense. When one is scanning through the signal list for complex designs, it is much easier to find the signals/components of interest if the names make sense. If one wishes to plot a number of variables, then left-click the desired signals holding down the Ctrl key on the keyboard, and then left-click Plot. The selected signals will all be plotted on separate axes. One can also superimpose several plots on the one set of axes. This can be achieved in two different ways,
377
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Introductory Exercise using Saber Simulator
DC and transient analysis button
Figure D.5: An example of SaberSketch with the Saber guide toolbar activated. dependent on whether one has already plotted the signals on separate axes. If one wishes to plot two signals on the same axis then select one of the signals and plot it, and then select the other, and go the the plot window and press the centre mouse button over the graph upon which one wishes the second signal to be plotted. The other way of plotting two or more signals on the same axis, is to firstly plot the signals on separate axes, and then use the Stack Region feature. This is activate by selecting one of the signals to be “stacked” on the same axis (this is achieved by placing the mouse cursor over the signal name to the right of the plot – the plot will go red, and then left-click), and then right-click and go the drop-down sub-menu Stack Region. At the bottom of this flyout one can see a number of Analog signals listed (the number dependent on the number of signals plotted on the graph window), with Analog 0 being the one at the bottom of the graph window. Select the analog signal number that corresponds to the axis that one wishes to plot onto. If one plots a signal and wants to delete it, then select the signal in the graph window, and then right click to get the drop-down menu and select the Delete Signal option.
D.4.1
Manipulating Results
One of the very powerful features of the SaberScope system is its ability to perform calculations on the results of the simulation, and also to take accurate
D.4 Plotting and Processing Results
379
Changed fields
Figure D.6: An example dc/transient simulation set-up window. measurements on the waveforms produced. Let us firstly consider the calculation capability. The waveform calculator allows one to subtract, add, multiply, divide, and perform a number of other manipulations on signals. The calculator is activated by pushing the “Calculator” button at the bottom of the screen. The signals that one wishes to carry out the calculations on are selected by left-clicking them in the signal window, and then middle clicking in the area just below the toolbar in the calculator. The signal name should appear in this window and the scrolling window immediately below it. The calculator works using reverse polish notation (like a HP calculator), therefore before selecting an operation we need to select the two signals to operate on. In the example shown in Figure D.10, we have selected the inductor voltage (vl) and current (i), and then selected the multiply function of the calculator (*) – i.e. we are working out the instantaneous power flow into the inductor. The
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Introductory Exercise using Saber Simulator
Changed variables
Figure D.7: The input-output table of the dc/transient analysis window. result then appears in the top window of the calculator. We can then plot this result by left clicking the small graph icon at the extreme left of the calculator toolbar. In order to look at a waveform in more detail one can expand the horizontal or vertical axis by simply selecting the axis by left-clicking, and then holding down the button to extend a yellow bar along the region of the axis that one wishes to expand. One can do this more precisely by right-clicking on the axis of interest and then using the drop-down menu to carry out a more precise numerical expansion of the axis (or alternatively go back to the original axis scaling). In addition to expanding the axes using the mouse cursor, one can also zoom in on the waveforms by simply clicking the mouse over the section of the waveform of interest, and then dragging out a square marque over the area. This area will then be zoomed on the plot.
D.4 Plotting and Processing Results
Figure D.8: The initial SaberScope window. All plotted curves have properties that can be altered. This is achieved by selecting the plot of interest, and then right-clicking and selecting Attributes.... The contents of the resultant window are self explanatory. The other major facility that is of use for processing plots is the measurement tool. This is activate by left clicking the “Caliper” button at the bottom of the SaberScope screen. This tool allows one to measure the precise absolute values of the quantities on the screen, rise time of steps etc. There are too many features to document here, so it is suggested that you have a look at the features, and try them to see what happens.
D.4.2
Fourier Analysis
The Fourier Analysis facility allows one to get frequency response plots for data produced by the simulator. A Fourier Analysis can only be performed after the simulator has run, and therefore falls into the post-processing category. In order to perform a Fourier Analysis one must firstly return to the SaberGuide window (don’t close the SaberScope window, simply iconise it to keep it out of the way). The following steps are carried out to perform a Fourier Analysis on a periodic waveform. 1. Select the Analyses→Fourier→Fourier... menu. 2. The left window in Figure D.11 will show up. I have filled in some values for this window. The Fundamental Frequency of the output waveforms is known as it was set by the frequency of the sine wave source in the circuit. The 80 millisecond time next to the Period End dialogue indicates that we are to analyse the period of the output ending at 80 milliseconds. Finally the Number of Harmonics stipulates the maximum number of harmonics that that analysis will calculate.
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Introductory Exercise using Saber Simulator
Figure D.9: A signal plotted in SaberScope. 3. Another tab in the Fourier window is the Input Output tab. Its contents appear as the right window in Figure D.11. In this case I have set the Signal List to be /... which means all signals, and the Include Signal Types is set to all, meaning that through and across variables are to be included. 4. Finally we left click OK or Apply and the Fourier analysis is carried out on the signals selected. Remark D.3 If one is analysing a non-periodic waveform or a pulse then the Fast Fourier Transform option should be used. In order to plot the results of the Fourier analysis go back to SaberScope and via the Signal Manager window open a file dialogue. One should see a new file with a fou.ai pl extension. Click on this file and click on Open. Another signal list box should open with the signals listed for which frequency data is available. These signals can then be plotted in a fashion similar to the time domain signals.
D.5
A Practice Exercise
In order to test your understanding of the above concepts it is suggested that you carry out the following on the circuit of Figure D.1. I suggest that you don’t blindly carry out the simulation, but try and understand what you are seeing in the results. For a simple circuit, it has surprising results, and you might learn something! 1. Execute the simulation and plot graphs of vs , vR , vL and i.
D.5 A Practice Exercise
Figure D.10: An example of a waveform calculation in SaberScope. 2. Measure the average and rms load current from the plots. 3. Measure the average voltage across the inductor, and try and explain the result. 4. Measure the voltage across the diode. What is the maximum reverse voltage it is subject to? 5. Plot graphs of the power dissipated in the load and the energy stored in the inductor. Measure the average power dissipation. 6. Measure the ac source power, and compare this value with the value dissipated in the load resistor. Why is there a discrepancy?
Figure D.11: Fourier analysis dialogues in Saber.
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Introductory Exercise using Saber Simulator 7. Perform a frequency analysis of the rectifier output voltage and current. Why is the spectrum of the current different from that of the voltage? 8. Replace the load resistor with a 300 volt dc source. Plot vS , i and vL . Note that current only flows for part of the half cycle of the voltage supply. Note where the peak current occurs. 9. Measure the average and rms values of the load current and voltage. Also measure the average power transferred to the load. Note that the average load power is now the product of the average current and average load voltage. 10. Perform a frequency analysis of the load current and voltage, and compare the results with the resistive load case. If the above exercise is carried out successfully then you should have a good preliminary working knowledge of the operation of the Saber simulation system. There are many other aspects of the system that we have not considered – you will need to know these for more sophisticated simulations.
Acknowledgment This tutorial is partially based on a Saber tutorial written by Dr. B.J. Cook of the Department of Electrical and Computer Engineering, University of Newcastle, Australia.
Appendix E
Assignment 1 Introduction This is a combined theoretical assignment and practical laboratory. This assignment/laboratory is a major assessment item for the course (worth 20%), and an appropriate time should be set aside for it. PLEASE start the assignment well ahead of the due date. In planning the time, one needs to take into consideration the time consuming nature of simulation studies, and the availability of the laboratory equipment. The assignment section mainly involves carrying out simulations of various PCB terminations in the Saber simulation package. Saber is available in the PC laboratory on the top floor of building EE (i.e. EE107/108). Students can also install and run the software at home. In order to run the software reasonably one will need the following: • At least 128Mb ram (this is the absolute mininum and the software will only just run with this) – the more the better as Saber is very resource hungry. • At least 400 MB of disk space for the Saber installation. You will also need approximatley 500MB of free space for swap on the disk. • Windows NT 4.0, Windows 2000, or Windows XP (I have not attempted to run the software on the Win95, Win98, Win Millenium systems. I suspect that it will not work). • An internet connect via modem or ADSL so that the licence server can be contacted to allow the software to run. Note that one must be connected to the internet for the duration of the simulation session. • The details of how to set up the environment variables so that the licencing will work. These instructions should be included with the software. If you don’t know how to use this package there is a demonstration exercise in the course notes appendix which you can do at your own leisure. This
386
Assignment 1 exercise will introduce you to the features of the Saber package needed for the assignment. The laboratory section of the assignment is designed so that you can confirm the results of the simulations using a special PCB that has appropriate traces and terminations placed on it. There are only two sets of equipment available for these labs1 , therefore the laboratory work will be carried out in an open laboratory manner. This means that you can come in to the laboratory, at a convenient time, and when the lab is open, and do the lab. It is quite OK for several students to do the lab together, but the interpretation of the results should be carried out individually. The equipment is very expensive, so please be careful during your experiments. Be particularly careful with the CRO probes, they are not very robust!
Collaboration Policy This assignment is meant to be an individual assignment. However, it is acceptable for students to discuss the assignment in order to understand what is going on. However, each student should produce their own individual report with the simulation and experimental results, with their own interpretation of the effects they observe. I draw your attention to the copy of the institutional plagiarism policy included in the course handout.
E.1
How to Answer the Questions
In the questions below you are requested to carry out a number of simulations and experiments. Associated with these are a number of explicit requests for explanations of the results. Please follow the following guidelines: • Could you please put a heading on these titled “Explanation for Q??.??”, highlighted, so that it is easy to located in the document. • Could you please keep the answers short and to the point. • Only include relevant plots. If the above is followed then this assignment should not be too arduous. Don’t get carried away with doing hours and hours of simulation – the simulations required for the assignment should not take inordinate amounts of time to complete.
E.2
Software Tools to Aid Report Production
Most students will be generating their results in electronic format. There are a number of techniques to include the diagrams for the simulations in your report. Saber itself has the ability to generate Postscript, jpeg etc. files. However, in 1 The limiting factor is the expensive cathode ray oscilloscopes and signal generators required.
E.2 Software Tools to Aid Report Production the past its capabilities in relation to this have not always generated the results one would desire (I have not checked the very latest version). Often the files produced, especially Postscript files, are huge and very difficult to manage in a word processing program. In order to aid the inclusion of diagrams students can download some software from my anonynous FTP server, at the following address in a Web browser: ftp://eecsbobb.newcastle.edu.au This is implicitly an anonymous ftp connection. If one connects using an FTP program, then the login requirements are (your input is boldfaced): username: anonymous password: put in your email address Once logged on, navigate to the Useful files directory. There are a number of files here, such as MWSnap, which is a very nice freeware screen capture program2 , IrfanView (a freeware viewer that also allows conversion of files to greyscale), Emacs (a public domain editor with LATEX aware mode), Miktex3 (a public domain version of the LATEX documentation system), Jpeg2ps (public domain converter for Jpeg files to Postscript), and several text editors. SaberScope produces by default colour plots. However, most students will be printing out their reports on black and white printers, therefore it may be advantageous to have the plots generated as black and white. This can be done by accessing the Graph→Color Map→Mono menu item. The actual lines of the plot will be converted to solid, dashed, dotted etc. lines. One can also right click select a plot and change these line styles as desired.
Question 1 Consider a fibre glass PCB that has a track width of 0.01 inch (which is a fairly typical). The permittivity of the FR4 board material is r = 4.5. The board FR4 material is 0.063 inch thick (i.e. 1.6mm). The copper on the board is 1oz per inch2 , or 30µm thick. From these specifications calculate the L0 and C0 per cm parameters for the line (hint the expressions in the Useful Formulae Appendix in the notes are useful for this, and pay attention to the limitations on physical dimensions for these expressions so that the right on is used). The track is sitting on a ground plane PCB – this means that one can consider that the ground return path has negligible inductance compared to the track. Given these parameters construct a transmission line of length 30cm using the Saber simulator. The line is being driven by a voltage source that has a rise time of 800psec and a ∆V of 3 volts. Carry out the following virtual experiments on this model of the transmission line: a. Generate the time domain plot for the voltages on the line at the source, load end several intermediate points along the line with the line terminated 2 This program allows one to capture any area of the screen and then save it to disk in a variety of different bit map file formats. 3 This document and the Elec3230 notes have been written in LAT X. E
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Assignment 1 as an open circuit, short circuit (use a small resistance value for this ≈ 0.01Ω) and with its characteristic impedance. Explain the waveforms that you observe. b. Change the termination approach to a source termination (as opposed to a load end termination) and plot the same results. Explain what you see and what are the implications. c. Allow another track to branch off the transmission line from the middle point. Initially make the two branch tracks the same length. Terminate both tracks at the end with the characteristic impedance and generate plots for the same points as in item a. Try different length branches for the tracks. Explain what you see from heuristic and theoretical viewpoints. How would you fix any problems observed? d. Investigate the effects of a mid track capacitive load of 10pf on the performance of the transmission line with a load characteristic impedance termination. Explain your observations. e. Design a RC load termination and simulate under the same input waveform conditions it to prove that it works correctly.
Hints • Make sure that you choose the appropriate time scale for the plots you generate. For example, for a transmission line of the type specified above the propagation delay is of the order of 2nsec. Therefore, depending on the question, time scales of 6 or 7 nsec in some instances, and between 12 and 15 nsec in others are appropriate. • The transmission line model should be constructed with the LC elements representing 1cm lengths of the line. This ensures that the model of the line is an adequate representation of the distributed nature of the line, whilst not over modelling the line and slowing the simulation, and generating huge output files.
Question 2 Consider the situation of two printed circuit board tracks on a PCB with the same parameters as in Question 1. These tracks are located 0.02 inch (or 0.508mm) apart, so there is mutual capacitance and inductance between them. One of the tracks is being driven with the same input signal as in Question 1, with the driver modelled as a voltage source with 31Ω of output impedance (i.e. similar to a TTL or CMOS output impedance). It is terminated with its characteristic impedance. The other line is initially terminated at the near (i.e. the end near the source of the driving line) and far ends with its characteristic impedance. Set up a Saber simulation to model this. Assume that the mutual capacitance is 0.1pF/cm, and the mutual inductance is 1nH/cm. For the following simulation results try and use theory to explain the results where possible. Carry out the following virtual experiments:
E.2 Software Tools to Aid Report Production a. Initially set the mutual capacitance to zero and consider what happens on the receiving PCB track at the terminations and mid points along the line. b. Repeat the above with the mutual inductance equal to zero and the capacitance equal to 0.1pF/cm. c. Now carry out the same tests with the mutual inductance and capacitance both present. Which of the two effects is dominant in the response? d. The situation thus-far is artificial in that the receiving line is terminated at both ends with the line characteristic impedance. Now replace the left hand termination with a short circuit and then repeat item a. Explain the results.
Laboratory The laboratory experiments will be carried out using a PCB with a ground plane, traces, and terminations place on it. The layout of the board is shown in Figure E.1. You will note that the board uses BNC connectors to connect to the CRO. These connectors connect to the measurement points using the “home brew” probe technique discussed in class. The objective of the lab is for you to see that the effects discussed in class, and seen in the simulations, actually do occur in a real PCB trace. In addition, comparison of the simulation and experimental results will allow an assessment to be made as to the usefulness of simulation in understanding the issues in this area. The laboratory equipment is located at the rear of the communications laboratory (EE104) on the top floor of building EE.
Laboratory Equipment The following equipment should be available on the lab bench for you to carry out the experimental studies: • Switching Electronics Laboratory PCB (see Figure E.1 for layout). • Agilent 81110A 165/330MHz Pulse/Pattern Generator, OR, Philips PM5776 1Hz–100MHz 1nsec risetime Pulse Generator, OR any other signal generator capable of producing a pulse rise time of 1nsec or less. Most of the standard signal generators are not capable of doing this. • HP 54542A 2Gs/sec 500MHz CRO, OR, Agilent 2Gs/sec 500MHz CRO, OR other 500MHz 2Gs/sec CROs with file storage and mathematical processing facilities. The oscilloscopes should have conventional 500MHz probes. The later Agilent CROs are the easiest CROs to use. • Three working 50Ω coaxial cables with standard size BNC connectors on both ends.4 You will also need a 1.44MB floppy disk to store the plots from the CRO. 4 Note that sometimes the coaxial cables have faulty soldred connections, so check that them by looking that the input signal.
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Assignment 1
Figure E.1: Test Printed Circuit Board.
E.2 Software Tools to Aid Report Production
Using the Equipment The Agilent signal generator and the two cathode ray oscilloscopes (CROs) mentioned in the equipment list above are complex pieces of equipment. For a person who has previously used a CRO (as most students doing this lab should have), using the CROs should not be a big problems. With a little experimentation and button pushing one can even work out how to use the more advanced features such as risetime measurement, and using waveform markers. Make sure that you set the CRO inputs to be 50Ω input impedance (there is also a 1MΩ input impedance option). The Agilent pulse generator is a complex piece of equipment. Fortunately it is fairly easy to operate, even without a manual. One should ensure that the rise time of the signals is set to 800psec (there is also a 1.6nsec option), and the output levels need to be set – the maximum output level is 4V. In addition the outputs are current limited, so this level must be set to a level that allows the output to go to 4V with a 50Ω load. You should set the generator to make, say, a 100µsec pulse at a frequency of say 2000Hz. If you are using another signal generator, then make sure that the rise time is set to be 1nsec or less. The frequency is not critical, but the pulse width must be long enough to allow the line to settle to steady state before another switching edge. You will need to save your results for the report. On the HP oscilloscope this can be done using the following sequence, which must be done before you generate your waveforms:5 • Press “Shift disk” – the Shift button is the blue one. • The storage options will then come up on the screen. Select “Store image enable”. • On the next set of menus select the TIF storage format. • Set auto-increment for the file name. The auto-increment feature for the file name means that the default file name will have a number added to it for each stored screen. If this is not selected then the initial file will be overwritten. To save a screen to the floppy disk, Press “Stop” to freeze the screen, and then “Print”. A message should appear saying that the data is being saved to a file. One other task that you have to do is to integrate a waveform. This function can be accessed from the “Math/FFT” button on the front panel of the HP CRO. If you are using another CRO then consult the manual to see how to carry out the equivalent operations.
Preliminary Work There is a little preliminary work to be done before doing the actual experiments. Several resistors are shown in Figure E.1. Determine the values of the resistors. In order to do this one must know what the resistors are to do: 5 Make
sure that you have a floppy in the drive before doing any of this.
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Assignment 1 • The first track has resistors RS1 and RT1 . These resistors have to be selected to make the trace look like 50Ω from the signal generator coaxial cable point of view, and the characteristic impedance of the line looking from the trace side. • The RT2 resistor is to match the 50Ω signal cable to the trace. There is no requirement for matching from the trace back to the coaxial signal cable.
The Experiments The experiments to be conducted on the PCB will mirror the simulation studies carried out in Questions 1 and 2. Carry out the following: 1. For the trace at the top of the PCB (i.e. the source terminated trace) generate a plot for the source end, mid-point and end of line waveforms. 2. For Experiment d generate the end of line plot using the standard CRO probe for the oscilloscope that it being used. There is a connection loop at the load end of the line to allow this measurement. Explain the different result from that obtained using the inbuilt “home brew” probe. A 3. For the second set of traces from the top of the board (i.e. the two traces that are very close together) plot the voltages across the non-driven line at the mid point and the end termination. Explain what you see and compare the results to those obtained for the equivalent situation in the simulation of Question 2. Were the parameters estimated in Question 2 close to the correct values. 4. The next experiment involves a trace with a branch off it – i.e. the third trace from the top of the board. Plot the waveforms on the originating trace prior to the branch, and at the end termination, and explain what you see. How well do the experimental results correlate to the simulation results. 5. The fourth trace from the top of the board has a 10pf capacitor on it to simulate the input capacitance of a logic gate. Plot the waveforms before the capacitor, and at the end termination and explain the observations. How well do they conform to the same situation when simulated. 6. Using the set of resistor to the left hand side of the board (capacitively coupled resistor circuit) and plot the coupling voltage waveforms. Work out what the coupling current and mutual capacitance values are. 7. Using the right most resistor circuit (inductively coupled resistor circuit), plot the coupling voltage. Calculate what the mutual inductance is between the two components is (account for the capacitance coupling that will also be present in this case).
Appendix F
Assignment 2 F.1
Introduction
This assignment/lab is on switching regulators. We shall consider the following switch mode converter structures: • The buck converter. • The boost converter. • The isolated forward converter. This assignment is a major assessment item, so allocate enough time to do it. The buck and boost converter sections will earn 86% of the marks, and the section on the forward converter only 16%. Therefore, if you are pushed for time, then concentrate your efforts on the first two sections. In order to carry out the experiment one needs to understand the circuitry of the experimental system. The power side circuit of the experimental kit is shown in Figure F.1. You will notice that the circuit switching elements are all BJTs, and not MOSFETs. This is due to the vintage of the experimental kit (which was developed many years ago by a student project). You will also notice that there are several passive components, as well as four high speed diodes, included in the kit. In addition to the power side of the kit there is also control circuitry. This is based on the National Semiconductor LM3524 switching regulator integrated circuit. For completeness the data sheet for an updated version of this IC (LM3524D) is included at the end of this lab sheet. The control circuitry included in the experimental kit is shown in Figure F.2. The oscillator allows control of both the ton and toff times. Remark F.1 You should note that the transformer used in the kit is a standard pulse transformer and has four windings. Only three of the windings are available to the user. The fourth winding is terminated with a resistor so that any oscillations that occur due to the interaction of the leakage inductance and the winding capacitance will be damped out (i.e. one can get underdamped LC oscillations due to this interaction). If you are not using a winding you should also terminate that winding with a resistor (don’t make it too small or too big –
394
Assignment 2
1
+12V
2
1 220W BC327
1mF
8mH
2.2mF 1kW
1kW
1W
1W
100V
2kW
1kW
1kW
0.01mF
BC337
BC337 BC337
46V
BC337
1kW
100W 2.2kW
0V
1N4448 1kW
220W 2.2kW
BC337
Figure F.1: Power circuit of switch experimental box.
10k
FB (feedback)
OSC
PWM
1N914
10V
1N914
5k
4.7k 22k
2.2k
1
16
2
15
3
14
4
9V
10k 1k
5
LM3524
5k
10k
560 2.2k
13
+
12
6
11
7
10
8
9
+
+
3 ´ 1000 mF 16V
0.1mF
1N914 1nF
0.0047 mF
50k 0.0047 mF
3.3k 4.7k
0.001mF
0V
Figure F.2: PWM control circuit for laboratory module.
F.2 Equipment Required several kΩ should be OK). The presence of the unused windings (even correctly terminated ones) leads to a distortion of the waveforms across the switching transistor when the transistor is turned off. Remark F.2 Most of the output transistors are current overload protected. However, please don’t test this, as I don’t know how good the current protection is. Remark F.3 The output transformer is not a power transformer, therefore it has a low power output capability of approximately 200mW (according to the laboratory manual written by the designer of the module). Consequently be careful that you do not overload it. Remark F.4 For many of the plots suggested below it may make sense to plot the switching waveform to the transistor at the same time. This allows one to correlate the waveform with the switching signals.
F.2
Equipment Required
a. Switch mode power supply experimental kit. b. Cathode ray oscilloscope (CRO), preferably with an ability to save the screen plots to a floppy disk. You do not need to have the very high speed oscilloscopes since this application is not very demanding from a frequency point of view. c. Current probe – only modest currents will be measured so this does not need to be a high current probe. d. Standard CRO voltage probes. e. 12V power supply. f. Miscellaneous resistors which can be used for different loads.
F.3
The Experiments
F.3.1
The Buck Converter
The first section of this experiment involves setting up a Saber simulation of a buck converter with open loop control – i.e. the switch of the converter is driven from an oscillator. The circuit to be simulated is shown in Figure F.3. a. Calculate the output ripple as a function of the frequency of the switching (with the component values shown). Assume that the nominal DC output voltage is 5V. b. Determine the output load value for which the inductor current will become discontinuous. c. Simulate the circuit of Figure F.3 so that the output ripple is 50mV. You can determine the appropriate frequency from the expression derived in Item a.
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Assignment 2 prbit_l4
prbit_l4
BIT STREAM
BIT STREAM
sw1_l4
switch_output_voltage
100
v_o
10
pwld
sw1_l4
v_dc
pwld
50e-3
100e-6
40000
Figure F.3: Buck converter – Saber circuit. d. Simulate the transient performance of the circuit in open loop with a step change in the load resistance. e. Increase the load value in the simulation and verify that the inductor current becomes discontinuous at the value calculated in Item b f. Place a closed loop PWM controller around the circuit of Figure F.3. The controller should have the general form shown in Figure F.4. You can use the ideal operational amplifier components from the Saber simulator library. Simulate the circuit with the control around it (you will have to determine the feedback gain to get the best performance without the system becoming unstable). Again simulate a step change in the load on the circuit performance (i.e.1kΩ to 500Ω). g. Set up the open loop circuit of Figure F.3 on the experimental module.1 Plot the current through the switch and through the inductor. Plot the output voltage ripple. Comment on the comparison of these plots with those obtained in the simulations. Find the value of load resistance required to get discontinuity in the inductor current, and compare with the theoretical value.2 h. Finally close the loop around the buck converter. The output voltage of the output is fixed by the resistance setting in the control circuit shown in Figure F.2. Experiment with step changes in the load resistance and consider the transient response of the output.3
F.3.2
Boost converter
Remark F.5 The output voltage of the experimental boost converter has to be controlled to be under 46V to prevent the Zener diode across 1 You
do not have an ideal switch in the module, so you will have to choose a transistor switch. Consult Figure F.1 to determine which switch to use. 2 You may have to connect an external resistor not included on the module to achieve this. 3 You should be able to trigger the CRO on the output transient if you use AC coupling. The load changes can be effected by plugging and unplugging a resistor.
F.3 The Experiments
397
verr
R1
Error amplifier PWM generation -
+
Vo
+
Switch interface
-
R2
Vref (Voltage reference)
To switch
Vtri (Triangular waveform)
Figure F.4: Conceptual PWM control circuit for the buck converter.
prbit_l4 BIT STREAM
prbit_l4 BIT STREAM
v_dc
10
100
sw1_l4
50e-3
v_o
sw1_l4
pwld
100e-6
40000
Figure F.5: Saber model of the boost converter.
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Assignment 2 the output transistor (as shown in Figure F.1) from distorting the output waveform. a. Calculate the output voltage versus duty cycle for the circuit of Figure F.5 with: (i) continuous inductor current, and (ii) a discontinuous inductor current. The load is a 1000Ω resistor and a 30V output voltage. Calculate the output ripple. b. Simulate the circuit of Figure F.5 and confirm the calculations of Item (a). c. Place a feedback controller, based on that of Figure F.4, around the circuit of Figure F.5 and simulate the stability of the resultant configuration. Apply step changes in the load resistance and plot the resultant output transient performance. Comment on the stability of circuit, and suggest how it may be improved. d. Set up the boost converter circuit of Figure F.5 on the experimental module. Apply a duty cycle so that a 30V output voltage is generated. Make sure that you start with a small duty cycle so that you do not generate a voltage that is too high for the transistor. Plot the current through the inductor. Experiment with changes in the duty cycle and look at the inductor current – is there any non-linearity in it and if so why? e. Change the load resistance in the experimental circuit of Item (d) so that the current in the inductor becomes discontinuous. Use the value calculated in Item (a) as a starting point. Plot the current in the system as that current becomes discontinuous. Generate plots that demonstrate the voltage gain of the converter under discontinuous current operation.
F.3.3
Forward converter
Remark F.6 Note that this section is only worth 16% of the mark, so if you are pressed for time then concentrate on the previous two converters. The magnetising inductance of the transformer in the experimental module is 0.00638H unsaturated. Saturation begins at 0.18Amp to 0.2Amp, so keep the primary current below this value. a. Calculate the duty cycle boundaries for the isolated forward converter circuit shown in Figure F.6 assuming that N1 : N2 = 1 : 1 and N1 : N3 = 1 : 2, and alternatively N1 : N2 = 1 : 2 and N1 : N3 = 1 : 1. Comment on the effect of the various turns ratios on the performance of the circuit. Calculate the voltage gain of the converter with continuous and discontinuous output filter current and arbitrary turns ratios. b. Set up the circuit of Figure F.6 in Saber and plot the output voltage, the voltage across the switch, the voltage across the energy feedback winding, the current through the energy feedback winding, and the current through the filter inductor for the various winding configurations. Alter the duty cycle so that the filter inductor current becomes discontinuous and check the value against the values from the expressions calculate in Item a.
F.3 The Experiments
399
D1
L
N3
+
N1
N2
D2
vL
iL
C
RL
Vo
Vd D3
SW
Figure F.6: Practical isolated forward converter circuit. c. Include a small leakage inductance in the Saber model of Item b and plot the output voltage across the switch. Compare to the situation when there is no leakage. Add a snubber circuit and redo this. d. Set up the circuit of Figure F.6 on the experimental module. Plot the same results as for Item b, and explain any discrepancies between the simulation and experimental results. Is there any sign of leakage inductance effects in this circuit? Apply a snubber to the switching transistor and replot the output voltage across the transistor.
400
Assignment 2
Appendix G
Review of Second Order Circuits This appendix will give a brief review of second order circuits. This is included as second order series and parallel circuit inevitably come into high speed digital systems due to the presence of inductance and capacitance in the various circuits.
G.1
Series RLC Circuits
Consider a circuit of the form shown in Figure G.1. Carrying out standard loop analysis we can write the following differential equation for this circuit: R
d2 i dv i di +L 2 + = dt dt C dt
(G.1)
Taking the Laplace Transform of (G.1) we can write the following transfer function for the current: i(s) sC = vin (s) LCs2 + RCs + 1
transfer function
(G.2)
and therefore the transfer function for the voltage across the capacitor is: vo (s) 1 = 2 vin (s) LCs + RCs + 1
(G.3)
One can see that the poles of (G.3) are: R ± s=− 2L
which can be written as: s = −α ±
R2 1 − 2 4L LC
α2 − ωo2
poles
(G.4)
(G.5)
402
Review of Second Order Circuits
R
+ vin
C
vout
i
-
L Figure G.1: Series RLC circuit where: R 2L 1 ωo = √ LC α=
natural resonant frequency resonant frequency damping factor
(G.7)
One can get a better impression of the position of the poles if they are plotted on the complex plane. This is shown in Figure G.2. Note that this diagram is only showing one of the two conjugate poles. We can define several other terms from this diagram. The natural resonant frequency, ωd , is the frequency of oscillation of the natural response (i.e. source free response) of the circuit when there is resistance present. This is different from the resonant frequency, ωo , which is the resonant frequency of a lossless series RLC circuit.1 Another variable of interest is the damping factor . The formal definitions are:
ωo2 − α2 (natural resonant frequency) α (damping factor) ξ = cos θ = ωo
ωd =
critical damping
(G.6)
(G.8) (G.9)
From Figure G.2 one can see that if the poles are off the real axis of the complex plane then there is a projection of the complex vector onto the imaginary axis. This means that there is an oscillatory mode in the response of the circuit. If the angle θ is zero, then the two poles are coincident. This condition corresponds to critical damping.2 Because there is not projection onto the imaginary 1 The resonant frequency is the frequency at which a driven series RLC circuit will exhibit is minimum impedance. 2 Critical damping gives the fastest response without overshoot.
G.1 Series RLC Circuits
403 Im wo
wd
wo
q
Re
a
Figure G.2: Series RLC circuit pole positions. axis there is no oscillatory or over shoot behaviour in the response. From the viewpoint of the equations critical damping corresponds to the condition: (G.10) ωd = ωo2 − α2 = 0 Therefore critical damping means that: α = ωo 1 R =√ 2L LC L ∴R=2 C
(G.11)
For the case where: α > ωo
(G.12)
we have two real poles generated. One the these poles will move towards the left on the real axis and the other to the right. The system response is now very slow, and it is said to be overdamped . There are no oscillations. Another important property of a series RLC circuit is its impedance. Rearranging (G.2) we can write the impedance transfer function: Z(s) =
vo (s) LCs2 + RCs + 1 = i(s) Cs
(G.13)
If we let s = jω (i.e. the resonant frequency), and substitute this into (G.13) we get: 1 ωL − jωC j 2 ω LC − 1 =R+j ωC
Z(s) = R +
(G.14)
overdamped
404
Review of Second Order Circuits Clearly the magnitude of this expression has a minimum value when the imaginary term is zero. Therefore: ω 2 LC − 1 = 0 ⇒ ω = √
1 = ωo LC
(G.15)
The minimum impedance is R under this condition. As noted earlier, this occurs at the resonant frequency (ωo ), and not the natural resonant frequency (ωd ).
G.1.1
Quality Factor
Another important measure of resonant second order circuits is the quality factor – Q. When a circuit is being driven in resonance this is defined as: Q 2π
Total energy stored in the circuit Energy dissipated per period
(G.16)
In the case of the series RLC circuit consider it to be driven with i(t) = Im cos ωo t. The expression for the instantaneous energy stored in the inductor is: 1 1 2 eL (t) = Li2 = LIm cos2 ωo t (G.17) 2 2 Similarly the energy stored in the capacitor is: eC (t) =
2 1 2 1 Im I2 L Cv = sin2 ωo t = m sin2 ωo t 2 2 2 ωo C 2
(G.18)
Therefore the total energy is: eL (t) + eC (t) =
1 2 1 2 LIm (cos2 ωo t + sin2 ωo t) = LIm 2 2
(G.19)
which is obviously a constant. The average power dissipation in a resistor with a sinusoidal input is: 1 2 I R 2 m and hence the energy dissipated over a period To is: PR T =
PR =
(G.20)
1 2 1 2 Im RTo = I R 2 2fo m
(G.21)
Using (G.19) and (G.21) in (G.16) one can write: Q = 2π
1 2 2 LIm 1 2 2fo Im R
L = ωo R 1 L ∴Q= R C If Q = 0.5 then:
= 2πfo
L R
1 using ωo = √ LC
(G.22)
1 L L R= =2 (G.23) Q C C which is the same expression for the resistance when the circuit is critically damped.
G.1 Series RLC Circuits
G.1.2
405
Time Domain Response
Let us now consider the time domain solution of (G.3). In this we shall be assuming that for t < 0 then vin (t) = V0 , and at t ≥ 0 vin (t) = 0 – i.e. the voltage drops to zero. Therefore the circuit becomes a source free circuit with an initial voltage on the capacitor of V0 volts. Therefore we only need to consider the natural response of the circuit. This situation will also give us a lot of information about the case when there is a positive step in the voltage. Examination of (G.1) suggests that a possible candidate solution is: v0 (t) = A1 es1 t + A2 es2 t
(G.24)
s1,2 = −α ± jωd
(G.25)
where: Expanding the exponential terms in this equation we can write: v0 (t) = e−αt [B1 cos ωd t + B2 sin ωd t]
(G.26)
where: B1 = A1 + A2 B2 = j(A1 − A2 ) In order that we can determine the B1 and B2 coefficients we apply some boundary conditions: v0 (0) = V0
(G.27)
dv0 (0) =0 dt
(G.28)
Applying the first of these conditions to (G.26) we can write: B1 = V0
(G.29)
Taking the derivative of (G.26) we get: dv0 = e−αt [(B2 ωd − αB1 ) cos ωd t − (B1 ωd + αB2 ) sin ωd t] dt
(G.30)
Applying (G.28) to this expression gives: αB1 = B2 ωd ⇒ B2 =
αV0 ωd
and hence the voltage equation becomes: α v0 (t) = V0 e−αt cos ωd t + sin ωd t ωd
(G.31)
(G.32)
and the derivative of this is: dv0 (t) = −V0 dt
α2 ωd + sin ωd t ωd
(G.33)
406
Review of Second Order Circuits From (G.8), (G.7), (G.6) and (G.22) we can derive the following expressions: R2 1 − ωd = LC 4L2 1 1 − = LC 4LCQ2 1 1 =√ 1− (G.34) 2 4Q LC We shall assume that Q > 0.5, which means that the circuit is underdamped and ωd > 0. If we want to find the point of the first maximum swing in the time response (i.e. the first maximum in the oscillatory response), then we know this must occur when ωd t = π. Therefore: π ωd √ π LC = 1 1 − 4Q 2
tf m = ⇒ tf m
(G.35)
We also also write: v0 (tf m ) = −V0 eαtf m
⎡
since ωd tf m = π LC 1− 1 2 4Q
∴ v0 (tf m ) = −V0 e
= −V0 e
⎤
√
R ⎣ π − 2L
√
−π 4Q2 −1
⎦
(G.36)
Figure G.3 shows that time plot for a series RLC circuit. In this particular case the circuit Q is 6.3. From (G.36) we can drawn the conclusion that:
Vovershoot /Vstep = e
G.2
transfer function
√
−π 4Q2 −1
(G.37)
Parallel RLC Circuits
This section carries out a similar analysis for a parallel circuit RLC as was carried out above for the series RLC circuit. To a large extent the results for this circuit configuration are a dual of those above, therefore some of the analysis here will be brief. The following discussion will be with reference to Figure G.4. If one applies nodal analysis to this figure one can write the following differential equation for the circuit: vin 1 diin 1 dvin d2 vin + = (G.38) + dt2 RC dt LC C dt If we take the Laplace transform of this and rearrange we can get the following transfer function:
G.2 Parallel RLC Circuits
407
1 0.8
LR O
t e MN 2L PQ
0.6
Voltage v volts
0.4 0.2 0 -0.2 -0.4 - 0.6 -0.8 0
0.5
-p
v 0 (t fm ) = -V0e
1
1.5
t fm =
4Q 2 -1
2 2.5 Time t (secs)
3
3.5
4
p LC 1 14Q 2
Figure G.3: Time response of a series RLC circuit with Q = 6.3.
iin
vin
R
L
Figure G.4: Parallel RLC circuit.
C
408
Review of Second Order Circuits 1 C(s2 + RC s+ iin (s) = vin (s) s
1 LC )
(G.39)
impedance transfer function
The impedance transfer function can be simply written from a rearrangement of (G.39 as: vin (s) s Z(s) = = (G.40) 1 1 iin (s) C(s2 + RC s + LC )
poles
As in the series RLC circuit case we can now find the poles of this transfer function, which have a similar form to those for the series RLC circuit: (G.41) s = −α ± α2 − ωo2 where: 1 2RC 1 ωo = √ LC
(G.42)
α=
(G.43)
As with the series RLC circuit we can define: ωd = ωo2 − α2 Critical damping
(G.44)
Critical damping is defined similarly to that for series RLC circuits in that ωd = 0. This leads to: α = ωo 1 1 =√ ∴ 2RC LC 1 1 ⇒R= 2 LC
(G.45)
The impedance of the circuit at resonance, as with the series RLC circuit, is of interest. Substituting s = jω into (G.40) and simplifying and taking the magnitude we can write: |Z(s)| =
ω2 R2
+
ω 1 L
− Cω 2
(G.46)
√ If ω = ωo = 1/ LC then: |Z(s)| = R
(G.47)
which can be shown to be the maximum impedance of the circuit.
G.2.1
Quality Factor
This will not be evaluated in the same detail as was carried out in the series RLC circuit section since the development is so close. However, the key expressions will be presented. It is assumed that the input voltage has the form: vin = Vm cos ωo t
(G.48)
G.2 Parallel RLC Circuits
409
Therefore the current into the inductor is: 1 t i= vin dτ L 0 1 t Vm cos ωo tdτ = L 0 Vm sin ωo t ∴i= Lωo
(G.49)
The energy stored in the inductor is therefore: 1 2 Li 2 1 = Vm2 C sin2 ωo t 2
eL (t) =
(G.50)
Similarly the energy stored in the inductor is: 1 2 Cv 2 in 1 = CVm2 cos2 ωo t 2
eC (t) =
(G.51)
The total stored energy is: eT (t) = eL (t) + eC (t) 1 = Vm2 C(sin2 ωo t + cos2 ωo t) 2 1 = Vm2 C 2
(G.52)
The energy dissipated in the resistor is: eR (t) = PR To = =
Vm2 To 2R
Vm2 2fo R
(G.53)
Applying the definition of quality factor (G.16) we can write: 1 2 V C Q = 2π 2 Vm2 m
2fo R
= 2πfo RC = ωo RC C =R L
(G.54)
410
Review of Second Order Circuits
Appendix H
Review of Transmission Lines This appendix carries out a brief review of classical transmission line theory. Much of the work in the appendix is based on [22]. A transmission is distinguished from a traditional lumped circuit network in that it is a transmission medium that is long enough that the currents and voltages at various points in the line cannot be considered to be the same value at any point in time. Therefore the line length is at least of the order of the wavelength of the signal being propagated down the line. Since an ideal transmission line is considered to be uniform, then the distributed nature of the currents and voltages (in respect of distance down the line) lead us to the conclusion that the line can be considered to be an infinite number of infinitesimal elements distributed along the line, each set of elements reacting to the local voltage and currents at any point of time. Remark H.1 Any propagation line really is a transmission line. However, if the wavelength is long compared to the physical length of the propagation line then the simplification can be made that at every point the same current voltage equations apply. This results in significant simplifications in the equations one uses to analyse the line. This is the basis of conventional lumped model circuit theory. Consider a transmission line consisting of two parallel wires of radius a and let the distance between the axes of the wires be denoted by b. The following transmission line equations, which are based on a circuits view of the transmission line, are valid under the following assumptions: 1. The separation distance b between the two wires and, therefore also the radius a of the wires is small in comparison with the space scale length of variations of the voltage and current as well as the associated electric and magnetic fields. 2. The transmission line is uniform – i.e. every section of it is the same as every other section.
412
Review of Transmission Lines 3. In general the currents in the two wires at a cutting point across the wires can obey the following law: I1 = IB + IU
(H.1)
I2 = −IB + IU
(H.2)
where: I1 − I2 2 I1 + I2 IU = 2
IB =
Notice that the currents consist of two components – the IB components are equal and opposite in the two wires. The IU components though are in the same direction in the two wires. This is the situation that occurs in an unbalanced transmission line and has to be treated using electromagnetic theory. It shall be assumed in this analysis that the line is balanced and the IU component is negligible. Remark H.2 Assumption 1 implies that: a
(H.3)
where λ as the wavelength of the electromagnetic wave in the medium surrounding the transmission line. Remark H.3 Assumption 2 means that the line has to be considered to infinite length. Clearly a finite length line does not satisfy this requirement. However, in most practical cases the end effects associated with finite length lines are small enough to justify their omission. Remark H.4 Assumption 3 states that the circuit approach to the analysis of the transmission lines can be carried out if the line is balanced. Imbalance an occur is a line due to things like unsymmetrical placement of the two lines with respect to other lines or the earth; unsymmetrical placement of a load on the line, or excitation on an unsymmetrical fashion. Now that we have outlined the assumptions we are now in a position to begin the modelling of the transmission line. The following parameters are shown in Figure H.1. Let use define: L inductance per unit length of line (H/m) C capacitance per unit length of line (F/m) R series resistance per unit length of line (Ω/m) G shunt conductance per unit length of line (mho/m) These parameters, for a particular configuration, can be deduced from field theory, or alternatively measured. For the moment we shall assume that we have these values by some means.
413
2a
b
2a x + Dx
x
A I (x + Dx , t )
I (x , t ) LDx
V (x , t )
RDx
C Dx
GDx
V (x + Dx , t )
Figure H.1: Two wire transmission line and a single element model.
414
Review of Transmission Lines
H.1
Basic Equations
Now let use consider the elemental section of transmission line shown in Figure H.1. At some particular time we have the following values: V (x, t); I(x, t) voltage and current at position x V (x + ∆x, t); I(x + ∆x, t) voltage and current at position x + ∆x Given the above definitions for the parameters of the system, then the parameters for a length of line ∆x is clearly ∆x times the value per unit length. To develop the circuit equations for the circuit element we resort to our old favourites – Kirchhoff’s voltage law and Kirchhoff’s current law. Applying Kirchhoff’s voltage law first we can write:
−V (x, t) + L∆x
∂ I(x, t) + R∆xI(x, t) + V (x + ∆x, t) = 0 ∂t
(H.4)
Dividing this expression by ∆x we can write: V (x + ∆x, t) − V (x, t) ∂ + L I(x, t) + RI(x, t) = 0 ∆x ∂t
(H.5)
Let us consider this expression as we take the limit as ∆x → 0. We can see that the first term of (H.5) is the definition of a derivative, hence we can write the equation as: ∂ ∂ V (x, t) = − L I(x, t) + RI(x, t) (H.6) ∂x ∂t Remark H.5 One can see that (H.6) simply says that the rate of change of voltage along a differential length of line is simply the inductive voltage drop on the line section plus the resistive voltage drop in the section. In a similar fashion to the voltage equation we can write a second equation using Kirchhoff’s current law applied to node A in Figure H.1: −I(x, t) + C∆x
∂ V (x + ∆x, t) + G∆xV (x + ∆x, t) + I(x + ∆x, t) = 0 (H.7) ∂t
As with the voltage equation we divide this equation by ∆x which allows one to write: I(x + ∆x, t) − I(x, t) ∂ + C V (x + ∆x, t) + GV (x + ∆x, t) = 0 ∆x ∂t which can be written as follows if ∆x → 0: ∂ ∂ I(x, t) = − C V (x, t) + GV (x, t) ∂x ∂t
(H.8)
(H.9)
Remark H.6 Equation (H.9) simply says that the change in the current across an element of the line is due to the shunt elements of the line bleeding off current.
H.2 Solution of Transmission Line Equations for the Lossless Case Since the transmission line is by assumption (definition) the same everywhere, then (H.6) and (H.9) are applicable at every point along the transmission line at any time t. Equations (H.6) and (H.9) constitute a pair of first order coupled partial differential equations. One can combine (H.6) and (H.9) into a single second order partial differential equation in voltage or current depending on the substitutions one carries out. For example, if one carries out a partial differentiation of (H.6) with respect to x then one can write: ∂ ∂2 ∂2 I(x, t) + R I(x, t) (H.10) V (x, t) = − L ∂x2 ∂x∂t ∂x Substituting for (∂/∂x)I(x, t) using (H.9) and manipulating gives: ∂2 ∂2 ∂ V (x, t) = LC 2 V (x, t) + (LG + CR) V (x, t) + RGV (x, t) 2 ∂x ∂t ∂t
(H.11)
Similarly, taking the partial derivative of (H.9) with respect to x gives: ∂ ∂2 ∂2 V (x, t) + G V (x, t) (H.12) I(x, t) = − C ∂x2 ∂t∂x ∂x Substituting for (∂/∂x)V (x, t) using (H.6) and manipulating the result gives: ∂2 ∂ ∂2 I(x, t) = LC 2 I(x, t) + (RC + GL) I(x, t) + GRI(x, t) 2 ∂x ∂t ∂t
(H.13)
Summary H.1 We can summarise the fundamental differential equations for a transmission line as: ∂ ∂ V (x, t) = − L I(x, t) + RI(x, t) (H.14) ∂x ∂t ∂ ∂ I(x, t) = − C V (x, t) + GV (x, t) (H.15) ∂x ∂t ∂2 ∂2 ∂ (H.16) V (x, t) = LC V (x, t) + (LG + CR) V (x, t) + RGV (x, t) 2 2 ∂x ∂t ∂t ∂2 ∂2 ∂ (H.17) I(x, t) = LC 2 I(x, t) + (RC + GL) I(x, t) + GRI(x, t) 2 ∂x ∂t ∂t Remark H.7 Because of the partial differential nature of (H.16) and (H.17) it is difficult to solve them in general. Note H.1 The voltage difference V (x, t) at some particular point on the line (i.e. a particular x) and at a particular time (i.e. a particular t) is the voltage difference between the two wires at that particular point. It is not the voltage difference to some single reference point.
H.2
Solution of Transmission Line Equations for the Lossless Case
Whilst the general solution of the transmission line equations are difficult, a specific solution can be more easily found for the case where the line is lossless
415
416
Review of Transmission Lines – i.e. R = G = 0. If we apply this condition to (H.14) and (H.15) we can write the following for the first order equations: ∂ ∂ V (x, t) = −L I(x, t) ∂x ∂t ∂ ∂ I(x, t) = −C V (x, t) ∂t ∂t
second order equations
(H.18) (H.19)
and similarly for the second order equations we can write: ∂2 V (x, t) = ∂x2 2 ∂ I(x, t) = ∂x2
1 ∂2 V (x, t) v 2 ∂t2 2 1 ∂ I(x, t) v 2 ∂t2
where: v=√
1 LC
(H.20) (H.21)
(H.22)
The symbol v is used in (H.22) because it turns out that this is the transmission velocity of waveforms down the transmission line. One can verify at this stage that it has the dimensions of velocity. In order to proceed any further with the solutions to the equations we introduce the following non-obvious change of variables: ξ = x − vt (H.23) η = x + vt Note H.2 The above change of variable implies that the original variables are related as follows to the new variables: x= t =
ξ+η 2 η−ξ 2v
(H.24)
Therefore the original V (x, t) and I(x, t) functions can be written as V (ξ, η) and I(ξ, η). Using the content of Note H.2 we can develop the following relationships for the differential of V in terms of the old and changed variables: dV =
∂V ∂V ∂V ∂V dx + dt = dξ + dη ∂x ∂t ∂ξ ∂η
dξ = dx − vdt;
dη = dx + vdt
(H.25) (H.26)
Substituting (H.26) into (H.25) and equating the dx and dt coefficients for the right and left sides gives one: ∂V ∂V ∂V = + ∂x ∂ξ ∂η 1 ∂V ∂V ∂V =− + v ∂t ∂ξ ∂η
or
or
∂ ∂ ∂ = + ∂x ∂ξ ∂η 1 ∂ ∂ =− + v ∂ξ ∂η
(H.27)
(H.28)
first order tions
equa-
H.2 Solution of Transmission Line Equations for the Lossless Case
417
These two expressions can be manipulated to give: ∂ 1 ∂ ∂ + =2 ; ∂x v ∂t ∂η
∂ 1 ∂ ∂ − =2 ∂x v ∂t ∂ξ
(H.29)
Considering (H.20) and (H.29) one can see the (H.20) can be written as: ∂ 1 ∂ ∂ 1 ∂ + − =0 (H.30) ∂x v ∂t ∂x v ∂t which using (H.29) can be written as: ∂2 V =0 ∂ξ∂η
(H.31)
Equation (H.31) is now a very simple equation to solve. One merely has to integrate the equation twice, once for the ξ variable and once for the η variable. These integrations can be written as follows: ∂ ∂V (H.32) dξ = f2 (η) + cv ∂ξ ∂η where the “” denotes the derivative with respect to the functions variable. Therefore after the first integration we are left with: ∂V = f2 (η) + cv ∂η
(H.33)
We now carry out the second integration with respect to η to find the solution to the voltage equation: ∂V dη = (f2 (η) + cv )dη V (x, t) = ∂η = f1 (ξ) + f2 (η) + cv = f1 (x − vt) + f2 (x + vt) + cv (H.34) Note H.3 The cv after integration is also a function of η. Therefore this is rolled into the function f2 (η) upon the η integration step. The cv constant in the final expression is simply a constant and is independent of either ξ or η. This has to be the case as it disappears after the two partial differentiations. Remark H.8 The integrations to end up with (H.34) can be carried out in any order – i.e. one could integrate with respect to η first followed by ξ and the result will be the same. One can easily prove that (H.34) is a solution to the original differential equation by carrying out the appropriate derivatives. This is most easily carried out by using the following general identity. Let γ(x1 , x2 ) be an arbitrary function of two variables, and f (γ) be an arbitrary function of γ, then by the chain rule of differentiation: ∂f ∂γ ∂ f (γ) = (H.35) ∂x1 ∂γ ∂x1
voltage equation
418
Review of Transmission Lines Applying this identity to the derivative of the left hand side of (H.20) we get: ∂2 ∂ V (x, t) = (f1 (ξ) + f2 (η)) 2 ∂x ∂x2 2 2 ∂ξ ∂η ∂2 ∂2 = 2 f1 + 2 f2 ∂ξ ∂x ∂η ∂x ∂2 ∂2 = 2 f1 + 2 f2 ∂ξ ∂η
(H.36)
Now applying the same identity to the right side of (H.20) we can write: ∂ ∂2 V (x, t) = 2 (f1 (ξ) + f2 (η)) ∂t2 ∂t 2 2 ∂ξ ∂η ∂2 ∂2 = 2 f1 + 2 f2 ∂ξ ∂t ∂η ∂t 2 2 ∂ ∂ = v2 f1 + 2 f2 ∂ξ 2 ∂η
current equation
(H.37)
If one compares (H.36) and (H.37) one can see that (H.20) holds as required for the solution. In a similar manner to the solution of the voltage equation one can also derive the solution for the current equation in the line: I(x, t) = g1 (x − vt) + g2 (x + vt) + ci
(H.38)
where g1 and g2 are arbitrary functions and ci is a constant independent of x and t. √ Remark H.9 The assertion was made earlier that v = 1/ LC was the velocity of a waveform down the transmission line. One can see from (H.34) and (H.38) that they contain two functions, one of x − vt and the other x + vt. In both equations the first function is moving to the right with a velocity of v and the second function is moving to the left with velocity v. If is assumed the both functions originate at x = 0 at t = 0. Remark H.10 One can see from (H.34) and (H.38) that the f and g functions (regardless of the direction of propagation) do not contain any attenuation term. Therefore the waveforms are propagated without any losses and will propagate forever down an infinite transmission line. This is a fact that follows from not including any losses in the line. Remark H.11 Another interesting point about the solutions is that they do not contain any frequency dependent terms. Therefore the transmission line has an infinite frequency response. One can propagate a signal of any frequency down the line without any losses. We note from (H.18) and (H.19) that there is a relationship between the voltage and the current at a particular point in the line. For example consider (H.19), rewritten here for convenience: ∂ ∂ I(x, t) = −C V (x, t) ∂t ∂t
(H.39)
H.2 Solution of Transmission Line Equations for the Lossless Case Evaluating the right hand side of this equation we get: −C
∂ ∂ V (x, t) = −C (f1 (x − vt) + f2 (xv t)) ∂t ∂t ∂f2 ∂f1 − Cv = Cv ∂ξ ∂η
Therefore we have:
∂ ∂f1 ∂f2 I(x, t) = Cv − Cv ∂t ∂ξ ∂η
(H.40)
(H.41)
We can now integrate this expression with respect to x to get an expression for I(x, t): ∂f1 ∂f2 I(x, t) = Cv − Cv dx (H.42) ∂ξ ∂η Using (H.35) on (H.34) one can see that: ∂ ∂ V (x, t) = (f1 (x − vt) + f2 (x + vt) + cv ) ∂x ∂x ∂(x − vt) ∂f2 ∂(x + vt) ∂f1 + = ∂(x − vt) ∂x ∂(x + vt) ∂x ∂f2 ∂f1 + = ∂ξ ∂η
(H.43)
Comparing the derivative in (H.43) with (H.42) one can see that:
and:
therefore:
∂f1 (ξ) ∂f1 = ∂x ∂ξ
(H.44)
∂f2 (η) ∂f2 = ∂x ∂η
(H.45)
∂f1 dx = f1 (ξ) + m(t) ∂ξ ∂f2 dx = f2 (η) + n(t) ∂η
and
(H.46) (H.47)
This means that I(x, t) can be written as: I(x, t) = Cvf1 (x − vt) − Cvf2 (x + vt) + f3 (t)
(H.48)
where f3 (t) is a function from the integration process. We can now differentiate (H.48) to get an expression that can be used with (H.18) as follows: −L
d ∂f1 ∂f2 ∂ I(x, t) = LCv 2 + LCv 2 − L f3 (t) ∂t ∂ξ ∂η dt ∂f2 d ∂f1 + − L f3 (t) = ∂ξ ∂η dt
(H.49)
419
420
Review of Transmission Lines since LC = 1/v 2 . This expression should be the same as (H.43) because of (H.18), therefore the function of integration f3 (t) must be zero or a constant since it disappears when a derivative is taken with respect to x. We shall denote this constant as ci and hence we can write the expression for the current in terms of the voltage functions as follows: I(x, t) = Cvf1 (x − vt) − Cvf2 (xv t) + ci
(H.50)
Remark H.12 A comparison of (H.50) with (H.38) leads one to the following equalities: g1 (x − vt) = Cvf1 (x − vt) g2 (x + vt) = −Cvf2 (x + vt) characteristic impedance
(H.51) (H.52)
Remark H.13 The previous remark leads us to the following conclusion – the term Cv is equal to 1/R0 , where R0 the characteristic impedance of the transmission line. This can be deduced from the fact that the current is related to the voltage functions via a real constant Cv. Therefore this constant must have the dimensions of resistance (which can be verified via a formal dimension analysis). If one expands this definition of characteristic impedance using the definition of v, then the expression for it is: L (H.53) R0 = C Using (H.53) one can write the expression for I(x, t) as: I(x, t) =
1 1 f1 (x − vt) − f2 (x + vt) + ci R0 R0
(H.54)
Remark H.14 The constants cv and ci that appear in the (H.34) and (H.38) do not have any relationship between them defined by the original differential equations of the system. There values are completely specified by the boundary conditions of the transmission line – i.e. by the source impedance and the load impedance. They are DC values for the voltage (cv ) and current (ci ) flowing in the transmission line under DC conditions. It is easily shown that the value of cv can be determined independently of the value of ci .
H.2.1
Semi-infinite Transmission Line
Thus far we have considered the transmission line to extend for an infinite distance in either direction from some initial starting point denoted as x = 0. However, most real transmission lines start at a source and go in a single direction from there. Under these conditions we cannot have a voltage or current waveform travelling in the negative direction,1 therefore the voltage and current waveforms are (assuming no DC component): V (x, t) = f1 (x − vt)
(H.55)
f1 (x − vt) R0
(H.56)
I(x, t) =
1 Because the line in infinite in the positive direction then no negative wave can be generated.
H.2 Solution of Transmission Line Equations for the Lossless Case Example H.1 Consider the situation shown in Figure H.2. We have a voltage source that puts a pulse onto the line at time t = 0. The voltage source has an internal impedance of Rg Ω. We shall work out the values of the functions for the voltages and currents down the line. The generator function can be written as: 0 ∀t < 0 (H.57) Vg (t) = 1 ∀t ≥ 0 Therefore: Vg (t)R0 = f1 (−vt) Rg + R0 f1 (−vt) Vg (t) = I(0, t) = Rg + R0 R0
V (0, t) =
(H.58) (H.59)
One can manipulate these expressions so that the f1 expressions can be more readily interpreted with respect to the generator function voltage. For example, after 10 seconds say, the waveform will have travelled 10v in the positive x direction. Therefore, position 10v on the x axis corresponds to t = 0 in the time axis of the voltage generator. Similarly the position 9v corresponds to the t = 1 position in the time axis of the voltage generator. Therefore one can see that the time axis effectively runs in the negative x direction on the transmission line voltage versus distance/current plot. Therefore the x axis waveform can be correlated to the time axis input waveform by realising that: t=
x v
(H.60)
is the time required for a waveform to travel the distance x. Therefore Vg (t−x/v) is equivalent to f1 (x − vt) for all t and x. Using this knowledge and the above equations one can write: x R0 Vg t − Rg + R0 v x f1 (x − vt) 1 I(x, t) = = Vg t − R0 Rg + R0 v
V (x, t) = f1 (x − vt) =
(H.61) (H.62)
Figure H.3 shows the plots for the time domain and distance domain at some time t1 . Notice that the plots effectively run in opposite directions to each other – i.e. the time domain plot evolves to the right in the figure, which corresponds to moving to the left in the distance plot. The crossed arrows shown corresponding points on the two plots. Also note the f1 (x − vt) has its own origin at the point of the dotted line and this origin moves with the waveform when plotted on the x axis.
H.2.2
Finite Transmission Line and Reflection Coefficient
Consider a finite transmission line starting at x = 0 and extending to x = l. At the point x = 0 there is a source generating a voltage and current into the line, and at l there is a load resistor RL .
421
422
Review of Transmission Lines
Rg
Vg
Transmission line R0
To ¥
Figure H.2: Semi-infinite transmission line with source
Vg (t )
Time domain plot
0
t
t1 f1(0)
f1(x - vt )
Distance domain plot
-vt1
vt1
x
Figure H.3: Plot of pulse in the time and distance domains
H.2 Solution of Transmission Line Equations for the Lossless Case
423
We have noted that at every cut plane in the line the voltage and the current are related as: V (x, t) = R0 (H.63) I(x, t) The obvious question then arises – what happens at the RL termination? The key to answering this question is to realise that Kirchhoff’s circuit equations, which hold all the way along the transmission line also have to hold at the RL termination. Before discussing the conditions at the termination in detail, let us introduce a little extra notation. We shall denote V+ and I+ to be the voltage and current waveforms that move in the positive x direction as they reach the termination. Similarly, we denote V− and I− as the voltage and current waveforms travelling in the −x direction at the termination. As the voltage and current waveforms approach the termination then in general: VL V+ = R0 = = RL (H.64) I+ IL This inequality implies that Kirchhoff’s circuit equations don’t hold. To see this, assume that the voltage VL = V+ . This would mean that IL = V+ /RL = V+ /R0 . Therefore, the current at the node required for the resistor does not equal the current flowing at that point in the transmission line. Kirchhoff’s current law is not obeyed. Even though this is a slightly artificial example, it nevertheless shows the basic problem. Of course Kirchhoff’s laws must be satisfied at the load resistor. In order for them the hold the V + waveform is considered to reflect from the termination and generate a waveform that moves in the −x direction. Similarly for the current waveform. Therefore: V+ + V− = VL I+ + I− = IL
(H.65) or
V+ V− VL − = R0 R0 RL
(H.66)
One can see from these equations that the voltage and current equations now make sense. Let us define the reflection coefficient as: ρ=
V− I− =− V+ I+
(H.67)
Substituting (H.65) and (H.66) into (H.67) one can write: V− V+ + V− V+ − = R0 R0 RL 1 1 1 1 ∴ V+ − + = V− R0 RL R0 RL RL − R0 V− ⇒ρ= = V+ RL + R0
(H.68)
Remark H.15 If RL = R0 then ρ = 0 which means that there is no reflection. If RL = 0 then ρ = −1 which means that the whole of the incident voltage waveform is reflected. Therefore V+ + V− = V+ + ρV+ = 0V .
reflection cient
coeffi-
424
Review of Transmission Lines Remark H.16 If RL > R0 then 0 < ρ ≤ 1, which implies that the incident and reflected voltage waveforms have the same polarity. Therefore at the load termination these voltages add together to produce a higher voltage than the incident voltage on its own. If RL = ∞ then ρ = 1 Remark H.17 As defined in (H.67) the reflection coefficient is a real value. In the case of reactive terminations the situation is much more complex.
H.3
Reflection Diagrams
Let us consider the situation shown in Figure H.4. We are interested in how the DC conditions are established in the transmission line after the switch is closed at t = 0. This situation is of particular interest when one is dealing with digital pulses, since this situation obviously mirrors the switching of a digital signal on a transmission line. Switch closed at time t=0
Rg R0 , v
V0
RL
x =0
Rg
x =l
I +1
R0
V0
V+1
Figure H.4: DC voltage transient on a transmission line When the switch is closed, after a very long time – in fact an infinite time if the line is considered to be lossless, the current and the voltage will settle to DC values. These values are given by: RL V0 R0 + RL V0 If = R0 + RL
Vf =
(H.69) (H.70)
We shall assume that at t < 0 the current and voltage in the line is zero. As soon as the switch is closed a step waveform will begin to travel done the transmission line (similar to the diagram in Figure H.3). We shall denote V+1
H.3 Reflection Diagrams
425
and I+1 as the forward travelling waveforms, therefore V+1 = R0 I+1 . From the equivalent circuit at the input one can deduce that: R0 V0 Rg + R0 V0 = Rg + R0
V+1 =
(H.71)
I+1
(H.72)
Considering the voltage waveform, it travels down the transmission line at the velocity v, reaching the termination at T = l/v. At this point one may or may not get a reflection, depending on the reflection coefficient, ρL . We shall assume the ρL = 0, therefore there is a reflection. The reflected voltage at the load resistance is: (H.73) V−1 = ρL V+1 which travels in the negative x direction with the same velocity v. Therefore for any time from T < t < 2T there is a voltage discontinuity travelling toward the generator – everywhere from the generator to the discontinuity the voltage is V+ 1 and from the discontinuity to the load the voltage is V+1 + V−1 . At time t = 2T the discontinuity will reach the generator. The generator is assumed to be an ideal voltage source, with its internal impedance being modelled by the generator resistance Rg . Because a transmission line is a linear circuit we can apply the principle of superposition to work out what happens when the reflected voltage meets the generator. We know if the reflected wave is not there (i.e. V−1 = 0) the voltage on the transmission line at the generator is V+1 travelling in the positive direction (as was present at t = 0). If the voltage source is not there (i.e. V0 = 0) then the reflected wave V−1 sees a resistance of Rg . If Rg = R0 then again we will have a reflected waveform with a reflection coefficient of: Rg − R0 (H.74) ρg = Rg + R0 The new reflected wave will move in the positive direction and its value is: V+2 = ρg V−1
(H.75)
We can now apply the superposition. The effective waveform that now propagates in the positive direction down the transmission line is: V+1 + V−1 + V+2 = (1 + ρL + ρg ρL )V+1
(H.76)
Therefore from the generator to the discontinuity we have the voltage of (H.76), and from the discontinuity to the load termination we have the (1 + ρL )V+1 . At time t = 3T the forward travelling waveform reaches the load termination again, and we again have a reflection based in the ρL reflection coefficient. Therefore the reflected waveform is: V−2 = ρL V+2
(H.77)
and therefore from the load termination to the discontinuity we have a voltage of: V+1 + V−1 + V+2 + V−2 = (1 + ρL + ρg ρL + ρg ρ2L )V+1
(H.78)
426
Review of Transmission Lines and from the discontinuity to the generator we have: (1 + ρL + ρg ρL )V+1
reflection diagram
(H.79)
The whole process then repeats again at the generator, and so on forever in the case of the lossless line. A good way of visualising reflections and the consequent building of the voltage waveforms is via a reflection diagram, as shown in Figure H.5. The horizontal axis is the distance along the transmission line, and the vertical axis is the time. The thick lines represent the waveforms travelling down the line, with the arrows indicating the direction of the wave. The annotation on each of the directed arcs denotes the magnitude of the reflected waveform. The reflection diagram can be used to obtain either: • The voltage distribution along the line at a particular time, or • The time dependence of the voltage at a particular point on the transmission line. t 6T
V+1r 3
Lr 2g
5T
2
t0 4T
2g
V +1r Lr
T5
V+1 2
r Lrg
T4 T3
3T
V +1rLrg 2T
V+1r
L
T2 T1
T
V +1 0
x =0 rg
l0
l1 x = l rL
Voltage
Figure H.5: Voltage reflection diagram
Example H.2 Suppose that one wishes to know the voltage distribution along the line at time t0 shown on Figure H.5. Following the dashed line in this figure one can see that at this time the voltage discontinuity is at position at l0 . To find the total voltage at this time we add up the incremental voltages for all the reflected waveforms on the line to the desired time. In the case of this specific example that voltage is: V (x, t0 ) = V+1 (1 + ρL + ρL ρg + ρ2L ρg + ρ2L ρ2g )
for 0 ≤ x ≤ l0
(H.80)
H.4 Time Harmonic Solutions for Lossy Lines
427
and because the waveform has not reached the section from l0 < x ≤ l then: V (x, t0 ) = V+1 (1 + ρL + ρL ρg + ρ2L ρg )
for l0 < x ≤ l
(H.81)
Suppose, on the other hand, we want to obtain the time dependence of the voltage at a specific point on the transmission line. Consider the dotted line in Figure H.5. As one proceeds vertically upwards along this dotted line it crosses the oblique wave propagation lines. Therefore at time T1 the voltage on the line at position l1 is V+1 , at T2 the voltage is V+1 (1 + ρL ), at T3 the voltage is V+1 (1 + ρL + ρL ρg ) and so on. Therefore one is able to plot the voltage on the transmission line at a particular point against time.
H.4
Time Harmonic Solutions for Lossy Lines
Up to this point we have been considering arbitrary functions propagating down lossless lines. However, it is beneficial to consider the propagation of time harmonic waveforms (such as sine and co-sinusoidal waveforms) down transmission lines. For example, it is possible to evaluate the impedance of the line, and to generate frequency response characteristics for lossless lines with these forms of waves. Let us represent the voltage distribution along a line as: V (x, t) = V (x) cos(ωt + θV ) − → → − = { V (x)ejωt } where V (x) = V (x)ejθV
(H.82) (H.83)
where θV is in general a function of x, the distance down the transmission line, and ω = 2πf = 2π/T where T the period of the waveform. This means that at a particular positions down the line the waveform is varying in magnitude as a co-sinusoidal wave. Note that V (x) is a function of x, the detail of which depends on the line parameters. Similarly: → − → − (H.84) I(x, t) = { I (x)ejωt } where I (x) = I(x)ejθI → − → − Remark H.18 One can see that V (x) and I (x) are phasors in the traditional circuit sense. The and the ejωt are implied in phasors. Now let use consider the general differential equations that govern the system, repeated here for convenience: ∂ ∂ V (x, t) = − L I(x, t) + RI(x, t) (H.85) ∂x ∂t ∂ ∂ I(x, t) = − C V (x, t) + GV (x, t) (H.86) ∂x ∂t Substituting (H.83) and (H.84) into these expressions we can write: − → − → ∂ ∂ V (x, t) = −L {jω I (x)ejωt } − R { I (x)ejωt } ∂x ∂t − → → − = −L{jω I (x)ejωt } − R { I (x)ejωt } → − → − = −jωL I (x) − R I (x) (making the implicit) → − = −(R + jωL) I (x)
(H.87)
428
Review of Transmission Lines Similarly we can write the following expression for the current equation: → → − ∂ − I (x) = −(G + jωC) V (x) ∂x
(H.88)
These expressions can be written as: → → − ∂ − V (x) = −z I (x) ∂x → → − ∂ − I (x) = −y V (x) ∂x
(H.89) (H.90)
where: z = R + jωL (the series impedance) y = G + jωC (the shunt admittance) The second order equations are: ∂2 ∂ ∂2 I(x, t) + R I(x, t) V (x, t) = − L ∂x2 ∂x∂t ∂x 2 2 ∂ ∂ ∂ V (x, t) + G V (x, t) I(x, t) = − C ∂x2 ∂x∂t ∂x
(H.91) (H.92)
(H.93) (H.94)
Let’s consider the first of these expressions. We can immediately say from (H.90) that: → − ∂ R I(x, t) = −Ry V (x) (H.95) ∂x Now consider the first partial derivative in the first equation: → − → − → ∂2 − ∂ I (x) = (−y V (x)) = −jωy V (x) ∂x∂t ∂t
(H.96)
remembering to put in the ejωt term into the phasor before doing the derivative. Similarly, we can write: → → − ∂2 − V (x) = −jωz I (x) ∂x∂t
(H.97)
Returning to (H.93) and substituting in the above two expressions we can write: → → − → − ∂2 − V (x) = − −jωLy V (x) − Ry V (x) 2 ∂x → − = (R + jωL)y V (x) → − = zy V (x) (H.98) Similarly, for (H.94) we can write: → → − → − ∂2 − I (x) = − −jωCz I (x) − Gz I (x) ∂x2 → − = (G + jω)z I (x) → − = zy I (x)
(H.99)
H.4 Time Harmonic Solutions for Lossy Lines
429
The parameter γ 2 = zy where zy = (R + jωL)(G + jωC). Summary H.2 In summary, the first and second order equations for the time harmonic waveform case are: → → − ∂ − V (x) = −z I (x) ∂x → → − ∂ − I (x) = −y V (x) ∂x → → − ∂2 − V (x) = γ 2 V (x) 2 ∂x → → − ∂2 − I (x) = γ 2 I (x) ∂x2
(H.100) (H.101) (H.102) (H.103)
where: z = R + jωL y = G + jωC √ γ = (R + jωL)(G + jωC) = zy
(H.104)
Remark H.19 Equations (H.102) and (H.103) are simple second order homogeneous differential equations. Much of the complexity has effectively been eliminated by the use of the phasor description for the signals.
H.4.1
Solutions for Voltage and Currents
The solutions to (H.102) and (H.103) can be seen from inspection to be of the general form: → − → − → − (H.105) V (x) = V 1 e−γx + V 2 eγx → γx → − → −γx − − + I 2e (H.106) I (x) = I 1 e → − − → − → → − where V 1 , V 2 , I 1 , and I 2 are constants that depend on the terminal conditions. Note that the first part of the right hand side of these two equations correspond, and similarly for the second components of both equations. Each of the components in each equation are independently solutions to the original differential equations. → → − − Remark H.20 Note that V 1 , I 1 etc. are phasors. This can easily be seen by considering the case of x = 0 in (H.105): → − → − → − (H.107) V (x) = V 1 + V 2 Both sides of the equation have to be phasors. Now let us consider the first expressions on the right hand side of (H.105) and (H.106), and substitute them into (H.100): → − → ∂ − V (x) = −γ V 1 e−γx ∂x → − → − −z I (x) = −z I 1 e−γx − → → − ∴ −γ V 1 e−γx = −z I 1 e−γx
(H.108)
430
Review of Transmission Lines Rearranging we can write: − → R + jωL V1 z → = y = G + jωC = Z0 − I1
(H.109)
Similarly for the second components of these equations we can write the following: → − V2 (H.110) → = −Z0 − I2 where the negative sign results from the current and voltage conventions. Remark H.21 The two components in (H.105) and (H.106) correspond to the forward moving (i.e. positive x direction) and backward moving waves on the line. We had a similar situation when we considered the solution to the transmission line equations for arbitrary waveforms. The relationships (H.109) and (H.110) allow us the write (H.106) in terms of voltages and the characteristic impedance: → − − → − → V 1 −γx V 2 γx I (x) = e − e Z0 Z0
H.4.2
(H.111)
Semi-infinite Transmission Line
Thus-far we have been considering the solution of the time harmonic equations for the infinite transmission line (i.e. infinite in both directions from the signal injection point). We shall now consider the solution of the equations for a line that starts at x = 0 and extends infinitely in the positive x direction. As we shall see this simplifies the general solutions (H.105) and (H.106). Firstly let us consider the constant γ. This is defined as (repeated here for convenience): γ = (R + jωL)(G + jωC) = (RG − ω 2 LC) + jω(CR + LG) = a + jb (H.112) Because γ is complex then we can define: γ 2 = (α + jβ)2 = a + jb
(H.113)
Expanding the α, β expression and equating real and imaginary parts we can write: (α2 − β 2 ) = (RG − ω 2 LC) 2αβ = ω(CR + LG)
(H.114) (H.115)
One can solve these expressions simultaneously to get rather complicated and messy expressions for α and β. From these expressions it is possible to deduce that α ≥ 0 and β ≥ 0 for all physically realisable transmission line component values. For the following sections we only need to consider that: γ = α + jβ
(H.116)
H.4 Time Harmonic Solutions for Lossy Lines
431
Let us consider the implications of a line extending from x = 0 to x = −∞ on (H.105): → − → − → − (H.117) V (∞) = V 1 eγ∞ + V 2 e−γ∞ → − Clearly for this equation to have physical meaning then V 1 = 0. This term of the equation relates to the section of the line that goes in the positive x direction in the infinite transmission line situation. Similarly, for a line extending from x = 0 to x = ∞ we have: − → → − → − V (∞) = V 1 e−γ∞ + V 2 eγ∞
(H.118)
→ − and therefore V 2 = 0 for a physically meaningful solution. Let us from this point only consider the situation of the line from x = 0 to x = ∞. The voltage equation for this line can be written as: − → → − → − V (x) = V 1 e−γx = V 1 e−(α+jβ)x
(H.119)
− → Because V (x) is a phasor we can reintroduce the ejωt term and take the real part of the resultant expression (this returns the equation to a time domain expression): − → → − V (x) = V 1 e−γx → − = V 1 e−αx e−jβx = V1 ejθV1 e−αx e−jβx
(H.120)
→ − where θV1 is an arbitrary phase shift in the V 1 phasor. It is not the phase shift θV introduced in (H.83), which is used to represent the total phase shift in the voltage expression. Considering the original definition in (H.83) we can now write: − → V (x) = V (x)ejθV = V1 e−αx ej(θV1 −βx)
(H.121)
and therefore we can see by inspection that: V (x) = V1 e−αx voltage amplitude θV = (θV1 − βx) voltage phase
(H.122) (H.123)
Remark H.22 Equation (H.122) shows that the voltage is attenuated as it travels down a lossy transmission line. Equation (H.123) shows that the phase is proportional to the distance down the line. This means that there is a modulated co-sinusoidal variation of the amplitude down the line. It also means that in the time domain that the waveform at some point x has a phase displacement of βx compared to the time waveform at location x = 0. If we now reintroduce the ejωt and take the Real part so we get: V (x, t) = {V1 e−αx ej(θV1 −βx) } ∴ V (x, t) = (V1 eαx ) cos(ωt + θV1 − βx)
(H.124)
432
Review of Transmission Lines Remark H.23 Equation (H.124) shows that γ = α + jβ defines completely the propagation of sinusoidal time harmonic waveforms down the line. For this reason γ is called the propagation constant. Remark H.24 We know that the co-sinusoidal input waveform is propagating down the transmission line with a velocity v. From a time domain point of view we know that the waveform will have the same value when: cos(ωt + θV1 ) = cos(ωt + θV1 + n2π) ⇒ ωt = ωt + n2π n2π ; n = 0, 1, 2, 3 · · · ∴t=t+ ω
(H.125) (H.126) (H.127)
i.e. the time changes by 2π/ω for the same value of different points down the transmission line. Therefore this time will clearly relate to the wavelength of the waveform on the line.
wavelength
Remark H.25 In time 2π/ω the waveform will have moved 2πv/ω down the transmission line. Therefore this distance must define the wavelength of the wave on the transmission line. An alternative expression can be derived by realising that at some particular time t that there will be multiple points down the transmission line with the same value. These points are clearly defined by the condition that: cos(ωt + θV1 − βx) = cos(ωt + θV1 − βx + n2π)
(H.128)
where λ denotes the wavelength of the waveform on the line. For this condition to hold we can see that equating the right and left sides: βx = βx + n2π n2π ∴x=x+ β
(H.129)
where x is some arbitrary position down the transmission line, and n = 1, 2, 3, · · · . Equation (H.129) says that at positions n2π/β apart down the line the values of the waveform will be the same, therefore this is another expression for the wavelength of the signal on the line: λ=
2π β
(H.130)
We can equate this expression for the wavelength with that mentioned earlier in this remark to give: 2π 2πv = β ω ω ∴v= β phase velocity
The velocity v is also known as the phase velocity.
(H.131)
propagation stant
con-
H.4 Time Harmonic Solutions for Lossy Lines
H.4.3
433
Finite Length Transmission Lines
In this section we now consider a transmission line that is a finite length – i.e. it is a terminated line. As mentioned when we were considering the general solutions for the time harmonic equations, the coefficients in (H.105) and (H.106) are determined by the boundary conditions of the line. In the case of the semiinfinite line one has boundary conditions at the start of the line. In the case of a finite length line there are boundary conditions at the start of the line as well as at the end of the line. → − → − If we consider V 0 and I 0 to be the specified input voltage and current then we can determine the constants as follows: → − − → → − V (0) = V 1 + V 2 = V0 → − → − − → V2 V1 − = I0 I (0) = Z0 Z0
(H.132) (H.133)
Solving simultaneously we can write: − → 1 V 1 = (V0 + I0 Z0 ) 2 → − 1 V 2 = (V0 − I0 Z0 ) 2 → − 1 1 ∴ V (x) = (V0 + I0 Z0 )e−γx + (V0 − I0 Z0 )eγx 2 2
(H.134) (H.135) (H.136)
Similarly: − → 1 1 (V0 + I0 Z0 )e−γx − (V0 − I0 Z0 )eγx I (x) = 2Z0 2Z0
(H.137)
Equations (H.136) and (H.137) can be written more succinctly using the relations: ey + e−y 2 ey − e−y sinh y = 2
cosh y =
(H.138) (H.139)
Therefore the equations for the waveform distribution down the transmission line with source boundary conditions become: − → V (x) = V0 cosh(γx) − I0 Z0 sinh(γx) → − V0 sinh(γx) + I0 cosh(γx) I (x) = − Z0
(H.140) (H.141)
An alternative formulation is to specify the boundary conditions at the load end of the finite length line. Consider the transmission line to have a total length of l, i.e. starting at x = 0 and ending at x = l. At x = l let the voltage → − → − be V L and the current be I L . Substituting these boundary condition into
434
Review of Transmission Lines (H.105) and (H.111) one can write: → → −γl − − + V 2 eγl = VL V 1e → − → − V 1 −γl V 2 γl e − e = IL Z0 Z0
(H.142) (H.143)
Solving these simultaneously we can write the coefficients as: → → − − → 1 − (H.144) V 1 = ( V L + I L Z0 )eγl 2 → → − → − 1 − (H.145) V 2 = ( V L − I L Z0 )e−γl 2 → − → − We also know that V L = I L ZL , where ZL the terminating impedance. Therefore we can write the coefficients as: → − → − IL (ZL + Z0 )eγl (H.146) V1= 2 → − → − IL (ZL − Z0 )e−γl (H.147) V2= 2 which allow us to write the general voltage and current equations in a form that contain the terminating impedance of the line: → − → − IL V (x) = (H.148) (ZL + Z0 )eγ(l−x) + (ZL − Z0 )e−γ(l−x) 2 → − → − IL (ZL + Z0 )eγ(l−x) − (ZL − Z0 )e−γ(l−x) (H.149) I (x) = 2Z0 Realising that (l−x) is the distance from the termination to the point of interest on the line, and again using the cosh and sinh relationships we can write: − → → − V (x) = I L [ZL cosh(γs) + Z0 sinh(γs)] → − → − IL I (x) = [Z0 cosh(γs) + ZL sinh(γs)] Z0 where s = (l − x)
(H.150) (H.151)
and l the total length of the line
H.4.4
Line Input Impedance
Consider the line in the previous section of length l and terminated with a load impedance of ZL . The circuit under consideration is shown in Figure H.6. Notice that we are assuming in this figure that the transmission line can be represented as an equivalent input impedance. From figure H.6 we can see that: → − → − Vs (H.152) I0= Zs + Zin → − → − V s Zin (H.153) V0= Zs + Zin
H.4 Time Harmonic Solutions for Lossy Lines
Zs
435
r I0
r IL
+
r V0
r Vs
ZL
-
x =l
x =0 Z in
Zs +
r Vs
r I0 Z in
r V0
-
Figure H.6: Terminated transmission line and the equivalent circuit → − → − Therefore if we know Zin then we can work out the V 0 and I 0 coefficients and substitute them into (H.140) and (H.141) to get the complete solution for the line. The general expression for the impedance for the line at any position x can be found from the ratio of (H.150) and (H.151) to give:2 − → − → I L [ZL cosh(γs) + Z0 sinh(γs)] V (x) = → Z(x) = − − → IL I (x) Z0 [ZL sinh(γs) + Z0 cosh(γs)] ZL cosh(γs) + Z0 sinh(γs) = Z0 ZL sinh(γs) + Z0 cosh(γs) ZL + Z0 tanh(γs) = Z0 Z0 + ZL tanh(γs) sinh(γs) where tanh(γs) = cosh(γs)
(H.154) (H.155)
The input impedance for a general terminated line can be written from (H.154) by realising that for the input impedance s = l (i.e. x = 0). Therefore the expression is: ZL cosh(γl) + Z0 sinh(γl) Zin = Z(0) = Z0 (H.156) ZL sinh(γl) + Z0 cosh(γl) 2 Remember
that s = l − x.
436
Review of Transmission Lines H.4.4.1
Lossless Line Input Impedance
Let us now consider the simplified situation of the lossless transmission line. Under this condition we have: R=0 G=0 therefore we can write γ as follows: γ = (jωL)(jωC) = −ω 2 LC √ ∴ γ = jβ (and β = ω LC)
(H.157)
(H.158)
In one uses this new definition of γ into the expressions for cosh(γl) and sinh(γl) we can write the following: cosh(γl) = cos(βl)
and
sinh(γl) = j sin(βl)
(H.159)
Making these substitutions into (H.156) we can get the input impedance for a lossless line:3 ZL cos(βl) + jZ0 sin(βl) Zin = Z0 (H.160) jZL sin(βl) + Z0 cos(βl)
H.4.5
Transfer Function of a Lossless Transmission Line
Consider (H.140) with x = l. This gives us an expression for the load voltage → − in terms of the line input voltage V 0 : → − − → Z0 sin(βl)] V L = V 0 [cos(βl) − j Zin
(H.161)
→ − → − since I 0 = V 0 /Zin , and Zin is defined in (H.160). From the equivalent circuit in (H.6) one can see that: → − − → Zin V s V0= Zin + Zs and hence the basic transfer function can be written as: → − Zin Z0 VL = sin(βl) cos(βl) − j → − Zs + Zin Zin V0
(H.162)
(H.163)
This basic equation can be further manipulated by including the definition for Zin . Considering the first term on the right hand side of (H.163) we can write: Zin Z0 [ZL cos(βl) + jZ0 sin(βl)] = Zs + Zin [(Zs Z0 + Z0 ZL ) cos(βl) + j(Z02 + Zs ZL ) sin(βl)]
(H.164)
Now considering the second term in (H.163) we can write: cos(βl) − j 3 Note
that Z0 =
L C
Z0 ZL sin(βl) = Zin ZL cos(βl) + jZ0 sin(βl) for a lossless line.
(H.165)
H.4 Time Harmonic Solutions for Lossy Lines
437
Combining these two terms we can write the transfer function as: − → Z0 ZL VL → = (Z Z + Z Z ) cos(βl) + j(Z 2 + Z Z ) sin(βl) − s 0 0 L s L Vs 0
(H.166)
Equation (H.166) can be used as a starting point for carrying out a frequency domain analysis of a transmission line with a particular loading on it.
H.4.6
Thevenin Equivalent Circuit
One can use all the information we currently have to develop a Thevenin equivalent circuit of the transmission line. Figure H.7 shows the structure of the Thevenin equivalent circuit.
Z eq
r IL
+ r Vse
ZL
r VL
-
Figure H.7: Thevenin equivalent circuit of a transmission line Let us begin with the equivalent impedance of the line looking from the load end towards the source. In order to find this the normal technique is to short circuit the source voltage and then work out the impedance looking from the load. In this particular case we can use the results we have in (H.160) to do this because of the symmetry on the system. We simply need to replace ZL with Zs in the input impedance expression which gives: Zs cos(βl) + jZ0 sin(βl) Zeq = Z0 (H.167) Z0 cos(βl) + jZs sin(βl) To find the equivalent source voltage one has to work out the current flowing at the load point if the load is replaced with a short circuit. We can use (H.163) to express the load voltage for a general load ZL in the following expression for
438
Review of Transmission Lines the load current: − → − → VL = IL= ZL
→ − Z0 ZL V s 2 (Zs Z0 +Z0 ZL ) cos(βl)+j(Z0 +Zs ZL ) sin(βl) ZL
→ − Z0 V s = (Zs Z0 + Z0 ZL ) cos(βl) + j(Z02 + Zs ZL ) sin(βl)
(H.168)
If ZL = 0 then this expression can be simplified to:4 − → IL=
− → Vs Zs cos(βl) + jZ0 sin(βl)
(H.169)
If one considers the equivalent circuit of Figure H.7 then the load current is: → − − → V se IL= Zeq
→ − [Z0 cos(βl) + jZs sin(βl)] V se = Z0 [Zs cos(βl) + jZ0 sin(βl)]
(H.170)
The currents in the actual line and the equivalent circuit under the condition of a short circuited load have to be the same, therefore equating (H.169) and (H.170) and then simplifying we can write: − → V se =
4 Note
→ − Z0 V s Z0 cos(βl) + jZs sin(βl)
→ − that with ZL = 0 then implicitly V L = 0.
(H.171)
Appendix I
Useful Formulae I.1
Introduction
This appendix contains a number of formulae that are useful in the area of transmission lines, especially when they occur in digital transmission systems. Most of the expressions here can be found scattered throughout the literature, but one reference that collects them together in one place is [1]. The expressions in this reference are almost all in imperial units. We shall use MKS units in this appendix where appropriate. In some cases imperial units will still be used because these are the units that are used extensively in the literature.1
I.2
Useful Constants
Table I.1 shows some constant that are useful when carrying out calculations involving electric and magnetic fields.
I.3 I.3.1
Formulae AWG Related Conversions
Equations (I.1) and (I.2) allows the American Wire Gauge to be converted to a wire diameter in metres and vice-versa. d ) 0.0254 AWG+10 d = 2.54 × 10−[ 20 −2] m
AWG = −10 − 20 log(
(I.1) (I.2)
Equation (I.3) allows one to obtain the resistance of a round wire given its diameter (or AWG) and length in metres: R=
4ρl (1 + (T − 20)δρ) πd2
(I.3)
1 For example, imperial units are used almost exclusively in PCB measurements, because much of the sofrtware used in this industry has been written in the USA, or its target market is in the USA.
440
Useful Formulae
Constant
Value
Permittivity of free space (0 ) Permeability of free space (µ0 ) Speed of light (c) Bulk resistivity of copper (ρ) ab Bulk resistivity of copper (ρ) c Temperature coefficient of copper resistivity (δρ)
8.854 × 10−12 Farad/m 4π × 10−7 Henry/m 2.998 × 108 metres/sec 1.724 × 10−8 Ω − m 1.671 × 10−8 Ω − m 3.9 × 10−3 /C◦
d
a This value takes into account the changes in the resistivity due to the annealing process and the chemical imperfections caused by the manufacturing process for wires. b The resistivity can be thought of as the resistance of the 1m3 block of material. c This ¡ is the conventional value for the resistivity of copper at 20◦ . d This quantity of defined as 1 dρ . ρ dt
Table I.1: Useful constants where T the temperature in ◦ C, l the length of the wire in metres, d the diameter of the wire in metres, ρ the resistivity in Ω-m, and δρ the resistivity temperature coefficient.
I.3.2
Copper Plate Weight Formulae
Printed circuit boards (PCBs) usually specify the thickness in terms of the copper plate weight (CPW) value. This is the weight of 1in2 of the copper plating on the board in the imperial unit of ounces. The expression to convert the CPW value into a plate thickness in inches is: t = 0.00137 × CPW (inches)
(I.4)
Clearly to convert this to a metric unit we need to multiply by the appropriate conversion factor. Since there are 25.4mm/in then the thickness in mm is tm = 25.4t = 0.034798 × CPW, and in metres tm = 0.0254t = 0.000034798 × CPW, where tm denotes that the thickness in metric units. One can clearly combine (I.4) with (I.3) to get the resistance of a PCB trace: R=
ρl (1 + (T − 20)δρ) 0.000034798(CPW)w
(I.5)
where w the width of the PCB trace in metres.2 If we consider the resistance of a ground plane then the non-uniform distribution of the current must be accounted for. One approximation to account for this is to consider two contact points to the ground plane. These contact points have a certain diameter which are denoted as d1 and d2 metres. These two contact points are l metres apart. An expression for the effective resistance 2 Equation (I.5) assumes that the current is uniform across the cross-section of the trace. This assumption is good for normal PCB traces, but breaks down with wide structures such as ground and power supply planes.
I.3 Formulae
441
between these two points on the plane is: 2l 2l ρ R= ln + ln (1 + (T − 20)δρ) 2πtm d1 d2 2l 2l ρ + ln (1 + (T − 20)δρ) or R = ln 0.000069596(CPW)π d1 d2
(I.6) (I.7)
Note I.1 If the contact points are near the edge of the plane then the resistance value calculated by (I.6) can increase by a factor of two. If the contact point is near a corner then it will increase by an even larger factor.
I.3.3
Parallel Plate Capacitance w
l Dielectric
h Figure I.1: Parallel plate capacitor. Figure I.1 shows a generic parallel plate capacitor. It is assumed that the material between the plates has a dielectric constant of = r 0 . The capacitance of the system is: lw A = Farads (I.8) C= h h
I.3.4
Inductance of Circular Wire Loops
The expression for the inductance of a circular loop of wire is: 8a L = µ0 a ln −2 R
(I.9)
where: a the loop radius R the wire radius Remark I.1 Note the weak dependence of the inductance with respect to the wire radius. This is a result of the ln function in (I.9). However, the inductance of the loop is strongly dependent on the radius of the loop.
442
Useful Formulae
I.3.5
Inductance of Rectangular Loops
Similar to the previous expression we can define the inductance of a rectangular loop as: 2y 2x L = 4 × 10−9 x ln + y ln (I.10) d d where: L the inductance in nH x the length of the rectangular loop in cm y the width of the rectangular loop in cm d the diameter of the wire in cm
I.3.6
Mutual Inductance of Two Loops
The following expression calculates the mutual inductance of two circular loops of wire. It should be noted that the loops must be well separated for this expression to be valid. Furthermore, is is assumed that the loops are flat, and their surface areas are parallel to each other for maximum coupling. The expression for the maximum mutual coupling is: Lm =
2A1 A2 d3
(I.11)
where: d separation of the loops in cm A1 the surface area of loop 1 in cm2 A2 the surface area of loop 2 in cm2 Equation (I.11) is valid for: d> d>
I.3.7
A1 A2
Mutual Inductance of Parallel Transmission Lines
The following expression gives the mutual inductance between two round or square parallel wires suspended above a ground plane. The units of the mutual inductance expression depend on the units of self inductance for one of the transmission lines (use an appropriate expression for this). The mutual inductance expression is:
1 Lm = L (I.12) 2 1 + hs where: s separation between wires in cm h height of wire above the ground plane in cm L the self inductance of one of the parallel wires
I.3 Formulae
I.3.8
443
General Transmission Line Expressions
This section contains some general expressions used for generic transmission lines. Characteristic Impedance
L0 C0
(I.13)
L0 C0
(I.14)
Z0 = Propagation delay per cm D=
Propagation delay per cm given effective permittivity √ D = 3.356 × 10−11 reff
(I.15)
Capacitance per cm C0 =
D Z0
(I.16)
Inductance per cm L0 = DZ0
(I.17)
where: L0 inductance per cm C0 capacitance per cm D propagation delay per cm reff effective relative permittivity
I.3.9
Coaxial Transmission Line
d2
d1
Dielectric material with relative permittivity of e r Figure I.2: Coaxial cable cross-section. Figure I.2 shows the cross-section of a coaxial cable. The relevant transmission line characteristic impedance expression is: d2 60 (I.18) Z0 = √ ln r d1
444
Useful Formulae The inductance and capacitance of the coaxial transmission line are respectively: d2 L = (2.002 × 10−9 )x ln (I.19) d1 (5.56 × 10−13 )xreff C= (I.20) ln dd21 where x the length of the cable in cm.
I.3.10
Single Wire Above a Ground Plane d
Assume air dielectric
h
Figure I.3: Round wire suspended above a ground plane. Figure I.3 shows the situation of a round wire suspended in air above a ground plane. This is the situation that occurs in a wire wrap board layout. The relevant expressions for this are: 4h Z0 = 60 ln (I.21) d where: d the diameter of the round wire in cm h the height of the wire above the ground plane in cm One of the advantages of wire wrap is that the propagation delay per cm is as fast as it can be – i.e. 3.336 × 10−11 sec/cm or 33.36 psec/cm. This is because it operates in an air dielectric.3 The total inductance of the wire trace can be found using (I.17) and multiplying by the length of the trace: 4h −9 L = (2.002 × 10 )x ln (I.22) d 3 We are assuming in this that the ground plane is on top of the supporting PCB material. In many situations this may not be the case, and consequently the relative dielectric will be greater that 1 and the propagation velocity will be lower.
I.3 Formulae
445
where x the length of the wire trace in cm. Similarly the total capacitance of the wire can be calculated using (I.16) and multiplying by the length: C=
(5.560 × 10−13 )x ln 4h d
(I.23)
where x the length of the wire trace in cm.
I.3.11
Twisted Pair Transmission Line
Twisted pair cables are used extensively for interconnection of systems. For example, the copper cabling from your house to the telephone exchange is twisted pair cable with a characteristic impedance of approximately 600Ω.
s
d
Insulation and dielectric material Surrounding dielectric is air Figure I.4: Configuration of twisted pair transmission line. Figure I.4 shows the configuration of the twisted pair conductors. The effective permittivity of the conductors depends on the degree of twist of the cables, since this alters the amount of flux the flows through the insulation dielectric and air. Suffice to say, the effective dielectric constant will be greater than one for insulated wire. The relevant expressions of this transmission line are: 2s 120 Z0 = √ ln (I.24) reff d Propagation delay per cm: √ D = 3.336 × 10−11 reff
(I.25)
Total inductance of the twisted pair transmission line can be calculated using the length of the line and (I.17) to give: −9
L = (4.003 × 10
2s )x ln d
(I.26)
446
Useful Formulae and similary the total capacitance for the transmission line is: C=
(2.78 × 10−13 )xr ln 2s d
(I.27)
where x the length of the line in cm.
I.3.12
Microstrip Transmission Line
Microstrip transmission lines are equivalent to tracks laid out on a conventional PCB, where the track is either on the top or the bottom layer of the board (as in a 4 layer PCB with the ground and positive supply planes in the middle of the board). The following equations give approximate expressions for the characteristic impedances of the microstrip [23]. A field solver is required to obtain more accurate results. It should be noted that the equations have limitations on the relative dimensions of the strip lines so that reasonable accuracy can be obtained. The following discussion is with reference to Figure I.5.
Dielectric constant e r
w t
h
Figure I.5: Dimensions of a microstrip transmission line. The following expressions are accurate for: w ≤6 h 1 ≤r ≤ 16
0.25 ≤
Z0 = Ca =
µ0 0 1 e Ca
(I.28)
2π 0 w ln( 8h ww + 4h ) 0 h + 1.393
w
when + 1.444 when
w h w h
≤1
+ 0.667 ln h >1 − 12 r + 1 r − 1 t 12h + + F − 0.217(r − 1) √ e = 1+ 2 2 w wh w 2 w 0.02(r − 1) 1 − h when h < 1 F = 0 when w h >1
where: e the effective permittivity
(I.29)
(I.30) (I.31)
I.3 Formulae
447
Equation (I.29) has a lower limit of 0.25 for the w/h ratio. An approximate expression for the characteristic impedance that will give values for smaller w/h ratios is: 5.68h 87 ln Z0 = √ (I.32) 0.8w + t r + 1.41 which is valid when 0.1 < w/h < 2.0 and 1 < r < 15.
I.3.13
Symmetric Stripline Transmission Line Dielectric constant e r
t
w h
Figure I.6: Dimensions of a symmetric stripline. The following expression are for a stripline where the interior conductor is in the middle of the top and bottom planes, as shown in Figure I.6 [1]. The following expressions are accurate for: t < 0.25 h t < 0.11 w For
w h
< 0.35 (i.e. a narrow line): 60 4h Z0sym = √ ln r πK1
2 w t t 4πw K1 = 1+ 1 + ln + 0.255 2 wπ t w
For
w h
(I.34)
> 0.35 (i.e. a wide line):
94.15 Z0sym = √ w r h−t + Kπ2 1 1 2 ln +1 − K2 = 1 − ht 1 − ht 1−
I.3.14
(I.33)
(I.35)
t h
− 1 ln
1 −1 (1 − ht )2
(I.36)
Offset Stripline Transmission Line
Figure I.7 shows the dimensions of an offset transmission line [1]. The characteristic of this line is obtained from those of the symmetric line. It should be
448
Useful Formulae
Dielectric constant e r
t b
w
a
Figure I.7: Dimensions of the offset transmission line. noted that these equations are an approximation, and a field solver should be used for more accurate results: Z0offset = 2
Z0sym (h1 , w, t, r )Z0sym (h2 , w, t, r ) Z0sym (h1 , w, t, r ) + Z0sym (h2 , w, t, r )
where: h1 = 2a + t h2 = 2b + t
(I.37)
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