EXPERIMENT NO. 13 Aim To implement VHDL code for SISO, SIPO, PISO and PIPO registers.
Tool required
Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a
Theory
Registers A register consists of a set of flip-flops (each flip-flop stores one bit of information).
Shift Register A shift register is a sequential logic device made up of flip-flops that allows parallel or serial loading and serial or parallel outputs as well as shifting bit by bit.
Serial input serial output (SISO) This configuration allows conversion from serial to serial format. Data is input and output serially.
Circuit diagram
Fig (13.1)
Serial input parallel output (SIPO) This configuration allows conversion from serial to parallel format. Data is input serially and output in parallel lines.
Circuit diagram
Fig (13.2)
Parallel input serial output (SIPO) This configuration allows conversion from parallel to serial format. Data is input in parallel format and data is output serially.
Circuit diagram
Fig (13.3)
Parallel input parallel output (SIPO)
This configuration allows conversion from parallel to parallel format. Data is input in parallel format and data is output in parallel format.
Fig (13.4)
VHDL code for SISO register LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY siso IS port(clk,si,pr,cr:in std_logic;s0:out std_logic); END ENTITY siso; ARCHITECTURE siso_beh OF siso IS signal s1,s2,s3: std_logic; begin process(clk,cr,pr,si) begin if(cr='0') then s1<='0';
s2<='0'; s3<='0'; s0<='0'; elsif(pr='0') then s1<='1'; s2<='1'; s3<='1'; s0<='1'; elsif(clk='1' and clk'event) then s1<=si; s2<=s1; s3<=s2; s0<=s3; end if; end process; END ARCHITECTURE siso_beh;
Output
result window of SISO register
VHDL code for SIPO register LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY sipo IS port(clk,si,pr,cr:in std_logic;Q1,Q2,Q3,Q4:INout std_logic); END ENTITY sipo; ARCHITECTURE sipo_beh OF sipo IS begin process(clk,cr,pr,si) begin if(cr='0') then Q1<='0'; Q2<='0'; Q3<='0'; Q4<='0'; elsif(pr='0') then Q1<='1'; Q2<='1'; Q3<='1'; Q4<='1'; elsif(clk='1' and clk'event) then Q1<=si; Q2<=Q1; Q3<=Q2; Q4<=Q3; end if; end process; END ARCHITECTURE sipo_beh of sipo;
Output
result window of SIPO register
VHDL code for PIPO register LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY PIPO IS port(clk,pr,cr:in std_logic; i:in std_logic_vector(1 to 4); q:out std_logic_vector(1 to 4)); END ENTITY PIPO; ARCHITECTURE PIPO_beh OF PIPO IS BEGIN process(clk,cr,pr,i) begin if(cr='0') then
q(1)<='0'; q(2)<='0'; q(3)<='0'; q(4)<='0'; elsif(pr='0') then q(1)<='1'; q(2)<='1'; q(3)<='1'; q(4)<='1'; elsif(clk='1'and clk'event)then q(1)<=i(1); q(2)<=i(2); q(3)<=i(3); q(4)<=i(4); end if; end process; END ARCHITECTURE PIPO_beh; Output
result window of SIPO register
VHDL code for bidirectional SISO register LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY bidec_SISO IS port(clk,pr,cr,m:in std_logic; SO,SI:inout std_logic); END ENTITY bidec_SISO; ARCHITECTURE bidec_beh OF bidec_SISO IS signal S1,S2,S3:std_logic; BEGIN process(clk,cr,pr,SI,m) begin if(cr='0') then S1<='0'; S2<='0'; S3<='0'; SO<='0'; elsif(pr='0') then S1<='1'; S2<='1'; S3<='1'; SO<='1'; elsif(clk='1'and clk'event)then if(m='0')then S1<=SI; S2<=S1; S3<=S2; SO<=S3; elsif(m='1')then S3<=SO;
S2<=S3; S1<=S2; SI<=S1; end if; end if; end process; END ARCHITECTURE bidec_beh;
Output
result window of directional SISO register
Result - The VHDL code for SISO, SIPO, PIPO and bidirectional SISO register were implemented and simulated successfully,
