TECHNICAL ARTICLE
FUNDAMENTAL PRINCIPLES BEHIND BEHI ND THE SIG SIGMA-DE MA-DEL LTA ADC TOPOLO TOPOLOGY: GY: PART PART 1
Michael Cliford Applications Engineer, Engineer, Analog Devices, Inc.
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fS Nyquist Operation
ADC
Introduction The Σ- Δ ADC is a staple in the tool kit of today’s signal acquisition and processing system designers. The aim of this article is to give the reader the base knowledge on the fundamental princi ples behind the Σ- Δ ADC topology. to pology. Examp les of the tr ade-off ade-offss between betw een noise, noi se, bandwidth, settling time, and all other key parameters associated with ADC subsyste su bsystem m design desi gn are explor ed to provide p rovide contex contextt for design designers ers of precision data acquisition circuits. Typically there are two blocks: the Σ- Δ Δ modulator and the digital signal processing bl ock, usually a digital fil ter. This high level block diagram and the key concepts of the Σ- Δ Δ ADC are shown in Figure 1.
Quantization Noise = q/√ 12 q = 1 LSB
fS 2
fS
Figure 2a. Nyquist scenario. Sampling at F S S , Nyquist bandwidth is F S S /2. Oversampling + Digital Filter + Decimation
KfS
Two Blocks: Analog Input
Σ Δ -
Modulator 1
Digital Signal Processing 2
Digital Filter
ADC
Digital Conversion Output Data Rate (ODR)
fS
DEC
Digital Filter
Reference Input
Removed Noise
Pillar Concepts in Understandin Understanding g Oversampling
Noise Shaping
Σ Δ ADCs -
Digital Filtering
Decimation
fS 2
KfS 2
KfS
Figure 2b. Oversampled scenario. Sampling occuring at K × F S S .
Figure 1. Pillar concepts of the Σ -- ADC. Δ
Oversampling + Noise Shaping + Digital Filter + Decimation
As the Σ- Δ Δ modulator is an oversampled architecture, let’s start with the sampling theory and the scenar io of Nyquist and oversampled ADC operation.
Digital Filter
Σ Δ -
Figure 2 illustrates the comparison between the Nyquist operation of an ADC with the oversampled case and finally with the Σ- Δ modulated (also oversampled ) case. Figure 2a represents the quantization noise of an ADC when running in a straight Nyquist opera tion. In this case, the quantization noise is determined by the LSB size of the ADC. F S is the sampling rate of the ADC and F S /2 is the Nyquist Ny quist frequ frequency. ency. Figure 2b shows the same sam e converter, except now it is used in an oversampled context so a faster sampling rate is employed. The sampling rate is increased by a factor of K with the quantization noise now spr ead over a wider bandwidth up to K × F S /2. The low -pass digit digital al fil ter (typically with decimation) decimation ) removes quantization noise outside of the blue r egion.
MOD
In-Band Signals
FMOD = K × ODR
DEC
fODR
Quantization Noise Shaped to Out of Band Zone Noise Removed by Digital Filter
fODR KfODR 2 2 K = Oversampling Ratio (OSR)
FMOD = K × ODR
Figure 2c. Σ - - Δ ADC scenario. Oversampled and noise shaped, sampling occurring at F MOD MOD = K × F ODR ODR .
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2
Fundamental Principles Behind the Sigma-Delta ADC Topology: Part 1
The Σ- Δ modulator has the added feature of noise shaping, as shown in Figure 2c. The quantization noise of the analog-to-digital conversion is shaped by the modulation scheme, shifting it (typically ) from a low bandwidth up to a higher frequency, allowing a low-pass digital filter to eliminate it from the conversion result. The Σ- Δ ADC can be designed with the noise floor determined by thermal noise and not limited by quantization noise.
the coarse output and reconstructs an accurate digital version of the analog input. A ones density output in response to a sine wave input is ill ustrated in Figure 4. The rate of change of the modulator output from a low level to high level depends on the rate of change of the input. At full-scale input of the sine wave, the modulator output switching rate reduces and the output +1 state dominates. Similarly when the sine wave is at its negative full scale, the transitions between +1 and –1 are reduced and the –1 output dominates. At the maximum rate of change of the sine wave input, the highest density of switching between +1 and –1 in the modulator output occurs. The rate of change of the output is following that of the input. It is the rate of transition of the Σ- Δ modulator output that describes the analog input.
Sample, Modulate, Filter The Σ- Δ ADC is clocked using either an internal or external sampling clock. Often the ADC’s master clock (MCLK ) is divided down prior to use by the modulator; be mindful of this when reading the ADC data sheet and understand the modulator frequency. The sampling frequency passed to the modulator sets the sampling frequency F MOD. The modulator outputs data to the digital filter at this rate, in turn the digital filter (typically lowpass, with some decimation ) provides data at the output data rate (ODR). Figure 3 illustrates this flow.
In-Depth View of a First Order
Using a linear model to describe this single bit modulator (Mod 1) the system is shown as a control system with negative feedback. The quantization noise is the difference between the input and the output of the quantizer. A low-pass filter follows the input delta node. In Figure 5b, the quantization noise is described by the term N.
Σ- Δ Modulator
The Σ- Δ modulator is a negative feedback system, analogous to a closedloop amplifier. The loop contains a low resolution ADC and DAC, as well as a loop filter. The output and feedback are coarsely quantized often only a single bit output as a high or low. The basic structure is implemented as an analog system for ADCs, where the quantizer is the block in which the sampling is accomplished. Provided conditions exist for stability of the loop, the output is a coarse representation of the input. The digital filter takes
H(f) is the function of the loop filter and it defines both the noise and signal transfer functions. H(f) is a low-pass filter function with very high gain at low frequencies (within the bandwidth of interest ) and attenuation of higher frequency signals. The loop filter can be implemented as a simple integrator or a cascade of integrators. In practice a DAC is placed in the feedback path to take the digital output signal and feed it back to the analog input delta node.
MCLK or CLK kHz or MHz Input Pin at the ADC
Internal Oscillator Crystal Oscillator External System Clock
Clock Source
Internal Clock Divider
Σ Δ -
Analog Input
Modulator
Modulator Sampling Clock FMOD = K × ODR Sets the Sampling Rate of the Modulator Data Output from Modulator at F MOD
Output Data Rate (SPS, KSPS, MSPS) ODR = FMOD /K
Digital Filter
Decimation Occurring Within the Digital Filter Block
Figure 3. Σ - Δ ADC flow: sampling from modulator output to digitally filtered output.
Single Bit Σ Δ Modulator Output in Time Domain
Output
-
+1
Linear Model (a) Σ
Input
Δ
In
+ –
Out
Low-Pass Filter
Quantizer
–1 0
50
100
150
200
250
Time (Clock Cyles) Ones Density of Output Represents the Input
Figure 4. Σ - Δ ones density in response to sine wave input. Linear model (a) of the Mod 1
Σ - Δ loop.
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Linear Model (b) N
Σ Δ
I
In +
H(f) –
+
Out
+ Quantizer
H(f) (dB) I = H(f) × [In – Out] Out = I + N Out = N + H(f) [In – Out] Out [1 + H(f)] = N + H (f) × In Out = In × H(f) +N × 1 1 + H(f) 1 + H(f)
0 dB
Input Transfer Function
Log f Filter Transfer Function H(f)
0 dB
0 dB
Noise Transfer Function
Noise Shaping Suppressing Quantization Noise at Low Frequency
1 1 + H(f)
H(f) 1 + H(f)
Log f Signal Transfer Function
Log f Noise Transfer Function
Figure 5. Linear model (b) of the Mod 1 Σ - Δ loop including equations, filter, signal, and noise transfer function plots.
Solving the equations shown in Figure 5 gives the signal and noise transfer functions. The signal transfer function operates as a low-pass filter, with a gain of 1 in the bandwidth of interest. The noise transfer function is a highpass filter function, providing the noise shaping. There is strong suppression of the quantization noise at low frequencies around dc. The quantization noise signal seen at high frequencies outside the bandwidth of interest is increased. For the single-order modulator (Mod 1), the noise increases at a rate of approximately 20 dB/decade. A common method to increase the resolution of the system is to increase the loop filter order by cascading two loop filters. The H (f) of the overall loop filter now has a greater roll off, and the noise transfer function has a transition of 40 dB/decade for a Mod 2 style. The quantization noise is shaped more aggressively, with much lower frequency noise. Figure 6 compares Mod 1 and Mod 2 Σ- Δ ADCs. The variations and styles of Σ- Δ modulators are wide ranging. Architectures that circumvent stability concerns of higher order, single bit loops are called multistage noise shaping modulators (MASH) architectures. The multistage (MASH style) architectures enable design of stable, high order Σ- Δ modulators through a combination of inherently stable lower order loops.
3
Clock KfODR = FMOD
Integrator V IN
1-Bit @FMOD
+
Integrator V IN
+
1-Bit DAC
1-Bit Stream @FMOD –
Latched Comparator (1-Bit ADC)
+V REF
1-Bit DAC
1-Bit Data Stream
–V REF
Clock KfS = FMOD
+
–
–
Integrator
Mod 1
Mod 2
H2(f) N2(f) = 40 dB/decade
) B d ( ) f (
) f (
H
H1(f)
1 H0 + 1
dB
0 dB
N1(f) = 20 dB/decade
Log f Filter Transfer Function
Log f Noise Transfer Function
2nd Order Digital Filter
1st Order
fS 2
KfS 2
Mod 1 vs. Mod Quantization Noise
Figure 6. Mod 1and Mod 2 block diagram configurations with comparative plots of the filter and noise transfer functions.
About the Author Michael Clifford is an applications engineer within the Linear and Precision Technology team at Analog Devices, Ireland. The author would like to acknowledge the content, contributi on, and influence of Adrian Sherry, Colin Lyden, and Walt Kester of Analog Devices to this article.
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