Este documento contiene una lista de problemas donde se calcula el punto Q de operación de transistor BJT, así como la ganancia en pequeña señal e impedancia de entrada/salida.Descripción completa
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laboratorio uis transistor Bjt como interruptorDescripción completa
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Descripción: Informe configuraciones básicas bjt Descripción de la polarización y modelos de pequeña seññal.
Descripción: Una breve investigación sobre los amplificadores BJT y las clases de amplificadores
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Chapter 4 BJT BIASING CIRCUIT
Introduc Intr oduction tion – Bia Biasing sing The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system. In fact, the amplifier increases the strength of a weak signal by transferring transferring the t he energy energy from the applied DC source to the weak input input ac signal sig nal The analysis analys is or design of any a ny electronic electronic amplifier therefore therefore has two components: •The dc portion and •The ac portion During the design desig n stage, the choice of parameters for for the required dc levels will affect affect the ac response. What is biasing circuit? Biasing: Bias ing: Application of dc voltages to establish establis h a fixed level of current current and voltage.
Purpose of the DC biasing circuit • To turn the device “ON” • To place it in operation in the region of its characteristic characteris tic where the device operates operates most linearly . •Proper biasing circuit which it operate in linear region and circuit have centered centered Q-point or midpoint biased •Improper biasing cause Improper biasing cause Distortion in the output signal • Produce limited or clipped at output signal •
Important basic relationship
I E
= I C + I B
β =
I C I B
I E = ( β + 1)I B ≅ I C V CB
=V
CE
−V
BE
Operating Point Act ive or Li near Regio n Operatio n Base – Emitter junction junction is forward biased biased Base – Collector junction is is reverse biased biased •
Good ope rating rating point •Satur Satur ation Region Operation Operation
Base – Emitter junction junction is forward biased biased Base – Collector junction junction is forward biased Region Operation •Cutoff Region Base – Emitter junction junction is reverse biased biased
BJT Analysis
DC analysis
AC analysis
Calculate the DC Q-point
Calculate gains of the amplifier
solving input and output loops
Graphical Method
DC Biasing Circuits •Fixed-bias circuit •Emitter-stabilized bias circuit •Collector-emitter loop •Voltage divider bias circuit •DC bias with voltage feedback
FIXED BIAS CIRCUIT
This is common emitter (CE) configuration 1st step: Locate capacitors and replace them with an open circuit 2nd step: Locate 2 main loops which; BE
loop (input loop)
CE loop(output loop)
FIXED BIAS CIRCUIT
1st step: Locate capacitors and replace them with an open circuit
FIXED BIAS CIRCUIT
2nd step: Locate 2 main loops. BE Loop
CE Loop
1
1
2 2
FIXED BIAS CIRCUIT
BE Loop Analysis ■
1
IB
From KVL;
−V CC + I B R B +V B E = 0 ∴ I B =
V CC
−V BE
R B
A
FIXED BIAS CIRCUIT
CE Loop Analysis ■
From KVL;
−V CC + I C RC +V CE = 0 ∴V CE =V CC − I C RC
IC
■
As we known;
■
I C = β I B B Substituting
2
A
with
VCC − VBE I C = β DC R B Note that RC does not affect the value of Ic
B
FIXED BIAS CIRCUIT
DISADVANTAGE Unstable –
because it is too dependent on β and produce width change of Q-point
For
improved bias stability , add emitter resistor to dc bias.
Load line analysis
A fixed bias circuit with given values of VCC,RC and RB can be analyzed ( means, determining the values of IBQ , ICQ and VCEQ ) using the concept of load line also. Here the input loop KVL equation is not used for the purpose of analysis, instead, the output characteristics of the transistor used in the given circuit and output loop KVL equation are made use of.
Saturation Region
Q-Point DC Load Line
Cutoff Region
Plot load line equation
=V CC − I C R C
V CE
IC(sat) occurs when
transistor operating in
saturation region
I C
sat
=
V CC RC
V CE = 0
VCE(off) occurs when
transistor operating
in cut-off region
V CE ( off ) = V CC − I C RC I
C = 0
Circuit Values Affect t he Q-Point
Increasing Rc Decreasing Vcc
Varying Ib
EMITTER-STABILIZED BIAS CIRCUIT
An emitter resistor, R E is added to improve stability 1st step: Locate capacitors and replace them with an open circuit 2nd step: Locate 2 main loops which; BE
Resistor, RE added
loop
CE loop
EMITTER-STABILIZED BIAS CIRCUIT
1st step: Locate capacitors and replace them with an open circuit
EMITTER-STABILIZED BIAS CIRCUIT
2nd step: Locate 2 main loops. BE Loop
CE Loop
1
1
2 2
EMITTER-STABILIZED BIAS CIRCUIT
1
BE Loop Analysis ■
From kvl; −V CC + I B R B +V BE + I E R E = 0
Recall;
I E
= ( β + 1) I B
Substitute for IE
−V CC + I B R B +V BE + ( β + 1)I B R E = 0 ∴ I B =
−V BE + ( β + 1)R E
V CC R B
EMITTER-STABILIZED BIAS CIRCUIT
CE Loop Analysis ■
From KVL;
−V ■
CC
+
I C RC
+V
CE
+
I E RE
=
0
Assume; I E ≈ I C
2 ■
Therefore;
∴V CE = V CC − I C ( RC + R E )
Improved Bias Stability The addition of the emitter resistor to the dc bias of the BJT provides improved stability, that is, the dc bias currents and voltages remain closer to where they were set by the circuit when outside conditions, such as temperature, and transistor beta, change.
Without Re
I c
V CC −V BE = β R B
With Re
V CC −V BE I c = β R B + ( β + 1) R E
Note :it seems that beta in numerator canceled with beta in denominator
VOLTAGE DIVIDER BIAS CIRCUIT
Provides good Q-point stability with a single polarity supply voltage
This is the biasing circuit wherein, ICQ and VCEQ are almost independent of beta. The level of IBQ will change with beta so as to maintain the values of ICQ and VCEQ almost same, thus maintaining the stability of Q point .
Two methods of analyzing a voltage divider bias circuit are: Exact metho d : can be app li ed to any vol tage di vid er circ uit Ap proximate method : direct method, saves time and energy, 1st step: Locate capacitors and replace them with an open circuit 2nd step: Simplified circuit using Thevenin Theorem 3rd step: Locate 2 main loops which; BE loop CE loop
VOLTAGE DIVIDER BIAS CIRCUIT ■
2nd step: : Simplified circuit using Thevenin Theorem
Thevenin Theorem;
From Thevenin Theorem; RTH
V TH
Simplified Circuit
=
R1 // R2
=
=
R2 R1
+
R2
R1
× R2
R1
+
V CC
R2
VOLTAGE DIVIDER BIAS CIRCUIT
2nd step: Locate 2 main loops.
BE Loop
CE Loop
2 2 1
1
VOLTAGE DIVIDER BIAS CIRCUIT
BE Loop Analysis ■
From KVL;
−V TH + I B RTH +V BE + I E R E = 0
Recall; 1
I E
= ( β + 1) I B
Substitute for IE −V TH + I B RTH +V BE + ( β + 1)I B R E = 0 ∴ I B =
−V BE + ( β + 1)R E
V TH R RT H
VOLTAGE DIVIDER BIAS CIRCUIT
CE Loop Analysis ■
From KVL; −V CC +
■
I C RC
+V CE +
I E RE
=
Assume; I E ≈ I C
2 ■
Therefore; ∴V CE = V CC − I C ( RC + R E )
0
Approximate analysis: R i
R2
→ I R 2
( β + 1) R E
R 2
I b
⇒ β R E > 10R 2
If
this condition applied then you can use approximation method . This
makes IB to be negligible. Thus I1 through R1 is almost same as the current I2 through R2. Thus R1 and R2 can be considered as in series. Voltage divider can be applied to find the voltage across R2 ( VB)
Approximate Analysis When
RE > 10R2 ,
Then IB << I2 and I1
R 2 VCC
VB
R1
VE
R2
VB
I2 :
VBE
VE
IE
RE
From Kirchhoff’s voltage law:
VCE
=
VCC
−
ICR C
−
IER E
IE ≅ IC VCE = V CC −I C (R C + R E )
This is a very stable bias circuit. The currents and voltages are nearly independent of any variations in .
DC Bias with Voltage Feedback
Another way to improve the stability of a bias circuit is to add a feedback path from collector to base. In this bias circuit the Q-point is only slightly dependent on the transistor beta, .
Base-Emitter Loop From Kirchhoff’s voltage law:
-VCC + I′C R C +I BR B +VBE +I E R E = 0 Where I B << IC: I' = I + I ≅ I C C B C
Knowing IC = IB and IE equation becomes: VCC – I B R C
IC, the loop
IBRB
VBE
Solving for I B: IB
VCC RB
VBE
(R C
RE )
IBRE
0
Collector-Emitter Loop Applying Kirchoff’s voltage law: ’