1. A full adder adds A. 2 bits B. 3 bits C. 4 bits D. any number of bits Answer: Option B Answer: Option Explanation:
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2. For a !od "4 parallel parallel counter counter we we need need A. " flip flops
B. " flip flops and 2 A#D $ates C. " flip flops and 4 A#D $ates D. none of t%e abo&e Answer: Option C Answer: Option Explanation: 2" ' "4 (o we need " flip)flops and *" ) 2+ ' 4 A#D $ates. View Answer Disc Answer Discuss uss in Foru Forum m Workspace eport
3. ,f t%e inputs to a 2 input -O -O $ate are %i$% t%en t%e output is %i$%. A. /rue B. False Answer: Option B Answer: Option Explanation: Output is 0ow. View Answer Disc Answer Discuss uss in Foru Forum m Workspace eport
4. /%e number of select lines in a 1" 1 multipleer are are A. 4 B. 3 C. 2 D. 1 Answer: Option A Answer: Option Explanation: 24 ' 1". View Answer Disc Answer Discuss uss in Foru Forum m Workspace eport
. 5s complement of " 16 is A. 4316 B. 7416 C. "16 D. 316 Answer: Option A Answer: Option Explanation:
) " ' 43. ". Am e8ui&alent 25s complement representation of t%e 25s complement number 1161 is A. 116166 B. 661161 C. 116111 D. 111161 Answer: Option D Explanation: 25s complement of *1161+ 2 ' 6611
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9. ,n a 9 se$ment display t%e se$ments a, c, d, f, g are lit. /%e decimal number displayed will be A. B. C. 4 D. 2 Answer: Option B Explanation:
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7. /%e minimum number of comparators re8uired to build an 7 bit flas% AD: is A. 7 B. "3 C. 2 D. 2" Answer: Option C
Explanation: 2n ) 1 ' 2 7 ) 1 ' 2. View Answer Discuss in Forum Workspace eport
. For a !od)"4 sync%ronous counter t%e number of flip flops and A#D $ates needed is A. " and 4 respecti&ely B. 4 and " respecti&ely C. 9 and respecti&ely D. and 9 respecti&ely Answer: Option A Explanation: 2" ' "4 ;ence " flip)flops. /%e number of A#D $ates is " ) 2 ' 4 see in t%e $i&en fi$ure
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16. A 4 bit DA: $i&es an output of 4. V for input of 1661. ,f input is 6116 t%e output is A. 1. V B. 2.6 V C. 3.6 V D. 4. V Answer: Option C Explanation:
A. B. 4 C. 3 D. 2 Answer: Option A Explanation: 1611 ' 11 in decimal and 161 ' in decimal 11 - ' . View Answer Discuss in Forum Workspace eport
13. For t%e lo$ic circuit of t%e $i&en fi$ure t%e simplified ?oolean e8uation
A. @ ' *A ?+ *: D+ *< F+ B. @ ' A ' ? : D < F C. A?:D
14. A combination circuit is one in w%ic% t%e output depends on A. input combination at t%at time B. input combination and pre&ious output C. input combination and pre&ious input D. present output and pre&ious output Answer: Option A Explanation: :ombinational circuit does not %a&e memory. View Answer Discuss in Forum Workspace eport
1. 917 ' >>>>>>>>>> . A. 1116662 B. 1116612 C. 1666612 D. 1166612 Answer: Option B
Explanation: 91 in octal ' 9 7 1' 9 in decimal ' 111661 in binary. 1". ?oolean epression for t%e output of -#O *<8ui&alent+ lo$ic $ate wit% inputs A and ? is A. A? A? B. A? A? C. *A ?+. *A ?+ D. *A ?+. *A ?+ Answer: Option C Explanation: *A ?+ *A ?+ ' A ⊕ ?. View Answer Discuss in Forum Workspace eport
19. An ( flip flop can be built usin$ #O $ates or #A#D $ates. A. /rue B. False Answer: Option A Explanation:
A. V B. 2. V C. 1 V D. 6 V Answer: Option B Explanation:
/ransistor is off.
.
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1. A 14 pin #O/ $ate 1: %as >>>>>>>>>> #O/ $ates. A. 7 B. " C. D. 4 Answer: Option B Explanation: " ,nput pins " output pins 1 supply pin and 1 $round pin. ;ence " #O/ $ates. View Answer Discuss in Forum Workspace eport
26. F5s complement of *2?FD+%e is A. < 364 B. D 463 C. D 462 D. : 463 Answer: Option C Explanation:
21. Assertion (A): !aster sla&e C flip flop is commonly used in %i$% speed sync%ronous circuitry Reason (R): !aster sla&e C flip flop uses two C flip flops in cascade. A. ?ot% A and are correct and is correct eplanation of A B. ?ot% A and are correct but is not correct eplanation of A C. A is true is false D. A is false is true Answer: Option D Explanation: )( C) flip)flop is not used &ery commonly. View Answer Discuss in Forum Workspace eport
22. ,nputs A and ? of t%e $i&en fi$ure are applied to a #A#D $ate. /%e output is 0OW
A. from 6 to " B. from 6 to 2 C. from 6 to 1 and 2 to 3 D. from 1 to 2 and 3 to 4 Answer: Option C Explanation: #A#D $ate $i&es 0ow output if all inputs are ;i$%. For ot%er combinations of inputs output is ;i$%. View Answer Discuss in Forum Workspace eport
23. <:0 is a saturatin$ lo$ic. A. /rue
B. False Answer: Option B Explanation: ,t is a non)saturatin$ lo$ic. ;ence %i$%est speed of operation. View Answer Discuss in Forum Workspace eport
24. For t%e #!O( $ate in t%e $i&en fi$ure F '
A. A?:D< B. *A? :+ *D <+ C. A*? :+ D< D. A ? : D< Answer: Option C Explanation: ? : are in parallel and A is in series wit% t%is parallel combination (imilarly D < are in series. /%en D < are in parallel wit% A ? and : @ ' A*? :+ D< . View Answer Discuss in Forum Workspace eport
2. /%e resolution of 4 bit countin$ AD: is 6. &olt for an Analo$ input of "." &olts. /%e di$ital output of AD: will be A. 1611 B. 1161 C. 1166 D. 1116 Answer: Option B Explanation:
Di$ital output of AD: resolution '
.
2". 5s complement of 1216 is A. 2116 B. 7916 C. 9716 D. 9"16 Answer: Option B Explanation: ) 12 ' 79. View Answer Discuss in Forum Workspace eport
29. /%e minterm desi$nation for A?:D is A. m7 B. m16 C. m14 D. m1 Answer: Option D Explanation: A?:D ' 1111 ' m1 . View Answer Discuss in Forum Workspace eport
27. ead t%e followin$ statements /%e circuitry of ripple counter is more comple t%an t%at of sync%ronous counter. /%e maimum fre8uency of operation of ripple counter depends on t%e modulus of t%e counter. /%e maimum fre8uency of operation of sync%ronous counter does not depend on t%e modulus of t%e counter. W%ic% of t%e abo&e statements are correct= A. 1 only B. 1 2 C. 1 2 3 D. 2 3 Answer: Option D Explanation:
:ircuitry of ripple counter is simpler t%an t%at of sync%ronous counter. View Answer Discuss in Forum Workspace eport
2. /%e minterm desi$nation for A?:D is A. m11 B. m13 C. m1 D. m1" Answer: Option C Explanation: A?:D ' 1111 ' m1 . View Answer Discuss in Forum Workspace eport
36. /%e lo$ic circuit of t%e $i&en fi$ure is e8ui&alent to
A.
B.
C.
D. Answer: Option C Explanation:
,n t%e $i&en fi$ure . 31. A multiple emitter transistor %as many emitters and collectors.
A. /rue B. False Answer: Option B Explanation: ,t %as many emitters but one collector. View Answer Discuss in Forum Workspace eport
32. A mode)16 counter can di&ide t%e clock fre8uency by a factor of A. 16 B. 166 C. 1666 D. 16666 Answer: Option A Explanation: Decade counter is di&ide by 16 counter. View Answer Discuss in Forum Workspace eport
33. W%ic% of t%e followin$ binary numbers is e8ui&alent to decimal 16= A. 1666 B. 1166 C. 1616 D. 1661 Answer: Option C Explanation: 1616 ' 7 6 2 6 ' 16. View Answer Discuss in Forum Workspace eport
34. A 4 bit sync%ronous counter %as flip flops %a&in$ propa$ation delay of 6 ns eac% and A#D $ates %a&in$ propa$ation delay of 26 ns eac%. /%e maimum fre8uency of clock pulses can be A. 26 !;E B. 6 !;E C. 14.3 !;E D. !;E
Answer: Option C Explanation: !aimum delay ' 6 26 ' 96 16 ) s.
;ence
.
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3. A counter %as 4 flip flops. ,t di&ides t%e input fre8uency by A. 4 B. 2 C. 7 D. 1" Answer: Option D Explanation: 24 ' 1". 3". A pulse train wit% a 1 !;E fre8uency is counted usin$ a 1624 modulus ripple counter usin$ C flip flops. /%e maimum propa$ation delay for eac% flip)flop s%ould be A. 1 s B. 6. s C. 6.2 s D. 6.1 s Answer: Option D Explanation:
/otal delay '
' 1 ms ' 16 delay of one flip flop. /%erefore delay for one flip)flop ' 6.1 ms.
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39. W%at will be maimum input t%at can be con&erted for a " bit dual slope AGD con&erter uses a reference of )"& and a 1 !;E clock. ,t uses a fied count of 46 *161666+. A. V B. .4 C. 16 V D. 7 V Answer: Option B Explanation:
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37. ,n t%e $i&en fi$ure s%ows a lo$ic circuit. /%e minimum ?oolean epression for t%is circuit is
A. A ? B. A ? : C. A? : D. A? A: ?: Answer: Option B Explanation: Output A*? :+ A? :*A ?+ ' A? A: A? A: ?: ' ? A ?: ' A ? :. View Answer Discuss in Forum Workspace eport
3. ,f number of information bits is 11 t%e number of parity bits in ;ammin$ code is A. B. 4 C. 3 D. 2 Answer: Option B Explanation: 2p H m p 1. ,f m ' 11 p must be 4 to satisfy t%is e8uation. View Answer Discuss in Forum Workspace eport
46. /%e number of di$it 1 present in t%e binary representation of 3 12 9 "4 7 3 is A. 7 B.
term of power two ;ence number of 515 is . 41. Out of ! 7 1 ! 1" 2 ! 1" and 3! 7 memories w%ic% memory can store more bits= A. ! 7 B. 2 ! 1" C. 3 ! 7 D. 1 ! 1" Answer: Option A Explanation: ?its are 46 ! 1" ! and 32 !. View Answer Discuss in Forum Workspace eport
42. A " bit ladder AGD con&erter %as input 161661. /%e output is *assume 6 ' 6 V and 1 ' 16 V+ A. 4.23 B. ".41 C. .2 D. .23 Answer: Option B Explanation: Output '
16 I ".41 V.
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43. A ripple counter %as 4 bits and uses flip flops wit% propa$ation delay time of 2 ns. /%e maimum possible time for c%an$e of state will be
A. 2 ns B. 6 ns C. 9 ns D. 166 ns Answer: Option D Explanation: ,n ripple counter all t%e delays are added. View Answer Discuss in Forum Workspace eport
44. A counter %as a modulus of 16. /%e number of flip flops is A. 16 B. C. 4 D. 3 Answer: Option C Explanation: 23 ' 7 and 2 4 ' 1" /%erefore 4 flip)flops are needed. (ome states will be skipped to $i&e a modulus of 16. View Answer Discuss in Forum Workspace eport
4. /%e counter s%own in t%e $i&en fi$ure is built usin$ 4 )&e ed$e tri$$ered to$$le FFs. /%e FF can be set async%ronously w%en ' 6. /%e combinational lo$ic re8uired to realiEe a modulo)13 counter is
A. F ' J4 J3 J2 J1 B. F ' J4 J3 J2 J1 C. F ' J4 J3 J2 J1 D. F ' J4J3J2J1 Answer: Option A
Explanation: :ounter is modulo)13 it will count up to 1 but due to mod)13 it will be reset at 13 *13+ 16 ' *1161 +2 ' J4 J3J2 J1. 4". ,n t%e fi$ure t%e 0
A. emits li$%t w%en bot% ( 1 and (2 are closed B. emits li$%t w%en bot% ( 1 and (2 are open C. emits li$%t w%en only ( 1 and (2 is closed D. does not
49. A 4 bit ripple counter uses flip flops wit% propa$ation delay of 6 ns eac%. /%e maimum clock fre8uency w%ic% can be used is A. !;E B. 16 !;E C. 26 !;E D. 2 !;E Answer: Option A Explanation: /ime delay ' 6 4 16 )s
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47. An A#D $ate %as two inputs A and ? and one in%ibit input (. Out of total 7 input states output is 1 in A. 1 state B. 2 states C. 3 states D. 4 states Answer: Option A Explanation: Only one input i.e. A ' 1 ? ' 1 and ( ' 6 $i&es output 1. View Answer Discuss in Forum Workspace eport
4. 2"716 ' >>>>>>>>>> . A. 16A1" B. 16?1" C. 16:1" D. 16D1" Answer: Option C Explanation: 16: in %eadecimal ' 1 1" 2 12 ' 2"7 in decimal. View Answer Discuss in Forum Workspace eport
6. ,n a C !aster sla&e flip flop A. bot% master and sla&e are positi&ely clocked B. bot% master and sla&e are ne$ati&ely clocked C. master is positi&ely clocked and sla&e is ne$ati&ely clocked D. master is ne$ati&ely clocked and sla&e is positi&ely clocked Answer: Option C Explanation:
