SMTEC/ DEPT/14-15/ODD/CP/REV 01
St.MOTHER THERESA ENGINEERING COLLEGE, THOOTHUKUDI, VAGAIKULAM - 628102 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING COURSE PLAN Subject Code/Name : CS6303 COMPUTER ARCHITECTURE Staff Name : J. AVINASH DHANDAPANI Date: 08/07/14
Yr/Dept: II CSE
Text Books: 1.David A. Patterson and John L. Hennessey, “Computer organization and design’, Morgan Kauffman / Elsevier, Fifth edition, 2014. Reference Books: 1. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, “Computer Organisation“, Sixth edition, Mc Graw-Hill Inc, 2012. 2. William Stallings “Computer Organization and Architecture” , Seventh Edition , Pearson Education, 2006. 3. Vincent P. Heuring, Harry F. Jordan, “Computer System Architecture”, Second Edition, Pearson Education, 2005. 4. Govindarajalu, “Computer Architecture and Organization, Design Principles and Applications", Second edition, Tata McGraw Hill, New Delhi, 2010. 5. John P. Hayes, “Computer Architecture and Organization”, Third Edition, Tata Mc Graw Hill,1998. 6. http://nptel.ac.in/.
Lect.No
Unit No
1 2 2 3,4 5 5 6 6 7 7 8 9,10
I I I I I I I I I I I I
11 11 12,13 14,15 16,17 18
II II II II II II
20,21 22,23 24,25 26 27,28
III III III III III
29 30
III III
31,32 33,34 35,36 37,38 39
IV IV IV IV IV
40 41 42,43 44,45 46
V V V V V
47 48
V V
Topics to be covered Text UNIT I OVERVIEW & INSTRUCTIONS T1 Eight ideas T1/R1/R2 Components of a computer system T1 Technology T1/R1/R2 Performance T1 Power wall T1/R1 Uniprocessors to multiprocessors T1/R1/R2 Instructions T1/R1/R2 Operations & operands T1/R1/R2 Representing instructions T1/R2 Logical operations T1/R1/R2 control operations T1/R1/R2 Addressing and addressing modes UNIT II ARITHMETIC OPERATIONS T1/R2/R5 ALU T1/R1/R2/R4/R6 Addition and subtraction T1/R1/R2/R6 Multiplication T1/R1/R2/R6 Division T1/R1/R2/R6 Floating Point operations T1 Subword parallelism UNIT III PROCESSOR AND CONTROL UNIT T1 Basic MIPS implementation T1/R1/R3/R5 Building datapath T1/R1 Control Implementation scheme T1/R1/R2 Pipelining T1/R4 Pipelined datapath and control
Page No
Week
11 13//03//1966 24 28/13/50 40 43/18 62/37/400 63/27/348 80/38/349 87/362 90/44/362 111/48/401
w1 w1 w1 w1 w1 w1 w2 w2 w2 w2 w2 w2
178/306/252 178/368/312/177 183/376/317 189/390/324 196/393/334 222
w3 w3 w3 w3 w4 w4
244 251/479/147/223 259/479 272/453 286/684
w4 w5 w5 w5 w6
Handling Data hazards & Control hazards T1/R1 T1 Exceptions UNIT IV PARALLELISM T1/R2/R3 Instruction-level-parallelism T1 Parallel processing challenges T1/R2 Flynn's classification T1/R2 Hardware multithreading T1/R2 Multicore processors UNIT V MEMORY AND I/O SYSTEMS T1/R1 Memory hierarchy T1/R2 Memory technologies T1/R1/R2 Cache basics T1/R1/R2 Measuring and improving cache T1/R1/R2 Virtual memory, TLBs Input/output system, programmed I/O, R1/R2/R3 DMA and interrupts R2/R3 I/O processors
303/461 325
w6 w6
332/444/280 504 509/630 516/646 519/684
w7 w7 w7 w8 w8
374/292 378/158 383/314/110 398/329/121 427/337/283
w8 w8 w9 w9 w9
234,208/217,473 242/474
w10 w10
Staff in charge
HOD
Principal
