Computer Organization Organization Lab, Department of ECE, K L University 13EM201 th
B.Tech IV Year, Semester VII, 2014-2015
Computer Organization Lab Experiments List List of Experiments intended as basic experiments of the course:-
1) Design of Carry-Look-Ahead Carry-Look-Ahead Adder 2) Implementation Implementation of Boolean expressions using multiplexers 3) Design of 4-bit Universal shift register using D-FF 4) Design of 4-bit ALU 5) Design of combinational multiplier List of Experiments supposed to finish in Open Lab Sessions:-
6) Design of Ripple carry Adder 7) Design Design of logic circuit to implement 10’s complement of BCD 8) Design of Associative Cache memory 9) Design of 4X4 RAM cell 10) Design of Booth’s multiplier
Few Sample Project Ideas:-
1)
Design of 1:16 demultiplexer using 1:8 and 1:4 demultiplexers
2) 9-bit odd/even parity generator/checker generator/checker 3) Design of mod-16 synchronous counter using T-FF 4) Design of 8 bit Divider circuit 5) 4 bit odd/even sequence generator generator using JK-FF 6) Implementation Implementation of full adder using PLA having 3 I/P’s, 8 product terms and two O/P’s 7) Design of 8X4 bit ROM using using MOSFET’s 8) Design of 2KX8 memory using two 1KX8 IC’s 9) Design and Implementation of UART. 10) Design and Implementation of FIFO. 11) Design a Melay FSM to generate sequence of Odd Numbers [0001, 0011…1111] and Implement using FPGA. 12)
Design a FSM for Traffic Light Controller.
13) Design and Interface of LIFO & FILO with 2x1 Multiplexer and Implement using FPGA. 14) Design and Implementation of Serial in Parallel out Register. 15) Design a Shift Register which shifts the given Input Sequence either Left or Right using Mode Control. 16) Design and Implementation of Carry Look Ahead Adder using CPLD. 17) Design and Implementation of Hamming Error Detection Techniques. 18) Design and Implementation of Digital Clock Using Seven Segment Display. 19) Design and Interface Binary to Gray & Gray to Binary Code Converters with 2x1 Multiplexer and Implement using FPGA. 20) Design a 2 to 4 Decoder and Interface with Seven Segment Display and Implement using FPGA. Objectives:
The Objective is to expose the students to the various key aspects of Computer Organisation & Architecture by enabling them to perform FPGA based prototyping of experiments with support of a design and simulation in Logisim and Xilinx.
Learning Objectives:
1. Design concepts implementation and model development using the Logisim tool. 2. Logical programming knowledge improvement through active HDL and Xilinx tools. 3. Application verification by dumping program in FPGA’s and testing the workbench.
4. Hardware implementation based on the knowledge gained by the student Pre-requisites:
1. Basic knowledge regarding digital logic design 2. Basic knowledge regarding memory organization 3. Awareness regarding any simulation tool 4. Awareness regarding any programming language like ‘C’ 5. Disciplined learning with positive attitude.
The execution of project based lab planned in two phases:Phase I: Experiments Based : First six weeks student need to work out and execute the list of
programs /experiments as decided by the instructor. These lists of programs /Experiments must cover all the basics required to implement any project in the concerned course. Phase II: Project Based: After six weeks student needs to work out on the project on the concerned
course designed by faculty or he/she may be allowed to do implement his/her own idea in the concerned course. Proposed Dates:-
09/07/2014 to 16/08/2014:- Overview and Basic Experiments of the Lab 18/08/2014 to 23/08/2014:- Abstracts collection and ZEROth review Third week of September, 2014:- First review Second week of October, 2014:- Second review Last week of October, 2014:- Final review Assessment Approach:-
The Project based Lab will be undertaken through External and Internal evaluation. The following Table reflects various evaluation components that will be used to assess the performance of the students. Type of Evaluation
External Evaluation
Internal Evaluation
Max Marks allocated
Evaluation component
60
End Semester External evaluation
40
Attendance Continuous Assessment End Semester Internal examination
Marks allocated
60 05 15
20
Subdivision of the evaluation component Report Viva Voce Execution *Demonstration Viva Voce Record Report Viva Voce Execution Demonstration
Marks Allocated 20 20 10 10 5 10 05 5 5 5 5
*A part of the project work done should be assessed in the End Semester External evaluation to
identify the capability of the student “Hands on experience &Practical knowledge” gained in the Lab. No student of the same batch (project based lab experiment batch) shall be tested by allotting the same experiment.
Signature of course coordinator
Signature of HOD
1. Design of Carry-Look-Ahead Adder Aim: - To design Carry-Look-Ahead Adder using Logisim and simulate the operation. Tools required: - Logisim Objective: - 1. Understanding behaviour of carry look ahead adder from module designed by the
student as part of the experiment 2. Understanding the concept of reducing computation time with respect of ripple carry adder by using carry generate and propagate functions 3. The adder will add two 4 bit numbers Theory:-
To reduce the computation time, there are faster ways t o add two binary numbers by using carry look ahead adders. They work by creating two signals P and G known to be Carry Propagator and Carry Generator. The carry propagator is propagated to the next level whereas the carry generator is used to generate the output carry, regardless of input carry. The block diagram of a 4-bit Carry Look ahead Adder is shown here below -
The number of gate levels for the carry propagation can be found from the circuit of full adder. The signal from input carry Cin to output carry Cout requires an AND gate and an OR gate, which constitutes two gate levels. So if there are four full adders in the parallel adder, the output carry C5 would have 2 X 4 = 8 gate levels from C1 to C5. For an n-bit parallel adder, there are 2n gate levels to propagate through.
Design Issues :
The corresponding Boolean expressions are given here to construct a carry look ahead adder. In the carry-look ahead circuit we need to generate the two signals carry propagator (P) and carry generator (G), Pi = Ai ⊕ Bi Gi = Ai · Bi The output sum and carry can be expressed as Sumi = Pi ⊕ Ci Ci+1 = Gi + ( Pi · Ci) Having these we could design the circuit. We can now write the Boolean function for the carry output of each stage and substitute for each Ci its value from the previous equations: C1 = G0 + P0 · C0 C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0 C3 = G2 + P2 · C2 = G2 P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0 C4 = G3 + P3 · C3 = G3 P3 · G2 P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0 Circuit Diagram:-
Procedure:-
To insert a logic gate, expand the folder Gates and click on the desired logic gate. Once the gate is selected, the mouse will turn into the shape of the selected gate. Place the gate in the circuit area on the right.
To connect the gates, select the arrow icon on to p (
).
Then drag from the output of one gate to the input of another gate. You can connect to any of the small blue dots on the gate symbol.
To create an input to the circuit, select the “Add Pin” icon with an outline of a square (
).
Similarly, add an output to the circuit by using the “Add Pin” icon with an outline of a circle (
).
To assign a name to the input/output pin, click on the pin while the arrow icon (
) is selected.
You may then add the label for the pins. Once you have connected the circuit, you will notice the color of the wire changes. A dark green color means that the current value on the wire is a logical ‘0’, while a light green color signifies a ‘1’. Other wire colours: blue = unknown value, gray = unconnected, red = conflict.
Observations and Result:
2. Implementation of Boolean expressions using Multiplexers Aim:- To design a scheme to implement Boolean expression with help of multiplexer using Logisim
and simulate the operation Tools required: - Logisim Objective:-
To observe Multiplexer active one output pin is also Boolean function with literal variables at the channel select pins and each input corresponding to one min term .
For n terms, use '' n'' input lines
= 1 0r 0 at multiplexer and m-input channel select pins for ''m ''literals of an SOP Boolean function . Theory:-
While Multiplexers are primarily thought of as “data selectors” because they select one of several Inputs to be logically connected to the output, they can also be used to implement Boolean functions. Similarly, while n-bit Decoders are primarily thought of as n-bit binary to 1 of 2n code converters or as Demultiplexers, they can also be used to implement Boolean functions of n variables. Consider the following truth table that describes a function of 4 Boolean variables. A 16 to 1 Multiplexer with A, B,C, and D applied to its S3, S2, S1, and S0 inputs respectively would select one of its 16 inputs for each of the 16 possible combinations of A, B,C, and D. We can implement the function described by the truth table by connecting a voltage source for logic level 1 or ground for a logic level 0 to each of the Multiplexer inputs corresponding to the required value of the function associated with the combination of A, B, C, and D that selected the input. Therefore, the inputs t o the Multiplexer will be the same as the F entries in the truth table provided A, B,C, and D are connected to the Multiplexer select inputs in the right order.
Circuit Diagram:-
Procedure:-
The design procedure of a combinational logic circuit using multiplexers is as follows. 1. Identify the decimal number corresponding to each min term in the expression.
2. The input lines corresponding to these numbers are to be connected to logic 1 level and all other input lines are connected to logic 0. 3. Then the select inputs are to be applied to the select lines. Using Logisim, to insert a logic gate, expand the folder Gates and click on the desired logic gate. Once the gate is selected, the mouse will turn into the shape of the selected gate. Place the gate in the circuit area on the right.
To connect the gates, select the arrow icon on to p (
).
Then drag from the output of one gate to the input of another gate. You can connect to any of the small blue dots on the gate symbol.
To create an input to the circuit, select the “Add Pin” icon with an outline of a square (
).
Similarly, add an output to the circuit by using the “Add Pin” icon with an outline of a circle (
).
To assign a name to the input/output pin, click on the pin while the arrow icon (
) is selected.
You may then add the label for the pins. Once you have connected the circuit, you will notice the color of th e wire changes. A dark green color means that the current value on the wire is a logical ‘0’, while a light green color signifies a ‘1’. Other wire colours: blue = unknown value, gray = unconnected, red = conflict.
Observations and Result:
3. Design of 4-bit Universal Shift Register using D-FF Aim: - To design a 4-bit unidirectional shift register using D-flip-flops using logisim and
simulate the operation of the same. Tools required: - Logisim Objective:-
The Shift Register is another type of sequential logic circuit that is used for the storage or transfer of data in the form of binary numbers. To understand the behaviour and flow of data is the objective of this experiment. Theory :-
The Shift Register is a type of sequential logic circuit that is used for the storage or transfer of data in the form of binary numbers. This sequential device loads the data present on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name “shift register”. A shift register basically consists of several single bit “D-Type Data Latches”, one for each data bit, either a logic “0” or a “1”, connected together in a serial or daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on. The data bits may be fed in or out of a shift register serially, that is one after the other from either the left or the right direction, or all together at the same time in parallel. The number of individual data latches required to make up a single Shift Register device is usually determined by the number of bits to be stored with the most common being 8-bits (one byte) wide constructed from eight individual data latches. The Shift Register is used for data storage or data movement and are used in calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format. The individual data latches that make up a single shift register are all driven by a common clock (Clk) signal making them synchronous devices. Shift register IC’s are generally provided with a clear or reset connection so that they can be “SET” or “RESET” as required. The effect of data movement from left to right through a shift register can be presented graphically as:
