Commutation Techniques 1 Ppt

THE PROCESS OF TURNING ON OR OFF A POWER ELECTRONIC DEVICE .

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Commutation ◦

Process of turning off a conducting thyristor.

Current Commutation  Voltage Commutation 

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NATURAL COMMUTATION

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FORCED COMMUTATION

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Occurs in AC circuits

T +

vs

~

R

 vo 

Sinusoidal

Supply voltage vs

3



0

2



t



t



t



t

Gate Pulse 



Load voltage vo Turn of o ff  occurs here 



3



0

2 Voltage across SCR tc

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AC VOLTAGE CONTROLLERS CONTROLLERS..

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PHASE CONTROLLED RECTIFIERS.

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CYCLO CONVERTERS.

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Applied to dc circuits Commutation achieved by reverse biasing the SCR or by reducing the SCR current below holding current value. Commutating elements such as inductance and capacitance are used for commutation purpose.

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Self commutation. Resonant pulse commutation. Complementary Complementary commutation. Impulse commutation. External pulse commutation. Load Commutation. Line Commutation.

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Elements such as inductors and capacitors are involved.

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Forced commutation is applied to DC D C circuits.

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It is applied to choppers & inverters.

Self Commutation Or  Load Commutation Or  Class A Commutation 

(Commutation By Resonating The Load)

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Under damped condition using L,C in series with load results in oscillating currents . This results in turning off an SCR when the current through load is zero. zero.

T

i

R Load

V

L

V c( 0 ) + C

In load side commutation the discharging and recharging of capacitor takes place through the load. Hence to test the commutation circuit the load has to be connected. Examples of load side commutation are Resonant Pulse Commutation and Impulse Commutation.

Note: For effective commutation the circuit should be under damped. 2

1   R  That is     2 L  LC  With R = 0, and the capacitor initially initially uncharged uncharged that is V C   0   0

 

i t 

V   L

sin

t  LC 

Current Curre nt i

0

 /2





t



t



2V Capacitor voltage

V

Gate pulse

Conduction time of SCR

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 

V

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Vol oltage tage across a cross SCR



t



t

T1

T2

L

T3

+ VS

RL

2VAUX

C

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VAUX