Members: Nguyen Duc Thinh, Nguyen Hoang Son, Le Minh Tuan , Nguyen Hoang Thanh Tu
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Computer Organization Homework 2 1) For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables i and j are assigned to registers $s0 and $s1, $s1 , respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[8] = A[i-j];
sub $t0, $s1, $s0
# t0 = i - j
sll $t0, $t0, 2
# $t0 = (i-j) * 4
add $t0, $t0, $s6
# t0 = addr of A[i-j]
lw $t0, 0($t0)
# $t0 = A[i-j]
sw $t0, 32($s7)
# B[8] = $t0
2) For the following MIPS assembly instructions, what is the corresponding C statement? Assume that the variables f and g are assigned to registers $s0 and $s1, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. sll $t0, $s0, 2 add $t0, $s6, $t0 sll $t1, $s1, 2 add $t1, $s7, $t1 lw $s0, 0($t0) addi $t2, $t0, 4 lw $t0, 0($t2) add $t0, $t0, $s0 sw $t0, 0($t1)
# $t0 = f * 4 # $t0 = &A[f] # $t1 = g * 4 # $t1 = &B[g] # f = A[f]
sll $t0, $s0, 2 add $t0, $s6, $t0 sll $t1, $s1, 2 add $t1, $s7, $t1 lw $s0, 0($t0) addi $t2, $t0, 4 lw $t0, 0($t2) add $t0, $t0, $s0
// $t0 = f * 4; // $t0 = &A[f]; // $t1 = g * 4; // $t1 = &B[g]; // f = A[f]; // $t2 = &A[f + 1]; // $t0 = A[f + 1]; // $t0 = $t0 + f = A[f + 1] + A[f];
sw $t0, 0($t1) // B[g] = $t0 = A[f + 1] + A[f]; Overall: B[g] = A[f + 1] + A[f]; f = A[f]; 3) For the MIPS assembly instructions in Exercise 2, rewrite the assembly code to minimize minimize the the number if MIPS instructions (if possible) needed to carry out the same function. sll $t0, $s0, 2 // $t0 = f * 4; add $t0, $s6, $t0 // $t0 = &A[f]; sll $t1, $s1, 2 // $t1 = g * 4; add $t1, $s7, $t1 // $t1 = &B[g]; lw $s0, 0($t0) // f = A[f]; addi $t2, $t0, 4 // $t2 = &A[f + 1] Simplify this instruction lw $t0, 4($t0) // $t0 = A[f + 1]; Change by this line add $t0, $t0, $s0 // $t0 = $t0 + f = A[f + 1] + A[f]; sw $t0, 0($t1) // B[g] = $t0 = A[f + 1] + A[f];
4) Translate the following MIPS code to machine language: addi $t0, $s6, 4 add $t1, $s6, $0 sw $t1, 0($t0) lw $t0, 0($t0) add $s0, $t1, $t0 Instructions addi $t0, $s6, 4 add $t1, $s6, $0 sw $t1, 0($t0) lw $t0, 0($t0) add $s0, $t1, $t0
Format I-type R-type I-type I-type R-type R-type
OP 8 32 43 35 32
RS 22 22 8 8 9
RT 8 0 9 8 8
RD 9 16
IM 4 0 0 -
5) Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i, and j are in registers $s0, $s1, $t0, and $t1, respectively. Also, assume that register $s2 holds the base address of the array D. for(i=0; i
add L1:
$t0, $0, $0 slt $t2, $t0, $s0 beq $t2, $0, Exit add $t1, $0, $0 L2: slt $t2, $t1, $s1 beq $t2, $0, L3 add $t2, $t0, $t1 sll $t4, $t1, 4 add $t3, $t4, $s2 sw $t2, 0($t3) addi $t1, $t1, 1 j L2 L3: addi $t0, $t0, 1 j L1 Exit: ...
#i=0 #i
6) Convert the following machine code program to assembly for MIPS 00011010010000000000000000000011 blez $t4,3 00100000000000000000000000000000 addi $zero, $zero, 0 10101110001010110000000000000000 sw $t2, $t5, 0 10101110001010100000000000000010 sw $t2, $t4, 2 00100001001010010000000000001000 addi $t1, $t1, 8 7) Pseudo-instructions Pseudo-instructions are not part of the MIPS instruction set but often appear in MIPS programs. The assembler then has to convert them into a small set of real MIPS instructions. For each of the following pseudo-instructions, convert them to a very short sh ort equivalent sequence of real MIPS instructions. If you need a temporary register, you should use $at.
Note that “small” is a constant that fits in 16 bits (i.e. small enough for the immediate field of an instruction), and “big” is a constant that is 32 bits (i.e. too long for the immediate field) lui $t2, upper(big) ori $t2, $t2, lower(big) add $t1, $t2, $zero addi $t0, $zero, small beq $t1, $t0, L slt $t0, $t4, $t3 beq $t0, $zero, L lui $t1, upper(big) ori $t1, $t1, lower(big) add $t0, $t2, $t1 8) Assume that we would like to expand the MIPS register fi le to 128 registers and expand the instruction set to contain four times as many instructions. a. How this would this affect the size of each of the bit fields in the R-type instructions? b. How this would this affect the size of each of the bit fields in the I-type instructions? _____________________________ _____________________________a. Expanding the register file to 128 bits adds 2 bits to rs, rt, and rd, increasing them to 7 bits each. Assuming 4x (=22) the instructions expands the opcode by 2 bits, to 8 bits total. b. 2 bit , each add to rs, rt and the opcode 9) Find the shortest sequence of MIPS instructions that extracts bits 16 down to 11 from register $t0 and uses the value of this field to replace bits 31 down to 26 in register $t1 without changing the other 26 bits of register $t1.
srl sll srl srl add
$t2, $t0, 10 $t2, $t2, 26 $t1, $t1, 6 $t1, $t1, 6 $t2, $t2, $t1
10) Show how the value 0xabcdef12 0 xabcdef12 would be arranged in memory of a little-endian and a big-endian machine. Assume Assume the data is stored starting at address 0. Address 0 1 2 3 The end
Little
12 ef cd ab
endian
BIG endian ab cd ef 12
