array multiplier

VHDL CODE FOR  ARRAY  MULTIPLIER 

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --library  UNISIM; --use UNISIM.VComponents.all; entity  mult64 is Port ( clk:in std_logic; --rst:in std_logic; a : in std_logic_vecto r(7 downto 0); b : in std_logic_vector (7 downto 0); prod : out std_logic_vector(15 downto 0)); end mult64; architectur e Beh av ioral of mult64 is constant n:intege r :=8; subty pe p lary is std_logic_vector(n-1 downto 0); ty pe p ary is array (0 to n) of plary ; signal pp,pc,ps:pary ; begin pgen:for j in 0 to n-1 gene ra te pgen1:for k in 0 to n-1 generate pp(j)(k)<=a(k) and b(j); end genera te; pc(0)(j)<='0'; end genera te; ps(0)<=pp(0); prod(0)<=pp(0)(0); addr:for j in 1 to n-1 gene rate addc:for k in 0 to n-2 genera te ps(j)(k)<=pp(j)(k) xor pc(j-1)(k) xo r ps(j-1)( k+1); pc(j)(k)<=(pp(j)(k) and pc(j-1)(k)) or (pp(j)(k) and ps(j-1)(k+1)) or (pc(j-1)(k)and ps(j-1)(k+1)); end genera te; prod(j)<=ps(j)(0); ps(j)(n-1)<=pp(j)(n-1); end genera te; pc(n)(0)< ='0'; addlast:for k in 1 to n-1 gene ra te ps(n)(k)<=pc(n)(k -1) xor pc(n-1)( k-1) xor ps(n-1)(k); pc(n)(k)<=(pc(n)(k -1) and pc(n-1)(k-1)) or (pc(n)(k-1) and ps(n-1)(k)) or (pc(n-1)( k-1) and ps(n-1)(k)); end genera te; prod(2*n-1)<=pc(n)(n-1); prod(2*n-2 down to n)<=ps(n)(n-1 down to 1); end behav ioral;