Under GPU K 2 7 V 1 1 9 2 6 1 C _ P 2 0 4 2 @ 2 U 0 _ P U G 1 . 0
D
K 3 7 V 9 6 2 1 1 C _ P 2 0 4 2 @ U 0 _ P U G 1 . 0
K 4 7 V 9 6 2 1 1 C _ P 2 0 4 2 @ U 0 _ P U G 1 . 0
K 5 7 V 9 6 2 1 1 C _ P 2 0 4 2 @ U 0 _ P U G 1 . 0
K 6 7 V 9 6 2 1 1 C _ P 2 0 4 2 @ U 0 _ P U G 1 . 0
K 7 7 V 9 6 2 1 1 C _ P 2 0 4 2 @ U 0 _ P U G 1 . 0
K 8 7 V 9 6 2 1 1 C _ P 2 0 4 2 @ U 0 _ P U G 1 . 0
K 9 7 V 9 6 2 1 C _ P 2 0 4 @ U 0 _ P U G 1 . 0
D
K K K K K K K K 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 3 . 3 . 3 . 3 . 3 . 3 . 3 . 3 . C 6 C 6 C 6 C 6 C 6 C 6 C 6 C 6 _ _ _ _ _ _ _ _ P 3 P 3 P 3 P 3 P 3 P 3 P 3 P 3 0 0 0 0 0 0 0 0 @ @ @ @ @ @ @ @ 6 6 6 6 6 6 6 2 U 6 0 2 U 0 2 U 0 2 U 0 2 U 0 2 U 0 2 U 0 2 U 0 P _ P _ P _ P _ P _ P _ P _ P _ U U U U U G G G G G G U G U G U 7 7 7 7 7 7 7 7 . . . . . . . . 4 4 4 4 4 4 4 4 V V V V V V V 1 0 V 3 1 0 3 1 0 3 1 0 3 1 0 3 1 0 3 1 0 3 1 0 3
K K 6 6 V 1 V 8 3 9 3 . 0 . 0 6 3 6 3 _ _ 3 C 3 C 0 P 0 P 6 6 2 0 2 @ 0 @ _ _ U U U U P 7 P 7 . . G 4 G 4 1
C
+VGA_CORE
C
Near GPU M 1 M 1 Y 1 M 1 M _ _ _ 6 V 7 V 9 V 0 V 0 V 5 9 9 1 5 2 5 . + 1 . 1 2 . + 2 2 3 2 + 1 2 _ + C 2 C 2 C 2 C _ C _ P _ P D P _ P V P V _ _ U U _ 0 0 @ U U @ @ @ @ U 0 2 2 U 9 2 2 U 0 0 2 U 9 7 2 U 7 3 P 3 P 3 P 4 P 4 3 G G G G 1
+ 1 5 .
B
K 1 5 6 1 3 V 3 3 . C 6 _ 2 P 3 0 2 @ 6 U 0 P _ U G 7 . 4
K 1 6 6 3 V 3 3 . C 6 _ P 3 0 2 @ 6 U 0 P _ U G 7 . 4
K 1 7 6 3 V 3 3 . C 6 _ P 3 0 2 @ 6 U 0 P _ U G 7 . 4
K 1 8 6 3 V 3 3 . C 6 _ P 3 0 2 @ 6 U 0 P _ U G 7 . 4
M 1 6 2 6 V 1 1 V 1 1 3 3 4 3 . C _ C 6 _ P 5 P 0 5 8 0 @ @ 0 8 2 U _ 2 U 0 P U P _ 7 U G G 4 2 2
M M 6 3 6 V 1 4 V 1 1 3 1 3 3 . 3 . C 6 C 6 _ _ P 5 P 5 0 0 @ @ 8 2 8 0 0 2 _ _ U U 2 2 2 2
M 5 6 V 1 3 3 . C 6 _ P 5 0 @ 8 0 _ U 2 2
B
K 9 6 3 V 3 3 . C 6 _ P 3 0 @ 6 U 0 P _ U G 7 . 4
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2011/06/02
Deciphered Date
2012/06/02
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET IN FORMATIO N. THIS SH EET MAY NO T BE TRAN SFERED FR OM THE C USTODY OF THE COMP ETENT DIV ISION OF R &D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
SCHEMATIC,MB A7912
Document Number
Friday, January 06, 2012
Rev B
4019ID
Sheet 1
55
of
60
5
4
3
2
Version change list (P.I.R. List) Item
Fixed Issue
1
Page 1 of 2 for PWR Reason for change
Rev.
PG#
Modify List
Date
Phase
1
S3 sequence @ DC
Meet Intel sequence SPEC
49
Change RP91 to 267K
2011 1208
DVT
2
1.5VSDGPU lose
Improve FB pin anit-noise
51
Change RP248 to 2K, PR255 to 1.74K, PR253 to 137K
2011 1208
DVT
3
Cut-in SMT memo
52
Add PC182, PC184
2011 1208
DVT
2011 1212 2011 1217
DVT
2011 1221
DVT
D
Standard design
4 5
7
Change PR138, PR150, PR178, PR194, RP205 , PR235 to 2.2
