CMR INSTITUTE OF TECHNOLOGY No.132, AECS Layout, I.T.P.L. Road, Kundalahalli, Bangalore- 560 037 Ph: 080- 28524466, Extn: 213 (EC Dept. HOD)
A LAB MANUAL ON
ANALOG ELECTRONICS Subject Code: 06ESL37 (As per VTU Syllabus)
PREPARED BY
Staff members - Dept. of E&C
No.132, AECS Layout, I.T.P.L. Road, Kundalahalli, Bangalore- 560 037 Ph: 080- 28524466, Extn: 213 (EC Dept. HOD)
CONTENTS EXPT. NO.
NAME
01
Half wave, full wave and bridge rectifier
01
02
Clamping circuits
10
03
Clipping circuits
16
04
RC coupled amplifier using BJT and FET
23
05
Hartley oscillator / Colpitt’s oscillator
31
06
Crystal oscillator
38
07
RC phase shift oscillator
41
08
Voltage series feedback amplifier using BJT
45
09
Thevenin’s theorem and maximum power transfer theorem
51
10
Series and parallel resonance circuits.
55
11
Darlington emitter follower.
59
12
Class-B push pull power amplifier.
63
13
Bibliography
65
14
Vivo-voce questions
66
OF THE
EXPERIMENT
PAGE NO.
Analog Electronics Laboratory Manual - 06ESL37
Ex.No:01
HALF WAVE, FULL WAVE AND BRIDGE RECTIFIER HALF WAVE RECTIFIER
AIM: To study Half Wave Rectifier and to calculate ripple factor, efficiency and regulation with filter and without filter. COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
1.
Diodes
BY127
2.
Capacitor
0.1µ f , 470µf
3.
Power Resistance Board
4.
Step down Transformer
5.
CRO, Multi ultim meter eter,, Mil Milli lia ammet mmeter er,, Con Conne nec cting ing Boa Boarrd
Qty
1 No. Each 1 No. 1 No.
12 V
1 No.
THEORY: Half wave rectifier circuit consists of resistive load, a diode and source of ac voltage, voltage, all connected connected in series. series. In half wave rectifier rectifier,, rectifyi rectifying ng element element conducts only during positive half cycle of input ac supply. The negative half cycles cycles of ac supply supply are eliminated eliminated from the output. The dc output waveform waveform is expected to be a straight line but the half wave rectifier gives output in the form of positive sinusoidal pulses. Thus the output is called pulsating dc. CIRCUIT DIAGRAM: HALF WAVE RECTIFIER WITHOUT FILTER CAPACITOR Step down Transformer
12V
Ammeter(0-250mA) A
BY127 AC (230V/50HZ)
C2
K
+
A
-
0.1UF
0 RL
V
ODC
VOAC
12V
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Analog Electronics Laboratory Manual - 06ESL37
HALF WAVE RECTIFIER WITH FILTER CAPACITOR
Step down Transformer
Ammeter(0-250mA)
12V
A
+
BY127 AC (230V/50HZ)
C2
K A
-
0
0.1UF
+
RL
VODC
VOAC
C1 470UF -
12V
DESIGN: VIN
rm s
=
12V
VINm
2VINrms
=
VO( DC)
Given
=
Vm / π
=
=
16.97V
5.4V
VO (DC ) IO(DC ) RL
=
=
=
5V
100 10 0mA
VO( DC) / IO( DC)
=
50Ω
Ripple = r = Vo rms / V O DC = 1.21 Design for the filter capacitor Ripple = 1/(4√3 f C R L) Given r = 0.25 C = 1/(4√3 f r R L) RL = 50Ω f = 50Hz = 461.88 F 470 F Efficiency = P DC (I 2DC * RL ) ) / [(Irms)2 * (RL + RF )] DC /P AC V NL −V FL FL
Regulation
% Regulation =
V FL FL
Χ100
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Analog Electronics Laboratory Manual - 06ESL37
PROCEDURE: 1. Connections are are made as shown in in the circuit diagram diagram 2. Switch on the the AC power supply 3. Observe the wave form on CRO across across the load resistor and measure measure the o/p amplitude and frequency. 4. Note down RL, IDC, VODC, VINAC, and V OAC in the tabular column for different
load resistances. 5. Calculate the ripple and efficiency efficiency and Regulation Regulation for each load resistance. resistance. 6. Repeat the above above procedure with filter capacitor. capacitor. TABULAR COLUMN: Sl. No.
R L
IDC
VO (DC)
VIN
VO (AC)
Ripple
Efficiency
Regulation
(AC)
WAVEFORMS: 20 VIN
t 0
- 20
VO
0
Vo (Without Filter)
t
VC
Vo (with filter)
t
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Analog Electronics Laboratory Manual - 06ESL37
FULL WAVE RECTIFIER AIM: To study the full wave rectifier and to calculate ripple factor and efficiency and Regulation with filter and without filter.
COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
1.
Diodes
BY127
2.
Capacitor
0.1µ f , 470µf
3.
Power Resistance Board
4.
Step down Transformer
5.
CRO, CRO, Mult Multim imet eter er,, Mi Mill llia iamm mmet eter er,, Conn Connec ecti ting ng Bo Boar ard d
Qty
2 Nos. Each 1 No. 1 No.
12 V
1 No.
THEORY: The cente centerr tapp tapped ed full full wave wave rectif rectifier ier circu circuit it is simila similarr to a half half wave wave rectifier circuit, using two diodes and a center tapped transformer. Both the input half cycles are converted into unidirectional unidirectional pulsating DC. CIRCUIT DIAGRAM: FULL WAVE RECTIFIER WITHOUT FILTER CAPACITOR Step down Transformer
Ammeter(0-250mA)
12V
A
BY127 AC (230V/50HZ)
C2
K
+
A
-
0.1UF
0 RL A
VO(DC)
VO (AC)
K
12V
BY127
FULL WAVE RECTIFIER WITH FILTER CAPACITOR Step down Transformer
Ammeter(0-250mA)
12V
A
BY127 AC (230V/50HZ)
C2
K
+
A
-
0
0.1UF
+
RL
VO(DC)
VO(AC)
C1 A
12V
K
470UF -
BY127
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Analog Electronics Laboratory Manual - 06ESL37
DESIGN: Vin rms = 12V Vin m = √ 2Vin rms = 16.97V VO DC = 2Vm/π = 10.8V Given
VO DC = 10V IO DC = 100mA RL = VO DC / IO DC = 100Ω
Ripple = r = Vo rms / V O DC = 0.48 Design for the filter capacitor Ripple = 1/(4√3 f C R L) Given r = .06 C = 1/(4√3 f r R L) RL = 100Ω f = 50Hz = 470UF Efficiency
(I 2DC * RL ) ) / [(Irms)2 * (RL + RF )]
= PDC /PAC V NL −V FL FL
Regulation
V FL FL
% Regulation =
Χ100
PROCEDURE: 1. Connections are made made as shown in the circuit diagram 2. Switch on the the AC power supply 3. Observe the wave form on CRO across across the load resistor and measure measure the o/p amplitude and frequency. 4. Note down RL, IDC, VODC
,
Vinac, Vinac, Voac Voac
in the tabular tabular column column for for different different
load resistances. 5. Calculate the ripple and efficiency and regulation regulation for each load resistance. 6. Repeat the above above procedure with filter capacitor. capacitor. TABULAR COLUMN: Sl. No.
R L
IDC
VO (DC)
VIN
VO (AC)
Ripple
Efficiency
Regulation
(AC)
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Analog Electronics Laboratory Manual - 06ESL37
WAVEFORMS:
t VIN
0
-
VO
0
Vo (Without Filter)
t VC
Vo (with filter)
t
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Analog Electronics Laboratory Manual - 06ESL37
BRIDGE RECTIFIER AIM: To study the bridge rectifier and to calculate ripple factor and efficiency and regulation with filter and without filter. COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
1.
Diodes
BY127
2.
Capacitor
0.1µ f , 470µf
3.
Power Resistance Board
4.
Step down Transformer
5.
CRO, CRO, Mult Multim imet eter er,, Mi Mill llia iamm mmet eter er,, Conn Connec ecti ting ng Bo Boar ard d
Qty
4 Nos. Each 1 No. 1 No.
12 V
1 No.
THEORY: The bridge rectifier circuit is essentially a full wave rectifier circuit, using four diodes, forming the four arms of an electrical bridge. To one diagonal of the bridge, the ac voltage is applied through a transformer and the rectified dc voltage is taken from the other diagonal of the bridge. The main advantage of this circuit is that it does not require a center tap on the secondary winding of the transformer; ac voltage can be directly applied to the bridge. The bridge rectifier circuit is mainly used as a power rectifier circuit for converting ac power to dc power, and a rectifying system in rectifier type ac meters, such as ac voltmeter in which the ac voltage under measurement is first converted into dc and measured with conventional meter. CIRCUIT DIAGRAM: BRIDGE RECTIFIER WITHOUT FILTER CAPACITOR Step down Transformer
Ammeter(0-250mA)
BRIDGE
12V
+
1
AC (230V/50HZ)
0
2 -
A
C2
-
0.1UF
+ 4
RL
Vo
3
12V
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Analog Electronics Laboratory Manual - 06ESL37
BRIDGE RECTIFIER WITH FILTER CAPACITOR S te p d o w n T r a n s fo r m e r
A m m e te r ( 0 - 2 5 0 m A )
B R ID G E
12V
+
1
A C (2 3 0 V / 5 0 H Z )
0
2
-
A
C 2
-
0 .1 U F
+ 4 +
-
R L C 1
Vo
470UF
3
12V
DESIGN: Vin rms = 12V Vin m = √ 2Vin rms = 16.97V VO DC = 2Vm/π = 10.8V Given
VO DC = 10V IO DC = 100mA RL = VO DC / IO DC = 100Ω
Ripple = r = Vo rms / V O DC = 0.48 Design for the filter capacitor Ripple = 1/(4√3 f C R L) Given r = .06 C = 1/(4√3 f r R L) RL = 100Ω f = 50Hz = 470UF Efficiency
η = PDC /PAC = (I2DC * RL) / [(Irms)2 * (RL + RF)] V NL −V FL FL
Regulation
% Regulation =
V FL FL
Χ100
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Analog Electronics Laboratory Manual - 06ESL37
PROCEDURE: 1. Connectio Connections ns are made made as shown shown in the circuit circuit diagra diagram m 2. Switc Switch h on the the AC powe powerr suppl supply y 3. Observe Observe the wave wave form on CRO acros across s the load resistor resistor and and measure measure the o/p amplitude and frequency. 4.
Note down RL, IDC, VODC , Vinac, Vinac, Voac Voac load resistances.
in the tabular tabular column column for for different different
5. Calc Calcul ulat ate e the the rip ripple ple fact factor or,, effi effici cien ency cy and and reg regulat ulatio ion n for for ea each ch load load resistance. 6. Repeat Repeat the above above proced procedure ure with with filter capac capacitor. itor. TABULAR COLUMN: Sl. No.
R L
IDC
VO (DC)
VIN
VO (AC)
Ripple
Efficiency
Regulation
(AC)
WAVEFORMS: Vin 20
t 0
- 20
Vo 0
Vo (Without Filter)
t
Vo (with filter) VC
t RESULT:
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Analog Electronics Laboratory Manual - 06ESL37
Ex.No:02
CLAMPING CIRCUITS
AIM: Design a clamping circuit for the given output. COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
Qty
1.
Diodes
BY127
1 No
2.
Capacitors
0.1 µ F
1 No
Signal generator, Cathode Ray Oscilloscope (CRO) with Probes, Dual Power Supply, Connecting Board THEORY: A clamper is one, which provides a D.C shift to the input signal. The D.C shift can be positive or negative. The clamper with positive D.C shift is called positive positive clamper and clamper clamper with negative negative shift is called called negative negative clamper. clamper. Consider a clamper circuit shown below. 0
. 1
u
-
+
C
D
1
Y
1
V i n
V o B
2
7
In the positive half cycle as the diode is forward biased the capacitor charges to the value ( VIN − VD ) with the polarity as shown in the figure. In the negative half cycle the diode is reverse biased. Hence the output is VO
=
VIN
−
Init Initia iall lly y let let us assu assume me that that the the capa capaci cito torr has has char charge ged d to
VC .
( VIN
− VD
)
i.e. (5 – 0.5) = 4.5V Then in the positive half cycle diode is forward biased and applying KVL to the loop,
∴ Vin –VC –V0 = 0 When Vin = 0
V0 =Vin –VC
V0 = 0 - 4.5 = - 4.5V
Vin = 5V
V0 = 5 – 4.5 = 0.5V
In the negative half cycle When Vin = -5V
V0 = -5 – 4.5 = -9.5V
The output shifts between 0.5V and – 9.5V.Here the output has shifted down by 4.5V The peak to peak voltage at the output of a clamper is the same as that of the input.
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CIRCUIT DIAGRAM AND DESIGN: Given Vin = 10V (p-p) A] In the positive half cycle: Diode is forward biased. Applying KVL to loop 1 Vin – VC – VD = 0 0
. 1
u
VC = Vin – VD -
+
= 5 - 0.5 ⇒ 4.5V
C
D
1
Y
1
V i n
In the negative half cycle:
V o B
2
7
Vin – VC – V0 = 0 V0 = Vin – VC When Vin = 0 When Vin = 5V
V0 = - 4.5V V0 =
0.5V
When Vin = -5V V0 = -9.5V B]In the negative half cycle: Diode is forward biased
0
Applying KVL to loop 1
C V i n
u
+
-
Vin + VC + VD = 0
. 1
B
Y
1
2 D
7 1 V o
VC = - ( Vin + VD) VC = - (-5 + 0.5) = 4.5V In the positive half cycle: Diode is reverse biased. Apply KVL to the loop Vin + VC – V0 = 0 V0 = Vin + VC When Vin = 0
V0 = 4.5V
When Vin = 5V
V0 = 5 + 4.5 = 9.5V
When Vin = - 5V
V0 = - 0.5V
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C] Assume VR = 2V In the positive half cycle: Diode is forward biased. Apply KVL to loop 1 Vin – VC – VD – VR = 0 VC = Vin – VD – VR
0.1u
= 5 - 0.5 – 2
-
+
C
= 2.5V
D1 BY127
Vin
Vo
In the negative half cycle:
VR
Diode is reverse biased Vin – VC – V0 = 0 V0 = Vin – VC When Vin = 0V
V0 = - 2.5V
When Vin = 5V
V0 = 2.5V
When Vin = -5V
V0 = -7.5V
D] Assume VR = 2V In the positive half cycle: cycle :
0.1u
Diode is forward biased and the capacitor charges.
-
+
C
Apply KVL to loop 1
D1 BY127
Vin
Vin – VC – VD + VR = 0
Vo VR
VC = Vin – VD + VR = 5 –0.5 +2 = 6.5V In the negative half cycle: Vin – VC – V0 = 0 V0 = Vin – VC When Vin = 0V
V0 = - 6.5V
When Vin = 5V
V0 = - 1.5V
When Vin = -5V
V0 = - 11.5V
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E]In the negative half cycle: Assume VR = 2V Diode is forward biased and capacitor charges. Apply KVL to the loop1 Vin + VC + VD + VR = 0 0.1u
VC = - ( Vin + VR + VD)
+
-
= - (- 5 + 0.5 + 2)
C
= 2.5V
BY127
D1
Vin
Vo
From the fig. we see that
VR
Vin + VC – V0 = 0 V0 = Vin + VC When Vin = 0
V0 = 2.5V
When Vin = 5V
V0 = 7.5V
When Vin = -5V
V0 = -2.5V
F] VR = 2V 0.1u
In the negative half cycle:
+
-
C
Diode is forward biased and capacitor charges.
BY127
D1
Vin
Apply KVL to loop 1
Vo VR
Vin + VC + VD - VR =0 VC = - ( Vin + VD - VR) = - (- 5 + 0.5 – 2) = 6.5V From the circuit we see that, Vin + VC - V0 =0 V0 = Vin – VC When Vin =0V
V0=6.5V
When Vin = 5V
V0= 11.5V
When Vin = - 5V
V0= 1.5V
PROCEDURE: 1. Rig up the circuit as shown in the circuit diagram. 2. Give a sinusoidal input of 10V peak to peak 3. Check and verify the output.
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WAVEFORMS: Vin 5V
0
t
- 5V
V0 0.5 0
t
[A] - 4.5 - 9.5
V0 9.5
4.5
[B] -
0 0.5
t
V0 2.5 0
[C]
t - 2.5
- 7.5
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V0
[D]
0 - 1.5
t
- 6.5
- 11.5
V0 7.5
2.5
[E]
0
t
- 2.5
V0 11.5
6.5
[F] 1.5 0
t
RESULT:
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Analog Electronics Laboratory Manual - 06ESL37
Ex.No:03
CLIPPING CIRCUITS
AIM: Design a clipping circuit for the given values. COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
Qty
1.
Diodes
BY127
1 No
2.
Resistors
10 KΩ
1 No
THEORY: The process by which the shape of a signal is changed by passing the signal signal throug through h a networ network k consis consistin ting g of linear linear elemen elements ts is called called linear linear wave wave shaping. Most commonly used wave shaping circuit is clipper. Clipping circuits are those, which cut off the unwanted portion of the waveform or signal without distor distortin ting g the remain remaining ing part part of the signal signal.. There There are are two types types of clipp clippers ers name namely ly para parall llel el and and seri series es.. A seri series es clip clippe perr is on one e in whic which h the the diod diode e is connected in series with the load and a parallel clipper is one in which the diode is connected in parallel with the load.
CIRCUIT DIAGRAM AND DESIGN: Assume Vin = 10V (Peak to Peak) (a)Consider the circuit in fig. 1
D
( a )
V i n
B
1 Y
1
2
7 1
In the positive half cycle D is forward biased
0
kV o
0
kV o
∴ V0 = Vin – 0.5 = 5 – 0.5 = 4.5 (0.5V is the diode drop) In the negative half cycle D is reverse biased
∴ V0 = 0V (b)Consider the circuit in fig. 2
D
1
In the positive half cycle D is reverse biased
∴ V0 = 0V
B V i n
Y
1
2
7 1
In the negative half cycle D is forward biased Applying KVL to the loop
∴ Vin + VD – V0 = 0 ∴ V0 = Vin + VD = -5 + 0.5 = - 4.5V
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(c) Consider the circuit circuit in fig. 3 Given VR = 2.5V In the positive half cycle (i) When |Vin| > |VD + VR|, D is forward biased Applying KVL, we get Vin = VD + VR + V0 V0 = Vin – VD – VR
D
1
B
Y
V
1
2
R
7
V i n
1
0
kV o
1
0
kV o
V0 = 5 – 0.5 – 2.5 V0 = 2V (ii) When |Vin| < |VD + VR|, D is reverse biased V0 = 0V In the negative half cycle, cycle , D is reverse biased V0 = 0V (d)Consider the circuit in fig. 4 Assume VR = 3V In the positive half cycle, cycle, D is reverse biased V0 = 0V In the negative half cycle (i) When |Vin| > |VD + VR|, D is forward biased Applying KVL, we get
D
Vin = - VD - VR + V0 V0 = Vin + VD + VR
B
1 Y
V
1
2
R
7
V i n
V0 = -5 + 0.5 + 3 V0 = -1.5V (ii) When |Vin < |VD + VR|, D is reverse biased V0 = 0V
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Analog Electronics Laboratory Manual - 06ESL37
(e)Consider the circuit in fig. 5 Assume VR1 = 2.5V and V R2 = 3V In the positive half cycle, cycle, D2 is reverse biased (i) When |Vin| > |VD1 + VR1|, D1 is forward biased Applying KVL, we get Vin = VD1 + VR1 + V0
B
Y
1
B
Y
D 1 1 22 7
D
2
2
7 V
R
2
R
1
V0 = Vin - VD1 - VR1 V0 = 5 - 0.5 – 2.5
V i n
V0 = 2V
V
1
0
k V o
1
(ii) When |Vin < |VD1 + VR1|, D1 is reverse biased V0 = 0V In the negative half cycle (i) When |Vin| > |VD2 + VR2|, D2 is forward biased Applying KVL, we get Vin = - VD - VR + V0 V0 = Vin + VD2 + VR2 V0 = -5 + 0.5 + 3 V0 = -1.5V (ii) When |Vin < |VD2 + VR2|, D2 is reverse biased V0 = 0V (f) Consider Consider the the circuit circuit in fig. fig. 6 During the positive half cycle, cycle , D is forward biased V0 = VD = 0.5V During negative half cycle, cycle, D is reverse biased
1
0
k
B V i n
D
Y
1 1
2 V o
V0 = Vin
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(g)Consider the circuit in fig. 7 During positive half cycle,
1
0
k
D is reverse biased V0 = Vin
V i n
D B
Y
1
1 7
2
V o
During negative half cycle, D is forward biased V0 = -VD = -0.5V (h)Consider the circuit in fig. 8 During positive half cycle
1
0
k
(i) When |Vin| > |VD + VR|,
D is forward biased
B
Y
D 2
1
1 7
V i n
V o
V0 = VD + VR = 0.5 + 2.5
V
R
V0 = 3V (ii) When |Vin| < |VD + VR|, D is reverse biased V0 = Vin During negative half cycle, D is reverse biased V0 = Vin (i)Consider the circuit in fig. 9 Assume VR = 2.5V During positive half cycle,
1
0
k
D is reverse biased V0 = Vin
D B
Y
1 1 2
V i n
During negative half cycle (i) When |Vin| > |VD + VR|,
+
7 V o
V
R -
D is forward biased Applying KVL to the loop, we get V0 = -VD - VR = - 0.5 - 2.5 V0 = -3V (ii) When |Vin| < |VD + VR|, D is reverse biased V0 = Vin During negative half cycle, D is reverse biased V0 = Vin
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(j) Consider the circuit in fig. 10 Assume VR1 = VR2 = 2.5V During positive half cycle, D 2 is reverse biased. (i) When |Vin| > |VD1 + VR1|, D1 is forward biased V0 = VD1 + VR1 = 0.5 + 2.5 V0 = 3V
1
0
k
(ii) When |Vin| < |VD1 + VR1|,
D
D1 is reverse biased V0 = Vin
B
Y
1 2
1
D 7
2 B
V i n
Y
1
2
7
V o V
During negative half cycle,
R
1
V
R
V o
2
1
D1 is reverse biased (i)When |Vin| > |VD2 + VR2|, D2 is forward biased Applying KVL to the loop, we get V0 = -VD2 - VR2 = -0.5 - 2.5 V0 = -3V (ii) When |Vin| < |VD2 + VR2|, D2 is reverse biased V0 = Vin (k) Consider the circuit in fig. 11
10k
Assume VR1 = 3.5V and V R2 = 2V During positive half cycle (i) When |Vin| > |VD1 + VR1|
D1
Vin
BY127
VR1
D1 is forward biased and
D2 BY127 Vo
VR2
D2 is reverse biased V0 = VD1 + VR1 = 0.5 + 3.5
=4V
(ii) When |Vin| < |VR2 – VD2| D1 is reverse biased and D2 is forward biased V0 = -VD2 + VR2 = - 0.5 + 2 ⇒ 1.5V During negative half cycle, D1 is reverse biased and D2 is forward biased V0 = -VD2 + VR2 = - 0.5 + 2 ⇒ V0 = 1.5V PROCEDURE: 1. Rig up the the circuit circuit as shown shown in the the fig. fig. 2. Give a sinus sinusoida oidall input input of 10V peak to to peak. peak. 3. Check Check the output output at the output output terminal. terminal. 4. To plot the transfer transfer characteristics, characteristics, connect channel channel 1 of of the CRO CRO to the output and channel 2 to the input and press the XY knob 5. Adjust Adjust the ground grounds s of both the the channels channels to the centre centre.. 6. Measure Measure the designed designed values. values.
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Analog Electronics Laboratory Manual - 06ESL37
WAVEFORMS: Series Clipper Vin 5 3 0
t
- 3.5 -5 Vo
Vo
4.5 Vin
(a)
0
t Vo
Vo (b) 0
t
Vin
- 4.5 Vo
2.0 (c) 0
Vin
t
3
Vo
-3.5
(d)
0
Vin
t
-1.5
Vo
-3.5
2 (e)
0
t
Vin 3
-1.5
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Shunt Clipper
Vin +5 0
t
+5 Vo
(f)
0.5
t
Vin
0.5
-5 Vo
4.5
(g)
0
t
0.5
Vin
Vo
VO 3
3.0
(h)
t
Vin
-5
Vo
+5 (i)
0
t
-3.0 Vin
-3
Vo
+3 (j)
0
Vin
t
3.0
-3 Vo
+4 1.5 (k)
0
t
Vin
RESULT: Department of Electronics & Communication Engg. – CMRIT
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Analog Electronics Laboratory Manual - 06ESL37
Ex.No:04
RC COUPLED AMPLIFIER - BJT
AIM: Design an RC coupled single stage BJT amplifier and determine its gain and frequency response, input and output impedances. COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
Qty
1.
Transistor
SL100
1 No
2.
Capacitors
0.1 µ f , 47µf
Each 1 No
3.
Resistors
22KΩ , 4.7KΩ , 1.2KΩ , 330Ω
Each 1 No
DC Supply, Signal Generator, CRO with Probe
Vcc = 12 v
CIRCUIT DIAGRAM:
Rc
R1
Cc
1.2 K 22K
Vo
CB 0.1
Vs
~
0.1
B
f
f
SL100
4.7K
CE
330
R
RE
2
47
f
0 To Find Input Impedance DRB
I/P
RC COUPLED AMPLIFIER
VOUT
To Find the Output Impedance
I/P
RC COUPLED AMPLIFIER
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D R B
VOUT
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Analog Electronics Laboratory Manual - 06ESL37
DESIGN: Given VCC = 12V, I C = 4mA, β = 100. R E: W.K.T. VRE = VCC / 10 = 12 / 10 = 1.2V ------for biasing IE ≈ IC = 4 mA From the fig. We see that, IERE = VRE RE = 1.2 / (4 x 10 -3 ) = 300Ω Therefore R E
330
R C: VCE = VCC / 2 = 6V ----- for Q point to be in active region. Applying KVL to output loop VCC –ICRC-VCE -VRE = 0 12 – 4 x 10 -3 RC – 6 -1.2 = 0 Therefore R C = 1.2k R 1 & R 2: From biasing circuit VB = VBE+ VRE = 0.7 + 1.2 VB = 1.9V Assume 10 I B flows through R1 and 9 I B flows through R2. W.K.T. IC = β IB 4 x 10 -3 = 100 IB Therefore IB = 40 µ A From the fig. we see that, R1 = VCC – VB / 10 IB = 12 – 1.9 / (10 x 40 x 10 -6 ) = 25.25k Ω Therefore R1
22k
R 2 = VB / 9IB = 1.9 / ( 9 x 40 x 10-6 ) = 5.28k Therefore R 2
4.7k
CE, CC, CB : Let CB = CC = 0.1µ F XCE = R /10 /10 E Therefore f = 10 / (2 π CE RE) Let f = 100Hz and W.K.T R E = 330Ω Therefore CE = 10 / 2 π f.RE = 48µ F Therefore CE
47
F.
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Analog Electronics Laboratory Manual - 06ESL37
PROCEDURE: 1) To find find Q point point:: Connect the circuit without Vs and capacitors. Set Vcc= 12V. Measure dc voltages at the base V B, collector Vc and V E with respect to ground Determine VCE = VC – VE = --------- V IC = (VCC-VC)/RC = -------- mA Q point is Q(VCE,IC) To check biasing conditions: With VCC=12V; VCE should be VCC /2 /2 = 6V VRE should be VCC /10 /10 = 1.2V VBE = 0.6V 2) Connect Connect the the circui circuitt of Fig(1) Fig(1) 3) Feed Feed a sine sine wave wave of peak peak to peak peak ampli amplitu tude de abou aboutt 40Mv 40Mv from from signa signall generator. 4)
Vary Va ry the input input sine sine wave frequen frequency cy from 10Hz 10Hz
to 1MHz in steps steps and
measure the output voltage V O of the amplifier. Input voltage Vi should remain constant throughout the frequency range. 5) Tabul Tabulat ate e the resu results lts.. 6) Plo Plott the graph graph of frequ frequenc ency y f versus versus Gain in dB and determ determine ine the GBW product Procedure to measure input impedance Zi: 1) Connect Connect the the circui circuitt of Fig(2). Fig(2). 2) Set the follow following ing:: DRB to zero. Input sine wave amplitude of 40Mv Input sine wave frequency to any mid band frequency. 3) Me Meas asur ure e VopVop-p. p. 4) Increase Increase DRB till VO = Vop-p/2. Vop-p/2. The correspond corresponding ing DRB value value gives the input impedance Zi. Procedure to measure output impedance: 1) Conne Connect ct as as in Fig(3) Fig(3).. 2) Set the follow following ing:: DRB to maximum value. Input sine wave amplitude to 40mv. Input sine wave frequency to any mid band frequency 3) Me Meas asur ure e VopVop-p. p. Department of Electronics & Communication Engg. – CMRIT
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Analog Electronics Laboratory Manual - 06ESL37
4) Decrease Decrease DRB till till Vo = Vop-p/2. Vop-p/2. The The correspondi corresponding ng DRB value value gives the output impedance Zo.
WAVEFORM: Vin
0
t
V0
0
t
OBSERVATION Vi =
Freq. (Hz) 100
---------------- mV
Output Voltage
AV = V0 / Vi
AV (dB) = 20log A V
. . . 1M
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Analog Electronics Laboratory Manual - 06ESL37
FREQUENCY RESPONSE CURVE ( in Semilog )
AV (db)
3db
f 1
f 2
f
Bandwidth = f 2 – f 1 RESULT:
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Analog Electronics Laboratory Manual - 06ESL37
Ex.No:04
RC COUPLED AMPLIFIER – FET
AIM: Design an RC coupled single stage FET amplifier and determine its gain and frequency response, input and output impedances. COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
1.
FET
BFW10
2.
Capacitors
0.37 µ f
Qty 1 No 2 Nos.
100 µf 3.
1 No
2.2 MΩ , 1 KΩ , 330Ω , 10 KΩ
Resistors
Each 1 No
DC Supply, Signal Generator, CRO with Probe CIRCUIT DIAGRAM:
VDD = 12V RD =1 KΩ C2=0.3µf
C1=0.37µf
G S
VINi
Vo
D
RG 2.2MΩ
BFW10
RS 330Ω
CS 100µf
RL
10 K Ω
0 To Determine Input Impedance:
47k
Vin
~
VOLTAGE SERIES FEEDBACK AMPLIFIER WITH / WITHOUT FEEDBACK
Vout
To Determine Output Impedance:
Vin
~
VOLTAGE SERIES FEEDBACK AMPLIFIER WITH / WITHOUT FEEDBACK
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D R B
Vout
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Analog Electronics Laboratory Manual - 06ESL37
DESIGN: Given VDD = 12V, IDss = 10 mA, V GS = - 2V, V P = -6 V For proper biasing: V DD=12 V; V DS = 6 V; VRS = VDD /10 = 1.2V VGS = - 0.7 to -2V To find R D : Applying KVL to the output loop of the circuit ID = IDSS (1-VGS / / VP)2
VDD = VDS + IDRD + VRS 12 = RD (5 x 10-3 ) + 6 + 1.2
= 10x10-3 (1- 2/6)2
RD = 960
= 4.4 mA ≈ 5mA
1k
To find R S : VRS = ISRS RS = VRS /I /IS = 1.2 / 5x10
-3
⇒ 240 Ω ≈ 270Ω
Assume R S = 2 M To find CS : XS = 0.1 Rs = 27 Ω XS = 1/2π f CS Let f = 50 Hz
Therefore CS = 100µf
Let C1 = C2 = C XD = 10 RD = 10KΩ XD = 1/2π f C C
therefore C = 0.318µf
TABULAR COLUMN: Vin = Frequency (Hz)
mV V0 (V)
AV
AV (dB)
10 20 . . . . . 1M
FREQUENCY RESPONSE CURVE ( in Semilog ) Department of Electronics & Communication Engg. – CMRIT
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Analog Electronics Laboratory Manual - 06ESL37
AV (db)
3db
f 1
f 2
f
Bandwidth = f 2 – f 1
WAVEFORM: Vin
0
t
V0
0
t
RESULT:
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Analog Electronics Laboratory Manual - 06ESL37
Ex.No:05
HARTLEY OSCILLATOR / COLPITT’S OSCILLATOR
AIM: AIM: Desi Design gn of Hart Hartle ley/ y/Co Colp lpit itts ts os osci cill llat ator or for for a give given n Radi Radio o freq freque uenc ncy y of f 0 =100 KHz using BJT.
COMPONENTS REQUIRED: Sl. No.
Components Details
1.
Transistor
2.
Capacitors
3.
Resistors
Specification
BC109
1 No
0.1 µ f , 1000 pf
2 No
47µf , 0.0023 µf
Each 1 No
18KΩ , 1.8K Ω , 3.9K Ω , 4700 Ω 1 K Pot
4.
Inductors
Qty
100 µH, 1mH, 5mH
Each 1 No Each 1 No
DC Supply, CRO with Probe
THEORY: THEORY: Oscill Oscillato ators rs are are device devices, s, which which genera generate te osc oscill illat ation ions. s. The frequ frequenc ency y of oscillations depends on the feedback network. Feedback may be of two types namely namely posit positive ive and and negati negative. ve. In positi positive ve feedb feedbac ack, k, the feedb feedback ack signal signal is applied in phase with the input signal thus increasing it. In negative feedback, the feedback signal is applied out of phase with the input thus reducing it. The feedback used in oscillators is positive feedback. The oscillators work on the principle of Barkhausen criteria. This states that for sustained oscillations i)
Loop gain Avβ must be equal to 1.
ii) The phase phase shift shift around around the loop must must be 0 deg deg of 360 deg. deg. Here Av is the gain of the amplifier and β is the attenuation of the feedback network. Consider Consider the feedback feedback network shown shown in the fig (1) below. Assume an amplifier with input signal Vin. The output signal V O will be 180 deg out of phase with Vin. So to get an in phase output, the feedback network provides 180-deg phase shift. Therefore the output V f from the feedback network can be made in phase and equal in amplitude to Vin and Vin can be removed. Even then the oscillations continue. Practical oscillations do not need any input signal to start oscillations. They are self-starting due to thermally produced noise in resistors and other components. Only one frequency ( f o) o) of noise satisfies, Barkhausen Barkhausen
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Analog Electronics Laboratory Manual - 06ESL37
criteria and the circuit oscillates with that frequency. The magnitude of f o keeps on increasing each time it goes around the loop. The amplification of fo is limited by circuit’s own non-linearities. Therefore to start oscillations Av β > 1 and to sustain it, the loop gain Av β = 1.
Fig 1. A m p l i f i e r
V i n
V o
A v
B
V f
The feedback network used here consists of L and C. Consider the circuit shown below fig 2. This circuit consists of L and C in parallel. The capacitor stores energy in its electric field whenever there is voltage across it and the inductor stores energy in its magnetic field whenever there is current through it. Initially let us assume that the capacitor has charged to V volts. When S is closed c= 0. When S is closed at t = t 0 , capacitor starts charging through the inductor. Thus a voltage gets built up across the inductor due to the change in current through it. If the capacitor was changed with the polarity as shown in the fig 2 the current starts flowing from the positive plate of the capacitor to the negat negativ4 iv4 plate plate of the capac capacito itor. r. As shown shown the voltag voltage e acros across s the capac capacito itorr reduces during the discharge time v reduces and I increases. At time t1 v will be 0 and I will be maximum as c is fully discharged, the capacitor charges like sinusoidal oscillations. oscillations. Thus the circuit oscillates with the frequency fo = 1/ 2π √ LC S
Fig.2
v
L
t
C
=
+ -
i
The Hartley oscillator consists of two inductors and a capacitor and Colpitts oscillator consists of two capacitors and an inductor.
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Analog Electronics Laboratory Manual - 06ESL37
The resonant frequency fo for Hartley oscillator is fo =1/ 2π √LeqC ------where Leq = L1 + L2.
The resonant frequency fo for Colpitts oscillator is fo = 1/ 2π √ LCeq ------where Ceq = C1C2/(C1 + C2)
CIRCUIT DIAGRAM: HARTLEY OSCILLATOR: Vcc = 9 v Rc
R1
Cc
1.8 K
VO
18K
CB
0.1
f
BC109
0.1
f
Variable 1 K Pot
3.9K 470
R
RE
2
CE 47
L1 = 100 µH
f
L2 = 1mH
GND
C = 0.0023 µ f
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Analog Electronics Laboratory Manual - 06ESL37
COLPITTS OSCILLATOR:
Vcc = 9 v Rc
R1 1.8 K
Cc
VO
18K
CB 0.1
0.1
f
BC109 f
Variable 1 K Pot
3.9K 470
R
RE
2
CE 47
f
C2 = 1000p f
C1 = 1000p f
GND
DESIGN: L = 5mH
Given VCC = 9V, IC = 2mA, β = 50
R E: W.K.T. VRE = VCC / 10 = 9 / 10 = 0.9V ------for biasing IE ≈ IC = 2 mA From the fig. We see that, IERE = VRE RE = 0.9 / (2 x 10 -3 ) = 450Ω Therefore R E
470
R C: VCE = VCC / 2 = 4.5V ----- for Q point point to be in active active region. region. Applying KVL to output loop VCC –ICRC-VCE -VRE = 0 9 – 2 x 10 -3 RC – 4.5 -0.9 = 0 Therefore R C = 1.8k R 1 & R 2: From biasing circuit VB = VBE+ VRE Department of Electronics & Communication Engg. – CMRIT
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Analog Electronics Laboratory Manual - 06ESL37
= 0.7 + 0.9 VB = 1.6V Assume 10 I B flows through R1 and 9 I B flows through R2. W.K.T. IC = β IB 2 x 10 -3 = 50 IB Therefore IB = 40 µ A From the fig. we see that, R1 = VCC – VB / 10 IB = 9 – 1.6 / (10 x 40 x 10 -6 ) = 18.5k Ω Therefore R1
18k
R 2 = VB / 9IB = 1.6 / ( 9 x 40 x 10-6 ) = 4.44k Therefore R 2
3.9k
CE, CC, CB : Let CB = CC = 0.1µ F XCE = RE/10 Therefore f = 10 / (2 π CE RE) Let f = 100Hz and W.K.T R E = 470Ω Therefore CE = 10 / 2 π f.RE = 34µ F Therefore CE
47
F.
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Analog Electronics Laboratory Manual - 06ESL37
HARTLEY OSCILLATOR: Attenuation β = Vf/Vo = IXL1 /IX /IX
L2
= XL1 / X
L2
=
2π foL1/2π foL2 = L1/L2
For sustained oscillations Avβ = 1 -------- Av = 1/β = L2/L1 For oscillations to start Av β > 1 -----------Av
> L2/L1
COLPITTS OSCILLATOR: Attenuation β C1/C2
= Vf / Vo = IX C1 /IX /IXC2 = XC1 / / XC2 = (1/ 2π foC1)/(1/2 π foC2) =
For sustained oscillations Avβ = 1 ---------- Av Av = C1/C2 For oscillations to start Av β > 1----------Av > C1/C2 DESIGN OF TANK CIRCUIT Assume = fo = 100 KHz HARTLEY OSCILLATOR f o = 1/ (2π √LeqC) ------where Leq = L1 + L2.
Assume L1 = 100 µH, L2 =1mH
∴ LEQ = ∴ f O =1/ (2π √2*10-3 C) ∴ C = 0.0023 µ f (Decade capacitance box) COLPITTS OSCILLATOR f O = 1/ (2π √ LCeq ) ------where Ceq = (C1C2)/(C1 + C2)
Assume C1 = C2 = 1000 pF
∴
Ceq =
∴ f O = 1/ 2π √ L * .05*10 - 6 ∴ L = 5 mH (Use decade inductance box)
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Analog Electronics Laboratory Manual - 06ESL37
PROCEDURE: 1.
Rig up the the cir circu cuit it as sho hown wn in the the cir circu cuit it diag diagra ram. m.
Before Before conne connecti cting ng the feedb feedbac ack k networ network, k, check check the circui circuitt for for biasing conditions i.e. check V CE, and VRE.
2.
3.
Afte Afterr con conne nect ctin ing g the the feed feedba back ck netw networ ork. k. Chec Check k the the ou outp tput ut..
4. Check for the sinusoidal waveform at output. Note down the frequency of the output waveform and check for any deviation from the designed value of the frequency. To get a sinusoidal waveform adjust adjust 1K Ω potentiometer.
5.
6. DCB/DIB can be varied to vary the frequency of the output waveform. TABULAR COLUMN HARTLEY OSCILLATOR SL NO
C
fo
COLPITTS OSCILLATOR SL NO
L
fo
WAVEFORM:
Vo
0 t
T
∴ frequency fo = 1/T RESULT:
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Analog Electronics Laboratory Manual - 06ESL37
Ex.No:06
CRYSTAL OSCILLATOR
AIM: AIM: To design a crystal oscillator to oscillate at the specified crystal frequency. COMPONENTS REQUIRED: Sl. No.
Components Details
1.
Transistor
2.
Capacitors
3.
Resistors
Specification
Qty
BC109
1 No
0.1 µ f
2 No
47µf
1 No
18KΩ , 1.8KΩ , 3.9KΩ , 470Ω 1 K Pot
4.
Crystal
2 MHz or 1.8 MHz
Each 1 No 1 No
DC Supply, CRO with Probe CIRCUIT DIAGRAM:
Vcc = 9 v Rc
R1
Cc
1.8 K
VO
18K
CB 0.1
0.1
f
BC109
f
Variable 1 K Pot
3.9K
R
470
RE
2
CE 47
f
2 MHz 1.8 MHz
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Analog Electronics Laboratory Manual - 06ESL37
DESIGN: Given VCC = 9V, IC = 2mA, β = 50
R E: W.K.T. VRE = VCC / 10 = 9 / 10 = 0.9V ------for biasing IE ≈ IC = 2 mA From the fig. We see that, IERE = VRE RE = 0.9 / (2 x 10 -3 ) = 450Ω Therefore R E
470
R C: VCE = VCC / 2 = 4.5V ----- for Q point point to be in active active region. region. Applying KVL to output loop VCC –ICRC-VCE -VRE = 0 9 – 2 x 10 -3 RC – 4.5 -0.9 = 0 Therefore R C = 1.8k R 1 & R 2: From biasing circuit VB = VBE+ VRE = 0.7 + 0.9 VB = 1.6V Assume 10 I B flows through R1 and 9 I B flows through R2. W.K.T. IC = β IB 2 x 10 -3 = 50 IB Therefore IB = 40 µ A From the fig. we see that, R1 = VCC – VB / 10 IB = 9 – 1.6 / (10 x 40 x 10 -6 ) = 18.5k Ω Therefore R1
18k
R 2 = VB / 9IB = 1.6 / ( 9 x 40 x 10-6 ) = 4.44k Therefore R 2
3.9k
CE, CC, CB : Let CB = CC = 0.1µ F XCE = RE/10 Therefore f = 10 / (2 π CE RE) Let f = 100Hz and W.K.T R E = 470Ω Therefore CE = 10 / 2 π f.RE = 34µ F Therefore CE
47
F.
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Analog Electronics Laboratory Manual - 06ESL37
PROCEDURE: 1. Rig up the the cir circu cuit it as sho hown wn in the the cir circu cuit it diag diagra ram. m. Before Before conne connecti cting ng the feedb feedbac ack k networ network, k, check check the circui circuitt for for biasing conditions i.e. check V CE, and VRE.
2.
3.
Afte Afterr con conne nect ctin ing g the the feed feedba back ck netw networ ork. k. Chec Check k the the ou outp tput ut..
4. Check for the sinusoidal waveform at output. Note down the frequency of the output waveform and check for any deviation from the designed value of the frequency. 5.
To get a sinusoidal waveform adjust adjust 1K Ω potentiometer.
WAVEFORM:
Vo
0 t
T
∴ frequency fo = 1/T RESULT:
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Analog Electronics Laboratory Manual - 06ESL37
Ex.No:07
RC PHASE SHIFT OSCILLATOR
AIM: Design a circuit, which generates repetitive waveform (Sinusoidal signal) of frequency 7 KHz. COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
Qty
1.
Transistor
SL100
1 No
2.
Capacitors
0.02 µ f
3 NoS.
0.1 µ f
2 Nos.
47µf 3.
1 No
22KΩ , 4.7KΩ , 1.2KΩ , 330Ω
Resistors
Each 1 No
1 K Pot 470Ω
3 Nos.
DC Supply, CRO with Probe THEORY: THEORY: RC Phase shift oscillator consists of a single transistor amplifier and a RCphase shift network. The Phase shift network consists of three RC sections. Here a fraction of the output of the amplifier is passed through a phase shift network before feeding back to the input. The phase shift in each section is 60 0 so that the total phase shift is 180 0.Another 1800 phase shift is provided by the transistor amplifier amplifier and therefore therefore the total phase phase shift of the the oscillator is 360 360
0
.The frequency frequency of oscillations is given by by fo
= 1 / [2π √ 6(RC)]
Let us consider a RC circuit.. Let I be the current flowing through both R and C. Then using I as the reference vector,Vo vector,Vo is in phase phase with I while Vc ,the voltage across across the capacitor capacitor is 900 behind as shown in the figure. Vi is the sum of Vo and Vc.Hence Vc is θ degrees ahead of Vi and represents a phase shift of θ degrees Vo = IR,
Vc =IXc
Tan θ =Vc/Vo =Ixc/IR = Xc/R = 1/(2 Therefore f = 1/(2
fCR Tan fCR Tan
fCR)
)
If there are 3 sections each each must give give approximately approximately 600 i.e.
= 600
Tan
= 3 =1.73
f= 1/(2
CR 3)
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Analog Electronics Laboratory Manual - 06ESL37
The above phase discussion ignored the additional current I that flows thro throug ugh h C for for othe otherr sect sectio ions ns,, so that that Vc is actu actual ally ly larg larger er than than the the valu value e indicated,which indicated,which means f is smaller. More accurately f = 1/ 1 /2π √ 6(RC)
CIRCUIT DIAGRAM: VCC(12V)
RC=1.2K R1=22K CC=0.1µf =0.1µf 2
Cc
D
C
A
C
B
C
C
Q1
1
SL100
0.1u
0.02µ f
0.02µ f
0.02µ f R
470Ω
R
470Ω
R
470Ω
3
R2=4.7 K
1k
RE=330Ω
CE=47µ f
DESIGN: Given VCC = 12V, IC = 4mA, β = 100. R E: W.K.T. VRE = VCC / 10 = 12 / 10 = 1.2V ------for biasing IE ≈ IC = 4 mA From the fig. We see that, IERE = VRE RE = 1.2 / (4 x 10 -3 ) = 300Ω Therefore R E
330
R C: VCE = VCC / 2 = 6V ----- for Q point to be in active region. Applying KVL to output loop VCC –ICRC-VCE -VRE = 0 12 – 4 x 10 -3 RC – 6 -1.2 = 0 Therefore R C = 1.2k R 1 & R 2: From biasing circuit VB = VBE+ VRE = 0.7 + 1.2 Department of Electronics & Communication Engg. – CMRIT
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Analog Electronics Laboratory Manual - 06ESL37
VB = 1.9V Assume 10 I B flows through R1 and 9 I B flows through R2. W.K.T. IC = β IB 4 x 10 -3 = 100 IB Therefore IB = 40 µ A From the fig. we see that, R1 = VCC – VB / 10 IB = 12 – 1.9 / (10 x 40 x 10 -6 ) = 25.25k Ω Therefore R1
22k
R 2 = VB / 9IB = 1.9 / ( 9 x 40 x 10-6 ) = 5.28k Therefore R 2
4.7k
CE, CC, CB : Let CB = CC = 0.1µ F XCE = RE/10 Therefore f = 10 / (2 π CE RE) Let f = 100Hz and W.K.T R E = 330Ω Therefore CE = 10 / 2 π f.RE = 48µ F Therefore CE
47
F.
DESIGN OF TANK CIRCUIT: We know that f=1/(2π RC√6) Given f O = 7 KHz Assume C = 0.02
F
R = 1/(2π x 0.02 x 10 -6 x 7 x 10 +3 x √6) =527
470
PROCEDURE: 1.
Make Ma ke the the c con onne nect ctio ions ns as show shown n in in the the circ circui uitt dia diagr gram am..
2.
Check th the ci circuit fo for bi biasing.
3.
Adjust ust the the 1k potent tentiiomet ometer er to get get sinus inusoi oid dal wavefo veform rm at the the
output. 4.
To measure th the phase sh shift
Method 1: Connect the channel 1 of the CRO to point D and channel 2 to point A. We will get two sine waves with a phase difference difference Measure the difference by converting the time into angle.
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Analog Electronics Laboratory Manual - 06ESL37
Method 2: a] Connect channel 1 to point D and channel 2 to point A. Press the XY knob and measure the phase shift.
θ =Sin-1 (a/b)
(approx.=60 0)
b a
b] Connect channel 2 to point B the graph is as shown
b a
θ = Sin-1(a/b) Phase angle =1800- θ
(approx. = 120 0)
C] Connect channel 2 to point C The transfer transfer function will will be almost almost a straight straight line and θ =00 and therefore phase angle =180 0 - 00 = 1800
WAVEFORM:
0
t
f=1/T
RESULT: Department of Electronics & Communication Engg. – CMRIT
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Analog Electronics Laboratory Manual - 06ESL37
Ex.No:08
VOLTAGE SERIES FEEDBACK AMPLIFIER USING BJT
AIM: To design and test a two stage voltage series feedback amplifier using BJT and to determine gain, frequency response, input and output impedance with and without feedback. COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
Qty
1.
Transistor
SL100
2 Nos.
2.
Capacitors
0.47 µ f
3 Nos
10µf
2 Nos
3.
Resistors
4.
Variable Resistor
12KΩ , 2.7KΩ , 2.2KΩ , 560Ω
Each 2 No
4.7 KΩ , 100 Ω
Each 1 No
1K Pot
1 No.
DC Supply, Signal Generator, CRO with Probe THEORY: The high gain amplifier is widely used in analog circuit design and will serve serve as the step to the next higher higher level of comple complex x analog analog systems systems.. The The philosophy behind the high gain amplifier is based on the concept of feedback. In analo analog g circui circuits ts we must must be able able to preci precisel sely y define define transf transfer er functi function. on. A familiar representation representation of this concept is illustrated in the block diagram below:
Σ
xs
+
xi
A
x0
_
xf
Here x
voltage or current
A
High Gain Amplifier
β
β
Feedback Network
xs
Input signal (source)
xi
Input signal to amplifier
xf
Feedback signal
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Analog Electronics Laboratory Manual - 06ESL37
The overall gain of the amplifier with feedback is given by Af = x0 / xs = A / (1 + A β ) The high gain amplifier is defined by A = x0 / xi The gains defined above may be current gain or voltage gain. In the circuit shown below, the feedback signal is the voltage V f across R1 and the sampled signal is the output voltage V 0 across R. It is called voltage series feedback amplifier because a part of the output voltage is fed back in series with the input. CIRCUIT DIAGRAM: WITHOUT FEEDBACK
Vcc = 12 v
R1 12K 0.47
2.2 K
Rc
12K
R1
Cc
2.2 K
0.47
f
0.47
B
SL100
~
Cc Vo
f
CB
Vs
Rc
f
SL100
2.7K
2.7K 560
R
RE
2
560
CE
R
RE
2
10
WITH FEEDBACK
CE
f
10
f
Vcc = 12 v
R1
2.2 K
12K
Rc
12K
R1
Cc
2.2 K
Rc Cc Vo
0.47
f
RE
2.7K
Vs
~
CE
R
2
100
SL100 2.7K
R
2
560
RE
CE f
10
RF
Department of Electronics & Communication Engg. – CMRIT
f 10R K
B
SL100
560
0.47
f
0.47
CB
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Analog Electronics Laboratory Manual - 06ESL37
To Determine Input Impedance 47k
Vin
~
VOLTAGE SERIES FEEDBACK AMPLIFIER WITH / WITHOUT FEEDBACK
Vout
To Determine Output Impedance
Vin
VOLTAGE SERIES FEEDBACK AMPLIFIER WITH / WITHOUT FEEDBACK
~
D R B
Vout
DESIGN: Given VCC = 12V, I C = 2mA,
β
= 25.
R E: W.K.T. VRE = VCC / 10 = 12 / 10 = 1.2V ------for biasing IE ≈ IC = 2 mA From the fig. We see that, IERE = VRE RE = 1.2 / (2 x 10 -3 ) R E
560
R C: VCE = VCC / 2 = 6V ----- for Q point to be in active region. Applying KVL to output loop VCC –ICRC-VCE -VRE = 0 12 – 2 x 10 -3 RC – 6 -1.2 = 0 Therefore R C = 2.2k R 1 & R 2: From biasing circuit VB = VBE+ VRE = 0.7 + 1.2 VB = 1.9V Assume 10 I B flows through R1 and 9 I B flows through R2. W.K.T. IC = β IB 2 x 10 -3 = 100 IB Therefore IB = 20 µ A
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From the fig. we see that, R1 = VCC – VB / 10 IB = 12 – 1.9 / (10 x 20 x 10 -6 ) Therefore R1
12k
R 2 = VB / 9IB = 1.9 / ( 9 x 20 x 10-6 ) R 2
2.7k
CE, CC, CB : Let CB = CC = 0.1µ F XCE = RE/10 Therefore f = 10 / (2 π CE RE) Let f = 100Hz and W.K.T R E = 560Ω Therefore CE = 10 / 2 π f.RE = 10µ f Therefore CE
10 f .
DESIGN FEED BACK CIRCUIT Let β = 0.02 β = R / f Rf + R Rf = β R / 1 – β R = 4.7 KΩ
Let
Therefore R f f = 100
PROCEDURE: 1. Rig the circu circuit it as shown shown in the the fig. fig. 2.
Check the circuit for biasing i.e. check V DD, VDS and VRS.
3.
Give a sinusoidal input of 10kHz from signal generator. Adjust the
amplitude of this sine wave such that the output doesn’t get clipped. 4. Observe Observe the the output output wavef waveform orm on on the CRO. CRO. 5. Measure Measure the output output voltage voltage using using AC AC milli voltme voltmeter. ter. 6. Measur Measure e the output output voltag voltage e for differ different ent frequen frequencie cies s of the input input and tabulate the readings as shown in the tabular column. 7. Plo Plott the graph graph of gain vs frequen frequency cy on a semilo semilog g graph graph sheet as shown in the fig. 8.
To measure input impedance connect a resistor of 47k Ω in series
with the signal generator. 9. Measur Measure e the voltag voltage e at the input input point point (VS) (VS) and at the point point after after the resistor (Vin). 10. Current
through
the
resistor
is
given
by
the
expression
I = ( VS – Vin ) / 47k 11. Input impedance is given by Zin = Vin / 47k Department of Electronics & Communication Engg. – CMRIT
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Analog Electronics Laboratory Manual - 06ESL37
12.
To mea meas sure ure out outp put impeda edance nce co connec nnectt a DRB DRB in in pa parallel llel with ith
the output. 13.
Adjust al all the kn knobs of the DR DRB to maximum.
14.
Start re reducing th the re resistance in in th the DR DRB fr from a la large va value
until the output reduces to half. 15.
The re resistance in in th the DR DRB is is th the ou output im impedance.
TABULAR COLUMN: Without Feedback Vin = constant
Frequen cy (Hz)
V0 (V)
AV
AV (dB)
AV
AV (dB)
10 20 . . . . . 1M With Feedback Vin = constant
Frequen cy (Hz)
V0 (V)
10 20 . . . . . . 1M
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EXPECTED GRAPH:
AV
Without feedback With feedback
0
f
WAVEFORM: Vin
0
t
V0
0
t
RESULT:
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Analog Electronics Laboratory Manual - 06ESL37
THEVININ’S THEOREM AND
Ex.No:09
MAXIMUM POWER TRANSFER THEOREM
AIM: AIM: To State and verify the thevenin’s theorem for the given circuit. COMPONENTS REQUIRED: Sl. No.
Components Details
1.
Specification
1 KΩ
Resistors
Qty
4 Nos.
DC Supply, Multimeter, Ammeter (0-10)mA THEORY: THEORY: Any Linear, bilateral network containing energy sources and impedances can be replaced with equivalent circuit consisting of a voltage source in series with an impedance. The Value of voltage source is open circuit voltage between terminals of a network and value of impedance is the impedance measured between the two terminal of a network with all energy energy sources eliminated. eliminated. Circuit diagram: 1 k
R 21
R 1
k
A
+
5 v
R 3 1
-
F I G
1 k
B
1
R 21
R 1
1 k
R L
k
k
A
+
5 v
+
R 3 -
1 k
1
V o
-
F I G
I L
R L
A
k
0 - 1 0
B
2
0-10mA 1k
R1
R2
1k
-
+ 1k
+
A +
R3 -
A
I
5v
+ Vo
-
FIG 3
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-
B
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Analog Electronics Laboratory Manual - 06ESL37
ZTH
+
0-10mA
_
A RL
VTH
Ith
1k
Procedure: 1. Connectio Connection n are made made as shown shown in the fig(2). fig(2). 2.
Supply voltage is adjusted to 5v and the ammeter reading I L is noted down.
3.
Open circuit the terminal A & B , Voltmeter reading Vo is measure which is the thevenin’s voltage. Vo=VTH= ___________Volts .
4. To find the Thevenin’s Thevenin’s impedance, impedance, connections connections are made as as shown in the fig (3) 5. The reading reading of voltmeter voltmeter V and ammeter ammeter I are noted noted . the thevenin’ thevenin’s s Impedance ZTH=V/I W ZTH=_____________ W 6. Thevenin’s equivalent equivalent circuit circuit connection connection are made as as shown in the fig (4) 7.
The supply voltage is set to V th as measured above.
8.
The ammeter reading Ith is noted. If Ith=IL, Thevenin’s theorem is verified.
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(2) MAXIMUM POWER TRANSFER THEOREM: THEOREM : Aim: Aim: (i) To state state and verify verify maximum power transfer transfer theorem. (ii) To determine determine maximum power and the value of RL for Maximum power transfer.
COMPONENTS REQUIRED: Sl. No.
Components Details
1.
Specification
1 KΩ
Resistors
Qty
1 No.
DC Supply, DRB, Multimeter, Ammeter (0-10)mA
Circuit diagram:
1 k R s -
1 0 v
0 - 1 0 m A -
+
A R
+
I
V
1
l 0
k
_
Circuit for measuring source resistance:
1 k R s
-
0 - 1 0 m A + A I s
+ V s _
+
-
1 0 v
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Procedure: 1. Connectio Connection n are made made as shown shown in the fig(i). fig(i). 2.
Supply voltage voltage V is set to 10V, the potentiometer R L is kept at maximum.
3. The readings of voltmeter (V) and ammeter (I) are noted down in the table. 4.
RL is decr decrea ease sed d in step steps s and and at ea each ch step steps s read readin ings gs of V and and I are are tabulated in the table.
5.
A graph of R L versus power is plotted, the maximum power Pmax and value of RL for maximum power transfer are noted from graph P MAX =_______W, R L = .
6. To measure measure source resistance the the connection are made made as shown shown in the fig (2) 7. Supply is set to 10V, the ammeter reading I and voltmeter reading reading are noted down. The source resistance RS=V/I =__________ If RS = RL, MPT Theorem is verified
V (volts)
Power , Watts
I mAmps
P = VI in W
RL= V/I
↑
PMAX
R L, for PMAX
R L, Ω
→
RESULT :
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Analog Electronics Laboratory Manual - 06ESL37
Ex.No: 10
SERIES AND PARALLEL RESONANCE SERIES RESONANCE CIRCUIT
Aim : To obtain the frequency response of an RLC series circuit and hence to determine a) Reson Resonanc ance e freque frequency ncy fo fo b) Band width width ,Upper ,Upper and Lower Lower half half power freque frequency ncy c) Q-f Q-factor tor.
COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
Qty
1.
Resistors
100 Ω
1 No.
2.
Capacitor
0.22µ f
1 No.
3.
Inductor
1 mH
1 No.
Signal generator, Multimeter
Circuit diagram:
L
C R
VO
DESIGN: fo = 1/2π √ LC Let L = 1mH C = 1/4π 2Lfo2 C = 0.22μf R = 100 Ω Find fo
Procedure: 1. Connectio Connections ns are made made as shown shown in the circuit circuit diagra diagram. m. 2. AC Supply Supply is switched switched on. on. oscillator oscillator output voltage voltage is adjusted to about maximum i.e 10V P-P 3. The frequency is gradually varied from zero hertz and for different value of “ f”, voltage is noted down. The results are tabulated in the tabular column. 4. Frequency response i.e a graph graph of frequency versus voltage voltage is drawn.
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5. From the graph , resonant frequency “fo” is noted down down at which which voltage voltage is maximum(Vo). maximum(Vo). 6. Lower half power frequency “f1” and upper half power frequency “f2” are noted corresponding to a voltage of Vo/ √ 2 Band width=f2-f1=_____________ hertz 7. The Q-fac Q-factor tor =fo/f =fo/f2-f 2-f1 1
Tabular column f in hz V in VOLTS
FREQUENCY RESPONSE CURVE ( in Semilog ) VO
VOmax VOmax/√2
BW
0
f 1 f 0
f 2
f , Hz
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PARALLEL RESONANCE CIRCUIT: Aim : To obtain the frequency response of an RLC series circuit and hence to determine a) Reso Resona nanc nce e frequ frequen ency cy fo b) Band width width ,upper and lower lower half half power frequenc frequency y c) Q-factor. or.
COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
Qty
1.
Resistors
100 Ω
1 No.
2.
Capacitor
0.22µ f
1 No.
3.
Inductor
1 mH
1 No.
Signal generator, Multimeter
Circuit diagram:
L
C
R
VO
Frequency response Vo
Vomin x √2
Vomin BW 0
f 1
f O
f 2
f in in Hz
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Procedure:
1. 2.
Connections are made as shown in the circuit diagram. AC Supply is switched on. oscillator output voltage is adjusted to about maximum i.e 10V P-P 3. The frequency is gradually varied from zero hertz and for different value of “ f”, voltage voltage is noted down. The The results are tabulated tabulated in the tabular column. 4. Frequency response i.e a graph of frequency versus voltage is drawn. 5. From the graph , resonant frequency “fo” is noted down at which voltage is minimum (Vo). Lower half power frequency “f1” and upper half power frequency 6. “f2” are noted corresponding to a voltage of V Omin x √2. a. Band width = f 2 - f 1=_____________ Hz 7. The Q-factor =fo/f2-f1
RESULT: RESULT:
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Ex.No:
11
DARLINGTON EMITTER FOLLOWER
AIM: To design design and test a Darlingto Darlington n emitter emitter follower circuit with and without boot strapping and determine the gain, input and output impedance for both the circuits. COMPONENTS REQUIRED: Sl. No.
Components Details
Specification
Qty
1.
Transistor
SL100
2 Nos.
2.
Capacitors
10 µ f
1 No
0.47µf
2 Nos.
3.
Resistors
1 MΩ , 2.2 M Ω , 1.5 KΩ , 10 KΩ , 47KΩ
DC Supply, CRO AC millivoltmeter
with
Probe,
Signal
Each 1 No
generator,
THEORY: Norm Normal ally ly tran transi sist stor ors s are are used used as ampl amplif ifie iers rs.. Bu Butt ther there e are are so some me applications in which, matching of impedance is required between two circuits without any gain or attenuation. In such applications emitter followers are used. Emitte Emitterr follow followers ers have have large large input input impe impedan dance ce and and small small output output impe impedan dance. ce. Darlington emitter follower has two transistors connected in cascade such that the emitter of first transistor is connected to the base of second transistor. The volta voltage ge gain gain of the darli darling ngton ton emitt emitter er follow follower er is clo close se to unity. unity. The major major drawback drawback of this circuit is that the second transistor amplifies leakage current of the first first transi transist stor or and ov overa erall ll leakag leakage e curren currentt become becomes s high. high. The output output is observed at the emitter terminal of the second transistor. Hence it is called an emitter follower.
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CIRCUIT DIAGRAM: Darlington emitter follower without bootstrapping Vcc = 12V
R1
1M
Cb = 0.47µf Q1
QSL100
SL100 R2
2.2 M
Vin CE = 0.47µf RE Vo
1.5 K
Darlington emitter follower with bootstrapping Vcc = 12V
R1
1M
Cb = 0.47µf Q1
QSL100 R3 SL100 Vin CE = 0.47µf R2
RE CE = 0.47µf
Vo
1.5 K
2.2 M
DESIGN: Given IC = 4mA, V CC = 12V, VBE = 0.6V, β
1
=β
2
= 100
To find R E: Applying KVL to the output loop of the second transistor, we get VCC = VCE + VRE Therefore VRE = VCC – VCE = 12 – 6 Therefore VRE = 6V W.K.T RE = VRE / IE2 Here IE2 = IC2 Therefore RE = 6 / 4 x 10 -3 R E = 1.5k Department of Electronics & Communication Engg. – CMRIT
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To find R 1 & R 2: From the circuit we have VA = VBE1 + VBE2 + VRE = 0.6 + 0.6 + 6 = 7.2V W.K.T. IC = β IB Therefore IB = (4 x 10-3)/ 100 = 40 µ A Let 10IB be the current through R1 and 9IB be the current through R2. From the fig. we see that R1 = (VCC – VA) / 10IB Therefore R 1 = 12K From the fig. R2 = VA / 9IB Therefore R 2 = 20 K
22K
W.K.T. CC = 10 / XRE = 10 / ( 2. π .f.RE) Assume f = 50Hz Therefore CC = 21.2
F
47
F
W.K.T. Cb = 10 / X RB = 10 / ( 2.π .f.RB ) Therefore Cb = 4.2 Chose R 3 = 10 K
F
4.7
where RB = R1 || R2 = 7.5kΩ
F
, CB = 10µf 10µf for for bootstrapping
PROCEDURE: 1. Rig up the the circuit circuit as shown shown in the the fig. fig. 2.
Check the circuit for biasing, i.e. check V CE, VCC and VRE.
3. Give a sinusoidal input signal signal of 1KHz from from a signal generator. 4. Se Sett the the inpu inputt sign signal al to a valu value e such such that that the the ou outp tput ut does doesn’ n’tt get get clipped. 5. For differen differentt frequencie frequencies s of the input signal, signal, read read the output output on the voltmeter and verify that the gain is 1. To measure input impedance, connect a resistor of 47k Ω in series with the signal generator. 6.
Measure the voltage at the input point (VS) and at the point after the resistor (VIN). 7.
Current through the I = (VS - VIN) / 47K. 47K. 8.
9.
resistor
Input impedance is given by
is
given
by
the
expression
ZIN = VIN / 47 K
10. To mea meas sure ure out outp put impeda edance, nce, connec nnectt a DRB in in pa parallel llel with with the output. 11.
Adjust al all the kn knobs of the DR DRB to maximum.
12. Start re reducing th the re resistance in in th the DR DRB fr from a la large va value until the output reduces to half.
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13. The re resistance in in th the DR DRB is is th the ou output im impedance. TABULAR COLUMN: VIN = __________ constant Frequency (Hz)
V0 (V)
AV
AV (dB)
WAVEFORM: Vin
Vin
0
t
0
t
V0
Vin
RESULT:
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Ex. Ex.No: 12
TRANSF NSFORMERLE ERLES SS CLAS LASS-B PUS PUSH PUL PULL POWER AMPLIFIER
Aim: Aim: Testing of a transformer less class-B push pull power amplifier and determination of its conversion efficiency. COMPONENTS REQUIRED: Sl. No.
Components Details
1.
Transistor
2.
Diode
3.
Capacitors
4.
Resistors
Specification
Qty
SL100
1 No.
SK100
1 No.
BY127
2 Nos.
47 µ f
2 Nos.
470 µf
1 No.
220Ω
2 No
DRB
1 No
DC Supply, CRO AC millivoltmeter
with
Probe,
Signal
generator,
Theory: In class B operation, to obtain output for the full cycle of signal, it is necessary to use two transistors and have each conduct on opposite half cycle, the combined operation providing a full cycle of output signal. Since one part of the circuit pushes the signal high during one half cycle and the other part pulls the signal low during the other half cycle, the circuit is referred to as a push pull circuit.
Circuit diagram:
VCC
R1 Ci
Q1
SL100 CO
D1 Ci
D2
Vi=50mV
SK100 R2
Q2
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RL VO
10 Ω .
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Analog Electronics Laboratory Manual - 06ESL37
12v
A
0-500µA
SL100
SK100 V
DESIGN: Given Vcc =2.5V; RL= 10 Ω; I DC = 3mA
Po (watts)
To Find R 1 & R 2: Applying KVL at the input circuit; We get ; Vcc = 2VR1 + 1.4 Therefore; VR1 = 0.55V; VR1 =IDCR1 = 0.55V; R1 = 183Ω. Choose; R1 = R2 = 220Ω. To Find Ci : Input coupling capacitor is given by, Xci >Zieff/10 >1.1K/10 Resistance(Ω) Resistance(Ω) Xci > 1/2πfCi ;Ci >28μF; Choose Ci = 47μF To Find CO: Output coupling capacitor is given by, Xco = 10 Xco > 1/2πfCo Co > 318μF; Choose; Co = 470μF 2 Poac=Vo /8R L Pidc=VccIdc Calculate circuit efficiency, η = Po (ac)/Pi(dc) = (π/4)Vo/Vcc = ? Procedure: 1. Connect Connect the circui circuitt as per the circuit circuit diagra diagram. m. 2. Set VI = 3V, using the signal generator. 3. Keeping the input voltage constant, vary the load resistor and note down the readings of the ammeter and peak to peak output voltage. 4. Calculate PDC, PAC and % efficiency η. 5. Draw the the plot plot of resista resistance nce versus versus output output power power..
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Tabulation Vi = RL (Ω )
---------------VO (v)
IDC(mA)
PAC
PDC
%η
Result:
BIBLIOGRAPHY 1.
“Ele “Elect ctro roni nic c devi device ces s and and cir circu cuit it the theor ory” y”,, Robe Robert rt L.B L.Boy oyle lest stad ad and and Louis Nashelsky.
2.
“Int “Integ egra rate ted d elec electr tron onic ics” s”,, Jaco Jacob b Mill Millma man n and and Chri Christ stos os C Halk Halkia ias. s.
3.
“Ele “Elect ctro roni nic c dev devic ices es and and cir circu cuit its” s”,, Dav David id A. Be Bell ll..
4.
“Ele “Elect ctro roni nic c dev devic ices es and and cir circu cuit its” s”,, G.K G.K.M .Mit itta tal. l.
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VIVA-VOCE QUESTIONS What are conductors, insulators, and semi-conductors? Give egs. 2. Name different types of semiconductors. 3. Wha What are are in intrin trins sic s sem emiicond condu uctor ctors s and and ext extri rins nsic ic s sem emiicond condu uctor ctors s? 4. How do do yo you ge get PP-wpe an and NN-type se semiconductors? 5. What is doping? Name differen rent levels els of doping. 6. Name different types of Dopants. . 7. What do you unders erstand by Don onor or and acceptor atoms? 8. Wha What is is th the ot other her nam name e for for p-ty p-type pe and and NN-type ype sem semic icon ondu duc ctors tors? ? 9. What are ma majorit rity carrie riers and minorit rity carrier riers s? 10. What is is tth he ef effect ect o off te temperat rature on on sem semiiconductors? rs? What is drift current?. 11. 12. What is depl epleti etion region or space charge rge regi egion on? ? 13. 13. Wha What is is jun junct ctio ion n pot poten enti tia al or or pot poten enttial ial ba barri rrier in PN PN ju juncti nctioI oI). ).? ? 14. 14. What What is a dio diode de? ? Nam Name e dif diffe fere rent nt type types s of of dio diode des s and and name name its its app appli lica cati tion ons s 15. 15. Wha What is is bia biasi sing ng? ? Na Name diff differ eren entt typ types es w.r. w.r.t. t. Diod Diode e bia biasi sing ng 16. How does a diode behave in its forward and reverse biased conditions? 17. What is static and dyriantic res resistance of of diode ode? 18. 18. Why Why the the curre urrent nt in the the fo~ar o~ard d bi biased ased diod diode e tak takes es expo expone nent ntiial pat path? 19. 19. What What do you you unde unders rsta tand nd 1?y 1?y AvaJ AvaJan anch che e brea breakd kdow own n and and zene zenerr brea breakd kdow own? n? 20 . Why diode is called unidirectional device. 21 . What is PIV of a diode 22 . What is is k kn nee vo voltage or or cu cut-in vo voltage? 23. 23. What What do you you mea mean n by by tra trans nsit itio ion n cap capac acit itan ance ce or spac space e cha charg rge e cap capac acit itor or? ? 24. 24. What What do you you mean mean by diff diffus usio ion n capa capaci cita tanc nce e or stor storag age e capa capaci cita tanc nce? e? 25. What is a transistor? Why is it called so? . 26 . Name di different ty types, of of tr transistors? 27. 27. Name Name diff differ eren entt con conffigur igurat atio ions ns in whi which the the trans ransiistor tor is oper opera ated ted 28. 28. Ment Me ntio ion n the the appl applic icat atio ions ns o off tra trans nsis isto tor. r. Exp Expla lain in how how tra trans nsis isto torr is used used as as s swi witc tch h 29. What is transistor biasing? Why is it neces ecess sary? ry? 30. 30. Wha What are are the the thr three ee diff differ eren entt reg regiion ons s in in whi whic ch the the trans ransis isto torr wor works ks? ? 31. Why trm trmiisistor is is c ca alled cu current ent c co ontrol rolled de device? 32. What is FET? Why it is called so? 33 . What are the parameters ofFET? 34 . What are the characteristics of FET? 35 . Why FE FET is is kn known as as vo voltage co controlled de device? 36 . What a arre th the di differences between BJ BJT and FE FET? 37. 37. Ment Me ntio ion n app appli lica cati tion ons s ofF ofFET ET.. Wha Whatt is is pin pinch ch offv offvQl Qlta tage ge,, VGS VGS(o (ofJ fJ)) and and lDss lDss 38. 38. Wha What is is an an amp ampllifie ifier? r? Wha What is is the the need eed for for an am amplif plifiier circ circui uitt? How do you classify amplifiers? , 39. 40. 40. Wha What is fait faithf hful ul ampl mplifi ificati cation on? ? Ho How w do you achie chieve ve this this? ? 41. What is is co coupling? Na Name di differen rent ty type.s e.s of of co coupling 42 . What is operating po point or quiescent point? 43. What do do y you ou mean by by fre freq quenc ency re respon ons se of of a an n am amplifier? 44. 44. What What are are gai gain, n, Ba Band ndwi widt dth, h, lowe lowerr cut cutof offf fre frequ quen ency cy and and upp upper er cuto cutoff ff freq freque uenc ncy? y? 45. What is is th the fi figure of merit rit of of an am amplifier ci circu rcuit? 46. What are the advantages of RC cou oup pled amplifier? er? 47. Why a 3db point is taken to calculate Ba Ban ndwidth? 48. 48. What What is semi semi-l -log og grap graph h she sheet et? ? Why Why it is used used to plot plot freq freque uenc ncy y res respo pons nse? e? 49 . How do you test a diode, transistor, FET? 50. 50. How Ho w do do you you iden identi tify fy the the ten tenni nina nals ls of Diod Diode, e, Tran Transi sist stor or& & FET FET? ? Men Menti tion on the the typ type e number of the devices used in your lab. 1.
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Analog Electronics Laboratory Manual - 06ESL37
51. 51. Desc Descri ribe be the the oper operat atio ion n ofN ofNPN PN tran transi sist stor or.. Def Defin ine e rev rever erse se satu satura rati tion on cur curre rent nt.. 52. Explain Doping w. w.r.t. Th Three regions of tran ransistor 53. 53. Expl Expla ain the term erms hie/h ie/hib ib,, ho hoel elho hob, b, hre/ re/hrb, hrb, hre/ hre/h hfb. fb. 54. Explain therma rmal ru run-.taway. Ho How it it ca can'be pr prevented. 55. 55. Defin efine e FET FET para parame mete ters rs and writ write e th the rel relation tion betw betwee een n them them.. 56. 56. Wha What are are Dra Draiin Cha Chara rac cteri terist stic ics s and and tran trans sfer fer c cha hara rac cteri terist stic ics? s? 57 . Explain the co construction and wo working of of FET 58 . What is is fe feedback? Na Name di different ty types. 59. 59. What What is the the effe effect ct of nega negati tive ve fee feedb dbac ack k on on the the char charac acte teri rist stic ics s of an ampl amplif ifie ier? r? 60. 60. Why Why comm common on coll collec ecto torr ampl amplif ifie ierr is is know known n as emit emitte terr fol follo lowe werr circ circui uit? t? 61. What is the applicati ation of emitter follower ckt? 62. 62. What What is casc cascad adin ing g and and casc cascod odin ing? g? Why Why do do you you casc cascad ade e the the ampl amplif ifie ierr ckt ckts. s.? ? 63 . How do you determine the value of of capacitor? 64 . Write down the diode cu current equation. 65. 65. Wri Write symbo ymbols ls of vario arious us pass passiv ive e and and activ ctive e compo ompone nen nts 66. 66. How Ho w do do y you ou dete determ rmin ine e th~ th~v value alue of res resistor stor by colou olourr cod code e met metho hod? d? 67. What is tolera erance and power rating of res resistor? 68 . Name different types of resistors. 69 . How do you c1assify resistors? 70 . Name different types of capacitors.. 71 . What a arre cl clipping ci circuits? Cl Classify th them. 72. Mention the applicatio tion of clippin ping circu rcuits. 73 . What are cl clamping ci circuits? Classify th them 74 . What is is tth he ot other na name of of clamping ci circuits? 75. Mention the applicatio tions of clampin ping circu rcuits. 76. 'What is Darlington gton emitter follower wer circu rcuit? 77. 77. Can Can we incr increa ease se the the numb number er of of tra trans nsis isto tors rs in in Dar Darli ling ngto ton n emit emitte terr foll follow ower er cir circu cuit it? ? Justify your answer. 78. 78. What What is the the dif diffe fere rent nt betw betwee een n Dar Darli ling ngto ton n emi emitt tter er foll follow ower er circ circui uitt & Vo Volt ltag age e follower circuit using Op-Amp. Which is better. 79. Name di differen erentt ty types of of Em Emitter follower ci circu rcuits. 80 . What is an Oscillator? Classify them. 81. 81. Wha What ar~ The The Bloc Blocks ks,, whi which fon onns ns an Osc Oscilla illato torr cir circu cuit its? s? 82 . What are da damped & Un-damped Os Oscillations? 83 . What are Barkhausen's criteria? 84. What ty type of of o os scillator ha has go got fr frequency s sttability? 85. 85. Wha What is is th the dis disad adva vant ntag age e of of Ha Hartle rtley y & Colp Colpiiit's it's Oscil scilllator ator? ? 86. Why RC RC ta tank Ci Circuit Os Oscillator is is used fo for AF AF range? 87. Why LC LC ta tank Ci Circu rcuit Os Oscillator is us used fo for RF RF ran range? 88. What ty type of of fe feedback is is us used in Os Oscillator ci circu rcuit? 89. 89. In a Tra Trans nsis isto torr typ type e No. No. SL 100 100 and in Diode ode BY BY 127 127,, wha whatt doe does s SL SL and and BY stands for 90. 90. Clas Classi sify fy Ampl Ampliifier fiers s ba based sed on: on: oper opera ating ting poin pointt selec electtion. ion. 91. What is is tth he ef efficienc ency o off Cl Class B push pu pull am amplifier? er? 92. 92. What What is the the dra drawb wbac ack k of of Cla Class ss B P Pus ush h pul pulll Amp Ampli lifi fier er? ? How How it is elim elimin inat ated ed.. What is the advantage of having complimentary symmetry push pull amplifier? 93. 94. 94. Wha What is is Boo Boots tstr trap appi ping ng? ? Wha Whatt is is the the adva advant ntag age e of of boo boots tstr trap appi ping ng? ? 95. 95. State tate Thev Theven enin in's 's Theo Theore rem m and and Ma Max. x.po powe werr tran transf sfer er theo theore rem. m. 96. What is the figure of merit rit of res resonance circu rcuit? 97 . What is is th the ap application of of re resonant ci circuit? 98 . What is a rectifier? Classify. 99. 99. Wha What is is th the ef effici ficien enc cy of of hal half wa wave and and ful fulll wav wave e rec recti tifi fier er? ? 100. 100. Wha What is is th the adv adva antag ntage e of Bridg ridge e rec recttifie ifierr of of Cen Centr tre e ta tapped pped typ type e FWR FWR Department of Electronics & Communication Engg. – CMRIT
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Analog Electronics Laboratory Manual - 06ESL37
101. 102 . 103 . 104.
105 . 106. 106. 107 . 108. 108. 109.
110. 110. 111 .
What is the disadvanta ntage of Brid ridge rectifier? What is a filter? Name different types of filter ckts. Which type of filter is used in day to day application and why? What is is ri ripple an and ri ripple fa factor? . What What is the the the theor oret etic ical al valu value e of of rip rippl ple e for for Half Half Wave Wave and and .Fu .Full ll wave wave rect rectif ifie ier? r? What is need for rectifier ckts. Why Why a step tep dow down n tra tran nsfor sforme merr is is us used at the the inpu inputt of of Rec Recti tifi fier er ckt. kt. What is TUF? . Wha What is is reg regul ula ation tion w.r. w.r.tt rec recti tifi fier er? ? And And ho how w it it is is ca calcul lculat ated ed? ? What is figure of merit of Rectifier ckt.
Department of Electronics & Communication Engg. – CMRIT
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