04-68283A Manual Digsy Chapter N Table of Operands

Chapter N Table of Operands

Drawing Number: 04 – 68 283000/A Issued: 19.06.02 Stored: 03.04.03 Version: 1.0.0 File name: 04-68283 Manual digsy Chapter N Table of Operands.doc Prepared by: Ralf Neuber

This manual was prepared with great care. The details and data in this document are regularly checked and updated and are at any time subject to change without notice. Nevertheless, INTER CONTROL does not assume liability for the correctness of the details/data in this document, since, despite great effort, mistakes cannot always be completely ruled out. In addition, INTER CONTROL reserves the right to make at any time technical changes to the product, which can also result in deviations from the contents of this document. The document includes information that enjoys protection of copyright. No part of this publication may be reproduced and/or translated into other languages without the prior written permission of INTER CONTROL. Of course, any ideas and suggestions regarding amendments, or notes concerning mistakes in this document are welcome. Please refer to INTER CONTROL.

INTER CONTROL Hermann Köhler Elektrik GmbH & Co. KG Schafhofstraße 30 D-90411 Nürnberg Germany Tel.: Fax: E-mail: Internet:

++49 911 9522-5 ++49 911 9522-857 [email protected] http://www.intercontrol.de

N Table of Operands

Manual digsy®compact

Table of Contents: N

Table of Operands ...................................................................................................................N-3 N.1 Introduction .......................................................................................................................N-3 N.2 Overview of the Operand Areas .......................................................................................N-3 N.3 Input Operands of the digsyâcompact E................................................................................N-4 N.4 Output Operands of the digsyâcompact E.............................................................................N-8 N.5 System Input Operands of the digsyâcompact E ................................................................N-12 N.6 System Output Operands of the digsyâcompact E..............................................................N-15 N.7 Configuration Operands of the digsyâcompact E ................................................................N-16 N.8 Notes...............................................................................................................................N-25

04 – 68 283000/A Version 1.0.0

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N Table of Operands

N


TABLE OF OPERANDS

N.1 Introduction The tables below are listing the inputs or outputs that are assigned to the respective operands required for programming (please refer to the Documentation and Programming system PROSYD1131 Type 4395.20.100).

NOTE:

PROSYD1131 V2.1 SP11 (or versions of a higher level) is to be used at any rate, if the complete flag area is to be addressed, too !

N.2 Overview of the Operand Areas The interface between firmware, application program PROSYD1131 and external processes is a data interface consisting of 1024 input bytes (I-area), 1024 output bytes (Q-area) and 2048 flag bytes (M-area). Since both the firmware and external processes (e.g., CANopen) are accessing these operands, the user should use the predefined operands in the variable control configuration for programming. Inputs (IX, IB, IW) Bytes

Area (read only)

0

Outputs (QX, QB, QW) Bytes

Area (read write)

0

Input variables 191 192

SYSIN 511 512

1023

Bytes

Area (read write)

0

191 192

255 256

Output variables

Flags (MX, MB, MW)

255

Configuration files freely usable for user variables; e.g., CANopen – input variables

SYSOUT

256 511 512

1023

freely usable for user variables; e.g., CANopen-output variables

1023 1024

2047

Figure N.1: Overview of the operand areas

04 – 68 283000/A Version 1.0.0

Page N-3

freely usable for CANopen input / output variables and fixly addressed user data

N Table of Operands


N.3 Input Operands of the digsyâcompact E Input operand as %IW (Word)

%IB (Byte)

Symbol address acc. to

%IX (Bit)

Data structure

Description

on C P U

Adjustable control configuration

I O

Digital Inputs (TDIGININ) 0

In.DigIn.Value[1] (WORD)

0

1

ID1 ID1_1

Digital input 1 of DcS CPU (ID1.1)

X

0.1

ID1_2


X

0.2

ID1_3


X

0.3

ID1_4


X

0.4

ID1_5


X

0.5

ID1_6


X

0.6

ID1_7


X

0.7

ID1_8


X

0.8

ID1_9


X

0.9

ID1_10


X

0.10

ID1_11


X

0.11

ID1_12


X

not used

:

:

0.15

not used In.DigIn.Value[2] (WORD)

2

3

X

0.0

0.12

1

All digital inputs of DcS CPU (ID1.1..ID1.12)

ID2

All digital inputs of DcS I/O (ID2.1..ID2.12)

X

1.0

ID2_1

Digital input 1 of DcS I/O (ID2.1)

X

1.1

ID2_2


X

1.2

ID2_3


X

1.3

ID2_4


X

1.4

ID2_5


X

1.5

ID2_6


X

1.6

ID2_7


X

1.7

ID2_8


X

1.8

ID2_9


X

04 – 68 283000/A Version 1.0.0

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Default Preset

N Table of Operands

Input operand as %IW (Word)

2

%IB (Byte)

%IX (Bit)

Symbol address acc. to Data structure


Description

on C P U


I O

1.9

ID2_10


X

1.10

ID2_11


X

1.11

ID2_12


X

1.12

ID2_13


X

1.13

ID2_14


X

1.14

not used

1.15

not used In.DigIn.Value[3] (WORD)

4

QD2_AS_ID3 QD2_1_AS_ ID3_1 QD2_2_AS_ ID3_2 QD2_3_AS_ ID3_3 QD2_4_AS_ ID3_4 QD2_5_AS_ ID3_5 QD2_6_AS_ ID3_6 QD2_7_AS_ ID3_7 QD2_8_AS_ ID3_8

2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 5

Readback Digital outputs of DcS I/O, configured as Digital inputs (QD2.1..QD2.8) Readback Digital output 1 of DcS I/O, when configured as Digital input (QD2.1) Readback Digital output 2 of DcS I/O, when configured as Digital input (QD2.2) Readback Digital output 3 of DcS I/O, when configured as Digital input (QD2.3) Readback Digital output 4 of DcS I/O, when configured as Digital input (QD2.4) Readback Digital output 5 of DcS I/O, when configured as Digital input (QD2.5) Readback Digital output 6 of DcS I/O, when configured as Digital input (QD2.6) Readback Digital output 7 of DcS I/O, when configured as Digital input (QD2.7) Readback Digital output 8 of DcS I/O when configured as Digital input (QD2.8)

X X X X X X X X X

not used Analog Inputs (TANININ)

3

6

4

8

5

10

6

12

7

14

8

16

9

18

10

20

11

22

12

24

13

26

04 – 68 283000/A Version 1.0.0

In.AnIn.Value[1] (WORD) In.AnIn.Value[2] (WORD) In.AnIn.Value[3] (WORD) In.AnIn.Value[4] (WORD) In.AnIn.Value[5] (WORD) In.AnIn.Value[6] (WORD) In.AnIn.Value[7] (WORD) In.AnIn.Value[8] (WORD) In.AnIn.VQS_ VCP (WORD) In.AnIn.VIMP (WORD) In.AnIn.TEMP (WORD)

IA1_1 IA1_2 IA1_3 IA1_4 IA2_1 IA2_2 IA2_3 IA2_4 VQS_VCP VIMP_CPU TEMP_CPU

Analog input 1 of DcS CPU (IU1.1 or II1.1) Analog input 2 of DcS CPU (IU1.2 or II1.2) Analog input 3 of DcS CPU (IU1.3 or II1.3) Analog input 4 of DcS CPU (IU1.4 or II1.1) Analog input 1 of DcS I/O (IU2.1 or II2.1) Analog input 2 of DcS I/O (IU2.2 or II2.2) Analog input 3 of DcS I/O (IU2.3 or II2.3) Analog input 4 of DcS I/O (IU2.4 or II2.4) Readback of offset voltage VCP of the inputs ID1.9..ID1.12 on the DcS CPU [mV] (VQS for the time being without meaning) Readback of operating voltage VIM on the DcS CPU [100mV] Internal temperature (close to the processor) in the DcS CPU [K]

Page N-5

X X X X X X X X X X X

Default Preset

N Table of Operands


%IB (Byte)

14

28

%IX (Bit)



Description

Data structure


In.AnIn.RAMPE (WORD)

RAMPE_CPU

on C P U

I O

Test ramp for the Analog inputs of DcS CPU X (presently not supported)

Counting Inputs (TCOUNTERIN) In.Cnt.Value[1] (DINT) In.Cnt.Value[2] (DINT) In.Cnt.Value[3] (DINT) In.Cnt.Value[4] (DINT) In.Cnt.Value[5] (DINT) In.Cnt.Value[6] (DINT) In.Cnt.Value[7] (DINT) In.Cnt.Value[8] (DINT) In.Cnt.Velocity[1] (WORD) In.Cnt.Velocity[2] (WORD) In.Cnt.Velocity[3] (WORD)

15

30

IC1_1

17

34

19

38

21

42

23

46

25

50

27

54

29

58

31

62

32

64

33

66

34

68

In.Cnt.Velocity[4] (WORD)

IC2_2_Velo

35

70


IC3_1_Velo

36

72


IC3_2_Velo

37

74


IC4_1_Velo

38

76


IC4_2_Velo

IC1_2 IC2_1 IC2_2 IC3_1

Counting input (ID1.11 as IC1.1) Counting input (ID1.12 as IC1.2) Counting input (ID2.11 as IC2.1) Counting input (ID2.12 as IC2.2) Counting input (ID2.9 as IC3.1)

1

of

DcS

CPU

2

of

DcS

CPU

1

of

DcS

I/O

2

of

DcS

I/O

3

of

DcS

I/O

X X X X X

IC3_2

Counting input 4 of DcS I/O (ID2.10 as IC3.2)

X

IC4_1

Counting input 5 of DcS I/O(ID2.13 as IC4.1)

X

IC4_2

Counting input 6 of DcS I/O(ID2.14 as IC4.2)

X

IC1_1_Velo IC1_2_Velo IC2_1_Velo

Velocity on counting input No. 1 of DcS CPU X (IC1.1) [Pulses/time window] Velocity on counting input No. 2 of DcS CPU X (IC1.2) [Pulses/time window] Velocity on counting input 1 of DcS I/O (IC2.1) [Pulses/time window] Velocity on counting input 2 of DcS I/O (IC2.2) [Pulses/time window] (In the case of a configuration as an AB-counter: 0 = forward or unchanged („A before B“), 1 = backward („B before A“)) Velocity on counting input 3of DcS I/O (IC3.1) [Pulses/time window] Velocity on counting input 4 of DcS I/O (IC3.2) [Pulses/time window] (In the case of a configuration as an AB-counter: 0 = forward or unchanged („A before B“), 1 = backward („B before A“)) Velocity on counting input 5 of DcS I/O (IC4.1) [Pulses/time window] Velocity on counting input 6 of DcS I/O (IC4.2) [Pulses/time window] (In the case of a configuration as an AB-counter: 0 = forward or unchanged („A before B“), 1 = backward („B before A“))

PWM Current Measurement (TPWMIN) 39

78

40

80

41

82

42

84

43

86

44

88

04 – 68 283000/A Version 1.0.0

In.PWM.Current [1] (WORD) In.PWM.Current [2] (WORD) In.PWM.Current [3] (WORD) In.PWM.Current [4] (WORD) In.PWM.Current [5] (WORD) In.PWM.Current [6] (WORD)

IPI1_1 IPI1_2 IPI1_3 IPI1_4 IPI1_5 IPI1_6

Readback of current on PWM-output of DcS CPU (QD1.1) [2mA/Digit] Readback of current on PWM-output of DcS CPU (QD1.2) [2mA/Digit] Readback of current on PWM-output of DcS CPU (QD1.3) [2mA/Digit] Readback of current on PWM-output of DcS CPU (QD1.4) [2mA/Digit] Readback of current on PWM-output of DcS CPU (QD1.5) [2mA/Digit] Readback of current on PWM-output of DcS CPU (QD1.6) [2mA/Digit]

Page N-6

1 2 3 4 5 6

X X X X X X

X

X

X

X

X

Default Preset

N Table of Operands


%IB (Byte)

45

90

46

92

%IX (Bit)

Symbol address acc. to Data structure In.PWM.Current [7] (WORD) In.PWM.Current [8] (WORD)


Description C P U

Adjustable control configuration IPI1_7 IPI1_8

on I O

Default Preset

Readback of current on PWM-output 7 X of DcS CPU (QD1.7) [2mA/Digit] Readback of current on PWM-output 8 X of DcS CPU (QD1.8) [2mA/Digit]

General Input Variables of the Control Unit (TCOMMONIN) 47

94 95

48

49

In.Common.Awp Cycle (BYTE) In.Common.Wdg Reset (BYTE)

I_AWPCycle I_WdgReset

96

In.Common.Pwr Fail (BYTE)

I_PwrFail

97

In.Common.PWR _VIQ1 (BYTE)

I_PWR_VIQ1

98 99

Duration of the last AWP-cycle [ms]

X

Detection of a Watch-Dog-Reset on the DcS X CPU (TRUE -> Watch-Dog-Reset occurred) Detection of an undervoltage VIM on the DcS CPU (TRUE = VIM smaller than 8V in the X 12V-system or smaller than 16V in the 24Vsystem) Readback of the load supply voltage VIQ1 of X DcS CPU not used

In.Common.PWR _VIQ2 (BYTE) In.Common. SRAMchecked (INT) In.Common. FWchecked (INT)

I_SRAMchecked

I_PWR_VIQ2

50

100

51

102

52

104

In.Common. Nodestate (BYTE)

I_Nodestate

105

In.Common. AWPchecked (INT)

I_AWPchecked

I_Fwchecked

Digital input for the load supply voltage VIQ2 of DcS I/O

X

Number of test runs in the SRAM of DcS CPU X (-1 stands for error) Number of test runs of the firmware in the X flash of DcS CPU (-1 stands for error) Indicates the NMS-state of the CAN-node (0=Initializing, 1=Disconnected, 2=Connecting, 3= Preparing, 4=PREPARED, X 5=OPERATIONAL, 127=PREOPERATIONAL; s. ENUM EnodeState) Number of test runs of the AWP(appl. progr.) X in the flash of DcS CPU (-1 stands for error)

Input Variables of the CAN-Bus on the DcS I/O (TCANIOIN) 53

106

In.CAN.Active (BYTE)

54

108

In.CAN.Data (BYTE)

04 – 68 283000/A Version 1.0.0

CANActive_In

Indication as to whether the communication partner is transmitting in the DcS I/O (1 -> cyclic transmission 2 -> WRN(Activation of the SHDN) 4 -> BOFF(Activation of SHDN)) Input data from the CAN-Bus of DcS I/O; Permissible data types: TCanIOMobaRx, TCanIOJ1939Rx, TCanIODeutzRx, , TCanIOMuxRx

Page N-7

X

X

TCanIO MuxRx

N Table of Operands


N.4 Output Operands of the digsyâcompact E Input operand as %QW (Word)

%QB (Byte)

%QX (Bit)


Description

on


C P U

I O

X

X

Default Preset

Output Variables for the Digital Outputs (TDIGOUTOUT) 0

Out.DigOut.Value (WORD)

0

1

Digital outputs of DcS CPU and (QD1.1..QD1.8 und QD2.1..QD2.8)

QD

I/O

2#0

0.0

QD1_1

Digital output 1 of DcS CPU (QD1.1)

X

2#0

0.1

QD1_2


X

2#0

0.2

QD1_3


X

2#0

0.3

QD1_4


X

2#0

0.4

QD1_5


X

2#0

0.5

QD1_6


X

2#0

0.6

QD1_7


X

2#0

0.7

QD1_8


X

2#0

0.8

QD2_1

Digital output 1 of DcS I/O (QD2.1)

X

2#0

0.9

QD2_2


X

2#0

0.10

QD2_3


X

2#0

0.11

QD2_4


X

2#0

0.12

QD2_5


X

2#0

0.13

QD2_6


X

2#0

0.14

QD2_7


X

2#0

0.15

QD2_8


X

2#0

Output Variables for the Counting Inputs (TCOUNTEROUT) 1

2

2

4

3

6

4

8

5

10

6

12

7

14

8

16

04 – 68 283000/A Version 1.0.0

Out.Cnt.Time Wnd[1] (WORD) Out.Cnt.Time Wnd[2] (WORD) Out.Cnt.Time Wnd[3] (WORD) Out.Cnt.Time Wnd[4] (WORD) Out.Cnt.Time Wnd[5] (WORD) Out.Cnt.Time Wnd[6] (WORD) Out.Cnt.Time Wnd[7] (WORD) Out.Cnt.Time Wnd[8] (WORD)

IC1_1_TimeWnd IC1_2_TimeWnd IC2_1_TimeWnd IC2_2_TimeWnd IC3_1_TimeWnd IC3_2_TimeWnd IC4_1_TimeWnd IC4_2_TimeWnd

Time window of counting input 1 of DcS CPU in [ms] Time window of counting input 2 of DcS CPU in [ms] Time window of counting input 1 of DcS I/O in [ms] Time window of counting input 2 of DcS I/O in [ms] Time window of counting input 3 of DcS I/O in [ms] Time window of counting input 4 of DcS I/O in [ms] Time window of counting input 5 of DcS I/O in [ms] Time window of counting input 6 of DcS I/O in [ms]

Page N-8

X

2#0

X

2#0 X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

N Table of Operands

Input operand as %QW (Word)

%QB (Byte)

9

18

%QX (Bit)


Description

Data structure


Out.Cnt.Start (BYTE)

IC_Start

9.0

IC_1_1_Start

9.1

IC_1_2_Start

9.2

IC_2_1_Start

9.3

IC_2_2_Start

9.4

IC_3_1_Start

9.5

IC_3_2_Start

9.6

IC_4_1_Start

9.7

IC_4_2_Start Out.Cnt.Reset (BYTE)

19


IC_Reset

9.8

IC_1_1_Reset

9.9

IC_1_2_Reset

9.10

IC_2_1_Reset

9.11

IC_2_2_Reset

9.12

IC_3_1_Reset

9.13

IC_3_2_Reset

9.14

IC_4_1_Reset

9.15

IC_4_2_Reset

Starting/Stopping the counting on the counting inputs of DcSs CPU and I/O (IC1.1..IC1.2 and IC2.1..IC4.2 on ID1.11..ID1.12 and ID2.9..2.14) Starting the counting on counting input 1 of DcS CPU (IC1.1 or ID1.11) Starting the counting on counting input 2 of DcS CPU (IC1.2 or ID1.12) Starting the counting on counting input 1 of DcS I/O (IC2.1 or ID2.11) Starting the counting on counting input 2 of DcS I/O (IC2.2 or ID2.12) Starting the counting on counting input 3 of DcS I/O (IC3.1 or ID2.9) Starting the counting on counting input 4 of DcS I/O (IC3.2 or ID2.10) Starting the counting on counting input 5 of DcS I/O (IC4.1 or ID2.13) Starting the counting on counting input 6 of DcS I/O (IC4.2 or ID2.14) Resetting the counter values (with concurrent stopping) on the counting inputs of DcSs CPU and I/O (IC1.1..IC1.2 and IC2.1..IC4.2 on ID1.11..ID1.12 and ID2.9..2.14) Resetting the counter values (with concurrent stopping) on the counting input 1of DcS CPU (IC1.1 or ID1.11) Resetting the counter values (with concurrent stopping) on the counting input 2 of DcS CPU (IC1.2 or ID1.12) Resetting the counter values (with concurrent stopping) on the counting input 1 of DcS I/O (IC2.1 or ID2.11) Resetting the counter values (with concurrent stopping) on the counting input 2 of DcS I/O (IC2.2 or ID2.12) Resetting the counter values (with concurrent stopping) on the counting input 3 of DcS I/O (IC3.1 or ID2.9) Resetting the counter values (with concurrent stopping) on the counting input 4 of DcS I/O (IC3.2 or ID2.10) Resetting the counter values (with concurrent stopping) on the counting input 5 of DcS I/O (IC4.1 or ID2.13) Resetting the counter values (with concurrent stopping) on the counting input 6 of DcS I/O (IC4.2 or ID2.14)

on C P U

I O

X

X

Default Preset

2#0

X

2#0

X

2#0

X

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0 X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

Analog Outputs (TANOUTOUT) 10

20

11

22

12

24

13

26

Out.AnOut.Value [1] (WORD) Out.AnOut.Value [2] (WORD) Out.AnOut.Value [3] (WORD) Out.AnOut.Value [4] (WORD)

QAI1 QAI2 QAI3 QAI4

Output value of Analog output 1 of DcS I/O (QAI1) [Digits] (0 to 500 Digits = 0 to +20mA) Output value of Analog output 2 of DcS I/O (QAI2) [Digits] (0 to 500 Digits = 0 to +20mA) Output value of Analog output 3 of DcS I/O (QAI3) [Digits] (0 to 500 Digits = 0 to +20mA) Output value of Analog output 4 of DcS I/O (QAI4) [Digits] (0 to 500 Digits = 0 to +20mA)

PWM-Outputs (TPWMOUT)

04 – 68 283000/A Version 1.0.0

Page N-9

N Table of Operands


%QB (Byte)

14

28

15

30

16

32

17

34

18

36

19

38

20

40

21

42

22

44

23

46

24

48

25

50

26

52

27

54

%QX (Bit)

Symbol address acc. to Data structure Out.PWM.Freq[1] (WORD) Out.PWM.Freq[2] (WORD) Out.PWM.Freq[3] (WORD) Out.PWM.Freq[4] (WORD) Out.PWM.Freq[5] (WORD) Out.PWM.Pwidth [1] (WORD) Out.PWM.Pwidth [2] (WORD) Out.PWM.Pwidth [3] (WORD) Out.PWM.Pwidth [4] (WORD) Out.PWM.Pwidth [5] (WORD) Out.PWM.Pwidth [6] (WORD) Out.PWM.Pwidth [7] (WORD) Out.PWM.Pwidth [8] (WORD) Out.PWM.Pstart (BYTE)


Description C P U

Adjustable control configuration QP1_Freq QP2_Freq QP3_Freq QP4_Freq QP5_8_Freq QP1_PWidth QP2_PWidth QP3_PWidth QP4_PWidth QP5_PWidth QP6_PWidth QP7_PWidth QP8_PWidth QP_Start

27.0

QP1_Start

27.1

QP2_Start

27.2

QP3_Start

27.3

QP4_Start

27.4

QP5_Start

27.5

QP6_Start

27.6

QP7_Start

27.7

QP8_Start

55

on

Frequency of the PWM-output 1 of DcS CPU (QD1.1) [Hz] Range: 50 to 1200Hz Frequency of the PWM-output 2 of DcS CPU (QD1.2) [Hz] Range: 50 to 1200Hz Frequency of the PWM-output 3 of DcS CPU (QD1.3) [Hz] Range: 50 to 1200Hz Frequency of the PWM-output 4 of DcS CPU (QD1.4) [Hz] Range: 50 to 1200Hz Frequency of the PWM-outputs 5..8 of DcS CPU (QD1.5..QD1.8) [Hz] Range: 50 to 1200Hz Pulse width of the PWM-output 1of DcS CPU (QD1.1) [Digits] Range: 0 to 1023 Digits Pulse width of the PWM-output 2 of DcS CPU (QD1.2) [Digits] Range: 0 to 1023 Digits Pulse width of the PWM-output 3 of DcS CPU (QD1.3) [Digits] Range: 0 to 1023 Digits Pulse width of the PWM-output 4 of DcS CPU (QD1.4) [Digits] Range: 0 to 1023 Digits Pulse width of the PWM-output 5 of DcS CPU (QD1.5) [Digits] Range: 0 to 1023 Digits Pulse width of the PWM-output 6 of DcS CPU (QD1.6) [Digits] Range: 0 to 1023 Digits Pulse width of the PWM-output 7 of DcS CPU (QD1.7) [Digits] Range: 0 to 1023 Digits Pulse width of the PWM-output 8 of DcS CPU (QD1.8) [Digits] Range: 0 to 1023 Digits Enabling the PWM-outputs 1 to 8 of DcS CPU (QD1.1 to QD1.8) Enabling the PWM-output 1 of DcS CPU (QD1.1) Enabling the PWM-output 2 of DcS CPU (QD1.2) Enabling the PWM-output 3 of DcS CPU (QD1.3) Enabling the PWM-output 4 of DcS CPU (QD1.4) Enabling the PWM-output 5 of DcS CPU (QD1.5) Enabling the PWM-output 6 of DcS CPU (QD1.6) Enabling the PWM-output 7 of DcS CPU (QD1.7) Enabling the PWM-output 8 of DcS CPU (QD1.8)

I O

Default Preset

X

10#400

X

10#400

X

10#400

X

10#400

X

10#400

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

not used General Output Variables of the Control Unit (TCOMMONOUT)

28

56

Out.Common.Pwr _Hold (BYTE)

Q_Pwr_Hold

57

Out.Common. VQSW1_OFF (BYTE)

Q_VQSW1_OFF

04 – 68 283000/A Version 1.0.0

Flag for defined switch-off of the control unit from the AWP (appl. prog.); shall be set after switch-on; in the case of FALSE and switched X off IPON, the control unit will be switched off (Vcc=0) Flag for switching the load supply voltage VIQ1 from the outputs QD1.1..QD1.8 X (true=outputs supplied; is currently not supported)

Page N-10

X

2#0

2#0

N Table of Operands


%QB (Byte)

%QX (Bit)


Description

on C P U


29 30


I O

Default Preset

not used 60

Change of the voltage level for the Digital inputs on the I/O TRUE -> 24V FALSE -> 12V

Out.Common. SET_12_24V (BOOL)

61

X

not used Output variables of the CAN-Bus of the DcS I/O (TCANIOOUT)

31

62 63

Out.CAN.Mode (BYTE) Out.CAN.Timeout (BYTE)

32

64

Out.CAN.Speed (ECanSpeed)

33

66

Out.CAN.Data

04 – 68 283000/A Version 1.0.0

Q_CAN_Mode Q_CAN_Timeout Q_CAN_Speed

Possible modes: 0=no mode, 1=MOBA, 2=J1939, 3=Deutz Motor connection J1939 Timeout of the CAN of DcS I/O in steps of [10ms] (0=no Timeout) Transmission speed of the CAN of DcS I/O (Data type from enumeration structure EcanSpeed in the library Prosyd.lib) From here all output-PDOs of the CAN-bus (Permissible data types: TCanIOMobaTx, TCanIOJ1939Tx, TCanIODeutzTx, TCanIOMuxTx)

Page N-11

X

10#0

X

10#200

X

KBD_ 125

X

TcanIO MuxTx

N Table of Operands


N.5 System Input Operands of the digsyâcompact E Input operand as %IW (Word)

%IB (Byte)

96

192

%IX (Bit)

193 97

194 195

98

196 197

99

100

200

101

202

102

204 205

103

206

104

208 209 210 211

106

212 213

107

214 215

108 109

110

Description

Data structure


SysIn.initialized (BYTE)

SYSIN_WasInit

SysIn.SW_Major (BYTE) SysIn.SW_Minor (BYTE) SysIn.SW_Bugfix (BYTE) SysIn.HW_Major (BYTE) SysIn.HW_Minor (BYTE)

SYSIN_CPU_SW _Major SYSIN_CPU_SW _Minor SYSIN_CPU_SW _Bugfix SYSIN_CPU_Har dware_Major SYSIN_CPU_Har dware_Minor

198 199

105


218

C P U

I O

Flag for the first AWP-processing (true=first AWP-run (is/was) effected, false=AWP not X yet started) Majority-version of the software of DcS CPU

X

Minority-version of the software of DcS CPU

X

Bugfix-version of the software of DcS CPU

X

Majority-version of the hardware of DcS CPU

X

Minority-version of the hardware of DcS CPU

X

not used SysIn.RetainIdx (BYTE) SysIn.Retain Length (WORD) SysIn.Retain Pcycles (WORD) SysIn.CanType (BYTE) SysIn.CanNode State (BYTE) SysIn.ErrorCnt (WORD) SysIn.IO_SW_ Major (BYTE) SysIn.IO_SW_ Minor (BYTE) SysIn.IO_SW_ Bugfix (BYTE) SysIn.IO_HW_ Major (BYTE) SysIn.IO_HW_Mi nor (BYTE) SysIn.FlManu Code (BYTE) SysIn.FlIdent (BYTE) SysIn.PWR_VIQ1 (BYTE) SysIn.cnt_PWR_ IPON-Changes (WORD) SysIn.PWR_ IPON (BYTE)

SYSIN_RetainIdx Current Retain data block SYSIN_Retain Length SYSIN_Retain PCycles

Provides the current Retain data length

X

X

X

X

Number of the Retain programming cycles so X far Type of the implemented CAN-protocol SYSIN_CANType X (0=CANopen-Slave) SYSIN_CAN NMS-state of the CAN-node X NodeState SYSIN_ErrorCnt SYSIN_IO_SW_ Major SYSIN_IO_SW_ Minor SYSIN_IO_SW_ Bugfix SYSIN_IO_HW_ Major SYSIN_IO_HW_ Minor SYSIN_FlManu Code

Provides the current error counter status

X

Bugfix-version of the software of DcS I/O

X

Majority-version of the hardware of DcS I/O

X

Minority-version of the hardware of DcS I/O

X

SYSIN_PWR_ IPON

State of the switching input IPON

220

SysIn.cnt_PWR_ FAIL (WORD)

SYSIN_CNT_ PWR_FAIL

X

X

Number of the IPON switching operations X (only change from high to low)

SYSIN_PWR_ FAIL

X

Minority-version of the software of DcS I/O

SYSIN_PWR_ IPON_Changes

SysIn.PWR_FAIL _Voltage(BYTE)

X

X

SYSIN_PWR_ VIQ1

SYSIN_FlIdent

X

Majority-version of the software of DcS I/O

Manufacturing Code of the Flash-EPROM X being on the DcS CPU Identity Code of the Flash-EPROM being on X the DcS CPU Readback of the load supply voltage VIQ1 of X DcS CPU

219

04 – 68 283000/A Version 1.0.0

on

X

Detection of an undervoltage VIM on DcS CPU (TRUE = VIM smaller than 8V in 12V- X system or smaller than 16V in 24V-system) Number of the detected undervoltages (VIM smaller than 8V in 12V-system or VIM smaller X than 16V in 24V-system)

Page N-12

Default Preset

N Table of Operands


%IB (Byte)

111

%IX (Bit)


Description

Data structure


222

SysIn.readCfg 10msTask[1] (WORD)

SYSIN_CFG 10MS_1

112

224


SYSIN_CFG 10MS_2

113

226


SYSIN_CFG 10MS_3

114

228


SYSIN_CFG 10MS_4

115

230


SYSIN_CFG 10MS_5

116

232


SYSIN_CFG 10MS_6

117

234


SYSIN_CFG 10MS_7

118

236


SYSIN_CFG 10MS_8

119

238


SYSIN_CFG 10MS_9

120

240


SYSIN_CFG 10MS_10

121

242

122

244

123

246

124

248

125

250

126

252

127

254

128

256

04 – 68 283000/A Version 1.0.0

SysIn.maxCur rentToMeasure[1] (WORD) SysIn.maxCur rentToMeasure[2] (WORD) SysIn.maxCur rentToMeasure[3] (WORD) SysIn.maxCur rentToMeasure[4] (WORD) SysIn.maxCur rentToMeasure[5] (WORD) SysIn.maxCur rentToMeasure[6] (WORD) SysIn.maxCur rentToMeasure[7] (WORD) SysIn.maxCur rentToMeasure[8] (WORD)

Manual digsy®compact on C P U

Configuring the 1st millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active) Configuring the 2nd millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active) Configuring the 3rd millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active) Configuring the 4th millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active) Configuring the 5th millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active) Configuring the 6th millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active) Configuring the 7th millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active) Configuring the 8th millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active) Configuring the 9th millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active) Configuring the 10th millisecond of the 10ms task (low Byte indicates active channel, Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc., Bit 8..14 irrelevant, Bit 15 = call-up active)

X

X

X

X

X

X

X

X

X

X

SYSIN_MAX_ IPI1_1

Maximum current to be measured on current X measuring channel 1 (QD1.1) [2mA/Digit]

SYSIN_MAX_ IPI1_2


SYSIN_MAX_ IPI1_3


SYSIN_MAX_ IPI1_4


SYSIN_MAX_ IPI1_5


SYSIN_MAX_ IPI1_6


SYSIN_MAX_ IPI1_7


SYSIN_MAX_ IPI1_8


Page N-13

I O

Default Preset

N Table of Operands


%IB (Byte)

129

258

%IX (Bit)

259


Description

SysIn.statePWM OffsetCalibration (BYTE) SysIn.statePWM GradientCalibra tion (BYTE)

on C P U


State of the Offset-calibration of the PWM X current measurement (true=calibrated) Status of the Gradient calibration of the PWM X current measurement (true=calibrated)

130

not used 262

SysIn.DayOf Week (BYTE)

SYSIN_DAYOF WEEK

263

SysIn.Week (BYTE)

SYSIN_WEEK

132

264

SysIn.RTC_Date (DATE)

SYSIN_RTC_ DATE

134

268

SysIn.RTC_Date AndTime (DATE_ AND_TIME)

SYSIN_RTC_ DATEANDTIME

131


136

Reading out the weekday of the real-time clock (0=Sunday, 1=Monday, .., 6=Saturday) (Only valid with RTC_Date-flag set in SystemCfg) Reading out the calendar week of the realtime clock (only valid with RTC_Date-flag set in SystemCfg) Reading out the date of the real-time clock (Notation: YYYY-MM-DD) (Only valid with RTC_Date-flag set in SystemCfg) Reading out the date and time of the real-time clock (Notation: YYYY-MM-DD-hh:mm:ss) (Only valid with RTC_Date-flag set in SystemCfg) not used

:

:

159

not used

04 – 68 283000/A Version 1.0.0

Page N-14

X

X X

X

I O

Default Preset

N Table of Operands


N.6 System Output Operands of the digsyâcompact E Input operand as %QW (Word)

%QB (Byte)

96

192

%QX (Bit)

193 97

194

Symbol address acc. to Data structure SysOut.initialized (BYTE) SysOut.set_Can Type (BYTE) SysOut.set_Can NodeState (BYTE)

Description

SYSOUT_Was Init SYSOUT_set CANType

Flag for one-time processing of the X AWP(appl. progr.)-cycle Sets the type of the CAN-protocol X (0=CANopen-Slave)

SYSOUT_set CANNodeState

Sets the NMS-state of the CAN-node

SysOut.en_ emergency (BYTE)

SYSOUT_ ENABLE_ EMERGENCY

98

196

SysOut.wSet_ VCP (WORD)

SYSOUT_SET_ VCP

99

198

SysOut.wSet_ VTS (WORD)

SYSOUT_SET_ VTS

100

200

SysOut.bReset WdgFlag (BYTE) SysOut.bActivate _setting_VCP (BYTE)

SYSOUT_ RESET_WDG

101

C P U


195

201

SYSOUT_ ACTIVATE_VCP

Mask for Emergency-readouts on the CANbus (0=no message, 1=normal message, 2=warning, 4=user error, 8=application error, 16=system error, 31=all) Setting the Offset voltage VCP for the inputs ID1.9..ID1.12 on the DcS CPU [mV] (0..34500mV in steps of 138mV) Setting the Test ramp VTS for testing the function of the AD-converter on the DcS CPU [mV] (0..34500mV in steps of 138mV) (presently not supported) Resetting the Watchdog counter WdgReset in TCommonIn with rising edge Activating the Offset voltage wSet_VCP not used

:

:

127

not used

04 – 68 283000/A Version 1.0.0

on

Page N-15

I O

Default Preset

X

X

2#0

X

10#0

X

2#0

X

2#0

X

2#0

N Table of Operands


N.7 Configuration Operands of the digsyâcompact E Input operand as %QW (Word)

%QB (Byte)


%QX (Bit)

Data structure

Desription

on C P U


I O

Default Preset

Configuration Variables for the Digital Inputs (TDIGINCFG) 128

Cfg.DigIn.Used[1] (WORD)

256

257

CFG_ID_CPU

128.0

CFG_ID1_1

128.1

CFG_ID1_2

128.2

CFG_ID1_3

128.3

CFG_ID1_4

128.4

CFG_ID1_5

128.5

CFG_ID1_6

128.6

CFG_ID1_7

128.7

CFG_ID1_8

128.8

CFG_ID1_9

128.9

CFG_ID1_10

128.10

CFG_ID1_11

128.11

CFG_ID1_12

128.12

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

not used Cfg.DigIn.Used[2] (WORD)

CFG_ID_IO

129.0

CFG_ID2_1

129.1

CFG_ID2_2

129.2

CFG_ID2_3

129.3

CFG_ID2_4

129.4

CFG_ID2_5

129.5

CFG_ID2_6

129.6

CFG_ID2_7

129.7

CFG_ID2_8

04 – 68 283000/A Version 1.0.0

0

:

128.15 258

X

not used

:

129

Using the Digital inputs of DcS CPU (ID1.1 to ID1.12) - dyncfg Using the Digital input 1 of DcS CPU (ID1.1) - dyncfg Using the Digital input 2 of DcS CPU (ID1.2) - dyncfg Using the Digital input 3 of DcS CPU (ID1.3) - dyncfg Using the Digital input 4 of DcS CPU (ID1.4) - dyncfg Using the Digital input 5 of DcS CPU (ID1.5) - dyncfg Using the Digital input 6 of DcS CPU (ID1.6) - dyncfg Using the Digital input 7 of DcS CPU (ID1.7) - dyncfg Using the Digital input 8 of DcS CPU (ID1.8) - dyncfg Using the Digital input 9 of DcS CPU (ID1.9) - dyncfg Using the Digital input 10 of DcS CPU (ID1.10) - dyncfg Using the Digital input 11 of DcS CPU (ID1.11) (Has to be set to „0“ when used as counter IC1.1) - dyncfg Using the Digital input 12 of DcS CPU (ID1.12) (Has to be set to „0“ when used as counter IC1.2) - dyncfg

Using the Digital inputs of DcS ID2.14) – dyncfg Using the Digital of DcS I/O (ID2.1) – dyncfg Using the Digital of DcS I/O (ID2.2) – dyncfg Using the Digital of DcS I/O (ID2.3) – dyncfg Using the Digital of DcS I/O (ID2.4) – dyncfg Using the Digital of DcS I/O (ID2.5) – dyncfg Using the Digital of DcS I/O (ID2.6) – dyncfg Using the Digital of DcS I/O (ID2.7) – dyncfg Using the Digital of DcS I/O (ID2.8) – dyncfg

Page N-16

I/O (ID2.1 to input

1

input

2

input

3

input

4

input

5

input

6

input

7

input

8

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

N Table of Operands


130


%QX (Bit)

259

129.8

CFG_ID2_9

129.9

CFG_ID2_10

129.10

CFG_ID2_11

129.11

CFG_ID2_12

129.12

CFG_ID2_13

129.13

CFG_ID2_14

Using the Digital input 9 of DcS I/O (ID2.9) (Has to be set to „0“ when used as counter IC3.1) - dyncfg Using the Digital input 10 of DcS I/O (ID2.10) (Has to be set to „0“ when used as counter IC3.2) - dyncfg Using the Digital input 11 of DcS I/O (ID2.11) (Has to be set to „0“ when used as counter IC2.1) - dyncfg Using the Digital input 12 of DcS I/O (ID2.12) (Has to be set to „0“ when used as counter IC2.2) - dyncfg Using the Digital input 13 of DcS I/O (ID2.13) (Has to be set to „0“ when used as counter IC4.1) - dyncfg Using the Digital input 14 of DcS I/O (ID2.14) (Has to be set to „0“ when used as counter IC4.2) - dyncfg not used

129.15

not used Cfg.DigIn.Used[3] (WORD)

260

CFG_QD_AS_ID CFG_QD2_1_AS _ID3_1 CFG_QD2_2_AS _ID3_2 CFG_QD2_3_AS _ID3_3 CFG_QD2_4_AS _ID3_4 CFG_QD2_5_AS _ID3_5 CFG_QD2_6_AS _ID3_6 CFG_QD2_7_AS _ID3_7 CFG_QD2_8_AS _ID3_8

130.1 130.2 130.3 130.4 130.5 130.6 130.7 261

on C P U


129.14

130.0

131

Desription

%QB (Byte)

Data structure


Using the Digital outputs of DcS I/O as Digital inputs (QD2.1 to QD2.8) - dyncfg Using the Digital output 1 of DcS I/O as Digital input (QD2.1) - dyncfg Using the Digital output 2 of DcS I/O as Digital input (QD2.2) - dyncfg Using the Digital output 3 of DcS I/O as Digital input (QD2.3) - dyncfg Using the Digital output 4 of DcS I/O as Digital input (QD2.4) - dyncfg Using the Digital output 5 of DcS I/O as Digital input (QD2.5) - dyncfg Using the Digital output 6 of DcS I/O as Digital input (QD2.6) - dyncfg Using the Digital output 7 of DcS I/O as Digital input (QD2.7) - dyncfg Using the Digital output 8 of DcS I/O as Digital input (QD2.8) - dyncfg

I O

Default Preset

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

not used Cfg.DigIn.Group (BYTE)

262

131.0

131.1

131.2

131.3

04 – 68 283000/A Version 1.0.0

Configuring the active switching levels of the Digital inputs of DcSs CPU and I/O CFG_ID_GROUP X (1=plusswitching, 0=groundswitching) dyncfg Configuring the active switching levels of the CFG_ID_ Digital inputs 1 to 5 of DcS CPU (ID1.1 to X ID1.4) (1=plusswitching, 0=groundswitching) GROUP_1 dyncfg Configuring the active switching levels of the Digital inputs 6 to 10 of DcS CPU CFG_ID_ X GROUP_2 (ID1.4 to ID1.8) (1=plusswitching, 0=groundswitching) - dyncfg Configuring the active switching levels of the Digital inputs 1 to 4 of DcS I/O CFG_ID_ GROUP_3 (ID2.1 to ID2.4) (1=plusswitching, 0=groundswitching) - dyncfg Configuring the active switching levels of the CFG_ID_ Digital inputs 5 to 8 of DcS I/O GROUP_4 (ID2.5 to ID2.8) (1=plusswitching, 0=groundswitching) - dyncfg

Page N-17

0

0

X

0

X

0

N Table of Operands


%QB (Byte)


%QX (Bit)

Data structure

Desription


131.4

C P U

I O

X

X

Default Preset

:

131.7

not used

263

not used

Cfg.DigOut.Used (WORD)

264

265

on

not used

:

132


CFG_QD

132.0

CFG_QD1_1

132.1

CFG_QD1_2

132.2

CFG_QD1_3

132.3

CFG_QD1_4

132.4

CFG_QD1_5

132.5

CFG_QD1_6

132.6

CFG_QD1_7

132.7

CFG_QD1_8

132.8

CFG_QD2_1

132.9

CFG_QD2_2

132.10

CFG_QD2_3

132.11

CFG_QD2_4

132.12

CFG_QD2_5

132.13

CFG_QD2_6

132.14

CFG_QD2_7

132.15

CFG_QD2_8

Using the Digital outputs of DcS CPU and I/O (QD1.1..QD1.8 and QD2.1..QD2.8) - dyncfg Using the Digital output 1 of DcS CPU (QD1.1) (Has to be set to „0“ when used as a PWM-output) - dyncfg Using the Digital output 2 of DcS CPU (QD1.2) (Has to be set to „0“ when used as a PWM-output) - dyncfg Using the Digital output 3 of DcS CPU (QD1.3) (Has to be set to „0“ when used as a PWM-output) - dyncfg Using the Digital output 4 of DcS CPU (QD1.4) (Has to be set to „0“ when used as a PWM-output) - dyncfg Using the Digital output 5 of DcS CPU (QD1.5) (Has to be set to „0“ when used as a PWM-output) - dyncfg Using the Digital output 6 of DcS CPU (QD1.6) (Has to be set to „0“ when used as a PWM-output) - dyncfg Using the Digital output 7 of DcS CPU (QD1.7) (Has to be set to „0“ when used as a PWM-output) - dyncfg Using the Digital output 8 of DcS CPU (QD1.8) (Has to be set to „0“ when used as a PWM-output) - dyncfg Using the Digital output 1 of DcS I/O (QD2.1) - dyncfg Using the Digital output 2 of DcS I/O (QD2.2) - dyncfg Using the Digital output 3 of DcS I/O (QD2.3) - dyncfg Using the Digital output 4 of DcS I/O (QD2.4) - dyncfg Using the Digital output 5 of DcS I/O (QD2.5) - dyncfg Using the Digital output 6 of DcS I/O (QD2.6) - dyncfg Using the Digital output 7 of DcS I/O (QD2.7) - dyncfg Using the Digital output 8 of DcS I/O (QD2.8) - dyncfg

X X X X X X X X X X X X X

0

X

0

X

0

X

0

X

0

Configuration Variables for the Analog Inputs (TANINCFG) 133

Cfg.AnIn.Used (BYTE)

266 133.0 133.1

04 – 68 283000/A Version 1.0.0

CFG_IA_Used CFG_IA1_1_ Used CFG_IA1_2_ Used

Using the Analog inputs of DcS CPU and I/O (IAV1.1..IAV1.4, IAV2.1..IAV2.4 or X IAI1.1..IAI1.4, IAI2.1..IAI2.4) - dyncfg Using the Analog input 1 X of DcS CPU (IAV1.1 or IAI1.1) - dyncfg Using the Analog input 2 X of DcS CPU (IAV1.2 or IAI1.2) - dyncfg

Page N-18

0 0

N Table of Operands


%QB (Byte)

%QX (Bit)


Desription

133.3 133.4 133.5 133.6 133.7 267

C P U Using the Analog input of DcS CPU (IAV1.3 or IAI1.3) - dyncfg Using the Analog input of DcS CPU (IAV1.4 or IAI1.4) - dyncfg Using the Analog input of DcS I/O (IAV2.1 or IAI2.1) - dyncfg Using the Analog input of DcS I/O (IAV2.2 or IAI2.2) - dyncfg Using the Analog input of DcS I/O (IAV2.3 or IAI2.3) - dyncfg Using the Analog input of DcS I/O (IAV2.4 or IAI2.4) - dyncfg

3 4

I O

Default Preset

X

0

X

0

1 2 3 4

X

0

X

0

X

0

X

0

not used

134

268

Cfg.AnIn.Upper Limit [1] (WORD)

CFG_IA1_1_ LimitUp

135

270


CFG_IA1_2_ LimitUp

136

272


CFG_IA1_3_ LimitUp

137

274


CFG_IA1_4_ LimitUp

138

276


CFG_IA2_1_ LimitUp

139

278


CFG_IA2_2_ LimitUp

140

280


CFG_IA2_3_ LimitUp

141

282


CFG_IA2_4_ LimitUp

142

284

Cfg.AnIn.Lower Limit [1] (WORD)

CFG_IA1_1_ LimitLow

143

286


CFG_IA1_2_ LimitLow

144

288


CFG_IA1_3_ LimitLow

145

290


CFG_IA1_4_ LimitLow

146

292


CFG_IA2_1_ LimitLow

147

294


CFG_IA2_2_ LimitLow

148

296


CFG_IA2_3_ LimitLow

149

298


CFG_IA2_4_ LimitLow

04 – 68 283000/A Version 1.0.0

on

Adjustable control configuration CFG_IA1_3_ Used CFG_IA1_4_ Used CFG_IA2_1_ Used CFG_IA2_2_ Used CFG_IA2_3_ Used CFG_IA2_4_ Used

133.2


Upper limiting value of the Analog input 1 of DcS CPU (IAV1.1 or IAI1.1) [Digit] (Range: 0 to 1023 Digits) - dyncfg Upper limiting value of the Analog input 2 of DcS CPU (IAV1.2 or IAI1.2) [Digit] (Range: 0 to 1023 Digits) - dyncfg Upper limiting value of the Analog input 3 of DcS CPU (IAV1.3 or IAI1.3) [Digit] (Range: 0 to 1023 Digits) - dyncfg Upper limiting value of the Analog input 4 of DcS CPU (IAV1.4 or IAI1.4) [Digit] (Range: 0 to 1023 Digits) - dyncfg Upper limiting value of the Analog input 1 of DcS I/O (IAV2.1 or IAI2.1) [Digit] (Range: 0 to 1023 Digits) - dyncfg Upper limiting value of the Analog input 2 of DcS I/O (IAV2.2 or IAI2.2) [Digit] (Range: 0 to 1023 Digits) - dyncfg Upper limiting value of the Analog input 3 of DcS I/O (IAV2.3 or IAI2.3) [Digit] (Range: 0 to 1023 Digits) - dyncfg Upper limiting value of the Analog input 4 of DcS I/O (IAV2.4 or IAI2.4) [Digit] (Range: 0 to 1023 Digits) - dyncfg Lower limiting value of the Analog input 1 of DcS CPU (IAV1.1 or IAI1.1) [Digit] (Range: 0 to 1023 Digits) - dyncfg Lower limiting value of the Analog input 2 of DcS CPU (IAV1.2 or IAI1.2) [Digit] (Range: 0 to 1023 Digits) - dyncfg Lower limiting value of the Analog input 3 of DcS CPU (IAV1.3 or IAI1.3) [Digit] (Range: 0 to 1023 Digits) - dyncfg Lower limiting value of the Analog input 4 of DcS CPU (IAV1.4 or IAI1.4) [Digit] (Range: 0 to 1023 Digits) - dyncfg Lower limiting value of the Analog input 1 of DcS I/O (IAV2.1 or IAI2.1) [Digit] (Range: 0 to 1023 Digits) - dyncfg Lower limiting value of the Analog input 2 of DcS I/O (IAV2.2 or IAI2.2) [Digit] (Range: 0 to 1023 Digits) - dyncfg Lower limiting value of the Analog input 3 of DcS I/O (IAV2.3 or IAI2.3) [Digit] (Range: 0 to 1023 Digits) - dyncfg Lower limiting value of the Analog input 4 of DcS I/O (IAV2.4 or IAI2.4) [Digit] (Range: 0 to 1023 Digits) - dyncfg

Page N-19

X

16# 0FFF

X

16# 0FFF

X

16# 0FFF

X

16# 0FFF X

16# 0FFF

X

16# 0FFF

X

16# 0FFF

X

16# 0FFF

X

16# 0000

X

16# 0000

X

16# 0000

X

16# 0000 X

16# 0000

X

16# 0000

X

16# 0000

X

16# 0000

N Table of Operands


%QB (Byte)

150

300

151

302

152

304

153

306

154

308

155

310

156

312

157

314


%QX (Bit)

Data structure Cfg.AnIn.VQS_ VCP_UpperLimit (WORD) Cfg.AnIn.VIMP_ UpperLimit (WORD) Cfg.AnIn.TEMP_ UpperLimit (WORD) Cfg.AnIn.RAMPE _UpperLimit (WORD) Cfg.AnIn.VQS_ VCP_LowerLimit (WORD) Cfg.AnIn.VIMP_ LowerLimit (WORD) Cfg.AnIn.TEMP_ LowerLimit (WORD) Cfg.AnIn.RAMPE _LowerLimit (WORD)


Desription

on C P U


I O

Upper limiting value of the offset voltage VCP CFG_VQS_VCP_ for the inputs ID1.9..ID1.12 on the DcS CPU X LimitUp in [mV] (Range: 0 to 32000mV) Upper limiting value of the operating voltage CFG_VIMP_ VIMP of DcS CPU in [100mV] (Range: 90 to X LimitUp 320 corresponds with 9 to 32V ) CFG_TEMP_ LimitUp

Default Preset 16# 7D00 10#350

Upper limiting value of temperature of DcS X CPU in [K] (Range: 243 to 393K)

10#393

Upper limiting value of test ramp VTS of DcS CPU in [Digit] (Range: 0 to 1023 Digits) X (presently without function) Lower limiting value of offset voltage VCP for CFG_VQS_VCP_ the inputs ID1.9..ID1.12 on the DcS CPU in X LimitLow [mV] (Range: 0 to 32000mV) Lower limiting value of operating voltage CFG_VIMP_ Vimp of DcS CPU in [Digit] (0 to 1023 -> X LimitLow 1Digit corresponds to 10mV)

16# 03FF

CFG_RAMPE_ LimitUp

16# 0000 10#90

CFG_TEMP_ LimitLow

Lower limiting value of temperature X of DcS CPU in [K] (Range: 243 to 393K)

10#243

CFG_RAMPE_ LimitLow

Lower limiting value of test ramp VTS of DcS CPU in [Digit] (Range: 0 to 1023 Digits) X (presently without function)

16# 0000

Configuration Variables for the Analog Outputs (TANOUTCFG) 158

Cfg.AnOut.Used (BYTE)

316

CFG_QAI

158.0

CFG_QAI1

158.1

CFG_QAI2

158.2

CFG_QAI3

158.3

CFG_QAI4

158.4

Using the Analog Outputs of DcS I/O (QAI1..QAI4) - dyncfg Using the Analog output of DcS I/O (QAI1) - dyncfg Using the Analog output of DcS I/O (QAI2) - dyncfg Using the Analog output of DcS I/O (QAI3) - dyncfg Using the Analog output of DcS I/O (QAI4) - dyncfg

1-4 1 2 3 4

X

0

X

0

X

0

X

0

X

0

X

0

not used

:

:

158.7

not used

317

not used Configuration Variables for the Counting Inputs (TCOUNTERCFG)

159

Cfg.Cnt.Used (BYTE)

318

CFG_IC

159.0

CFG_IC1_1

159.1

CFG_IC1_2

159.2

CFG_IC2_1

159.3

CFG_IC2_2

159.4

CFG_IC3_1

159.5

CFG_IC3_2

04 – 68 283000/A Version 1.0.0

Using the counting inputs of DcS CPU and I/O X (IC1.1..IC1.2; IC2.1..IC4.2) - dyncfg Using the counting input 1 X of DcS CPU (IC1.1) - dyncfg Using the counting input 2 X of DcS CPU (IC1.2) - dyncfg Using the counting input 1 of DcS I/O (IC2.1) - dyncfg Using the counting input 2 of DcS I/O (IC2.2) - dyncfg Using the counting input 3 of DcS I/O (IC3.1) - dyncfg Using the counting input 4 of DcS I/O (IC3.2) - dyncfg

Page N-20

0 0 X

0

X

0

X

0

X

0

N Table of Operands


%QB (Byte)

%QX (Bit)


Desription

CFG_IC4_1

159.7

CFG_IC4_2 Cfg.Cnt.AB (BYTE)

on C P U


159.6

319


CFG_AB

159.8

CFG_IC1_AB_1

159.9

CFG_IC1_AB_2

159.10

CFG_IC2_AB_1

159.11

CFG_IC2_AB_2

159.12

CFG_IC3_AB_1

159.13

CFG_IC3_AB_2

159.14

CFG_IC4_AB_1

159.15

CFG_IC4_AB_2

Using the counting input 5 of DcS I/O (IC4.1) - dyncfg Using the counting input 6 of DcS I/O (IC4.2) - dyncfg Using the counting inputs of DcS I/O as ABcounters(IC2.1 to IC4.2) (1=AB-counter, 0=single counter) - dyncfg Using the counting input IC1 of DcS CPU as AB-counter (A-signal) (IC1.1) (1=AB-counter, 0=single counter) X (presently not supported, must be „0“) – dyncfg Using the counting input IC1 of DcS CPU as AB-counter (B-signal) (IC2.2) (1=AB-counter, 0=single counter) X (presently not supported, must be „0“) – dyncfg Using the counting input IC2 of DcS I/O as AB-counter (A-signal) (IC2.1) (1=AB-counter, 0=single counter) - dyncfg Using the counting input IC2 of DcS I/O as AB-counter (B-signal) (IC2.2) (1=AB-counter, 0=single counter) - dyncfg Using the counting input IC3 of DcS I/O as AB-counter (A-signal) (IC3.1) (1=AB-counter, 0=single counter) - dyncfg Using the counting input IC3 of DcS I/O as AB-counter (B-signal) (IC3.2) (1=AB-counter, 0=single counter) - dyncfg Using the counting input IC4 of DcS I/O as AB-counter (A-signal) (IC4.1) (1=AB-counter, 0=single counter) - dyncfg Using the counting input IC4 of DcS I/O as AB-counter (B-signal) (IC4.2) (1=AB-counter, 0=single counter) - dyncfg

I O

Default Preset

X

0

X

0

X

16#00

2#0

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

X

2#0

Configuration variables for the PWM-Outputs (TPWMCFG) 160

Cfg.PWM.Used (BYTE)

320

CFG_QP

160.0

CFG_QP1_1

160.1

CFG_QP1_2

160.2

CFG_QP1_3

160.3

CFG_QP1_4

160.4

CFG_QP1_5

160.5

CFG_QP1_6

160.6

CFG_QP1_7

160.7

CFG_QP1_8

04 – 68 283000/A Version 1.0.0

Using the PWM-outputs 1 of DcS CPU (QD1.1..QD1.8) - dyncfg Using the PWM-output of DcS CPU (QD1.1) (Has to be set used as a digital output) - dyncfg Using the PWM-output of DcS CPU (QD1.2) (Has to be set used as a digital output) - dyncfg Using the PWM-output of DcS CPU (QD1.3) (Has to be set used as a digital output) - dyncfg Using the PWM-output of DcS CPU (QD1.4) (Has to be set used as a digital output) - dyncfg Using the PWM-output of DcS CPU (QD1.5) (Has to be set used as a digital output) - dyncfg Using the PWM-output of DcS CPU (QD1.6) (Has to be set used as a digital output) - dyncfg Using the PWM-output of DcS CPU (QD1.7) (Has to be set used as a digital output) - dyncfg Using the PWM-output of DcS CPU (QD1.8) (Has to be set used as a digital output) - dyncfg

Page N-21

to

8

X

0

1 to „0“ if X

0

2 to „0“ if X

0

3 to „0“ if X

0

4 to „0“ if X

0

5 to „0“ if X

0

6 to „0“ if X

0

7 to „0“ if X

0

8 to „0“ if X

0

N Table of Operands


%QB (Byte)

%QX (Bit)



Desription C P U


321

on I O

Default Preset

not used Configuration Variables for the General Functions of the Control Unit (TCOMMONCFG)

161

162

163

322

Cfg.Common. AwpCycle (BYTE)

CFG_AWPCycle

323

Cfg.Common. U_12_24 (BYTE)

CFG_U_12_24

324

Cfg.Common. CheckSRAM Startup (BYTE)

CFG_Check SRAMStartup

325

Cfg.Common. CheckSRAMRun (BYTE)

CFG_Check SRAMRun

326

Cfg.Common. CheckPRG Startup (BYTE)

CFG_Check PRGStartup

327

Cfg.Common. CheckPRGRun (BYTE)

CFG_Check PRGRun

04 – 68 283000/A Version 1.0.0

Setting a fixed AWP(appl. prog.)-cycle time [ms] (Range: 1 to 255ms) (If the actual cycle time of the AWP is longer than the adjusted one, the AWP will nevertheless be completely processed and the cycle time not kept) Configuring the system voltage level for the switching thresholds of the digital inputs (possible values: 12V or 24V) Configuring an SRAM test run in the startup of the DcS CPU (Notation: 2#nnnnSSSS) In the whole RAM, (n+1) Bytes each will be checked in step widths of ((S+1)*16). n: number Check bytes=n+1 0=1; 1=2; ..; 16#F=16Bytes S: Step width=S+1*16Byte 0=16; 1=32; ..; 16#F=256 Special values: 16#00=Test 1 Byte every 256 steps; 16#F0=Check of the whole RAM Configuring a continuous SRAM-check of the DcS CPU (Notation: 2#nnnnSSSS) In the whole RAM, (n+1) Bytes will be checked in step widths of ((S+1)*16) steps. n: Number Check bytes=n+1 0=1; 1=2; ..; 16#F=16Bytes S: Step width=S+1*16Byte 0=16; 1=32; ..; 16#F=256 Special values: 16#00= Check 1 Byte every 256 steps; 16#F0=Check of the whole RAM Configuring a flash-ROM test run in the startup of the DcS CPU (Notation: 2#nnnnmmmm) n = reserved; m = Mode: 2#0000=Check AWP-CRC (approx.100ms/16kByte) 2#0001=Check AWP-CKS (approx. 25ms/16kByte) 2#0010=Check FW-CRC (approx. 100ms/16kByte) 2#0011=Check FW-CKS (approx. 25ms/16kByte) 2#11xx=reserved, Bit0: 1=CRC, 0=CKS Configuring a continuous flash-ROM check of the DcS CPU (in every cycle) (Notation: 2#nnnnmmmm) n = reserved; m = Mode: 2#0000=Check AWP-CRC (approx. 185µs/16Byte) 2#0001=Check AWP-CKS (approx. 80µs/16Byte) 2#0010=Check FW+AWP-CRC (approx. 370µs/16Byte) 2#0011=Check FW+AWP-CKS (approx. 160µs/16Byte) 2#0100=Check FW-CRC (approx. 185µs/16Byte) 2#0101=Check FW-CKS (t approx. 8µs/16Byte) 2#1xxx := reserved, Bit0: 1=CRC, 0=CKS Special value: 16#00 = no continuous check

Page N-22

X

X

10#5

X

10#24

X

16#00

X

16#00

X

16#08

X

16#00

N Table of Operands


%QB (Byte)

%QX (Bit)



Desription

on C P U


I O

Default Preset

Configuration Variables for the CAN-Bus of the DcS I/O (TCANIOCFG) 164

165

328

Cfg.CAN.Mode (BYTE)

CFG_CAN_ Mode

329

Cfg.CAN.ModePa r (BYTE)

CFG_CAN_ Timeout

330

Cfg.CAN.Speed (EcanSpeed)

CFG_CAN_ Speed

331

Adjustment of the CAN-protocol of the DcS I/O (possible modes: 0=no mode, 1=MOBA, 2=Caterpillar J1939, 3=Deutz J1939) Adjustment of the Timeout of the CAN-bus of the DcS I/O in steps of [10ms] (0=no Timeout) Adjustment of the transmission speed of the CAN-bus of the DcS I/O in [EcanSpeed (see Prosyd.lib)]

X

2#0

X

10#200

X

KBD_ 125

not used

166

not used

:

:

195

not used Configuration Variables for the Control System (TSYSTEMCFG)

196

392

197

394

198

396

397 199

398

399

200 202

Max. number of Watchdog-resets. When this number of watchdog-resets is reached one after the other, the AWP will be deactivated Number of faultless AWP-cycles after which Cfg.Sys.cycles CFG_Cycles the internal Watchdog-reset-counter will be WDclear (WORD) ToClearWdg reset Mask for EMERGENCY-readouts on the CAN-bus: 16#00 = no message, Cfg.Sys.en_ 16#01 = NO_ERROR = normal message, CFG_Enable emergency 16#02 = WARNING = warnings, Emergency (BYTE) 16#04 = USER_ERROR = user error, 16#08 = APP_ERROR = application error, 16#10 = SYS_ERROR = system error, 16#1F = output of all Cfg.Sys.RTC_ CFG_RTC_DATE Flag for updating the Date & Time variables in Date_flag (BYTE) _FLAG SystemIn Configuring the character frame of the RS232 Cfg.Sys.ASC0_ CFG_ASC0_ of the DcS CPU CharLen (BYTE) CharLength (16#18 = 1 Stop bit & 8 Data bits) Configuring the parity error detection of the RS232 of DcS CPU Cfg.Sys.ASC0_ CFG_ASC0_ Parity (BYTE) PARITY (16#00 = no parity, 16#10 = EVEN-parity, 16#20 = ODD-Parity) Configuring the transmission rate of the Cfg.Sys.ASC0_ RS232 of DcS CPU CFG_ASC0_ Baudrate BAUDRATE (possible values: 2400, 4800, 9600, 19200, (DWORD) 38400, 57600) Cfg.Sys.maxWD reset (WORD)

CFG_MaxWdg Reset

not used

:

:

211

not used

04 – 68 283000/A Version 1.0.0

Page N-23

X

10#5

X

10#500

X

16#1F

X

2#1

X

16#18

X

16#00

X

10# 19200

N Table of Operands

04 – 68 283000/A Version 1.0.0

Page N-24


N Table of Operands

N.8 Notes

04 – 68 283000/A Version 1.0.0

Page N-25


N Table of Operands

04 – 68 283000/A Version 1.0.0

Page N-26


04-68283A Manual Digsy Chapter N Table of Operands

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