02 PLinesE User's Guide V1.1

pLinesE4 // pLinesE8 Communication Server User's Guide

Prepared by THALES Air Traffic Management

Ce document est la propriété de THALES ATM et ne peut être reproduit sans son autorisation

Page

1/32

User’s Guide

pLinesE4 and pLinesE8

18 03 04

Version 1.1

VERSION UPDATES

Document version

Modification date

1.0

25-11-03

1.1

18-03-04

Page or Paragraph

Comments Initial writing

all

New THALES logo

Ce document est la propriété de THALES AT M et ne peut être reproduit sans son autorisation

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Page 2/32

User’s Guide


18 03 04

Version 1.1

VERSION UPDATES

Document version

Modification date

1.0

25-11-03

1.1

18-03-04

Page or Paragraph

Comments Initial writing

all

New THALES logo


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Page 2/32


User’s Guide 18 03 04

Version 1.1

TABLE OF CONTENTS 1.

SAFETY PRECAUTIONS.......... PRECAUTIONS................................ ............................................ ............................................ ......................................... ................... 5 1.1

Power Supply .................................................................. ......................................................................................................................... ....................................................... 5

1.2

Static Electricity...................................................................... Electricity..................................................................................................................... ............................................... 5

2.

ABOUT THIS DOCUMENT......................................................... DOCUMENT............................................................................... .................................. ............ 5

3.

ABSTRACT.............................................. ABSTRACT....................... .............................................. ............................................. ............................................. ............................ ..... 6

4.

MATERIAL DESCRIPTION................ DESCRIPTION..................................... .......................................... ........................................... ................................ .......... 7 4.1

pLinesE features .................................................................. .................................................................................................................... .................................................. 7

4.2

Block diagram........................................................................................................................ 8

4.3 Processing unit main features............................................................................................ features............................................................................................... ... 9 4.3.1 Processor(s) .................................................................... ..................................................................................................................... ................................................. 9 4.3.2 Flash Memory........................................................................................... Memory.................................................................................................................. ....................... 9 4.3.3 SDRAM................................................................... SDRAM ........................................................................................................................... ........................................................ 9 4.3.4 SRAM............................................................................................................................ SRAM................................................................................................................. ........... 10 4.3.5 "System CPLDs" .................................................................... ........................................................................................................... ....................................... 10 4.3.6 "System FPGA" ................................................................ ............................................................................................................. ............................................. 10 4.3.7 "Communication FPGA" .................................................................. ............................................................................................... ............................. 10 4.3.8 Clocks circuit................................................................ circuit ................................................................................................................. ................................................. 11 4.3.9 Extra features.................................................................. features ................................................................................................................. ............................................... 11 4.3.10 Interrupt handling ......................................................................... .......................................................................................................... ................................. 12 4.4 Communication Ports ......................................................................... ......................................................................................................... ................................ 13 4.4.1 Synchronous/Asynchronous Ports ................................................................. ................................................................................. ................ 13 4.4.2 Features of multimode asynchronous/synchronous asynchronous/synchronous connections................................... 14 4.4.3 Serial ports diagram....................................................................................................... 15 4.5 Auxiliary Port .................................................................... ...................................................................................................................... .................................................. 16 4.5.1 Basics............................................................................................................................. Basics............................................................................................................................. 16 4.5.2 Connecting auxiliary ports ports between local and remote pLinesE .................................... 16 4.5.3 Protocol.......................................................................................................................... Protocol.......................................................... ................................................................ 16 4.6

PMC support.................................................................. support........................................................................................................................ ...................................................... 16

4.7

System Interface ............................................................... .................................................................................................................. ................................................... 17

4.8 Connectors Overview ......................................................................... .......................................................................................................... ................................. 18 4.8.1 Connectors location on the CPU board .......................................................... ......................................................................... ............... 18 4.8.2 Connectors pin assignments ...................................................... .......................................................................................... .................................... 19

5.

CHARACTERISTICS........................... CHARACTERISTICS..... ............................................ ............................................ ............................................ ............................. ....... 25 5.1

Physical Dimensions ............................................................... ............................................................................................................ ............................................. 25


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18 03 04

Version 1.1

6.

7.

User’s Guide

5.2

Power-supply........................................................................................................................ 25

5.3

Climatic Environment......................................................................................................... 25

5.4

Electromagnetic parameters............................................................................................... 26

5.5

Safety .................................................................................................................................... 26

SOFTWARE.................................................................................................................... 27 6.1

Basic Modules ...................................................................................................................... 27

6.2

Board Support Packages..................................................................................................... 28

SETTING UP .................................................................................................................. 29 7.1 Mechanical integration ....................................................................................................... 29 7.1.1 Self-adhesive Pads......................................................................................................... 29 7.1.2 Installation into a 19’’ cabinet ....................................................................................... 30 7.2

Switch On/Off ...................................................................................................................... 31

7.3 Integration hints .................................................................................................................. 31 7.3.1 Positioning the pLinesE................................................................................................. 31 7.3.2 Cabling Precautions....................................................................................................... 31 7.4

Parameter setting................................................................................................................. 31

8.

RELIABILITY (MTBF)................................................................................................. 32

9.

CORRECTIVE MAINTENANCE................................................................................ 32


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Version 1.1

1.

SAFETY PRECAUTIONS

1.1

Power Supply

Warning All operations on this device must be carried out by sufficiently skilled personnel.

Caution The power supply must always be disconnected before installation, repair and maintenance operations are carried out on this product. Failure to comply with this basic precaution will subject the operator to serious electrical shock hazards capable of causing death. Always unplug the power cable before such operations.

1.2

Static Electricity Electronic boards and their components are sensitive to static electricity. Therefore, care must be taken during all handling operations and inspections of this product, in order to ensure product integrity at all times.

2.

ABOUT THIS DOCUMENT This document contains information proprietary of THALES ATM. It may not be copied or transmitted by any means, disclosed to others without our prior written consent. The information contained in this document is, to the best of our knowledge, entirely correct. However, we cannot accept liability for any inaccuracies, or the consequences thereof, nor for any liability arising from the use or application of any circuit, product, or example shown in this document. We reserve us the right to change, modify, or improve this document without further notice.


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Version 1.1

3.

ABSTRACT The pLinesE product family is a line of communication computers designed to connect to : multimode asynchronous/synchronous communication ports • Ethernet 10/100Mbps networks • another product of this family for equipment redundancy purposes. • The pLinesE family is an enhancement of the previous µLines/PLines based on 68K/MPC860 processors and supersedes it. The pLinesE family comprises : • pLinesE4, featuring the full basic functions set and providing: • 4 multimode asynchronous/synchronous communication ports • 3 Ethernet 10/100 Base Tx ports • pLinesE8, providing • 8 multimode asynchronous/synchronous communication ports • 3 Ethernet 10/100 Base Tx ports. •

pLinesE8 + Exp (optional) , similar to pLinesE8, but providing slots either for PMC-PCI, or Ethernet daughter boards.

pLinesE4-8 is powered by one or two MPC8250/70, being part of the PowerQUICCII processor family. This embedded processor couples a 603e core wi th a RISC communication processor and three Fast Ethernet controllers. This processor provides 280MIPS@200Mhz in the basic version and up to 630MIPS for the high range version.

The communication processor implemented in the PowerQuiccII processes 4 high speed synchronous or asynchronous ports. On the pLinesE8 a second PowerQuiccII in slave mode provides optionally 4 additional asynchronous/synchronous ports. This product provides original and powerful functions that allows to build a communication redundant system by combining two pLinesE4-8 computers. This capabilities are ensured by a hardware security bus and watchdog that can isolate communication ports of one system. Isolated ports are in high impedance. pLinesE4-8 is supplied in a 1U 19” rack. The computer is provided with an standard AC/DC or an optional DC/DC converter. A front panel LCD-Keypad makes easier the utilization.

Others versions named pLinesE_VME provide the same functions for VME applications. This product family, based on the PowerQUICC II range, introduces new high-performance products to Interface Concept LINES range.


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18 03 04

Version 1.1

4.

MATERIAL DESCRIPTION

4.1

pLinesE features

User’s Guide

The pLinesE is packaged in a 19” / 1U box. Its operational connectors are gathered on the rear panel, whereas a terminal output, a 4 keys pad, a LCD, and a set of leds, are placed on the front panel. The pLinesE4, based on a POWERQUICCII processor, gives the following communication functions: • three Ethernet 10/100Mbps channels • four multimode asynchronous/synchronous ports capable of synchronous mode and asynchronous protocols such as HDLC, Bisync, Transparent, UART, Isochrones, etc. • asynchronous port, controlled by SMC1, with a RS232 interface accessible on the front panel. • one "Auxiliary Port" consisting of two input and two output lines with a RS422 transceiver, is available on the rear panel. The pLinesE8 uses two POWERQUICCII processors, one of them configured as a Master (enabled core), the second as a slave POWERQUICCII (disabled core). The master provides : • three Ethernet 10/100Mbps connections • four multimode asynchronous/synchronous ports capable of 10Mbps (1) in synchronous (differential mode) and up to 4Mbps (1) in asynchronous mode • one asynchronous port, controlled by SMC1, with a RS232 interface, is accessible on the front panel. • one "Auxiliary Port" consisting of two input and two output lines with a RS422 transceiver, is available on the rear panel. The slave provides : • four other multimode asynchronous/synchronous ports with the equivalent features Options are available on pLinesE8 : • daughter boards for three optional Ethernet 10/100Mbps connections • reserved footprint may be optionally equipped to provide a slot for 32bits/33MHz PCI/PMC • daughter boards for customer expansion to use the available function of the CPM of the slave PowerQuiccII, TDM channels for instance.

Multi-mode ports are mainly DTE compliant, however it can be configured in DCE mode with some restrictions. They allow a number of software programmable electrical modes, selectable by port. Each channel have V.35 and V.11 Receiver Termination Network . Note : 1. Those values correspond to the maximum speed provided by the Communication Processor implemented in the PowerQuiccII. Software configuration or electrical parameters of a channel could reduce those performances (250Kbps for V28, etc) .


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User’s Guide


18 03 04

Version 1.1

4.2

Block diagram The diagram below shows the pLinesE organization and expansion possibilities. +5V=> Line transceivers, LCD, Fans I/Os => uP, SDRAM, Ethernet Transceivers, Fpgas

5V=> 3.3v / 4A Switching regulator

Power Supply

PowerQuiccII core

Switching regulator

Quad Eth transformer

Ethernet Transceivers PHY1

Eth Optional SDRAM 32 bit local bus

PH2

Eth Eth

PHY3

From ‘’System FPGA’’

Security port Transc

Terminal

RJ45

2 3 2 S R

local S M C

FCC

PQII Master

I²C optional E²prom

Com. FPGA

S C C

Ports 1 to 4

CPLD Sys s s h e r c d t a d l A

s r h C 0 D 2 * C L s w o r 2

Transc

Transc

Bus 60x 4 keys ad

Transc

FPGA system

@

CPLD Mux

4*Stacked DB25 Connectors

SDRAM 64 bit wide

s a r t e a f f D u B

data bus

T° monitoring Transc

Flash A 16bit Opt Flash B 16bit

SRAM 8bit / 128ko

SuperCap

Opt. RTC

Bus 60x Transc

v s r

S M C

PQII Slave

PCI

S C C

Com. FPGA

Ports 5 to 8

Transc

Transc

FCC

PMC-PCI 32 3v3 33/66 MHz Optional PMC board

Optional Com. extension


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Version 1.1

4.3

Processing unit main features

4.3.1

Processor(s) Main features (pLinesE4): • Processor: Motorola POWERQUICCII providing 280 MIPS at 200 MHz 64-bit 32MB SDRAM on PowerPC (60x) bus, • 16-bit 8MB • three Ethernet 10/100Mbits ports using POWERQUICCII's FCC ports • four multi-protocol serial ports using PQII's SCC ports interfaced through four multimode • transceivers Additional features ( pLinesE8) owing to a second Motorola POWERQUICCII processor configured in Slave mode : Four additional multi-protocol serial ports interfaced through four multimode transceivers • Optional expansion for 3 ports Ethernet 10/100Mbs daughter boards • Optional expansion to PMC/PCI 32bits/33/66MHz boards • In the basic configuration the operating frequencies are : • Bus (system clock) .................................... : 66 MHz CPM .......................................................... : 133 MHz • Core ........................................................... : 200 MHz •

Others values are available on demand. The CPU’s frequency will be up to 450Mhz with a CPM’s frequency up to 300Mhz.

4.3.2

Flash Memory The flash memory is based on AMD CMOS technology. This memory bus width is 16-bit only. The basic capacity is 8MB (64 Mbits), in one device. This memory bank is divided in 128 sectors of 64KB. The sixteen first sectors are reserved for the Interface Concept firmware. This Flash memory can be extanded following two ways : Increase the capacity of the first chip up to 32MB • Equip a second flash component with the same features. • Today the available chips allow a maximal capacity of 64MB of flash memory.

4.3.3

SDRAM Main SDRAM : 60x bus The basic memory capacity is 32 MB, expandable to 64 or 128 MB according to the factory equipment. The bus is 64-bit wide. The 8, 16, 32 or 64 bits access are allowed. Optional SDRAM on Local bus A reserved footprint may be optionally equipped to provide an additional 32 bit wide, 16 MB SDRAM, accessed via the master PQII local bus.

In case of intensive communication data flows (configuration with many Fast Ethernet channels at full-speed), this option may be interesting.


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18 03 04

Version 1.1

4.3.4

User’s Guide

SRAM The pLinesE is delivered with a 128KB SRAM. This memory area is accessible via an 8-bit bus. This SRAM can be backuped by an optional ‘’supercapacitor’’ ensuring 48 hours data retention. This range will be obtained after at least four hours of operation. If main AC/DC is off, SRAM data may be erased by shorting its power supply (discharging the capacitor) using a dedicated jumper.

4.3.5

"System CPLDs" Includes the following modules : RESET logic • Processor start-up resources ("MPC8250 configuration word") • • Access control to 8 and 16-bit peripherals (buffer and acknowledgment control) • FPGA configuration Status and control registers • A second CPLD functionality provides SDRAM address multiplexing, according to the memory devices size and organization.

4.3.6

"System FPGA" The System FPGA provides the following features : Identification, Status and Configuration registers • Watchdog (places line interfaces in Hi-Z state + asserts interrupt or full reset) • Auxiliary port • • Interrupt request formatting, queuing, status, and handling: Ethernet events (link up, etc) o Auxiliary port o Temperature trip points o o Expansions Calendar o Line interface configuration: • Electrical mode / Loopback o Communications clocks redirect o Transmission buffer control (Tx_En) o • Peripherals access control: Calendar (option) o User LED control (on board) •

4.3.7

"Communication FPGA" A FPGA implements additional functionalities of 4 SCC multimode ports managing (Ports 1-4). pLinesE8 uses also a FPGA for the extra 4 serial ports (5-to 8). They provide the following features : • Identification, Status and Configuration registers • Communication clocks management Mode selection (DTE/DCE ...) in option •


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Version 1.1

4.3.8

Clocks circuit System clocks : • A 66.66 MHz 100ppm oscillator supplies processor input Clock. • A 50 MHz oscillator supplies the reference frequency for board time base.

Note : For pLinesE8, the PCI-PMC clock is generated by the PO WERQUICCII from the 66.66 MHz system clock. The 33.33 or 66.66 MHz is selectable by software. Ethernet and Time Base clock A 50 MHz 25ppm oscillator supplies the reference for Ethernet ports. Optional reference clock A footprint is reserved for an optional oscillator for specific applications.

Example : a 14.7456 MHz oscillator can theoretically supply an error-free 38400 baud clock reference.

4.3.9

Extra features

4.3.9.1 Temperature monitoring The pLinesE uses a standard dual trip point temperature monitor adjustable using external resistors. In the basic configuration the trip points are set at +55°C and +70°C . The first point corresponds to the maximal admissible operational temperature and the second point the absolute maximal running temperature. The monitor circuit is wired to the F PGA which may generate an interrupt when a temperature threshold is exceeded.

4.3.9.2 Fans monitoring Two long-life fans are installed in the pLinesE box. The rotation of each fan is monitored. In case of default an interrupt is generated towards the processor.

4.3.9.3 I2C EEPROM An user’s optional 16-kbit EEPROM can be installed for data backup. This component can be used through the I²C bus available on the PowerQuiccII.

4.3.9.4 Real Time Clock / Calendar An EPSON RTC7301SF clock/calendar can be installed as an option. This component allows to implement a independent calendar clock with hh/mn/ss:yyyy/mm/dd capabilities. Besides regular calendar functions, it can be set to generate interrupts on a specific date. This very low-power circuit is compatible with the SRAM data backup, and can use a ‘’supercapacitor’’ for backup.


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User’s Guide


18 03 04

Version 1.1

4.3.10 Interrupt handling The following diagram reviews the various interrupt sources in a pLinesE.

P

PQII Slave

II Master

Irq_PCI IRQ[7..0] DSR[5..8] = PC[0..3]

SWT Mem Control Data Error PCI_Err# Bus Monitor address IRQ0

NMI_OUT INT_OUT

OR

MCP#

IRQ[0]#

Fpga “System” Irq#_LTX971 Irq#_Expansion Temp Treshold N°1 Temp Treshold N°2

IRQ[7..0] IRQ[1]#

Level

Falling edge or Level

Int#

TMCNT PIT

IRQ[2]#

Polarity Status Output selection

PPC G2 Core

Falling or rising Edge Timer 1 Timer 2 Timer 3 Timer 4

IRQ[3]#

IRQ[4]# FCC 1 FCC 2 FCC 3

Edges Keypad RTC Com. ports P[1-4] Com. ports P[5-8]

CPM = level 4

Polarity Synchro Latch Status Acquittement

MCC 1 MCC 2

IRQ[5]#

SCC 1 SCC 2 SCC 3 SCC 4

IRQ[6]#

DSR[1..4] = PC[0..3]

Auxiliary Port • Command Fault • Command Def • Activity Event • Activity Fault

SMI#

SMC 1 SMC 2

IRQ[7]#

Watch Dog HTR Fans rotation

r e l l o r t n o C t p u r r e t n I

SPI I²C

PC[4]#

IDMA 1 IDMA 2 IDMA 3 IDMA 4

Port C [15..0]

SDMA

PC[5]#

Risc Timers Rsv

PC[6]#


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Version 1.1

4.4 4.4.1

User’s Guide

Communication Ports Synchronous/Asynchronous Ports SCC channels [1.. 4] from master CPM (1) used to control the four main channels of a pLinesE4 (P1..P4), whereas SCC channels of slave are used to control pLinesE8 ( P5..P8). The main communication protocols allowed by these SCC controllers are : Asynchronous standard mode or with an external bit clock (isochronous) • Synchronous mode with : • Transparent flow o HDLC o Bisync o Ethernet 10M o The electrical multimode features of communications ports are provided by multi-mode line interface chips SIPEX SP508. These integrated circuits are software configurable and support various electrical modes (V10, V11, V28, V35, High impedance). The [1..8] channels can be set up independently for : EIA 530 (V11 & V10 modes) • EIA 530A (V11 & V10 modes) • RS232 (V28 mode) • RS449 – V36 (V11 & V11 modes) • X21 (V11 mode) • • V35 (V35 & V28 modes) • High impedance They support fast 10Mbps differential transmission rates. The real data rates also depend on the channel configuration (CPM). They also support an internal termination resistor for V11 or V35 mode. These adaptation’s networks can be disconnected by software. pLinesE is configured for DTE mode but, in option, with some restrictions it can be used in DCE mode.

Note 1 : •

CPM = Communication Processor Module implemented in the PowerQuiccII.


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Version 1.1

4.4.2

User’s Guide

Features of multimode asynchronous/synchronous connections The following table shows the lines available for each serial port : Name TxD RxD RTS CTS DTR DSR DCD RxC TxC TxCC RI TI RL LL

Function Transmit data Receive data Request to send Clear to send Data terminal ready Data set ready Data carrier detect Receive clock Transmit clock Transmit clock Ring indictor Terminal Remote loop back Local loop back

DTE Mode O / HIZ (1) I O I O I I I O I I I O O

DCE Mode (1) O (1) I O I O I O I O O I I O O

(O) = Output ; (I) = Input

Input lines (CTS, DSR, DCD) may generate an interrupt upon change of state. The factory and contractual configuration is DTE. For DCE mode a few restrict ions may appear in new version of pLinesE’s. The driver/receiver affectations are not swapped between DCE, DTE configurations. For this reason in DCE mode for each line, the external connection must use the right pins in the connector. Note 1 : •

To take in charge alternate protocol in network data link like RS485, this driver can be set in high impedance by software and/or hardware


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User’s Guide


18 03 04

Version 1.1

4.4.3

Serial ports diagram

FPGAs

Associated Functions

Control Alternat

"Envelope Mode"

Line Interfaces SP508

3V3

5V

µ TxD

µ RTS

i TxD F_TEN

i TEN

F_RTS

i RTS

103

TxD_A TxD_B

105

RTS_A RTS_B ST

i_TCk i

µ TCK io

i TCk o

DTE/DCE capability

µ DCD Dte Dce

_DCD io

1k

TxCKi_A TxCKi_B

113

TxCKo_A TxCKo_B

109

_DTE#_DCEh

F_DTE_DCE RxC Multiplexing

114

µ RxC

i_RxC

µ RxD

i_RxD

µ CTS

i_CTS

Level Translation

115

RxC_A RxC_B

105

RxD_A RxD_B

106

CTS_A CTS_B

Level Translation F_RL RL, LL control registers

Ri, Ti status registers

Mode Control Hi Z Conteol

i_RL

F_LL

i_LL

Fi_Ri

i_Ri

F_Ti

i_Ti

F_Mo

i_M0

F_M1

i_M1

F_M2

i_M2

DCD_A DCD_B

140 141

RL LL

125

Ri

142

Ti

(WD, Rst, Soft) Clk100mS

Leds TxD Leds RxD

Command and Flashing Leds Rx, Tx

TR control register

µ PA

i DTR

µ PC

i_DSR


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108

107

DTR_A DTR_B DSR_A DSR_B

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Version 1.1

4.5

Auxiliary Port

4.5.1

Basics The pLinesE was designed for the purpose of providing a redundant system, connecting 2 boxes “in parallel”. One of them is active, the other one is inactive, placed in “High impedance”. In order to control the system, each pLinesE has a RS422 compliant port consisting of two input and two output lines ( 120ohms “dynamic” impedance). In the absence of an operating remote device, the logic level of input lines is defined by bias resistors.

4.5.2

Connecting auxiliary ports between local and remote pLinesE The auxiliary ports have to be connected “point to point” via a crossing 8 wires ribbon cable.

pLines E «A»

4.5.3

A A A A

S S E E

ACT CMD ACT CMD

B B B B

S S E E

ACT CMD ACT CMD

pLinesE «B»

Protocol The 2 outputs of a device provide a 50Kb/s coded information to the inputs of the opposite device, which verifies frames and data format at low level, and gives “Activity” and “Command” information to the software. For each input channel : • A status information is available in an FPGA register • An interrupt request is generated when data changes • An interrupt request is generated in case of error ( frame length, data format …)

4.6

PMC support Mezzanine card connectors can be installed as an option on the pLinesE8. These connectors link to the local bus of the POWERQUICCII operating either as a traditional 32-bit 66MHz processor bus, or a 32-bit 33/66MHz PCI bus. The POWERQUICCII does not accept 5V, only 3.3V or Universal PCI-PMC boards, or 3.3V I/O boards, are supported. To obtain more information about the PCI bridge capabilities see the MPC8265 user’s guide. Only a Non-Monarch PMC works on the pLinesE.


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Version 1.1

4.7

System Interface The front panel provides the following elements to the user’s : 2 status LEDs: • Power => ON (Green) / OFF ( led OFF) o CPU => o Inactive :.................................................................... OFF Active, waiting for software initialization ................ RED Initialization successfully performed ....................... GREEN 3 pairs of leds for Ethernet ports • 100 : 10Mbits = OFF, 100Mbits = ON o Link/Activity = OFF: no link. ON: link plus blinks when TX or Rx activity o • 4 pairs of leds (pLinesE4) or 8 pairs of leds (pLinesE8) for communication ports status. Bottom leds: OFF= no reception // YELLOW = Rx activity o Top leds: OFF= no transmission // GREEN = Tx activity o When a port is three-stated, the leds blink at ½ second rate. o 1 small keypad ( 4 keys ) to allow pLinesE configuration • A 2 rows, 20 characters LCD, with backlight under control of software. • • 1 RJ45 Auxiliary Port connector for terminal connection   

Front panel

Ethernet

R1 R2R3 R4

1 2 3

T1 T2T3 T4

Board Status 3*2 Leds Power Ethernet

Serial Ports P[1..4]

R5 R6 R7 R8

T5 T6 T7 T8

Serial Ports P[5..8]

Console

RJ45 to Terminal

LCD

Keypad

The Rear Panel gathers the different connectors (Standard mains male plug) : 4 / 8 SubD25 sockets ( synchronous / asynchronous communication ports ) • 1 Quad RJ45 block for 3 Ethernet ports and Auxiliary port • • A reservation is pre-cut out for easy mounting of a PMC bezel Rear panel Expansion Board

Provision for PMC fitting

P7

P5

P3

P1

AUX Eth1

P8

P6

P4

P2

Eth2 Eth0

4* SubD25 ( pLines8 )

Auxiliary port 3* 10/100 Mb Ethernet

4* SubD25 ( pLines4 )


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Mains

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Version 1.1

4.8

Connectors Overview

4.8.1

Connectors location on the CPU board Fan1 Power

FAN 1

Fan2 Power

FAN 2

Eth 1 Eth 0 AUX

+5V from AC/DC module Power Sense.

Eth 2

Ports -

Terminal

Keypad Ports -

JTAG (programmable

JTAG/COP (MPC8250 chain)

LCD

Ports Super-Cap Shortcircuit jumper I2C E²PROM

Ports 4..6 Ethernet EXT

PMC-PCI


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Version 1.1

4.8.2

Connectors pin assignments

4.8.2.1 Communication ports P[1..8] pLinesE4/8 provides signals from 4/8 asynchronous/synchronous ports in standard female SubD25 connectors. Pin assignments are shown in the table below: Mode DB-25 Pin-out

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

RS232 (V.28)

DTE

out in out in in in in in out in in out in in in out

Signal Name

Shield TxD RxD RTS CTS DSR GND DCD

Electrical Level

V28 V28 V28 V28 V28 V28

TxCC

V28

RxClk

V28 V28

LL

out out

DTR

out

RL

in out out

TxC

in

Ti

V28 V28

V28 V28

EIA-530 Signal Name

Electrical Level

Shield TxD(a) RxD(a) RTS(a) CTS(a) DSR(a) GND DCD(a) RxClk(b) DCD(b) TxC(b) TxCC(b) CTS(b) TxD(b) TxCC(a) RxD(b) RxClk(a)

V11V11+ V11+ V11+ V11+ V11+ V11+ V11V11+ V11-

LL

V10

RTS(b) DTR(a)

V11+ V11-

RL

V10

DSR(b) DTR(b) TxC(a)

V11+ V11+ V11-

Ti

V10

V11V11V11V11V11-

RS422 (.V11) Signal Name

Electrical Level

Shield T(a) R(a) C(a)

V11V11V11-

GND I(a)

V11-

I(b)

V11+

S(b)

V11+

T(b) S(a) R(b)

V11+ V11V11+

C(ba)

V11+

V.35 Signal Name

Electrical Level

101 103(a) 104(a) 105 106 107 102 109 115(b)

V28 V35+

113(b) 114(b)

V35+ V35+

103(b) 114(a) 104(b) 115(a)

V35+ V35V35+ V35-

113(a)

V35-

V35V35V28 V28 V28

This table uses (A, B) to designate the following: A indicates inverted inputs and outputs • B indicates non-inverted inputs and outputs • The cable shield is coupled to the frame via the connector body. The coupling is provided by screws on the front panel and by grounding clips.


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4.8.2.2 Ethernet 10/100TX Ports The three Ethernet 10/100TX ports present on the pLinesE board output to a Quad RJ45 type female outlet (2 stacked rows). Three jacks are occupied by Ethernet ports, the 4 th is used by the auxiliary port. Ports are numbered as indicated after (FCC1 = Eth 0, FCC2 = Eth 1, FCC3 = Eth 2). Ethernet ports are coupled to MPC8250 Master’ FCCs via LXT971A transceivers. AUX

Eth. 1

Eth. 2

Eth. 0

Each port is associated with a led pair on front panel / ON : 100Mbit • Bottom: “100” ...... : Off: 10MBit • Top: Link/Activity”... : ON (permanent) = Link present Blink : follows Rx/Tx activity

The three Ethernet ports use the following distribution:

Pin N° 1 2 3 6 4,5,7,8

Function Tx+ TxRx+ Rxfeed back circuit

Note : Feed Back circuit is provided by 100 ohms terminators.

4.8.2.3 "Auxiliary" port The "auxiliary port" ( the four th-jack RJ45 of the quad back panel block), operates in RS422 mode. Signal distribution is shown in the table below: Pin 1 2 3 4 5 6 7 8

Function S_ACT+ S_ACTS_CMD+ S_CMDE_CMDE_CMD+ E_ACTE_ACT+

Comment “Auxiliary Port Activity status” output to opposite pLinesE (Differential pair) “Auxiliary Port Remote command” output to opposite pLinesE (Differential pair) “Remote command”input from opposite pLinesE (Differential pair) “Auxiliary Port Activity status” input from opposite pLinesE (Differential pair)

This distribution enables two pLinesE boards to interconnect via a ribbon cable. Notice that the pin-out allows proper connection using standard connector mounting at one end of the ribbon cable, whereas the second end is simply inverted.


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4.8.2.4 SMC1 port of MPC8250 (Master) The SMC1 serial port is set to operate in RS232 mode. The port is wired to a RJ45 connector placed on the front panel. Pin N° 3 4 5 1,2,6,7,8

Function GND TxD RxD unused

4.8.2.5 JTAG programmable devices connector A JTAG chain gathers the 4(pLinesE4) or 5(pLinesE8) programmable devices in the following order: N° in Chain 1 2

3 4 5

Device PLD Max3064TC100-10 PLD Max3064TC100-10

Function “System”= board/processor control “Mux”: SDRAM Address multiplexer

TDO

TDO

Fpga EP1K30QC208-3 Fpga EP1K30QC208-3 Fpga EP1K30QC208-3

“System” Communication ports [1-4] Communication ports [5-8] (pLinesE8)

The 2 PLDs may be directly programmed using a JTAG tool (Altera “Byte Blaster”) terminated by a HE10-10 male connector. The signal distribution complies with ALTERA recommendations. Pin no. 1 2, 10 3 4 5 7 9 6, 8

Function TCK GND TDO 3.3V TMS TRST# (unused) TDI NC

4.8.2.6 COP/JTAG emulation probe connector The COP/JTAG port accommodates emulation probes and complies with Motorola specifications. However, minor differences may emerge when using probes from third-party suppliers. Please refer to supplier's specifications. The port uses an HE10-16 type male connector. Pin Function 1 TDO 3 TDI 5 Q_REQ# 7 TCK 9 TMS 11 SRESET# 13 HRESET# 15 CHKSTOP_OUT

Function Q_ACK# TRST# Power Sense unused unused GND unused GND


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Pin 2 4 6 8 10 12 14 16

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4.8.2.7 Display connector The display connector is an HE10-16 positions male model. Signal assignment is as following: Pin

Function

(RowA)

1 3 5 7 9 11 13 15

+5V RS E (Enable) Data[1] Data [3] Data [5] Data [7] Backlight[-]

Pin (RowB) GND 2 Brightness 4 Rh/Wl 6 Data [0] 8 Data [2] 10 Data [4] 12 Data [6] 14 Backlight[+] 16

Some displays from the market, although compatible for all other signals, have backlight polarity inverted. Adaptation is possible by means of the GR246 / GR247 pads By default GR246 GR247

Pin N° 1-2 2-3

Function Backlight[-] <= Control line Backlight[+] <= Vcc +5V

Note : •

The indicated Backlight polarity corresponds to the default configuration.

4.8.2.8 MPC8250 I2C and SMC ports I2C and SMC ports of the MPC8250 slave of pLinesE8 are connected to a foot print, non equipped in standard, but which could be fitted with a high density HE10 20 positions smt connector. Pin assignment is the following : Pin N° 1 3 5 7 9 11 13 15 17 19

Function S_SMC2_TxD S_SMC2_RxD S_SMC1_TxD S_SMC1_RxD M_SMC2_TxD M_SMC2_TxD GND GND S_I2C_SCL M_I2C_SCL S_I2C_SDA M_I2C_SDA +3.3V +5V Rsv_PGA_Sys Rsv_PGA_Sys Rsv_PGA_Sys Rsv_PGA_Sys M_PC[6] M_PC[4]

Pin N° 2 4 6 8 10 12 14 16 18 20

Note : •

M prefix corresponds to Master 8250. S prefix corresponds to Slave 8250. Besides I²C and SMC ports , 4 wires are connected to “System” FPGA


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4.8.2.9 PMC expansion connectors PMC-PCI type connectors can accept a PMC expansion board, according to VITA 32-bit PMC-PCI specifications "host" board.

Jn1 (32-bit PCI)

Pin Signal name 1 TCK 3 GND 5 INTB# 7 PRESENT# 9 INTD# 11 GND 13 CLK 15 GND 17 REQ# 19 V(I/O) 21 AD[28] 23 AD[25] 25 GND 27 AD[22] 29 AD[19] 31 V(I/O) 33 FRAME# 35 GND 37 DEVSEL# 39 GND 41 SDONE# 43 PAR 45 V(I/O) 47 AD[12] 49 AD[09] 51 GND 53 AD[06] 55 AD[04] 57 V(I/O) 59 AD[02] 61 AD[00] 63 GND

Signal name NC INTA# INTC# +5V PCI RSVD +3.3V_Aux GND GNT# +5V AD[31] AD[27] GND C/BE[3]# AD[21]# +5V AD[17] GND IRDY# +5V LOCK# SBO# GND AD[15] AD[11] +5V C/BE[0]# AD[05] GND AD[03] AD[01] +5V REQ64#

Jn2 (32-bit PCI)

Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64

Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

Signal name NC TMS TDI GND PCI RSVD BUSMODE2# RST# +3.3V PME# AD[30] GND AD[24] IDSEL +3.3V AD[18] AD[16] GND TRDY# GND PERR# +3.3V C/BE[1]# AD[14] M66_EN AD[08] AD[07] +3.3V PMC RSVD PMC RSVD GND ACK64# GND

Signal name TRST# TDO GND PCI RSVD PCI RSVD +3.3V BUSMODE 3# BUSMODE 4# GND AD[29] AD[26] +3.3V AD[23] AD[20] GND C/BE[2]# IDSELB +3.3V STOP# GND SERR# GND AD[13] AD[10] +3.3V REQB# GNTB# GND EREADY# RESET_OUT# 3.3V MONARCH#

Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64

The same connectors can accept specific expansion boards using a "processor" bus (reserved use). The pLinesE can provide to the PMC board a DC electrical power of 10Watts either on the 5VDC or on the 3.3VDC.

Caution : The pLinesE PCI bus is only compatible with a 3.3VDC signaling.


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4.8.2.10 Optional connector for extra 3 Ethernet ports A non equipped footprint could optionally be fitted with a « PMC type » connector, gathering the MII ports of the PowerQuiccII slave (pLinesE8). This connector could then be a mother slot for a daughter board fitted with transceivers providing three extra Ethernet ports.

P33

Pin Signal name 1 +5V 3 INT_EXT_ETH 5 +3.3V 7 EXT_MII_MDC 9 EXT_MII_MDIO 11 ETH3_RxD3 13 ETH3_RxD1 15 ETH3_RxCk 17 ETH3_RxErr 19 ETH3_TxErr 21 ETH3_TxCk 23 ETH3_TxD3 25 ETH3_TxD1 27 ETH3_Col 29 ETH2_RxD3 31 ETH2_RxD1 33 ETH2_RxCk 35 ETH2_RxErr 37 ETH2_TxErr 39 ETH2_TxCk 41 ETH2_TxD3 43 ETH2_TxD1 45 ETH2_Col 47 ETH1_RxD3 49 ETH1_RxD1 51 ETH1_RxCk 53 ETH1_RxErr 55 ETH1_TxErr 57 ETH1_TxCk 59 ETH1_TxD3 61 ETH1_TxD1 63 ETH1_Col

Pin Signal name 2 EXT_PRSNT1 4 HRESET# 6 +3.3V 8 GND 10 GND 12 ETH3_RxD2 14 ETH3_RxD0 16 GND 18 ETH3_RxDV 20 ETH3_TxEn 22 GND 24 ETH3_TxD2 26 ETH3_TxD0 28 ETH3_CRS 30 ETH2_RxD2 32 ETH2_RxD0 34 GND 36 ETH2_RxDV 38 ETH2_TxEn 40 GND 42 ETH2_TxD2 44 ETH2_TxD0 46 ETH2_CRS 48 ETH1_RxD2 50 ETH1_RxD0 52 GND 54 ETH1_RxDV 56 ETH1_TxEn 58 GND 60 ETH1_TxD2 62 ETH1_TxD0 64 ETH1_CRS

Only available on the pLinesE8


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5.

CHARACTERISTICS

5.1

Physical Dimensions Parameter

Width Height Depth Weigth

5.2

User’s Guide

Nominal range 19” 1U (44,45mm) 170 mm 2500 grams

Power-supply The main electrical specifications are shown in the following table: Parameter

value 90 – 264VAC 47 – 70 Hz 20ms < 0.5mA 50/60Hz 264VAC < 18 Amp (115VAC) < 36 Amp (230VAC)

Input range Frequency Hold-up time at 115VAC Safety ground leakage current Inrush current

5.3

Climatic Environment The table below outlines the operating environment. Parameter Ambient Air temperature Humidity (non-condensing) Temperature gradient Pressure

Nominal range 0-55°C 10-95% ±20°C/h 85-110kPa

The table below outlines the storage environment : Parameter Air temperature Humidity (non-condensing) Temperature gradient Pressure

Nominal range -25 to 65°C 5 to 95% ±25°C/min 65-110kPa


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5.4

Electromagnetic parameters The table below outlines the CE parameters obtained by these products. Nature of perturbations ESD discharge HF radiation Spikes

Standards EN61000-4-2 EN61000-4-3 EN61000-4-4

Shock waves

EN61000-4-5

Common HF tests Alimentation Variation Electromagnetic emission Electromagnetic emission

EN61000-4-6 EN61000-4-11 EN55022 EN55022

Severity TT/TR 10V/m +/-2kV +/-2kV +/-2kV +/-2kV CT/CR CT/CR B B

Comments +/-6kV contact, +/-8kV AIR 80 to 1000Mhz - AM80% in power supply on bus in power supply on bus

Conduction Radiation

To obtain these values, use a properly grounded shielded cable.

5.5

Safety The table below outlines the safety environment : Parameter Human safety Isolation PS input / chassis

Reference EN60950 1500 VAC 1mn


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6.

Software

6.1

Basic Modules Several software configurations are available for pLinesE. The basic configuration is described in the following table:

Hardware independent software

Hardware dependent software

Hardware

IC_Tools

IC_Boot

IC_Bios

Power PC Core MPC8260 serial controller Memory controller Clock timer Interrupt controller Ethernet controllers

Watchdog (FPGA) Line transceivers Flash device PCI interface I²C interface Auxiliary functions

Functionalities of the different modules : • The IC-Boot handles the board initialisation, the FPGA configuration and the self-tests, • The IC-Bios consists of several functions which best simplify the access to components (Flash programmer, …), The IC-Tools gather a set of services for the board operation, such as Board Self Test Utility, Flash • start configuration, Ethernet loading (BootP), … The board setting may be done of different manners : Using an “emulator” probe via the JTAG port, • Running debug tools on serial port • • Powerful debug via Ethernet port.


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6.2

Board Support Packages In addition to these modules, Interface Concept has ported on this board several operating systems. In this case, we can deliver as an option a “Board Support Package” module specific to each system. The systems, which are currently available, are the VxWorks and LINUX. In the case you are using an operating system, the application is set up in the following way:

Application Software

Hardware independent software

Hardware Dependent software

Hardware

Kernel

I/O system

BSP RTOS or Linux

IC_Bios

PowerQuiccII and peripheral functions


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7.

SETTING UP

7.1

Mechanical integration An “installation kit”may be delivered, providing 4 adhesive pads and 2 mounting flanges allowing the use of pLinesE either on a table, or in a 19”cabinet. Master Communication Processor

Slave Communication Processor only on pLinesE8

PMC Slot

7.1.1

Self-adhesive Pads The unit is supplied with four self-adhesive pads. If the unit is to be part of a free standing stack, stick the pads to each marked corner on the underside of pLinesE. Note : •

Do not use the pads if you intend to mount the unit into a 19"cabinet


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7.1.2

User’s Guide

Installation into a 19’’ cabinet To fit the mounting flanges : 1. Remove “A” and “B(1) screws from each corner 2. Fit the corner plate (they are symmetrical, one for left, one for right) using “A” and “B(1) screws the longer screws from the engineering kit.

B

B(1) A


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7.2

User’s Guide

Switch On/Off Plug the inline cable to switch the pLinesE ‘’ON’’ Unplug the inline cable to switch it ‘’OFF’’.

7.3

Integration hints

7.3.1

Positioning the pLinesE When deciding the working location of the pLinesE, ensure : Water and moisture cannot enter the case unit • • Airflow around the unit and through the vents in the side of the case is not restricted. Interface Concept recommend that you provide a minimum of 50mm clearance.

7.3.2

Cabling Precautions Shielded cables are mandatory and they must be correctly connected. To obtain reliable transmissions : • Connect the pLinesE to earth, using a 2.5mm² (minimum) cable, to the ground screw on the rear panel. • All cables shield must be tied to chassis via the plug hood, and the plug hood must be screwed to its receptacle. The RJ45 sockets are only usable for data link. Cables must be far from any source of electrical noises such as radios, broadband amplifiers, power lines and fluorescent lighting fixtures.

7.4

Parameter setting See the pLinesE Firmware user’s manual.


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02 PLinesE User's Guide V1.1

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