This is a laboratory report for fluid flow regimes.
TorsionFull description
hydrauic abFull description
inorganic chemistry
...Full description
Hydrology
Exp 5Full description
Dry Experiment using Microsoft ExcelFull description
study of petrol and diesel engineFull description
...Full description
Calorimetry is a process of measuring the amount of heat involved in a chemical reaction or other process.
experiment 11
Dry Experiment using Microsoft ExcelDescripción completa
Full description
experiment report
asynchronous counters
KPI
CIT-EEE-09EE48-LAB CIT-EEE-09EE48-LA B MANUAL – EXP EXP NO:10
EXPERIMENT NO : DATE :
DESIGN OF ASYNCHRONOUS AND SYNCHRONOUS COUNTER
AIM:
To design
i) 3 bit asynchronous up counter ii) 3 bit synchronous down counter iii) mod 10 counter (decade counter) iv) 4 bit synchronous counter using JK flip flops.
APPARATUS REQUIRED: . IC Trainer kit Counters:
Flip flops can be connected together to perform counting operation. Such group of flip flop is a counter. Counters can be classified into two broad categories according to the way they are clocked: as ynchronous and synchronous counter Asynchronous counter: An asynchronous counter is the one in which the flip flops within the counter do not change states at exactly the same time because they do not have a common clock pulse. In fact the first flip flop is clocked by the external clock pulse and then each successive flip flop is clocked by the output of the preceding flip flop. i) 3 bit asynchronous up counter:
Circuit diagram:
1
CIT-EEE-09EE48-LAB MANUAL – EXP NO:10
Truth Table: CLOCK PULSE
Q2
Q1
Q0
Initially
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8 recycles
0
0
0
Timing Diagram for 3 bit up counter:
Asynchronous counters are commonly referred to as ripple counters. From the above timing diagram it is clear that the effect of clock pulse is first “felt” by flip flop 0. This effect gets propagated to the flip flop 1 only after the propagation delay through flip flop 0. Then , there is propagation delay through flip flop 1 before flip flop 2 gets triggered. Thus, the effect of an input clock pulse “ ripples” through the counter , taking some time , due to propagation delays, to reach the last flip flop. In the 3 bit asynchronous up counter, the JK FF values are cleared first. Then based on the external clock pulse the counting begins. The output gets incremented for each clock pulse until all the JK FF output goes high. Then this cycle repeats. So this can be called as mod 8 counter. ii) 3 bit asynchronous down counter:
In 3 bit asynchronous down counter all the JK FF outputs Q where made high by grounding clr pin. Then for each external clock pulse received the output count gets reduced 2
CIT-EEE-09EE48-LAB MANUAL – EXP NO:10
until all the outputs becomes 0. At the end eight clock cycles the above output cycle gets repeated. Circuit Diagram:
Truth table: CLOCK PULSE
Q2
Q1
Q0
Initially
1
1
1
1
1
1
0
2
1
0
1
3
1
0
0
4
0
1
1
5
0
1
0
6
0
0
1
7
0
0
0
8 recycles
0
0
0
iii) Mod 10 counter (decade counter):
Mod (modulus) type counters are nothing but the modified form of up counter. They are modified such that their output is modulus of the design value of the counter. For example , 4 bit asynchronous up counter can count values from 0 to 15 as seen before. Mod 10 counter is designed such that the output cycles between 0 to 9 ie (output is mod 10). Such circuit can be designed using the required truth table. There are many ways to design a mod counter. One such type is designed as shown in figure. 3
CIT-EEE-09EE48-LAB MANUAL – EXP NO:10
Circuit Diagram:
Truth table: CLOCK PULSE
Q3
Q2
Q1
Q0
Initially
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10 recycles
0
0
0
0
Synchronous counter:
In synchronous counters, the clock input is connected to all of the flip flops so that they are clocked simultaneously.
4
CIT-EEE-09EE48-LAB MANUAL – EXP NO:10
iv) 4 bit synchronous counter:
The 4 bit synchronous counter is implemented using positive edged JK FF. The design is made using the truth table. It is clear that all the FF are triggered by the same clock pulse. Circuit Diagram:
Truth Table: CLOCK PULSE
Q3
Q2
Q1
Q0
Initially
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
5
CIT-EEE-09EE48-LAB MANUAL – EXP NO:10
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
15
1
1
1
1
16recycles
0
0
0
0
Viva Questions:
1. What is flip flop? How does it differ from latch? 2. What is counter? 3. Bring out the difference between synchronous and asynchronous counter. 4. Counter is a sequential circuit. Justify this statement. 5. What is mod counter? What is the maximum mod counter that can be designed using 4 JK flip flop?
Result:
Thus the 3 bit asynchronous up counter, 3 bit synchronous down counter, mod 10 counter (decade counter) and 4 bit synchronous counter were designed using JK flip flop and their outputs were verified using the truth table.
