W-DS-0004-A0 BIT1611B

BIT1611B

Beyond Innovation Technology Co., Ltd.

Digital Video Decoder with OSD, T-CON and DAC

Version: A0

Please lease read read t he noti ce stated stated in this preambl preamble e carefull carefull y befor e accessin accessing g any co ntents of the docu ment attached. attached. Ad m i s s i o n o f B i TEK’s TEK ’s s tatem tat emen entt t h erei er ein n i s pr p r esu es u m ed o n c e th e doc ument is i s released released to th e receiver.

2006/5/5 2006/5/ 5

Confidential, Confidenti al, for authorized user only

page 1 of 109 DOC NO.W-DS-0004


BIT1611B

Notice: Firstly, the information furnished by Beyond Innovation Technology Co. Ltd. (BiTEK) in this document is believed to be accurate and reliable reliable and subject to BiTEK’s BiTEK’s amendment without prior notice. And the aforesaid aforesaid information does not form any part or parts of any quotation or con tract between BiTEK and the info rmation receiver. receiver. Further, no responsibility responsibility is assumed for the usage of the aforesaid aforesaid information. BiTEK makes no representation representation that the interconnect of its circuits as described herein will not infringe on exiting or future patent rights, nor do the descriptions contained herein imply the granting of licenses to make, use or sell equipment constructed in accordance therewith. Besides, the product in this document is not designed for use in life support appliances, devices, or systems whe re malfunction of this product can reasonably be expected to result in personal injury. injury. BiTEK customers’ using or selling this product for use in such applications shall do so at their own risk and agree to fully indemnify BiTEK for any damage resulting from such improper use or sale. At last, the information furnished in this document is the property of BiTEK and shall be treated as highly confidentiality; any kind of distribution, disclosure, copying, transformation or use of whole or parts of this document without duly authorization from BiTEK by prior written consent is strictly prohibited. The receiver shall fully compensate BiTEK without any reservation for any losses thereof due to its violation of BiTEK’s BiTEK’s confidential request. The receiver is deemed to agree on BiTEK’s confidential request therein suppose that said receiver receives this document without making any expressly opposition. In the condition that aforesaid aforesaid opposition is made, the receiver shall return this this document to Bi TEK immediately without any delay. -Version -Version A4

2006/5/5 2006/5/ 5




BIT1611B

Notice: Firstly, the information furnished by Beyond Innovation Technology Co. Ltd. (BiTEK) in this document is believed to be accurate and reliable reliable and subject to BiTEK’s BiTEK’s amendment without prior notice. And the aforesaid aforesaid information does not form any part or parts of any quotation or con tract between BiTEK and the info rmation receiver. receiver. Further, no responsibility responsibility is assumed for the usage of the aforesaid aforesaid information. BiTEK makes no representation representation that the interconnect of its circuits as described herein will not infringe on exiting or future patent rights, nor do the descriptions contained herein imply the granting of licenses to make, use or sell equipment constructed in accordance therewith. Besides, the product in this document is not designed for use in life support appliances, devices, or systems whe re malfunction of this product can reasonably be expected to result in personal injury. injury. BiTEK customers’ using or selling this product for use in such applications shall do so at their own risk and agree to fully indemnify BiTEK for any damage resulting from such improper use or sale. At last, the information furnished in this document is the property of BiTEK and shall be treated as highly confidentiality; any kind of distribution, disclosure, copying, transformation or use of whole or parts of this document without duly authorization from BiTEK by prior written consent is strictly prohibited. The receiver shall fully compensate BiTEK without any reservation for any losses thereof due to its violation of BiTEK’s BiTEK’s confidential request. The receiver is deemed to agree on BiTEK’s confidential request therein suppose that said receiver receives this document without making any expressly opposition. In the condition that aforesaid aforesaid opposition is made, the receiver shall return this this document to Bi TEK immediately without any delay. -Version -Version A4

2006/5/5 2006/5/ 5




BIT1611B

Contents 1 General General Descriptio Description............................................................................. n............................................................................. 10 2 Feature.................................................................................................11 Information ................................................................................ 13 3 Order Information Functional Block Diagram.................................................................... Diagram.................................................................... 13 4 Functional Definition ....................................................................................... 14 5 Pin Definition 6 Application Examples ............ ...... ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ........ .. 18 7 Function Function Description............................................................................ Description............................................................................ 20 7-1

Version Control............................................................................................................................ 20

7-2 7-3 7-4

Interrupt Function ............................................................................. ........................................................................................................................ ........................................... 20 Double Buffer ....................................................................... .............................................................................................................................. ....................................................... 22 Pad Type Setup................................................................................. Setup ........................................................................................................................... .......................................... 22

7-5 7-6

GPO (General Purpose Output) Function .......................................................................... ................................................................................... ......... 25 System Enable and Reset........................................................................................................ Reset........................................................................................................... ... 28 7.6.1 Hardware Reset.................................................................................................. Reset.................................................................................................................. ................ 28 7.6.2 Software Reset ........................................................................ ................................................................................................................... ........................................... 28 7-7 Built-in DAC........................................................................... DAC ................................................................................................................................. ...................................................... 29 7-8 Clock Domain Systems ................................................................................ ............................................................................................................... ............................... 30 7-9 Panel Timing Setup .......................................................................... ..................................................................................................................... ........................................... 31 7-10 7-11

Output Data Path............................................................................................ Path......................................................................................................................... ............................. 32 Serial RGB Output Mode ............................................................................ ............................................................................................................ ................................ 33

7-12 7-13

Special Output Setup ....................................................................... .................................................................................................................. ........................................... 33 Special Timing Adjustment ........................................................................... .......................................................................................................... ............................... 34 7.13.1 Synchronization Timing ..................................................................... ...................................................................................................... ................................. 34

7.13.2 Two-Fields Synchronization Timing Timing........................................................................... .................................................................................... ......... 34 7-14 TCON Function ................................................................................. ........................................................................................................................... .......................................... 35 7-15 TCON Clock Mode ........................................................................... ...................................................................................................................... ........................................... 36 7-16 External Pin Setup ........................................................................... ...................................................................................................................... ........................................... 37 7-17 Display Layer................................................................................................... Layer............................................................................................................................... ............................ 39 7-18 Background 2 ....................................................................... .............................................................................................................................. ....................................................... 39 7-19 Background and Test Pattern Pattern Setup ...................................................................... ........................................................................................... ..................... 40 7-20 Auto Blue Screen ............................................................................. ........................................................................................................................ ........................................... 40 7-21 Input Image Window Setup .......................................................................... ......................................................................................................... ............................... 41 7-22 7-23

Input Data Data Path Setup ..................................................................... ................................................................................................................. ............................................ 42 Input Format ......................................................................... ................................................................................................................................ ....................................................... 43 7.23.1 ITU656 .......................................................................... ................................................................................................................................ ...................................................... 43

7.23.2 ITU656-Like ............................................................................. ........................................................................................................................ ........................................... 43 7.23.3 ITU601 .......................................................................... ................................................................................................................................ ...................................................... 43 7.23.4 RGB888 ....................................................................... .............................................................................................................................. ....................................................... 43 7.23.5 Serial-RGB .............................................................................. ......................................................................................................................... ........................................... 44 7.23.6 YUV444 ....................................................................... .............................................................................................................................. ....................................................... 44 7-24 Input Mode Selection ....................................................................... .................................................................................................................. ........................................... 44 7-25 CSYNC Decoder ............................................................................... ......................................................................................................................... .......................................... 46 7-26 Auto Switch ........................................................................... ................................................................................................................................. ...................................................... 47 7-27 Display Window Setup .................................................................................. ................................................................................................................ .............................. 47 7-28 Re-size Engine ................................................................................... ............................................................................................................................ ......................................... 48 2006/5/5 2006/5/ 5




BIT1611B

7.28.1 Horizontal Re-size Down .................................................................................................... 48 7.28.2 Vertical Re-size Down ........................................................................................................ 49 7-29 Timing Adjustment ....................................................................................................................... 50 7-30 7-31

Brightness/Contrast Adjustment.................................................................................................. 53 Image Enhancement ................................................................................................................... 55 7.31.1 Black Level and Black/White expansion............................................................................. 55 7.31.2 Sharpness and Smoothness Process ................................................................................ 56 7.31.3 UV Domain Process ........................................................................................................... 57

7.31.4 Chroma Transient Improvement (CTI)................................................................................ 58 7-32 Gamma Correction ...................................................................................................................... 58 7.32.1 Adjust-Curve ....................................................................................................................... 58 7.32.2 Look-Up-Table (LUT) .......................................................................................................... 59 7-33 Dither........................................................................................................................................... 60 7-34 Color Space Conversion ............................................................................................................. 60 7-35 PLL and OSC Pads ..................................................................................................................... 60 7-36 Timer ........................................................................................................................................... 61 7-37 GPI and KEY Function ................................................................................................................ 62 7-38 Auto Detection............................................................................................................................. 63 7-39 7-40

EEPROM Setup .......................................................................................................................... 64 Serial Peripheral Interface (SPI) ................................................................................................. 64

7-41 7-42 7-43 7-44 7-45

Power Sequence Control ............................................................................................................ 66 PWM Function............................................................................................................................. 67 Feedback PWM Control .............................................................................................................. 69 IR Decoder Function ................................................................................................................... 70 Video Decoder............................................................................................................................. 71 7.45.1 Architectures....................................................................................................................... 71 7.45.2 Analog Input Path ............................................................................................................... 71 7.45.3 Color Standard Setting and detect ..................................................................................... 72 7.45.4 Luminance Process ............................................................................................................ 73 7.45.5 Chroma Process................................................................................................................. 75 7.45.6 Synchronization Process .................................................................................................... 77 7.45.7 AFE Architectures............................................................................................................... 78 7.45.8 Analog AGC Control ........................................................................................................... 78 7.45.9 Analog Clamp Control ........................................................................................................ 79 7.45.10 Digital AGC and Clamp Control......................................................................................... 80

7.45.11 ADC Control ...................................................................................................................... 81 7.45.12 AFE PLL Clock Control...................................................................................................... 82 7.45.13 Status Register .................................................................................................................. 82 7-46 OSD Function.............................................................................................................................. 84 7.46.1 OSD Windows Function ..................................................................................................... 84 7.46.2 OSD Memory Mapping ....................................................................................................... 85 7.46.3 OSD Windows Attribute ...................................................................................................... 88 7.46.4 External OSD Interface....................................................................................................... 90 7.46.5 OSD User Programmable RAM Selection.......................................................................... 92 7.46.6 OSD Built-in Fixed Font...................................................................................................... 93

8

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Interface Mode .................................................................................... 94 8-1

Options Pins ................................................................................................................................ 94

8-2

Script Master Mode ..................................................................................................................... 94 8.2.1 Architecture ........................................................................................................................ 94 Confidential, for authorized user only


Beyond Innovation Technology Co., Ltd. 8.2.2 8.2.3 8.2.4 8-3

9

BIT1611B

Start and Interrupt ............................................................................................................... 95 Instruction Set..................................................................................................................... 95 Instruction Format............................................................................................................... 97

Slave Mode ................................................................................................................................. 99 8.3.1 BiTEKbus Protocol ............................................................................................................. 99 8.3.2 Two-Wire Protocol ............................................................................................................ 100

Timing Diagram ................................................................................. 103 9-1 9-2

Hardware Reset: ....................................................................................................................... 103 Clock and Interrupt: ................................................................................................................... 103

9-3 9-4

Input Signal: .............................................................................................................................. 103 Output Signal:............................................................................................................................ 104

9-5

Micro Processor Interface: ........................................................................................................ 104

10 Electrical Characteristic ..................................................................... 106 11 Soldering Information ........................................................................ 107 11-1

Reflow Soldering: ...................................................................................................................... 107

11-2 11-3

Wave Soldering: ........................................................................................................................ 107 Manual Soldering: ..................................................................................................................... 108

12 Package Information ......................................................................... 109

2006/5/5

Confidential, for authorized user only



BIT1611B

Tables Table 5-1

BIT1611B PIN Define ................................................... ....................................................... ......................... 15

Table 7-1

Version Control Register ........................................................ ....................................................... ............... 20

Table 7-2

Interrupt Source............................................................................. ............................................................... 20

Table 7-3

Interrupt Register........................................................................... ............................................................... 20

Table 7-4

Video Decoder lock source for interrupt select ....................................................... ...................................... 21

Table 7-5

Double Buffer Register ................................................. ........................................................ ........................ 22

Table 7-6

Multi-Function Pads..................................................... ........................................................ ......................... 22

Table 7-7

Output Tri-State Control Register ..................................................... ........................................................ .... 25

Table 7-8

General Purpose Output Register ..................................................... ....................................................... .... 25

Table 7-9

General Purpose Output Pads Setup Table.................................................. ................................................ 26

Table 7-10

Soft Reset Register ................................................... ........................................................ ......................... 28

Table 7-11 DAC Register..................................................................... ........................................................ ................. 29 Table 7-12

Clock Domain System Register.......................... ........................................................ ................................ 30

Table 7-13

Panel Timing Setup register ................................................. ........................................................ .............. 31

Table 7-14

Output Data Path Register ................................................... ........................................................ .............. 32

Table 7-15

Serial RGB Output Register ................................................. ........................................................ .............. 33

Table 7-16

Special Output Pads Setup Register ............................................... ........................................................ ... 33

Table 7-17

Special Timing Adjust Register ....................................................... ........................................................ .... 34

Table 7-18

TCON Function Register ...................................................... ....................................................... ............... 35

Table 7-19

TCON Clock Mode Register........................................................... ....................................................... ..... 36

Table 7-20

External Pin Setup..................................................... ........................................................ ......................... 37

Table 7-21

External Pin Setup Mapping........................................................... ....................................................... ..... 38

Table 7-22

Background 2 Register............................. ....................................................... ........................................... 39

Table 7-23

Background and Test Pattern Register................. ........................................................ .............................. 40

Table 7-24

Blue Screen Register ................................................. ........................................................ ........................ 40

Table 7-25

Input Crop Register ................................................... ........................................................ ......................... 41

Table 7-26

Output Data Path Register ................................................... ........................................................ .............. 42

Table 7-27

Input Mode Select Register .................................................. ........................................................ .............. 44

Table 7-28

CSYNC Decoder register ..................................................... ........................................................ .............. 46

Table 7-29

Auto Switch Register .................................................. ....................................................... ......................... 47

Table 7-30

Display Windows Register........................................... ....................................................... ........................ 47

Table 7-31

Horizontal Scale Down Register................ ........................................................ ......................................... 48

Table 7-32

Vertical Scale-Down Register................................................ ....................................................... .............. 49

Table 7-33

Timing Adjust Register............................................................................ .................................................... 51

Table 7-34

Color Adjustment Register........................................... ....................................................... ........................ 53

Table 7-35

Y Domain Process Register ................................................. ........................................................ .............. 55

Table 7-36

Sharpness and Smoothness Process Register .................................................... ...................................... 56

Table 7-37

UV Domain Register............................................................ ........................................................ ............... 57

Table 7-38

Chroma Transient Improvement Register......................................... ........................................................ .. 58

Table 7-39

Adjust-Curve Register ................................................ ........................................................ ........................ 59

Table 7-40

LUT Gamma Memory Address ....................................................... ........................................................ .... 59

Table 7-41

LUT Gamma Register ................................................ ........................................................ ........................ 60

Table 7-42

Dither Register ................................................ ........................................................ ................................... 60

Table 7-43

Color Space Converter Register.......................... ....................................................... ................................ 60

Table 7-44

PLL Register............................................................. ........................................................ .......................... 60

Table 7-45

Timer Register............ ........................................................ ....................................................... ................. 61

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BIT1611B

Table 7-46

GPI and KEY Register....................................... ....................................................... .................................. 62

Table 7-47

Auto Detection Register ....................................................... ....................................................... ............... 64

Table 7-48

EEPROM Read/Write Speed Register ...................................................... ................................................. 64

Table 7-49

SPI Register .................................................... ....................................................... .................................... 64

Table 7-50

Power Sequence Control Register .................................................. ........................................................ ... 66

Table 7-51

PWM Function Register ....................................................... ....................................................... ............... 67

Table 7-52

Feedback PWM Function Register......................................... ....................................................... ............. 69

Table 7-53

IR PWM Pulse Detect Register ...................................................... ........................................................ .... 70

Table 7-54

Analog Input Path Register .................................................. ........................................................ .............. 72

Table 7-55

Color Standard register ........................................................ ....................................................... ............... 73

Table 7-56

Luminance Process Register...................................................................................... ................................ 74

Table 7-57

Chroma Process Register .................................................... ........................................................ .............. 75

Table 7-58

Synchronization process Register............................................................ .................................................. 77

Table 7-59

Analog AGC Control Register...................................... ........................................................ ....................... 78

Table 7-60

Clamp Control Register ........................................................ ....................................................... ............... 79

Table 7-61

Digital AGC Control Register................................................. ....................................................... .............. 80

Table 7-62

ADC Control Register..................... ........................................................ .................................................... 81

Table 7-63

AFE PLL Clock Control Register ..................................................... ....................................................... .... 82

Table 7-64

Video Decoder Status Register ...................................................... ........................................................ .... 83

Table 7-65

OSD Windows Register.............................................. ........................................................ ........................ 84

Table 7-66

OSD Memory Mapping Table ................................................ ....................................................... .............. 85

Table 7-67

OSD Windows Attribute Register....................................................................... ......................................... 88

Table 7-68

External OSD Register ............................................... ........................................................ ........................ 90

Table 8-1

Options Pins Setup...................................................... ........................................................ ......................... 94

Table 8-2

Register and Address Index ................................................... ........................................................ .............. 94

Table 8-3

Register and Address Index ................................................... ........................................................ .............. 95

Table 8-4

Instruction Set ................................................... ........................................................ ................................... 95

Table 8-5

BiTEKbus Slave Address ....................................................... ....................................................... ............... 99

Table 8-6

Two-Wire Protocol Device Address ................................................... ........................................................ . 100

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BIT1611B

Figures Figure 4-1

BIT1611B Architecture................................................ ........................................................ ........................ 13

Figure 5-1

Pin configuration (LQFP-128) ................................................ ....................................................... .............. 14

Figure 6-1

Application 1 .................................................... ....................................................... .................................... 18

Figure 6-2

Application 2 .................................................... ....................................................... .................................... 18

Figure 6-3

Application 3 .................................................... ....................................................... .................................... 19

Figure 6-4

Application 4 .................................................... ....................................................... .................................... 19

Figure 7-1

Interrupt Function Block.................. ........................................................ .................................................... 21

Figure 7-2

Double Buffer Function ............................................... ........................................................ ........................ 22

Figure 7-3

GPO function ................................................... ........................................................ ................................... 27

Figure 7-4

Hardware Reset Waveform............................................................................... .......................................... 28

Figure 7-5

Clock Select Function ................................................. ........................................................ ........................ 31

Figure 7-6

Panel Timing Setup........................................... ........................................................ .................................. 32

Figure 7-7

Output Data Path Select ....................................................... ....................................................... ............... 33

Figure 7-8

Synchronization Timing........................................................................... .................................................... 34

Figure 7-9

Two-Fields Synchronization Timing ................................................. ........................................................ ... 34

Figure 7-10

TCON Clock Mode................................................... ........................................................ ......................... 36

Figure 7-11 External Pin Setup ................................................... ........................................................ ......................... 38 Figure 7-12

Display Layer................................................. ........................................................ ................................... 39

Figure 7-13

Input Window Setup........................................ ........................................................ .................................. 41

Figure 7-14

Input Data Path Setup ........................................................ ....................................................... ............... 42

Figure 7-15

ITU656/656-like input....................................... ....................................................... .................................. 43

Figure 7-16

ITU601 input .................................................. ........................................................ ................................... 43

Figure 7-17

RGB 8:8:8 input ....................................................... ........................................................ ......................... 43

Figure 7-18

Serial-RGB input........ ....................................................... ........................................................ ................ 44

Figure 7-19

YUV 4:4:4 input........................................................ ........................................................ ......................... 44

Figure 7-20

Input Mode Select......................... ....................................................... ..................................................... 46

Figure 7-21

Display Window Setup........................................................ ....................................................... ............... 47

Figure 7-22

Re-size function ....................................................... ........................................................ ......................... 48

Figure 7-23

Timing Adjustment VREF Information...................................................... ................................................. 50

Figure 7-24

R_OS_XT Adjust flow chart ................................................. ....................................................... .............. 52

Figure 7-25

Timing Adjust flow.................................................... ........................................................ ......................... 53

Figure 7-26

Brightness and Contrast ..................................................... ........................................................ .............. 54

Figure 7-27

Gamma LUT Ram Setting................................................... ........................................................ .............. 54

Figure 7-28

Black Level Adjustment................................................................ ........................................................ ..... 55

Figure 7-29

Black and White Adjustment ................................................ ....................................................... .............. 56

Figure 7-30

Black and White Slope............................ ....................................................... ........................................... 56

Figure 7-31

Gamma Correction ................................................... ....................................................... ......................... 58

Figure 7-32

Example of Adjust-Curve .................................................... ........................................................ .............. 59

Figure 7-33

SPI Protocol................................ ........................................................ ...................................................... 65

Figure 7-34

Power Sequence Function......................................... ........................................................ ....................... 67

Figure 7-35

PWM function ................................................ ........................................................ ................................... 68

Figure 7-36

Video Decoder Architectures ........................................................ ........................................................ .... 71

Figure 7-37

Video Decoder Analog Input Path........................................................... .................................................. 72

Figure 7-38

Luminance Process .................................................. ....................................................... ......................... 73

Figure 7-39

Chroma Process Function Block...................................................................... ......................................... 75

Figure 7-40

Synchronization Process .................................................... ........................................................ .............. 77

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BIT1611B

Figure 7-41

AFE Architectures...... ........................................................ ....................................................... ................ 78

Figure 7-42

Analog Auto Gain Control ................................................... ........................................................ .............. 78

Figure 7-43

Video Decoder PLL....................... ....................................................... ..................................................... 82

Figure 7-44

OSD Windows Setup ................................................ ........................................................ ........................ 85

Figure 7-45

OSD Memory Mapping ....................................................... ....................................................... ............... 86

Figure 7-46

OSD User Programmable Font RAM........................... ........................................................ ..................... 87

Figure 7-47

Palette RAM Example........................................................ ........................................................ ............... 87

Figure 7-48

OSD Windows Attribute ...................................................... ....................................................... ............... 90

Figure 7-49

Fixed FONT ................................................... ........................................................ ................................... 93

Figure 8-1

Bitek Serial Interface bus...................................................... ....................................................... ............... 99

Figure 8-2

BiTEKbus Extension Mode ................................................... ........................................................ ............ 100

Figure 8-3

I2C Slave Address Mapping.............................................................................. ........................................ 101

Figure 8-4

Read/Write Mode................................................................ ........................................................ .............. 102

2006/5/5




BIT1611B

1 General General Descr Descr ipt ion BIT1611B is a high performance digital video decoder combining T-CON, OSD and DAC within one single device. The decoder transfers and decodes most popular NTSC and PAL video contents from TV tuner or DVD sources. Signal feeding into BIT1611B BIT1611B includes analog CVBS and Y/C, digital CCIR656 CCIR656 and digital RGB RGB format. The Automatic Gain Control (AGC) for AD converter extends extends the capability for handling weak and distorted distorted signals. Advanced CTI CTI and Skin-Tone Skin-Tone processes help for improving the picture quality a lot. The programmable timing timing control (T-CON) (T-CON) let most of the popular panels (resolution under under 512xRGBx512) 512xRGBx512) used for BIT1611B BIT1611B system. Programmable brightness, brightness, contrast and color saturation with embedded GAMMA correction let user compensate any color problem of display. Embedded OSD makes system designer very easy to develop a friendly interface between user and end product. Advanced wide range display display format controller controller can convert convert a 4:3 display to 16:9 very smoothly smoothly.. BIT1611B BIT1611B can be used for a traditional hand-held LCD monitor very very easily. easily. With the outstanding video processing processing performance, it is also suitable for Car TV/navigation TV/navigation system and portable portable AV AV system. For some LCD monitors, which combine combine graphic and video input within a single system, BIT1611B BIT1611B is the most convenient and compact solution.

2006/5/5

Confidential,, for authorize Confidential authorized d user only



BIT1611B

2 Feature 2-1 General:             

No external memory required Two Two 8-bit video CMOS analog-to-digital converters Require only one crystal crystal (24.576MHz) (24.576MHz) for all color color standards standards YUV to RGB color space converting Programmable arbitrary zoom-out zoom-out ratio ratio in horizontal and vertical vertical Anamorphic 4:3 to 16:9 display converting Embedded brightness, contrast, sharpness and gamma gamma correction correction Embedded Skin-Tone and CTI Embedded programmable OSD for user user Interface Interface Embedded programmable programmable TCON (Timing-Control) generator generator for LCD interface Embedded 4 PWM (Pulse (Pulse Width Modulator) Modulator) generators for general purpose control Embedded IR remote control decoder Embedded video decoder

2-2 2-2 Input:            

Four analog analog inputs, inputs, internal internal analog analog source source selectors, for example (4 x CVBS) or (2 x Y/C) or (1 x Y/C and 2 x CVBS) Automatic detection of 50 and 60 Hz field frequency Programmable Progra mmable switching between betwee n PAL PAL BGHI, PAL PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43 and NTSC Japan and SECAM standards 24-bit RGB/YUV input up to 30MHz 16-Bits RGB (RGB 5/6/5) input 8-bit Serial RGB Data format ITU-R BT.601 BT.601 16-bit (CCIR 601) ITU-R BT.656 BT.656 8-bit (CCIR 656) Support digital digital MUX MUX for two video source source input Built-in YUV YUV to RGB color space converter Programmable RGB input ports sequence and pins sequence 5V tolerance tolerance input input pads pads support 5V/3.3V interface

2-3 Output:          

Single (18/24 (18/24 bits) port RGB data output Programmable RGB output ports sequence and pins sequence Analog RGB output support support line line invert invert function function Maximum output pixel pixel frequency frequency 30 MHz MHz Support inverse inverse and frequency adjustment for LCD panel clock Support programmable H/V sync. for LCD panel Support programmable TCON for LCD panel Support Serial-RGB Interface LCD Panel Support Delta Delta and Stripe types LCD panel Free-run Synchronization mode if sync sync signal disappeared

2-4 Interface:   

2006/5/5

Support Two-wire BiTEKbus interface 2 Support I C bus interface Support 24Cxx serials EEPROM EEPROM Script controller controller




BIT1611B

2-5 OSD:       

Built-in OSD generator with 240 ROM fonts, 512 mix mix color, 3 windows 16 user download fonts 5 sizes sizes of zooming font (1/2, x1, x2, x2, x3, x4) Flashing font attribute Fringe font attribute Transparent overlay for OSD windows Support external OSD interface

2-6 Power management :  

3V power power source, source, 5V tolerant for input pads 3.3V / 5V power power source for output pads

2-7 Package: 

2006/5/5

LQFP 128 pins



BIT1611B


3 Order Information BIT 1611B - LQ LQFP type package Part number Beyond Innovation Technology Co., Ltd.

4 Functional Block Diagram

Figure 4-1

2006/5/5

BIT1611B Architecture



BIT1611B


5 Pin Definition 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 8 7 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 9 9

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AVDD AIN11 AGND AIN12 AVDD REFT1 REFB1 AGND AOUT1 AVDD AIN21 AGND AIN22 AVDD REFT2 REFB2 AGND AOUT2 AVDD TEST AGND GND RIN7 RIN6 RIN5 RIN4 RIN3 RIN2 RIN1 RIN0 VCC ICLK1

4 3 E D K D 2 1 7 6 D 5 4 D 3 2 D 1 0 7 D 6 D 5 D 4 3 D 2 D T B S T T N T T D T T N T T T D T N T D T T N T D F _ M M D N L D S T U U G U U V U U G U U U V U G U V U U G U V E G O G C V T W W R O H O O H O O H O O O H O H O H O O H O _ R O O ] R / P ] O / P / H H / B B B B B C _ L G G / G / G / G / G / B / B / / B / / 7 2 1 ] / ] / [ 6 [ / A C A L L ] L 3 / 2 1 1 2 H D 2 1 0 H M M O O E E [ [ [ 2 U R H H H H H E D A L D A P P _ S S O O O Q W W _ P P P T T _ _ P P P G G 6 P P N N C C C S S O / / 5 ] ] ANALOG_G G G O O P P G 5 T T T [ 4 [ C C ANALOG_R T O O T / / P P L DAC_REFB L G G E E DAC_GND S S _ _ P4/GPO[3]/GOUT1 6 5 P P HGND P3/GPO[2]/GOUT0 VCOM/ROUT7 HVDD LD(OEV)/ROUT6 FRP/ROUT5 HGND CKV/ROUT4 STV1/ROUT3 HVDD STV2/ROUT2 P2/GPO[1]/ROUT1 HGND P1/GPO[0]/ROUT0 GND FB4/VSYNC2 OPTIONS[5] OPTIONS[4] OPTIONS[3] VCC OPTIONS[2] OPTIONS[1] D L GND U R K T T N OPTIONS[0] X X K A E E L S S L VCC ] ] ] ] ] ] / ] / ] C V H B B G R 7 6 5 4 3 2 1 0 FB3/HSYNC2 [ I [ I [ I [ I [ I [ I [ I [ D D D D D D D I S S S S S S S P P P P P P P VCCA 1 1 P # O O O O O O O G / G / G / G / G / G / G / G / / / / / / / C C / T ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] O I 7 6 N 7 6 E A [ 5 [ 3 [ 4 [ 2 [ 1 [ 0 [ D 2 [ 5 [ 4 [ D 3 [ 2 [ 1 [ 0 [ C K N D C C C [ D D Y Y [ N I N I N I N I N I N I N I N N L C N I N I N I N N I N I N I N I N C T N S N S S C I S E N C S I G O O V G G G G G G G G G C I V V H B B B B G B B B B V R I N I G R G

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6

Figure 5-1

2006/5/5

Pin configuration (LQFP-128)



BIT1611B


Table 5-1 Pin #

2006/5/5

BIT1611B PIN Define

Pin Name

Pin Type

Function Description

1

AVDD

AVDD

AFE Power (3.3V)

2

AIN11

AIN

3

AGND

AGND

4

AIN12

AIN

5

AVDD

AVDD

AFE Power (3.3V)

6

REFT1

AOUT

Reference voltage 1 Output for ADC1

7

REFB1

AOUT


8

AGND

AGND

AFE Ground

9

AOUT11

AOUT

AFE Analog Output for ADC 1

10

AVDD

AVDD

AFE Power (3.3V)

11

AIN21

AIN

12

AGND

AGND

13

AIN22

AIN

14

AVDD

AVDD

AFE Power (3.3V)

15

REFT2

AOUT


16

REFB2

AOUT


17

AGND

AGND

AFE Ground

18

AOUT2

AOUT

AFE Analog Output For ADC 2

19

AVDD

AVDD

AFE Power (3.3V)

20

TEST

I

21

AGND

AGND

22

GND

G33

23

RIN7

I

R-Port[7] Data Input

Pull-Down

24

RIN6

I


Pull-Down

25

RIN5

I


Pull-Down

26

RIN4

I


Pull-Down

27

RIN3

I


Pull-Down

28

RIN2

I


Pull-Down

29

RIN1

I


Pull-Down

30

RIN0

I


Pull-Down

31

VCC

P33

32

ICLK1

I

Clock 1 Input

33

GND

I

Ground of (3.3V)

34

OSCO

I

Oscillator Output

35

OSCI

I

Oscillator Input

36

VCC

P33

37

GIN7

I

38

GIN6

39

Analog Input Source 1 AFE Ground Analog Input Source 2

Analog Input Source 3 AFE Ground Analog Input Source 4

Test Input AFE Ground Ground of (3.3V)

3.3V Power

3.3V Power G-Port[7] Data Input

Pull-Down

I/O

G-Port[6] Data Input / External OSD CLK

Pull-Down

GIN5

I/O

G-Port[5] Data Input / External OSD VSYNC

Pull-Down

40

GIN4

I/O

G-Port[4] Data Input / External OSD HSYNC

Pull-Down

41

GIN3

I

G-Port[3] Data Input / External OSD Blank

Pull-Down

42

GIN2

I

G-Port[2] Data Input / External OSD B

Pull-Down

43

GIN1

I

G-Port[1] Data Input / External OSD G

Pull-Down



BIT1611B


2006/5/5

44

GIN0

I

G-Port[0] Data Input / External OSD R

Pull-Down

45

GND

G33

46

ICLK2

I

47

VCC

48

VSYNC1

I

Vsync 1 Input

Pull-Down

49

HSYNC1

I

Hsync 1 Input

Pull-Down

50

BIN7

I

B-Port[7] Data Input / GPI[7]

Pull-Down

51

BIN6

I


Pull-Down

52

BIN5

I


Pull-Down

53

BIN4

I


Pull-Down

54

GND

G33

55

BIN3

I


Pull-Down

56

BIN2

I


Pull-Down

57

BIN1

I

B-Port[1] Data Input / GPI[1] / External TCON_UD

Pull-Down

58

BIN0

I

B-Port[0] Data Input / GPI[0] / External TCON_RL

Pull-Down

59

VCC

P33

60

IR

I

IR Remote Control Input

61

INT

O

Interrupt Output

62

GND

G33

Ground of (3.3V)

63

RESET#

64

GNDA

AG33

PLL Ground

65

VCCA

AP33

PLL Power Supply (3.3)

66

HSYNC2

67

VCC

P33

3.3V Power

68

OPTIONS0

I/O

Interface Control Pin 0

69

GND

70

OPTIONS1

I/O


71

OPTIONS2

I/O

Interface Control Pin 2 /GPI[8] /SPI_SCL

72

VCC

P33

3.3V Power

73

OPTIONS3

I/O

Interface Control Pin 3 /GPI[9] /SPI_SDA

74

OPTIONS4

I/O

Interface Control Pin 4 /GPI10] /SPI_CS

75

OPTIONS5

I


Pull-Up

76

VSYNC2

I

VSYNC2 Input / PWM4 Feedback

Pull-Down

77

GND

78

ROUT0

O

79

HGND

G50

80

ROUT1

O

R-Data Output Port[1] / GPO[1] / Power_P2

81

ROUT2

O

R-Data Output Port[2] / STV2

82

HVDD

P50

83

ROUT3

O

R-Data Output Port[3] / STV1

84

ROUT4

O

R-Data Output Port[4] / CKV

85

HGND

G50

86

ROUT5

O

R-Data Output Port[5] / FRP

87

ROUT6

O

R-Data Output Port[6] / LD

88

HVDD

P50

89

ROUT7

O

R-Data Output Port[7] / VCOM

90

GOUT0

O

G-Data Output Port[0] / GPO[2] / Power_P3

Ground of (3.3V) Clock 2 Input

P33

I

3.3V Power

Ground of (3.3V)

3.3V Power

System Reset (Active Low)

I

HSYCN2 Input / PWM3 Feedback

G33

G33

Pull-Down

Pull-Up

Pull-Down

Ground of (3.3V)

Ground of (3.3V) R-Data Output Port[0] / GPO[0] / Power_P1 5.0/3.3V Ground

5.0/3.3V Power (I/O port)

5.0/3.3V Ground




BIT1611B


2006/5/5

91

HGND

G50

5.0/3.3V Ground

92

GOUT1

O

93

DAC_GND

AG50

DAC Ground (5.0V)

94

DAC_REFB

AG50

DAC Reference Bottom Voltage Voltage

95

AROUT

AOUT

Analog R Data Output

96

AGOUT

AOUT

Analog G Data Output

97

ABOUT

AOUT

Analog B Data Output

98

DAC_REFT

AP50

DAC Reference Referen ce Top Voltage

99

DAC_VDD

AP50

DAC Power Supply (5.0V)

100

GOUT2

O

101

HGND

G50

102

GOUT3

O

G-Data Output Port[3] / STH2

103

GOUT4

O

G-Data Output Port[4] / STH1

104

HVDD

105

GOUT5

O

106

HGND

G50

107

GOUT6

O

108

HVDD

109

GOUT7

O

G-Data Output Port[7] / CPH3

110

BOUT0

O

B-Data Output Port[0] / TCON_RL /Power_P5 /Power_P 5

111 111

BOUT1

O

B-Data Output Port[1] / TCON_UD /Power_P6 /Power_P 6

112

HGND HGND

G50

113

BOUT2

O

B-Data Output Port[2] / TCON_Q2H

114

BOUT3

O

B-Data Output Port[3] / TCON_GPO[0]

115

HVDD

P50

116

BOUT4

O


117

BOUT5

O


118

HGND HGND

G50

119

BOUT6

O

B-Data Output Port[6] / Power_P5

120

BOUT7

O

B-Data Output Port[7] / Power_P6

121

RTS1

O

Special Function Output 1 / GPO[6]

122

RTS2

O

Special Function Output 2 / GPO[7]

123

HVDD

P50

124

OCLK

O

125

HGND

G50

126

ODE

O

Output Data Enable

127

PWM1

O

PWM1 output / GPO[4] /PWM3 Output

128

PWM2

O

PWM2 output / GPO[5] /PWM4 Output

G-Data Output Port[1] / GPO[3] / Power_P4

G-Data Output Port[2] / OEH

P50

5.0/3.3V Ground

5.0/3.3V Power (I/O port) G-Data Output Port[5] / CPH1 5.0/3.3V Ground G-Data Output Port[6] / CPH2

P50


5.0/3.3V Ground


5.0/3.3V Ground

5.0/3.3V Power (I/O port) Output Clock 5.0/3.3V Ground



BIT1611B


6 Ap p li c atio at io n Examp Ex amp les le s CVBSx4or S-Videox2or CVBSx2+S-Video InternalMux

Options AnalogRGBOutpu AnalogRGBOutputt

Analog Video Source

External OSD

ITU656/ITU656-Like RGB888/RGB565 Serial-RGB DigitalVideo Source

Analo g TFT Panel

M U BIT1611B X

Smallerthan 512x512

MCU TFTTCONSignals

BiTEKbusorTwo-Wire Figure 6-1

Application 1

CVBSx4or S-Videox2or CVBSx2+S-Video InternalMux Analog Video Source

Options DigitalRGBOutput 8:8:8

External OSD

ITU656/ITU656-Like RGB888/RGB565 Serial-RGB DigitalVideo Source

Analo Digital g TFT Panel

M U BIT1611B X


MCU BiTEKbusorTwo-Wire Figure 6-2

2006/5/5

DigitalTFTPanelTiming Signal

Application 2



BIT1611B


CVBSx4or S-Videox2or CVBSx2+S-Video InternalMux Analog Video Source ITU656/ITU656-Like RGB888/RGB565 Serial-RGB DigitalVideo Source ExternalPin Setting

Options Analog DigitalRGBOutput

8:8:8

External OSD

Analo g TFT Panel

M U BIT1611B X

EEPROM TFTTCONSignal

24CxxEEPROM Figure 6-3

Application 3

CVBSx4or S-Videox2or CVBSx2+S-Video InternalMux Analog Video Source ITU656/ITU656-Like RGB888/RGB565 Serial-RGB DigitalVideo Source ExternalPin Setting

Options DigitalRGBOutput 8:8:8

External OSD

Analo Digital g TFT Panel

M U BIT1611B X


EEPROM

24CxxEEPROM Figure 6-4 2006/5/5


DigitalTFTPanelTiming Signal

Application 4



BIT1611B


7 Function Descript ion 7-1 Version Contro l BIT1611B provides two registers to save the information of the number of the version of the hardware and the soft ware. Please refer to the Table 7-1 for the details:

Table 7-1

Version Control Register

Mnemonic

Address R/W

bit

Description

Default

[1:0] Product version R_HW_VER

0x000

R

8

[4:2] Product Number

0xC6

[7:5] Product Group R_SW_VER

0x001

RW

8

Software Version Control

0x00

7-2 Interrup t Functi on BIT1611B Interrupt Function provides INT Pin (Pin61) to be the Interrupt Trigger Output. Interrupt can be set as a Edge or Level trigger through setting the registers. It can be set as “Active High “ or “Active Low “ when it is level trigger. It can be set as a “Falling Edge” or “Rising Edge” trigger when it is a edge triggered interrupt. The Interrupt is a “Three Layers” configuration (FLAG, MASK and ACK) as described in Figure 7-1. BIT1611B provides 8 Interrupt Sources. Please refer to Table 7-2, Table 7-3 and Table 7-4 for the details:

Table 7-2

Interrupt Source

Interrupt Source

R_HASSIG_FLAG

bit

Function R_NOSIG_SEL(0x101[3]=0

Active when input HSYNC has some changes in 2047 XCLKs

R_NOSIG_SEL(0x101[3]=1

Active when Video Decoder Lock select source (see Table 7-4)


Active when input HSYNC has no change in 2047 XCLKs


Active when Video Decoder Un-Lock select source (see Table 7-4)

0

R_NOSIG_FLAG

1

2 Active when input VSYNC variation larger than the setting of R_MODECHG_MRG

R_MODE_FLAG

Active when selected VSYNC falling edge occurs. R_VSYNC_FLAG

3 R_INT_VSSEL(0x005[6] = 0

VSYNC from input Vsync source

R_INT_VSSEL (0x005[6])= 1

VSYNC from output Vsync

R_INT_ERRSEL(0x005[7] ) =0

Active when timer1 overflow


Active when Line Buffer error type 1 occurs.

R_INT_ERRSEL(0x005[7]) = 0

Active when timer2 overflow


Active when Line Buffer error type 2 occurs.

R_ERROR1_FLAG

4

R_ERROR2_FLAG

5

R_IR_FLAG

6 Active when IR Remote Control Detection is ready.

R_KEY_FLAG

7 Active when GPI (General Purpose Input) status changes.

Table 7-3

Interrupt Register

Mnemonic

Address

R/W

bit

Description

Default

Interrupt Flag: R_INT_FLAG

0x002

R

8

0: Nothing.

-

1: Interrupt event occurs. 2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. Interrupt MASK: R_INT_MASK

0x003

RW

8

0: Interrupt Mask Off (Enable interrupt).

0x00

1: Interrupt Mask On (Disable interrupt). Interrupt ACK: R_INT_ACK

0x004

RW

8

0: Clear Interrupt Flag and Disable Interrupt.

0x00

1: Enable Interrupt. Interrupt TYPE: R_INT_TYPE

0x005[0]

RW

1 0: Edge Type.

0

1: Level Type. Interrupt Polarity: 0: High level active (Level Type) R_POL_INT

0x005[1]

RW

1

0

0: Rising edge active (Edge type) 1: Low level active (Level Type) 1: Falling edge active (Edge type) Line buffer error detection select

R_ERROR_TYPE

0x005[2]

RW

1

0

0: ODD Field. 1: EVEN Field. Interrupt vector[3] source select

R_INT_VSSEL

0x005[6]

RW

1 0: Input source Vsync.

1

1: Output Vsync. Interrupt vector[4] and vector[5] source select R_INT_ERRSEL

0x005[7]

RW

1

1

0: From timer overflow 1: From line buffer error

Table 7-4 Mnemonic

Video Decoder lock source for interrupt select Address

R/W

bit

Description

Default

Video Decoder Lock source for interrupt select 00: from STD_READY & SYNC_READY R_HLCK_SEL

0x130[7:6] RW

2 01: from STD_READY

11

10: from SYNC_READY 11: from HLCK

R_INT_ACK

R_INT_FLAG

R_INT_MASK

FF

Interrupt Control

INT

Interrupt Source

Figure 7-1

2006/5/5

Interrupt Function Block



BIT1611B


7-3 Double Buf fer BIT1611B provides “Double Buffer Register” for user to do “Parallel” updating. The double buffer is provided for the re-size factor (0x5D~0x5F) and Display window setup (0x56~0x59). Please refer to the Figure 7-2 and Table 7-5.

Figure 7-2 Table 7-5

Double Buffer Function

Double Buffer Register

Mnemonic

Address

R/W bits

Description

Default

Double Buffer Load Enable R_LOAD_EN

0x005[4]

RW

1 0: Nothing

0

1: Load Double Buffer Register Update Type R_LOAD_TYPE

0x005[5]

RW

1 0: Immediately

0

1: Control by R_LOAD_EN

7-4 Pad Type Setup BIT1611B provides some pads with Multi-Function, these pins and their functions are described in Table 7-6. 7-7 provides the information of the “Tri-state” operated output pins and the setting of the relative registers. Table 7-6 PIN

2006/5/5

Table

Multi-Function Pads Type

GIN0 (44)

I

GIN1 (43)

I

GIN2 (42)

I

GIN3 (41)

I

GIN4 (40)

I/O

GIN5 (39)

I/O

Multi-Function

Control Register

G-Port[0] data Input

R_EXTOSD_EN (0x162[0])=0

External OSD R Input




External OSD G Input




External OSD B Input




External OSD Blank Input


I G-Port[4] Data Input


O External OSD HSYNC Output




O External OSD VSYNC Output




Beyond Innovation Technology Co., Ltd. GIN6 (38)

I/O

BIT1611B



O External OSD Clock Output


B-Port[0] Data Input BIN0 (58)

I

External TCON type select 1

R_EXTPIN (0x0C9[7]) = 1

GPI[0]

R_KEY0_TYPE (0xC4[1:0])

B-Port[1] Data Input BIN1 (57)

BIN2 (56)

I

BIN3 (55)

I

BIN4 (53)

I

BIN5 (52)

I

BIN6 (51)

I

BIN7 (50)

I

HYSNC2(66)

I

VSYNC2(76)

I

ROUT0 (78)

ROUT1 (80)

O

O

ROUT2 (81)

I/O

ROUT3 (83)

I/O

ROUT4 (84)

O

ROUT5 (86)

O

ROUT6 (87)

O

ROUT7 (89)

O

GOUT0 (90)

2006/5/5

I

O

External TCON type select 2

R_EXTPIN (0x0C9[7]) = 1

GPI[1]


B-Port[2] Data Input GPI[2]












HSYNC Source 2 Input PWM3 Feedback Input VSYNC Source 2 Input PWM4 Feedback Input R Data [0] Output

R_GPO_SEL (0x08[0])=0

GPO [0] Output

R_GPO_SEL (0x08[0])=1

Power_Phase1 Output

R_GPO_SEL (0x08[0])=1 & R_POWER_SEL(0xBC[0])=1

R Data [1] Output

R_GPO_SEL (0x08[1])=0

GPO [1] Output

R_GPO_SEL (0x08[1])=1

Power_Phase2 Output

R_GPO_SEL (0x08[1])=1 & R_POWER_SEL(0x0DA[1])=1

R Data [2] Output

R_TCON_EN (0x037[7])=0

TCON STV1 Output/Input

R_TCON_EN (0x037[7])=1

R Data [3] Output

R_TCON_EN (0x037[7])=0

TCON STV2 Output/Input

R_TCON_EN (0x037[7])=1

R Data [4] Output

R_TCON_EN (0x037[7])=0

TCON CKV Output

R_TCON_EN (0x037[7])=1

R Data [5] Output

R_TCON_EN (0x037[7])=0

TCON FRP Output

R_TCON_EN (0x037[7])=1

R Data [6] Output

R_TCON_EN (0x037[7])=0

TCON LD Output

R_TCON_EN (0x037[7])=1

R Data [7] Output

R_TCON_EN (0x037[7])=0

TCON VCOM Output

R_TCON_EN (0x037[7])=1

G Data [0] Output

R_GPO_SEL (0x08[2])=0

GPO [2] Output

R_GPO_SEL (0x08[2])=1

Power_Phase3 Output





GOUT1 (92)

GOUT2 (100)

O

GOUT3 (102)

I/O

GOUT4 (103)

I/O

GOUT5 (105)

O

GOUT6 (107)

O

GOUT7 (109)

O

BOUT0 (110)

BOUT1 (111)

O

O

BOUT2 (113)

O

BOUT3 (114)

O

BOUT4 (116)

O

BOUT5 (117)

BOUT6 (119)

BOUT7 (120)

PWM1 (127)

PWM2 (128)

2006/5/5

O

O

O

O

O

O

BIT1611B

G Data [1] Output

R_GPO_SEL (0x08[3])=0

GPO [3] Output

R_GPO_SEL (0x08[3])=1

Power_Phase4 Output


G Data [2] Output

R_TCON_EN (0x037[7])=0

TCON OEH Output

R_TCON_EN (0x037[7])=1

G Data [3] Output

R_TCON_EN (0x037[7])=0

TCON STH1 Input / Output

R_TCON_EN (0x037[7])=1

G Data [4] Output

R_TCON_EN (0x037[7])=0

TCON STH2 Input / Output

R_TCON_EN (0x037[7])=1

G Data [5] Output

R_TCON_EN (0x037[7])=0

TCON CPH1 Output

R_TCON_EN (0x037[7])=1

G Data [6] Output

R_TCON_EN (0x037[7])=0

TCON CPH2 Output

R_TCON_EN (0x037[7])=1

G Data [7] Output

R_TCON_EN (0x037[7])=0

TCON CPH3 Output

R_TCON_EN (0x037[7])=1

B Data [0] Output

R_TCON_EN (0x037[7])=0

TCON_RL

R_TCON_EN (0x037[7])=1

Power_Phase5 Output

R_TCON_EN (0x037[7])=0 & R_POWER_SEL(0x0DA[4])=1

B Data [1] Output

R_TCON_EN (0x037[7])=0

TCON_UD

R_TCON_EN (0x037[7])=1

Power_Phase6 Output


B Data [2] Output

R_TCON_EN (0x037[7])=0

TCON GPO [0]

R_TCON_EN (0x037[7])=1

B Data [3] Output

R_TCON_EN (0x037[7])=0

TCON GPO [1]

R_TCON_EN (0x037[7])=1

B Data [4] Output

R_TCON_EN (0x037[7])=0

Q2H-BAR

R_TCON_EN (0x037[7])=1

B Data [5] Output

R_TCON_EN (0x037[7])=0

CKV_BAR

R_TCON_EN (0x037[7])=1

Power_Phase5 Output


B Data [6] Output

R_TCON_EN (0x037[7])=0

LD_BAR

R_TCON_EN (0x037[7])=1

Power_Phase6 Output


B Data [7] Output

R_TCON_EN (0x037[7])=0

OEH_BAR

R_TCON_EN (0x037[7])=1

PWM1 Output

R_GPO_SEL (0x08[4])=0

GPO [4] Output

R_GPO_SEL (0x08[4])=1

PWM3 Output

R_GPO_SEL (0x08[4])=0 & R_PWM3_SEL(0xD1[2])=1

PWM2 Output

R_GPO_SEL (0x08[5])=0

GPO [5] Output

R_GPO_SEL (0x08[5])=1

PWM4 Output

R_GPO_SEL (0x08[5])=0 &



BIT1611B

Beyond Innovation Technology Co., Ltd. Table 7-7 Mnemonic

Output Tri-State Control Register Address

R/W

bit

Description

Default

R_ROUT_TRI

0x007[0]

RW

1

ROUT Port Tri-State Enable

1

R_GOUT_TRI

0x007[1]

RW

1

GOUT Port Tri-State Enable

1

R_BOUT_TRI

0x007[2]

RW

1

BOUT Port Tri-State Enable

1

R_OCLK_TRI

0x007[3]

RW

1

OCLK pin Tri-State Enable

1

R_ODE_TRI

0x007[4]

RW

1

ODE pin Tri-State Enable

1

R_INT_TRI

0x007[5]

RW

1

INT Pin Tri-State Enable 1  Tri-State, 0 Normal

1

7-5 GPO (General Purpose Output ) Functi on BIT1611B provides 8 GPO Register control outputs. It may be programmed as: “Status”, ”High Level”, ”Low Level “ and “Tri-state”. The relative register settings please refer to Table 7-8 and Table 7-9.

Table 7-8 General Purpose Output Register Mnemonic

Address

R/W Bits

Description

Default

GPO Port Enable: R_GPO_SEL

0x008[5:0]

RW

6 0: Disable.

0x00

1: Enable. GPO Port Type: R_GPO_TYPE

0x009[5:0]

RW

6 0: Normal.

0x3F

1: Tri-State. GPO Port Value: R_GPO_REG

0x00A[7:0]

RW

8 0: Low Level.

0x00

1: High Level. GPO Output Source Select R_GPO_STATUS 0x101[2]

RW

1 0: From GPO Register

0

1: From Video decoder status Video decoder status output select R_VD_MON

0x103[7]

RW

1 0: Normal Status

0

1: Testing Only

2006/5/5



BIT1611B


Table 7-9

General Purpose Output Pads Setup Table

GPO Pin Name/ No.

Output Pin

GPO[0]

R_GPO_SEL[0] = 1,R_GPO_STATUS(0x101[2])=0

R_FIDT

R_GPO_SEL[0] = 1 R_GPO_STATUS(0x101[2])=1,R_VD_MON(0x103[7])=0

ROUT[0](78)

VD_VSYNC (For test only)


GPO[1]


R_STD_READY


ROUT[1](80)

VD_HSYNC (For test only)


GPO[2]


R_SYNC_READY


GOUT[0](90)

VD_HC (For test only)


GPO[3]


R_HLCK


GOUT[1](92)

VD_HSY (For test only)

2006/5/5

Register recommended setting


GPO[4]

PWM1(127)

R_GPO_SEL[4] = 1

GPO[5]

PWM2(128)

R_GPO_SEL[5] = 1

GPO[6]

RTS1(121)

R_RTS1_SEL[2:0] = 110

GPO[7]

RTS2(122)

R_RTS2_SEL[2:0] = 110



BIT1611B

Beyond Innovation Technology Co., Ltd. Data ROUT[1:0] R_GPO_REG(0x00A[1:0]) orVideoDecoderStatus

0 1

MUX

Pad(78,80)

R_GPO_SEL(0x008[1:0]) R_GPO_TYPE(0x009[1:0]) R_ROUT_TRI(0x007[0]) Data GOUT[1:0] R_GPO_REG(0x00A[3:2] ) OrVideoDecoderStatus R_GPO_SEL(0x008[3:2])

0 1

MUX

Pad(90,92)

_GPO_TYPE(0x009[3:2]) R_GOUT_TRI(0x007[1] ) R_GPO_TYPE(0x009[4]) PWM1Signal R_GPO_REG(0x00A[4])

0

Pad (127)

1 MUX

R_GPO_SEL(0x008[4]) R_GPO_TYPE(0x009[5]) PWM2Signal R_GPO_REG(0x00A[5])

0 1 MUX

Pad(128)

R_GPO_SEL(0x008[5])

000 001 Pad (121)

MUX _GPO_REG(0x00A[6])

110 111

R_RST1_SEL(0x026[2:0 ])

000 001 Pad (122)

MUX R_GPO_REG(0x00A[7])

110 111

R_RST2_SEL(0x026[6:4 ]) Figure 7-3 2006/5/5

GPO function



BIT1611B


7-6 System Enable and Reset BIT1611B provides Hardware Reset an d Software Reset functions.

7.6.1 Hard ware Reset BIT1611B may be reset to the “Power-On” status through Reset PIN (Pin 63) with a logic low signal, which is larger than 16 XCLK cycles time. Please refer to Figure 7-4 for the relative timing waveform.

eset u se must e onger t an cycles



RESET PIN Figure 7-4

Hardware Reset Waveform

7.6.2 Softw are Reset BIT1611B may reset the different functional blocks through setting the different registers. Table 7-10.

2006/5/5

Please refer to the

Table 7-10

Soft Reset Register

Mnemonic

Address

R/W

bit

R_SYNCDET_EN

0x00B[0]

RW

1

SYNCDET function soft reset.

1

R_PWM1_EN

0x00B[1]

RW

1

PWM1 function soft reset.

1

R_PWM2_EN

0x00B[2]

RW

1


1

R_PWM3_EN

0x00B[3]

RW

1


1

R_PWM4_EN

0x00B[4]

RW

1


1

R_SAMPLE_EN

0x00B[5]

RW

1

SAMPLE function soft reset.

1

R_SRST_VP

0x00C[0]

RW

1

Video Process function soft reset.

1

R_SRST_OUT

0x00C[1]

RW

1

Output function soft reset

1

R_SRST_OSD

0x00C[2]

RW

1

OSD function soft reset.

1

R_SRST_CHROMA

0x00C[3]

RW

1

Chroma Decoder function soft reset.

1

R_SRST_SYNC

0x00C[4]

RW

1

Sync Decoder function soft reset.

1

R_SRST_CLOCK

0x00C[5]

RW

1

Clock control function soft reset

1

R_SRST_AGC

0x00C[6]

RW

1

AGC function soft reset.

1

R_SRST_COMB

0x00C[7]

RW

1

Reserve (set to 1)

1

Description


Default


BIT1611B


7-7

Buil t-in DAC

Building three groups of DAC by offering Analog R , G , B to export in BIT1611B, its is relevant please consult Table 7-12 to establish Register:

Table 7-11

DAC Register

Mnemonic

Address

R/W bit

Description

Default

DAC Clock Phase Select 00: Phase 1 R_DACCLK_MODE

0x00E[3:2] RW

2 01: Phase 2

00

10: Phase 3 11: Phase 4 DAC LCLK Source polarity R_DAC_POL

0x00E[4]

RW

1 0: Normal

0

1: Invert DAC Clock polarity R_DAC_SEL

0x00E[5]

RW

1 0: Normal

0

1: Invert DAC Noise Reduce R_DAC_DG

0x00E[6]

RW

1 0: Disable

1

1: Enable DAC Enable R_DAC_EN

0x00E[7]

RW

1 0: Disable

0

1: Enable

2006/5/5



BIT1611B


7-8 Clock Domain Systems There are 4 clock domains in BIT1611B: 1. PCLK Domain: Source Clock 2. LCLK Domain: Panel Clock 3. XCLK Domain: System Clock 4. MCLK Domain: Image Clock The relative register settings please refer to Table 7-12 and Figure 7-5. NOTE

The frequency of XCLK Domain should be lower than LCLK Domain.

Table 7-12 Mnemonic

Clock Domain System Register Address

R/W bit

Description

Default

LCLK Domain Enable: R_LCLK_EN

0x00F[0]

RW

1 0: Disable.

1

1: Enable. LCLK Domain Polarity: R_POL_LCLK

0x00F[1]

RW

1 0: Normal.

0

1: Invert. LCLK Domain Clock Source Select: 00: ICLK1. R_LCLK_SEL

0x00F[3:2]

RW

2 01: ICLK2.

11

10: PLLCLK 11: OSCCLK PCLK Domain Enable: R_PCLK_EN

0x00F[4]

RW

1 0: Disable.

1

1: Enable. PCLK Domain Polarity: R_POL_PCLK

0x00F[5]

RW

1 0: Normal.

0

1: Invert. PCLK Domain Clock Source Select: R_ PCLK_SEL

0x00F[6]

RW

1 0: ICLK1.

1

1: ICLK2. XCLK Domain Clock Source Select: 00: OSCCLK. (OSCCLK=Oscillator Frequency)) R_XCLK_SEL

0x00E[1:0]

RW

2 01: OSCCLK / 2.

00

10: OSCCLK / 4. 11: OSCCLK / 8. R_MCLK_MODE

0x050[7:5]

RW

3

MCLK Domain Clock Source Select MCLK = PCLK / (R_MCLK_MODE+1)

001

Video Decoder Path Clock Source Select R_VD_CLK1

0x101[6]

RW

1 0: Normal Path (ICLK1 or ICLK2)

0

1: Video Decoder Clock (27MHz) Video Decoder Path Clock Source Select R_VD_CLK2

0x101[7]

RW

1 0: Normal Path (ICLK1、ICLK2、PLLCLK、OSCCLK)

0

1: Video Decoder Clock (27MHz)

2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. R_PCLK_SEL ICLK1

0 1

ICLK2

R_VD_CLK1

MUX

0

0 1

InternalVD Clock(135Mhz )

MUX

M U 1 X

R_LCLK_SEL[0] 0 1

DIV

MUX

PLL

MCLK

R_MCLK_MODE R_VD_CLK2R_POL_LCLK

00 01 10 11

PCLK

R_PCLK_EN

R_LCLK_SEL

OS C

0

M 1 U X

R_PCLK_SEL

InternalVD Clock(27Mhz)

R_POL_PCLK

M U 1 X 0

M U X

MUX

LCLK

R_LCLK_EN PLLCLK

R_XCLK_SEL OSCCL K

DIV

00 01 10 11

XCLK

MUX

Figure 7-5

Clock Select Function

7-9 Panel Timin g Setup The output signal timing to panel can be set by BIT1611B according to EVEN or ODD field. Refer to Table 7-13. The related timing definition please refers to Figure 7-6. Table 7-13 Mnemonic R_OS_XP R_OS_XS R_OS_XW R_OSE_XT_M0 R_OSO_XT_M0 R_OSE_XT_M1 R_OSO_XT_M1

2006/5/5

Panel Timing Setup register Address 0x013[5:4], 0x010[7:0] 0x013[3:2], 0x011[7:0] 0x013[1:0], 0x012[7:0] 0x016[5:4], 0x014[7:0] 0x016[1:0], 0x015[7:0] 0x01C[5:4], 0x01A[7:0] 0x01C[1:0], 0x01B[7:0]

R/W

bit

Description

RW

10

HSYNC Pulse Width

0x010

RW

10

Active Window Horizontal Start Position

0x020

RW

10

Active Window Horizontal End Position

0x200

RW

10

RW

10

RW

10

RW

10

Horizontal Total Length for EVEN Field on Mode 0 Horizontal Total Length for ODD Field on Mode 0 Horizontal Total Length for EVEN Field on Mode 1 Horizontal Total Length for ODD Field on Mode 1

Default

0x2C4 0x2C4 0x23E 0x23E

R_OS_YP

0x020[7:0]

RW

8

VSYNC Pulse Width

0x002

R_OS_YS

0x021[7:0]

RW

8

Active Window Vertical Start Position

0x005

R_OS_YW

0x024[1], 0x022[7:0]

RW

9

Active Window Vertical End Position

0x0EF

R_OS_YT

0x024[0], 0x023[7:0]

RW

9

Vertical Total Length

0x0FC



BIT1611B


(0,0)

HSYNC Output R_OS_XP S Y _ S O _ R

Blank Range

P Y _ S O _ R

W Y _ S O _ R

Panel Active Window

T Y _ S O _ R

R_OS_XS R_OS_XW

VSYNC Output

R_OSE_XT R_OSO_XT

Figure 7-6

Panel Timing Setup

7-10 Out put Data Path The output data bus can be inverted, rotated and swapped.

Table 7-14 Mnemonic

2006/5/5

Refer to Table 7-14 and Figure 7-7.

Output Data Path Register Address R/W

bit

Description

Default

R_SWAPE_ORB 0x024[2]

RW

1

R data output Swap with B data output on EVEN Field 0: swap disable; 1: swap enable

0

R_SWAPE_ORG 0x024[3]

RW

1

R data output Swap with G data output on EVEN Field 0: swap disable; 1: swap enable

0

R_SWAPE_OGB 0x024[4]

RW

1

G data output Swap with B data output on EVEN Field 0: swap disable; 1: swap enable

0

R_SWAPO_ORB 0x024[5]

RW

1

R data output Swap with B data output on ODD Field 0: swap disable; 1: swap enable

0

R_SWAPO_ORG 0x024[6]

RW

1

R data output Swap with G data output on ODD Field 0: swap disable; 1: swap enable

0

R_SWAPO_OGB 0x024[7]

RW

1

G data output Swap with B data output on ODD Field 0: swap disable; 1: swap enable

0

R_POL_ROUT

0x025[0]

RW

1

R Data output Polarity  0:normal 1:invert

0

R_POL_GOUT

0x025[1]

RW

1

G Data output Polarity  0:normal 1:invert

0

R_POL_BOUT

0x025[2]

RW

1

B Data output Polarity  0:normal 1:invert

0

R_ROL_ROUT

0x025[4]

RW

1

R Data Rotate  0:disable 1:enable

0

R_ROL_GOUT

0x025[5]

RW

1

G Data Rotate  0:disable 1:enable

0

R_ROL_BOUT

0x025[6]

RW

1

B Data Rotate  0:disable 1:enable

0

R_OCLK_POL

0x025[7]

RW

1

Output Clock Polarity  0:normal 1:invert

0



BIT1611B


Figure 7-7

Output Data Path Select

7-11 Serial RGB Output Mode The output format of BIT1611B can be a serial RGB signal. The serial RGB output format can be defined to any one of ROUT, GOUT and BOUT ports. Please refer to Table 7-15. Table 7-15 Mnemonic

Serial RGB Output Register Address R/W Bits

Description

Default

Serial-RGB format output enable R_SERIAL_OUT

0x025[3]

RW

1

0

0: Disable 1: Enable

7-12 Special Output Setup RTS1 (pin 121) and RTS2 (pin 122) are 2 special outputs of BIT1611B. Their functions can be decided by special registers, please refer to Table 7-16. Table 7-16 Special Output Pads Setup Register Mnemonic

Address

R/W

bit

Description

Default

000: Output HSYNC Signal 001: Output HREF Signal 010: Output VSYNC Signal R_RTS1_SEL 0x26[2:0]

RW

3

011: Output VREF Signal 100: Output EVEN/ODD Signal

111

101: PWM3 110: General Output Port Bit [6] (R_GPO_REG[6]) 111: Tri-State Output R_RTS2_SEL 0x26[6:4]

RW

3 000: Output HSYNC Signal

111

001: Output HREF Signal 010: Output VSYNC Signal 011: Output VREF Signal 100: Output EVEN/ODD Signal 101: PWM4 2006/5/5



BIT1611B


110: General Output Port Bit [7] (R_GPO_REG[7]) 111: Tri-State Output

7-13 Special Timing Adj ust ment BIT1611B provides 2 timing adjustment modes to fit the various requirements of panels. Please refer to Table 7-17.

7.13.1 Synchroni zation Timing Output Vsync signal will be synchronized with input Vsync signal by this mode.

Input VSYNC Output VSYNC Figure 7-8

7.13.2

Synchronization Timing

Two-Fields Synchroni zation Timing Output Vsync signal will be decided by even/odd field Vsync and R_OS_YT (0x024[0], 0x023[7:0]).

Figure 7-9

Table 7-17

Two-Fields Synchronization Timing

Special Timing Adjust Register

Mnemonic

Address R/W

bit

Description

Default

Sync. With input VSYNC enable R_SYNCO_EN

0x013[6]

RW

1

0: Two-Fields Synchronization Mode

1

1: Synchronization Mode Two-Field Synchronization Mode Select R_SYNCO_MODE

0x013[7] RW

1

0: EVEN Field Synchronize

0

1: ODD Field Synchronize Minimum Output Lines protect R_PROTECT_MODE

0x026[7] RW

1

0: Disable

1

1: Enable

2006/5/5



BIT1611B


7-14 TCON Function BIT1611B has a programmable TCON function inside and that can control the analog panels directly. Table 7-18 Mnemonic

TCON Function Register Address

R/W

bit

Description

Default

R_STV_START

0x029[0], 0x027[7:0]

RW

9 STV Signal Start

0x002

R_STV_END

0x029[1], 0x028[7:0]

RW

9 STV Signal End

0x003

VCOM Signal TYPE 00: Always 0 R_VCOM_TYPE

0x029[3:2]

RW

2 01: Always 1

11

10: FRP Invert 11: FRP FRP Output Polarity R_POL_FRP

0x029[4]

RW

1 0: Normal

0

1: Invert R_STH_START

0x02E[5:4], 0x02A[7:0]

RW

10 STH Signal Start

0x01D

R_STH_END

0x02E[7:6], 0x02B[7:0]

RW

10 STH Signal End

0x020

R_CKV_START

0x02E[1:0], 0x02C[7:0]

RW

10 CKV Signal Start

0x027

R_CKV_END

0x02E[3:2], 0x02D[7:0]

RW

10 CKV Signal End

0x051

R_LD_START

0x033[5:4], 0x02F[7:0]

RW

10 LD Signal Start

0x001

R_LD_END

0x033[7:6], 0x030[7:0]

RW

10 LD Signal End

0x037

R_OEH_START

0x033[1:0], 0x031[7:0]

RW

10 OEH Signal Start

0x014

R_OEH_END

0x033[3:2], 0x032[7:0]

RW

10 OEH Signal End

0x015

R_VCOM_SHIFT

0x035[1:0],0x034[7:0]

RW

10 VCOM Shift

0x064

Data Bus Control on FRP 00: Disable R_BUS_INV

0x035[3:2]

RW

2 01: Follow Shift VCOM

00

10: Follow FRP 11: Follow Invert FRP R_POL_OEH

0x036[0]

RW

1 OEH Output Polarity

0

R_POL_STH

0x036[1]

RW

1 STH Output Polarity

0

STV Output Polarity R_POL_STV

0x036[2]

RW

1 0: Normal

0

1: Invert R_TCON_GPO

0x036[5:3]

RW

3 TCON GPO Register

000

OEH gated with ODE R_OEH_GATE

0x036[6]

RW

1 0: Disable

1

1: Enable LTPS Mode Select R_LTPS_MODE

0x036[7]

RW

1 0: Normal Mode

0

1: LTPS TCON Mode STH Output Select R_STH_SEL

0x037[0]

RW

1 0: STH1 = OUT STH2= IN

0

1: STH1 = IN, STH2 = OUT STV Output Select R_STV_SEL

0x037[1]

RW

1 0: STV1 = OUT STV2= IN

0

1: STV1 = IN, STV2 = OUT R_TCON_RL 2006/5/5

0x037[2]

RW

1 TCON R/L Signal


0 page 35 of 109 DOC NO.W-DS-0004

BIT1611B

Beyond Innovation Technology Co., Ltd. 0: Low Level 1: High Level TCON U/D Signal R_TCON_UD

0x037[3]

RW

1 0: Low Level

0

1: High Level R _Q2H_POL

0x037[4]

RW

1 Q2H Output Polarity

0

R_POL_LD

0x037[5]

RW

1 LD Output Polarity

0

CKV Output Polarity R_POL_CKV

0x037[6]

RW

1 0: Normal

0

1:Invert TCON Function Enable R_TCON_EN

0x037[7]

RW

1 0: Disable

0

1: Enable

7-15 TCON Clock Mode BIT1611B provides 2 kinds of TCON clock mode for panels：

LCLK TYPE1

LCLK TPYE2 TYPE3 TYPE4 Figure 7-10

Table 7-19 Mnemonic

TCON Clock Mode

TCON Clock Mode Register Address

R/W Bits

Description

Default

TCON Clock Output Mode R_CPH_HALF

0x029[5]

RW

1 0: Normal Mode

0

1: Half Clock Mode CLK TYPE Select R_3CLK_SEL

0x029[6]

RW

1 0: Normal

1

1: 3 Clocks Mode CPH Clock Mode R_CPH_MODE

0x029[7]

RW

1 0: Delta-Panel Clock Mode

0

1: Stripe-Panel Clock Mode R_CPH1_PHASE

0x038[2:0]

RW

3 TCON CPH1 clock delay phase

000

Bit[0] Enable => 2ns Delay Bit[1] Enable => 4ns Delay 2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. Bit[2] Enable => 7ns Delay CPH1 Clock polarity R_CPH1_POL

0x038[3]

RW

1 0: Normal

0

1: Invert TCON CPH2 clock delay phase R_CPH2_PHASE

0x038[6:4]

RW

3

Bit[0] Enable => 2ns Delay Bit[1] Enable => 4ns Delay

000

Bit[2] Enable => 7ns Delay CPH2 Clock polarity R_CPH2_POL

0x038[7]

RW

1 0: Normal

0

1: Invert TCON CPH3 clock delay phase R_CPH3_PHASE

0x035[6:4]

RW

3

Bit[0] Enable => 2ns Delay Bit[1] Enable => 4ns Delay

000

Bit[2] Enable => 7ns Delay CPH3 Clock polarity R_CPH3_POL

0x035[7]

RW

1 0: Normal

0

1: Invert R_CPH1_SEL_M0

0x039[1:0]

RW

2 CPH1 Source Select for Even Field

00

R_CPH2_SEL_M0

0x039[3:2]

RW

2 CPH2 Source Select for Even Field

00

CPH3 Source Select for Even Field 00: Type 1 Clock R_CPH3_SEL_M0

0x039[5:4]

RW

2 01: Type 2 Clock

00

10: Type 3 Clock 11: Type 4 Clock R_CPH1_SEL_M1

0x03A[1:0]

RW

2 CPH1 Source Select for Odd Field

00

R_CPH2_SEL_M1

0x03A[3:2]

RW

2 CPH2 Source Select for Odd Field

00

CPH3 Source Select for Odd Field 00: Type 1 Clock R_CPH3_SEL_M1

0x03A[5:4]

RW

2 01: Type 2 Clock

00

10: Type 3 Clock 11: Type 4 Clock R_CPH1_EN

0x039[6]

RW

1 CPH1 output enable

1

R_CPH2_EN

0x03A[6]

RW

1 CPH2 output enable

1

CPH3 output enable R_CPH3_EN

0x03A[7]

RW

1 0: Disable

1

1: enable

7-16 External Pin Setup For some registers; TCON R_TCON_STH、R_TCON_STV、R_TCON_RL、R_TCON_UD and R_POL_Q2H; BIT1611B can program them through external pins. Please refer to following tables and figure. Table 7-20 Mnemonic

2006/5/5

External Pin Setup Address

R/W bit

Description

Default

R_M0_STH

0x0C8[0]

RW

1 R_TCON_RL Setting on BIN[1:0]==01

0

R_M0_STV

0x0C8[1]

RW

1 R_TCON_UD Setting on BIN[1:0]==01

0

R_M0_RL

0x0C8[2]

RW

1 R_TCON_STH Setting on BIN[1:0]==01

0



BIT1611B

Beyond Innovation Technology Co., Ltd. R_M0_UD

0x0C8[3]

RW

1 R_TCON_STV Setting on BIN[1:0]==01

0

R_M0_Q2H

0x0C8[4]

RW

1 R_TCON_Q2H Setting on BIN[1:0]==01

0

R_M1_STH

0x0C8[5]

RW


0

R_M1_STV

0x0C8[6]

RW


0

R_M1_RL

0x0C8[7]

RW


0

R_M1_UD

0x0C9[0]

RW


0

R_M1_Q2H

0x0C9[1]

RW


0

R_M2_STH

0x0C9[2]

RW


0

R_M2_STV

0x0C9[3]

RW


0

R_M2_RL

0x0C9[4]

RW


0

R_M2_UD

0x0C9[5]

RW


0

R_M2_Q2H

0x0C9[6]

RW


0

External pin setup enable R_EXTPIN

0x0C9[7]

RW

1 0: Disable

0

1: Enable STH,STV,RL,UD and Q2H synchronize with R_TCON_SYNC

0x039[7]

RW

1 0: Disable

0

1: Enable

Table 7-21 External Pin

External Pin Setup Mapping Pin Number

Mapping Internal Register

BIN[0]

57

External Mode Select 0

BIN[1]

58

External Mode Select 1

Figure 7-11 External Pin Setup

2006/5/5



BIT1611B


7-17 Display Layer The display has 5 layers in priority. Higher layer in the same position may over write pixels of lower layer. Please refer to Figure 7-12 of the whole structure.

Figure 7-12

Display Layer

7-18 Backgro und 2 BIT1611B supports 64 colors of background for border in 4:3 display modes. The register settings and their description are showed below Table 7-22. Table 7-22 Mnemonic

Background 2 Register Address

R/W

bit

R_BG2_R

0x03B[5:4]

RW

2

R_BG2_B

0x03B[3:2]

RW

2

R_BG2_G

0x03B[1:0]

RW

2

Description Background 2’s R Color used for 4:3 display Background 2’s B Color used for 4:3 display Background 2’s G Color used for 4:3 display

Default 11 00 00

Blank enable before image process R_ZERO1_EN

0x08A[6]

RW

1

0: Disable

0

1: Enable Blank enable after image process R_ZERO2_EN

0x08A[7]

RW

1

0: Disable

0

1: Enable

2006/5/5



BIT1611B


7-19 Backg roun d and Test Pattern Setup BIT1611B includes 8 kinds of display patterns for testing, pure (262144 colors) and gradient. and their description are showed below Table 7-23. Table 7-23

The register settings

Background and Test Pattern Register

Mnemonic

Address

R/W

Bits

Description

Default

R_TESTPAT_R

0x03C[5:0]

RW

6

Test Pattern R Color Value

0x00

R_TESTPAT_G

0x03D[5:0]

RW

6

Test Pattern G Color Value

0x00

R_TESTPAT_B

0x03E[5:0]

RW

6

Test Pattern B Color Value

0x3F

R_TESTPAT_RATIO

0x03F[7:0]

RW

8

Test Pattern gradient ratio

0xE8

Test Pattern Type 000: 262144 color

R_TESTPAT_TYPE

0x040[2:0]

RW

3

001:R: gradient G: set by R_TESTPAT_G B: set by R_TESTPAT_B 010: R: set by R_TESTPAT_R G: gradient B: set by R_TESTPAT_B 011: R + G: gradient B: set by R_TESTPAT_B 100: R: set by R_TESTPAT_R G: set by R_TESTPAT_G B: gradient 101: R+B: gradient G: set by R_TESTPAT_G 110: R: set by R_TESTPAT_R G+B: gradient

000

111: R+G+B: gradient Gradient direction R_TESTPAT_HV

0x040[4]

RW

1

0:Vertical

1

1:Horizonal Gradient rate R_TESTPAT_DIRECT

0x040[5]

RW

1

0: Decrease

0

1: Increase Background Mode Enable R_BACKGROUND_EN

0x040[6]

RW

1

0: Disable

0

1: Enable Free-Run Mode Enable R_FREERUN_EN

0x040[7]

RW

1

0: Disable

1

1: Enable

7-20 Auto Blue Screen BIT1611B shows “Blue Screen” automatically when input signal is terminated or input mode is changed. Table 7-24

2006/5/5

Blue Screen Register

Mnemonic

Address

R_AUTOON_TIME

0x041[6:0]

R/W

Bits

RW

7

Description Blue Screen to Normal Screen Delay times (based on VSYNC)


Default 0x0F page 40 of 109 DOC NO.W-DS-0004

BIT1611B

Beyond Innovation Technology Co., Ltd. Blue Screen Function Enable R_AUTOON_EN

0x041[7]

RW

1

0


7-21 Input Image Windo w Setup The registers in Table 7-25 decide input image window area. be calculated for matching to the screen, refer to Figure 6-12. Table 7-25

Input Crop Register

Mnemonic R_IS_XS_M0 R_IS_XW_M0 R_IS_YS_M0 R_IS_YW_M0 R_IS_XS_M1 R_IS_XW_M1 R_IS_YS_M1 R_IS_YW_M1

Within the Input Image Window, each pixel data will

Address 0x044[2:0], 0x042[7:0] 0x044[6:4], 0x043[7:0] 0x047[1:0], 0x045[7:0] 0x047[5:4], 0x046[7:0] 0x04A[2:0], 0x048[7:0] 0x04A[6:4], 0x049[7:0] 0x04D[1:0], 0x04B[7:0] 0x04D[5:4], 0x04C[7:0]

R/W

bit

Description

RW

11 Mode0 Input Window horizontal Start Position 0x098

RW

11 Mode0 Input Window horizontal End Position

0x358

RW

10 Mode0 Input Window vertical Start Position

0x015

RW

10 Mode0 Input Window vertical End Position

0x135

RW

11 Mode1 Input Window horizontal Start Position 0x094

RW

11 Mode1 Input Window horizontal End Position

0x354

RW

10 Mode1 Input Window vertical Start Position

0x015

RW

10 Mode1 Input Window vertical End Position

0x0FF

(0,0)

Default

HSYNC Input Blank Range

Input Image Window

S Y _ S I _ R

W Y _ S I _ R

R_IS_XS R_IS_XW

VSYNC Input Figure 7-13

2006/5/5

Input Window Setup



BIT1611B


7-22 Inp ut Data Path Setup Input data ports of BIT1611B can be inversed, rotated and swapped through the registers. Refer to Table 7-24 and Figure 7-13. Table 7-26

Output Data Path Register

Mnemonic

Address R/W

bit

Description

Default

R_POL_RIN

0x04E[0]

RW

1

R Data input Polarity  0:normal 1:invert

0

R_POL_GIN

0x04E[1]

RW

1

G Data input Polarity  0:normal 1:invert

0

R_POL_BIN

0x04E[2]

RW

1

B Data input Polarity  0:normal 1:invert

0

R_ROL_RIN

0x04E[3]

RW

1

R Data Rotate  0:disable 1:enable

0

R_ROL_GIN

0x04E[4]

RW

1

G Data Rotate  0:disable 1:enable

0

R_ROL_BIN

0x04E[5]

RW

1

B Data Rotate  0:disable 1:enable

0

R_ISWAP_RB

0x04F[0]

RW

1

R Data bus swap B Data bus  0:disable 1:enable

0

R_ISWAP_RG

0x04F[1]

RW

1

R Data bus swap G Data bus  0:disable 1:enable

0

R_ISWAP_GB

0x04F[2]

RW

1

G Data bus swap B Data bus  0:disable 1:enable

0

Data Path Select R_VD_PATH

0x101[4]

RW

1

0

0: Normal Path ( R,B,G Port) 1: Video Decoder Path

R_RIN_EN

0x04F[4]

RW

1

RIN Port Enable

1

R_GIN_EN

0x04F[5]

RW

1

GIN Port Enable

1

BIN Port Enable R_BIN_EN

0x04F[6]

RW

1

1


RData 0 M Port U VDY 1 X Data R_VD_PATH

BData Port VDU Data

0

1

M U X

R_VD_PATH

GData 0 M Port U VDV 1 X Data R_VD_PATH

1

0

M U X

R_POL_RIN

1

0

M U X

R_POL_BIN 1

0

0

1

M U X

0

R_ISWAP_RB 0

1

0

R_POL_GIN

M U X

Rotat e

0

1

0

M U X

R_ISWAP_RG R_ISWAP_GB

1

0

R_ISWAP_GB

M U X

M U X

Pre_RI N

R_ROL_RIN 1

1

1

0

R_ISWAP_RG

R_ISWAP_RB

M U X

Rotat e

M U X

M U X

Figure 7-14

2006/5/5

1

M U X

Pre-BIN

R_ROL_BIN

Rotat e

1

0

M U X

Pre-GIN

R_ROL_GIN

Input Data Path Setup



BIT1611B


7-23 Input Format BIT1611B supports 7 types of Input formats: ITU656、ITU656-Like、ITU601、RGB888、RGB565、Serial-RGB and YUV444.

7.23.1

ITU656 8 bits, including EVEN/ODD, HSYNC, VSYNC and YUV data. (27MHz input frequency)

7.23.2

ITU656-Like 8 bits, including YUV data, while HSYNC, VSYNC need to be provided from additional input pins. (27MHz input frequency)

FF

00

00

EAV

80

10

....

FF

Figure 7-15

7.23.3

00

00

SAV

U0

Y0

V0

Y1

U2

Y2

....

ITU656/656-like input

ITU601 16 bits, ITU video signal (13.5 MHz input frequency)

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

U0

V0

U2

V2

U4

V4

U6

V6

U8

V8

U10

V10

U12

V12

U14

V14

U15

Figure 7-16

7.23.4

....

ITU601 input

RGB888 24 bits, VGA format. BIT1611B supports max. resolution of 640x480 (@60Hz).

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

R16

G0

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

B 10

B11

B12

B13

B14

B15

B16

Figure 7-17

2006/5/5

....

RGB 8:8:8 input



BIT1611B

Beyond Innovation Technology Co., Ltd. 7.23.5

Serial-RGB BIT1611B supports max. 40 MHz serial data ratio.

R0

G0

B0

R1

G1

B1

R2

G2

B2

Figure 7-18

7.23.6

R3

G3

B3

R4

....

Rn

Gn

Bn

....

Serial-RGB input

YUV444 YVU 4:4:4 format (YUV Color Space Mode), BIT1611B supports max. resolution of 640x480 (@60Hz).

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

U0

U1

U2

U3

U4

U5

U6

U7

U8

U9

U10

U11

U12

U13

U14

U15

U16

V0

V1

V2

V3

V4

V5

V6

V7

V8

V9

V10

V11

V12

V13

V14

V15

V16

Figure 7-19

....

YUV 4:4:4 input

7-24 Input Mode Selectio n The input mode of BIT1611B can be selected by setting registers, refer to Table 7-27 and Figure 7-20. Table 7-27 Mnemonic

Input Mode Select Register Address

R/W

Bits

Description

Default

Input Mode Select R_IMODE

0x050[0]

RW

1

0

0: YUV Domain Source Input 1: RGB Domain Source Input Source Format Select RGB Domain Source  R_IMODE= 1 00: Serial-RGB Format 01: RGB 5:6:5 Format

R_SRC_SEL

0x050[2:1]

RW

2

00

1x: RGB 8:8:8 Format YUV Domain Source  R_IMODE = 0 00: ITU656 / ITU656-Like Format 01: ITU601 Format 1x: YUV 4:4:4 Format Input Active Pixel Mode

R_PIXEL_MODE

0x050[4:3]

RW

2

00: 1 Pixel Mode ( RGB888、RGB565、YUV444、 ITU601) 01: 2 Pixel Mode (ITU656/ITU656-Like)

01

10: 3 Pixel Mode (Serial RGB) 11: 4 Pixel Mode R_SORT_656 2006/5/5

0x051[2:0]

RW

3

ITU656 / ITU601 Format Control


 Data

sequence Shift

000 page 44 of 109 DOC NO.W-DS-0004

BIT1611B

Beyond Innovation Technology Co., Ltd. X00: No Shift X01: Shift 1 Clock X10: Shift 2 Clocks X11: Shift 3 Clocks Serial – RGB Format Control

 Serial-Bus

Data Sort

000: Always 0 001: R-G-B 010: R-B-G 011: G-R-B 100: G-B-R 101: B-G-R 110: B-R-G 111: Always 1 RGB 5:6:5 Format  Data compensation mode X0X: Compensate with R_SORT_656[0]. X1X: Compensate with LSB Data. R_POL_IHS

0x051[3]

RW

1

External HSYNC polarity  0:Normal, 1:Invert

0

R_POL_IVS

0x051[4]

RW

1

External VSYNC polarity  0:Normal, 1:Invert

1

External Sync Enable 00: Internal ITU656 Decoder R_EXT_SYNC

0x051[6:5]

RW

2

01: CSYNC 10: External Sync 2 signal (R_VD_SYNC = 0)

00

10: Video Decoder Sync (R_VD_SYNC = 1) 11: External Sync 1 signal Sync Select R_VD_SYNC

0x101[5]

RW

1

0: Normal Path (External HSYNC,VSYNC)

0

1: Internal Video Decoder SYNC EVEN/ODD Signal Select 00: ITU656-EVEN Signal R_SEL_EVEN

0x052[1:0]

RW

2

01: Visual EVEN/ODD Signal

00

10: Always EVEN Field 11: Always ODD Field Visual EVEN/ODD Mode R_VISUAL_TYPE

0x052[2]

RW

1

0: Normal EVEN/ODD Mode

0

1: Always Change by VSYNC One Line Shift Mode R_SHIFT_EN

0x052[3]

RW

1

0: Disable

0

1: Enable One Line Shift Base R_EVEN_TYPE

0x052[4]

RW

1

0: Even Field

0

1: ODD Field

2006/5/5



BIT1611B


0

1

Figure 7-20

Input Mode Select

7-25 CSYNC Decoder BIT1611B supports the Csync decoder which separates Csync into Hsync and Vsync. Table 7-28 Mnemonic

Please refer to Table 7-28.

CSYNC Decoder register Address R/W

Bits

Description

Default

CSYNC Source Select R_CSYNC_SEL

0x052[5] RW

1

0: from HSYNC1 or HSYNC2

0

1: from VSYNC1 or VSYNC2 CSYNC Decoder HSYNC Output Polarity R_CSYNC_HS

0x052[6] RW

1

0: Normal

0

1: Invert CSYNC Decoder VSYNC Output Polarity R_CSYNC_VS

0x052[7] RW

1

0: Normal

0

1: Invert

2006/5/5



BIT1611B


7-26 Auto Switch BIT1611Bprovides 2 sets of registers, switch between auto and manual modes for Input Window, Re-size Factor and Timing Setup. BIT1611B detects and decides for 50Hz(Mode 0)/60Hz(Mode 1) input signal automatically when it is in auto mode.

Table 7-29

Auto Switch Register

Mnemonic

Address R/W

Bits

Description

Default

Auto Switch Mode R_AUTO_SWITCH

0x04E[6]

RW

1

1

0: Manual Mode 1: Auto Mode Manual Mode Select

R_SWITCH_MODE

0x04E[7]

RW

1

1

0: Select Mode0 1: Select Mode1

7-27 Display Window Setup “Display Window”, defined by BIT1611B, is a specified image area that well-produced image shows onto t his area within suitable timing adjustment; refer to Table 7-27 for related registers. Table 7-30

Display Windows Register

Mnemonic

Address

R/W

bit

Description

Default

R_DIS_YS

0x053[7:0]

RW

8 Display Window Vertical Start Position

0x005

R_DIS_YW

0x059[2], 0x054[7:0]

RW

9 Display Window Vertical End Position

0x0EF

R_DIS_ACTY

0x059[1], 0x055[7:0]

RW

9 Display Window Vertical Active Height

0x0EA

R_DIS_XS R_DIS_XW

0x059[5:4], 0x056[7:0] 0x059[7:6], 0x057[7:0]

R_DIS_ACTX 0x059[0], 0x058[7:0]

RW

10 Display Window Horizontal Start Position

0x020

RW

10 Display Window Horizontal End Position

0x200

RW

9 Display Window Active Horizontal Width

0x1E0

(0,0)

HSYNC Output R_OS_XP

Blank Range Panel Active Window

P Y _ S O _ R

Display Window

R_DIS_XS

VSYNC Output

R_DIS_ACTX

Y T C A _ S I D _ R

W Y _ S I D _ R

Background Color

R_DIS_XW

Figure 7-21

2006/5/5

S Y _ S I D _ R

Display Window Setup



BIT1611B


7-28 Re-size Engine BIT1611B adjusts the source pictures to display screen in horizontal and vertical directions. explain how BIT1611B do the re-sizing of display.

Following sections

Horizontal Non-Linear Resize-Down Horizontal Three-Step Resize-Down

Data Input

Buffer

M U X

Vertical Linear ResizeDown

Data Output

Horizontal Linear Resize-Down ResizeupRate

ResizeupRate

ResizeupRate

Position

Linear Mode

Position

Three-Step Mode Figure 7-22

7.28.1

Position

Non-Linear Mode

Re-size function

Horizon tal Re-size Down

For the panel which display resolution is smaller than i t from the source, BIT1611B reduces the display size in horizontal direction. Table 7-31

Horizontal Scale Down Register

Mnemonic

Address

R/W bit

Description

Default

R_SCX_P1_START

0x05C[3:0], 0x05A[7:0] RW 12 Horizontal Phase1 Start Value

0x03C

R_SCX_P2_START

0x05C[7:4], 0x05B[7:0] RW 12 Horizontal Phase2 Start Value

0x0E5

R_SCX1_SHIFT

0x05F[2:0], 0x05D[7:0]

RW 11 Horizontal Zone 1 Shift Value

0x177

R_SCX1_FIX

0x05F[5:4], 0x05E[7:0]

RW 10 Horizontal Zone 1 Fix Value

0x0E0

Horizontal Scaling Enable R_SCALEX_EN

0x060[0]

RW

1 0: Disable (Bypass Mode)

1

1: Enable (Scale Mode) Horizontal Scaling Filter Type R_SCALEX_FILTER

0x060[2:1]

RW

2

11: Triangle Filter 10: Box Filter

11

0x: Filter Disable R_SHAKE_MODE

0x060[3]

RW

1 Shake Mode Select

0

0: Field Shake Mode 2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 1: Line Shake Mode Wide Screen Mode Enable R_WIDESCREEN_EN

0x060[6]

RW

1 0: Disable

0

1: Enable Wide Screen Type

R_WIDESCREEN_TYP 0x060[7] E

RW

1 0: 3-Zone Wide Screen

0

1: Non-Liner Wide Screen R_SCX2_SHIFT

0x067[3:2], 0x061[7:0]


0x000

R_SCX3_SHIFT

0x067[5:4], 0x062[7:0]


0x000

R_SCX2_FIX

0x067[0], 0x063[7:0]

RW

9 Horizontal Zone 2 Fix Value

0x000

R_SCX3_FIX

0x067[1], 0x064[7:0]

RW

9 Horizontal Zone 3 Fix Value

0x000

R_ANZOOM_R1

0x067[6], 0x065[7:0]

RW

9 Non-Linear Increase Value

0x000

R_ANZOOM_R2

0x067[7], 0x066[7:0]

RW

9 Non-Linear Decrease Value

0x000

7.28.2

Vertic al Re-size Down

BIT1611B can reduce the display size in vertical direction for Even/Odd fields independently. source picture to a low-resolution panel. Table 7-32

That will fit the

Vertical Scale-Down Register

Mnemonic R_SCYE_START_M0 R_SCYO_START_M0 R_SCY_SHIFT_M0 R_SCY_FIX_M0

R_VSCALE_EN_M0

Address 0x06A[1:0], 0x068[7:0] 0x06A[5:4], 0x069[7:0]

R/W bit

Description

Vertical Start Value for EVEN Field on Switch Mode 0 Vertical Start Value for ODD Field RW 10 on Switch Mode 0 Vertical Shift Value on Switch 0x06D[4], 0x06B[7:0] RW 9 Mode 0 Vertical Fix Value on Switch Mode 0x06D[6], 0x06C[7:0] RW 9 0 Vertical Scaling Function Enable on Switch Mode 0 0x06D[0] RW 1 0: Disable (Bypass Mode) RW 10

Default 0x01E 0x0BB 0x100 0x000

1

1: Enable (Scale Mode) Vertical Scaling Filter Enable on Switch Mode 0 R_VSCALE_FILTER_M0

0x06D[2:1]

RW

2 11: Triangle Filter 10: Box Filter

11

0x: Filter Disable

R_CUT_AUTO_M0

0x06D[3]

RW

1

Vertical Pre-Scaling Change Mode on Switch Mode 0 0: Manual (R_CUT_MODE)

0

1: Auto (EVEN/ODD)

R_LINE_CUT_M0

0x06D[5]

RW

1

Vertical Pre-Scaling Down Enable on Switch Mode 0 0: Disable

0

1: Enable

R_CUT_MODE_M0

0x06D[7]

RW

1

Vertical Pre-Scaling Down Mode on Switch Mode 0 0: EVEN Line

0

1: ODD Line

2006/5/5



BIT1611B


Vertical Start Value for EVEN Field on Switch Mode 1 Vertical Start Value for ODD Field 0x073[5:4], 0x072[7:0] RW 10 on Switch Mode 1 Vertical Shift Value on Switch 0x076[4], 0x074[7:0] RW 9 Mode 1 Vertical Fix Value on Switch Mode 0x076[6], 0x075[7:0] RW 9 1 Vertical Scaling Function Enable on Switch Mode 1 0x076[0] RW 1 0: Disable (Bypass Mode)

R_SCYE_START_M1

0x073[1:0], 0x071[7:0] RW 10

R_SCYO_START_M1 R_SCY_SHIFT_M1 R_SCY_FIX_M1

R_VSCALE_EN_M1

0x080 0x080 0x100 0x000

1

1: Enable (Scale Mode) Vertical Scaling Filter Enable on Switch Mode 1 R_VSCALE_FILTER_M1

0x076[2:1]

RW

2 11: Triangle Filter 10: Box Filter

11

0x: Filter Disable

R_CUT_AUTO_M1

0x076[3]

RW

1

Vertical Pre-Scaling Change Mode on Switch Mode 1 0: Manual (R_CUT_MODE)

0

1: Auto (EVEN/ODD)

R_LINE_CUT_M1

0x076[5]

RW

1

Vertical Pre-Scaling Down Enable on Switch Mode 1 0: Disable

0

1: Enable

R_CUT_MODE_M1

0x076[7]

RW

1

Vertical Pre-Scaling Down Mode on Switch Mode 1 0: EVEN Line

0

1: ODD Line

7-29 Timing Adjustment BIT1611B Timing adjustment principle: (1) “t1” of IVREF is smaller than but close to “t2” of OVREF. Follow the procedures in Figure 7-24 (2) The overflow/underflow error caused by Line Buffer should be corrected. Follow the procedures in Figure 7-25

Figure 7-23 2006/5/5

Timing Adjustment VREF Information



BIT1611B


Table 7-33

Timing Adjust Register

Mnemonic

2006/5/5

Address

R/W

bit

Description

Even Field Output VSYNC 10 synchronize Delay time on switch mode 0 Odd Field Output VSYNC 10 synchronize Delay time on switch mode 0 Even Field Output VSYNC 10 synchronize Delay time on switch mode 1 Odd Field Output VSYNC 10 synchronize Delay time on switch mode 1 Even Field Output VSYNC 10 synchronize Delay time on switch mode 0 Odd Field Output VSYNC 10 synchronize Delay time on switch mode 0 Even Field Output VSYNC 10 synchronize Delay time on switch mode 1 Odd Field Output VSYNC 10 synchronize Delay time on switch mode 1

Default

R_DLYE_OCLK_M0

0x019[5:4], 0x017[7:0] RW

R_DLYO_OCLK_M0

0x019[1:0], 0x018[7:0] RW

R_DLYE_OCLK_M1

0x01F[5:4], 0x01D[7:0] RW

R_DLYO_OCLK_M1

0x01F[1:0], 0x01E[7:0] RW

R_DLYE_IHS_M0

0x070[5:4], 0x06E[7:0] RW

R_DLYO_IHS_M0

0x070[1:0], 0x06F[7:0] RW

R_DLYE_IHS_M1

0x079[5:4], 0x077[7:0] RW

R_DLYO_IHS_M1

0x079[1:0], 0x078[7:0] RW

R_COUNT1

0x193[7:0], 0x192[7:0]

R

16 OVREF vs. IVREF Length

-

R_COUNT2

0x19D[7:0]

R

8 Line Buffer Error Value

-


0x332

0x332

0x118

0x118

0x010

0x010

0x12

0x12


BIT1611B

Beyond Innovation Technology Co., Ltd. Start

Read R_COUNT1

R_COUNT1 > 0x8000+R_DIS_YW

Yes

R_COUNT1 > 0x8000 No

Yes

VALA =

VALB

R _ COUNT1 − 0 x8000 VALA

R _ DIS _ YW

=

R _ OS _ XT

+ VALA

Finish

=

VALB

0 x8000 − R _ COUNT 1

=

R _ DIS _ YW

R _ OS _ XT

− VALA

Write R_OS_XT with VALB

Wait 2 fields

Figure 7-24

2006/5/5

R_OS_XT Adjust flow chart



BIT1611B

Beyond Innovation Technology Co., Ltd. Start

Enable Line Buffer Error check Interrupt

Read R_INT_ACK

Finish

ERROR2 = 1

VA LC

Write R_DLY_IHS with R_DLY_IHS +1

=

yes

ERROR1 = 1

no

yes

yes

Read R_COUNT2

Read R_COUNT2

R _ DLY _ OC LK +

R _ COUNT 2 VA LC

3

=

R _ D LY _ OC LK −

VALC > 1024

R _ COUNT 2

VALC < 0

no

3

yes

Write R_DLY_IHS with R_DLY_IHS -1

no

Write R_DLY_OCLK with VALC

Wait 2 fields

Clear Line Buffer Error check Interrupt

Figure 7-25

Timing Adjust flow

7-30 Brightness/Contrast Adjustment For RGB domain data, BIT1611B adjusts Brightness and Contrast in each color channel respectively. Table 7-34

Color Adjustment Register

Mnemonic

Address

R/W

bit

Description

Default

R_BRIGHTNESS_R

0x07C[7:0]

RW

8

R Channel Brightness Value

0x80

R_BRIGHTNESS_G

0x07D[7:0]

RW

8

G Channel Brightness Value

0x80

R_BRIGHTNESS_B

0x07E[7:0]

RW

8

B Channel Brightness Value

0x80

Brightness Type Select R_BRIGHTNESS_SEL 0x08A[5]

RW

1

0: By frame (value from register) 1: By line

R_CONTRAST_R 2006/5/5

0x07F[7:0]

RW

8

0

(value from Gamma RAM)

R Channel Contrast Value


0x80 page 53 of 109 DOC NO.W-DS-0004

BIT1611B

Beyond Innovation Technology Co., Ltd. R_CONTRAST_G

0x080[7:0]

RW

8

G Channel Contrast Value

0x80

R_CONTRAST_B

0x081[7:0]

RW

8

B Channel Contrast Value

0x80

Contrast Adjust Type R_CONTRAST_TYPE

0x08B[1]

RW

1

0

0: Type 1 1: Type 2

DATA_INPUT R

G

B

R_BRIGHTNESS

G

DATA_OUTPUT 0 M 1 R_BRIGHTNESS_SEL

BRIGHTNESS

CONTRAST

B GAMMA_LUT_RAM (R_GAMMA_LUT_MODE=1)

Figure 7-26

Gamma Table G

Brightness and Contrast

Line1 Brightness Line2 Brightness Line3 Brightness Line4 Brightness Line5 Brightness

Line256 Brightness Line257 Brightness

Gamma Table B

Line511 Brightness Line512 Brightness

Figure 7-27

2006/5/5

R_BRIGHTNESS_SEL=1 R_GAMMA_LUT_MODE=1

Gamma LUT Ram Setting



BIT1611B


7-31 Image Enhancement 7.31.1Black Level and Black/White expansio n This function is performed in Y domain. Table 7-35

Y Domain Process Register

Mnemonic

Address

R/W

bit

R_BLACK_LEVEL

0x082

RW

8

R_WHITE_SLOPE

0x083

RW

8

R_BLACK_SLOPE

0x084

RW

8

R_WHITE_START

0x085

RW

8

R_BLACK_START

0x086

RW

8

Description Black Level Value (0x00 = -128, 0x01 = -127, 0x7F = -1, 0x80 = 0, 0xFF = 127 White Slope Value (0.0 ~ 1.9922) (0x00=0.0000,0x80=1.0000,0xFF=1.9922) Black Slope Value (0.0 ~ 1.9922) (0x00=0.0000,0x80=1.0000,0xFF=1.9922) White Start Pointer (when Y >= 128) 0x00 = +0, 0x7F = +127; ( R_WHITE_START <= 0x7F) Black Start Pointer (when Y < 128) 0x00 = -0, 0x80 = -128; (R_BLACK_START <= 0x80)

+

YIN

bit7~bit0

Default 0x80

0x80 0x80

0x80

0x80

YOUT

+

R_BLACKLEVEL

MUX

-

bit7

Figure 7-28

2006/5/5

128

Black Level Adjustment



BIT1611B

Beyond Innovation Technology Co., Ltd. Bit7~bit0 -1

128

128 YIN

Bit7~bit0

-

x

-

mux

x

+

+

YOUT

mux

bit7

> R_BLACK_START mux R_WHITE_START

R_BLACK_SLOPE

/

mux R_WHITE_SLOPE

128

Figure 7-29

Black and White Adjustment

OUT 255

Slope = R_WHITE_SLOPE/128 128+R_WHITE_START

128-R_BLACK_START

Slope = R_BLACK_SLOPE/128

0

128+R_WHITE_START 128-R_BLACK_START

Figure 7-30

7.31.2

255

IN

Black and White Slope

Sharpness and Smoothn ess Process

BIT1611B provides 8 types of filter settings for Y domain data with 8 different image effects Table 7-36

Sharpness and Smoothness Process Register

Mnemonic R_IMG_FILTER_EN

Address 0x08B[7]

R/W Bits RW

Description

1 YUV Domain Image Enhance Enable

Default 0

0: disable 2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 1: enable

YUV Domain Image Enhance Filter Select 0x08B[6]

RW

1 0: Smoothness 1: Sharpness

R_IMG_FILTER 0x08B[5:4] RW

7.31.3

When R_IMG_FILTER[6] = 0; 00: Smoothness 1 Filter (low smoothness) 01: Smoothness 2 Filter 10: Smoothness 3 Filter 11: Smoothness 4 Filter (high smoothness) 2 When R_IMG_FILTER[6] = 1, 00: Sharpness 1 Filter (low sharpness) 01: Sharpness 2 Filter 10: Sharpness 3 Filter 11: Sharpness 4 Filter (high sharpness)

000

UV Domain Proces s

For UV-domain BIT1611B supports UV Gain, Skin Tone and Kill Color functions. color, as he likes. Please refer to Table 7-37. Table 7-37

User can tune the display

UV Domain Register

Mnemonic

Address

R/W

Bits

R_U_GAIN

0x087[6:0] RW

7

R_V_GAIN

0x088[6:0] RW

7

Description U Gain Value (0x00 = -128, 0x01 = -127, 0x7F = -1, 0x80 = 0, 0xFF = 127 V Gain Value (0x00 = -128, 0x01 = -127, 0x7F = -1, 0x80 = 0, 0xFF = 127

Default 0x40

0x40

HUE Enable R_HUE_EN

0x08B[0]

RW

1

0: disable

0

1: enable, Control Color enable R_KILL_COLOR

0x08B[2]

RW

1

0: disable

0

1: enable Hue COS Sign R_HUE_SATCOS

0x08E[7]

RW

1

0: positive 1: negative

0x08E[6:0] RW

7

0x00

Hue COS Value Hue SIN Sign

R_HUE_SATSIN

2006/5/5

0x08F[7]

RW

1

0: positive 1: negative

0x00

0x08F[6:0] RW

7

Hue SIN Value

R_HUE_U_MAX

0x090[7:0] RW

8

U Maximum Threshold

0xFF

R_HUE_U_MIN

0x091[7:0] RW

8

U Minimum Threshold

0x00

R_HUE_V_MAX

0x092[7:0] RW

8

V Maximum Threshold

0xFF

R_HUE_V_MIN

0x093[7:0] RW

8

V Minimum Threshold

0x00



BIT1611B


Chrom a Transient Impro vement (CTI)

Table 7-38

Chroma Transient Improvement Register

Mnemonic

Address

R/W Bits

Description

Default

CTI Enable R_CTI_EN

0x089[0]

RW

1 0: disable

0

1: enable R_CTI_BW

0x089[2:1] RW

2 CTI Bandwidth Select

00

R_CTI_COMP

0x089[4:3] RW

2 CTI Compare Select

00

R_CTI_GAIN

0x089[7:5] RW

3 CTI Gain Value

000

R_CTI_CORING

0x08A[3:0] RW

4 CTI Coring Value

0000

7-32 Gamma Correct ion BIT1611B has 2 kinds of Gamma Correction functions, Adjust-Curve and Look-Up-Table.

Image_input

RAM

1

R

M

1 M

Image_output

0

0

G B

GAMMA CURVE

GAMMA LUT

R_GAMMA_CURVE_EN

Figure 7-31

7.32.1

R_GAMMA_LUT_EN

Gamma Correction

Adjust-Curve

There are 6 segments in the curve. User can decide each curve slope and start offset of the curve, refer to Figure 7-32 and Table 7-39. There is only one curve for all R, G, B colors.

2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. Output Signal SLOPE1

SLOPE2

SLOPE3

SLOPE4

SLOPE5

SLOPE6

SLOPE7

(Example Case) Adjust-Curve Default Gamma Curve

SLOPE : 0~1.968 RANGE : 0~255 DI_OFFSET: 0~255

DI_OFFSET

0

RANGE1

RANGE2

RANGE3

Figure 7-32

Table 7-39

RANGE4

RANGE5

RANGE6

255

Input Signal

Example of Adjust-Curve

Adjust-Curve Register

Mnemonic

Address

R/W

bit

Description

Default

GAMMA Curve Enable R_GAMMA_CURVE_EN

0x0A2[1]

RW

1 0: Disable

0

1: Enable R_RANGE1

0x094[7:0]

RW

8 The Range1 End Position

0x24

R_RANGE2

0x095[7:0]

RW


0x48

R_RANGE3

0x096[7:0]

RW


0x6C

R_RANGE4

0x097[7:0]

RW


0x90

R_RANGE5

0x098[7:0]

RW


0xB4

R_RANGE6

0x099[7:0]

RW


0xD8

R_SLOPE1

0x09A[5:0]

RW

6 The Slope of Range1

0x20

R_SLOPE2

0x09B[5:0]

RW


0x20

R_SLOPE3

0x09C[5:0]

RW


0x20

R_SLOPE4

0x09D[5:0]

RW


0x20

R_SLOPE5

0x09E[5:0]

RW


0x20

R_SLOPE6

0x09F[5:0]

RW


0x20

R_SLOPE7

0x0A0[5:0]

RW


0x20

R_DI_OFFSET

0x0A1[7:0]

RW

8 The RGB Output Data Offset

0x00

7.32.2

Look-Up-Tabl e (LUT) Embedded memory of the size 768 x 8-bit in BIT1611B, it is the LUT gamma RAM.

Table 7-40

2006/5/5

LUT Gamma Memory Address

Register Address

Description

0x200H~0x2FFH

Red Color LUT GAMMA

0x300H~0x3FFH

Green Color LUT GAMMA

0x400H~0x4FFH

Blue Color LUT GAMMA



BIT1611B

Beyond Innovation Technology Co., Ltd. Table 7-41

LUT Gamma Register

Mnemonic

Address

R/W Bits

Description

Default

GAMMA LUT Enable R_GAMMA_LUT_EN

0x0A2[0]

RW

1

0

0: Disable 1: Enable GAMMA LUT RAM Mapping Mode

0: RGB Input Mapping to RGB Gamma 0 RAM 1: RGB Input Mapping to R Gamma RAM Note: Must disable GAMMA function when access GAMMA RAM.

R_GAMMA_LUT_MODE

0x0A2[2]

RW

1

7-33 Dither Embedded User-Programmable Dithering Function makes 18-bit (RGB) panel the better display q uality. Table 7-42

Dither Register

Mnemonic

Address

R/W

bit

Description

Default

Dither Function Enable R_DITHER_EN

0x08B[3]

RW

1 0: Disable

0

1: Enable R_DITHER_EVEN

0x08C[7:0]

RW

1 EVEN Field Dither Factor

0x87

R_DITHER_ODD

0x08D[7:0]

RW

1 ODD Field Dither Factor

0x78

7-34 Color Space Conversion BIT1611B provides 2 kinds of Color Space Conversions that convert YUV Color Domain to RGB Color Domain. Table 7-43

Color Space Converter Register

Mnemonic

Address

R/W

bit

Description

Default

Color Space Conversion R_Y2R_SEL

0x08A[4]

RW

1 0: No Gamma-Correction

0

1: Gamma-Correction

7-35 PLL and OSC Pads BIT1611B provides a built-in phase lock loop (PLL) clock generator. According to the oscillator of frequency generating and the setting of registers, the generator may generate user defined clock output. The related registers and equation are described in Table 7-11 Note : BIT1611B uses the oscillator of 24.576MHz.

Table 7-44 Mnemonic

PLL Register Address

R/W bit

Description

Default

PLL base clock select R_PLL_SRC

0x00B[7]

RW

1 0: from Oscillator

0

1: from PCLK R_PLL_VND 2006/5/5

0x0A4[7:0]

RW

8 PLL N Value.


0x88 page 60 of 109 DOC NO.W-DS-0004

BIT1611B

Beyond Innovation Technology Co., Ltd. R_PLL_VMD

0x0A6[2:0],0x0A5[7:0]

RW 11 PLL M Value

0x256

R_PLL_VMTDIV

0x0A6[3]

RW

1 Output clock test enable (setting to 0 )

R_PLL_VPD

0x0A6[6:4]

RW

3 PLL D Value

R_PLL_HALFCK

0x0A6[7]

RW

1 Half Clock output

0

R_PLL_LEN

0x0A7[0]

RW

1 Lock enable

0

R_PLL_VPRST

0x0A7[1]

RW

1 VCO Reset

1

R_PLL_VPLPFS

0x0A7[2]

RW

1 PLL Lpf select

0

0 010

VCO frequency range selection. R_PLL_VFSEL

0x0A7[3]

RW

1 0: Low Range

0

1: High Range R_PLL_R

0x0A7[5:4]

RW

2 REF skew control

00

R_PLL_S

0x0A7[7:6]

RW

2 SEL skew control

00

PLL _ OUT

=

R _ PLL _ VMD R _ PLL _ VND

×

2

−

( R _ PLL _ VPD )

×

OSC _ Freq _ Sel

-- Frequency formula –

7-36 Timer There are 2 independent 8-bit counters in BIT1611B, refer to Table 7-45. Table 7-45

Timer Register

Mnemonic R_TIMER0_COUNT_VAL

Address 0x0BA[7:0]

R/W bit RW

Description

8 Timer0 Count Value.

Default 0x00

Timer0 Enable: R_TIMER0_EN

0x0BB[2]

RW

1 0: Disable.

0

1: Enable. Timer0 Count Mode: R_TIMER_MODE

0x0BB[3]

RW

1 0: One-Shot.

0

1: Circular. Timer0 Count Base: 00: Reserve. R_TIMER0_BASE_MODE

0x0BB[1:0]

RW

2 01: H Sync.

00

10: V Sync. 11: Unused. R_TIMER1_COUNT_VAL

0x0BC[7:0]

RW

8 Timer1 Count Value.

0x00

Timer1 Enable: R_TIMER1_EN

0x0BD[2]

RW

1 0: Disable.

0

1: Enable. Timer1 Count Base: 00: Reserve. R_TIMER1_BASE_MODE

0x0BD[1:0]

RW

2 01: H Sync.

00

10: V Sync. 11: Unused.

2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. XCLK TIMER0_OUT COUNTER0

0

1

2

3

4

5

0

R_TIMER0_EN R_TIMER0_MODE R_TIMER0_BASE_MODE[1:0]

0

R_TIMER0_VAL[7:0]

5

(a) Mode 0 (One-Shot)

XCLK TIMER0_OUT COUNTER0

0

1

2

3

4

5

0

1

2

3

4

5

0

R_TIMER0_EN R_TIMER0_MODE R_TIMER0_BASE_MODE[1:0]

0

R_TIMER0_VAL[7:0]

5

(b) Mode 1 (Circulate)

7-37 GPI and K EY Functi on BIT1611B provides 8 sets of GPI(General Purpose Input). Each set can be arranged as Level, Key Down and Key Up status. The status can be checked by Interrupt(0x002[7]) or read the registers as below: Table 7-46 Mnemonic

GPI and KEY Register Address

R/W

bit

Description

Default

GPI[7:5] Input Pin Select [0]: GPI[5] 0: From BIN5 1: From OPTIONS2 R_KEY_SEL

0x0C0[2:0]

RW

3

[1]: GPI[6] 0: From BIN6

000

1: From OPTIONS3 [2]: GPI[7] 0: From BIN7 1: From OPTION4 R_KEY_DB

0x0C0[4:3]

RW

2

GPI De-Bounce Setup

11

R_KEY_ACK

0x0C1[7:0]

R

8

GPI read back Status

-

R_KEY_STATUS

0x0C2[7:0]

R

8

Real Time GPI Status

-

GPI Polarity R_KEY_POL

0x0C3[7:0]

RW

8

0: Normal

0x00

1: Invert

2006/5/5

R_KEY0_TYPE

0x0C4[1:0]

RW

2

GPI[0] Type Setup

11

R_KEY1_TYPE

0x0C4[3:2]

RW

2

GPI[1] Type Setup

11

R_KEY2_TYPE

0x0C4[5:4]

RW

2

GPI[2] Type Setup

11



BIT1611B

Beyond Innovation Technology Co., Ltd. R_KEY3_TYPE

0x0C4[7:6]

RW

2

GPI[3] Type Setup

11

R_KEY4_TYPE

0x0C5[1:0]

RW

2

GPI[4] Type Setup

11

R_KEY5_TYPE

0x0C5[3:2]

RW

2

GPI[5] Type Setup

11

R_KEY6_TYPE

0x0C5[5:4]

RW

2

GPI[6] Type Setup

11

GPI[7] Type Setup 00: Key-Down R_KEY7_TYPE

0x0C5[7:6]

RW

2

01: Key-Up

11

10: Level Change 11: Disable

7-38 Auto Detection BIT1611B provides 6 kinds o f input signal detections: PCLK based SYNC detection, XCLK based SYNC detection, Mode Change detection, Mode Type detection, Even/Odd type detection and No signal detection. (1) PCLK based SYNC detection: Using PCLK to detect the “External HSYNC”, ”External VSYNC Low Pulse Width” and “Total SYNC Width”. Its main function is to detect the polarity and the operation mode of the “SYNC” signal. This detection operation is started automatically when power is on. It cannot be stared or stopped by MCU. The operation is as bellow: To read the data of SYNC : Register (0x18D[7:0]): HSYNC Low pulse (in PCLK)。 Register (0x191[6:4], 0x18E[7:0]): HSYNC Total width (in PCLK)。 Register (0x18F[6:0]): VSYNC Low pulse (in HSYNC)。 Register (0x191[1:0], 0x190[7:0]): VSYNC Total width (in HSYNC)。 (2) XCLK based SYNC detection Using XCLK to detect the “External HSYNC”. Its main function is to detect the operation mode. It will count the input HSYNC low level width and HSYNC high level width based on XCLK. The operation is as below: To read the data of SYNC Register (0x198[5:0],0x197[7:0]): HSYNC High Level Width (in XCLK) Register (0x19A[5:0],0x199[7:0]: HSYNC Low Level Width ( in XCLK) (3) Mode Change Detection: To detect the variation of “VSYNC”, if the variation is larger than the value that is set in the register, then MCU will be interrupted. The detail operation is as bellow: a. Set R_MODECHG_MRG (0x0CB[3:0]): the maximum variation of VSYNC. b. Set Interrupt Enable (Register: 0x004[2]). c. If the variation of VSYNC larger then the value that is set in above register, the MCU is interrupted through INT pin, or by polling the Interrupt Flag Register(0x002[2]) . (4) Mode Type Detection: NTSC and PAL modes can be detected automatically and store in Register(0x18C[0]). (5) Even/Odd Type Detection: The Even/Odd change of VSNC can be detected automatically and store the status in Register(0x18C[1]) (6)No signal Detection: BIT1611B senses any toggle happened for Hsync. If there is no any toggle within 2047 XCLKs then a interrupt(0x02[1:0]) is responded. Reading the Register (0x18C[2]) will get the status.

2006/5/5



BIT1611B


Table 7-47

Auto Detection Register

Mnemonic

Address

R_MODECHG_MRG 0x0CB[3:0]

R/W

bit

RW

4

Description

Default

VSYNC maximum variation

0xC

Mode Status  0: 50Hz  1: 60Hz EVEN Type status  0: had EVEN/ODD information  1: no EVEN/ODD information Sync Status 0: Signal Ready 1:No Signal EVEN/ODD Information  0: EVEN Field  1: ODD Field

R_MODE_TYPE

0x18C[0]

R

1

-

R_EVENSAME

0x18C[1]

R

1

R_SYNC_DET

0x18C[2]

R

1

R_IEVEN

0x18C[3]

R

1

R_IS_XP

0x18D[7:0]

R

8

HSYNC Low pulse (in PCLK)

-

R_IS_XT

0x191[6:4], 0x18E[7:0]

R

11 HSYNC Total width (in PCLK)

-

R_IS_YP

0x18F[6:0]

R

7

VSYNC Low pulse (in HSYNC)

-

R_IS_YT

0x191[1:0], 0x190[7:0]

R

10 VSYNC Total width (in HSYNC)

-

-

-

-

7-39 EEPROM Setup BIT1611B provides Script Mode that IC is programmed by EEPROM directly. can be adjusted.

Table 7-48

The read/write speed of EEPROM

EEPROM Read/Write Speed Register

Mnemonic

Address

R/W bit

Description

Default

R_SERIAL_CKEN_SEL 0x0CC[2:0] RW

EEPROM Read/Write Speed 3 0x7: Slowest 0x0: Fastest

111

R_I2C_SLAVE

7 Script Control I2C Command Slave Setup

0x00

0x0CD[6:0] RW

7-40 Serial Peri pher al Interface (SPI) BIT1611B provides especially in Master mode the three-wire Serial Peripheral Interface function.

Table 7-49

SPI Register

Mnemonic

Address

R/W bit

Description

Default

SPI Enable: R_SPI_EN

0x0CC[3]

RW

1 0: Disable (GPI).

0

1: Enable (SPI). R_SPI_SPEED

0x0CC[5:4]

RW

2 SPI Speed Select:

11

00: 81.4ns. 2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 01: 162.8ns. 10: 325.6ns. 11: 651.2ns. SPI Mode Select: 00: 12bit R_SPI_MODE

0x0CC[7:6]

RW

2 01: 14bit.

10

10: 16bit. 11: 24bit.

SPI_CS SPI_SCL SPI_SDA

D11

D10

D9

D8

R_SPI_MODE

0

R_SPI_SPEED

0

Figure 7-33

2006/5/5

D7

D6

D5

D4

D3

D2

D1

D0

SPI Protocol



BIT1611B


7-41 Power Sequence Control BIT1611B performs Power Sequence Control.

Table 7-50 Mnemonic

Power Sequence Control Register Address

R/W bit

Description

Default

R_P1_HSYNC

0x0D5[0],0x0CF[7:0]

RW 10 Phase 1 Delay with HSYNC

0x000

R_P2_HSYNC

0x0D5[1],0x0D0[7:0]


0x000

R_P3_HSYNC

0x0D5[2],0x0D1[7:0]


0x000

R_P4_HSYNC

0x0D5[3],0x0D2[7:0]


0x000

R_P5_HSYNC

0x0D5[4],0x0D3[7:0]


0x000

R_P6_HSYNC

0x0D5[5],0x0D4[7:0]


0x000

R_P1_VSYNC

0x0D6[3:0]

RW

8 Phase 1 Delay with VSYNC

0x00

R_P2_VSYNC

0x0D6[7:4]

RW


0x00

R_P3_VSYNC

0x0D7[3:0]

RW


0x00

R_P4_VSYNC

0x0D7[7:4]

RW


0x00

R_P5_VSYNC

0x0D8[3:0]

RW


0x00

R_P6_VSYNC

0x0D8[7:4]

RW


0x00

Data Output Control enable R_DATA_CTRL

0x0D5[6]

RW

1 0: Disable

0

1: Enable Power Sequence Function enable R_POWER_EN

0x0D5[7]

RW

1 0: Disable

0

1: Enable R_POL_P1

0x0D9[0]

RW

1 Phase 1 Polarity

0

R_POL_P2

0x0D9[1]

RW

1 Phase 2 Polarity

0

R_POL_P3

0x0D9[2]

RW

1 Phase 3 Polarity

0

R_POL_P4

0x0D9[3]

RW

1 Phase 4 Polarity

0

R_POL_P5

0x0DB[3]

RW

1 Phase 5 Polarity

0

Phase 6 Polarity R_POL_P6

0x0DB[7]

RW

1 0: Normal (High Active)

0

1: Invert (Low Active) R_DATA_UP

0x0D9[6:4]

RW

3 Data Control Phase Select

000

Power Sequence Output Control R_POWER_SEL

0x0DA[5:0]

RW

6 0: Disable

0

1: Enable R_POWER_P5

0x0DB[2:0]

RW

3 Power Phase 5 Output Select

000

Power Phase 6 Output Select 000: Phase 1 001: Phase 2 R_POWER_P6

0x0DB[6:4]

RW

3 010: Phase 3

000

011: Phase 4 100: Phase 5 101~111: Phase 6

2006/5/5



BIT1611B


R_POWER_EN

R_P1_VSYNC+R_P1_HSYNC

POWER_P1

R_P2_VSYNC+R_P2_HSYNC R_P1_VSYNC+R_P1_HSYNC

POWER_P2


POWER_P3


POWER_P4


POWER_P5


POWER_P6 R_P6_VSYNC+R_P6_HSYNC

Figure 7-34

Power Sequence Function

7-42 PWM Function BIT1611B provides 2 independent general-purpose PWM outputs, used for controlling backlight and audio or others.

Table 7-51 Mnemonic

PWM Function Register Address

R/W

bit

Description

Default

R_SYNC_DELAY

0x0E1[6], 0x0DE[7:0]

RW

9 Synchronize delay time

0x000

R_PWM1_REF

0x0E1[1:0], 0x0DF[7:0]

RW

10 PWM1 Reference Cycles.

0x000

R_PWM1_FREQ

0x0E1[4], 0x0E0[7:0]

RW

9 PWM1 Output Cycles.

0x000

R_PWM1_DUTY

0x0E3[0], 0x0E2[7:0]

RW

9 PWM1 Output Duty Cycle

0x000

PWM1 synchronized with VSYNC R_PWM1_SYNC

0x0EA[0]

RW

1 0: Disable

0

1: Enable PWM1 Output Polarity R_PWM1_POL

0x0EA[1]

RW

1 0: Normal

0

1: Invert PWM1 Output Select R_PWM1_SEL

0x0EA[2]

RW

1 0: PWM1 Output

00

1: PWM3 Output PWM1 synchronized with HSYNC R_SYNC_OHS

0x0EA[3]

RW

1 0: Disable

0

1: Enable R_PWM2_REF

0x0E7[1:0], 0x0E4[7:0]

RW

10 PWM2 Reference Cycles.

0x000

R_PWM2_FREQ

0x0E7[4], 0x0E5[7:0]

RW

9 PWM2 Output Cycles.

0x000

R_PWM_SYNC_DELAY 0x0E7[5], 0x0E6[7:0]

RW

9 PWM2 落後 PWM1 角度

0x000

R_PWM2_DUTY

0x0E9[0], 0x0E8[7:0]

RW


0x000

R_PWM2_SYNC

0x0EA[4]

RW

1 PWM2 synchronized with VSYNC

0

0: Disable 2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 1: Enable PWM2 Output Polarity R_PWM2_POL

0x0EA[5]

RW

1 0: Normal

0

1: Invert PWM2 落後 PWM1 R_PWM_SYNC_EN

0x0EA[6]

RW

1 0: Disable

0

1: Enable PWM2 Output Select R_PWM2_SEL

0x0EA[7]

RW

1 0: PWM2 Output

0

1: PWM4 Output

Panel clock R_PWM_REF

Reference clock Base on panel clock R_PWM_FREQ

PWM Output Base on reference clock R_PWM_DUTY

R_PWM_SYNC_EN == 1 PWM1/PWM2 Setup the same

PWM1 Output PWM2 Output R_PWM_SYNC_EN == 0 PWM1/PWM2 Setup the same

PWM1 Output PWM2 Output Figure 7-35

2006/5/5

PWM function



BIT1611B


7-43 Feedback PWM Control BIT1611B supports 2 sets of PWM output signals. The duties of both PWM signals are adjustable through the feed back loop, which is suitable for DC-DC control circuit.

Table 7-52

Feedback PWM Function Register

Mnemonic

Address

R/W

bit

Description

Default

R_PWM3_FREQ

0x0EB[7:0]

RW

8 PWM3 Output Cycles

0x00

R_PWM3_DUTY

0x0EC[7:0]

RW


0x00

PWM3 Output Polarity R_PWM3_POL

0x0F1[0]

RW

1 0: Normal

0

1: Invert PWM3 Feedback Enable R_PWM3_FB

0x0F1[1]

RW

1 0: Disable

0

1: Enable PWM3 Synchronization Source R_PWM3_SEL

0x0F1[2]

RW

1 0: Input VSYNC

0

1: Output VSYNC PWM3 Mode R_PWM3_SYNC

0x0F1[3]

RW

1 0: Free run Mode

0

1: Synchronization Mode R_PWM4_FREQ

0x0ED[7:0]

RW

8 PWM4 Output Cycles

0x00

R_PWM4_DUTY

0x0EE[7:0]

RW


0x00

PWM4 Output Polarity R_PWM4_POL

0x0F1[4]

RW

1 0: Normal

0

1: Invert PWM4 Feedback Enable R_PWM4_FB

0x0F1[5]

RW

1 0: Disable

0

1: Enable PWM4 Synchronization Source R_PWM4_SEL

0x0F1[6]

RW

1 0: Input VSYNC

0

1: Output VSYNC PWM4 Mode R_PWM4_SYNC

0x0F1[7]

RW

1 0: Free run Mode

0

1: Synchronization Mode

2006/5/5

R_FB_LOW

0x0EF[7:0]

RW

8 Feedback tracer Low limit

0x00

R_FB_HIGH

0x0F0[7:0]

RW

8 Feedback tracer High limit

0x00

R_POWER_DB

0x0C0[7:5]

RW

3 Feedback De-Bounce Setup


111


BIT1611B


7-44 IR Decoder Function BIT1611B supports IR Decoder function in NEC format. It can detect the NEC IR format and then feedback to MCU through interrupt pin.

Table 7-53 Mnemonic

R_IR_CODE

R_IR_CC

IR PWM Pulse Detect Register Address

R/W

bit

0x0F5[7:0]

R

8

NEC IR /Data

-

0x0F6[7:0]

R

8

NEC IR /Code

-

0x0F7[7:0]

R

8

NEC IR Data

-

0x0F8[7:0]

R

8

NEC IR Code

-

8

User Defined Customer /Code

0x00

8

User Defined Customer Code

0x00

0x0F9[7:0] 0x0FA[7:0]

RW

Description

Default

NEC IR Decoder Enable R_IR_EN

0x0FB[0]

RW

1

0: Disable

0

1: Enable NEC IR Polarity R_POL_IR

0x0FB[1]

RW

1

0: Normal

1

1: Invert NEC IR Clock Base 000: XCLK 001: XCLK/2 010: XCLK/3 R_IR_BASE

0x0FB[4:2]

RW

3

011: XCLK/4

000

100: XCLK/5 101: XCLK/6 110: XCLK/7 111: XCLK/8 NEC Interrupt Conditions [5]: Check IR Code = ~IR /Code R_IR_CHECK

0x0FB[7:5]

RW

3

[6]: Check IR Data = ~IR /Data

000

[7]: Check IR Code = User Defined Customer Code and IR /Code = User Defined Customer /Code Repeat Code Detection Enable R_IR_DISREPT 0x0FC[0]

RW

1

0: Enable Repeat Code

0

1: Disable Repeat Code R_IR_DB

0x0FC[2:1]

RW

2

IR De-Bounce Setup

10

IR Code Type R_IR_TYPE

0x0FC[4]

R

1

0: First Code

-

1: Repeat Code

2006/5/5



BIT1611B


7-45 Video Decod er BIT1611B provides the Video Decoder for decoding the TV signals. Video Decoder features: 1) Four analog inputs, internal analog source selector, e.g. 4 x CVBS or 2 x Y/C ( or 1xY/C and 2 x CVBS) 2) Fully programmable static gain for main channels or automatic gain control for the selected CVBS or Y/C channel 3) Two 8-bit video analog to digital converters 4) Line-locked system clock frequencies 5) Automatic detection of 50 and 60 Hz field frequency 6) Luminance and chrominance signal processing for PAL, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43 and NTSC-JAPAN

7.45.1A rchit ectures

Synchronization Process

AIN11 AIN12 AIN21 AIN22

Video Mux

ADC

Video Mux

ADC

Figure 7-36

Y

2D Comb Filter & Path C select

Hsync Vsync

LumaProcess

YOUT

Chroma Process

UOUT VOUT

Video Decoder Architectures

7.45.2 Analo g Input Path BIT1611B Video Decoder provides two 8 bits ADC and 4 analog inputs for user defined applications. detail of the path is shown as below.

2006/5/5


The


BIT1611B


R_SEL1(0x102[3]) AIN11 AIN12

AIN21 AIN22

R_ANY_SEL(0x102[1]) 0

1 0

MUX

ADC1

1 0

MUX

ADC2

Figure 7-37

Mnemonic

0

0

1 MUX

1 MUX

Chroma

R_ANC_SEL(0x102[0])R_YC_EN(0x103[3])

R_SEL2(0x102[6])

Table 7-54

Luma

1 MUX

Video Decoder Analog Input Path

Analog Input Path Register Address

R/W bit

Description

Default

Chroma Path Select R_ANC_SEL

0x102[0]

RW

1 0: ADC 2

0

1: ADC 1 Luma Path Select R_ANY_SEL

0x102[1]

RW

1 0: ADC 1

0

1: ADC 2 ADC 1 Enable R_ADC1_EN

0x102[2]

RW

1 0: Disable

0

1: Enable Analog MUX Select for ADC1 R_SEL1

0x102[3]

RW

1 0: AIN12 Pin (4)

0

1: AIN11 Pin (2) ADC 2 Enable R_ADC2_EN

0x102[5]

RW

1 0: Disable

0

1: Enable Analog MUX Select for ADC2 R_SEL2

0x102[6]

RW

1 0: AIN22 Pin (13)

0

1: AIN21 Pin(11) Y/C Mode Enable R_YC_EN

0x103[3]

RW

1 0: Disable (CVBS Mode) 1: Enable (S-Video Mode)

7.45.3 Color Standard Settin g and detect BIT1611B provides AUTO, Semi-AUTO and MANUAL modes for detecting color standards including PAL、 PAL60、PAL-N、SECAM、PAL-M、NTSC-443-60、NTSC-M、NTSC-443-60and Black&White. 2006/5/5



BIT1611B


Color Standard register

Mnemonic R_STD_SEL1

Address

R/W

bit

0x104[2:0]

RW

3

Description

Default

Color Standard Setup for Manual Setting and Semi-Auto on 50Hz Color Standard Setup for Semi-Auto on 60Hz

000

000: PAL/PAL-60 001: PAL_N 010: SECAM R_STD_SEL2

0x10D[6:4]

RW

3

101

011: PAL_M 100: NTSC_4.43_50Hz 101: NTSC_M / NTSC_J 110: NTSC_4.43_60Hz 111: Black & White Color Standard Detect

R_STD_AUTO

0x104[3]

RW

1

0: Manual Color Standard (Defined on 0x104[2:0])

0

1: Auto Color Standard Manual 50/60Hz select R_FSEL

0x104[4]

RW

1

0

0: 50Hz 1: 60Hz Auto 50/60Hz detect

R_AUFD

0x104[5]

RW

1

0: Manual 50/60Hz (Defined on 0x104[4])

1

1: Auto 50/60Hz detect Auto Color Standard Detect Mode Select R_STD_MOD

0x10D[7]

RW

1

1

0: Mode 0 1: Mode 1

R_STD_COUNT

0x117[5:0]

RW

6

Color Standard Detect Ready Threshold

0x38

7.45.4 Lum inanc e Process The luminance process of BIT1611B is shown be low.

YIN

Pre Filter ) N ] E 2 [ _ 3 F 0 E 1 x R 0 P ( _ R

Chrom a Trap

BandPass Filter

) L ) ] L ] ] N ) 1 [ E 0 E 0 [ E : S 3 _ 3 S 2 _ 0 _ [ T 0 T 1 S 5 H 1 x H x S 0 1 C 0 0 ( A x _ ( C _ R R P 0 B ( _ R

L ) ] E 3 : S [ _ 4 R 5 0 O 1 x C 0 _ ( R

L ) ] E 5 : S 6 _ [ R 5 E 0 1 P x A 0 _ ( R

Blackleve l L ) ] E 0 : V 7 E [ L 8 K 0 1 C x A 0 L ( B _ P V D _ R

Figure 7-38 2006/5/5

Contra st T ) ] S 0 : A [ 7 R 7 T 0 N 1 x O 0 C ( _ P V D _ R

Brightnes s ] S ) S 0 : E 7 [ N 6 T 0 H 1 x G I 0 ( R B _ P V D _ R

Path Dela y

YOUT

L ) ] E 0 : D 3 Y [ _ D R 0 1 x 0 (

Luminance Process



BIT1611B


Table 7-56

Luminance Process Register

Mnemonic

Address

R/W bit

Description

Default

Chroma Trap Enable R_CHT_EN

0x103[0]

RW

1 0: Disable

1

1: Enable Chroma-Trap Control (Internal Test) R_CHT_SEL

0x103[1]

RW

1 0: Type 1

0

1: Type 2 Luma Pre-Filter Enable R_PREF_EN

0x103[2]

RW

1 0: Disable

1

1: Enable R_BPASS_SEL

0x105[2:0]

RW

3 Band Pass Frequency Select

00

Coring circuit amplitude value 00: Coring factor 1 R_COR_SEL

0x105[4:3]

RW

2 01: Coring factor 2

00

10: Coring factor 3 11: Coring factor 4 Aperture Factor 00: 0 R_APER_SEL

0x105[6:5]

RW

2 01: 0.25

00

10: 0.5 11: 1.0 R_DVP_BRIGHTNESS

0x106[7:0]

RW

R_DVP_CONTRAST

0x107[7:0]

RW

R_DVP_BLACKLEVEL

0x108[7:0]

RW

Brightness Adjustment (0x00= 0) (2’s complement) (Range: +127~-128) Contrast Adjustment 0x80=1 8 (Range: 0~1.9999) 8

8 Black level Adjustment

0x20 0x84 0x10

Y Data Path Delay R_YDEL

0x10D[3:0] RW

4

1111: Delay 16 Clocks 1000: Delay 0 Clock

0x7

0000: Delay -15 Clocks

2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 7.45.5 Chrom a Proc ess

SECAM Processing

CIN

AntiFilter

Demodulator

LowPass Filter

ChromaGain Processing

SubCarrier Generator

Color Standard Detector Figure 7-39

Table 7-57

Re-Comb Filter

UOUT VOUT

Color Standard

Chroma Process Function Block

Chroma Process Register

Mnemonic R_DVP_SATURATION

Address

R/W

bit

0x109[6:0]

RW

7

Description Saturation Value

Default 0x40

Chrominance HUE control R_CHROMA_HUE

0x10A[7:0]

RW

8

01111111: +178.6° 0000000: 0°

0x00

1000000: -180° R_DVP_UGAIN

0x10B[7:0]

RW

8

U Gain Value Adjustment

0x00

R_DVP_VGAIN

0x10C[7:0]

RW

8

V Gain Value Adjustment

0x00

Chroma Fixed-Gain Value R_CHROMA_GAIN

0x10E[6:0]

RW

7

000000: Minimum gain (0.25) 010000: Normal gain (1.0)

0x24

111111: Maximum gain (3.5) Chroma Gain Type Select R_CHROMA_GAIN_SEL

0x10E[7]

RW

1

0: Auto-Gain

0

1: Fixed-Gain (Defined on 0x609[6:0]) R_GAIN_CTL_VALUE

0x110[0], 0x10F[7:0]

RW

9

Chroma Gain Reference value

0x100

Auto color kill from color detect R_AUTO_KILL

0x110[1]

RW

1

0: Disable

1

1: Enable (Auto Kill from color detect) TV / VCR Mode Select R_CDV_SEL

0x110[2]

RW

1

0: Mode 1

0

1: Mode 2 CCIR Mode R_CCIR_EN

0x110[3]

RW

1

0: Disable

0

1: Enable R_GAIN_CTL_SPEED

0x110[5:4]

RW

2 Auto Chroma Gain Loop Filter

10

00: Slow time constant 2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 01: Medium time constant 10: Fast time constant 11: Frozen SECAM Invert Enable R_SECAM_INV

0x110[6]

RW

1

0: Disable

0

1: Enable SECAM Cross Color Reduction R_SXCR

0x110[7]

RW

1

0: Disable

0

1: Enable R_THRESHOLD_SECAM

0x111[7:0]

RW

8

Color Killer Threshold for SECAM

0x1F

R_THRESHOLD_QAM

0x112[7:0]

RW

8

Color Killer Threshold for PAL and NTSC

0x50

R_SECAM_SENSITIVE

0x113[7:0]

RW

8

SECAM switch sensitive level

0x80

R_PAL_SENSITIVE

0x114[7:0]

RW

8

PAL switch sensitive level

0x80

R_LOWER_BOUND

0x115[3:0]

RW

4

Color Standard Detect Threshold 1

0x4

R_UPPER_BOUND

0x115[7:4]

RW

4

Color Standard Detect Threshold 2

0xC

R_CHROMA_LPPI1

0x116[1:0]

RW

2

Chroma Low Pass Filter Factor 1

01

R_CHROMA_LPPI2

0x116[3:2]

RW

2

Chroma Low Pass Filter Factor 2

10

SECAM freq. synchronize R_SECS_SEL

0x116[4]

RW

1

0: Disable

0

1: Enable R_SQP_LPPI

0x116[6:5]

RW

2

Sub-Carrier Phase Detect factor 1

01

R_SQP_SPUP

0x116[7]

RW

1


1

Chroma Phase Detect Mode R_CHROMA_PHASE

0x117[6]

RW

1

0: Mode 1

1

1: Mode 2 Sub-Carrier Lock Type R_COMPENSATE_SEL

0x117[7]

RW

1

0: Phase Adjustment

1

1: Frequency Adjustment R_SQP_LMT

2006/5/5

0x135[6]

RW

1



0


BIT1611B

Beyond Innovation Technology Co., Ltd. 7.45.6 Synchron ization Process

LUMA

SYNC SILCER

Vertical Processor Figure 7-40

Table 7-58

Reference Clock Generator

PHASE DETECTOR

Reference Clock

HSYNC

COUNTER

VSYNC

Synchronization Process

Synchronization process Register

Mnemonic

Address

R/W bit

Description

Default

R_SYNC_IDEL

0x118[7:0]

RW

8 Horizontal increment delay

0x4A

R_SYNC_HSYS

0x119[7:0]

RW

8 Horizontal Sync Start

0x2F

R_SYNC_HSYE

0x11A[7:0]

RW

8 Horizontal Sync End

0xFF

R_SYNC_HCS

0x11B[7:0]

RW

8 Clamp Signal Start

0xF2

R_SYNC_HCE

0x11C[7:0]

RW

8 Clamp Signal End

0xC0

R_SYNC_HSS

0x11D[7:0]

RW

8 Horizontal Delay

0xFD

R_BGPU_POINT

0x11E[7:0]

RW

8 Burst Start point

0x06

R_AGC_MASK_S

0x121[5:4],0x11F[7:0]

RW 10 AGC Mask Start Point

0x16

R_AGC_MASK_E

0x121[1:0],0x120[7:0]

RW 10 AGC Mask End Point

0x1FE

R_HLCK_THD

0x122[7:0]

RW

7 H-Lock Detect Threshold

0xFF

R_SLICER_THD

0x123[7:0]

RW

7 Sync-Slicer Threshold

0x00

Vsync Detection Mode 00: Mode1 R_VNOISE_MODE

0x124[1:0]

RW

2 01: Mode2

01

10: Mode3 11: Bypass Mode R_FIDT_THD

0x124[7:4]

RW

4 50/60Hz Detect Threshold

0x8

R _SYNC_LPADJ

0x125[1:0]

RW

2 Low Pass Filter Margin Value

11

R_SYNC_PDGAIN

0x125[3:2]

RW

2 Phase Detection Margin Value

11

R_SYNC_LPLMT

0x125[4]

RW

1 Low pass filter trace value

0

HPLL Mode Enable R_SYNC_HPLL

0x125[5]

RW

1 0: Disable

0

1: Enable VCR Mode Enable R_VTRC

0x125[7]

RW

1 0: Disable

0

1: Enable

2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 7.45.7 AFE Arc hit ectur es

R_SAD10 (0x136[0])

0 AIN11 AIN12

1 0 MUX

CLAMP

1

PGA

MUX

AIN22

0 MUX

CLAMP

1

PGA

R_SAD11 (0x136[1]) R_SAD20 (0x136[4])

0 1

MUX

ADC2

Figure 7-41

ADC2 (Internal) AOUT2 (Pin18)

R_AMUX2 (0x136[6])

R_SEL2 (0x102[6])

ADC1 (Internal) AOUT1 (Pin9)

R_AMUX1 (0x136[2])

R_SEL1 (0x102[3])

AIN21

ADC1

R_SAD21 (0x136[5])

AFE Architectures

7.45.8 Analo g AGC Contr ol BIT1611B AGC provides a 0.5~2 times input gain to compensate the abnormal input signals automatically. The relative settings are shown as below.

R_GAIN1_VALUE (0x128[0],0x126[7:0])

From ADC1 From ADC2

0

0 1

MUX

R_FIXEDGAIN1 (0x128[1])

AGC

1

R_GAIN_SEL (0x129[0])

0 MUX

R_GAIN2_VALUE (0x128[4],0x127[7:0])

Figure 7-42

Table 7-59

To ADC2 PGA

R_FIXEDGAIN2 (0x128[5]) Analog Auto Gain Control

Analog AGC Control Register

Mnemonic

2006/5/5

To ADC1 PGA

1 MUX

Address

R/W bit

Description

Default

R_GAIN1_VALUE

0x128[0],0x126[7:0]

RW

9 Fixed Gain Value for ADC1

0x0F6

R_GAIN2_VALUE

0x128[4],0x127[7:0]

RW

9 Fixed Gain Value for ADC2

0x0F6



BIT1611B


Auto Gain Control Enable fro ADC1 R_FIXGAIN1_EN

0x128[1]

RW

1 0: Auto Gain Control

1

1: Fixed Gain Value Auto Gain Control Enable for ADC2 R_FIXGAIN2_EN

0x128[5]

RW

1 0: Auto Gain Control

1

1: Fixed Gain Value Auto Gain Control Hold R_GAIN_HOLD

0x128[7]

RW

1 0: Disable

0

1: Enable Gain Source Select R_GAIN_SEL

0x129[0]

RW

1 0: From ADC1

0

1: From ADC2 Fixed Gain Enable on HLCK R_GAIN_HLCK

0x129[1]

RW

1 0: Disable

0

1: Enable R_GAIN_THB

0x129[7:4]

RW

4 AGC Bottom Threshold Value

0x1

7.45.9 Analog Clamp Control BIT1611B Video Decoder can set the clamp level respectively for each ADC input channel.

Table 7-60

Clamp Control Register

Mnemonic

Address

R/W bit

Description

Default

Analog Clamp and Gain Vsync Mode R_AAGC_VSMODE

0x129[2]

RW

1 0: Normal Mode (VSYNC)

0

1: AGC Mask Mode (AGC Mask) Analog Clamp and GAIN Disable on VSYNC R_MACROVISION_EN

0x129[3]

RW

1 0: Disable

1

1: Enable R_ACLAMP_LEVEL

0x12A[7:0] RW

8 Analog Clamp Level

0x3C

Analog Clamp1 Enable R_ACLAMP1_EN

0x12B[0]

RW

1 0: Disable

1

1: Enable Analog Clamp 1 Level Select R_ACLAMP1_MODE

0x12B[1]

RW

1 0: From R_ACLAMP_LEVEL (0x12A[7:0])

1

1: Middle Level (128) R_ACLAMP1_SPEED

0x12B[3:2] RW

2

Clamp trace speed for 00(slowest)~11(fastest)

ADC1

channel.

00

Analog Clamp2 Enable R_ACLAMP2_EN

0x12B[4]

RW

1 0: Disable

1

1: Enable Analog Clamp 2 Level Select R_ACLAMP2_MODE

0x12B[5]

RW

1 0: From R_ACLAMP_LEVEL (0x12A[7:0])

1

1: Middle Level (128)

2006/5/5

Clamp trace speed for 00(slowest)~11(fastest)

ADC2

channel.

R_ACLAMP2_SPEED

0x12B[7:6] RW

2

R_CLAMP1_MOD

0x12F[3]

RW

1 Clamp 1 Type

0

R_CLAMP2_MOD

0x12F[7]

RW

1 Clamp 2 Type

0


00


BIT1611B

Beyond Innovation Technology Co., Ltd. 7.45.10 Digital AGC and Clamp Control

BIT1611B digital AGC provides a 0.25~8 times input digital gain to compensate the abnormal input signals automatically. The relative settings are shown as below.

Table 7-61

Digital AGC Control Register

Mnemonic R_DGAIN1_VALUE

R_FIXDGAIN1_EN

Address

R/W

bit

0x12E[0],0x12C[7:0]

RW

9

0x12E[1]

RW

1

Description Fixed Gain Value for Digital AGC1 Digital Auto Gain Control Enable for ADC1 0: Auto Gain Control

Default 0x040

1

1: Fixed Gain Value Gain source select for ADC1 R_DGAIN1_SEL

0x12E[2]

RW

1

0: From ADC1 Source

0

1: Reference with ADC2 AGC Value Digital AGC1 and Clamp Auto Enable R_DGAIN1_AUTO

0x12E[3]

RW

1

0: Disable

0

1: Enable Digital Clamp Control Enable for ADC1 R_DCLAMP1_EN

0x12F[0]

RW

1

0: Disable

0

1: Enable Digital Clamp 1 Trace Hold enable R_DCLAMP1_HOLD 0x12F[1]

RW

1

0: Disable

0

1: Enable(Hold) Digital Clamp 1 Level Select R_DCLAMP1_TYPE

0x12F[2]

RW

1

0: From R_DCLAMP_LEVEL (0x131[7:0])

0

1: Middle Level (128) R_DGAIN2_VALUE

R_FIXDGAIN2_EN

0x12E[4],0x12D[7:0]

0x12E[5]

RW

RW

9

1

Fixed Gain Value for Digital AGC1 Digital Auto Gain Control Enable for ADC2 0: Auto Gain Control

0x040

1

1: Fixed Gain Value Gain source select for ADC2 R_DGAIN2_SEL

0x12E[6]

RW

1

0: From ADC2 Source

0

1: Reference with ADC1 AGC Value Digital AGC2 and Clamp Auto Enable R_DGAIN2_AUTO

0x12E[7]

RW

1

0: Disable

0

1: Enable Digital Clamp Control Enable for ADC2 R_DCLAMP2_EN

0x12F[4]

RW

1

0: Disable

0

1: Enable Digital Clamp 2 Trace Hold enable R_DCLAMP2_HOLD 0x12F[5]

RW

1

0: Disable

0

1: Enable(Hold) Digital Clamp 2 Level Select R_DCLAMP2_TYPE

0x12F[6]

RW

1

0: From R_DCLAMP_LEVEL (0x131[7:0])

0

1: Middle Level (128) 2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. R_CLAMP_INC

0x130[3:0]

RW

4

Digital Clamp Speed

0xF

Digital AGC VSYNC Mode R_DAGC_VSMODE

0x130[4]

RW

1

0: Normal VSYNC

0

1: AGC Mask R_DCLAMP_VALUE 0x131[7:0]

RW

8

Digital Clamp Level

0x3C

7.45.11 ADC Cont rol BIT1611B provides two ADCs.

Table 7-62 Mnemonic

The relative settings are shown below.

ADC Control Register Address

R/W bit

Description

Default

ADC1 Switch 1 Enable R_SAD10

0x136[0]

RW

1 0: Open

0

1: Close ADC1 Switch 2 Enable R_SAD11

0x136[1]

RW

1 0: Link to Ground

0

1: Link to ADC Input Bypass PGA R_AMUX1

0x136[2]

RW

1 0: Enable (don’t using PGA)

0

1: Disable (using PGA) ADC2 Switch 1 Enable R_SAD20

0x136[4]

RW

1 0: Open

0

1: Close ADC2 Switch 2 Enable R_SAD21

0x136[5]

RW

1 0: Link to Ground

0

1: Link to ADC Input Bypass PGA R_AMUX2

0x136[6]

RW

1 0: Enable (don’t using PGA)

0

1: Disable (using PGA) ADC Test Mode Enable R_ADCTEST

0x136[7]

RW

1 0: Disable

0

1: Enable ADC Clock Polarity R_ADCCLK_INV

0x137[2]

RW

1 0: Normal

0

1: Invert ADC Clock Select R_ADCCLK_SEL

0x137[3]

RW

1 0: CLK_135 (13.5MHz)

0

1: CLK_27 (27.0MHz)

2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 7.45.12 AFE PLL Clock Contr ol BIT1611B provides a PLL to generate the clock signal for the Video Decode. shown as Table 7-58.

The relative settings are

ICLK2 Referenc e Clock

1

0

1 0 MUX

R_CLKMUX

PLL

MUX

0

MUX

1

0 1

R_RMUX

1

ICLK1

0 MUX

1

R_DVT_PLL

Figure 7-43

Table 7-63

CLK13 5

R_INV_CLK

R_DVT_PLL

0

MUX

MUX

CLK27

R_INV_CLK

Video Decoder PLL

AFE PLL Clock Control Register

Mnemonic

Address

R/W bits

Description

Default

CLK135/CLK27 Clock Polarity R_INV_CLK

0x137[0]

RW

1 0: Normal

0

1: Invert CLK135/CLK27 Source Select R_DVT_PLL

0x137[1]

RW

1 0: Internal Clock

0

1: External Clock Reference Clock Select R_RMUX

0x137[4]

RW

1 0: External Clock Source

0

1: Internal Clock Source PLL Clock phase shift R_PMUX

0x137[5]

RW

1 0: Normal

0

1: Shift 180° Internal CLK135 Clock Source Select R_CLKMUX

0x137[6]

RW

1 0: PLL Clock

0

1: Reference Clock PLL Enable R_EAPLL

0x137[7]

RW

1 0: Disable

0

1: Enable

7.45.13 Status Register BIT1611B provides the “Read Only Registers”. video decoder from the relative registers.

2006/5/5

An external MCU may read out the internal settings of the



BIT1611B


Video Decoder Status Register

Mnemonic

Address

R/W bits

Description

Default

R_DCLAMP1_OUT

0x180[7:0]

R

8 Digital Clamp 1 trace value

-

R_DCLAMP2_OUT

0x181[7:0]

R

8 Digital Clamp 2 trace value

-

R_GAIN_OUT

0x185[2], 0x182[7:0]

R

9 Analog AGC trace value

-

R_DGAIN1_OUT

0x185[0], 0x183[7:0]

R

9 Digital AGC1 trace value

-

R_DGAIN2_OUT

0x185[4], 0x184[7:0]

R

9 Digital AGC2 trace value

-

AGC 1 Value Monitor R_OVER1

0x185[1]

R

1 0: gain value less than 511

-

1: gain value equal to 511 AGC 2 Value Monitor R_OVER2

0x185[5]

R

1 0: gain value less than 511

-

1: gain value equal to 511 Color Standard Detection Result 000: PAL 001: PAL_N 010: SECAM R_COLOR_STANDARD

0x186[2:0]

R

3 011: PAL_M

-

100: NTSC_4.43_50Hz 101: NTSC_M / NTSC_J 110: NTSC_4.43_60Hz 111: B&W Vsync Frequency R_FIDT

0x186[3]

R

1 0: 50Hz

-

1: 60Hz Hsync Lock Status R_HLCK

0 x186[4]

R

1 0: Un-Locked

-

1: Locked Vsync Frequency (Fast Mode) R_FFIDT

0 x186[5]

R

1 0: 50Hz

-

1: 60Hz H-LOCK Ready R_SYNC_READY

0x186[6]

R

1 0: Not Ready

-

1: Ready Auto Color Standard Detect Ready R_STD_READY

0x186[7]

R

1 0: Not Ready

-

1: Ready R_INC_CHRO

0x18B[3], 0x188[7:0], 0x187[7:0]

R

17 Line-Lock Frequency Output

-

R_SUB_FREQ

0x18B[1:0], 0x189[7:0]

R

10 Sub-Carrier Frequency Output

-

R_SUB_PHASE

0x18B[6:4], 0x18A[7:0]

R

11 Sub-Carrier Frequency Phase

-

Color kill detect R_COLORKILL

0x18B[2]

R

1 0: Normal

-

1: Color Kill Enable

2006/5/5



BIT1611B


7-46 OSD Function The embedded OSD supports the following features: 1. Three OSD Windows 2. 240 Fixed FONT ROM / 16 User programmable FONT RAM 3. 128 characters Display RAM 4. Index-based Display RAM Memory Management 5. Independent zoom ratio x0.5~x4 for horizontal and vertical directions. 6. Programmable Vertical Directions Line Space 7. Fade IN/OUT Effect 8. 16 Colors Palette Items(512 colors) 9. Blink display Effect 10. Fringe Font Effect 11. External OSD interface

7.46.1OSD Window s Fun cti on With the embedded OSD, BIT1611B opens at most 3 OSD windows at the same time refer to Table 7-47 for related registers.

Table 7-65 Mnemonic

2006/5/5

OSD Windows Register Address

R/W

bit

R_W1_HSTART

0x13A[5:4], 0x138[7:0]

RW

10 OSD1 start X position

0x000

R_W1_VSTART

0x13A[0], 0x139[7:0]

RW

9 OSD1 start Y position

0x000

R_W1_HWIDTH 0x13B[5:0]

RW

6 OSD1 Width (in Characters)

0x00

R_W1_VWIDTH 0x13C[4:0]

RW

5 OSD1 Height (in Characters)

0x00

R_W2_HSTART

0x148[5:4], 0x146[7:0]

RW


0x000

R_W2_VSTART

0x148[0], 0x147[7:0]

RW


0x000

R_W2_HWIDTH 0x149[5:0]

RW


0x00

R_W2_VWIDTH 0x14A[4:0]

RW


0x00

R_W3_HSTART

0x156[5:4], 0x154[7:0]

RW


0x000

R_W3_VSTART

0x156[0], 0x155[7:0]

RW


0x000

R_W3_HWIDTH 0x157[5:0]

RW


0x00

R_W3_VWIDTH 0x158[4:0]

RW


0x00


Description

Default


BIT1611B


(0,0) T R A T S V _ 3 W _ R

T R A T S V _ 2 W _ R

R_W1_HSTART

HSYNC

R_W1_HWIDTH

T R A T S V _ 1 W _ R

H T D I W V _ 1 W _ R

OSD1

H T D I W V _ 2 W _ R H T D I W V _ 3 W _ R

OSD2

OSD3 R_W3_HSTART R_W3_HWIDTH

R_W2_HWIDTH

R_W2_HSTART

VSYNC

Figure 7-44

OSD Windows Setup

7.46.2 OSD Memory Mappin g

Table 7-66

OSD Memory Mapping Table Memory

Mapping Address

OSD Display RAM (CODE)

500H~57FH

OSD Display RAM (ATTR.)

580H~5FFH

Palette RAM

600H~63FH (same as 640H~67FH, 680H~6BFH,63C0H~6FFH)

User programmable FONT RAM

2006/5/5

700H~7FFH(R_BANK_SEL=0, map to User Font 0~7) 700H~7FFH(R_BANK_SEL=1, map to User Font 8~15)



BIT1611B

Beyond Innovation Technology Co., Ltd. FixedROM 00 01

DisplayRAM 7bit 8'h00

WORD0 WORD1

1bit

CODE

F0

(highbit11~bit6) (lowbit5~bit0)

ATTR

WORD126

8'h7F

UserProgrammable FONTRAM

E F

8'h80 WORD0 WORD1

8'hF F

WORD127

WORD126

(highbit11~bit6)

WORD127

FF

(lowbit5~bit0)

PaletteRAM B6

B5

B4

Bit[3:0]

0

PaletteIndex

PaletteIndex0

4bit

PaletteIndex1

Addressbit7

PaletteIndexF 3F

0:ForegroundBlinkDisable 1:ForegroundBlinkEnable

BorderEnable 0:BackgroundFadeDisable 1:BackgroundFadeEnable

ForegroundTransparentEnable BackgroundTransparentEnable ForegroundFadeEnable BackgroundBlinkEnable

Address0

B5

B3

B2

B1

B0

Address1

ForegroundR

ForegroundG

Address2

ForegroundB

BackgroundR

Address3

BackgroundG

BackgroundB

Figure 7-45

2006/5/5

B4

OSD Memory Mapping



BIT1611B


Figure 7-46

OSD User Programmable Font RAM

Figure 7-47 2006/5/5

Palette RAM Example



BIT1611B

Beyond Innovation Technology Co., Ltd. 7.46.3 OSD Windo ws Attr ibu te BIT1611B can set different attributes onto 3 OSD windows independently.

Table 7-67

OSD Windows Attribute Register

Mnemonic

2006/5/5

Address

R/W bit

Description

Default

R_W1_INDEX

0x13D[6:0] RW

7 OSD1 Display RAM Start index

0x00

R_W1_FADE

0x13E[3:0] RW

4 OSD1 Fade in/out Level

R_W1_WHMIRROR

0x13E[4]

RW

1 OSD1 Window Mirror for horizontal

0

R_W1_WVMIRROR

0x13E[5]

RW

1 OSD1 Window Flip

0

R_W1_FHMIRROR

0x13E[6]

RW

1 OSD1 Characters Mirror for horizontal

0

R_W1_FVMIRROR

0x13E[7]

RW

1 OSD1 Characters Mirror for vertical

0

0x0

Font Border Selection bit7:left,up; bit6:up; bit5:right,up; 0x00 bit4:left; bit3:right; bit2:left,down; bit1:down; bit0:right,down; Border Horizontal Width (R_W1_BORDER_HW<=R_W1_FONTSIZE_ H) 0 2’b00:1 pixel; 2’b01:2 pixels; 2’b10:3 pixels; 2’b11:4 pixels; Border Vertical Width (R_W1_BORDER_VW<=R_W1_FONTSIZE_ V) 0 2’b00:1 pixel; 2’b01:2 pixels; 2’b10:3 pixels; 2’b11:4 pixels; Font Border Color 0 Bit2 : Color R; bit1 : Color G; bit0 : Color B; OSD1 Horizontal Character Size 000:x1, 001:x2, 010:x3, 011:x4 000 100:x0.5 (odd), 101:x0.5 (even), 11x:x0.5 (field change) OSD1 Vertical Character Size 000:x1, 001:x2, 010:x3, 011:x4 00 100:x0.5 (odd), 101:x0.5 (even), 11x:x0.5 (field change)

R_W1_BORDER_SEL

0x13F

RW

8

R_W1_BORDER_HW

0x140[1:0] RW

2

R_W1_BORDER_VW

0x140[3:2] RW

2

R_W1_BORDER_COLOR 0x140[6:4] RW

3

R_W1_FONTSIZE_H

0x141[2:0] RW

3

R_W1_FONTSIZE_V

0x141[6:4] RW

3

R_W1_LNNUM

0x142[3:0] RW

4 OSD1 vanish Line Number

0x0

R_W1_LNDIR

0x142[4]

RW

1 OSD1 vanish Line Direction

0

R_W1_EN

0x143[0]

RW

1 OSD1 Window enable

0

R_W1_BLINKCYCLE

0x143[3:1] RW

OSD1 Blink Period (in VSYNC) 3'b000 : 1; 3'b001 : 2; 3'b010 : 4; 3 3'b011 : 8; 3'b100 : 16; 3'b101 : 32; 3'b110 : 64; 3'b111 : 128;

R_W1_STR_GAP

0x143[6:4] RW

3 OSD1 Vertical Character space

000

R_W2_INDEX

0x14B[6:0] RW


0x00

R_W2_FADE

0x14C[3:0] RW


R_W2_WHMIRROR

0x14C[4]

RW

1 OSD2 Window Horizontal Mirror

0

R_W2_WVMIRROR

0x14C[5]

RW

1 OSD2 Window Flip

0

R_W2_FHMIRROR

0x14C[6]

RW

1 OSD2 Characters Horizontal Mirror

0

R_W2_FVMIRROR

0x14C[7]

RW

1 OSD2 Characters Vertical Mirror

0

R_W2_BORDER_SEL

0x14D

RW

8

Font Border Selection bit7:left,up; bit6:up;


000

0x0

bit5:right,up;

0x00


BIT1611B


2006/5/5

bit4:left; bit3:right; bit2:left,down; bit1:down; bit0:right,down; Border Horizontal Width (R_W2_BORDER_HW<=R_W2_FONTSIZE_ H) 0 2’b00:1 pixel; 2’b01:2 pixels; 2’b10:3 pixels; 2’b11:4 pixels; Border Vertical Width (R_W2_BORDER_VW<=R_W2_FONTSIZE_ V) 0 2’b00:1 pixel; 2’b01:2 pixels; 2’b10:3 pixels; 2’b11:4 pixels; Font Border Color 0 bit2 : Color R; bit1 : Color G; bit0 : Color B; OSD2 Horizontal Character Size 000:x1, 001:x2, 010:x3, 011:x4 000 100:x0.5 (odd), 101:x0.5 (even), 11x:x0.5 (field change) OSD2 Vertical Character Size 000:x1, 001:x2, 010:x3, 011:x4 000 100:x0.5 (odd), 101:x0.5 (even), 11x:x0.5 (field change)

R_W2_BORDER_HW

0x14E[1:0] RW

2

R_W2_BORDER_VW

0x14E[3:2] RW

2

R_W2_BORDER_COLOR 0x14E[6:4] RW

3

R_W2_FONTSIZE_H

0x14F[2:0] RW

3

R_W2_FONTSIZE_V

0x14F[6:4] RW

3

R_W2_LNNUM

0x150[3:0] RW


0x0

R_W2_LNDIR

0x150[4]

RW


0

R_W2_EN

0x151[0]

RW


0

R_W2_BLINKCYCLE

0x151[3:1] RW


R_W2_STR_GAP

0x151[6:4] RW


000

R_W3_INDEX

0x159[6:0] RW


0x00

R_W3_FADE

0x15A[3:0] RW


R_W3_WHMIRROR

0x15A[4]

RW

1 OSD3 Window Horizontal Mirror

0

R_W3_WVMIRROR

0x15A[5]

RW

1 OSD3 Window Flip

0

R_W3_FHMIRROR

0x15A[6]

RW

1 OSD3 Characters Horizontal Mirror

0

R_W3_FVMIRROR

0x15A[7]

RW

1 OSD3 Characters Vertical Mirror

0

R_W3_BORDER_SEL

0x15B

RW

8

R_W3_BORDER_HW

0x15C[1:0] RW

2

R_W3_BORDER_VW

0x15C3:2]

RW

2

R_W3_BORDER_COLOR 0x15C[6:4] RW

3

R_W3_FONTSIZE_H

3

0x15D[2:0] RW

000

0x0

Font Border Selection bit7:left,up; bit6:up; bit5:right,up; 0x00 bit4:left; bit3:right; bit2:left,down; bit1:down; bit0:right,down; Border Horizontal Width (R_W3_BORDER_HW<=R_W3_FONTSIZE_ H) 0 2’b00:1 pixel; 2’b01:2 pixels; 2’b10:3 pixels; 2’b11:4 pixels; Border Vertical Width (R_W3_BORDER_VW<=R_W3_FONTSIZE_ V) 0 2’b00:1 pixel; 2’b01:2 pixels; 2’b10:3 pixels; 2’b11:4 pixels; Font Border Color 0 bit2 : Color R; bit1 : Color G; bit0 : Color B; OSD3 Horizontal Character Size 000 000:x1, 001:x2, 010:x3, 011:x4



BIT1611B

Beyond Innovation Technology Co., Ltd. 100:x0.5 (odd), 101:x0.5 (even), 11x:x0.5 (field change) OSD3 Vertical Character Size 000:x1, 001:x2, 010:x3, 011:x4 3 100:x0.5 (odd), 101:x0.5 (even), 11x:x0.5 (field change)

R_W3_FONTSIZE_V

0x15D[6:4] RW

R_W3_LNNUM

0x15E[3:0] RW


0x0

R_W3_LNDIR

0x15E[4]

RW


0

R_W3_EN

0x15F[0]

RW


0

R_W3_BLINKCYCLE

0x15F[3:1] RW


R_W3_STR_GAP

0x15F[6:4] RW


Figure 7-48

000

000

000

OSD Windows Attribute

7.46.4 Extern al OSD Interfac e BIT1611B can connect with external OSD device for advanced OSD performance, total 512 colors can be displayed. However, at such circumstance, BIT1611B will not support graphic mode input.

Table 7-68 Mnemonic R_EXTOSD_EN

External OSD Register Address 0x162[0]

R/W bit RW

Description

1 External OSD Enable

Default 0

0: Disable 2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 1: Enable External OSD Blank polarity R_POL_EXTBNK

0x162[1]

RW

1 0: Normal

0

1: Invert External OSD HSYNC polarity R_POL_OSDHS

0x162[2]

RW

1 0: Normal

0

1: Invert External OSD VSYNC polarity R_POL_OSDVS

0x162[3]

RW

1 0: Normal

0

1: Invert External OSD CLOCK polarity R_POL_OSDCLK

0x162[4]

RW

1 0: Normal

0

1: Invert R_COR0_R

0x163[2:0]

RW

External OSD Color 3 ExtOSD_B = 0,ExtOSD_G = 0,ExtOSD_R = 0

000

Color R Value R_COR0_G

R_COR0_B

R_COR1_R

R_COR1_G

R_COR1_B

R_COR2_R

R_COR2_G

R_COR2_B

R_COR3_R

R_COR3_G

R_COR3_B

2006/5/5

0x163[6:4]

0x164[2:0]

0x164[6:4]

0x165[2:0]

0x165[6:4]

0x166[2:0]

0x166[6:4]

0x167[2:0]

0x167[6:4]

0x168[2:0]

0x168[6:4]

RW

External OSD Color 3 ExtOSD_B = 0,ExtOSD_G = 0,ExtOSD_R = 0 Color G Value

000

RW

External OSD Color 3 ExtOSD_B = 0,ExtOSD_G = 0,ExtOSD_R = 0 Color B Value

000

RW

External OSD Color 3 ExtOSD_B = 0,ExtOSD_G = 0,ExtOSD_R = 1 Color R Value

111

RW


000

RW


000

RW


000

RW


111

RW


000

RW


111

RW


111

RW


000



BIT1611B

Beyond Innovation Technology Co., Ltd. R_COR4_R

R_COR4_G

R_COR4_B

R_COR5_R

R_COR5_G

R_COR5_B

R_COR6_R

R_COR6_G

R_COR6_B

R_COR7_R

R_COR7_G

R_COR7_B

RW


000

RW


000

0x16A[2:0] RW


111

0x16A[6:4] RW


111

0x16B[2:0] RW


000

0x16B[6:4] RW


111

0x16C[2:0] RW


000

0x16C[6:4] RW


111

0x16D[2:0] RW


111

0x16D[6:4] RW


111

0x16E[2:0] RW


111

0x16E[6:4] RW


111

0x169[2:0]

0x169[6:4]

7.46.5 OSD User Progr ammable RAM Selection The following register used to select banks when read/write the OSD User Programmable RAM. User Programmable RAM Selection Mnemonic

Address

R/W Bits

Description

Default

User Programmable RAM Banks Selection R_BANK_SEL

0x162[7]

RW

1 0: Bank 0, mapping to User Font 0~7

0

1: Bank 1, mapping to User Font 0~7

2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. 7.46.6 OSD Bui lt-in Fixed Font

BIT1611B has built 240 fonts for embedded OSD and the addresses refer to the following.

Lower Nibble 0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0 1 2 3 4 5

Upper

6

Nibble 7 8 9 A B C D E

Figure 7-49

2006/5/5

Fixed FONT



BIT1611B


8 Interface Mode BIT1611B provides 2 kinds of Interface Mode (Slave Mode 和 Script Master Mode).

8-1 Optio ns Pins BIT1611B uses 6 external pins for Mode selection.

Table 8-1 OP5

OP4

0

Refer to Table 8-1 :

Options Pins Setup

OP3

OP2

GPI[10:8]

OP1

OP0

Mode

SCL

DIO

EEPROM 24Cxx Script Mode

1

0

0

0

SCL

DIO

I2C Mode Slave Address (0x00~0x0D)

1

0

0

1

SCL

DIO


1

0

1

0

SCL

DIO


1

0

1

1

SCL

DIO


1

1

0

0

BITCK

BITDIO

BiTEKBUS Mode Slave Address 0x81

1

1

0

1

BITCK

BITDIO


1

1

1

0

BITCK

BITDIO


1

1

1

1

BITCK

BITDIO


8-2 Scri pt Master Mode BIT1611B provides Script Control Function that let user store the program inside of Serial EEPROM. BIT1611B can just work with the EEPROM according to the instructions in EEPROM. 24cxx series (24C02~24C16) Serial EEPROM are supported.

8.2.1

Architecture BIT1611B built-in Script Control that has 4 Internal Registers (A_reg, B_reg, C_reg, Z_reg) and 4 Internal Address Indexes (PC、EADDR、RADDR、IADDR). The calculation and logic operation are performed in A_reg and B_reg.

Table 8-2 Register and Address Index Register and Address Index

2006/5/5

bits

Memo

A_REG

8

A Register

B_REG

8

B Register

C_REG

1

Carry Flag Register

Z_REG

1

Zero Flag Register

PC

11

Program Counter

EADDE

11

EEPROM Address

RADDR

11

Internal Register Sets Address

IADDR

8

I2C Address



BIT1611B


8.2.2

Start and Interr upt BIT1611B built-in Script Control Function that provides Interrupt Processing. The conditions of Interrupt (0x02[7:0]) can be proceeded, and BIT1611B provides automatic Re-ACK function so as to reduce the complexity of program. Table 8-3 shows the related starting address:

Table 8-3 Register and Address Index Event

Type

Address

POR(Power On Reset)

Immediate

PC = 0x10

SIGIN(0x02[0])

Index

PC = {EADDR[1],EADDR[0]}

NOSIG(0x02[1])

Index


MODECHG(0x02[2])

Index


VSYNC(0x02[3])

Index


ERROR1(0x02[4])

Index


ERROR2(0x02[5])

Index


IR(0x02[6])

Index


KEYIN(0x02[7])

Index

PC ={EADDR[15],EADDR[14]}

8.2.3

Instr uct ion Set BIT1611B built-in Script Control Function that support the following instruction code:

Table 8-4

Instruction Set

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

0

0

0

0

0

0

0

1

1

0

0

0

0

0

1

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

1

1

0

0

0

0

0

0

1

1

1

0

0

0

0

1

0

0

0

0

0

0

0

1

0

0

1

0

0

0

0

1

0

1

0

0

0

0

0

1

0

1

1

0

0

0

0

1

1

0

0

0

0

0

0

1

1

0

1

2006/5/5

Instruction ADD A_reg  A_reg +B_reg SUB A_reg  A_reg – B_reg INC A_reg  A_reg + 1 DEC A_reg  A_reg – 1 CLR A_reg  0 COMP A_reg – B_reg (no update A_reg) MOV B,A B_reg  A_reg HALT Program Stop into Standby Mode AND A_reg  A_reg (and) B_reg OR A_reg  A_reg (or) B_reg XOR A_reg  A_reg (xor) B_reg NOT A_reg  ~A_reg SHR A_reg  A_reg >> 1 SHL


Command Byte

C

Z

1

●

●

1

●

●

1

●

●

1

●

● ●

1 1

●

●

1 1 1

●

1

●

1

●

1

●

1

●

1

● page 95 of 109 DOC NO.W-DS-0004

BIT1611B

Beyond Innovation Technology Co., Ltd. A_reg  A_reg << 1 0

0

0

0

1

1

1

0

0

0

0

1

0

R10

R9

R8

0

0

0

1

1

R10

R9

R8

0

0

1

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

0

0

1

0

0

1

0

1

0

0

1

0

0

1

1

0

0

0

1

0

1

E10

E9

E8

0

0

1

1

0

R10

R9

R8

0

0

1

1

1

R10

R9

R8

0

1

E10

E9

E8

R10

R9

R8

1

0

B2

B1

B0

E10

E9

E8

1

1

0

0

1

E10

E9

E8

1

1

0

0

0

E10

E9

E8

1

1

0

1

1

0

X

X

1

1

0

1

0

0

X

X

1

1

0

1

0

1

X

X

1

1

1

0

0

E10

E9

E8

1

1

1

0

1

E10

E9

E8

1

1

1

1

0

E10

E9

E8

1

1

1

1

1

E10

E9

E8

2006/5/5

SWAP A_reg  B_reg MOV A, R[ADDR] A_reg [RADDR] MOV R[ADDR],A [RADDR]  A_reg MOV A, NUM A_reg  NUM MOV B,NUM B_reg  NUM DELAY NUM Delay NUM XCLK NOTC C_flag  ~C_flag NOTZ Z_flag  ~Z_flag RET PC  RET_ADDR MOV E[ADDR],NUM [EADDR] #NUM MOV R[ADDR],NUM [RADDR]  NUM FILL R[ADDR],NUM,CNT Loop CNT [RADDR+CNT]NUM MOV R[ADDR],E[ADDR],CNT Loop CNT [RADDR+CNT] [EADDR+CNT] JB EADDR,Bit IF A.[Bit]=1 PC EADDR else PC+1 MOV A,E[ADDR] A_reg  [EADDR] MOV E[ADDR],A [EADDR]  A_reg MOV A,I[ADDR] A_reg  [IADDR] MOV I[ADDR],A [IADDR]  A_reg MOV SPI, NUM SPI  NUM(3byte) JC EADDR IF C_reg=1 PC EADDR else PC+1 JZ EADDR IF Z_reg=1 PC EADDR else PC+1 JMP EADDR PC  EADDR CALL EADDR RET_ADDR Next Command Addr PC  EADDR


1

●

2

●

2

●

2 2 2 1 1

● ●

1 3 3 4

4

2

2

●

2 2

●

2 4

2

2

2

2


BIT1611B


Instruct ion Format

1Byte OPCODE | 1byte

|

Instruction: ADD, SUB, INC, DEC, CLR, SHR, SHL, SWAP, NOTC, NOTZ, RET.

COMP,

MOV B,A;

HALT,

AND,

OR, XOR,

NOT,

2Byte

OPCODE | 1byte

A7 A6 A5 A4 A3 A2 A1 A0 || 1byte |

Instruction: MOV A, I[ADDR];

MOV I[ADDR], A;

OPCODE A10 A9 A 8 A7 A6 A5 A4 A3 A2 A1 A0 | 1byte || 1byte | Instruction: MOV A, R[ADDR]; MOV R[ADDR], A; MOV A, E[ADDR]; MOV E[ADDR], A; JC EADDR; JZ EADDR; JMP EADDR; CALL EADDR;

OPCODE B2 B1 B0 A10 A 9 A8 A7 A6 A5 A4 A3 A2 A1 A0 |

1byte

||

1byte

|

Instruction: JB EADDR, Bit;

OPCODE | 1byte Instruction: MOV A, NUM;

#NUMBER || 1byte MOV B, NUM;

| DELAY NUM;

3Byte OPCODE |

A10 A9 A 8 A7 A6 A5 A4 A3 A2 A1 A0 NUMBER 1byte || 1byte || 1byte

Instruction: MOV E[ADDR], NUM;

|

MOV R[ADDR], NUM;

4Byte

OPCODE | 1byte

NUMBER1 || 1byte

NUMBER2 || 1byte

NUMBER3 || 1byte

|

Instruction: MOV SPI, NUM;

OPCODE | 2006/5/5

A10 A9 A 8 A7 A6 A5 A4 A3 A2 A1 A0 NUMBER

1byte

||

1byte

||


1byte

COUNT VALUE ||

1byte

| page 97 of 109 DOC NO.W-DS-0004


BIT1611B

Instruction: FILL R[ADDR], NUM, CNT;

OPCODE E10 E9 E8 R10 R9 R8 E7 E6 E5 E4 E3 E2 E1 E0 R7 R6 R5 R4 R3 R2 R1 R0 COUNT VALUE | 1byte || 1byte || 1byte || 1byte

|

Instruction: MOV R[ADDR], E[ADDR], CNT;

2006/5/5



BIT1611B


8-3 Slave Mode BIT1611B provides BiTEKbus Protocol and Two-Wire Protocol for communication. decide the protocol.

8.3.1

Pin (OP5) and pin (OP4)

BiTEKbus Protocol BIT1611B decides the Slave Address by Pin73(OP3) and Pin71(OP2):

Table 8-5

BiTEKbus Slave Address

OP3

OP2

Slave Address

0

0

Slave Address = 0x81

0

1


1

0


1

1


BiTEK Serial Interface Bus 2 Wire (CE always tied high) bus timing : Slave address SDAT LINE

register address

S

7

6

5

4

3

2

DATA from slave 1

A C K

X

0 W

7

6

5

4

3

2

STOP

1

0

P

A C K

A C (End) K

BDAT from master A C

A C

K from slave

BCLK

(End from master)

K from slave

from master 1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

No 9th 7 8 clock

6

Single read Slave address SDAT LINE

register address n

S

7

6

5

4

3

2

1

A C K

X

BDAT

DATA n from slave 0 W

7

6

5

4

3

2

DATA n+1 from slave 1

0

7

6

5 4

3

2

STOP

1

0

P

A C K

A C K

A C K

A C

A C

A C

(End)

from master A C K from slave

BCLK

K from slave

K from master

K from master

from master 1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

(End from master)

No 9th clock

Burst read

Figure 8-1

2006/5/5

Bitek Serial Interface bus



BIT1611B


Figure 8-2

8.3.2

BiTEKbus Extension Mode

Two-Wire Proto col BIT1611B Slave Address provides Two-Wire Protocol for register accessing.

8.3.2.1 Two-Wire Protocol Device Address BIT1611B Two-Wire Protocol delivers 8-bit Device Address(slave address) after Start bit. and Pin71(OP2) decide the bit-6 an d bit-5 of Device Address.

Table 8-6

Two-Wire Protocol Device Address

Internal Register Address

Write Device Address

0x00(PIN73 = 0、PIN71=0) 0x000~0x0FF 0x20(PIN73 = 0、PIN71=1) (Register Bank1) 0x40(PIN73 = 1、PIN71=0) 0x60(PIN73 = 1、PIN71=1) 0x02(PIN73 = 0、PIN71=0) 0x100~0x1FF 0x22(PIN73 = 0、PIN71=1) (Register Bank2) 0x42(PIN73 = 1、PIN71=0) 0x62(PIN73 = 1、PIN71=1) 0x04(PIN73 = 0、PIN71=0) 0x200~0x2FF 0x24(PIN73 = 0、PIN71=1) (Gamma Table for R Channel) 0x44(PIN73 = 1、PIN71=0) 0x64(PIN73 = 1、PIN71=1) 0x06(PIN73 = 0、PIN71=0) 0x300~0x3FF 0x26(PIN73 = 0、PIN71=1) (Gamma Table for G Channel) 0x46(PIN73 = 1、PIN71=0) 0x66(PIN73 = 1、PIN71=1) 0x08(PIN73 = 0、PIN71=0) 0x400~0x4FF 0x28(PIN73 = 0、PIN71=1) (Gamma Table for B Channel) 0x48(PIN73 = 1、PIN71=0) 0x68(PIN73 = 1、PIN71=1) 0x0A(PIN73 = 0、PIN71=0) 0x500~0x5FF 0x2A(PIN73 = 0、PIN71=1) (OSD Display RAM) 0x4A(PIN73 = 1、PIN71=0) 0x6A(PIN73 = 1、PIN71=1) 0x0C(PIN73 = 0、PIN71=0) 0x600~0x6FF 0x2C(PIN73 = 0、PIN71=1) OSD Palette RAM) 0x4C(PIN73 = 1、PIN71=0) 0x6C(PIN73 = 1、PIN71=1) R_BAMK_SEL=0 0x0E(PIN73 = 0、PIN71=0) (0x162[7] ) 0x2E(PIN73 = 0、PIN71=1) 2006/5/5

Pin73(OP3)


Read Device Address 0x01(PIN73 = 0、PIN71=0) 0x21(PIN73 = 0、PIN71=1) 0x41(PIN73 = 1、PIN71=0) 0x61(PIN73 = 1、PIN71=1) 0x03(PIN73 = 0、PIN71=0) 0x23(PIN73 = 0、PIN71=1) 0x43(PIN73 = 1、PIN71=0) 0x63(PIN73 = 1、PIN71=1) 0x05(PIN73 = 0、PIN71=0) 0x25(PIN73 = 0、PIN71=1) 0x45(PIN73 = 1、PIN71=0) 0x65(PIN73 = 1、PIN71=1) 0x07(PIN73 = 0、PIN71=0) 0x27(PIN73 = 0、PIN71=1) 0x47(PIN73 = 1、PIN71=0) 0x67(PIN73 = 1、PIN71=1) 0x09(PIN73 = 0、PIN71=0) 0x29(PIN73 = 0、PIN71=1) 0x49(PIN73 = 1、PIN71=0) 0x69(PIN73 = 1、PIN71=1) 0x0B(PIN73 = 0、PIN71=0) 0x2B(PIN73 = 0、PIN71=1) 0x4B(PIN73 = 1、PIN71=0) 0x6B(PIN73 = 1、PIN71=1) 0x0D(PIN73 = 0、PIN71=0) 0x2D(PIN73 = 0、PIN71=1) 0x4D(PIN73 = 1、PIN71=0) 0x6D(PIN73 = 1、PIN71=1) 0x0F(PIN73 = 0、PIN71=0) 0x2F(PIN73 = 0、PIN71=1) page 100 of 109 DOC NO.W-DS-0004

BIT1611B

Beyond Innovation Technology Co., Ltd. 0x700~0x7FF (OSD User Font RAM Bank1) R_BAMK_SEL = 1 (0x162[7]) 0x700~0x7FF (OSD User Font RAM Bank2)

0x4E(PIN73 = 1、PIN71=0) 0x6E(PIN73 = 1、PIN71=1) 0x0E(PIN73 = 0、PIN71=0) 0x2E(PIN73 = 0、PIN71=1) 0x4E(PIN73 = 1、PIN71=0) 0x6E(PIN73 = 1、PIN71=1)

0x4F(PIN73 = 1、PIN71=0) 0x6F(PIN73 = 1、PIN71=1) 0x0F(PIN73 = 0、PIN71=0) 0x2F(PIN73 = 0、PIN71=1) 0x4F(PIN73 = 1、PIN71=0) 0x6F(PIN73 = 1、PIN71=1)

I2C Slave Address 0x00 0x0F

0x00~0x0F

0x20 0x2F

0x20~0x2F

0x40 0x4F

0x40~0x4F

0x60 0x6F

0x60~0x6F

OP3=0

OP2=0

OP3=0

OP2=1

OP3=1

OP2=0

OP3=1

OP2=1

0xFF Figure 8-3

2006/5/5

I2C Slave Address Mapping



BIT1611B


g n i t t e S 3 7 n i P m o r F

g n i t t e S 1 7 n i P m o r F

Figure 8-4

2006/5/5

Read/Write Mode



BIT1611B


9 Timin g Diagram 9-1 Hardware Reset: XCLK 16 XCLKs

Power supply voltage

RESET

9-2 Clock and Interrup t: XCLK

…

Interru t condition occur

IN

MCU read Reg[0x02] from BIT1611B Write Reg[0x04] by MCU

9-3 Input Signal: TI0S PCL TI0H IHS IVS

TI1S PCL TI1H RDIN7~0 GDIN7~0

2006/5/5



BIT1611B

Beyond Innovation Technology Co., Ltd. Symbol

Describe

TI0S,TI1S TI0H,TI1H

Max.

Min.

Unit

Input Setup time

2

ns

Input Hold time

2

ns

9-4 Output Signal: TOC Reg [0x25] Bit 7 = 0 OCL

Reg [0x25] bit 7 = 1

TO _MAX_DL TO_MIN_DL OVS OHS ODE R/G/BODD7~0 R/G/BEVEN7~0

Valid

Symbol

Describe

Timing

Unit

TOCK

Output clock half period

TO_MAX_DL

Output signal Max delay

TOCK - 1

ns

TO_MIN_DL

Output signal Min delay

TOCK - 4

ns

ns

9-5 Micro Processor Interface: (1)MCU write T_UC_CK

Bit_CLK T_W_H T_W_S Bit_CS Bit_DIO

2006/5/5

Valid

Symbol

Describe

Min

T_UC_CK

MCU clock period

12 * (1/XCLK)

ns

T_W_H

Write setup time

3

ns

T_W_S

Write hold time

3

ns


Max

Unit


BIT1611B


(2)MCU read T UC C Bit_CLK TR_MIN_DL TR_MAX_DL

Valid

Bit_DIO

Symbol

Describe

Min

T_UC_CK

MCU clock period

12 * (1/XCLK)

ns

TR_MAX_DL

Read Max delay

(3 * (1/XCLKI))+15

ns

TR_MIN_DL

Read Min delay

(3 * (1/XCLKI))+5

ns

PS.

2006/5/5

Max

Unit

XCLKI : crystal frequency (14.318 M)



BIT1611B


10 Electr ical Characterist ic 10-1 Absol ute Ratin g SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

AVcc

Supply Voltage for Analog Core

-0.3

3.6

V

VCC

Supply Voltage for Digital Core

- 0.3

3.6

V

Supply Voltage for Output Pad and DAC

-0.3

5.5

V

VIN

Input Voltage for Digital Core (5V Tolerant)

- 0.3

VCC+0.3

V

VINA

Input Voltage for Analog Core

-0.3

Avcc+0.3

V

TSTG

Storage Temperature

- 40

125

℃

HVdd

10-2 Recomm end Operating Cond iti on SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

AVcc

Supply Voltage for Analog Core

3.0

3.3

3.6

V

VCC

Supply Voltage for Digital Core

3.0

3.3

3.6

V

Hvdd

Supply Voltage for Output Pad and DAC

3.0

5.0

5.5

V

TOPR

Operating Temperature

-40

85

℃

MAX

UNIT

-1

1

uA

- 10

10

uA

0.3*VCC

V

10-3 DC Electrical Characters (under Recommend Operating Condition and TJ =0℃ to 115℃) SYMBOL

PARAMETER

CONDITION No pull-up nor

IIL

Input Leakage Current

IOZ

Tri-state Leakage Current

VIL

Input Low Voltage

CMOS

VIH

Input High Voltage

CMOS

VOL

Output Low Voltage

IOL= 4,8,16 mA

VOH

Output High Voltage

IOH= 4,8, 16 mA

VtVt+ CIN3 COUT3 CBID3 RI

Schmitt trigger negative

pull-down

MIN

TYP

0.7*VCC

V 0.4

2.4

V V

CMOS

1.10

V

CMOS

1.80

V

Input Capacitance

3

pF

Output Capacitance

3

pF

3

pF

50

KΩ

going threshold voltage Schmitt trigger positive going threshold voltage

Bi-directional Buffer Capacitance Input Pull-up/down Resistance

Note: The capacitance listed above does not include pad capacitance and package capacitance. One can estimate pin capacitance by adding pad capacitance about 0.5pF and the package capacitance.

2006/5/5



BIT1611B


11 Soldering Information 11-1 Reflow Solderin g: The choice of heating method may be influenced by plastic QFP package). If infrared or vapor phase heating is used and the package is not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stenciling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferable be kept below 245 °C for thick/large packages (packages with a 3 thickness ≧ 2.5 mm or with a volume ≧ 350 mm so called thick/large packages). The top-surface temperature of the packages should preferable be kept below 260 °C for thin/small packages (packages with a thickness < 2.5 mm 3 and a volume < 350 mm so called thin/small packages). Stage

Condition

Duration

max3.0+/-2℃/sec

-

150℃~200℃

60~180 sec

2’nd Ram Up

max3.0+/-2℃/sec

-

Solder Joint

217℃ above

60~150 sec

Peak Temp

260 +0/-5℃

20~40 sec

Ram Down rate

6℃/sec max

-

1’st Ram Up Rate Preheat

Temp (℃)

260 217 200 150

25 RT

60~ 180

60~150

Time(sec)

11-2 Wave Soldering: Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2006/5/5




BIT1611B

11-3 Manual Soldering: Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

2006/5/5



W-DS-0004-A0 BIT1611B

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