vlsilab

VLSI LAB MANUAL 2010

VLSI LAB MANUAL (06ESL77) Mahesh .A .A Department of Electronics and Communication

1 Bangalore

Mahesh. A.A

Prepd. By, Dept. Electronics and Communication


INDEX I.

VLSI DESIGN FLOW AND THE TOOLS USED IN CADENCE

II.

PART A: Digital Simulation PROCEDURE FOR CREATING DIGITAL SIMULATION USING VERILOG AND CADENCE DIGITAL TOOL. Experiment1: Inverter Experiment2: Buffer Experiment3: Transmission Gates(TG) Experiment4: Logic Gates AND,OR,NAND,NOR,XOR,XNOR Experiment5: Flip Flops JK,MS,SR,D,T Experiment6: Synchronous Counter Experiment7: Asynchronous Counter Experiment8: Parallel Adder Experiment 9: Serial Adder

III.

PART B: Analog Design

PART B[1] : Schematic Simulation PROCEDURE FOR CREATING THE SCHEMATIC SIMULATION Experiment 1(a): Experiment 2(a): Experiment 3(a): Experiment 4(a): Experiment 5(a): Experiment 6(a):

Inverter Schematic and test Cell View Common Source Amplifier Schematic and test Cell View Common Drain Amplifier Schematic and test Cell View Differential Amplifier Schematic and test Cell View Operational Amplifier Schematic and test Cell View R-2R DAC Schematic and test Cell View

PART B[1] : Layout Simulation

Layout Design Rules

IV.

PROCEDURE FOR CREATING THE LAYOUT AND SIMULATING Experiment 1(b): Inverter Layout Design Experiment 2(b): Common Source Amplifier Layout Design Experiment 3(b): Common Drain Amplifier Layout Design Experiment 4(b): Differential Amplifier Layout Design Experiment 5(b): Operational Amplifier Layout Design VLSI Viva Questions 2 Bangalore

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VLSI LAB MANUAL 2010 1) VLSI DESIGN FLOW AND TOOLS USED IN CADENCE PDK stands for Process Design Kit. A PDK contains the process technology and needed information to do device-level design in the Cadence DFII environment.

3 Bangalore

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PART - A

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VLSI LAB MANUAL 2010 2) PART A: Digital Simulation PROCEDURE FOR CREATING DIGITAL SIMULATION USING VERILOG AND CADENCE DIGITAL TOOL. Open Terminal Window and use the following commands  #csh  #source cshrc  #ls (ls can be skipped if you know which is the next directory to go)-this will list out the directories like Cadence_digital_labs cadence_analog_labs … then  #cd Cadence_digital_labs/Workarea  Crate a directory for the experiment presently executed by using following command. mkdir directory name Ex: mkdir Inverter  Create the module file/s(Verilog module ): Vi modulename.v Ex: vi inverter.v The file name can be changes with respect to the experiments.  A Text Editor window will open.To enter text in editor window PRESS “I” and then type the program and exit to terminal window by save and exit command --- Press Esc :wq!  Repeat the steps for test bench by following above TWO steps with different file name. Ex: vi test_inverter.v  Now to compile  Compile the module file/s with message option: ncvlog modulefilename.v-messages Ex: ncvlog inverter.v –messages (RTL code compilation)  Compile the test bench file with message option: ncvlog testbenchname.v-message Ex: ncvlog inverter.v –messages Note: Check out for error and warnings. If any then go back to text editor and edit and the compile

5 Bangalore

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VLSI LAB MANUAL 2010  Elaborate the top level design(test bench)  ncelab toplevelmodulename-access+rwc-message Top level module name to be elaborated is the name of test bench module ncelab inv_test –access +rwc –messages  Simulate the top level design  Non GUI mode ncsim toplevelmodulename ncsim inv_test  In GUI Mode Ncsim toplevelmodulename-gui ncsim inv_test -gui Now a console and Design Browser windows of Simvision are opened. In the Design Browser Window,Select the toplevelmodulename scope(Ex:inv_test) and select all the signals displayed and click on the waveform button in the toolbar. Waveform Window opens.Press run to run the simulation for a time period specified in the time field.

6 Bangalore

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VLSI LAB MANUAL 2010 Synthesize procedure using Cadence Tool

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 # cd csh  #source cshrc  # cd Cadence_digital_labs/Workare  #cd rclabs --for digital synthesis enter into rclabs  #cd rtl --The verilog file to be sythesizd must be copied into this directory form the directory where the simulated code is present. i.e from your directory created under Workarea.  cd .. --Come back rclabs directory  #cd work --Get into work directory under rclabs to synthesize the hdl file present in rtl directory. #rc –gui --this would start a GUI window for synthesizing. rc:/>set_attr lib_search_path ../library rc:/>set_attribute hdl_search_path ../rtl rc:/>set_attr library slow_highvt.lib (if this step gives an error then close the rc window by closing the GUI window and then type the following) • #cd / • #cd root/Cadence_digital_labs • #tar -xzvf Cadence_digital_labs.tar.gz (this should work and then continue with RC labs again) rc:/>read_hdl {file_name.v} Ex:read_hdl {ff1.v} (ff1.v must be in rtl directory of rclabs) rc:/>read_sdc ../constraints_filename.g (if any constraints file they must be read here) rc:/>elaborate rc:/>synthesize -to_mapped -effort medium ---now you must be able to see the schematic else go to file and click on update GUI in GUI window. rc:/>write > any_name.v rc:>report timing - This gives the timing reports like delay, propagation so on rc:/>report power - This gives the power dissipation report static and dynamic power dissipation rc:/>report area - This gives no of cell used and the area used for the calls.

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Experiment1: Inverter

Verilog code for inverter `resetall `timescale 1 ns / 1 ns `view vlog //Define our own Inverter, module inverter ( out , in ); // Declarations of I/O ,Power and Ground Lines output out; input in; supply1 pwr; supply0 gnd; // Instantiate pmos and nmos switches pmos (out,pwr,in); nmos (out,gnd,in); endmodule `noview

8 Bangalore

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VLSI LAB MANUAL 2010 Test bench for inverter `resetall `timescale 1 ns / 1 ns `view vlog // Testbench for Inverter Module module inv_test; wire out ; reg in ; ùselib view = vlog // Instantiate inverter Module inverter i1 ( out, in ) ; `nouselib // Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input=" , in , " Output=", out ); end endtask // Apply Stimulus initial begin in = 1'b0 ; in = 1'b1 ; in = 1'bx ; in = 1'bz ; end

#10 ; display ; #10 ; display ; #10 ; display ; #10 ; display ;

endmodule `noview 9 Bangalore

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VLSI LAB MANUAL 2010 Experiment 2: BUFFER

Verilog code for BUFFER `resetall `timescale 1 ns / 1 ns `view vlog //Define our own Inverter, module inverter ( Y, A ); // Declarations of I/O ,Power and Ground Lines output Y; input A; supply1 pwr; supply0 gnd; // Instantiate pmos and nmos switches pmos (Y,pwr,A); nmos (Y,gnd,A); endmodule // Define our own Buffer module buffer ( out, in); // Declarations of I/O Lines output out; input in; 10 Bangalore

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VLSI LAB MANUAL 2010 // Wire Declaration wire a; // Instantiate Inverter module inverter i1 (a,in); inverter i2 (out,a); endmodule `noview

Test bench for BUFFER `resetall `timescale 1 ns / 1 ns `view vlog // Testbench for Buffer Module module buf_test; wire out ; reg in ; ùselib view = vlog // Instantiate Buffer Module buffer b1 ( out, in ) ; `nouselib // Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input=" , in , " Output=", out ) ; end endtask // Apply Stimulus initial begin in = 1'b0 ; #10 ; display ; in = 1'b1 ; #10 ; display ; in = 1'bx ; #10 ; display ; in = 1'bz ; #10 ; display ; end endmodule `noview 11 Bangalore

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VLSI LAB MANUAL 2010 Experiment 3: TRANSMISSION GATE(TG)

Verilog code for TG `resetall `timescale 1 ns / 1 ns `view vlog //Define our own Transmission Gate, module trangate ( out , in , cntrl1, cntrl2 ); // Declarations of I/O and Control Lines output out; input in; input cntrl1,cntrl2; // Instantiate pmos and nmos switches pmos (out,in,cntrl1); nmos (out,in,cntrl2); endmodule `noview

12 Bangalore

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VLSI LAB MANUAL 2010 Test bench for TG `resetall `timescale 1 ns / 1 ns `view vlog // Testbench for Inverter Module module trangate_test; wire out ; reg in ; reg cntrl1,cntrl2; ùselib view = vlog // Instantiate trangate Module trangate t1 ( out, in, cntrl1, cntrl2 ) ; `nouselib // Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input=" , in , " Output=", out , " Control1=",cntrl1 , " Control2=",cntrl2 ) ; end endtask // Apply Stimulus initial begin in = 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; in = 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; in = 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; in = 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; end


endmodule

`noview 13 Bangalore

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VLSI LAB MANUAL 2010 Experiment 4: LOGIC GATES 4.1 NAND GATE

Verilog code for NAND GATE `resetall `timescale 1 ns / 1 ns `view vlog //Define our own Nand Gate, module nandgate ( out , in1 , in2 ); // Declarations of I/O ,Power and Ground Lines output out; input in1,in2; supply1 pwr; supply0 gnd; // Declaration of Wire wire contact; // Instantiate pmos and nmos switches pmos (out,pwr,in1); pmos (out,pwr,in2); nmos (out,contact,in1); nmos (contact,gnd,in2); endmodule `noview 14 Bangalore

Mahesh. A.A


VLSI LAB MANUAL 2010 Test bench for NAND GATE `resetall `timescale 1 ns / 1 ns `view vlog // Testbench for Nand Gate Module module nand_test; wire out ; reg in1,in2 ; ùselib view = vlog // Instantiate Nand Gate Module nandgate n1 ( out, in1, in2 ) ; `nouselib // Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask // Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; in1 = 1'b0 ; in2 = 1'b1 ; in1 = 1'b1 ; in2 = 1'b0 ; in1 = 1'b1 ; in2 = 1'b1 ; end


endmodule `noview

4.2 AND GATE 15 Bangalore

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Verilog code for AND GATE `resetall `timescale 1 ns / 1 ns `view vlog //Define our own And Gate, module andgate ( out , in1 , in2 ); // Declarations of I/O ,Power and Ground Lines output out; input in1,in2; supply1 pwr; supply0 gnd; // Declaration of Wires wire contact; wire nout; // Instantiate pmos and nmos switches to form Nand gate pmos (nout,pwr,in1); pmos (nout,pwr,in2); 16 Bangalore

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VLSI LAB MANUAL 2010 nmos (nout,contact,in1); nmos (contact,gnd,in2); // Instantiate pmos and nmos switches to form Inv pmos (out,pwr,nout); nmos (out,gnd,nout); endmodule `noview

Test bench for AND GATE `resetall `timescale 1 ns / 1 ns `view vlog // Testbench for And Module module and_test; wire out ; reg in1,in2 ; ùselib view = vlog // Instantiate And Gate Module andgate a1 ( out, in1, in2 ) ; `nouselib // Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ); end endtask // Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; end endmodule `noview

4.3 NOR GATE 17 Bangalore

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Verilog code for NOR GATE `resetall `timescale 1 ns / 1 ns `view vlog //Define our own Nor Gate, module norgate ( out , in1 , in2 ); // Declarations of I/O ,Power and Ground Lines output out; input in1,in2; supply1 pwr; supply0 gnd; // Declaration of Wire wire contact; // Instantiate pmos and nmos switches pmos (contact,pwr,in1); 18 Bangalore

Mahesh. A.A


VLSI LAB MANUAL 2010 pmos (out,contact,in2); nmos (out,gnd,in1); nmos (out,gnd,in2); endmodule `noview

Test bench for NOR GATE `resetall `timescale 1 ns / 1 ns `view vlog // Testbench for Nor Gate Module module nor_test; wire out ; reg in1,in2 ; ùselib view = vlog // Instantiate Nor Gate Module norgate n1 ( out, in1, in2 ) ; `nouselib // Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ); end endtask // Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; end endmodule `noview

4.4 OR GATE 19 Bangalore

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Verilog code for OR GATE `resetall `timescale 1 ns / 1 ns `view vlog //Define our own Or Gate, module orgate ( out , in1 , in2 ); // Declarations of I/O ,Power and Ground Lines output out; input in1,in2; supply1 pwr; supply0 gnd; // Declaration of Wires wire contact; wire nout; // Instantiate pmos and nmos switches for Nor gate pmos (contact,pwr,in1); pmos (nout,contact,in2); nmos (nout,gnd,in1); nmos (nout,gnd,in2); 20 Bangalore

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VLSI LAB MANUAL 2010 // Instantiate pmos and nmos switches for Not gate pmos (out,pwr,nout); nmos (out,gnd,nout); endmodule `noview

Test bench for OR GATE `resetall `timescale 1 ns / 1 ns `view vlog // Testbench for Nor Gate Module module or_test; wire out ; reg in1,in2 ; ùselib view = vlog // Instantiate Orgate Module orgate n1 ( out, in1, in2 ) ; `nouselib // Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ); end endtask // Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; end endmodule `noview

4.5 XNOR GATE 21 Bangalore

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Verilog code for XNOR GATE `resetall `timescale 1 ns / 1 ns `view vlog //Define our own XNOR Gate, module xnorgate ( out , in1 , in2 ); // Declarations of I/O ports output out; input in1,in2; wire in2bar; assign in2bar = ~in2; // Instantiate pmos and nmos switches : 22 Bangalore

Mahesh. A.A


VLSI LAB MANUAL 2010 pmos (out,in2bar,in1); nmos (out,in2,in1); pmos (out,in1,in2bar); nmos (out,in1,in2); endmodule `noview

Test bench for XNOR GATE `resetall `timescale 1 ns / 1 ns `view vlog // Testbench for Xnor Module module xnor_test; wire out ; reg in1,in2 ; ùselib view = vlog // Instantiate Xnor gate Module xnorgate x1 (out, in1, in2 ) ; `nouselib // Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask // Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; end endmodule `noview

4.6 XOR GATE 23 Bangalore

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Verilog code for XOR GATE `resetall `timescale 1 ns / 1 ns `view vlog //Define our own XOR Gate, module xorgate ( out , in1 , in2 ); // Declarations of I/O ports output out; input in1,in2; wire in2bar; assign in2bar = ~in2; // Instantiate pmos and nmos switches : pmos (out,in2,in1); nmos (out,in2bar,in1); pmos (out,in1,in2); nmos (out,in1,in2bar); endmodule `noview

Test bench for XOR GATE 24 Bangalore

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VLSI LAB MANUAL 2010 `resetall `timescale 1 ns / 1 ns `view vlog // Testbench for Xor Module module xor_test; wire out ; reg in1,in2 ; ùselib view = vlog // Instantiate Xorgate Module xorgate x1 (out, in1, in2 ) ; `nouselib // Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask // Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; end endmodule `noview

Experiment 5: FLIP FLOPS 25 Bangalore

Mahesh. A.A


VLSI LAB MANUAL 2010 5.1 D Flipflop:

Verilog File for D fillip flop module d_ff(d,clk, q,qb); input d,clk; output reg q,qb; always@(posedge(clk)) begin q = d; qb = ~d; end endmodule

Test Bench for D fillip flop module d_test; reg d,clk; wire q,qb; d_ff my_ff(d,clk,q,qb); initial clk = 1'b1; always #5 clk = ~clk; initial begin d = 0; #10; d = 1; #10; d = 0; #10; d = 1; #10; end endmodule

5.2 JK FLIP FLOP 26 Bangalore

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Verilog Code for JK-FF module jk_ff(j, k, clk, q, qb); input j,k,clk; output reg q,qb; reg kk = 1'b0; reg [1:0] t; always@(posedge(clk)) begin t={j,k}; case(t) 2'b00 : kk = kk; 2'b01 :kk = 1'b0; 2'b10 : kk = 1'b1; 2'b11 :kk = ~kk; default: ; endcase q = kk; qb = ~q; end endmodule

Test Bench for JK-FF 27 Bangalore

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VLSI LAB MANUAL 2010 module jk_test; reg j,k,clk; wire q,qb; jk_ff my_ff (j,k,clk,q,qb); initial clk = 1'b0; always #5 clk = ~clk; initial begin j = 0; k = 0; #10; j = 1; k = 1; #20; j = 0; k = 1; #10; j = 1; k = 1; #20; j = 1; k = 0; #10; end endmodule

5.3 MS FLIP FLOP 28 Bangalore

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Verilog Code MS- FF module ms_ff(j,k,clk, q,qb); input j,k,clk; output q,qb; jk_ff u1(j,k,clk,qm,qmb); jk_ff u2(qm,qmb,~clk,q,qb); endmodule

Test Bench for MS-FF module ms_test; reg j,k,clk; wire q,qb; ms_ff my_ff (j,k,clk,q,qb); initial clk = 1'b0; always #5 clk = ~clk; initial begin j = 1; k = 0; #10; j = 0; k = 1; #10; 29 Bangalore

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VLSI LAB MANUAL 2010 j = 1; k = 0; #10; j = 0; k = 1; #10; j = 1; k = 1; #10; end endmodule

5.4 SR FLIP FLOP 30 Bangalore

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Verilog Code SR FF module sr_ff(s,r, q,qb); input s,r; output reg q,qb; reg st = 1'b0; reg [1:0] k; always@(s|r) begin k = {s,r}; case(k) 2'b00 : st = st; 2'b01 : st = 1'b0; 2'b10 : st = 1'b1; 2'b11 : st = 1'bz; default: ; endcase q = st; qb = ~q; end endmodule

Test Bench SR FLIP FLOP module sr_test; 31 Bangalore

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VLSI LAB MANUAL 2010 reg r,s; wire q,qb; sr_ff my_ff(s,r,q,qb); initial begin r = 0; s = 0; #10; r = 0; s = 1; #10; r = 1; s = 0; #10; r = 1; s = 1; #10; r = 0; s = 0; #10; r = 0; s = 1; #10; r = 1; s = 0; #10; r = 1; s = 1; #10; end endmodule

5.5 T FLIP FLOP 32 Bangalore

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Verilog Code for T FF module t_ff(t,clk, q,qb); input t,clk; output q,qb; jk_ff u1(t,t,clk,q,qb); endmodule

Test Bench Code for T FF module t_test; reg t,clk; wire q,qb; t_ff my_ff(t,clk,q,qb); initial clk = 1'b0; always #5 clk = ~clk; initial begin t = 0; #10; t = 1; #10; t = 0; #10; t = 1; #10; end endmodule

Experiment 6: SYNCRONOUS COUNTER 33 Bangalore

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Verilog code for SYNCRONOUS COUNTER module count(clk,UpDown, reset, q); input clk,UpDown; input reset; output reg [3:0] q; reg [3:0] t=4'd0; always@(posedge(clk)) begin if(reset==0) t=4'd0; else if(UpDown == 1) t = t + 1; else t = t - 1; q=t; end endmodule

TEST BENCH for SYNCRONOUS COUNTER 34 Bangalore

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VLSI LAB MANUAL 2010 module Test_updown; reg clk,reset,updown; wire [3:0] q; count my_count (clk,updown,reset,q); initial clk=1'd0; always #5 clk = ~clk; initial begin reset = 0; updown = 1; #5; reset = 1; #160; updown = 0; #160; updown = 1; end endmodule

Experiment 7: ASYNCRONOUS COUNTER 35 Bangalore

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Verilog code for ASYNCRONOUS (RIPPLE)COUNTER module count_ashyn(clk,rst,updown, count); input clk,rst,updown; output reg [3:0] count; always@(posedge(clk),posedge(rst)) begin if(rst == 1) count = 4'd0; else if(clk == 1) if( updown == 1) count = count + 1; else count = count - 1; end endmodule

TEST BENCH for ASYNCRONOUS (RIPPLE)COUNTER 36 Bangalore

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VLSI LAB MANUAL 2010 module test_asyn; reg clk,rst,updown; wire [3:0] count; count_ashyn uut (clk,rst,updown,count); initial clk = 1'd0; always #5 clk = ~clk; initial begin updown = 1; rst = 0; #10; rst = 1; #20; rst=0; #83; rst = 1; #10; rst = 0; updown = 0; #33; rst = 1; end endmodule

Experiment 8: PARALLEL ADDER 37 Bangalore

Mahesh. A.A



Cin 0 0 1 1

A3 1 0 1 0

A2 0 1 0 0

A1 0 1 0 0

A0 1 1 1 1

B3 1 0 1 0

B2 0 0 0 0

B1 0 0 0 1

B0 1 1 0 1

Cout 1 0 1 0

S3 0 1 0 1

S2 0 0 0 1

S1 1 0 0 1

S0 0 0 1 0

Verilog code for FULL ADDER module fulladd (cin,x,y,s,cout); input cin,x,y; output s,cout; assign s = x^y^cin; assign cout =( x & y) | (x & cin) |( y & cin); endmodule

Verilog code for PARALLEL ADDER module adder4 ( carryin,x,y,sum,carryout); input carryin; input [3:0] x,y; output [3:0] sum; output carryout; fulladd stage0 (carryin,x[0],y[0],sum[0],c1); fulladd stage1 (c1,x[1],y[1],sum[1],c2); fulladd stage2 (c2,x[2],y[2],sum[2],c3); fulladd stage3 (c3,x[3],y[3],sum[3],carryout); endmodule

TEST BENCH for PARALLEL ADDER module adder4_t ; 38 Bangalore

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VLSI LAB MANUAL 2010 reg [3:0] x,y; reg carryin; wire [3:0] sum; wire carryout; adder4 a1 ( carryin,x,y,sum,carryout); initial begin $monitor($time,"SUM=%d",sum); x = 4'b0000; y= 4'b0000;carryin = 1'b0; #20 x =4'b1111; y = 4'b1010; #40 x =4'b1011; y =4'b0110; #40 x =4'b1111; y=4'b1111; #50 $finish; end endmodule

Note:

Simulation and synthesis of parallel adder uses a full adder in it’s module . Therefore, In simulation process it is necessary to compile full adder verilog file and parallel adder with test bench. In synthesis it is necessary to read_hdl file of full adder as well as parallel adder

Experiment 9: SERIAL ADDER 39 Bangalore

Mahesh. A.A


VLSI LAB MANUAL 2010 Verilog code for SERIAL ADDER module serial_adder ( A,B, reset, clock, sum); input [7:0] A,B; input reset,clock; output [7:0] sum; reg [3:0] count; reg s,y,Y; wire [7:0] qa,qb,sum; wire run; parameter G=0,H=1; shiftrne shift_A (A,reset,1'b1,1'b0,clock,qa); shiftrne shift_B (B,reset,1'b1,1'b0,clock,qb); shiftrne shift_sum (8'b0,reset,run,s,clock,sum); //adder fsm //output and next state combinational circuit always @(qa or qb or y) case (y) G: begin s = qa[0]^qb[0]; if (qa[0] & qb[0]) Y = H; else Y = G; end H: begin s = qa[0] ~^qb[0]; if (~qa[0] & ~qb[0]) Y =G; else Y = H; end default : Y = G; endcase //sequential block always @(posedge clock) if (reset) y <= G; else y <= Y; 40 Bangalore

Mahesh. A.A


VLSI LAB MANUAL 2010 //control the shifting process always @(posedge clock) if (reset) count = 8; else if (run) count = count - 1; assign run=|count; endmodule

TEST BENCH for SERIAL ADDER module serial_adder_t ; reg [7:0] A,B; reg reset,clock; wire [7:0] sum ; initial clock = 1'b0; always #5 clock =~clock; serial_adder s1 (A,B,reset,clock,sum); initial begin reset = 1'b0;A = 8'b10101010; B = 8'b11111111; #20 reset = 1'b1; #20 reset = 1'b0; #150 reset = 1'b1; A = 8'b11110000 ; B = 8'b11110011; #20 reset = 1'b0; #200 $finish; end initial $monitor ($time, " SUM = %d ", sum); Endmodule

Verilog code for SHIFT REGISTER 41 Bangalore

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VLSI LAB MANUAL 2010 module shiftrne ( R,L,E,w,clock,q); parameter n=8; input [n-1:0] R; input L,E,w,clock; output [n-1:0] q; reg [n-1:0] q; integer k; always @(posedge clock) if (L) q <= R; else if (E) begin for (k=n-1;k>0;k=k-1) q[k-1] <= q[k]; q[n-1] <= w; end endmodule

Note:

Simulation and synthesis of serial adder uses a shift register in it’s module. Therefore, In simulation of Serial adder It is necessary to compile shift register verilog file and serial adder with test bench. In Synthesis of Serial adder it is necessary to read_hdl file for shift register as well as serial adder.

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PART – B

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3) PART B[1]: SCHEMATIC SIMULATION PROCEDURE FOR CREATING THE SCHEMATIC SIMULATION I. Commands to get into Cadence 1. Right Click and open the terminal window 2. Type the following commands as follows and press enter. i) csh ii) source cshrc iii) ls – shows the directories – check for existence of cadence_analog_labs_613.If not found inform the system admin else go to next step iv) cd cadence_analog_labs_613 v) virtuoso & II. Procedure for Schematic simulation using Cadence 1. Now two windows must open i)virtuoso/command interpreter window ii)”Whats New…” 2. Close the 2nd window 3. Use 1st window i.e virtuoso window(CIW) for further processing. i) ii) iii) iv) v)

Create a New Library Create Schematic Cell view. Create the Symbol for schematic Cell view. Create the test Cell view. Analog simulation by spectre

i) Procedure for Creating New Library. a. File –New – Library b. Name : Give name for ur library Ex: VLSILAB c. Enable Attach to an existing technology library, Click OK d. Attach the library to the technology library gpdk180.Click OK ii) Create Schematic Cell view. a. Go to 1st window i.e virtuoso(CIW) b. File-New-Cell view c. Setup the new file form Library: Select the one you a created. Cell : Give the experiment name Ex: Inverter View: Schematic Type: Schematic press OK 44 Bangalore

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VLSI LAB MANUAL 2010 d. Add the required components from the libraries and make the connections. 1. Go to instance fixed menu or use shortcut key “I” from keypad to go instances 2. Click on browse. This opens the library browser 3. Now select the appropriate library for components like Gpdk180 ----------------- nmos, pmos Analog library ---------- Vdd, Gnd, Vcc, Vpulse, Vsin 4. Make the connections by using fixed narrow wire key 5. Click Check and Save button iii) Creating the Symbol for schematic Cell view a. In the schematic window, execute Crate – Cell view – From Cell view The cell view from cell view window appears Check Lib Name, Cell Name, From View name must be schematic Press ok b. Now Symbol generation form appears. Click Ok If No changes required c. A new window with with default symbol is created. d. Edit the symbol if you want to give actual symbol shape else continue. i. Execute Create-Cell view-from cell view ii. Library Name and Cell Name must be same which you have used for schematic. Press OK iii. Check for the position of pin side.Prss OK iv. Edit for the shape by Create-Shape-Choose required options to edit. iv) Creating the new test cell view a. Go to CIW window, Execute File-New-Cell view b. Setup the new file form Library: Select the one you a created. Cell: Cell name must be different from the name used in schematic cell view. Ex: Inverter_test View: Schematic Type: Schematic press OK c. Follow the step 3(ii) d to make the required connections v) Analog simulation by SPECTRE. 45 Bangalore

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VLSI LAB MANUAL 2010 a. In test cell view window Launch – ADE L(Analog Design Environment) b. Execute Setup—Simulation/directory/Host A new window opens c. Set the simulation window to spectre and click ok d. Execute Setup-Model Library. Anew window opens, Check of gpdk.scs as lib and section type as stat then press OK. e. Execute Analysis – Choose. A window opens. f. Select the type and set the specifications and press OK g. Execute Output s—to be plotted – Select on Schematic h. Then Select the INPUT WIRE(Vin ) and OUTPUT WIRE(Vout) from your test Schematic using mouse i. Execute Simulation -- Net list and Run

Experiment 1(a): Inverter Schematic Cell View 46 Bangalore

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Specifications:

nmos Input Pins Output pin

 NM0  W=2u L=.180U & NM1 W=2U L=.180U  Vdd,Vss,Vin,Vbias  Vout

Specifications: Vpulse  V1 = 0 V2 = 1

Vdd

= 1.8

td = 0,tr=tf=1 n, ton= 10n ,T=20n Simulation Settings 47 Bangalore

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VLSI LAB MANUAL 2010 Setup for transient analysis: 1. Stop time = Setup for D.C analysis 1. Component to be selected in schematic is_______for d.c analysis 2. Start = -5 Stop = 5 resp. Setup for A.C analysis 1. Turn on Frequency button 2. In sweep range section – Start ____ stop ______ 3. Select point per decade = _____ Check enables and apply

Expected Waveform: Transient analysis

DC Analysis

Experiment 2(a): Common source Amplifier schematic Cell view 48 Bangalore

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VLSI LAB MANUAL 2010 The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a voltage amplifier. As a transconductance amplifier, the input voltage is seen as modulating the current going to the load. As a voltage amplifier, input voltage modulates the amount of current flowing through the FET, changing the voltage across the output resistance according to Ohm's law. The easiest way to tell if a FET is common source is to examine where the signal enters, and leaves. The remaining terminal is what is known as "common". In this example, the signal enters the gate, and exits the drain. The only terminal remaining is the source. This is a common-source FET circuit.

Specifications:

nmos Pmos Input Pins Output pin

 PM0  W=50u L=1U  NM0 W=10U L01U  Vdd,Vss,Vin,Vbias  Vout

Common source Amplifier schematic test Cellview Specifications: Vsin 

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a.c magnitude d.c voltage offset voltage amplitude frequency

=1 =0 =0 =5m =1K

Vdd = 2.5 Vss = -2.5 Vbias = 2.5



Simulation Settings Setup for transient analysis: 2. Stop time = 5m

Setup for D.C analysis 3. Component to be selected in schematic is Vsin for d.c analysis 4. Start = -5 Stop = 5 resp. Setup for A.C analysis 4. Turn on Frequency button 5. In sweep range section – Start 7 stop – 150 to 100M 6. Select point per decade = 20 Check enables and apply

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VLSI LAB MANUAL 2010 Expected Waveform: Transient analysis

DC Analysis

AC Analysis- Frequency

Experiment 3(a): Common drain amplifier schematic Cell view 51 Bangalore

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VLSI LAB MANUAL 2010 A common-drain amplifier, also known as a source follower, is one of three basic single-stage field effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this circuit the gate terminal of the transistor serves as the input, the source is the output, and the drain is common to both (input and output), hence its name. The analogous bipolar junction transistor circuit is the common-collector amplifier. In addition, this circuit is used to transform impedances. For example, the Thévenin resistance of a combination of a voltage follower driven by a voltage source with high Thévenin resistance is reduced to only the output resistance of the voltage follower, a small resistance. That resistance reduction makes the combination a more ideal voltage source. Conversely, a voltage follower inserted between a small load resistance and a driving stage presents an infinite load to the driving stage, an advantage in coupling a voltage signal to a small load.

Specifications:

nmos Input Pins Output pin

 NM0  W=50u L=1U & NM1 W=10U L=1U  Vdd,Vss,Vin,Vbias  Vout

Common drain amplifier test cellview Specifications: Vsin 

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=1 =0 =0 =5m =1K

Vdd = 2.5 Vss = -2.5 Vbias = 2.5



Simulation Settings Setup for transient analysis: 1. Stop time = 5m Setup for D.C analysis 1. Component to be selected in schematic is Vsin for d.c analysis 2. Start = -5 Stop = 5 resp. Setup for A.C analysis 1. Turn on Frequency button 2. In sweep range section – Start 7 stop – 150 to 100M 3. Select point per decade = 20 Check enables and apply

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VLSI LAB MANUAL 2010 Expected Waveform: Transient analysis

DC Analysis

AC Analysis- Frequency

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VLSI LAB MANUAL 2010 Experiment 4(a): Differential Amplifier schematic Cell view

Specifications:

nmos Pmos Input Pins Output pin Bidrectional pins

 NM0&NM1  W=3u L=1U , NM2,NM3  4.5U L=1U  PM0 & PM1 W=15U L=1U  V1,V2,Idc  Vout  Vdd,Vss

Differential Amplifier schematic test Cellview

Specifications: Vsin  55 Bangalore

Mahesh. A.A

a.c magnitude = 1 amplitude =5m

Vdd Vss

= 2.5 = -2.5 Prepd. By,

Dept. Electronics and Communication

VLSI LAB MANUAL 2010 frequency

=1K

Idc

= d.c.current=30u

Simulation Settings Setup for transient analysis: 3. Stop time = Setup for D.C analysis 5. Component to be selected in schematic is_______for d.c analysis 6. Start = -5 Stop = 5 resp. Setup for A.C analysis 7. Turn on Frequency button 8. In sweep range section – Start ____ stop ______ 9. Select point per decade = _____ Check enables and apply

Expected Waveform:

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VLSI LAB MANUAL 2010 Experiment 5(a) : OPAMP schematic Cell view

\ Specifications:

Diff_Amplifier Cs_amplifier Input Pins Output pin

 From your library  From your library  Vinv,Vnoninv,Id.c,Vdd,Vss  Vout

OPAMP schematic test Cell view

Specifications: Vsin 

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=1 =0 =0 =5m =1K

Vdd Vss Idc

= 2.5 = -2.5 = d.c current=30 u


VLSI LAB MANUAL 2010 Simulation Settings Setup for transient analysis: 4. Stop time = Setup for D.C analysis 7. Component to be selected in schematic is_______for d.c analysis 8. Start = -5 Stop = 5 resp. Setup for A.C analysis 10. Turn on Frequency button 11. In sweep range section – Start ____ stop ______ 12. Select point per decade = _____ Check enables and apply

Expected Waveform:

Experiment 6(a) : R-2R DAC schematic Cell view 58 Bangalore

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Table for component building: Lib Name Cell Name gpdk180 polymer analog lib Idc,gnd My.Library op-amp

Properties R=2K and 1K idc=30u symbol

D0,D1,D2,D3 –Input pins Vout-output pin Vdd and Gnd –Input pins

R-2R DAC Test Cellview

Table for component building: 59 Bangalore

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Lib Name analog lib

Cell Name Vpulse

Vdc,gnd My.Library

R-2R DAC

Properties V0: V1=0V V2=2 V1: V1=0V V2=2 V2: V1=0V V2=2 V3: V1=0V V2=2 Vdd=2 Vss=-2

Total period(T)=10n Pulse width(Ton)=5n Total period(T)=20n Pulse width(Ton)=10n Total period(T)=40n Pulse width(Ton)=20n Total period(T)=80n Pulse width(Ton)=40n

symbol

Simulation Settings Setup for transient analysis: 5. Stop time = Setup for D.C analysis 9. Component to be selected in schematic is_______for d.c analysis 10. Start = -5 Stop = 5 resp. Setup for A.C analysis 13. Turn on Frequency button 14. In sweep range section – Start ____ stop ______ 15. Select point per decade = _____ Check enables and apply

Output Waveform: 60 Bangalore

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PART B[2]: LAYOUT DESIGNING 61 Bangalore

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VLSI LAB MANUAL 2010 I) Layout Design Rules 0A

Minimum NBURIED width 1.0um

0B

Minimum NBURIED space 1.0um

1A

Minimum NWELL width 1.0um

1B

Minimum NWELL space 1.0um

1C

Minimum NBURIED enclosure of NWELL 0.3um

1D

Minimum PWELL width 1.0um

1E

Minimum PWELL space 1.0um

1F

Minimum NBURIED enclosure of PWELL 0.3um

2A

Minimum OXIDE width 0.4um

2B

Minimum OXIDE space 0.3um

2C

Minimum NWELL enclosure of OXIDE 0.5um

2D

Minimum NWELL to OXIDE space 0.5um

3A

Minimum NIMP width 0.4um

3B

Minimum NIMP space 0.4um

3C

Minimum NIMP enclosure of OXIDE 0.2um

3D

Minimum NBURIED enclosure of NIMP 0.6um

4A

Minimum PIMP width 0.4um

4B

Minimum PIMP space 0.4um

4C

Minimum PIMP enclosure of OXIDE 0.2um

4D

Minimum NBURIED enclosure of PIMP 0.6um

4E

PIMP and NIMP cannot overlap

5A

Minimum POLY width 0.18um

5B

Minimum POLY space 0.3um

5C

Minimum POLY extension beyond OXIDE (poly endcap) 0.2um

5D

Minimum OXIDE extensions beyond gate POLY 0.4um

5E

Minimum Poly to OXIDE spacing 0.2um

6A

Minimum and maximum width of CONT 0.2um

6B

Minimum CONT space 0.2um

6C

Minimum OXIDE enclosure of CONT 0.2um 62 Bangalore

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VLSI LAB MANUAL 2010 6D

Minimum POLY enclosure of CONT 0.2um

6E

Minimum POLY to CONT space 0.2um

6F

Minimum NIMP enclosure of CONT 0.2um

6G

Minimum PIMP enclosure of CONT 0.2um

6H

Minimum CONT to Oxide space 0.2um

7A

Minimum METAL1 width 0.3um

7B

Minimum METAL1 space 0.3um

7C

Minimum METAL1 enclosure of CONT 0.1um

8A

Minimum and maximum width of VIA1 0.2um

8B

Minimum VIA1 space 0.3um

8C

Minimum METAL1 enclosure of VIA1 0.1um

9A


9B


9C


10A


10B


10C


11A


11B


11C


11D

Minimum METAL3 enclosure of VIA2 for metal capacitor 0.1um

12A

Minimum CAPMETAL width 0.5um

12B

Minimum METAL2 enclosure of CAPMETAL 0.4um

12C

Minimum CAPMETAL enclosure of VIA2 0.2um

12D

Minimum CAPMETAL enclosure of METAL3 0.3um

13A

Maximum distance from a source/drain OXIDE region to the nearest well tie 10um

14A


14B


14C


15A


15B

Minimum METAL4 space 0.3um 63 Bangalore

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VLSI LAB MANUAL 2010 15C


16A


16B


16C


17A


17B


17C


18A


18B


18C


19A


19B


19C


20A

Minimum BONDPAD width 45.0um

20B

Minimum BONDPAD space 10.0um

20C

Minimum and Maximum METAL1 enclosure BONDPAD 3.0um

20D


20E


20F


20G


20H


Some of the important design rules mentioned above are pictorially represented in next page.

(p.t.o) N WELL RULE

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OXIDE RULE

N imp/ P imp RULES

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Poly RULE

PMOS LAYOUT: 66 Bangalore

(W/L) = (2um / .18 um )

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The PMOS is designed with respect to the design rules mentioned. The PMOS is designed with a respect to the W/L ratio. W



Width of channel Nimp

L



Width of POLY1

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VLSI LAB MANUAL 2010 Layout of PMOS: ( W/L ) = (2um/.18um)

NMOS LAYOUT : 68 Bangalore

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(W/L) = (2um / .18 um ) Prepd. By, Dept. Electronics and Communication


LAYOUT OF NMOS : (W/L) = ( 2um/.18um)

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VLSI LAB MANUAL 2010 II ) LAYOUT GENERATION & TESTING PROCEDURE 1. Open the Inverter schematic window 2. Launch → Lay out XL 3. A window opens, Enable create New option, A New – cell view form open

set the cell Name: Inverter ( Same as Schematic ) View Name : Layout and click OK. A LSW [ Layout schematic window] & blank Layout window opens. 4. In Layout window, Execute Connectivity – Generate – All from source. In the layout editor window, A Generate Layout form appears. In this form enable Labels options & Click OK. 5. Now, we can view the components and Area of silicon [boundary]. The Area defines that the required layout can be fitted in to that. There for try to restrict to this area. NOTE: As a beginner extend the height of area by maximum of 2 units. 6. Stretch the area by using stretch Key from edit window.

7. Move the components in to specified area and arrange them at required positions properly. 8. Press shift – F to observe the internal view of the NMOS & PMOS. 9. Now Zoom the layout editor window and align the NMOS & PMOS exactly. [That is poly

of both MOS must match to avoid the DRC errors]. 10. Make the required connections by selecting the required material from LSW window like poly, metal then create the required shapes by executing Create → Shape → Path / Rectangle 11. Once the required connection are made, the next step is to connect the required overlapping materials by using corresponding connectors (via)s 71 Bangalore

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VLSI LAB MANUAL 2010 Ex: The input ‘A’ in inverter layout Input A - Contact made up of metal 1 Gate terminal shorted is poly. As input A is placed on poly, now these two different layers are connected by using corresponding connectors. That is M1 – POLY1 Via There for Execute Create – Via In the Vias form, select the corresponding connector required and click Hide and the place on required position in layout by double click. 12. Finally save the layout.

13. Testing [Running DRC, ERC, LVS & RCX]

A) Running DRC( Design Rule Checker)

i)

Execute Assura – Run DRC.

The DRC form opens Check: ii)

Library: ?

Cell: ?

View: ? [Layout].

This should be same what you have set iii)

Technology – gpdk 180. Then click OK.

iv)

A progress form appears.[Don’t click on OK]

v)

When DRC finishes, a dialog box appears asking you if you want to view your DRC results, and then click yes to view the results of this form.

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VLSI LAB MANUAL 2010 vi)

If any DRC errors exist, a Error Layer window [ELW] appears. Open ELW window and rectify the errors by selecting the errors one by one.

vii)

Then follow step (i) to (v) mentioned above unit you get a message as “ No DRC errors found” then clck on close to terminate the DRC run.

B) Running LVS( Layout Vs Schematics) . i)

Assura – LVS in Layout window

ii)

A Assura – Run LVS window opens. Check: →Schematic Design Source Lib:

Cell:

View:

→Layout Design Source Lib:

Cell:

View:

iii)

These should be have Schematic & Layout to be compared CLICK OK. The LVS begins and progress. Form appears.

iv)

If schematic & Layout matches completely, you will get the form displaying “Schematic and Layout Match” If Not matching, a form informs LVS completed successfully and asks if you want view the results of this run. CLICK Yes in the form.

v)

The LVS debug form opens indicating the mismatches and you need to correct all these mismatches and Re – run the LVS.

C) Running RCX. i)

Assura – Run RCX.

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VLSI LAB MANUAL 2010 ii)

Assura RCX form opens. Set the output type under setup tab as extracted View. [ It may be preset]. CLICK OK. Under filtering tab of the form, Enter Power Nets as Vdd!, Vss! And Enter ground nets as gnd! Then Click OK for the form.

iii)

RCX progress form appears, wait until it completes the process.

iv)

Whwn RXC complete, a dialog box appears, informs you that Assura RCX run Completed Successfully.

v)

Go to CIW (Virtuso window) File – open – av- extracted view form the corresponding library. Then, the av-extracted view window opens with parasitic components (RC). Observe the view by zooming

III) Creating Configuration View i) Creating Config View a. Go to CIW window, Execute File-New-Cell view b. Setup the new file form Library: Select the one you a created. Cell: Cell name must be different from the name used in schematic cell view. Ex: Inverter_test View: Config Type: Schematic press OK A Hierarchy Editor window and New Configuration Form opens c. In the New Configuration form, Click on Use Templates present at the bottom of form. A use Templates window opens. d. In Use Template form set Name: SPECTRE by scroll down button, then Click OK. e. Now,In the New Configuration window Change Top Cell View: Schematics and Set the Library Link: BLANK, Then CLICK OK in New Configuration window. Now, Hierarchy Editor Window Opens. f. In Hierarchy Editor Window, Press Table View tab and check cell building. 74 Bangalore

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VLSI LAB MANUAL 2010 g. h. i. j.

In Hierarchy Editor Window, Press Tree View tab and check occurances. Press Recompute the Hierarchy icon Save the current configuration. Close the hierchy Editor window. Execute File – Close Window

IV) RUNNING circuit without parasites. a. Go to CIW window and open (Inverter_test) Config view, Top cell view form opens. b. Enable Yes and Yes in Top Cell View form c. Launch – ADE L(Analog Design Environment) d. Execute Setup—Simulation/directory/Host A new window opens e. Set the simulation window to spectre and click ok f. Execute Setup-Model Library. Anew window opens, Check of gpdk.scs as lib and section type as stat then press OK. g. Execute Analysis – Choose. A window opens. h. Select the type and set the specifications and press OK i. Execute Output s—to be plotted – Select on Schematic j. Then Select the INPUT WIRE(Vin ) and OUTPUT WIRE(Vout) from your test Schematic using mouse k. Execute Simulation -- Net list and Run

Propagation Delay Calculation After completing STEP (IV) ,A waveform window will be opened. a. In the waveform window execute Tool – Calculator. A calculator window appears b. Click on special function tab. A window with different functions open, In this select delay. c. A addition form for calculation will be present to select and the parameters for delay calculation. i. Place the curser in signal1 text box, Enable Wave button and enable the input Net(Vin) (Line) in the schematic window. ii. Repeat above step for Signal 2. iii. Set threshold values w.r.t experiment ( Ex: For Inverter ; Threshold Value 1 & Threshold Value 2 to 0.9,this directs the calculator to calculate the delay at 50% i.e at 0.9 volts( 1.8V/2) iv. Click OK and observe the expression created in the calculator buffer. d. Click on the Evaluate the buffer icon to perform the calculation and note down the valued returned after execution. 75 Bangalore

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VLSI LAB MANUAL 2010 e. Close the calculator window.

IV) RUNNING circuit with parasites. a. Open the same hierarchy Editor window which is already set for config. b. Select the TREE VIEW tab,this will show the design hierarchy in tree format. c. CLICK right button on IO (lib name Inverter schematic) in TREE VIEW and Select set instances view as av_extracted view. d. Press Recompute the Hierarchy icon, the configuration is now updated from schematic to av_extracted view e. Then,go output waveform window( analog design environment) and click Netlist and RUN f. Observe the waveform with additional nets and parameters. g. Calculate the delay again and match with the previous one.

Now you can conclude how much delay is introduced by parasites by comparing delay with and without parasites and based on this we need to optimize the parasitic effect and reduce the delay due to parasites. This finally leads to an optimized layout

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LSW What is LSW? It is a layout Vs Schematic window which consists of different layers used for layout. The layers to drawn or traced has to be selected from the LSW window and the required type of shape has to be created by using the Create  Shape Select the required shapes. The Shapes may be a Rectangle, Circle, Path so on. Rectangle: This shape is chosen when the shape to be drawn is rectangular and but the size is not defined. Path: This shape is chosen when the path to be drawn is with predefined with. The drawn shapes must follow the design rules.

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Experiment 1(b): Inverter layout

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Experiment 2(b): Common Source layout 79 Bangalore

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Experiment 3(b): Common Drain layout

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Experiment 4(b): Differential Amplifier layout

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Experiment 5(b): Operational Amplifier layout 82 Bangalore

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4) VLSI Questions 84 Bangalore

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Why don’t we use just one NMOS or PMOS transistor as a transmission gate? Because we can't get full voltage swing with only NMOS or PMOS .We have to use both of them together for that purpose. Why don’t we use just one NMOS or PMOS transistor as a transmission gate? nmos passes a good 0 and a degraded 1 , whereas pmos passes a good 1 and bad 0. for pass transistor, both voltage levels need to be passed and hence both nmos and pmos need to be used. What are set up time & hold time constraints? What do they signify? Setup time: Time before the active clock edge of the flip-flop, the input should be stable. If the signal changes state during this interval, the output of that flip-flop cannot be predictable (called metastable). Hold Time: The after the active clock edge of the flip-flop, the input should be stable. If the signal changes during this interval, the output of that flip-flop cannot be predictable (called metastable). Explain Clock Skew?

clock skew is the time difference between the arrival of active clock edge to different flip-flops’ of the same chip. Why is not NAND gate preferred over NOR gate for fabrication? NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate. Additionally, the gate-leakage in NAND structures is much lower. What is Body Effect? In general multiple MOS devices are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. However while connecting the devices serially this may result in an increase in source-to-substrate voltage as we proceed vertically along the series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1. Why is the substrate in NMOS connected to Ground and in PMOS to VDD? we try to reverse bias not the channel and the substrate but we try to maintain the drain, source junctions reverse biased with respect to the substrate so that we don’t loose our current into the substrate. What is the fundamental difference between a MOSFET and BJT ? In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) In BJT, we see current due to both the carriers.. electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device In CMOS technology, in digital design, why do we design the size of pmos to be higher than the nmos. What determines the size of pmos wrt nmos. Though this is a simple question try to list all the reasons possible? In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos helps in pulling down the output to ground PMOS helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node. If we have a larger PMOS than there will be more carriers to charge the node quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise and fall times for the output node. Why PMOS and NMOS are sized equally in a Transmission Gates?

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Mahesh. A.A


VLSI LAB MANUAL 2010 In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's the reason why we need not size them like in CMOS. In CMOS design we have NMOS and PMOS competing which is the reason we try to size them proportional to their mobility. What happens when the PMOS and NMOS are interchanged with one another in an inverter? If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1 O/P will be degraded 1 Similarly degraded 0 Why are pMOS transistor networks generally used to produce high signals, while nMOS networks are used to product low signals? This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high and pMOS can’t drive full '0' or low. The maximum voltage level in nMOS and minimum voltage level in pMOS are limited by threshold voltage. Both nMOS and pMOS do not give rail to rail swing. What’s the difference between Testing & Verification? What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up? A latch up is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component, triggering a parasitic structure(The parasitic structure is usually equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning of the part. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical over stress - EOS What is slack? The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a particular path. Slack may be +ve or -ve. Difference between Synchronous and Asynchronous reset. What is DRC ?What is LVS ? what are the differences between SIMULATION and SYNTHESIS ? Simulation <= verify your design. synthesis <= Check for your timing Simulation is used to verify the functionality of the circuit.. a)Functional Simulation: study of ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup, hold and other timing requirements of devices like flip flops are met. Synthesis: One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology. Basically the synthesis tools convert the design description into equations or components.

FPGA vs ASIC Definitions FPGA: A Field-Programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions.

86 Bangalore

Mahesh. A.A


VLSI LAB MANUAL 2010 ASIC: An application-specific integrated circuit (ASIC) is an integrated circuit designed for a particular use, rather than intended for general-purpose use. Processors, RAM, ROM, etc are examples of ASICs. Speed ASIC rules out FPGA in terms of speed. As ASIC are designed for a specific application they can be optimized to maximum, hence we can have high speed in ASIC designs. ASIC can have high speed clocks. Cost FPGAs are cost effective for small applications. But when it comes to complex and large volume designs (like 32-bit processors) ASIC products are cheaper. Size/Area FPGA are contains lots of LUTs, and routing channels which are connected via bit streams(program). As they are made for general purpose and because of re-usability. They are ingeneral larger designs than corresponding ASIC design. For example, LUT gives you both registered and non-register output, but if we require only non-registered output, then it’s a waste of having an extra circuitry. In this way ASIC will be smaller in size. Power FPGA designs consume more power than ASIC designs. As explained above the unwanted circuitry results wastage of power. FPGA won’t allow us to have better power optimization. When it comes to ASIC designs we can optimize them to the fullest. Time to Market FPGA designs will still take less time, as the design cycle is small when compared to that of ASIC designs. No need of layouts, masks or other back-end processes. It’s very simple: Specifications -HDL + simulations -- Synthesis -- Place and Route (along with static-analysis) -- Dump code onto FPGA and Verify. When it comes to ASIC we have to do floor planning and also advanced verification. The FPGA design flow eliminates the complex and time-consuming floor planning, place and route, timing analysis, and mask / re-spin stages of the project since the design logic is already synthesized to be placed onto an already verified, characterized FPGA device.

Type of Design ASIC can have mixed-signal designs, or only analog designs. But it is not possible to design those using FPGA chips.

87 Bangalore

Mahesh. A.A


VLSI LAB MANUAL 2010 Customization ASIC has the upper hand when comes to the customization. The device can be fully customized as ASICs will be designed according to a given specification. Just imagine implementing a 32-bit processor on a FPGA! Prototyping Because of re-usability of FPGAs, they are used as ASIC prototypes. ASIC design HDL code is first dumped onto a FPGA and tested for accurate results. Once the design is error free then it is taken for further steps. It’s clear that FPGA may be needed for designing an ASIC. Non Recurring Engineering/Expenses NRE refers to the one-time cost of researching, designing, and testing a new product, which is generally associated with ASICs. No such thing is associated with FPGA. Hence FPGA designs are cost effective. Simpler Design Cycle Due to software that handles much of the routing, placement, and timing, FPGA designs have smaller designed cycle than ASICs. More Predictable Project Cycle Due to elimination of potential re-spins, wafer capacities, etc. FPGA designs have better project cycle. Tools Tools which are used for FPGA designs are relatively cheaper than ASIC designs. ReUsability A single FPGA can be used for various applications, by simply reprogramming it (dumping new HDL code). By definition ASIC are application specific cannot be reused.

88 Bangalore

Mahesh. A.A


vlsilab

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