Chapter 4 Solutions for Reinforced Concrete Mechanics and Design 6th edition
Delay & Delay AnalysisFull description
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VLSI DESIGN BOOK for final year Engg studentsFull description
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1. Delay Definitions
t pd r : rising propagation delay – From input to rising output crossing VDD/2 t pd f : falling propagation delay – From input to falling output crossing VDD/2 t pd : average propagation delay – tpd = (tpdr + tpdf )/2 t r : rise time – From output crossing 0.2 VDD to 0.8 VDD t f : fall time – From output crossing 0.8 VDD to 0.2 VDD
5: DC an d Tr an s i en t Res p o n s e
CMOS VLSI Design
4th Ed.
2
1. Delay Definitions
t cdr : rising contamination delay – From input to rising output crossing VDD/2
t cdf : falling contamination delay – From input to falling output crossing VDD/2
t cd : average contamination delay – tcd = (tcdr + tcdf )/2
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
3
Arrival time
Arrival time is the latest time at which each node in a block of logic will switch
The slack is the difference between the required and arrival times.
Positive slack means that the circuit meets timing.
Negative slack means that the circuit is not fast enough.
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
4
Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically – Uses more accurate I-V models too!
But simulations take time to write, may hide insight 2.0
1.5
1.0 (V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
800p
1n
t(s)
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
5
Delay Estimation
We would like to be able to easily estimate delay – Not as accurate as simulation – But easier to ask “What if?” The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay – C = total capacitance on output node – Use effective resistance R – So that tpd = RC Characterize transistors by finding their effective R – Depends on average current as gate switches
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
6
Effective Resistance
Shockley models have limited value – Not accurate enough for modern transistors – Too complicated for much hand analysis
Simplification: treat transistor as resistor – Replace Ids(Vds, Vgs) with effective resistance R • Ids = Vds/R – R averaged across switching of digital gate
Too inaccurate to predict current at any given time – But good enough to predict RC delay
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
7
3. RC Delay Model
Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width d
g
d k s
s kC
R/k
kC 2R/k
g
g kC
kC
d k
g
kC
s
s 5: DC and Transient Response
kC
d CMOS VLSI Design
4th Ed.
8
RC Values
Capacitance – C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm – Gradually decline to 1 fF/ mm in nanometer techs.
Resistance – R 6 KW*mm in 0.6 mm process – Improves with shorter channel lengths
Unit transistors – May refer to minimum contacted device (4/2 l) – Or maybe 1 mm wide device – Doesn’t matter as long as you are consistent
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
9
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter 2C R
A
2 Y
2
1
1
2C
2C
2C
2C
Y R
C
R C
C C
C
d = 6RC 5: DC and Transient Response
CMOS VLSI Design
4th Ed.
10
Delay Model Comparison
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
11
Example: 3-input NAND
Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
2
2
2 3 3 3
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
12
3-input NAND Caps
Annotate the 3-input NAND gate with gate and diffusion capacitance. 2C 2 2
2C 2C
2C 2 2
2C
2C 2 2
2C
2C 2C 9C
5C 5C 5C
5: DC and Transient Response
3C 3C 3C
CMOS VLSI Design
3 3 3 3 3 3
3C 3C 3C 3C 3C
3C
4th Ed.
13
Elmore Delay
ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder
t pd
R
i to source
C i
nodes i
R1C1 R1 R2 C2 ... R1 R2 ... R N C N R1
R2
R3
C1
C2
5: DC and Transient Response
RN C3
CMOS VLSI Design
4th Ed.
CN
14
Example: 3-input NAND
Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates. 2
2
2 3 3 n1
h copies
3
t pdr 9 5hC R 3C R 3C R
Delay has two parts – Parasitic delay • 15 or 12 RC • Independent of load – Effort delay • 5h RC • Proportional to load capacitance
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
16
Contamination Delay
Best-case (contamination) delay can be substantially less than propagation delay.
Ex: If all three inputs fall simultaneously 2
2
2 3 3 n1 3
Y 9C n2 3C
5hC
3C
R 5 tcdr 9 5h C 3 h RC 3 3
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
17
Diffusion Capacitance
We assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact – Reduces output capacitance by 2C – Merged uncontacted diffusion might help too 2C
2C
Shared Contacted Diffusion
Isolated Contacted Diffusion
Merged Uncontacted Diffusion
2
2
2 3 3
3C 3C 3C
5: DC and Transient Response
CMOS VLSI Design
3
4th Ed.
7C 3C 3C
18
Isolated/Shared/Merged Diffusion
Shared contacted diffusion can reduce the diffusion capacitance
Un-contacted diffusion nodes can reduce more capacitance
Isolated 5: DC and Transient Response
Merged
Shared CMOS VLSI Design
4th Ed.
19
Layout Comparison
Which layout is better?
VDD
A
VDD
B
A
Y
GND 5: DC and Transient Response
B
Y
GND CMOS VLSI Design
4th Ed.
20
4. Linear delay models
The normalized delay of a gate: d = f + p – p is the parasitic delay – f is the effort delay: f = gh – g is logical effort – h is electrical effort (fanout): h = Cout/Cin
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
21
Logical Effort
Logical Effort is defined as the ratio of the input capacitance of the gate to the input capacitance of an inverter that can deliver the same output current. Logical effort of common gates Gate type
Number of Inputs 1
2
3
4
n
NAND
4/3
5/3
6/3
(n+2)/3
NOR
5/3
7/3
9/3
(2n+1)/3
2
2
2
2
Inverter
Tristate, multiplexer
1
2
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
22
Parasitic Delay
The parasitic delay of a gate is the delay of the gate when it drives zero load Parasitic delay of common gates Gate type
Number of Inputs 1
2
3
4
n
NAND
2
3
4
n
NOR
2
3
4
n
4
6
8
2n
Inverter
Tristate, multiplexer
1
2
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
23
Parasitic Delay
Parasitic Delay for n-input NAND gate
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
24
Example
Use the linear delay model to estimate the delay of the fanout-of-4 (FO4) inverter. Assume the inverter is constructed in a 65 nm process with = 3 ps.
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
25
Summary of logical Effort
5: DC and Transient Response
CMOS VLSI Design
4th Ed.
26
Review 1.
What are tpdr , tpdf , tf , tr , tcdr , tcdf ?
2.
Calculate arrive time of the following circuit:
20 10 30
40
30 40
3.
Explain the delay estimation of a fanout-of-1 inverter (slide 14)
4.
Explain the tpdr and tpdf delay estimation of 3-input NAND driving h identical gates (slide 19).
