UVM Interview Questions Q1: What is UVM? What is the advantage of UVM? Ans: UVM (Universal Verifcation Methodology) is a standardized st andardized methodology methodology or veriying the both complex & simple digital design in simple way. UVM eat!res" irst methodology & second collection o class libraries or #!tomation $e!sability $e!sability thro!gh testbench %l!g & %lay o verifcation %s 'eneric estbench evelopment Vendor & *im!lator ndependent *mart estbench estbench i.e. generate legal stim!l!s as rom pre+planned coverage plan *!pport ,V -,overage riven Verifcation *!pport ,$V -,onstraint $andom Verifcation UVM standardized !nder the #ccellera *ystem nitiative $egister modeling Q2: UVM derived from which language? Ans: ere is the detailed connection between *V/ UVM/ 0VM and other methodologies. Q3 What is the di!erence "etween uvm#com$onent and uvm#o"%ect? &' We alread( have uvm#o"%ect) wh( do we need uvm#com$onent which is actuall( derived class of uvm#o"%ect? Ans: !vm1component" 2!asi *tatic 3ntity (ater b!ild phase it is available thro!gho!t the sim!lation) #lways tied to a given hardware(U nterace) 0r a 4M port aving phasing mechanism or control the behavior o sim!lation ,onfg!ration ,omponent opology !vm1ob5ect" ynamic 3ntity (create when needed/ transer rom one component to other & then dereerence) 6ot tied to a given hardware or any 4M port 6ot phasing mechanism
Q*: Wh( $hasing is used? What are the di!erent $hases in uvm? Ans: UVM %hases is !sed to control the behavior o sim!lation in a systematic way & exec!te in a se7!ential ordered to avoid race condition. his co!ld also be done in system verilog b!t man!ally.
4ist o UVM %hases" b!id1phase connect1phase end1o1elaboration1phase start1o1sim!lation1phase r!n 1phase (tas8) *!b %hases o $eset %hase" pre1reset1phase reset1phase post1reset1phase pre1confg!re1phase confg!re1phase post1confg!re1phase pre1main1phase main1phase post1main1phase pre1sh!tdown1phase sh!tdown1phase post1sh!tdown1phase extract1phase chec81phase report1phase 9elow fg!re ma8es it more clear
Q+: Which uvm $hase is to$ , down ) "ottom - u$ . $arallel? Ans" 0nly b!ild phase is a top+down & other phases are bottom+!p except r!n phase which is parallel. he b!ild phase wor8s top+down since the testbench hierarchy may be confg!re so we need to b!ild the branches beore leas Q/: Wh( "uild $hase is to$ - down . connect $hase is "ottom - u$? Ans: he connect phase is intended to be !sed or ma8ing 4M connections between components/ which is why it occ!r ater b!ild phase. t wor8 bottom+!p so that its got the correct implementation all the way !p the design hierarchy/ i wor8ed top+down this wo!ld be not possible Q0: Which $hase is function . which $hase is tas? Ans: 0nly r!n phase is a tas8 (time cons!ming phase) & other phases are !nctions (non+bloc8ing) Q: ow uvm $hases initiate? Ans: UVM phases initiate by calling r!n1test(:test;<) in top mod!le. =hen r!n1test() method call/ it frst create the ob5ect o test top & then call all phases. Q0: ow test cases run from simulation command line?
Ans: n top mod!le write r!n1test()> i.e. on?t give anything in arg!ment. hen in command line " @UVM13*6#M3Atestname Q: 4i!erence "etween module . class "ased 56? Ans: # mod!le is a static ob5ect present always d!ring o the sim!lation. # ,lass is a dynamic ob5ect beca!se they can come and go d!ring the lie time o sim!lation. Q7: What is uvm#con8g#d" ? What is di!erence "etween uvm#con8g#d" . uvm#resource#d"? Ans: !vm1confg1db is a parameterized class !sed or confg!ration o diBerent type o parameter into the !vm database/ *o that it can be !sed by any component in the lower level o hierarchy. !vm1confg1db is a convenience layer b!ilt on top o !vm1reso!rce1db/ b!t that convenience is very important. n partic!lar/ !vm1reso!rce1db !ses a Clast write winsC approach. he !vm1confg1db/ on the other hand/ loo8s at where things are in the hierarchy !p thro!gh end1o1elaboration/ so Cparent wins.C 0nce yo! start start1o1sim!lation/ the confg1db becomes Clast write wins.C #ll o the !nctions in !vm1confg1dbD() are static/ so they m!st be called !sing the "" operator t is extended rom the !vm1reso!rce1dbD()/ so it is child class o !vm1reso!rce1dbD() Q19:What is uvm#transaction) uvm#se#item) uvm#o"%ect) uvm#com$onent? Q11:What is the advantage of ;uvm#com$onent#utils<= and ;uvm#o"%ect#utils<= ? Q12:What is the di!erence "etween ;uvm#do and ;uvm#ran#send? di! "etween uvm#transaction and uvm#se#item? Q13:What is the di!erence "etween uvm #virtual#seuencer and uvm#seuencer ? Q1*:What are the "ene8ts of using UVM? Q1+:What is su$er e(word? What is the need of calling su$er"uild<= and su$erconnect<=? Q1/:Is uvm is inde$endent of s(stemverilog ? Q10:>an we have user de8ned $hase in UVM? Q1:What is $#seuencer ? Q17:What is uvm 'A model ? wh( it is reuired ? Q29:What is the di!erence "etween new<= and create? Q21:What is anal(sis $ort? Q22:What is 5M @I@&? Q23:ow seuence starts? Q2*:What is the di!erence "etween UVM 'A model "acdoor writeread and front door writeread ?
Q2+:What is o"%ection? Q2/:What is the advantage of ;uvm#$re#"od( and ;uvm#$ost#"od( ? Q20:What is the di!erence "etween Active mode and Bassive mode? Q2:What is the di!erence "etween co$( and clone? Q27:What is UVM factor(? Q39:What are the t($es of seuencer? CD$lain each? Q31:What are the di!erent $hases of uvm#com$onent? CD$lain each? Q32:ow set#con8g#E wors? Q33:hat are the advantages of uvm 'A model ? Q3*:What is the di!erent "etween set#con8g#E and uvm#con8g#d" ? Q3+:What are the di!erent override t($es? Q3/:What is virtual seuence and virtual seuencer? Q30:CD$lain end of simulation in UVM? Q3:ow to declare multi$le im$orts? Q37:What is s(m"olic re$resentation of $ort) eD$ort and anal(sis $ort? Q*9:What is the di!erence in usage of F8nish and glo"al sto$ reuest in UVM? Q*1:Wh( we need to register class with uvm factor(? Q*2:can we use set#con8g and get#con8g in seuence ? Q*3:What is uvm#heart"eat ? Q**:how to access 4U5 signal in uvm#com$onentuvm#o"%ect ?
#9 nterview 2!estions
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ow #9 is pipelined architect!reE =hat is the size o max data can be transerred in single transerE 3xplain ;8 bo!ndary concept in #9E 08ay response is single cycleE b!t errorIsplitIretry is two cycle/ whyE 3xplain the concept o two cycle responseE =hat i the slave gets the address o!t o rangeE ow to connect m!ltiple slaves to single masterE 3xplain the ro!nd robin arbitration conceptE 3xplain the split+retry conceptE =hat is the diBerence between $3#P and $3#P10U signalsE =hat is the slave response or 9U*P transerE =hat is the diBerence between =$#%H and 6,$HE ow to terminate the 6,$ type transerE =hat is diBerence between 9U$* and 9eatE ow to calc!late the size o the b!rstE s $3#P is np!t or o!tp!t toIrom the slaveE =hat is align and !n+align conceptE 3xplain wrapping calc!lationE s early b!rst termination is done by *laveI#rbiterE 3xplain the 40,Q3 transerE =hat is dea!lt MasterE
FF. FG.
=hat is little+endian and big+endianE ow slave will detects the end o 6,$ type b!rst transerE
#R nterview 2!estions
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ow #R is diBerent rom #9E 3xplain the concept o #R HQ9 bo!ndary conditionE 3xplain the valid ready handsha8e in #RE 3xplain the channel conceptE 3xplain the o!t+o+order conceptE =hat is fxed b!rst typeE 3xplain the #R response typesE
G&> Veri8cation Interview Questions ;. =hat is the diBerence between *0, and % VerifcationE F. =rite a bloc8 diagram o *0, architect!reE G. =hat is the target o verifcation in *0, verifcationE H. s coverage is considered in *0, VerifcationE J. =hat are the ma5or components in *0, architect!reE K. =hat are the challenges o *0, verifcationE
AGI> Veri8cation Interview Questions ;.=hat is the diBerence between *0, and % VerifcationE F=hat is the m!lti cloc8 domain designE ,onsider the simple memory model and explain the possible Verifcation scenariosE =hen will yo! consider that verifcation is doneE =hat is the diBerence between % and V%E =hich is best among % level and *0, level verifcationE ow important is code reviewsE
Q :What is the di!erence "etween V4 and Verilog? Ans:!ndamentally spea8ing/ not a lot. Po! can prod!ce rob!st designs and comprehensive test environments with both lang!ages/ or both #*, and %'#. owever/ the two lang!ages approach the tas8 rom diBerent directions> V4/ intended as a specifcation lang!age/ is very exact in its n at!re and hence very verbose. Verilog/ intended as a sim!lation lang!age/ it m!ch closer to , in style/ in
that it is terse and elegant to write b!t re7!ires m!ch more care to avoid nasty b!gs. V4 doesn?t let yo! get away with m!ch> Verilog ass!mes that whatever yo! wrote was exactly what yo! intended to write. yo! get a V4 architect!re to compile/ it?s probably going to approximate to the !nction yo! wanted. or Verilog/ s!ccess!l compilation merely indicates that the syntax r!les were met/ nothing more. V4 has some eat!res that ma8e it good or system+level modeling/ whereas Verilog is m!ch better than V4 at gate+level sim!lation. =hat is latch !p in ,M0* design and ways to prevent itE # %roblem which is inherent in the p+well and n+well processes is d!e to relatively large n!mber o 5!nctions which are ormed in these str!ct!res/ the conse7!ent presence o parasitic diodes and transistors. 4atch+!p is a condition in which the parasitic components give rise to the 3stablishment o low resistance cond!cting path between V and V** with isastro!s res!lts 4atch+!p may be ind!ced by glitches on the s!pply rails or by incident radiation. 4atch+!p pertains to a ail!re mechanism wherein a parasitic thyristor (s!ch as a parasitic silicon controlled rectifer/ or *,$) is inadvertently created within a circ!it/ ca!sing a high amo!nt o c!rrent to contin!o!sly Sow thro!gh it once it is accidentally triggered or t!rned on. epending on the circ!its involved/ the amo!nt o c!rrent Sow prod!ced by this mechanism can be large eno!gh to res!lt in permanent destr!ction o the device d!e to electrical overstress (30*). %reventions or 4atch+Up by adding tap wells/ or example in an nverter or 6M0* add 6@ tap in n+well and connect it to Vdd/ and or %M0* add %@ tap in p+s!bstrate and connect it to Vss. an increase in s!bstrate doping levels with a conse7!ent drop in the val!e o $s. red!cing $p by control o abrication parameters and by ens!ring a low contact resistance to Vss. and the other is by introd!cing o g!ard rings..... 4atch!p in 9!l8 ,M0* # byprod!ct o the 9!l8 ,M0* str!ct!re is a pair o parasitic bipolar transistors. he collector o each 9T is connected to the base o the other transistor in a positive eedbac8 str!ct!re. # phenomenon called latch!p can occ!r when (;) both 9T?s cond!ct/ creating a low resistance path between Vdd and '6 and (F) the prod!ct o the gains o the two transistors in the eedbac8 loop/ b; x bF/ is greater than one. he res!lt o latch!p is at the minim!m a circ!it mal!nction/ and in the worst case/ the destr!ction o the device.
parasitic1transitor1in1b!l81cmos ,ross section o parasitic transistors in 9!l8 ,M0* parasitic1transitor1in1b!l81cmos1e7!ivalent1circ!it 37!ivalent ,irc!it 4atch!p may begin when Vo!t drops below '6 d!e to a noise spi8e or an improper circ!it hoo8!p (Vo!t is the base o the lateral 6%6 2F). s!cient c!rrent Sows thro!gh $s!b to t!rn on 2F ( $s!b O.L V )/ this will draw c!rrent thro!gh $well. the voltage drop across $well is high eno!gh/ 2; will also t!rn on/ and a sel+ s!staining low resistance path between the power rails is ormed. the gains are s!ch that b; x bF ;/ latch!p may occ!r. 0nce latch!p has beg!n/ the only way to stop it is to red!ce the c!rrent below a critical level/ !s!ally by removing power rom the circ!it. he most li8ely place or latch!p to occ!r is in pad drivers/ where large voltage transients and large c!rrents are present. %reventing latch!p abIesign #pproaches" $ed!ce the gain prod!ct b; x b; move n+well and n@ so!rceIdrain arther apart increases width o the base o 2F and red!ces gain betaF also red!ces circ!it density b!ried n@ layer in well red!ces gain o 2; F. $ed!ce the well and s!bstrate resistances/ prod!cing lower voltage drops W higher s!bstrate doping level red!ces $s!b W red!ce $well by ma8ing low resistance contact to '6 W g!ard rings aro!nd p+ andIor n+well/ with re7!ent contacts to the rings/ red!ces the parasitic resistances. cmos1transitor1with1g!ard1rings ,M0* transistors with g!ard rings *ystems #pproaches" Ma8e s!re power s!pplies are oB beore pl!gging a board. # Chot pl!g inC o an !npowered circ!it board or mod!le may ca!se signal pins to see s!rge voltages greater than O.L V higher than Vdd/ which rises more slowly to is pea8 val!e. =hen the chip comes !p to !ll power/ sections o it co!ld be latched. ,are!lly protect electrostatic protection devices associated with I0 pads with g!ard rings. 3lectrostatic discharge can trigger latch!p. 3* en ters the circ!it
thro!gh an I0 pad/ where it is clamped to one o the rails by the 3* protection circ!it. evices in the protection circ!it can in5ect minority carriers in the s!bstrate or well/ potentially triggering latch!p. $adiation/ incl!ding x+rays/ cosmic/ or alpha rays/ can generate electron+hole pairs as they penetrate the chip. hese carriers can contrib!te to well or s!bstrate c!rrents. *!dden transients on the power or gro!nd b!s/ which may occ!r i large n!mbers o transistors switch sim!ltaneo!sly/ can drive the circ!it into latch!p. =hether this is possible sho!ld be chec8ed thro!gh sim!lation.