DIGITAL FUNDAMENTALS Ninth Edition
Thomas l. Floyd
-PEARSON
Prentice Hall
Pearson Education Intema tional
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Prentice
Hall
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Preface Welcome 10 Digital FUlIlfalllellfais, Nimh Editioll . A strong foundation in the core funda-
menials of digital technology is vilal to anyone pursuing a career in lhis exciting. fast-paced industry. This lext is carefully organized 10 include up-to-date coverage of topics th m can be covered in their entirety, used in a condensed format. or omitled ahogctllcr. depending upon the course emphasis. The lopics in this text are covered inlhe same clear, straightforward, and well-illustrated formai lhat has been so successful in the previous editions of Digital FlIIu/alllell1a/s. Many topics have been strengthened or enhanced and numerous ;mprQvemellls can be found throughout the book. You will probably find more lopics than you can cover in a single course. This range of topics provides the flexibility to accommodate a variety of program requirements. For example. some of the design-oriented or system appl ic
New in This Edition T he Hamming error detecting and correcting code Cany look-ahead adders A brief introduction to VHDL Expanded and improved coverage o f lest instruments All expanded and reorganized covemgc of programmable logic
Improved troubleshooting coverage New approach 10 Digiml System Applications
FeabJres Full-color format Margin notes provide information in a very condensed form. Key tenns are lisled in each chapter opener. Within the chapter, lhe key tenns are in boldface color. Each key term is defined at the end of the chaplt:r, as wel l as at the end of the book in the comprehensive glossary along with other glossary tenns that are indicatctl by black boldface in the lext.
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PREFACE
Chapter 14 is designed as a "floating chapter" 10 provide optional coverage of IC technology (inside-the-chi p circuitry) at any point in your COUfSc:. O verview and objeetivcs in each chapter opener Introduction and objccti ves al the beginning of each section within a chapter Review questions and exercises at the end of each section in a chapler A Related Problem in each worked example
Computer Notes interspersed Ihroughoutto provide interesting in formation abou t computer technology as it relates to the text coverage Hands-On Tips interspen;t:d throughout to provide useful and practical infonnation The Digital Syslem Application is a feature at the end o f many chapters that provides interesting and practical applications of logic fundamcnta ls. Chapter summaries at the end of each chapter Multiple-choicc self-test at the end of each chapter Extensive se<:tionalized problem sets at the end of each chapter include ba.,ic. uQublcshooting. system applicat ion. and special design problems. T he use and application of test instruments, including the oscilloscope, logic analyzer. fu nction generator, and DMM . arc covered. Chapter 12 provides an introduction to computers. Chapter 13 introduces digital signal processi ng. incl udi ng analog-to-digital and digital-to-analog conversion. Concepts of programmable logic arc introduced beginning in Chapler I . Specific fi xed-function IC devices are introduced throughout. Chapter 11 provides a coverage of PAls. GAb. CPLDs and FPGAs as well as a generic coverage of PLD programming. Sek.'Cled circuit d iagrams in the lext, identified by the specia l icon shown here. art: rendered in MuJtisimQ1 200 1 and Mu ltisi m i!l 7. and these circui t files art: provided on the e nclosed CD-ROM. These flies (also available on the Companion Website at www_prenhall.comJnold)art: provided at no extra cost 10 the consumer and are for usc by anyone w ho chooses (0 usc Multi sim software. Multisim is widely regarded a~ an excellent simulation 1001 for classroom and labnratory leaming. However. successful use of this textbook is not dependent upon use of the c ircuit files. Boundary scan logic a<;sociatt:d with programmable devices is introduced in Chapter II. In addition to boundary scan. trou bleshooting coverage includes methods for lesti ng programmable logic. such as traditional. bed-of-nails. and Oying probe. Boundary scan and tht:se other mt:lhods are imponal1\ in manufacturing and industry. For those who wish to include ABEL programming. an introduction is provided on the Compan ion Website at www.pn:nhall.comJfloyd.
PREfACE
Accompanying Student Resources £Xperil11enr.~ ill Digiud FlIndamentals, a laboratory manual by David M. Suchla. Solutions for th is manual are available in the Instructor's Resource Manual.
Two CD-ROMs incl uded with each copy of the text: Circu it files in Muhis;m for use with Muh isim sofl ware Texas Instruments digital devices data sheets
Instructor Resources POlI"erPoin fJ .flides. T hese presentations reature Lecture Notes and fi2 ures rrom
the text. (On CD-ROM and onli ne.) CalnplI/lioll \Veb.~ife. (www.prenhall.comtnoyd). Forl he instructor. this website offers the ability to post your syllabus online with our Syllabus Manager1"M. This is a great solution ror classes taught online. Ihal are self-paced , or in any compulerassisted manner. IlISlruclor 's Resollrce Mallual. Includes worked-oul solutions to chapter problems, solutions to Di1,!ital System Applications, a summary or Multisim simulation results, and worked-out lab results ror the lab manual by David M. Buchla. (Print and on linc.)
Tnt Item File. This edition of thc Test Item File reatures over 900 questions. TestGell. ~ This is an electronic ve~ion of the Test Hem Fi le, enahl ing i n.~truclor.~ to customize tests for the classroom.
To access supplementary materials online, instructors need 10 request an instructor access code. Go to www.prenhall.colll . click the Instructor Resource Cent~r link. and then cl ick Register Today for an instructor acce:,,, code. Within 48 hOUr!; aftcr registering you will receive a confirming e-mail including an instructor accc)'s code. Once you have received your code, !,!O to the website and log on for full instructions on download ing the materials you wish to uSt!.
Illustration of Chapter Features Chapte,. Opener Eacn chapter begi ns with a two-page sprcad. a.~ shown in Figure P- I . The left page includes a list of the sections in lhechapter and a list of chaplerobjectives. A typical right page includes an overview of the chapter. a list of spt!Cilic devices introduced in the chapter (each new device is indicated by an Ie logo at the point where il is introduced), a bricf Digital System Applicntion pn.:view. a list of key terlllS. and a websitc reference for chapter sludy aids. Section Opene,. Each of the sections in a chapter begins with a brief imroduction that includes a general overview and section objectives. An illustration is shown in Figure P- 2. Section Review Each section ends wi lh a rev iew consisting of questions or exercises that emphasizc the main concepts presented in the section. 111is feature is shOwn in Figure P- 2. Answers to the Section Reviews are al the end of the chapter.
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PREFACE
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Troubleshooting Section Man}, chapters include a troubleshoot ing secti on that relates to the topics covered in the chapter and thm emphasizes tro ubleshooting techniques and the use of test instruments. A portion of a typical troubleshooting sectio n is illustrated in Figure P-4 . Digital SYJtem Application Appearing althe end of many chapters, this feature presents a practical application of the concepts covered in the chapter. This fea ture presents a "realworld" system in which analysis, troubleshooting. and design elements are implemented u:
Tablet counting and control system: Chapter I Digi181 display: Chaplers 4 and I I. Storage tank control system: Chapter 5
PREFACE
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Traffic lighl control syslCm: Chaplers 6. 7. and 8 SecunlY syslem: Chapters 9 and 10 Digital System Applications may be treated as optional because omilling Ihe m will not afTccl any other matenal in the text. Figure P- 5 shows a portion of a Digital Syslem Application feature. Chapter End
The following sludy aids end each chapter:
Summary Key term glossary
Sel f-lest Problem sellhat includes some or all or lhe foll owi ng categories: Basic. Troubleshooting. Di£ ital System Application, Design. and Mullisim Troubleshooting Pract ice Answers 10 Seclion Reviews Answers to Related Problems for Examples Answers to Self-Test BookEnd
Appendices: Code conversion and table of powers of two light inlerface circuits (Appendix B)
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PREFACE
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An!>wers to odd-numbered problems Comprehensive glossary Index
To the Student Digitailechnology is hot~ Most everyth ing has already gone d igilai or will in Ihe near future. For example, cell phones and other types of wireless communication, television, radio. process controls. aUlomotivt: t:lt:ctronics. consumer t:lectronics. global navigation. military systems. to name on ly a few applications. dcpend heavily o n dig ital electronics. A strong foundation in the fu ndamentals of digital technology will prepare you for the highly skilled and high-paying jobs of the future. The singlc masl important thing you can do is to understand the core fundamen tab.. From tht:re you can go anywhere. In addition. programmable logic is becoming extremely important in loday's technology and that topic is imroduced in this book. Of course, cfficiellllroubleshooting is a s kill that is also widdy soughl. Troubleshooting and testing methods from tradilionaltesti ng 10 man· ufacturing techniques, such a<; bed-of-nails, flying probe, and boundary scan, arc covered in lhis book. These are examples oflhe skills you can acquire with a scrious Cff0l1 10 learn the concepts presented. The CD- ROMs Two CDs are included with this book. One comai ns Texas Instruments dara sheet.. for digital integrated circuit ... The other cont.. ins circuit tiles in Muhisim for use with Multisi m software Versions 200 1 or 7. (These Version 2[() 1 and Version 7 circuit fi les-as well as those for use with Multisim 8-3lso appear on the Companion Website at \'I'\'I'\'I'.p renhall.cnmlflo),d.)
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PREfACE
User's Guide for Instructors Generally. time limilation or program empha~ i s detenninc the topics to be covered in a course. It is nOI uncommon to omit or condense topics or to al ter the sequence of certain lopics in onler 10 customize the material for a particular COUfsc . The author recognizes this and ha.. designed this textbook spccitically to provide great nexibility in topic coverage. Using a modular approach, certai n topics arc organized in separate sections or features such that if they arc omi lted, the rest of thc coverage is not affected. Also, iflhese topics arc included. they now scamlcssly with the rest of the coverdge. The book is organized around a core of fundamental topics that arc. for the most pan, essential in any digital course. Around this core. there are other topics thai call be included or omitted depending Ofl the course emphasis or olher factors. Figure P-6 illustrates this modular concept. Core Fundamentnls 111e fundamental topics ofdi gitaJ logic shOUld, for the most pan, be covered in all programs. Linked wthe core are several "satellite" topics that may bcconsidert.'d for omission or inclusion. depending on your COurl;C goals. Any block surrounding Ihe core can be omiued without affecting the core fundamen tals.
•
Programmable Logic Although it is an imponant topic. progrcllnmable logic can be omitted. but it is recommended that you cover this topic if at all possible. You can cover as lillie or a~ much as you consider practical for your program.
•
Troubleshooting sections appear in many chapters.
•
Troublruhooting
•
Digital System Applications
System appl ic
Integrated Circuit Techn ologiru Some or all of the topics in Chapter 14 ean be covered at sclected points if you wish to d iscuss detail!> of the circuitry that make up digital integraled circuits.
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• Special TOpiel These lopic!> are illllVductioll to ComplIll'l:\' and Digifllt Signed Processillg in Chapters 12 and 13, respectively. These are spccial topics and may no( be essen-
tial 10 your digilal course. Also, within each block in Figure P-6 you call choose toomit or de-emphasize some topics because of time constraints or other priorities. For example. in the core fu ndamentals. error cOITCction codes, carry look-ahead adders. sequcntial logic design. and other selected topics could be omitted . Cmtomizing the Table of Contents You can take anyone of several pathfi through Digital Fl/lulamenra/s. Nimh Editioll, dependi ng o n the goals of your particu lar program.
Whether you choose a minimal covcrage of only core fundamentals. a full -blown coverage of all the topics. or anything in between. thi s book call be adapted to your needs. The
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Table of Conlenls following Ihis prefacc is color coded to match the blocks in Figure P~6. This allows you to idcnlify topics for omission or inclusion for customizing your course. Several options for usc of Digital Fl/Iu/alllel1la/s. Ninth Edirioll arc shown below in terms of topics color coded to Figure P-6. Other options arc possible, too. induding partial coverage of some l op i c.~. Option I Option 2
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•• ••• Option 4 •••• Option 5 •••••• Option 3
Acknowledgments This innovative text has been realized by the e fforts and the skills of many people. I think that we have accompli shed what we SC I out to do, which wa~ to produce a textbook sccond to none. At Prentice Hall, Kate Un.~ne r and Rex Davidson have contributed a great amount of time, talcnt. and effort to move this project through its many phases in ordcr to produce thc book :l~ you see it. Lois Porter ha~ done a fa ntastic job of editing the manu~cri pl. She has unraveled thc mystcries of this author's markllp~ and often nearl y illcgible notes and. from that tangled mess, extrdCtcd an unbelievably organized and superbly edited manuscript. Also, Jane Lopez has done another ocautiful job with the graphics. Another indi\·idual who contributed si~n ifi ca ntl y to this book is GlIry Snyder, who has provided all oft hc Mullisim circuit li les (ill Mult isim Versions 200 1. 7, and 8. all of which appear on thc Companion Website at www.prenhall.comltloyd). I extend my thanks and appreciation to all of these people and Dlhers who were indircctly involvcd in the projcct. In the revision of this and alitextlx>oks, I depend on cxpen input rrom many users as well as non-users. I want 10 offer my si ncere thanks to the following reviewers, who submittcd many valuable suggestions and provided lOIS of constructive criticism: 80 Bany. Univcrsity of North Carolina-Charlone: Chuck McGlumphy. Behnonl Technical College: and Amy Ray. Mitchell ConununilY College. My appreciation goes to David Buchla for his dTons to make sure that the lab manual i ~ closely coordinated with the text and for his valuahle input. I would also like to mention Muhammed Arif Shabir for his suggestion uJlll:cming sh ift registers. I thank all of the members of the Prentice Hall sales force whose effons have helped make my books available [Q a large numhcr of users throughoutlhc world. In addition, I am gratcfu l to all of you who have adopted Ihis tcxt for your c1a'ises or for your own usc. Without you we would 110( be in business. I hope that you fi nd this book to be a valuablc learning tool a.nd reference for students. Tom f-
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Contents Core fOllies which call be comidered (1$ olNiollal
1
Digital Concepts 2
4
Digital and Analog Quanlitics 4
1- 2
Binary Digits. Logic Lcvels, and Digital Wavcrorms 6
4-1
Boolcan Operations and Expressions 184
4-2
Laws and Rulcs o f Boolcan Algcbra 185
1-3
Ba<;ic Logic Opemtions
4--3
DeMorgan's TIlcorem 191
1- 4
Ovcrvicw of Ba<;ic Logic Functions 14
4-4
Boolean Ana lysis of Logic Circuits 194
1- 5
Fixed-Function Integratcd C irl:uits 19
4--5
Simplification Using Boolean Algebra 196
6
IIltrodUl'1illn In Pro!,'ra mmahlc l.o!,'ic 22
4-6
7
Test anll M(' .. ~ urcll1c nl
SlandOlrd Fonns of Boolean Expressions 200
4--7
Boolean Expressions and Truth Tables 206
4- 8
Thc KamauBh Map 2 10
I~
In~Iru mcn i s
27
Di2ila l Sy';tem Application 38
2
Number Systems, Oper
46
4-9
KamauBh Map SOP MinimiZaiiOIl 2 12
Decimal NlIlIlocrs 48
4- 10
Kamaugh Map
22 1'
2- 2
Binary Numbers 50
4- 11
Five-Variablc Kamaugh Maps 225
Decima l-tn-Binary Conversion 53
4 [2
VHDL 228
2-4
Binal)' Arithmetic 56
2- 5
I 's and 2's Complemcnts of Binary Numocrs 60
2-6 2- 7
Signed Numocrs 62
5-1
Basic Cumbinational Logic Circui ts 246
Arithmctic Operations with Signl.>d Numbers 68
5- 2
Implemcming Combinational Logic 250
5- 3
2-8
Hcxadecimal Numbers 75
Thc Universal Property of NAND and NOR Gatcs 256
2- 9
Octal Numbers 82
5-4
2- 10
Binary Coded Decimal (BCD) 84
Combi national Logic Using NAND and NOR Gates 258
5- 5
Logic Circuit Operation wi th Pulsc Waveform Inputs 263
5 6 5 7
CUlllhinational Logic \vilh VIIDJ 166
2- 12
I..
Dig!",1 SY~ l cm Applil'ilt iun 230
5
Combinational logic Analysis 244
Error Detection and Correction Codes 95
logic Gates 112 3- 1
xii
ros Minimizalion
2- 3
2- 11 Digital Codc.<; 87
3
Boolean Algebra and logic Simplification 182
I-I
Troublc,homing. 272 Digi tal SY<;lcm Application 278
The Inverter 114
3-2
TIle AND Gale
3-3
Thc OR Gate 124
J 17
3-4
The NAND Gate 129
3-5
The f'\OR Gate 134
3-6
Thc Exclusivc-OR and Exclusive-NOR Gates 139
,l--7
Pro,gr.mmlal:lle Logic 14J
3-8
Fixed-Function Logic ISO
J- 9
Troublc~hllOlin,g
160
6
Functions of Combinational logic 296 6- 1
Basic Addcrs 298
6-2
Par-
6-3
Ripple Carry versus Look-Ahcad Cany Adders 308
6-4
Comparators 3 11
6- 5
Decoders 316
6-6
Encoders 324
CO NT ENTS
10
6-7
Code Conveners 329
6-8
Mulliplexers (Data Selectors) 331
10- 1
6-9
Demultiplexers 340
10-2
Random-Access Memories (RAMs) 542
6- 10
Parity Generdtors/Checkers 342
10-3
Read-Only Memories tROMs) 555
Tru ubk,hooting 345
10-4
Programmable ROMs (PROMs and EPROM s) 560
(1
II
of Semiconductor Mcmory 53H
10-4
H ash Memories 563
10-6
Memory Expansion 568
7-1
Larches 372
10-7
Special Types of Mcmories 574
7-2
Edge-Triggered Fl ip-Flops 378
10-8
Magnetic and Optical Storage 579
7-3
Flip-Flop Operating C haracteristics 390
I 0---9
Trol1blc~h \l()1 inl:!
7-4
Rip-Flop Applications 393
7-5
O ne-Shots 39t1
7-6
Thc 5551imer 403
7--7
Trtmhk,hutlli n!! -10')
5H5
Digital Systcm Applicat ion 5':W
11
Counters 426 8- 1 Asynchronous Counter Operation 428
Programmable logic and Software 604 II I
Pro,grmnmable LUl!IC SPLD, 011111 CPL[)" 606
II -1
Ahenl
CPLD~
61.J
II '\
XIIi !)>.
CPL D~
620
11 -4
MUCHll:t:II, 623
8- 2
Synchronous Countcr Operation 436
II 5
Programmable I.o{;ic: l-K, A, 62H
8-3
lJp/DO\.vn Synchronolls Counters 444
11-6
Altern
FPGA~
633
8-4
Design of Synchronous Counters 447 .
II -7
Xilinx FPGAs 637
8-5
Cascaded Counters 457
II 8
Progr.ul1 l11able i.ul!ic Soft\\:m.: 643
8-6
Counter Decoding 46 1
11- 9
BoumJary Scan L01,!it: 654
II 10 Troubleshooting 661
8-7
Countcr Applications 464
8--8
Logic Symbols with Dependency Notation 469
tI ()
Trouble,tlOot lllg 47 I
Di!;ilal Sy,tclII Application "68
12
Introduction to Computers 692 12- 1 TIle Basit: Computer 694
Dig ital Systcm Applicntion 475
9
Ba~ i cs
latches. Flip- Flops, and Timers 3 7 0
Digital Systcm Application .J t I
8
xiii
Memory and Storage 536
Digital System Application 348
7
•
12- 2
Microprocessors 698
Shift Registers 492
11- 3
A Specific Microprocessor Family 700
9- 1
Basic Shift Registcr Functions 494
12-4
Computer Progrnmmin!; 707
9- 2 9- 3
Serial lnl5erial Out Shift Registers 495 Scriall n/Parallcl Out Shift Registers 499
12- 5
i ntl':ITU p b
9-4
Parallel In/Serial Out Shift Registers 501
9- 5
Parallelln/Parallci Out Shift Registers 505
~
Bidircctiol1'll Shift Registers 507
9-7
Sh ift Register Counters 510
9--8
Shi ft Register Applications 5 14
13 I
Digital Signal
9-9
Logic Symbols with Dependcncy Notation 52 J
13-2
Converting Analog Signab to Digital 745
13-3
Analog-to-Digital Conversion Melhods 751
Tmubb huolin,\! 522
13--4
The Digital Sign:,! Proccssor (DSP) 762
Digilal Sy,tcm ApplicatIon 515
13- 5
Digital-til-Analog Convcn;illll Methods 768
9- 10
7 18
12-6
Di rect MelllOlY Acce.~s (DMA) 720
12- 7
Internal Interfaci ng 722
12- H Sl!ind..trd Buses 726
13
Introduction to Digital Signal Processing 742 Proce.,~in!!
Ba,ics 744
xiv
•
CONTENTS
14 Integrated Circuit Technologies 784 14-1
Ba~it: Opcnttional Characlerislics and Paramelers 786
14-2 CMOS Cin:uil" 794 14-3
TTL Circuit!' 799
14-4
Practical Con"ideraljon~ in Ihe Use of TIL 8(»
14-5
Compari~oll
of CMOS and TTL Pcrfonnance R12
Emitter-Coupled Logic (EeL) Circuit" 813
14-6 14-7 PMOS. NMOS. and E~CMOS 814
APPENDICES
A
Conversions 825
8
Traffic light Interface 827
Answers to Odd-Numbered Problems 828
Glossary 856 Index 865
DIGITAL FUNDAMENTALS
DIGITAL CONCEPTS CHAPTER OUTLINE
,-, ' -2
Digital and Analog Quantities
B.asic logic Operations
,-,
Overview of Basic logic Flmctions
'-6 ' -7
Introduction to Programmable logiC
c::c
fixed-Function Integrated Circuits
Test and Measurement Instruments Digital Sys:tem AppliCOltion
~od
•
Explain the balie diffcreoce5 between digital quantities
•
Show how voltage levels are used to represent digib l quantities
•
Describe various paramctcr1 of iI puhc waveform such as rile
Bill.Jry Digits. logic levels, and Digital Waveforms
' -3 ' -4
CHAPTER OBJECTIVES omalog
time, fall time, pulse width, frequency, period, and duty cycle • •
Explain the basic logic Qpef3tionl of NOT, AND, and OR DeKribe the logic functions of the comparator, adder, code
converter, encoder, decoder, multiplexer. demu'tiple
Iclt:ntify fixed-function digital intcgr
KEY TERMS
INTRODUCTION The term digital is derived from the way computers perform operations, by counting digits. For many yean, applicatiom of digital electronics were confined to computer s)'1tems. Today, digital technology is applied in a \.Vide range of areas in addition to computen. Such applications as television, communications s)'1tems, radar, navigation and guidance systems, military system~, mediC
Key terms are in order of appearance in the chapter.
Analog
Output
Digital
Gate
Binary
NOT
Bit
Inverter
Pulse
AND
Clock
OR
Timing diagram
Integrated circuit (Ie)
Data
SPLD
Serial
CPLD
Parallel
FPGA
logic
Compiler
In put
Troublehooting
•••
DIGITAL SYSTEM APPLICATION PREVIEW
The last feature in many chapters of this textbook uses a system application to bring together the principal topics covered in the chapter. Each system is designed to fit the particular chapter to iIIUltrate how the theory and devices can be used. Throughout the book, five different systems are introduced, some covering two or more chapten. All of the I~teml are simplified to make them manageable in the context of the chapter material. Nthough they are based on actual system requirements, they are designed to accommodate the topical coverage of the chapter and are not inte nded to necessarily represent t he most efficient or ultimate approach in a given application. This chapter introduceJ the first system. which il an industrial process control system for counting and contro lling items for packaging on a conveyor line. It is designed to incorporate all of the logic functions that are introduced in this chapter so that you C
~
YUrT TH E COMPANroN WE8SITE
Study aids for this chapter ilre availilble ilt http;!lwww.prenhall.comlfloyd
3
4
•
1-1
DIGITAL CONCEPTS
DIGITAL AND ANALOG QUANTITIES Electronic circuits can bc dividcd into two broad categories, digital and analog. Digital electronics involves quant ities with discrete values, and analog electronics involves quant ities with eOlliinuous values. Allhough you will Ix! studying digital fu ndamentals in this book, you should also know something about analog because many applications require both ; and illierfac ing betwccn analog and digital is important. Arter completing this .~eetion . you should be able to • Define (ll/a/og • Define digital . Explain the difference between digital and analog quanti ties _ State the advantages of digital over analog . Give examples of how digital and analog quantities arc used in ciectronics
An analog* quantity is one having continuous values. A digital quantity is one having a discrete SCI o f values. Most things Ihat can be measured quantitatively occur in nature in analog form. For example, the air temperature changes over a continuous range of \-alues. During a g iven day, the temperature does not go from. say, 70° to 7 10 instantaneously; it takes on all the infinite values in between. If you graphed the temperature on a typical summer day. you would have a smooth, continuous curve similar to the curve in Figure I- I. Other examples o f analog qualllities
&aph of an analog quantity (temperatu re ven.u< time).
Tempemture ( OF)
,
100
,-
OS
90
~j- r-/Li' ,
-
85
-
-,
'" ", 75
I
,
~
1/ I-{.
70
I
/ '
r-
I
I
I
I
I
I
, I , I
,
' I
,1+:
,,
I 1
,.
!
J
i
I
"~ d--
r L
I
'f
·I-+_
L
'
TIme
ufda~
2 3 4 5 6 7 8 9 10 II 12 I 2 3 4 5 6 7 8 9 10 I I 12 A .M
Rather than graphing the temperature on a continuous ba~is, suppose you just take a temperature reading evcry hour. Now you hm'e sampled values represcnting the temperdture at discrete points in time (every hour) over a 24-hour period, as indicated in Figure 1- 2. You have effectively converted an analog quantity to a fOlm that can now be digitized by representing each sampled value by a digital code. It is importam to realize that Figure 1- 2 itself is nOi the digital representation of the analog quantity.
The Digital Advantage Digital represcntat ion has cel1ain advantages over analog representation in electronics applicat ions. For one thing, digital data can be processed and transmitted more efficiently and reliably than analog data. A I ~, d igital data has a great advantage when storage is necessary. For example. music when converted to digital form can be stored more compactly and reproduced with greater accuracy and clarity than is possible when it is in analog form . Noise (unwanted voltage flucluations) docs not affect digital data nearly as much 11.<; it docs analog signals.
" All l)uld (enllS lire important and are detinl1:l in lhe l11d-of.lJ(K)k gto.'iSllry. The blue bold tenns are key tcrms and arc included in a Kl·,. Tenn gl0SS8ry alliK' md of ~a..,h ..,haplcr.
DIGITAL AND ANALOG QUANTITIES
(CJl
h
~.
" ~LI-l- '" ~ :, i " I ,I '" I
,
!
I
-'-
-
,
S<.mpled-v.:rJue representation (quantization) of the analog
, I
I-
I 2 ]
ht -
-
quantity in Figure I-I . Eacn value represented by a dot un be digitized by representing it a~ a digiLlt code that conlists of a M:!ria of II and 01.
1 L
!
15
10
5
FIGURE 1- 2
Tempo..'f>lture
100
•
.
-
-
4 5 6 1 8 9 10 II 12 1 2 ]
4
5 6 1
l
Ti me of day
8 9 10 !l 12
'M
A .M .
An Analog Electronic System A public address system. used 10 amplify sound so Ihal il can be heard by a large aud ience, is onc simple example of an applicalion of analog electronics. The basic diagram in Figure 1- 3 illustrates lhal sound waves, which are an
@.
~
FIGURE 1- 3
Original m und wavC.'i
A basic audio public addrw o/Item. Repmtlut."C
Microphone
uV
Line.1r amplifier
Audio ~i~n.1 1
Amplified audio
si~llIll
A System Using Digital and Analog Methods The compacl disk (CD) player is an example of a system in which both digital a nd ana log circuits arc used. The simplified block diagram in Figure 1-4 illuslrates Ihe ba~ic principle. Music in dig ital form is stored on the compact disk. A laser diode Opfical system picks up the d ig ital data from the fOWl ing disk a nd transfers iliO the digilal-to-almlog (.'On\"elier ([)AC). FIGURE 1-4
CD drive
B
1111 10111 1101
Digit.u.l data
D'gillll-ll>-nn:!log l"O,wcrtcr
Li near amplirtcr
A""log reproduction of music mKlio Sign.1'
50000
6
_
DIGITAL CONCEPTS
The DAC changes lhe digital dalll info an analog signal that is an electrical reproduction of the original music. This signal is amplified and senf to the speaker for you 10 enj oy. When the music was originally recorded on the CD, a process, essentially the reverse of the one described here, lIsing an :'lIlulog-to-digital COlll'crtcr (ADC) was used.
1. Define analog. Amwer~
are at the end of the
chapter.
2. Defin e digital. 3. Explain the difference between a digital qua ntity and an a nalog quantity. 4. Give an example of a system that is analog and one that is a combination of both digital and analog. Name a system that is entirely digital.
1-2
BINARY DIGITS, LOGIC LEVElS, AND DIGITAL WAVEFORMS Digital electronics involves circuits and systems in which there are only two possible states. These ~tates are represen ted by two differe nt voltage levels: A HIGH and a LOW. The IWO sLates can alw be re presented by cUlTent levels, bits and bumps on a CD or OVD. etc. In digital systems such as computers, combinations o f the two states, called codes. lire used to re present nu mbers. symools. Hlphllbctic characters. and other types of information. The tWQ-l·;lale number system is called billar:)', and its two digits are 0 and I. A binary digit is called a bit. Arter completi ng this section. you s hould be able to - Deti ne biliary - Define bil - Name the bil<; in a binary system - Explain how voltage levels arc used to represent bits - Explain how voltage levels are interpreted by a digiull circuil _ Describe the general charHctcristics of a pulse . Detennine tl'M! amplitude. rise tin"le. fall time. and width of a pulse _ Identify ,lrJd dt~ ribe the characteristics of a digit,,1 wavefOim _ Delennine the amplitude. period. frequency. and du ty cycle of a digit,ell wavefonn - Explain what a ti ming diagmm is and stHie its purpose - Explain serial and parallel data transfer and st
Binary Digits Each of the two digits in the binary system, I and O. is called a bit, which is a contraction of the words bill(lry lliSil. In digital circuits. two different vollHge levels are used to represent the two bits. Generally, I is represented by the higher voltage. which we wi ll refe r to as a HIGH. and II 0 is re presented by the lower voltage level. which we will refer to as a LOW. This is called positive logic and will be used throughoutlhe book.
HIGH Babbage, who dt:\ll::loped a crude mechanic.'!1 computation device in , 8305. John Atanaroff wal the fint to apply e lectronic procelling to digita l computing in 1939. In 11946, an electronic digital computer called ENIAC wal implemented with vacuum-tube cin:uib. Even though it took up an entire room. ENJAC didn't have the computing power of your handheld calculator.
I
=
1 and
LOW = 0
Another system in which a I is represented by a LOW and a 0 is represented by 1l HIGH is called lIesutil'e loSic. Groups of bits (combinations of Is and Os), called ('vlles, arc used to rcpresem num bers, leiters, symbols, instructio ns, and anythi ng else required in a g iven application.
logic levels The voltages used to represent a I and peciried maximum value. Likewise, a LOW can be any voltage between a specified minimum
BINARY DIGITS, LOGIC LEVEU, AND DIGITAL WAV EFORMS
FIGURE 1 - 5
Logic revel ' ,mgel of voltage for iI
VtI(",", )
I·HGH
d igital circ;u it.
(binary I) VtI(min)
Unallowed Vl.l...... )
LOW (binary 0) VL~min)
and a specified maximum. There can be no overlap between the accepted range of H IGH levels and lhe Hccepted range of LOW levels. Figure 1- 5 illustrates Ihe gener1.li mnge of LOWs and HIGHs fon. digital circuit. The variHble VH 1lIUl» represenls the maximum HIGH voltage value, l.wd VH(min) represents the minimum HIG H voltage value. The mHximum LOW voltage value is represented by V,.(..... ~). and Ihe minimum LOW voltage value i~ represenred by V l.(mi n). The voltage vlllues between V•.(........ ) lind VlI(fflinl are unllcceptable for proper operation. A voltage in the una llowed mnge can appear (IS either (I HIG H or a LOW to 11 given c ircuil and is the refore not an acceptllble value. For example, the HIGH values for a cel1ain type of digital circuit called CMOS may range from 2 V to 3.3 V (lnd the LOW values may range from o V to 0.8 V. SO, for example, if (I voll<'ge of 2.5 V is applied. the circui t wi ll (lccept il (IS 1.1 HIG H or binary I. If (I volt(lge of 0.5 V is applied, the circuit will (lccept it as a LOW Of binary O. For Ihis type of circuit. voltages between 0.8 V and 2 V are tlflHcceptable.
Digital Waveforms Digit.1 1 wavefonns consist of voltagt: levels Ul1.lt are ch(lnging back and fort h between the HIGH and LOW levels or st:ltcs. Figure 1-6(a) shows that a single positive-going pulse is generated when the voltage (or current) goes from ils normally LOW level to its HIGH level and then hack to ilS WW level. The negali ve-going. pu lse in Figure l-6(b) is gener.ued when the vollllge goe.'l from its nonna Uy HIGH level to its LOW level and back 10 its HIGH level. A digilal waveform is made up of a series of pulses.
/1
HIGll
HIGH - - n
." ',g"
leading edge lOW
'0
(a) Posi!ivc-goi ng pul ~
F" ll" oc trai ling edge
/ L-
'1
U
Falli ng or lead ing edg(' 1.1)\\
--
'0
FIGUR£ 1-6 Rising or / , ng edge
'1
(b) Ntgativt:-goi ng pu lse
The PuiJe As indic .. led in Figure 1-6, a pulse has two edges: a leading edge that OI:CUr.; firsl l.lt time and a trailing edge thai occurs la:;1 at time For a positive-guing pulse, the leading edge is a rising edge, and Ihe tT1liling edge is a fallin g edge. The pul ses in Figure 1-6 are ideal because the rising and fall ing edges are assumed to change in zero time (insl1.lfllancously). In pmctice, the~e ImnsiLiuns nt:vt:r OCCllf instamaneotlsly. although for nJl)st digilill work you can 1.l!',sumc ideal pulses. Figure 1- 7 shows 1.1 nOll ideal pulse. In re(llily, all pulses exhibit some or all of these characteristics. T he oVt:rshoot and ringing are somcti mc:; produced by stmy inductive and
'0
'I'
Idea l pu r.e;.
•
7
8
•
DIGITAL CONCEPTS
FIGURE 1 - 7
OWr.IKlOI
Nonideal pulse C""",..,cteriltiCi.
r -- ---~-, 50% , •••:
AmP1'illXlt!
---;c;c:-",7.:;:-----:,~. ,
,, ,,,
,01> I 1. -
'"
PuI..., ... H.llh
I
-l
Rise: lin~
,,1 ,,
,, 1 1
7
1 1
hltume
capacitive effects. The droop can be caused by strdY capacitive and circuit resistance, forming an RC circuit with a low time constant. The lime requ ired for a pulse to go from its LOW level to its HIGH level is called the rise time (t,), and the time required for the transi tion from the HIGH level to the LOW level is called the fall time (t,). In practice, it is cOllunun to measure rise lime from 10% of the pulse amplitude (height from baseline) to 90% of the pulse amplitude and to measure the fall time from 90% to 10% of the pulse amplitude, as indiCllted in Figure 1- 7. The bollom 10% and Ihe lOp 10 % of the pulse are not induded in the rise and fall limes because of the nonlinearilies in the waveform in these areas. The pulse width ttw) is a measure of the duration of the pulse and is often defined as the lime inlerv,ll between .he 50% poims on .he rising and fall ing edges, as indicated in Figure 1- 7. Waveform Characteristics Mo~t wtlveforms encountered in di!!ital systems are composed of series of pu lses, sometimes called pulse lraills, and can be classified as ei ther periodic or nonperiodic. A periodic pulse waveform is one that repeats itself al a fix ed interval. called a period (T). The frequcncy (j) is the rule at which it repeats itself and is measured in hertz (Hz). A nonperiodic pulse wavefclnn, of course, does not repeat itself at fi~ed intervals and may be composed of pul se,~ of randomly differing pulse widths and/or randomly differi ng time intervals between the pulses. An example of cl.lch type is shown in Figure 1- 8.
I-T,
+ T. + 1,-1
(b) Nonperiodic
Period '" 1', '" 1'2 '" 1'1 '" .•. '" 7~ Frequency ",
f
{al Periodic (square wave)
FIGURE 1- 8
Examples of digital
w~forml.
The frequency (f) of a pulse (digital) wavefoml is the reciprocal of the period. The relationship between frequency and period is expressed as follows:
Equation 1- 1
Equation 1-2
f~
I
T
BINARY DIGITS, LOGIC LEVELS, AND DIGITAL WAVEFORMS
•
An important characteristic of a periodic digititl waveform is its duty c}-clc, which is the mtio of the pulse width (flY) to Ihe period (T). It can be expressed as a percentage. DUI)' cycle =
T 100% ( tw)
I
Equation 1- 3
EXAMPLE 1-1 A porlion of a periodic digital wavefonn is shown in Figure 1- 9. The measuremenlS are in milliseconds. Determine lite fo llowing: (II) period
(b) frequenc),
(e) duty cycle
[2;,- -"---1'1 1":-
Jlc-------------7n.';-----,,~) U
FIGUR£
Solution
If)
11
1-9
(a) The period is measured from the edge of one pu lse to Ihe corresponding edge of
the next pulse. In this case T is measured from leading edge to leading edge, as indicated. T eqmtls 10 ms. (b)
f~
1
-
T
~
1 10ms
-
~
100Hz
1 m, )
t .. ) 100% = - - 100% = 10% (c) DUlY cycle = ( T ( JOms
Related Problem'
/I. periodic digital waveform has a pulse width of 25 IlS and a perioo o f 150 ps. Determine the frequency and Ihe dUly cyclc.
- Answers are m the end of the chajXcr.
A Digital Waveform Carries Binary Information Binm)' informal ion that is handled by digilal systems appeilrs as waveforms that represent sequences of bits. When Ihe waveform is HIGH, il binary I is present; when the wavefoml is LOW, a binary 0 is present. Each bil in a sequence occupies a defined time interval called a bit time. The Qock In digital sy~ l e m s, ,t il waveforms are synchronized with a basic timing waveform ca lled the clock. The clock is a periodic waveform in which each imerval belween pulses (the perioo) eqmlls Ihe lime for one bil. An example of a clock waveform is shown in Figure 1- 10. Nolice Ihlll. in this case, each changc in level of waveform A occurs ,II the leading edge of the clock waveform. In other cases, level changes occur at lhe trnilingedgeoflheclock. Duringeilch bit timeof lhe clock, w,weform A is either HIGH or LOW. These HIGHs and LOWs represent a sequence of bils as indicated. A group of several bifS can be used a.~ a piece of binary infonnation, such as a number or a lener. 'I1IC clock wavefonn itself does not carry information.
The ipeed
Cit" oper
of microprocessor u!oed in the Iysrem. The speed sp«ifiC
I
9
10
•
DIGITAL CONCEPTS
FIGURE 1-10
Bit
Example of 21 clock w.weform synch ronized with 21 w2l\oeform
repree:ntation of 21 iequence of bib.
C lock
A
I
o
o
Bi t st:
II
II
II
II
II
II
Tuning Diagram s A timing diagram is
Example of a timing diilgram.
Oock
A
B
L
c
A. B. and C HIGH
Data Transfer Dal:.:l refers to groups of bits thai convey some type of infonnntion. DinaI}' data. which are represented by digital waveform.~, must be transferred from one circuit 10 another within a digital systcm or from one system to another in order to accompLish a given purpose. For example. numbers ~tored in bi nm)' form in the memory of 11 computer must be lramferred to the computer's central processing unit in ordcr 10 belldded. The sum of the addition must then be transferred to 11 monitor for d isplay and/or transferred back to the memory. In computcr systems. as illustf1lted in Figure 1- 12, binary data are transferred in two ways: serial and paf1lllel. When bits are transfelTed in serial form from one point to another, they are sent one bit at a time along a si ngle line. as illustrated in Figure 1- 12(11) for the case of 11 computer-tomo<.lcm transfer. During the time interval from,o to the first bit is transferred. During lhe time interval from'l to ' 2' the secund bit is transferred, and so on. "0 tntnsfer eight bits in 5Cries, it takes cight time imcrv:lls. When bits are transferred in parallel form, all the bits in a group are sent oul on separate lines at the same time. TIlere is onc li ne fOl" each bit. liS shown in Fi& 'lJre 1- I2(b) for the example of e ight bits being Imnsferred from a cumputer 10 a printer. To transfer eight bits in parallel , it lakes one time interval compared 10 eight time intervals fo r the serial transfer. To summarize, (In advantage of .serial transfer o f biotlry data is that a min imum of only one line is required. In parallel transfer. a number o f li nes equal to the number of
'I.
BINARY DI G ITS, LOGIC LE VELS, A N D DIG ITA L WAVEFO RM S
~
COl11lJU11'f"
:n :
•
Prinler
J9 8 ,, n ,, ,
~
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8 :
~ 10
I,
12
')
'4
"
,/)
, ,
'7
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COI11fl'lltT
'u, "~
" " (a ) Serial transfcr of8 biL\ of binary data fl{)lTl L"(lmputcr to modem. Interval 10 !o ' t is first .
(b)
l'aIllJlclt ran~fcr
of 8 biLS of bi nruy d l.la from computer In
printer. Tr~ beginni nGtime
i~ '0-
FIGURE 1 - 12
/JIusl:r
I
EXAMPLE 1-2
(a ) Delermine the total ti me req uired to serially transfer the eight bits co ntained in waveform A of Figure 1- 13. and indicate the sequence of biK The left-most bit is the fi rst to be tmnsferred. The 100 kHz clock is used as reference . (b) What is the lotal time to tr:msfer the s..lme e ighl bits in pamllel?
Clock
A
FIGURE 1-1]
Solution
(a) Since the frequellcy of the clock is 100 kHz. Ihe period is
1
T =-=
f
1 = lOp..s 100 kHz
I( take..,; 10 p.5 to trJ.llsfcr C
To determine the sequence of bits, examine the waveform in Figure 1- 13 during each bit lime. If wave form A is HIGH during the bit time, ,I I is tmnsferred. lf
11
12
•
DIGITAL CONCEPTS
waveform A is LOW during the bit time, a 0 is transferred, The bit sequence is illustrated in Figure 1- 14. '111e le ft-most bil is the firsi lo be II"
o ;
"
o
o
fiGURE 1 - 14
(b) A parallel tnmsfer would take 10 p.S for all eight bits. Related Prob~m
I
SECTION 1-2 REVIEW
If bin<1ry d:!ta lire transferred at the rate o f 10 mi ll ion bits per second (10 Mbil.v's), how long will it lake 10 paralle1 lmnsfer 16 bils on 16 lines? How long will il take to seri:tlly tr:tnsfer 16 bits?
1. Define binary. 2 . What does bit mean? 3. What are the bib in a binary system? 4. How arc the rise time and fall time of a pulse measured? 5. Knowing the period of a wa~lTl'I, how do you find the frequency? 6, Explain what a clock Wo'I\lefolTl'l is. 7. What is the purpose of a timing diagram? 8. What is the main advantage of parallel transfer over serial tramfer of binary data?
1- 3
BASIC lOGIC OPERATIONS in its bi.!sic form, 10glc is Ihe realm o f human re:tsoning th:!t tells you:t cert:!in proposition (declarative stmemcnt) is true if certain conditions are true. Propositions can be c1assified:ts lrue or false. Many ~ it u:ttions and prucesses that yOll em;uunter in you r daily life Clm be expressed in the form of propositional, or logic. functions. Since such functions are tme/false or yes/no statements, digital circuil.~ with thei r two-stme characteristics are :tpplic:!ble. Afler completi ng this section, you shou ld be ahle to - List three basic logic operations _ Define the Nor operation • Define the AND operation . Define the OR oper:tt ion
Several propositions. when combined, foml propmitional. or logic, funct ions. For example. Ihe propositional statement ''11Ie light is on" wi ll be true if "The bulb is not burned out" is tme and if "The switch is on" is true. The refore, this logical st:ltement can be made: Tire lighl is 011 Oll/Y ifille bll/b is lIot bl/rlled Ollt Ulld ffle .Iwitclr is 011. In this cxaJnple the frffit sta tement is true on ly if the last two st:tlements are true. T he first statement ("'The light is on") is the n the basic proposition, and the other two statements are the conditions on which the proposition depends. In the I 850s. the iris h logici:!n and mathematician George Boote developed a mathematical system for formulating logic statements with symbols so that problems can be writlen and solved in a manner similar to ordi nary algebra. Boolean algebm, as it is known
8ASIC lO GIC OPERATIONS
today, is applied in the design and amllysis of digital systems and will be covered in der.ai! in Chapter 4. The lenn logic is applied to digital circuits used 10 implement logic functions. Several ki nds of digita1 logic circuits life the basic elements thllt form the building blocks for such complex digitltl systems liS the computer. We will now look at these eiemenls and discuss their fu nctions in a very gener.1 1 Wily. Later chllpters will cover these circuits in dctai l. Three basic logic oper'dtions (NOr, AND, and OR) are indicated by standllrd disti nctive shape symbols in Figure 1- 15. Other standard symbols for these logic opcmtions will be introduced in Chapter 3. The lines connected to each symbol are the inputs and outputs. The inputs tlfC on the left of each symbol and the output is on the light. A circuit that perform s a specified logic oper'dtion (AND, OR) is called a logic gatc. AND :Uld OR gates can have any number of inputs, as indicated by the dashes in the figu re. FIGURE 1 - 15
The billie logic oper
'Y"'bols. AN D
N (Jf
OR
In logic opemtions, the true/false cond itions mentioned earl ier are represented by II HIGH (true) and a LOW (false). Each of the three basic logic opemlions produces a unique response to a given set of conditions.
NOT The NOT openltion changes one logic level to the opposite logic level, as indicated in Figure 1- 16. When lhe input is HIGH ( I ), the output is LOW (0). When the input is LOW, the output is HIGH. In eithe r case, the output is 1101 the Slime as the input. The Nor operation is implemented by a logic circuit known liS an inverter_
IItG~1 (I) ~ l.OW (O)
LOW (tJ)~ Hlml (l)
FIGURE 1 - 16
Th e NOT oper
AND The AND opemtion produces a HIGH output only when :tli the inputs are HIGH, as indi-
in Figure 1- 17 for the C:lse of two inputs. When one input is HIGH (/I1l1 the other input is HIGH, the output is HIGH. When any or all inputs ltre LOW, the output is LOW. Tlle AND opemlion is implemented by a logic ci rcuit known liS an AND gate.
Calc
I-IIGII (I ) = D IUGH (1) lI1UH (J)
IIIGJ-/ ( t ) = D -
lOW (0)
LO\.\ (0)
FIGURE 1-11
LOW (O)~
HtUH (I)~ LOW {O)
LOW (0) = D -
lO\V {O)
L{)\\ (0)
OR The OR operation produce.~ a HIGH omput when one or more inputs are HIGH, as indicated in Figure 1- 18 for the case of two inputs. When one input is HIGH or the other input is HIGH or both inputs are HIGH, theoulput is HIGH. When both inputs arc LOW. the output is LOW. '111c OR operat ion is implemented by a logic circuit koown a-; an OR gale.
The AND oper
•
13
14
_
DIG ITAL CONCEPTS
FIGURE 1 - 18
The OR oper
HIGH ( I ) = D -
HIGH
HIGH
(I )
HI<.iH (I ) = D -
HIGH (I )
I.Q\\ (0)
I
SECTION 1-3 REVIEW
( I)
1.0W ( O ) = D !UGH ( I )
1.0W (O) = D LOW (0)
IIIGH (I )
I.OW «(I)
1. When does the NOT operation produce a HIGH output? 2. When does the AND operation produce a HIGH output?
3. Whe n does the OR operation produce a HIGH output?
4. What is an inverter?
S. What is a logic gate]
1-4
OVERVIEW OF BASIC lOGIC FUNCTIONS The Ih ree oosic logic elements AN D , OR, and Nor Clin be combined to form more complex logic cin:uils thai perform many llsefu l opemtions and th
The Comparison Function J\'lagnitud e compariw n is perfomlcd by 11 logic circuit called 11 comparator, covered in C hapter 6. A comparmor compares two qu:mtities and indicates whether ur not they are equal. For examplc. suppose you have two numbers and wish 10 know if they are eqUltJ or nOI equal and, if not equal, which is grealer. The comparison funclioll is represented in Figure 1- 19. One num ber in binary form (represented by logic levels) is applied (0 input A,
FIGURE 1- 19
Comparator
The comp
A>8 A
~"{)(\C
A
rur :!
Biruuy
8
A<8
(a) Baliic
1litw.1)
magnitude compumlor
"
..,oo.le for :;
(b)
E~~mple :
Compa rator A>JJ - - LOW
A
A = IJ -
- LOW
A<8 -
HIGII
is less than JJ (2 < jJ as intlic-.ucd by
lhe HIGH ou tpUl (A < 8)
OVERVIEW OF BASIC lOGIC FUNCTIONS
•
and the other number in bi nary fonn (represented by logic levels) is applied to input 8. 'Ille outputs indicate the relalionship of [he two numbers by producing a HIGH leve! on [he proper output line. Suppose th1.11 a binary representation of the numbe r 2 is applied [0 input A and a bi nary representation of the number 5 is applied to inpullJ. (We discuss the biOal)' representat ion of numbers and symbols in Chapter 2.) A HIG H level will appear on Ihe A < B (A is less [han 8) output, indicating the relationship between the two numbers (2 is less than 5). The wide arrows represent a group of parallel lines on which the bils are transferred.
The Arithmetic functions Addition Addi tion is pclformed by a logic circu it called an adder, covered in Chapler 6. An adder adds two binary numbers (on inputs A and B with 1.1 carry input C,n' and generates a sum (1:) and ,I carry output (COlLI)' as shown in Figure 1-20(<1'. Figure 1- 20(b) ill ustTlltes the addi tion o f 3 and 9. You know that the sum is 12; the adder indic1.Ites Ihis re~u l t by producing 2 on the sum output and 1 on the carry output. Assume that the carry input in Ihis eX1.Impie is O.
Adder
Adder B,""'Y
A
r
Sum
~-OOJC
for)
A
Binary code for 2
bina!)
numbt-r. B CIlfTV In -
C,"" -
Con
Carry OUt
Binu!} ror q Bm:tf} U -
lYl(]~
8
C_
-
BUlIuyl
C..
Hinary ~... Idc:
(II) Bnsic ad
for 12
(b) Example: A plus 813 + 9 " 12)
F IGUR E 1 _ 20
The addition function.
Subtraction Subtraction is also perforoled by a logic circuit. A subtrdctcr requires three inputs: the two numbers that are to be subtr.u;ted and a borrow input. The two ou t put~ are the difference and the borrow output. When, fOf instance, 5 is subtracted from H with no borrow input. the difference is 3 with no borrow output You will ~ in Chapter 2 how subtraction can actu
The Code Conversion Function A code is a sct of bits ammged in a unique pattern and used 10 represen\ speci fied inforrmllion. A code convet1er changes one form of coded information into another coded forlll . Examples are conversion between binal)' and other cooes such a<; the binary coded decimal
•
•
In A microproceuor, the arithmetic logic unit (AlU) perfurms the oper.!tiom of add,
I
wbtrAct, multiply, And divide AS
well as the logk operations on
digitAl dab as directed by a series of instructions. A typica l Al U is COOltructed
logic ga tei.
of
many thousanm of
15
16
•
DIGITAL CONCEPTS
(BCD) and rhe Gray code. Various types of codes arc covered in Chapler 2. and eode converters are covered in ChaplCf 6.
The Encoding Function The encoding function is pcrfonned by a logic circuit called an encoder, covered in Chaple r6. The encoder converts information. such ao; a decimal number or an alphabetic characler, inlo somc coded form . For example, one certain type of encoder converts each of rhe decimal digits. 0 through 9, 10 a binary code. A HJGH level on the input eoITCsponding to a specific decimal digi t proouces logic levels that represent the proper binary code on the output lines. Figure 1- 2 1 is a simple illustration of an encoder uscd to convert (encode) a calcu lator keystroke into a binary code that can be processed by the calculator circuits. FIGUR E 1-2 1
r-,H~I,GOH,--_
--,:
An encoder used to encode oil calculoiltor keyltroke into a binoilry code for ltorage or hx calculation.
-
.:ncodcr
7
-,
COw
-4 3 -2 9
wlIlrn
Binary ~.,!
-I
-0
CDCDIIl
IJDO I+f- 1 Cak " I'llor kcypOO
The Decoding Function The decod ing function is performed by a logic circuit called a decoder, covered in Chapter 6. The decoder converts coded information, such a!'> a hinary number. into a nOI1coded form. such as a decimal form. For example. one particular type of decoder converts a 4-bi t binary code i11l0 the appropriate decimal digit. Figure 1- 22 is a simple iIIustmtion of olle type of decoder lhal is usctl to activate a 7segment display. Each of the seven segments of the display is connected to an output line from the decoder. When a pmticular binary code appears 011 the decoder inputs. the appropriate output lines arc activated and light the proper segments to display the decimal digit corresponding 10 the binary code. FIG URE 1-22
A decoder used to convert oil s.pecioill binary code into oil 7-~gment decimal reoildoul. Binary inpul
II
o
1-scgmcm displ ay
The Data Selection Function Two types of circuits that select dala arc the multiplexer and the demultiplexer. The mulliplexer. or mux for short, is a logic c ircuit that swirches. digital data from several input lines onto a single oUlpUl line in a specilied time sequence. Functionally. a multiplexer can be represented by an electronic switch operation thai sequentially cunncrts each of Ihe input lines to the output line. The demultiplexer (demux) is a logic circuit thaI switches digital
OVERVIEW OF BAS IC l OG IC FUN CT IONS
•
17
data rrom one inpul line 10 several oulpul lines in a spcciticd timc sequcncc. Essentially, Ihc dcm ux is a mux in reversc. Mu ltiplcxing and dcmu lliplexing arc uscd whcn dala fro m sevcral .'illurces arc to he transmitted ovcr one line to a distan t location and rcdistribUled 10 scvcral destinations. Figure 1- 23 illustrates this type of application whcre digi tal data from thrcc sources arc scnt out
I~mullipluer
l\Iu ltiple:o:u
JUU1JlJUl JlJUL ~
A
"
". totl
Dalllfmm AluD
Dala rmm
",
."
B lo(O
Oala from C lu F
Oma from AIOD
tot)
6>,
D
." 6>,
.',
N,
E
Swilching SCG' OCOCC cQIllrol input
E
>
JUU1JlJUl JlJUL ~
Switchi ng 5e(J UCfICC
control input
FIGURE 1-21
Ill ustration of a balic mu ltiplexingfdemultiplexing applicatic>n.
In Figurc 1- 23. dH ta from input A arc conncctcd to the outpul line duri ng timc intcrval 6f t and Inmsmilted to the demultiplexer Ihat connects thc m to output D. l 1lcn. during in· tcrval j,t!. the multiplcxcr switches to input B and the dem ult iplexer switches to output E. During interval 6.rJ • the mu lt iplexer swi lches 10 inpu t C and the dcmultiplexcrswitchcs to output F. 'Iosllmmarizc. during the first time interval . input A data gu to output D. During the sccond timc interval. input B data go In output E DUring thc third ti mc intcrval. inp ut C data go to output F. After this. the sequcncc repems. BCC,IUse the timc is dividcd up :Jmong SC\'eml sources Hnd desti nations whcrc cach has its turn to scnd and receivc data.. this process is called rime di"i.~·ivn lIudrip1exil1X (1UM).
The Storage Function Slomge is a function th,,' is requircd in most digi tal systcms. and its purposc is to retain binary data for a period of timc. Some storagc dcviccs arc used for short-tcrm storage and somc are used for long-tcrm storagc. A storo,gc devicc ean "memorizc" a bit or a group of bits and retai n the inronnation as long as necessary. Common types of storagc dcviccs are aip-flops. registers. scmieonductor mcmories. magnetic disks. magnctic tape. and optical d isks (CDs). A flip-flop is a bistable (two stable slatcs, logic circuit that can store on ly one bi t at a time, eithcr a I or a 0, Thc output of a nip-nop indicatcs which bit it is storing. A HIG H output indicatcs Ihal a I is stored and a LOW output indicates that a 0 is stored. Fli pfl ops are implemented with logic gates and arc covered in Chapter 7.
Flip- flOPJ
A register is formed by combining several fl ip-Oops so tllat groups of bi ts can be Slored. For cxam ple. an 8-bil register is constructed from eight nip-flops. In addi tion to SIOrl ll g bilS, registers can be used to shift the bils from one position to anotllcr within thc register or out of the regis tcr to anothcr circuit; thc refore, these devices arc known as shiJi registers. Shift registers arc covered in Chaptcr 9. Registef"l
cache are lemicooc.luctor . The regi.te... in a are corut:rud.OO of . Magnetic . used in the , the f1opP'( and for the CD-ROM.
18
•
DIGITAL CONCEPTS
The t WO basie types of shi.ft registers arc serial and paranel. The bits are stored in a.serial shirt register one at a lime, as iIIuslrated in Figure 1- 24. A good analogy to the serial shi ft register is lauding passcngcrsonlo a bus sing le fi le through the door. They also exit the bus single file . FIGURE 1 - 24
Ex
>l"'riallhift regilter. Edeh block represenll one storage
~cen~
or flip-
Srri.'" hI!' input Ii ~
un
0101 --1 0 0 0 0
nop.
010
Fiflit bit ( I ) is ~i ftcd
-
1 0 0 0
01 --1 0
o-
Initially. the ~gistCf"contains only i lU'lIlid 7.cros as shown h...'T"C.
data or all
1 0 0
1- 0 - 1 0 ,
serial ly into thc
"·giSler. Second hi t (0) is shifted seriall y into rcgisl<..T and li..,t bit is ilh ift...-d right. Th inl bit ( I ) is shifted into registcr and the fi('l;t and second bits arc shirt~-d right.
bit (0) is shiftcd into regi~er and the fits!.. sccood. <100 third bits an: shifled
Founh
right. 1bc l'C.si ster now and is r"JI.
stOfCS
all four hilS
The birs are stored in a parallel register simultaneously From parallel lines. lIS shown in Figure 1- 25. For this case, a g
Example of the operation of a
parallellhift register.
r:.If"J lld tlll\ (In
mput hn ....
0
1 0
1
1~~!:l1J I"j "'"y. "" ~O
",,'>OCT
j,,m.,.
conlalDlng only nondata 1.cros.
Semic:.onductor Memories Semiconductor memories arc devices typically used for storing large numlx::rs of bits. In one IYPC of memory. called the read-only memory or ROM . the binary dala are permanenrly or sem ipcnmlllently stored ~lIld cannot be readil y changed. In the random-access memory or RAM, the binary data are tempomrily stored and caO lx:: ea"i ly changed. Memories are covered in Chapter 10. Magnetic. Memories Mllgnetic disk memories are used for mass Slomgc of bi nary data. Examples are the so-called n oppy di sks used in computcrs illld the computer's internal hard disk. Magncto-nplieal disks usc laser beams to store ,1Ild retrieve data. Magnetic tape is still used in memory applications and for back ing up data from other storage devices.
The Counting Function The counting func tion is important in digital systems. There are mllny types of digital counters, but their bnsie pU'1)()Se is to count events represcnted by changing levels or pulses. To count, the counter must "remember" the prescnt number so that it can go to the
FIX ED - FUNCTION INTEGRATED CIRCUITS
ncxt prope r number in sequcnce. Therefore. storage capability is an irnpon am characteristic of all counters, and flip- nops are gCllcmlly used to implement thclll. Figure 1- 26 illustrat~ the basic idea ot" counter opcralion. Counters are covered in Chapter 8.
Counl~r
Parallel
JLJLfLJl.Jl. _ 2.
3
..\
OUIPU! !ioc.~
:'i
InptJI pul~
I
I
I
[he numbLT of inpul
ptltscs eoumed.
FIGURE l - Z6 IJIl1lOtriltion of oolic counter oper" tion.
I
-----------
SECTION 1-4
REVIEW
1. What does a comparator do? 2. What are the (our basic arithmetic operations? 3. Describe encoding and give an example. 4_ Describe decoding and give an example. 5_ Explain the basic purpo~ of multiplexing and de multiplexing. 6_ Name four types of storage devices. 7. What does a counter do?
1-5
FIXED- FUNCTION INTEGRATED CIRCUITS
Allthc logic clements and fu nctions that ha, rc been discussed are generally available in integrnted cireuit (Ie) foml. Dig itHI systems have incorporated ICs for many years because o fl.heir small size, high reliabi lity, low cost. and low power consumption. It is important to be able to recogni ze the Ie packages and to know how the pin conncctions arc numbered, as well as to be familiar with the way ill which circuit complex ities and cin:uittcchnologics determine the various ICclassifications.
After completing this section. you should be able
I
BUlar)" Hillary (}jour:' Bin"I)' Fl inary .·uoJc ",)tic L-.>tk: eu\c ewe fir I ~! ~3 ~ ..\ fi~:'i Sctj ucnce o f bi nar)" codo..-s Ih,lt TCpTeM-""Ill
10
- Recognize [he differe ncc between through-hole devices and surracc-mount fi xedfUncli on devices - Idcntify dual in-line packages (DIP) - Identi fy small-outline integrated circuit packages (SOIC) - Identify plastic leaded chip carrier packages (PLCC) - Ident ify Icadlcss rermnic chip carrier plIcku£es (LCCq - Detcrmine pin numbers on various types of IC packages _ Explain the complexity classifiCations for fixed-function ICs
A monolithic integrated circuit (Ie) is an electronic c ircuit that is constructed entirely on a single small chip of si licon. All the components that make up the c ircuittnmsistors, d iodes, resislors. and capacitors- arc an integral part o f that single chip. Fixed-fu nction logic and programmable log ic arc two broad categorit:s of digital ICs. In fi xed- function logic_ the logic fun ctions arc set by Ihe manufacturer and cannot be allered .
I
_
19
20
•
DIGITAL CONCEPTS
Figurc 1- 27 shows a Cutaway view of one type o f lixcd-funcl io n Ie packagc wilh lhe circuit chip shown within the paekagc. Points on the chip arc connected to (he package pins to allow input and output connections to the oulsidc world. FtGURE 1 - 27
Cutilway view of one type of frxedfunction Ie pi!Ckage showing the chip mounted imide, with connections to input and output pins.
Ie Packages Intc!:!nl.led circuit (lC) packages arc classilied according to thc way they are mounted on printcd circuil (PC) boards as cithcr Ihmugh-hole mounled or surfaec mounlcd. The throug h-holc type packages have pins(leads) thllt are inscnctl lhmugh holes in the PC board and can be soldered 10 conductors 0 0 the oppos ite side. 1llC most common Iype of thmughhole packagc is the dual in-line package (DIP) shown in Figure 1- 28(a). FIGURE 1- 28
Exilmples of through-hole ilnd sunare-mounted devices. The DIP is l.Jo,&er thiln the sole with the ~me number of lea~. This pilrticulilr DIP is ilpproximotely 0.785 in. long. and the SOIC is approllimiltely 0.385 in. long.
(OI l Dual
in-line pacl;agc (01 1')
(b)
Snwll-oo.l1tinc Ie (SOle)
Another type of IC packagc uses s urfacc-mount technology (SI\1T). Surface mounting is a spilce-saving alternativc 10 thmugh-hole mounting. The holes through thc PC board arc unneces~ry for SMT. The pins of surface-mounted Pftckagcs arc soldered directly to conductors on Olle side of the board, leaving the olher sidc free for additional circuits. Also, for a circuit with the :<;amc number of pins, a surfacc- mountcd package is much smaller than i1 dual in-line package bccllUSC the pins arc placed closer togcthcr. An example of a surfacemounted Pftckagc is the small-outli nc integrntctl cireuit (SOIC) shown in Figure 1- 28(b). Three common types of SMT packages are the SOIC (small-outlinc IC), Ihe PLCC (plas tic leaded chi p C'drrier), and thc LCCC (lcadlcss ccramic chip carrier). Thesc types of packagcs arc availablc in various sizes depending on thc nu mber of leads (more leads arc required for more complex circuits). Examples of each type lire shown in Figure 1- 29. As you can sce, thc Icads of the SOIC arc formed into a "gull- wing" shape. The Icads of the PLCC arc turned under thc packagc ill l! J-typc sh"pc. Instcild oflcads, the LCCC has melal contacts molded into its ccrl1fnic body. Othcr variations of SMT packages include SSOP (shrink small-oulline package), TSSOP (thin shri nk sma!l-outlioc packagc), and TVSOP (thin very small -outlinc packagc).
Pin Numbering All IC packagcs have a standard fonnat for numbering the pins (leads). -nlC dual in-line packages (DIPs) and thc sllli1 I1-outlinc Ie pi1ckagcs (SOICs) have the numbering arrangcme nt illus trated in Figure 1- 30(a) for a 16-pin package. Looki ng at the top of thc packagc,
FIXED-FUNCTION INTEGRATED C IRCUITS
FIGURE 1-29 ExilmpJe1 o f SMT pilckilge configu riloon1.
HIU. Em/ view
End view
End view
(a) sorc ,"'i lh
(b ) PLCC wit h
-gull -winM;" lcad-i
J-lypc
lcad~
(d LCCC with 110 leads (C()nlaclS arc
pan ur ca'C)
pin I is indicated by an idcntifier thl1t can be either a small dot, a nOtch, or a bevcled edge. The dOl is always next to pin I . Also. with the notch oricmed upward. pin I is always the top left pin. as indicalcd. Starting with pin I. the pin numbers increase a<; you go down, thcn ac~s and up. 1l1c highest pin number is always to Ihe right ofthc notch oropposilc the dot . The PLec lmd LCCC packages havc leads amlOged on all four sides. Pin I is indicated by a dot or other index mark and is located at thc center of one set of leads. ',be pin numbers increase going countcrclockwise as viewed from the top of the package. The highest pin number is
Pi n I
iOC01 ificr
'4.Mch
~" I
3
Pin numbering for two Itilndil rd
/ 19
typeJ o f Ihown.
,d.:milicr ... I
, , 2
"
4
4
6 7
"
8 (a) DlPor
Ie pilcki!gel. Top views are
sOle
13 (b) i'LCC orLCCC
Complexity Classifications for Fixed-function ICs Fixed-function digill!l ICs are classificd according to their complexity. They are listed here fro m the l ea~t complex to the most complex . The complexity figures stated here fo r SS !. MSI, LSI, VLSI, and Ul SI arc genera lly accepted, but defini tions may vary from one source to another. Small-scale integration (SSI) describes fixed-funCi ion ICs that have up to len equivltlent gate circuits on a single chip, and they include basic gates and nip-naps. Medium-scale integration (MS)) desc ri be~ intcgmted circuits that have from 10 to 100 equivalent gates on a chip. They include logic functions such as encoders. decoders, coumers, registers. multiplexers, anthmelle circuits, small memories. and othcrs. Large-scale integration (LSI) is a classificalion of ICs with complexities of from more than 100 to 10,000 equivalent gatcs per chip. including memories. Vel'"~: la~e-scale integnltion (VI...5I) descri bes integrated circuits with complexitics of from more than 10,000 to 100,000 equivalent gates per chip.
•
21
11
•
DtGtTAL CONCEPTS
Ultra la~-scale integration (UtS)) describes very large memoril:s, larger microprocessors, and larger single-chip compUicrs. Complex ities of more than 100.000 equivalent gates per chip arc classified as ULSI.
Integrated Circuit Technologies The types of transistors with which all integmted circuits arc implemented arc either MOSFETs (metal-oxide semiconductor field-cffocltrnnsistors) or bipolar junction transistors. A ein:uitlcchnology that uses MOSFETs is CMOS (complementary MOS,. A type of fixcdfunction digital circuit tcchnology that uses bipolar junction tnUlsistors is TTL (transistortransistor logic). BiCMOS usc... a combination of both CMOS ami rn~. All gates and other functions can be implemellled with either type ofcircuillcchnology. SS I and MS ! circuits arc generally available in both CMOS and TIL LSI . VLS I, and ULSI arc generally implcmented with CMOS or NMOS because it requires less area on a chip and consumes less power. There is more on these integrated technologies in C hapter 3. In addition, Chapter 14 provides a complete circu it-level covemge. Handlillg Preawtioru for CMOS Because of their particular structure, CMOS devices arc very sensitive to static charge and can be da maged by c1CClrost;tlic discharge (ESD) if not hilndled properly. The followin2 precautions should be taken when you work with CMOS devices:
CMOS devices should be shipped and stored in conductive foam. All instruments :!Od metal benches used in test ing shou ld be conneclCd to canh ground. '111e handler's wrist should be connected to curth ground with a length o f wire and high-value series resistor.
Do not remove a CMOS device (or any device for that matter) from a circuit while the dc power is on. Do not connect ac or signal voltages to a CMOS device while the de power supply is off.
I
SECTION 1 - 5 REVIEW
,. What is an integrated circuit? Z. Define the terrm DIP, 5MT, SOIC, 551, M51, LSI, VL51and ULSI.
l
3. Generally, in wha t dassification does a fixed -function IC with t he following number of eqUivalent gates fall?
(0) 10
1-6
(b) 75
(e) 500
(d) 15,000
(e) 200,000
INTRODUCTION TO PROGRAMMABLE lOGIC Prog rammable logic requires both hllJuware and sotiwarc. Programmable logic devices can be programmed to perform specified logic functions by the manufacturer or by the user. One advantage of progl1lmmable logic over fixed -function logic is that the devices u~ much less bomd space for an equivalent amount of logic. Another advalllage is that, with programmable logic, designs can be readi ly changed withuut rewiring ur replacing components. Also. a logic design can gcneml1y be implemented t~1ster and with less COSl with programmable logic than with fixed-function ICs.
INTR.ODUCTION TO PR.OGRAMMABlE lOG IC
After completing thi s section, you should be able to • Stme the major types of programmablc logic and discuss Ihc d ifferences . Discuss methods of programming • List the major programming langua!,cs uscd for progntmmable logic . Discuss the programmable logic dcsign process
Types of Programmable Logic Devices Many Iypes of progrmnmablc logic arc avai lable, ranging from s mall devices that can replace a Jew fixcd-fuocti on devices to complcx high-density devices Ihat can replace thousands of fixed-function devices. Two major c
fiGURE 1-31
Programmable logk.
Progmmmabic logic
I
I FPGA~
I
I
SPI~
CPLDs
Simple Programmable Logic Device (SPLD) The SPLD wa.. the OIiginal PU) and is sti ll avai lable for small-scalc applications. General ly, an SPLO can replace lip to ten fiXed-function ICs and their intcrconnections. depending on thc type of functions and the specific SPLD. Most SPLOs are in one of lwo catcgorics: PAL and GAL. A PAJ~ (progmmmable army logic) is a devicc thai can be PrQbT.J.mmcxl olle time. It consists of a progmmmablc array of AND gates and a fixed array of OR gales. as shown in Figure 1-32(a). A GAL (generic array logic) is a
==~
Progrummablc ANDarr:J.y
-
-=
I-IKt;d OR array a",!
OUlpullogic
~
, -=,,,, =,,, , , -= =-
(a) PAL
fiGURE 1_32
Block diagram! of !imple programmable logic deviCe! (SPlli).
(b) GAL
Rcpmgrammable AND Olrruy
-
~ !'iKedOR an'ily:md
programmable outPlJl lo~k
--=,,, ,,
-=
•
23
24
•
DIGITAL CONCEPTS
device that is b.'l.<;ically a PAL Ihal can be reprogrammed many times. It consists o f a reprogrammable ati"dy of AND gales and a fixed array of OR ~ates with programmablc OUpUL.., as shown in Figure 1- 32(b). A typical SPLD packagc is shown in Figure 1- 33 and generally has from 24 to 28 pins. FIGURE 1 - 33 Typica l SPLD
p
Ulmplex Programmable LogiC Device (CPLD) As technology pro~resscd and Ihe amount o f c ircu ilry thai could he pul on achip (chip density) increased, rranufacturcrs were able 10 put more limn one SPLD on a si ngle chip lUld the CPLD was born. Essentially. the CPLD is a device co nlainin~ multiple SPLDs and am rcphH.:e rmmy (jxcd-function ICs. Figure 1- 34 shows a basic C PLD block d iagram with four logic array blocks (LABs) and a programmable interconnection array (PIA). Depending on the speci fic CPLD, there can he from two to sixty-lour LABs. Each logic array block is rou~ hl y equivalent 10 one SPLD. FIGURE 1 - 34
General block diagram of a CPLD.
D-
c--;,,,
LAB
LAB
----= -,-= ,, ,
-'--=
c--2PIA
c::--c--;-, ,,
----=
LAB
=-'-
LAB
~ ,
,,
-'--c::>
Generally, C PLDs can be used to impJcrncnt any of the logic functions discussed earlier, for example. decoders, encoders, multiplexers. demult iplexers, and adders. They arc available in a variety of con figurations, Iypically nLllgin~ from 44 to 160 pin p,tcka~es. Examples ofCPLD packa~es arc shown in Figure 1- 35 . FIGUR E 1 - 35
(a) 84·pin PLCC package
(b) 128· pin PQFP package
field Programmable Gate Army (fPGA) An I· I'GA is gCllcntlly more complex and hilS a much higher density th"'l a CPLD. although their applicalions can sometimes overhtp. As mentioned, the SPLD and the CPLD arc closely rclaled because thc CPLD ba<;ically contains a number o f SPLDs. T he FPGA , however, hao; a di ffere nt internal structure (architcc-
INTRODUC TION TO PROGRAMMABLE lOGIC
•
PrtllT,mmmb!!: IntCI\"llIlt1CCfioo'
110
uo
110
block
blvck
block
00
-/ -
I/O block
110 block
block Logic bl ock
Logic
Log ic
block
block
Lot·
block
110
I/O bloc k
block logic
Logic block
Logic block
block
Log ic block
uo
110 block
block
l~ic
""," bloc!.:
block
Logic
Logic
block
bl od :
110
"0
""'"
bloc"
110
110
"0
uo
block
block
block
block
FIGURE 1 - )6 Ba~ic Itructure
01 an FPGA.
lure), a,.>; illustrated in Figure 1- 36. The three basic clements in an PPGA arc the logic block. t he prograrnmtlblc intcrconneClions, and the inpUl/outPUI (UO) blocks. The logic blocks in an FPGA arc not as complex as the logic ilfmy blocks (LABs) in
it
C PLD, but gcncmlly there arc many more of them . When the logic blocks are relatively simple, Ihe FPGA Ul'l:hitccturc is caJlcdjiJlc-grailled. When the logic blocks arc larger and more complex, lhe architcclUrc is called coaHc-grailletl. The va blocks arc on the outer edges o f the structure and provide individually selectable input, OUiput, or bidirectional 'lecess to the oUiside world. The d istributed progrnmmable interconnection mHlri x provides for interconncction of the logic blocks and connection to inpurs and outputs. Large FPGAs can have tens of thousands of logic blocks in addition 10 memory and other resou rce.~. A ty pical FPGA ball-grid array package is shown in Figure 1- 37. TI1C~ typcs o fIY
00 0 00000000000000000 00000000000000000000 00000 0 00000 0 0000000 0 00000 0 0000000000000 0 000 0 0000 0000 0000 0000 0 00 0 0000 0 0 00 0000 0 000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00 0 0 0000 0 000000000000000 00 0 0 00 0 0 000000000 0 0 0 00000000000000000000 0000 0 00 0 00 0000000000
FIGURE 1-37
A typical b,;,1J-grid arr;J)' piKk..lge
co .... figuratio .....
25
26
•
D IGITAL CONCEPTS
The Programming Process An SPLD, CPLD, or FPGA can be thoughl of as a "blank slate" Oil whidl you iHlplcl1lcJlt a specified circuit or syslCm design using a ccrtain process. This proces.c; rCtlui rc.c; a softw(lre development package installed on a computer to implemelll a circuit design in the programmable chip. The computer must be interfa(;e d with a developmcnt board or progr..mming fixture containing the devit:e. as ill ust rated in Figurc 1- 38. FIGURE ' - 38 Basic configur.... tion (or progr.... mming
.... Pl D or FPGA. t'rngl'llmm;tble dev ice
insl;tUt.'d 00 a tlcvclopmcn[ boIIni ~lId IIllcrconlll."Clcd wilh OIocr devices o n
Computer running HI)L .~oftware
Intt:rf...:c cable
[oc board t nol s hownl
Several steps, called the de.~i~1I floII', are involved in the process of implementing a digitallogic design in a programmable logic device. A block diagram o f a lypical programming process is shown in Figure 1- 39. As indicated. the design has access to adcsign library.
now
fiGUR E 1- 39 S.uic programlT\ilble logic: design
Dc!;igll.:nlry
flow blod< diagr.lm.
Design library
Functiooal simulmioo
Synthesis
I
I Timing simulatioo
I
Compiler
Download
Design Entry This is the first programming step. The circuit or system design must be entered illla the design application software usi ng text-based entry, graphic e ntry (schematic capture), or slate diagmm description. Design entry is device independent. Tex\-ba"cd entry is accomplished with a hard ware description language (I-IDL) sueh as VHDL, Verilog.
TEST AND MEAS UREMENT IN STRU ME NTS
•
AHDL, or ABEL. Graphic (schemat ic)entry allows prestOTed logic functions from a library to oc selected, placed on the screen, and then interconnected to creat(! a logic design. Statediagram entry requires specifi cation of both the states through which a sCQlIential logic ('ircuit progresses and the conditions that produce each state change. Once a design has ocen entered, it is compiled. A compiler is a program that controls the design now process and translates source code into object code in a format that can be logically tested or downloaded to a target device. The source code is created during design entry, and the object code is the fin al code that ac tually causes the design tobe implementcd in the programmable de"ice.
Functional Simulation The entered and compiled design is simulated by software to confi rm that the logic circu it func tions as expected . The simulation w ill verify that correc t outputs arc produced for a specified set o f inputs. A device-independent software tool for doing this is generally called a wOl'cfiJrm cdirOl: Any flaws demonslmted by the simulation wou ld be corrected by going back to design entry and maki ng appropriate changes. Synthesis Syntht'Sis is where the design is translated into a netli st. which has a Standard fonn and is device indcpendcnt. Implementation Implementation is where the logic structu res described by the netlist arc mapped into the actual structure orthe specific device being programmed. The implementation process is called firring or plClce Cll1d mille and resu lts in an output called a bitstream, which is device dependent. runing Simulation This step comes aft er the design is mapped into the specific device. T he tim ing simulation is basically used to confirm that there are no design Oaws or ti ming problems due to propagation delays. Download Once a bitstream has been generated for a specific programmable device, il has to be downloaded to the device 10 implement the SOftware design in hardware. Some programmable devices have to be installed in a special piece of equipment called a device pmg/'(lll/lI/eJ' or on a development board. Other types o f devices can be programmed while in a system--callcd in-system programming (ISP}--using a smndard JTAG (Joinl 1bst Action Group) interface. Some devices are volati le, which menns they lose their contents when reset or when power is tu med off. In this cao;c, the bilstream data must be stored in a memory and reloaded inlo the device after each resct or power-oft·. Also, Ihe contenls of an ISP device can be manipu lated or upgraded while it is operating in a system. This is called "onthe_ny" rcconfigtlration.
i
SECTION 1-6 REVIEW
1. li1t three major categorie1 of programmable logic dcvice1 aod 1pecify their acronyms. 2. How dOe1 a CPLD differ from an SPLD?
3. Name the 1teps in the programmiog procCSI. 4, Briefly explain each ltep named io question 3.
1-7
TEST AND MEASUREMENT INSTRUMENTS
Trouhk'Shooting is the process of systematically isolating. identifying. and corrccti ng a faull in a circuit or system. A va rie ty of instrumen ts arc avai lable for use in tTOllblcshooting and testing. Some common types of instrume nts arc introduced and discussed in this scction.
l7
28
_
DIGITAL CON CEPTS
Arrcr completing Ihis seclion. you should be ablc to _ Distinguish between an analog and a d igital oscilloscope _ RCt:ugni7..c common oscilloscope controls _ ()clemlinc amplilude, period, frequency, and duty cyele of a pulse wa\'e fonn with an oscilloscope - Discuss the logic analyzcr and some common formats _ Describe the purpose of the dc power supply, funClion gener-ltor, and digital lllultinlClcr (DMM)
The Oscilloscope The oscilloscope (scope for shOlt) is one of the most widely used inslrulTIe nts for gcnerdl testing and lroublcshooling. The scope is basically a graph-displaying device thallnlces thc graph of a measured electrical signa! on its screen. In mOSI applications, the graph shows how signals change over time. The vertical ax is of the display screcn represents vohage, and Ihe horizontal axis rcprcsenl<; ti me. Amplilude, period. and frequency of a signal can be measured using the oscilloscope. Also, Ihe pu lse width, dUly cycle, rise time, and fall time of a pulse waveform can be determined. Mosl scopes can display at least two signals on the screen at one time, enabling Ihe ir lime relationship to be observed. A typical oscilloscope is shown in Figure 1-40. FIGURE 1 - 40 A typica l dual-channe l cncillcncope. Vied with permilSion from Te ktron ix,
'""
Two basic Iypes of osc illoscopes. analog and digital. can be used to view digital waveforms. As shown in Figure 1-4 I(a), the analog scope works by applying thc measured waveform dinx tly to control the up and down mot ion o f thc electron beam in the l:alhodemy tube (CRT) as it sweeps across the displ ay screen. As a res ult. the beam traces oulthe waveform pattern on the screen . As shown in Figure 1-4 I(b), the digital scope convens the measured wavefom1 10 d igital infommtion by a sampling process in an analog-todigita l converter (ADC ). The digital information is thcn used to reconstruct the wavc form on the screen. The digital scope is more wi
TEST AND MEASUREMENT INSTRUMENTS
•
FIGURE 1 - 41 Com~rjKln
or ilnalog and digital
mcilJmcopes.
(b) Digital
(II) Analog
To measure a vohage, a IlNlbc must be connected from the scope to the point in a circuit at which the vohage is present. Generally, a xlO probe is used thai rcduce!; (attenuates) the signal amplitude by ten. The signal goes through Ihe probe into Ihe vertical c ircui ts where it is either further allcnuatcd or amplified, depend ing on the actual amplilUde and on where you SCI the vertical cOlllrol of the scope. The vertical ci rcuits then d rive the vertical denccLion pl ates of lhe CRT. Also, the signal goes La the triggcr circuits that trigger the horil.onla l circuits to ini liatc repet itive horizonlal sweeps of the electron beam across the screen using a sawtoolh waveform. Therc are many sweeps per second so that the beam appears 10 fo rm a solid line across the screen in lhe shape of the waveform . This basic operation is illustrated in Figure 1-42, Bmic Operation of Analog Oscilloscopes
FIGURE 1 _ 42
Oscilloscope
Block diagram of iln analog oloCiUolCOpe.
Vcrt icul cin;Il;\s
Triggrrcircll;ts
Horizontal circu its
Basic Operation of Digital Orcillou:opes Some parts of a digital scope arc similar to the analog scope. HO\\.'cvcr. thc digital scope is more complex than an analog scep:: and typically has
29
30
•
DIGITAL CONCEPTS
Oscilloscope
Acquisition circuit,
UHOOll;: Ol"O---,-_,
Yeniclll drcuits
l nl OO li 01 0
Tn~gcrcircuilS
-
lIori ~.onUll
RC<."'O!lstruction and di.play circuits
circuits
fiGURE 1 - 43
Block diilgram of iI digitill oscilloscope.
The (jara then goes (Q the reconstruction and display c ircuits for display in its original analog form. Figure 1-43 shows a basic block diagram for a digital osci lloscope. OIO'lIOfCDpe Controls
A front panel view of a Iypical dual-channel oscilloscope is shown in Figure 1-44. Instruments vary depending on model and manufacturer, but most have certain comlllon features. For example. the two vertical sectio ns contain a Position control, a channel menu bunon. and a V/div control. The horizontal section conta in'> a seddiv control.
..,.. ~
0=
t;;I
_._.
~O·:b~O - ,
-
""'" I;;l
''0' 0..
HORIZOHT.ot.
~
_- ,---
- 0 c:Jc:J - -_. -c:J 0 .- 0.. ,- Q -c:J ,.,
Q
..'<£>
~
-J ~ ®l "
~,
"A
~.
~~
~
fiGURE 1-44
A typica l dual-channel oscill()I.Cope. Numben below screen indicate the value1 for eacll division on tile vertical (voltage) and Ilorilontal (time) scales and can be ...aried uiing the \oeltiall ilnd horizontal controll on tile scope_
TEST AND MEASUREM ENT INSTRU ME NTS
•
31
Some oflhe main oscilloscope controls arc now d iscussed. Refer to the uscr manual for complete dctails of your particular scope.
Vertical Convoh In thc vertical section of the scope in Figure 1-44, thcre arc identical eonlm ls for each of the two channels (CH I and CH2). The Position control lel<; you move a d ispl ayed waveform up or dow n velt ically on the screen. T he Menu button provides for the selection of scvcral items that appear on the screen, such a<; the coupling modes (ae, dc, or ground). coarse or fi ne adjustment for the V/div, probe auenuatiOIl. and other parametcrs. Thc Vldiv control ildjusts the num ber of volts represented by each vertical division on the screen. The VIdiv .'..1<;0. it allows you to observe time de lays between two waveforms. Figure 1-45 compare.<; a triggered loan untriggered signal. The untriggered .<;ignal tends to drift across the screen, producing what appeal1' to be multiple waveforms. FIGURE 1 - 45
CompariK)fl of an untriggered and a triggered waveform on an OSCiflOKOpe .
(a) Unlriggered waveform display
(b) TrigSered waveform display
Coupling a Signal into the Scope Coupling is tht: method used 10 connect a signal voltage \0 be measured into the oscilloscope. DC and AC coupli ng are us ually selected from the Vertic
J2
•
DIG ITAL CONCEPTS
FIGURE 1 - 46
Displil)'S of the k'me w.weform having a de component
(3) OC coupled l'o'llVeform
(b) f\C coupled waveform
FIGURE ' - 47
An oscilloscope VOltage probe. Used with permission (rom Tektronix, Inc.
have a series resislance ten times larger than the inpul resistance of the scope are called ><10 probes. Probes with no series resistance are called x l probes. The osci lloscope adjusts its calibration for the attenuation of the type of probe being used. For most measurements, the xlO probe should be used. However, if you are measuring very small signab, a x l may be the best choice. The probe has an adjustment that allows you to compensate for the input capadlancc of the scope. Mosl scopes have a probe compensation output that proviues a calibrated square wave for probe compensation. Before making a mea<;urcmefil , you should make sure that the probe is properly compensated to d illlinate any distortion introduced. Typically, there is a screw or other means of adjusting compensation on a probe. Figure 1-48 shows S(;opc waveforms for three probe conditions: properly compensatcd, undereompcnsatcd, and overcompensatcd. If the wavefonn appears eithcr over- or undercompensated. adjust the probe until the properly compensated square wavc is achieved.
Properly compensalt.'II
O,·ercompellsall.""tl FIGURE 1 - 48
Probe compensation conditiom.
TEST AND MEASUREMENT INSTRUMENTS
•
Bascd on thc readouts. determine Ihe amplitude and the period of the pulsc waveform on the sereen of a digil3J osci lloscope as shown in Figure 1--49. Also. calculate the freq ucncy. FIGURE
Solution
t - 49
The V/div setting is I V. 111C pulses arc three d ivisions high. Since eaeh division represcnt.. I V, Ihe pulse amplitude is Amplitude = (3 div)(I V/div) = 3 V The sec/djv sctting is 10 p.s. A fu ll qcle of thc wavcfonn (from beginning of one pulsc to the beginning of the next) COVCl'S four divisions; thcrefore. the pcr'ioo is Period = (4 di" )( 10 p.s/di v) = 40 P.s The frequency is ealr.:ulated as I
I
T
40 J,LS
f = - = -- = Related Problem
25 kHz
For' a V/div selling of 4 V and secldiv sell ing of 2 ms, detcrmine the amplitUde and period of the pulse shown on the screen in Figure 1-49.
The Logic Analyzer Logic analyzers arc used for measurements of multiple digital signals and measurcmcnt si tuations with difficult trigger req uircmenL~. Basically, the logic analyzer came about a'i a result o f microprocessors in which troublcshooLing or de buggi ng required many morc inputs than an oscilloscope offered . Many osci lloscopes have two input channels and some are available with four. Logic analyzers are available with from 34 to 136 input channels. Gencrally. an oscilloscope is used either when amplitude. frequency, and other timing paramete~ of a fcw signals at a time or when panlmeters sut.:h an rise and fal/times. overshoot. amI delay ti mes need to be memmred. The logic analyzer is used when thc logic lcvels of a large number of signals need to be determined and for the correlalion of simultaneous signals based on their timi ng relationShips. A typical logie analyzer is shown in Figure I - 50. and a simplilied block lliagrdTn is in f igure I- 51. TIle large number of signals that can be acquired al onc time is a major factor that distinguishcs a logic analyzer from an oscilloscope. Generally. the two types of data acquisition in a logic analyzer are the liming acqu isition and the slate acquisition. Timing aClJuisition is used primarily when the timing relationships among the various signals
Data AcquiJitiOlI
33
34
•
DIGITAL CONCEPTS
FIGURE I - 50
Typical logic ;,n;,lyze r. U~ with perminion from Tektronix. Inc.
fiGUR E I - 5 1
Simplified bled<. diagram of a logic ;,nalyzer. Own"",1
--
illru!~
Input buffer
,,"
Acquisition memory
SIImpl ing
Analysis
,""
di~play
I Clock circuitS
_
Trigger logic and memO!')' oomrol
need to be determined. Statc acquisition is used when you need to view the sequence of states a'i .hey appc'ar in a system under test. It is often helpfu l to have corrc-iated timing arn.! state dala. and Illostlogie analyzers can simultaneously acquire that data. For examplc, a problem m
TEST AND MEASUREM ENT INSTRUMENTS
•
ing Lhe values of the inpw waveforms (I s and Os) at various points in time (sample points). Ty pically. Ihis dala can be displayed in hexadecimal or other formals. Figure I- 52 shows simplified versions of these two d isplay moc.lcs. The listing display samples correspond to the sampled points shown in red on the wavcfonn d isplay. You will study binary and hexadecimal (hex) numbers in the ncxt chapler. fiGURE' -52 1\\10 logic analyzer display modes.
123~567b
(a) Wavcfnnn displ ay
(b) Li stin g display
Two more modes Ihal are useful in computcr and micropnx:essor-based systcm testing are the instruction trace and the sourcc code debug. The instn.lction trace determines and displays instructions that occur, for example, on Ihe data bus in a microprocessorbased system. In this mode the op-codes and Lhe mnemonics (Engli sh-like names) of instructions afe generally d isplayed as well a .. theif corresponding memory address. Many logic analyzcrs also include a source code debug mode, which esscntially allows YOll to sec what is actually going on in the system under test when a program instruction is cxecuted. Probru Three basic types of probes arc used with logic analyzers. One is a mult.ichannel compression probe that can be auached 10 points on a circuit board, as shown in Figure I- 53. Another type of multichannel probe, similar 10 the one shown, plugs into dedicated sockets mounted on a circuit board. A third type is a single-channel clip-on probe. fiGURE 1 - 53 A typica l mu ltichaonel logic ana lyzer probe. Used with permiiSion from TektroniK, Inc.
Signal Generators Logic. Signal Source lliese inslrumenL" arc al!>!) known as pulse generators and pattenl generators. TI1CY arc specifically designed to generate d igital signal ... with precise edge
35
36
•
DtGtTAl CO N CEPTS
placement and amplilUdes and 10 produce the streams of Is and Os nccded to lest computer buse~, micropn..x.:cssOr.i, and olhcr digital systems.
Arbitrary Waveform Gene,.aton and Function Generoton The arbilmry waveform generator can be lIscd to generate standa rd sign'l/:, like sine waves. tri~llgu l ar waves. and pulses as well as signals wi th various shapes and I:hanlcleristics. Wavefonns can be defined by mathematical or graphical input. A typical arbitmry waveform generator is shown in Figure 1- 54(a). The func tion generator prov ides pulse waveforms as wel l as si ne wave.~ and triangular waves. Most fu nct ion generators have logic-compatible outputs to provide thc proper level and drivc for inputs to dig ital circu its. Typical func tion generators arc shown in Figure 1-54(b).
~I (a) An
~rbilr.\ry w~vcforll\
gcncr;\lor.
11>\ E,;\\mplcs of function gl'llcnmJl1l. FIGURE 1 - 54
Typica l signal generaton. UJeO with permission from Tektronix, Inc.
The Logic p,.obe and Logic Pulse,. The logic probe is a convenie nt. inexpens ive handheld tool that provides a means of troubleshooting a digi tal ci rcuit by sensing va rious condi tions aI a point in a circuit. as ill ustrated in Figure I-55 . The probe can detect highlevel voltage, low-level voltage, single pulscs, repet itive pulses, and opens on a PC
Lamp
00
= IIIG It
Lanlp off = LOW
._ ,....... One Ilash : single pul se
FIGURE 1-55
IIl uJtration of how" IOgi( pulser and" logic prob.: Q n be l).eeI to apply" pul,e to a given point and check for rcsulting pulse activity at another part of the ara.oit.
TEST AND MEASUREM ENT INSTRUME NTS
•
37
board. 11le probe lam p indicates the- condi tio n that ex ists at a certain point. as indicated in the fig ure. The logic pulser proo uccs a repetitive pulsc waveform that can be applied to any point in a circuit. You can apply pulses a1 one point in a c ircuil with the pulscr and check another point for resulting pulses with a lugic probe.
Other Instruments Th e DC Power Supply This inSlrument is an indispensable instrument on any test bench. The power supply converts ac power fro m the sta ndard wall outlet inlo regulated dc voltage. All dig ital circui ts requ ire de voltage. Many logic circuits require ·1 5 V or + 3.3 V to operate. The power supply is used to power circuits duri ng design. development, and troubleshooting when in-system pov.·er is nOi available. Typical test bench de power supplies are shown in FiguTC I- 56.
FIGURE 1 - 56
---
~ -- --
... ...-_-...-...
Ii •
--
17'11
a Iq 3
TypiCilJ dc power 1uppJies. Courte1y of B+ K Preci~icn .
"-
Th e Digital Multimeter (DMM) The DMM is used for measu ring de and ac voltage and resistance. Figure I-57 shows typical test bench and handheld DMMs .
... FIGURE 1-57
e.
••
Typicnl DMMs. Courre.y of S + K
., .
e.
." •
i
SECTION 1 - 7
REVIEW
Precilion.
.
1. What is the main difference between a digital and an analog oKilioscope? Z. Name two main diffe rence~ between a logic analyzer and an O1cilloscope7 3. What does the V/div control o n an oscilloscope do? 4 . What dOe1 the 5ec/div control on an oKilloscope do?
5. What;1 the pu rpo1t! of a function generato r?
38
•
DIGITAL CONCEPTS
to (..,11 into a bottle on the cooveyor belt
in p".ra ll e ' to the A inpu t of the adder.
of tableb going into each bottle and diiplil)'la continu.)lIy upda ted tou l nea.r
The B input o f the add e r comel from P"''''"e l regilter B thlt holds the total
the com.oeyor line as ~II al a t a remote loa.tion in another part o( the pli'Ol This system utili2C!. a ll the b...lic logic functiom
number of bblcb bottled, up through the l.lIt bottle filled. f or example, if ten bott.lcJ have been filled aOO exh bottle
thiltwere introduced in Seaioo 1-4,
hokl! fifty r:.wlcb, register B cont.linl the bin.,ry representation fOf SOO. Then, when the next bottle ha. been filled, the binary numbel fOl 50 appea rs on the A input o f the .,dder, and the binary number for 500 is o n the B input. The adder produces a new l....-n o f 550, whic:h illto red in regilter B, replacing the p,eviOVI lum of 500. The I»IliII)' number in regilter B il transfer~ in p;.r..llel to the code converter and da::oder, ",*"ich changt!"l it ITom bin.)ry fonn to de6o'rW form for d ilplil)' o n a readou t neolr the coOTVt:)'Ol' line. The binary nu mbe r in the regilte r il ...110 tr".rnferred to a mu ltiplexe r (mux) 10 tholt itCMI be converted from paralle l to ~ics form.lnd uarnmitttd .)Iong a lingle line to a remote location lOme dKbnce ".way. It is more ccoflOf"l'lic:.od to run ... linsJc line th.vl to run ~al p.l~leI'inC1 when ligniflC,).(\t d ilbnces are im.clved, .:Ind lpeed of dab tranlmi"ion ... not a factor in thisappliGItion. At the rt'lllOte 10000tion, th .. .,.ri,,1rf"t'" ar.. rl""", I~plexer1 ..."rf K'f't to regilter C. From there the data Me then decoded fOf d isplay on the remote rC.lCfoul Keep in mind th.)t!:"" 1~tem Ii purety "" instructional model aOO doC!. not nete Of fTlOIt efficient way to implement this hypothcticll prOCC!.1. Although there are certainly other appfO;lChe, thi1 partiOJl.ar approach n..1 been u~d in order to ill ustrate an appliC.ltion of the logic: functions tn..t were introduced in Section 1-4 and that"""" be covered in deUil in fu ture ch
it! only purpose is to lhow you how I:t-6e functiom may be combined to .)(;hieve .. desired resu lt.
In thi1 digibl ¥tem ... ppliGlotion (051.), a
The gene ",,1ope""tion is al (o1lO'M. An opoc...l seruor at tile bottom of the funne l neck detecb e;och L'IbIet thlt ~SeI and
~irnplified J)'!'tem "PP1ic.ltion r:i the logic:: dcmcnb
goeJ to the counter .,nd adv..ncc$ it by one
d ilC\.lJied in Section 1-4 Ii prCloCnted. It il irnport.lnt thlt you Undcl"ltolod how
count; thus, .)tMl)' time dUl"ing the Illiing o f ... bottle, the counter conUins the
Vo'Irious digitAl functions Co'Ifl opcr... tc together ," a totol ¥tcm to perform a ~cified task. It Is ..110 importol nt to begin to think in terms o f ')'Item-leve l ope""tion
btnary reprcscot.ltion r:i the number of b bleb in the bottle. The ~ry coont is traooelTed from the cou nter on parallel lino to the B input of the compa"'lo1
beaUle,
work will
in p ractice, a la rge p.'Irt of )'Qur in..ot..e I~term rather than
iodividUil I functions. Of cou rse, to underst
In t he di1p lay portion of the 1)"Item, the n umber in the counter il tr>lnlfe rred
below. The digiU I I)'Item control! the numbe,
produce! .. n e lectric.'" pulse. This pulse
(comp). A preset bin." y number equal to the OlI mber of tab lcb thlt arc to go into
each bottle is pl..c.ed on the A input of the COlTlpa""tor. The preset number COfTlC!. from the keyp;td and the
-.
application o f the various functional
deviccI ilt the l)'Item level
SUMMARY
•
On-site display
Register A Nu mbcr o f tablets per boule
Keyp;1d for elllering llUmber of mblet.\ per bollie
Oi llll,.)' code for prcsct ""mbC!" oflabicis JX.T bun k
C"'"
,
converter
HIG H closes va l\'e and ativances cotl\"eyol'. LOW
Jl
0
,
,
II
,_
Counter
r+
ad\'llilCC!;
A
r
8
C~
I.
-
Pul se re:;cls OOll" lcr to leJO when nu t boUle is in place .
, b'''ry ,"'" f",,'.. ;'C 'OO :::!'c:' h:i'C ' :li:..
~' "..
,
0
B
-
On-site displa)' of
B
,, ,, ,,
One ptJlsc from ~IISOI for ~dCh 1able1 Ctll'llllT by
Comp
Bili ary cotle for UClual llumberof tablel~ in bou le
~. ,~'" "','e",.",
Senl'(
"4 ,
total tablets bOll iL'd
550 t
New lotal sum
~ ,
Register B
r+'
HI GH causes new SUlTlto be ~tored.
COO,
lX'Coder B
cal~crte
MUX
Jl
m"" "",h',,, 'm,,',,"" '0 ,"","o'm
'"w, wm
l
' t.
:.:f:"'Cre=":ID:':':dC""':"C'}C':":'~:.:':m:""C':":":':"C":':":"cryc:OO:"C'Cf:i'C'______________ ~
[
DEMUX
...
",gl"~C '"
,Jtt""'" C
00=",
,
...
t
S"ilch ing seq uence cOIltrol input
550 Remote unit
FIGURE 1 - 58
Simplified bMic:: block dillgnm for" bblet-counting lind bottling control system.
•
An analog quanti ty has continuous values.
•
A di gital quant ilY has a discre .... set of values.
•
A binary dig it is called II b it.
•
A pu lse is chardcler izcd by risc lime, fall t ime, pu lse width, and amp lit ude.
39
40
•
DIGITAL CONCEPTS
•
1nc Ih :
T
•
!
The duty cycle of a pulse wave fonn is the rati o of the pulse width to the period, expres.'iCd by the following formula as a percentage: Duty cycle ""
C;)
100%
•
A timing d iagram is an arrangement of two or more waveforms showing t~ir relatiooship w ith rcspct; t to time.
•
T hree basic logic operations arc Nal: AN D. and OR. The stanrnml in Figure I- 59.
FIGURE
for these are given
'-S' "CIT
•
symbol~
AND
OR
1bc basic logic functions a rc comparison . ari thmetic, code conversion, dc«ding , encoding, data
selection, ~tornge. and cou nting.
KEY TERMS
•
The two brOi.ld physical cmegories of Ie packages a rc through-hole mounted and surface mou nted.
•
The ca tegories of I C~ in terms of ci rcuit complexi ty arc S51 (s mall-scale int~gralion J, MS I (medium-scale integration). LSI. VL'51. and ULSI (large-scale. very large-scale, and ultl1l largescal e integration).
•
Two types of S PLDs (simple prognunmablc log ic dev ices) a rc PA L ( progmmmable array logic) aod GAL (gene ric affilY logic).
•
l "e C'PLD (complex progrOlmmable logic dcvK:eJ contains mult iple S PLDs w ith programmable interconnections.
•
'I"e t-t'GA (field progTUlllmllble gate 8mly) has a di lTerel\{ interna l structure than the CP LD and is genera lly used fOT more com plex circuits and systcms.
•
Common in.~tn1mcnts used in testing and trouble shooti r,g dif!i tul Circlli ts are the oscilloscope, logic analyzer. waveform gene rator. function generator. de powe r s upply. digita l mu llimcler. logic probe, and log ic pu rser.
Key te,rru and other bold terms jn the c hapter are defined jn the end-of-book
~Ims;>ry.
A nalog Being conti nuous or having (."OOti nuous values. A ND A basic logic opcmlion in wh ich a true (HIGH) outpu t occurs only when all the in put condi tions are true (HI G H). mnllry Ilaving two va lues Of states; describes a n umber ~ystcm that has a ba'iC of two a nd uti lizcs I lim] 0 as its digit~.
nit A bi nary digi t. which Clm be either a l ora O. C lock The bas ic timing signal in a d igi tal s yste m ; a periodic wavcfonn in wBch each interval between pulses equals the time for one bit. Compile r A program that cont,{)l ~ the dc~ ign now pmccs~ "nu t ~ n~ tatcs source::otlc inloobj (,ct <.X><.lc in a fo nna! that can be logica lly tested Of down loaded to a tm-ge! device. CPLD A complex programmable logic device that consists basically of mu ltiple S PLD alT'dys w ith program mab le itl tcrcon ncc t i on.~. Il'dta Information in numeric, OI lphllbctic. or other form. Digital Related to dig ils or d iscrete quantitics; hav in g a set of di sc rete values.
SElF.TEST •
41
FPGA fkld programmable ga le array. G ate A logic circuil that performs a
~pcci f1cd
logic operation such as AN D or OR.
Input The signal or line going into a circuit. Inlegr.!ted circuit (IC ) A type of cin;uil in which all of the compunents arc chip of scmiC{)fld uctive materia l of extremc1 y small sizc.
illle~ratCI.I
on a
~ing le
Im'et1er A NOT circ uit; a circui t that changes a IIIG ll lo a LOW or vice versa. Logie In digi t1l1 electron ics, the dl'Cision-llmking capability of gale circu its, in which 11 I·IIGU represe nts a true stntcmen\ and a LO\V re presents a false o ne.
NOT A b."lsic logic opcrlltion Iha t
perfOl1n~ iIW\..,.s ioll~.
OR A basic logic opemtion in which a Ime (I IIGI I) OUlput occurs when ol1e or more of the input conditions are true (HI GH). O utput The signal or lil1e coming out of a cireuit. l'lmdlel In digital systems, d."lta ot:curring simullUllcously on scvcnll lilles; the transfe r or proccssillg of several bils simu ll aneously.
Pulse A sudden ch.lIlge from o ne levc1 to ilnothcr. followed after (I time. called Ihe pulse w id th. by a sudden change bac k to the o riginal level. Serial I hIV in g One clement followi ng another, as in
SI'LD Simple programmable 10llic device. T iming d i:lgram A graph of digi t(ll waveforms showing Ih: time relationship of t.....o or more wavefonns. Troubleshooting Thc techniq ue rau lt in a ci rcuit o r system.
proccss of systematicall y idcnt.ifying, isolal.ing, an d correcting a
01"
Aruwen are at
I. A quantity having cont inuo us \'lI luC"S is (a) a digital quantity
(b) nn annlog quant ity
(c) a binary q uantit y
Cd) n nntunll qUllntity
2. The term bil means (a) a small amount of data
(h) '1I o r a (l
(e) binnry digit
(d) both answer.-; (b) and (c)
3. The time imerval on thc ie(ldillg edge of a pulse betwcc n I {)% and 9(1% of fhe amplitude is the
(II) fall lime
(a) rise time
(c) pulse width
(d) pcrior.\
4. A pulse in n certain w!wc fo rm occurs evcl)' I (l ms. The fn.'q uL'I1cy is (a) I kHz (11) I Hz (c) 100 liz (d) 10Hz S. In a certain digital w'lvcform. the period is tw icc the pulse width. T he duty cycle is
(a) 100%
(ll) 200%
(c) 50%
6. An inve rter (a) performs thc NUl" operation
(b) changes a HIG H to n LOW
(c) changes a LOW to a IIIGII
(d) docs a ll of the above
7. The ou tpu t of an AN D gatc is HI G I-I when (a) any input is HlG II
(b) a ll inpu ts are I-IIG H
(e) no inpuls arc HIGH
(d) both answers (a) and (b)
It The ou tput of an OR gate is HI G H when (a) (lny illput is HI G H
(b) all inpu ts arc HIG I I
(e) no inputs nre HI G H
(d) both
9. The device uscU to convert a binary Illlmbcr to a 7-segment display fommt is the (a) mu l1 iplexcr
(ll) cncor.\er
(e) decoder
(d) register
42
•
DIGITAL CONCEPTS
10. An e";ilmple of a data slorage devicc is (
(b) the nip-nop
(d) the register
(e) both answers (b) and (d)
(e) the wmpardtor
I I. A fixed-funct ion Ie pac kage containing four AND g:lles is an c,.;ampJc of Ie) sOle (d) S5 1 (a) MSI (b) SMT 12. An LSI devicc has a circuil complc,.;ily of from (a) 10 10 100cquh'alem gmcs
(b) morc than 100 to 10.000 cqui va lem gales
(e) 2000 10 5000 cquinl/cnt gates
(d) more than 10.000 10 I OO.CXXl equivalen t gates
13. VHDLi s a (a) logk dcl'ke
(b) PLD progra mming language
(c)wmputcr language
(d) vel)' high dens it y logic
14. A CPLD is a (a) eont rulled prul!fllm logic deviee
(II) t:umple,.; programmable Iq'!ic drivCf
(el comple,.; programmable logic dcvice
(d) ecn tral processi ng logic device
15. An FPCiA is a
PROBLEMS SECTION 1 - 1
(01 field programm<1ble gale array
fbi l'ast progra nunable gate array
(c ) lield progrommable ge neric ilmly
td) n a.~h process gate appliClITion
Ano;wen to odd- nu mbered probleml ~re 3t the end of the book.
Digital lind Analog Quantities I . Name two advantages of digital data as comp
SECTION 1 - 2
Binary Digib, LogiC Levels, and Digital Waveforml 3. Defi ne Ihe 1;/.:q uellCC of bits (I s and Os) represe nted by each of Ihe following seq uences of
le vels:
(a) HIGII. HIO I I, LOW, HIGH, LOW, LOW, LOW. HIGH (bl LOW. LOW. LOW. HIG H. LOW. HIGH. LOW. HIGH. LOW
4. List lhc sequence of Icvcl ~ (H IGH und LOW) Ihut represcn t ea(;h of the following bil seql.lCnces:
(al l O I I I O I
(b) 1 1101 00 1
5. For the pu lsc shown inl-lgure 1--60, graphicall y dC lenn ine Ihe following:
(a) .-ise time
(b) fall time
(e) pulse width
FIGURE 1- 60
(d) amp lit ude
I
10 r nnn17
o 2
6. Detcmtinc the period of the digil,1l waveform in Figure 1--61 . 7. What is the frequency of lne wavcfonn in 1-1gure 1-6 11
3
,
PROBLEMS
•
43
8. Is the pulsc waveform in Figure 1- 6 1 pcriook or no npcriod ic?
9. Deternlinc the duty cycle of the wave form in Fig ure 1-61
p
v
0
;
3
CJ , CJ CJ CJ 7
11
9
I 15
13
• I(rru.)
17
FIGU RE 1-61
10. Determine the bit sequence represe nted by the wavcfon n in Figure 1-62. A bit ti,ne is I J.IS thi s casco
I I. What is the tOlal serial transfer time fo r thccighl bit!; in Fig ure 1-il2? What transfer time?
,,, 4J1s
,, ,,,
i~
the total pl.lnlliel
,
,
,
5J1s
6p>
,, 7 JIS
8ps
FIGURE 1-6 2
SECTION 1 - ]
Basic Logic Operations 12. A logic circuit requires U IGHs on all ils inpu ts to mak.e the outpu t H IG H. What Iype of logic circuit is it'] 13. A ba~i c 2-inpul logic cir!.:uil has a 1-I1GH output is LOW. Identify the circuit.
IHl
nne input and a LOW o n Ihc (Jl hcr inplu, and the
14. A basic 2-mput logic circuit has a HIG H on o ne input ami a LOW on the other input, ami the ou tput is I-IIGI·I. What type of logic circuit is it?
SECTION 1-4
Overview of Basic logiC Functions lS. Name Ihe Jogic functi on of each block in Figure 1-63 based on your ubservation of the inputs and OU lput ~.
, ,
;
HIG H -
6 -
II
1.0 ..... LOW
)
)
HIC,H
(,)
(b)
(c)
-
- - HIGH
- n ;0'l
- - LOW
7
- - t ()\\
Select inputs (d)
FIGURE 1 - 63
J 6. A pulse waveform with a frequency of 10 kH z is upplied to the input of a countCf. During 100 ms. how many pulses are cou nted? 17. Consider II regi ster thaI en n store eight biK A~ulnc Ihal il hns been rcs(.'1 so that il conlains zcros in all posit ions. If you transfer fOuf alternating bils (0 101 ) seriall y into the register. beginning w ith 1\ I and shifting 10 the rig hI, what w illlhe total contenl of the register be as soon as the fomth bit is Slored?
44
•
DIGITAL CONCEPTS
SECTION 1- 5
Fixed-Function Integrated Circuits 18. A fix:cd-fu oction d i{!ital IC chip has a complexity of 200 eq ui vale nt gmes. How is it classified? 19. Expla in the main diflcrcncc between thc DIP and SMT packages.
20. I...abc l lhe pin nu mbers on the pllckages in Figu re 1-64. Top views are shown. FIGURE 1-64
(b)
(.)
SECTION 1-6
Introduction to Programmable logic 21 . Wh ich o f the follow ing acronyms do not dc."Cribe progrn mmable logic?
PAL, GAL. SPLO. ABEL. CPI.D. CUPL. FPGA 22, Whal do each of the follow ing Siand foc'! (a) SPLO
(b) CPtD
(d) FPCA
(c) HOI...
(e) GAL
23. Defi ne ellch o f Ihe follow ing PLO programm ing terms: (a) design entry
(b) s imulation
(c) compilation
(d) d ownload
24. Desc ribe Ihe process o f place-and -mute.
SECTION 1- 7
rest and Measurement Instruments: 25. A pulse is d isplayed on the sc reen of an oscil loscope. and you measure the OOfiC line a" I V a nd the lop of the pu lfiC
a.~
8 V. Whll! is the amplitude '!
26. A logic probe is applied 10 a contact point on a n IC Ih:lI is opcrlIting in a system. The lump 011 the probe flashes repemedly. What docs Ihis indicate'!
SECTION 1-8
Digital System Application 27. Define the lenn system. 28. In the system de picted in Fig ure I-58. why a re thc mu ltiplexe r and lIern ultipl ex:er I1CL""C""ary? 29. What 3(.1ion can be taken to cha w,;e the number oftablelS per botdc in the system of Figure I-58?
SECTION REVIEWS SECTION 1- 1
Digital and Analog Quantities I. Ann/os means continuous,
2. Digita/ means discrete. 3, A di~i t al quami ly has a d iscrelc SCI Qf values and an analog qU !l.l1lilY has cont inuous v3 lucs. 4. A public addrcs.<; sys tem is Malog. A CD playcr is a lh110g and di gita l. A COIllpulcr is a ll di g itaL
SECTION 1 - 2
Binary Digits:. Logic Levell, and Digital Waveforms 1_ Binary meanS having Iwo Siales or va lues. 2. A bit is a binary dig it. 3. The bi ls are I and O. 4. Ri se time; from 10% 10 9O% ofampl it ud e. Fall time: from 90% to 10% ofam plitudc.
5. 6. 7. 8.
Frequcncy is the fCC ipt"OCa l of the period.
A cluc k wave form
i.~
a bas ic ti ming waveform from which ot her wavcforms arc derived.
A timing diagram shows the lime re lalionsh ip of two or more wave forms, Pa rallcltra nsfcr is faster than scriul tnmsfer.
ANSWERS
SECTION 1-3
•
45
Basic logic Operations I. When the input is LOW
2. When all inptlls arc HIGU 3. When any or ll Jl inputs arc J-IlGt-1
4.
An inverter is a Nor circuit.
5. A logic gale is ac ircui t thai performs a logil;: operation (AND. OR).
SECTION 1 - 4
Overview of Basic logic Functions I. A comparator compares the magn itudes of two input numbers.
2. Add. subt roct. multipl y. Hnd divide 3. Eneoding is changing a familiar foml such as dedmal lO a coded form such as binary. 4. I)c(:oding is changing a code to a fami liar (onn such as binary 10 decimaL
5. Multiplexing puts data from m
6. Fli p-- nops, regi ste ..... scmieonduclOr memories, magnetic disks 7. A
SECTION 1 - 5
(''OOllier (OOlllS cve ms wit h a sequence of binary statcs.
Fixed-Function Integrated Circuits: l. An IC is an electronic ciKuit with all components integrated on a single silicon chip.
2. DIP-dual in· line ~ckagc; SMT---5 urfa<.:r.,'·- mou,lttech no logy; SOIC---,;nlllll·ulllline integrated c in; uil: SSr---5 ma ll-sc~, lc integration: MS I- mcdium-scale integrati on; LS I- largescale intcgration: VLS I-vcry large-scille integratioo; ULSJ- uJl ra large-scale integration
3. (a) 55 1
SECTION 1-6
(bJ MSJ
(d) VL~ I
(e) LSI
(e) ULSI
Introduction to Programmable logic I. Simplc prognlllllTlnbJc logic device (SPLD). com plex prognullIllable Jogie device (CPLD), and field prognlmmable gate army (FPGA)
2. A CPLD i~ made up o f rnullipl e SPLDs. 3.
Dc.~jgn
entry, functional si mulation. synthesis. implemcntatioo. timing ~imu L1lion , and down load
4. Desigll entry: The logic des ign is entered using development software. Flllicl iollnl siml/lntio/!:
The design is software sim ulated to make ~urc it \I"ork.~ logically. S)'II/"esi.~: The design is tmnslnted into a nctiist. IlIIplclllcntnlioll: The logic dcveloped by the netlist is mapped into the progra mmable dev ice . Timillg Si//!U/(llioll: The design is software sim ulated to confirm th at the re arc no ti ming problems. /Juwnlocld: The design is placed into the program mable device.
SECTION 1 - 7
Test and Measurement Insb'uments: 1. The analog scope applics the lllC'lsurcd wavcform di rectly to the display d rcuits. The d igital scope first coo\'ens the mCilsurcd signnl to uig ilill form . 2. 111c logic analyzcr has more channels than the oscillosopc and has more than one data di splay fontl.1l. 3.
1llc V/div (.'Ontrol sets the voltage f04'" ene h divis ion nn the
S(.TCcl l.
4. The scod,v control sc,.~ the lime fOf each divisioo00 lhe screen.
S. Thc function generator produces various types of wavefoffilS.
RELAIl'D PROBLEMS FOR EXAMPLES 1-1 f = 6.07 kHz; DUly cycle = 16.7% 1-2 Pamllcl lmnsfer: IlX) ns; Scrialtrans fer. 1.6 ps 1-3 Am pl itude = 12 V; T = 8 ms
SELF-TEST I. (b)
2. (d)
3. (a)
4. (c)
5. (c)
6. (d)
7. (b)
9. (eJ
10. te)
J I . td)
12. (d)
13. (b)
14. (c)
15. (a)
8. (d)
SYS EMS, IONS. AND CODES
N CHAPTER OUTLINE
I- I
Decimal Numbers
I-I
Binary Numbers
1- 3
Decimal-to-Binary Cc;",version
1-'
Binary Arithmetic
1-5
l's and 2's Complements of Binary Numbers
2-6
Signed Numbers
2- 7
Arithmetic Operations with Signed Numbers
2- 8
HelC.ldecimai Numbers
2- 9
Octa.l Numbers
2-10
Bin.aryCoded Decimal (BCD)
2- 11
Digital Code}
2- 12
Elror Detection and Correctioo Codes
INTRODUCTION
CHAPTER OBJECTIVES Review the
decimal number S)'Item
Count in the birKIry number system Convert from dedmal to binary and from binary to decimal Apply arithmetic operation! to birKIry numben Determine the 1'1 and 2'1complemenb of a birKIry number
Expral signed binary numberl in sign-magnitude, 1' I complement, 2'1 complement. and f1~ting-point format Carry out arithmetic oper-atiOnl with ligned binary numberl Convert between the binary imd hexadedmal number systenl1 Add numberl in hexadecimal form Convert between the binary and ocbl numbe r I)"tem. Express decimal numben in bin..ry coded decimal (BCD) form
The binary oumber system and digital codes are fundamental to computers and to digital electronics io general. In this chapter, the binary number system and ib relationship to other number syste ml luch al decimal, hexadecimal, and octal is presented. Arithmetic operations with binary numbe", are covered to provide a basis for undet1tanding how computers and many other types of digital systems work. Allo, digital codes luch al binary coded decimal (BCD). the Gray code, and the ASCII a re COVered. The parity method (or detecting erron in codes il introduced and a method (or correcting erron il described. The tutorial, On the use o( the calculator in certain operations are based On t he n-86 graphics calculator and the TI-36X calculator. The procedures shown may vary on othe r types.
,e.
VIIiT THE COMPA NION WE8SITE
Study aid, for thil chapter are .waitable at
Add BCD numben Convert between the binary S)'Item and the Gf
I http://\VIH'W.prenhall.com/f1oyd
Inte.-pret the American Standard Code for InfO
KEY TERMS
LSB
BCD
MSB
Alphanumen'c
Byte
ASCII
f loating-point number
Parity
Hexadecimal
Hamming code
Octal
47
48
•
2-1
NUMBER SYSTEMS, OPERATIONS, AND CODES
DECIMAL NUMBERS You a re fami liar wilh lhe deci mal number syste m because yo u use deci mal numbers every day. Allhough decimal numbers are commonplace, thei r weighted Slructure is often not understood. In this seClion. the structure of decimal numbers is reviewed. 'n lis review will help you more easily understand thc struct ure of fhe bim,ry numocr system, which is importanl in computc rs and dig ital clcclronic.~. Afte r completing this section, you should be able to • Explain why the deci mal number system is a weighted syste m . Explain how powers o f tcn are used in the decimal system . Dete rmine the wcig ht of each digit in a dccimal number
The decimal number ¥tem has ten digib.
In the dL'Cirnal num ber system each of the tcn digits. 0 through 9. represents a certain quanti ty. As you know. thc Icn sy mbol.~ (digits) do not limit you to expres.~i n g only te n different quantities because you use lhe various digits in appropriate positions within a number to indicate the magni tude of thc quantity. You can exprcss qua ntities up through nine before running OU I ofdigils; if you wish toexprcss aq ua mity greater than nine, you use two or more digi ts, a nd the position of each diEit within the number tells you the magnitude it represents. If, for examplc, you wish to express the quan tity twen ty-t hree. you usc (hy their respecti ve positions in lhe number) the digit 2 10 represent the quantity Iwcnly :md the digit 3 to represcllllhe qUilniity three, as ill us traled below.
-------,1 r-
The digit 2 ha" a weig ht of
10 in Ihi" po"ilion.
2
The digi t J ha.... il weig ht of I in thi ~ pD'oition.
3
.--' '--. 2 X 10
J, 2U
+
3XI
J,
+
3
J 23 The decimal number system has a base of 10.
The position of cach digil in a dec imal number indicates the mag nitude of the quantit y represented and can be assigned a weight. The weights for whole numbers arc positi vc powers of ten that increase from right to left, beginning with I ff = I .
For fmctional nu mbers. thc weights are negative powers of ten that deerease fmlll left to rig ht beginning with 10- ' . The value of a digit i, determined by its j>illition in the number.
lol 10 1 100.10- 1 10- 2 10- 3•
.
't-.- Det:unal point The value of a decimal number is the sum of the digits aftcr each uigit has tx.-cn multipl ied by its weight, as Examples 2- 1 a nd 2- 2 iJi ustnlle,
DECIMAL NUMBERS
I
•
EXAMPLE 2-1 Express the decimal number 47 as a sum of the V'
SoIu.tion
The digit 4 has a weight of 10, which is 10 1, as indicated by its po:-.ition. Thedigil 7 has a weight of I . which is I rf. as imJicated by its position.
+ (7 x
47 = (4 X 10 1) = (4 X 10)
Related Problem·
I
+ (7 x I )
=
40 + 7
Determine the value of each digit in 939. 'Answers:lre at fhe end of the chapter.
I
EXAMPLE 2 - 2 Express the decimal number 568.23 a<; a sum of the values of each digit.
Solution
The who le nUlllbcr digit 5 ha<; a weight of I(X). which is 10? thc digil 6 has a wcight of 10. which is 10 1• the digit 8 has a weight of J. which is Irf, the rractional digit 2 has a weight of 0. 1, which is 10- 1, and the fnlct ional digit 3 h a weight of 0.0 1, which is 10 - 2.
+
568.23 = (5 X ](i )
(6 X 10 1)
+
(8 X
lao) + (2 X 10- 1) + (3 X 10- 2)
-(5 X lOO) + (6X I0) + (8 X I) = 500 +60 +8 Related Problem
+ (2 X O. I) + (3XO.O I) +0.2 +0.03
Determine the value of each digit in 67.924.
Powers ofTen Find the value of
&le
Iw.
10' TI·86
Step 1.
Elm!)
Step 2.
II mmI
Step 3.
TI·36X
rl
SECTION 2 - 1 REVIEW Answen ilre ilt the end of the
dlilpter.
Step t.
a
Step 2.
II G
10 "3 1000
El Pi 1000
1. What weight doe the digit 1
(a) 1370
h~ in
«)
(b) 6725
each of the following numbers?
7051
(d) 58.72
2. Expres5 Cdch of the foll owing decimal number! oilS oil sum of t he products obtained by multiplying e;)ch digit by if:.! "ppropri;)te weight:
(a) 51
(b) 137
«)
1492
(d) 106.58
49
50
•
2-2
NUMBER SYSTEMS, OPERATIONS, AND CODES
BINARY NUMBERS The binary num ber system is anot her way to represent quantities. It is less complicated tha n the decimal system beeause it has o nly two digits. The decimal system wil h ils ten digits is a base-ten system; the binary system with its two digits is a base-two system. The two binary digits (bils) are I and O. The position of a I or 0 in a binary number indicates its weight. o r value within the number. just as the position of a decimal digit determines the value oftha! digi!. The weights in a binary number are baSI..""
Counting in Binary The binary number system has two digits (bib).
The binary number system base of 2.
nai a
To learn to count in the binary system, first look at how you count in the decimal syste m. You start at zero a nd count up to nine before you run oUi of digits. Yoothen start another digit position (10 the left) and colllinue counting 10 through 99. At this point you have exhausted alJ two-digit combinations, so a thi rd dig it position is needed 10 count from 100 through 999. A comparable s ituation occurs whe n you count in binary, exccplthat you have only two digits, calJed bill'. Begin courlling : O. I. Al lhis point you have used boIh digits. so include a nother digit position and continue: 10, II . You have now exhausted all combinations of two digits. so a third position is n..'quireti. With Ihree d igit positions you can cominue to COUIlt: 100, 10] , 110, and I I J. Now you need a founh digit position locontin uc, and so on. A binary count of zcrn through tiftcen is s hown in Table 2- 1. Notice the patterns with which the Is a nd Os al ternate in each column.
TABLE 2 _ 1
DECIMAL NUMBER
BINARY NUMBER
0
I
0 0
2 3
0 0
0 0
0
0
0 0
0 I
0 I
I
0
4
0
0
5
0
0
6
0
7
0
0 I
I
I
8
0
0
0
0
9
0
10
0
"12
0
13 14
L'
0 I
I
0
0
0
I
0
BINARY NUMBERS
As you have st.'Cn in Table 2- 1, four bits arc required 10 count from zero 10 IS . Ln general, with 11 bits you can counlup to a numbLT ct]ua/ to 2" - I.
•
The value of a bit is determined by its positio n in the number.
Largest decimal numbe r = 2" - I For example, with five bils (11 = 5) you can count from zero to thirty-one. 2~ - 1
= 32 -
1 = 31
With six bits (/I = 6) you can count from ....ero 10 sixty-three.
26 - 1 = 64 - 1 = 63 A table of powers of I wO is given in Appendix A.
Powers of Two
a.
bDmpk
Find the value of2s.
n -86
Step 1. Step 2.
TI-36X
Step 1. Step 2.
2'5
ata
32
a0 a G)
32
An Application Learning to count in binary wi.l1 hclp you to basically understand how digital circu its can be used 10 count events. This can be anything from counting items on an assembly line to counting opcmtions in a computer. Let's take a simple example of counting tcnnis balls going into a box from a conveyor belt. Assume that nine balls arc to go into each box. The counter ill Figure 2- 1 counts the pulses from a sensor that de tects the passing o f a ball and pmdu(.'Cs a sequencc of logic levels (digital wavcfoOlls) on each o f its four parallel outputs. Each set of logic Icvels represents a 4-bit binary number (HIGH = I and LOW = 0), as indicated. As the decoder receives these waveforms, it decodes each sct of four biL~ and converts it to the corresponding decimal number in the 7-seg ment display. When the counter gets 10 the binary Slate of 1001. it has counted ni ne tennis balls, thc display shows decimal 9. and a new lxlx is moved under the conveyor. Then thc counter goes back to its ...em state (0000), and thc pr()(.·css starts ovcr. (Thc number 9 was used only in the interest o f singlc-digit simplicity.) Balt count 2nd !).aU
Counlcr
"" "'"
'"
1st ball
0 0
0
()
()
0
0
I'
0
u
0
u
0
0
0
0
0
()
()
10
0
0 1 '
[Q][]I2lGl[g][SJ[6][J]IBl~ FIGURE 2 - 1
Illustration of iI simple binary counting appliCdtion.
51
""""'"
~g L
t
52
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
The Weighting Structure of Binary Numbers The weight or value of a bit incre<1~ (rom right to left in binary number.
A binary number is a weighted number. The right-most bit is the LSD (least significant bit) in a binary whole number and has a weight of 2° = I. The weight..; increase (rom right to left by a powcr of two for each bit. The left-most bit is the MSB (most significant bit); its weight depends on the size of the bi nary number. Fmctional numbers can also be represented in binary by placing bits to the right of the binary point, just as fractional decimal digits arc placed to the right of the decimal point. 111e left-most bit is the MSB in a binary fraetioml l number and has a weight of TI = 0.5. 111e fmetional weights decrease from left to right by a negati ve power of lwo for each bit. The weight structure of a binary numbe r is
~
2" -
I..
2J 22 i 2° . 2 ~ 1
2 ~2
. . . 2 ~"
'L- Binary point memory 'OCCltions. Each
I
where II is the number of bits frum the binary point. Thus. ail lhe bit.;; to the left of the bi Ilary point have weights that arc positive JXlwers of two, as pre\,jously d iscussed for whole numbers. All bits to the right of the binary point have weights Ihat are negative powers of two, or fmct iollal weights. T he powers of two and their equivalent decimal weights for an 8-bit binary whole number and a 6-bit binary f mctioflaJ mllnber arc shown in Table 2- 2. Notice thai the weight doubles for each positive power o f two and thai the weight is halved for each negative power oflwo. You can easily exlend the table by doubling the weight of the most significant positivc power of two and halving the weight of thc least significant negative power of lwo: for example. 29 = 5 12 and 2 - 1 = O.OO7RJ25.
~~~:~,~'::~~,,~.g;n;ed ~ uniqueSome II addreJJ. microprocesson, (or ecilmple, h;we 32 addres. lines can select 2lZ unique 10000tiorn.
TABLE 2_2
Binaryweighu.
28
27
256
128
POSITIVE POWERS OF TWO (WHOLE NUMBERS) 2' 2$ 2( 23 22
64
32
In
8
4
1
2- 1
NEGATIVE POWERS OF TWO (FRACTIONAL NUMBER) 2 -2 2 -3 2-( 2- 5
In
114
I
21 2
2°
I
0.5
0.25
2- 6
118
111 6
1/32
1/64
0.125
0.0625
0.03125
0.015625
Binary-to-Decimal Conversion Add the w-eigMJ of ~II 1s in a binary number to get the
TIle dccim!tl value of any binary number Can be found by adding the weights of all bits that arc I and discarding the weights of all bits Ihal arc O.
decim<'ll value.
I
EXAMPLE 2-3 Convert the binary whole number 11 0 1101 to decima1.
Solution
Determine the weight of each bit that is a I . and then find the sum of Ihe weight.. 10 get the dec imal number. Weight: 26 25 24 23 22 21 20 Binary number: 1 1 0 I I 0 1 110110 1 = 26 + 25 + 23 + 22 + 2° = 64 + 32 + 8 + 4 + I = 109
R€lnted Problem
Conven the binary number 10010001 to dl:cimal.
DECI M AL -YO-B INARY CONVERS I ON
I
•
EXAMPLE 2-4 Convert the fractiona l binary numberO.10 11 Solution
10
decimal.
Determine the weight of each bit thaI is a I, and then sum the weights to get (he dcci m,ll fmction. Weight: T I T2 Binary number: O . I 0 0. 101 1 = TI = 0.5
Rela ted Problem
I
SECTION 2-2
T I
+ T l + 2-4 + 0.125 + 0.0625
J
Til 1
= 0.6875
Convert the binary number 10. 11 1 to decimal.
1. What is the largest decimal number that can be represented in bimary with eight bib?
REVIEW
2 . Determine the weighto( the 1 in the binary number 10000. 3 . Convert the binary number 10 1111 01 .01 1 to decimal.
2-3
DECIMAl- TO - BINARY CONVER510N
In Section 2- 2 you learned how to convert a bin;lry number to the equivalent &::cimal nu mber. Now you will learn two ways of converting from a decimal num ber to a binary number. A rtcr completing this section, you should be able to • Convert a decimal number 10 binary using the sum-of- weights method _ Convert a deci mal whole number to bi nary using the repeated division-by-2 method - Convert a decimal fmclion (0 binary using the repcaH.'(/ mUltiplication-by-2 method
Sum-of-Weights- Method One way to li nd the binary number Ihal is equivalenl 10 a given decimal number is 10 delennine the sel of binary weights whose SUIll is equal to the decimal number. An easy way 10 remember binary weights is that the lowest is I , which is ~, and thai by doubl ing any weight. you gel the next higher weight; thus, a list of seven binary weights would be 64, 32. 16, 8,4, 2, I as you leaOlcd in Ihe lasl section . The decimal number 9, for example, can be expressed as the sum of binary weights as fo llows:
9 = 8 + I or 9 = 23 +:t> PlaCing I s in the appropriate weight posilions, 23 and 2°, and Os in the 22 and 21 position!. detennines lhe binary number for deci mal 9.
2}
22 21
o
0
'f! Binary number for decimal 9
To get the bimary number for a given decimal number, find the bin~ry weights that add up to the decimal number.
S3
S4
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
I
EXAMPLE 2-5
Convert the following decimal num1:x:rs to binary:
Solution
(d) 82
(a) 12
(b) 25
(a) 12 = 8
+ 4 = 2 3 + 22 _ __
(b) 25 = 16
{cl 58
_ _ __ __ _ _ _ _ __
+ 8 + I = 24 + 2} + 2° 5
Related Problem
....1
1100
) 11001
4
3
lc) 58 = 32+ 16 + 8+2 = 2 + 2 +2 + 2 ' (d) 82 = 64 + 16
_
111010
+ 2 = 26 + T + 2'
1010010
Convert Ihe decimnl number 12510 binary.
Repeated Division- by-2 Method To get the binary number for a given decimal number, divide the dedmal number by 2 until the quotient k O. Remainden form the binary number.
A systematic method of converting whole numbers from decimal 10 binary is Ihe repellted process. For example. 10 convert the decimal number 12 10 binary, begin by dividing 12 by 2. Then divide each resulting quotient by 2 unti 11here is a 0 whole-number quotient. The remainde.-s gCller
di ,'i.~;oll -by-2
Remainder
12 -= 6
~ 6
-= 3
~
3
- = 1
~
.!.. = o 2
Stop when the II h o lc-nu m~r
q U O.
~
Convert the follow ing decimal numbers 10 binary: (a) 19
(b) 45
0 - -----, 0 - -,
DECIMAl-TO- BINARY CONVERSION
Solution
(a)
Remainder
45 = 22
-
~
'.----J
22
9 - = 4
-
~
4 - = 2
~ 2
- = 1
~ ,
,
- ~ O
Remainder
(b)
'9 = 9
= 11
0
'r-J "
0
-
= 5
~ 5
- = 2
~~
,~
- = 1
MSB -.5
o ~ , '1 ~ I
1 0 0 1 I
L LSB
-~ O
I 0 I
MSB Related Problem
-.5
o, LLSB
Convert decimal number 3910 bi nary.
<":oll\"eniioll ofa Decimal Number to 8 Uinary Number
Exompl.
Convert decimal 57 to binary. 57 to Bin
BASE
TI-86
Step l. Step 2. Step 3. Step 4.
a aa
Em
iii
111001b
m rmm
DEC
TI-36X
•
Step I. Step 2.
O@J
aa
BIN
Step 3.
0 0
Converting Decimal Fractions to Binary Examples 2- 5 and 2-6demollslnlt{:d who le-number col\vcrsions. Now let's look at fractional convcrsions. An easy way to remember fmctional binary weights is thatt hc most significant weight is 0.5, which is T I, and that by halving ally weight, you get the next lower weight; thus a list of four fractional binary weights would be 0.5, 0.25, 0. 125, 0.0625.
111 001
55
56
•
NUMBER SYSTEMS, O PERATIONS, AND CODES
Sum -oF-Weights T he sum-uf-weights method can be applied to fractional decimal numbers, as shown in the followi ng example:
+ 0. 125 = r 1 + 2- ) "" 0. 10 1 T here is a I in the r l position, a () in the r 2 position, and a 0.625 "" 0.5
I in the r3 position.
Repeated Multiplication by 2 As you have seen. decimal whole num bers can be COIlven ed to binary by repeated division by 2. Decimal fractions can be converted to binary by repeated multiplication by 2. For exam ple, to conven the decimal fraction 0.3 125 10 binary. begin by multiplying 0.3 125 by 2 and then mUltiplying each resulting fractional part or the product by 2 until the fractional product is zero or until the desired number of decimal places is reached. The carry digits, or carries. generated by the multiplications produce the binary number. T he first carry pnxluced is the MSD, and the last can y is the LSB. This procedure is illustrated m; fo llows:
.r- LSB
MSB.
o1 0.3 125 X 2 = 0.625
t 0.625 X 2 = 1.25 T
t
0.25
x 2 = 0.50
0 - - ------'
t 0.50 X 2 "" 1.00 Continue to the desired number of decimal or stop when the fmetional P31t is all Lt'ms.
I
SECTION 2-3 REVIEW
Place~J
1. Convert each decimal number to binary by using the 1um-of-weighu method: (,) 23 (b) 57 (e) 45.5 2. CorM!rt each decimal number to binary by using the repeated division-by-2 method (repeated multiplicatio n-by-2 fo r fractions) ;
(,) 14
2-4
(b) 21
(e) 0.375
BINARY ARITHMETIC Dinary arithmetic is c.,,~nt ial in all d igital computer.,; and in many other types of digital systems. To undcrst
j
BINARY ARITHMETIC
•
57
Binary Addition Remember. in binilry 1 10. not 2.
The fou r basic rules for adding binary di!lits (bits) arc as foll ows: 0 + 0 = 0 0 + 1= I
Sum of 0 with a carry o f 0 Sum of I with a carry of 0
1+ 0 = I I + I == JO
Sum of I with a carry o f 0 Sum of 0 with a carry o f I
Notice that the firstlhrec rules res ult in a single bit and in the fou rth rule Iheaddilion of two Is yields a bi nary two (10). When binary numbers are added, the laSI (."flooitioll creates a Sum of 0 in a given column and a carry o f lover 10 the next column to the left . as illustrated in the fo llowing addition of 11 + I :
' ili-L Carry CarT)
o
,
I
+0 I
0 0
I 0
In lhe right column, 1 + I = 0 with a carry o f I to lhe next column to the left In the middle column, I + I + 0 == 0 with a carry of I to Ihe next {:o lumn to the left . In the kft colUl11n , I + 0 + 0 = I . When there is a carry of I , you have a situat ion in which three bits are being added (a bit in each of the two numbers and a carry bit). This sit uation is illustrated as follows: Cu rry bit s~
1 + 1 + + +
0 + 1+ 0 + 1+
0 0 1 1
01 = 10 = 10 = 11
=
Sum of I with a eany of 0 Sum of D with a carry o f I Sum of 0 with a carry o f I Sum of I with a carry o f I
Add the foll owing binary numbers: (a) II
Solution
(b) I ()(I
+ 10
(c) I II
+
11
(d) 110 + 100
The equivalent decimal addilion is also shown for reference. (a)
Related P,oblem
+ II 3
II + 11
.±J
+ 10
110
6
110
(b)
100
4 +2 6
(c)
III
7
±.ll
.±J
±lJlll
1010
10
1010
(d)
11 0
6 +4 10
Addll 11 and l lOO.
Binary Subtraction The four ba<;ic rules for subtracting bits are as follows:
0 - 0= 0 I - 1= 0 1- 0 = 1 10 - I = I
o-
! with a borrow of I
Remember in binary 10 - 1 = 1, not9.
58
•
NUMBER SYSTEMS. OPERATIONS. AND CODES
When subtracting numbers, you sometimes have to borrow from the next column to the left. A borrow is required in binary only when you try 10 subtract a I from a O. In this case, when a I is bon'OWed from the next column to the leI'l, a 10 is created in the column being subtracted, and the la'it o f the four basic mles just listed must be applied. Examples 2-8 llnd 2- 9 illustrate binary subtraction; the equivalent decimal subtractions arc also shown.
I
EXAMPLE 2 8
Perfoml the following binary subtractions: (8) II - 0 1
Solution
(8)
(b) 11 - 10
II
3
=-l!l
-=-l
10
2
(b)
II
3
=-1Q 01
- 2
No borrows were required in this example. The binary number 01 is thc same as I.
Related Problem
I
Suhtract 100 from I II.
EXAMPLE 2-9
Subtract 01 1 from 101.
Solution
IOJ
5
- 011
=1
010
2
Let's examine exactly what was done to subtract the two binary numbers since a borrow is required. Begin with Ihe righl column. Left colu mn: Whcn a I is borro\\cd, aOis len , soO - 0 -= 0. \ \.
r
,
1101
..=.Q..ll
0 10 1
Related Problem
Midd le<;o lumn: Borrow I from ncxt column 10 the left, making a lOin this column, then 10 - I = I. Righi column : I - I = 0 I
Subtract lOl from llO.
Bina,.y Multiplication Binary multiplication of two bib is the !.arne as multiplication of the decimal digib 0 and 1.
The four b1L'i ic ru les for multiplying bits arc as follows:
Oxo = o
oX
1= 0
I xO = O I X 1= I
BINARY AR ITHMETIC
•
59
Multiplication is performed with binary numbers in the same manner as with decimal numbers. It involves forming panial products, shifting each successive partial product le ft one place.nnd then adding all the partial products. Example 2- 10 i l l u st rat~ the proc-edurc; Ihe equivalent decimal multiplications are shown for rcferc.nce.
Perform the following binary Illultiplications: la) II x I I
Solution
(b) 101 x 111 II
(a)
Lll Partinl 11 produ<..1S \±lL
3 2Ll 9
rb)
III X JOI II I ()[X)
j
Pnntal product~
7
xS 35
+ III
1001
100011 Related Problem
Multiply 110 1 x 1010.
Binary Division Division in binary follows the same prucedurc as di vision in decimal. as Example 2- 11 illustr'dles. The equivalent decimal divisions ure also given.
I
EXAMPLE 2 - 11
Perform the fo llowing binary divisions: (a) 1JO~ II
Solution
(a)
(b) 11 0..:.. 10
10
2
II
ll Ji10 11 000
3)6
(b) IOfiIO
6 0
3 2)6 6
10 10 10
0
00 Related Problem
i nCT'ON 2-4 REVIEW
Divide I 100 by 100.
1. Perform the following binary additions:
(a) 11 01 + 1010
(b) 10111
+ 0 11 01
2. Perform the following binary ~ubtractiom :
(a) 1101 - 0100
(b) 1001 - or II
3 . Perform the indicated binary operations:
(a) 110 x 111
(b) 1100-+-011
A calculator can be u~ed to perform arithmetic operatiom with binary numbers al long a~ the capacity of the calculator i~ not exceeded.
60
_
2-5
NUMBER SYSTEM S, O PERATIONS, AND CODES
, ' S AND 2 ' S COMPLEMENTS OF BINARY NUMBERS The I 's complement and the 2's complement of a bimuy number arc important beeause_ they pen nit the representation of negative numbers. Thc mcthoo of 2's complement arithmetic is commonly used in computers to handJc ncgati vc nu mbers. After completing this section, yoo shoold be ablc 10 - Convert a binary number 10 its I's complement _ Convert a binary nu mber 10 its 2's complemen t using eithe r of IWO methoos
Finding the l's Complement Change each bit in a number to get the l's complement.
The I's complement of a binary number is found by changing all Is 10 Os and all Os to 1s, as illustrated below:
I
a I 1a0
I 0
Binary number
tUtUU
a 1001
10 I
I's complement
The simplest way 10 obtain the I 's complement of a binary num ber with a d igital circuil is to usc pamllel inverters (NOT circuits), as s hown in Figure 2-2 for an 8- bit binary number,
FIGURE 2 -2
Example of inverterl used to o bu in the "s complement of a binary number.
o
"
o
"
Finding the 2's Complement Add I to the 1's complement to get the 2's complement.
The 2's complement of a binary nu mber is found by adding I 10 the LSn of Ihe 1's complement. 2's complement = (I's complement)
I
+
EXAMPLE 2 - 12 Find the 2's complement of 101 100 10. 10 1100 10 01 001 101
SciUtiOll
+
I 01001110
Related Problem
ninary number I's complement Add 1 2's compicment
Determine the 2's complement of 1100 101 1.
1'5 AND 2'5 COMPLEMENTS OF BINARY NUMBERS
An altcrnative mcthod of find ing the 2's complement of a bi nary number is as follows: 1. Start al the righl with the LSB and write the bits as Ihey are up to and including the first I.
•
Change all bits to the left of the least significant T to get 2 's complement.
2. Take the 1's complements of the rcml1ining bits ,
Find the 2's complemenl of 101 11000 lIsing the alternati ve IJlClhnd,
Solution
L
Related Problem
Binary number 2's complcmelll
10 111 000
I 's complcmcnts ~ 01001000 of original bitS - !
These
b i t~
stay the same
Find the 2's complement of 11 000000,
The 2's com plcmclll of a negalivc binary nu mber can be reali zcd w.:ing invcrtcrs and an adder, as indicated in Figure 2- 3, Thi s illustrates how an S-bit nu mber can be conve rted to its 2's complcmcnt by first invc rting each bit (taking thc l 's comple mcm) ~U1d the n add ing 1 10 Ihe I's complement with an adder circu it,
Negative number
"
"
II
fiGURE 2 - 3
II
~ple of obtaining the 2', complement of a negative binary number,
, 's complement Inpul lJ il.'
Adder
Dey in
1-;::;:;"" (add I)
Outpul bil.'i {sumJ
2's complement
"
II
"
o
To t'Ollvert from a I 's o r 2's complement back 10 the true (unco mplemcnted) bina ry form, use the same t WO procedures de~cri bcd previously, To go from thc l 's complement back to true binary, reverse all the bits, To go from Ihe 2's complement form back to true binary, take the l's comple ment of the 2's complemellt numbe r and add I to the least significan t bit.
1. Determine the l 's complement of each binary number:
Ca) 00011010
Cb) 11110111
C,) 10001101
2. Determine the 2's complement of eac;h binary num ber:
Ca) 00010110
Cb) 11 111100
C,)
61
1001000 1
62
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2-6
NUMBER SYSTEMS, OPERATIONS, AND CODES
SIGNED NUMBERS Digital systcms. such as the computcr. must be able to handle both positive and negative numbers. A !>igncd binary number consist!> of both sign and magnitude information. The sign indicates whether a number is po~itive or negative. and the magnitude is the va lue of the number. There are three forms in which signed integer (whole) numbers can be represented in binary: sign-magnitude, I 's eomplemelll , and 2'~ ~omplelTlent. or these. the 2"s complement is the most important and Ihe sign-magnitude is the least used. Non integer and very large or small numbers can be ex prcs~cd in noming-point Formal. After eompkting this sc(.1ion. you ~ h ou ld be able to • Express positive and negative nu mbers in sign-magnitude . Exprc!>s positive and neg:ltivc numbers in I 's complement . Express positive and negative numbers in 2's complemcnt - Detennine the decimal value of signed binary numbers • Exprcs~ a binary number in tlooting-point form:l1
The Sign Bit The left-most bit in a signed binary number is I.hcsign bit, which tells you whether the IlUmber is positive or negative. A 0 sign bit indicates n positi\'e number, a nd a 1 sign bit indicates n negath'c number.
Sign- Magnitude Form When a signed binary number is represented in sign-magnitude, the left-lllost bit is the siEn bit and the remaini ng bi ts nre the magnillide bits. The magnitude bits are in true (uncomplemented) binm)' for both positive and negative !lumbers. For example, the decimal number + 25 is expressed as an 8-bit signed binary number using the Sign-magnitude fUlm as 0001 100 1 -~
Sign bit.1
The decimal number
~ 25
L
Magnitude bits
is ex pre..<;5C(! as
100 11 00 1
Notice that the only difference between + 25 and -25 is the sig n bit because the magni lude
bits are in tnlc binary for both positive and negative numbers. In the sign-nmgnitud(' form, a negntin number ha.; the same magnitude bil.; us the ('OrrcsllOlwing positive number but the sign bit is a I miller thall a 7£1'0, Computers use the 2'1 complement fOf' negative integer numberl in a ll arithmetic
III~:;::~~ ofThe rcawn il that number;s the i1
011
adding the 2's
J complement of the number. I Comput~
complement by inverting the bits and adding I, uling ,pccii11 inltructionl tmt produce th e same result as the adder in Figure 2- 3,
l 's Complement Form Positive numbers in I 's complement fo rm are re presented the same way as the positive signmagnitude numbers. Negative numbers. however, are the I 's complements o f the corre-spOnding positive numbers. For example. using eight bits. the decimal number - 25 is expresslX! as the I·s complement of +25 (fO) IIOOI) as 111 001 10
III the I 's complement fornI, a n(:gativc lIumm.'r is Ihe l's complement of the corresponding positi\'e number.
SIGNED NUMBERS
•
2's Complement Form Positive numben; in 2's complement form arc represented Ine same way a" in Ihe signmagnitude and I's complement forms. Nc~ati \'e numbers are the 2's complements of the curresponding posi tive numbers. Again, usi ng ci~ ht bits, let's take decimal number - 25 and express it as the 2's complement of +25 (000 11001 ). I J 100 111
In the 2's complement loml, a negative number is the 2's complement of the corresponding positive numOCr.
I
EXAMPLE 2-14
Express the decimal number - 39 as an 8-bit nu mber in the sign-magllilUde, l 's complement, and 2'.~ complemenl fonn s. Solution
First, Wlile the 8-bit numbe r for + 39. 00 100 111
In the s;gll-mllgll;flIdeforlll. - 39 is produced by chang ing fhe sign bit to a I and leaving the magnitude bits as they nrc. The numbt.~r is 10100111 In the J '.~ cOlllplemem fo rm, - 39 is produced by laking the I 's complement of +39 (00 100 111 ). 11011000 Inlhe 2 's cOlllplemelll fo,.m, - 39 is produced by taking the 2's complement of + 39 (00 I00 1( 1) as fo llows: 1 J 0 11000
I's complement
+ IHlIIOOl
Related Problem
Express
2's complcment
+ 19 and - 19 in sign-magnitude, I's complement, and 2's complement.
The Decimal Value of Signed Numbers Sign-magnitude Decimal values of positive and negaTive numbers in the sign-mllgnitude fonn are detc.rmincd by slIImning the weights in all the magnitude bit positions where there are Is and ignori ng those positions where there arc zeros. The sign is determined by examination of thc sign bit.
I
EXAMPLE 2 15
Determine the decimal vallie of this signed binary l1umlx;r eKpresscd in signmagnitude: 1001010 1. Solution
The sewn magnitude bits ilnd the ir powers-of-two weights are as follows: 26 2s 24 23 22 2) 2°
o
0
0
0
63
64
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NUMBER SYSTEMS, OPERATIONS, AND CODES
Summing the weights where there are Is,
16+4 + 1 = 21 The sign bit is I; therefore, the decimal number is -21.
Related Problem
Determine the dccimal value of the sign-magnitude number 0 111 0 111 .
"s
Complement Decimal values of positive numbers in the I's complement form are determined by summing the weights in aU bit positions where there are Is and ignoring those posit ions where there arc zeros. Dt'Cimal values of neg alive numbers arc dt!tenn ined by assigning a negative value to the weight of lhe sign bit. summing all the weights where there arc Is, and adding I to the resu lt.
i
EXAMPLE 2-16 Dett~rm ine the decimal values of the signed bina!)' numbers expressed in I's complement:
(a) {)(xli O! II
Solution
(b) 111 0 1000
(a) The bits and their powers-oF-two weights for the positive number areas Follows:
- 2'
2'
o
I
Summing the weights where there arc Is,
16 + 4
+2 +
I = +23
(b) The bits and their powers-oF-two weights for the negati\'e number are a<.: follows. Notice thatlhe negative sign bi t has a weight of _ 2 7 or - 128. -27
26
1
25
24
2'
0
o o
2'
Summing the weights where there are Is,
- 128 + 64 + 32
+ 8 = - 24
Adding I to the result, the fina l decim.alllumber is
-24+ I = -23
Related Problem
Dclenll ine the dt'Cimai value of the I 's complemem number 111 010 11.
2s Complement Decimal values of positive and negative numbers in the2'scomplcment fonn are determined by summing the weights in all bit positions where there are Isand igIlOring those positions where there arc zeros. The weighl of the sign bi t in a negat ive number is given a negative value.
I
EXAMPLE 2-17
Delermine the decimal values oflhe signed binary numbers ex pressed in 2's complement : (3) 0 1010 110
(b) 10101010
SIGNED NUMBERS
Solution
•
(a) The bilS and their powers-of-two weights for thc positive number are as follows : _ 21
26
25
2"
23
2'
o
I
0
I
0
o
Summing the weights where there arc Is. 64+ 16+4+2 = +86 (b) 'Ole bilS and their powers-of-two weights for the negative number are as foll ows,
Notice that the negative sign bit has a weight of _21 = - 128.
2'
2'
I
o
Summing the weights where there are Is. - 128+32 + 8+2 = - 86 Related Problem
Detcrmine the decimal value of the 2's complement number 11010111.
From these examples. you can see why Ihe 2's complement fonn is preferred for repre· scnting SigllCd intcger numbers: To COllVcl1 to decimal, it simply requires a summation of weights regardless of whether the number is positive or negative. The I 's complement system Il.'quircs adding I to the summation of wcights for negative numbers bUI not for po"itive number.;. Also. the I's complement form is generally IlOt uscd because two representations of zc.ro (
Range of Signed Integer Numbers That Can Be Represented We have used 8-bit numbers for illmtralioll because the 8-hil grouping is common in mOSI computers and has been given the special name byte. With one bytc or eight bits, you can represent 256 d ifferent numbers. With two bytcs or sixteen bits, you can represent 65,536 diffcrl'nt numbers. With four bytes or- 32 bilS, yOll can rcplesent 4.295 x 10 9 differen t I1lUllbers. The formula for findi ng the number of different combinations of n bilS is 'Iotal combinations = 2" For 2's complement signed numbers. the range of values for n-bit numbers is Hange = _ (2n - I) to + (2" - I - I) where in each cac;c there is one sign bil and /I - I magnitude bits. For example. wi th fOllT bits you can represent numbers in 2's complement ranging from - (2J) = - 8102 3 - I = + 7. Si milarly. with eight bits you can go from - 128 to + 127, with sixteen bits you can go from - 32.768 to + 32,767. and so Oil,
Floating-Point Numbers To represent very large integer (whole) numbers. many bils are required. There is also a problem whclI numbers with both integer and fract ional parts. such as 23.56 18, need to be represented. The floating-point number system, based 011 scientific notation, is capable of repr~ell lill g very large and very slllall numbers without an i nclea~e 111 the number of bits and also for representing numbers that have both integer and fractional components. A noaling-point number (also kllown a~ a reed /lumber) consists of two parts plus a sign. The manti"s8 is Ihe part of a floaling-point number Ihat represents the magnitude of
The range of magnitude of a binary number dependl on t~ number of bits en}.
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NUMBER SYSTEMS, OPERATIONS, AND CODES
the nUlllocr. The exponent is the pa rt of a tloati ng-point number thut rcp 'escnts thc number of places that the decimal point (or binary point) is to be movcd. A decimal examplc wi ll be helpfu l in undcrstanding the basic concept of floating-point numbers. Let 's considcr a dccimal numocr wllich, in inte!.'Cr rOml, is 24 I,5{)(i,800. The mantissa is .24 15068 and the exponent is 9. When thc intcger is expressed as a floatingpoint numocr, it is normalized by moving the decimal poim 10 thc left of aJllhc digits !ill that the mamissa is a Fractional number and the exponent is the power of ten. The floali ngpoint number is wlittcn as 0 .24 15068 x 109
In addition to the CPU proc~ing unit). oomputeri use coprocesJOfJ to perform complicated mathematical calculations ming Ooating-point nu mber!. The purpose iJ to increase performance by freeing up the CPU for other tadu. The mathema tical coproceuor il allO known al the Ooating-point unit
For binary floating-point numbers, the fonnat is defined by ANS UI EEE Standa rd 7541985 in three forms: single-precision, double-precision. and e)'1ellded-preci.~ion. T I1c..;;e ll!l have the same basic formats except for the number of bits. Single-precision floating-point numbers have 32 bits, double-precision numbers have 64 bil'i, and extended-precision numbers have 80 bits. We will restrict our discussion to the single-pn::cision floati ng-point fOlmat. Single-Precision Floating-Point Binary Numbers In the standard format for a sillglcprecision binary number, the sign bit (S) is thc IcfHnost bit, the exponcnt (El includes the next eight bits, and the mantissa or fractional p..1.J1 (F) includes the remaining 23 bit". as shown next.
..
(FPU).
32 bits
IS I
Exponent (I::.)
I bit
8 bils
r Mantissa (fruction,
.. F)
23 bit!>
In the mantissa or fructional part, the binary point is understO
2,
101 10 100 1000 1 = 1.0 11 0100 1000 1 x 21 2 Assuming that this is a positive number, thc sign bit (S) is O. The cxpunent, 12, is cxpressed as a biased cxponent by adding it to 127 (12 + 127 = 139). The biased exponent (E) is expressed as thc bina ry num ber 1000 1011. Thc mantissa is the fractional part (F) o f the binary number, .01 10100 1000 1. Becausc there is always a I 10 thc left of the binary [.K)int in thc power-of-two expression, it is not includcd in the mantissa. TIlccomplcte floating-point number is
s o
E
F
100010 11
OJ 10 I00 I000 I()()()(X)()(XX)
Next, let's sec how to evaluatc a binary nUJllber that is already in floating-point format. Thc general approach to determ ining the value of a floati ng-point num ber is ex pressed by the following formula: Number = (-l)s(I
+ F)(2E-I27)
SIGNED NUMBERS
•
To illuslrale. let's consider the following floming-poim binary number:
s
E
F
IOQ HXXH
I roo I II COO IOOOOOOOOOOOO
The sign bit is I. The biased expo nent is 100 10001 = 145. Applying the formu la. we gel Number :=: (- I ) I( 1. 1000 11 1000 1)(2 1~5 - m ) ~ (- 1)( 1.1 000 11 1000 1)(2 " ) ~ - 11 000 11 1000 10000000 This floating-point binary number is equivalent to - 407,b88 in decimal. Since the exponent can be any number bet ween - 126 and + 128, extremely large and small numbers can be expressed. A 32-bit noaling-point number can replace a binalY integer number having 129 bits. I3ccallse the exponent determines the position of the binary point. numbers containing both integer and fmctio nal parts l:an be represented. There are t\\-o exceptio ns to the fo nnat for floati ng-point numbers: The number 0.0 is represented by all Os, and infinity is represented by alli s in the e1\ponent and all Os in the mantissa.
I
EXAMPLE 2-18
Convert the deci ma.l number 3.248 x I(f to a single-precision floating-point binary number. Solution
Com'el1 the deci mal number to bi nary. 3.248 x 104 = 32480 :=:
1111110111 ~ = 1.l111101l1 OOOOOx2 1 ~
The MSI3 will not occupy a bil position because i\ is always a I . Therefore. the mantissa is the fractional 23-bil binary number lllllOll l(X)()()OCJ()()( a.nd the biased e1\lxmel1l is 14
+
127 = 141 = 1000110 12
The complete floating-point number is
III !
11101111 0 I 1 11111 0 11100000000000000
Related Problem
I
Determine the binary value of the following fl oating-point binary number: 0 100 11000 10000 1000101 00 11 0000000
1.
Expre~~
the dedmal number + 9 a~ an 8-bit binary number in the sign-magnitude
system. 2. Express the decimal number - 33 ali an 8-bit binary number in the l's complement ",tern. 3. Express the decimal number - 46 as an 8-bit binary number in the 2's complement system.
4. lilit the three parb of a Signed, floating- point number.
67
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2-7
NUMBER SYSTEMS, OPERATIONS, AND CODES
ARITHMETIC OPERATIONS WITH SIGN ED NUMBERS In the last section, you Ieamed how signed num bers are represented in three difTercnl forms. In this scction. you will Jearn how signed numbers are added, subtracted, multiplied, and divided. Because the 2's complement fon n for represent ing signed numbers is the most wide! y used in computers and microprocessor-based systems, the coverage in this section is limited to 2's complement arithmet ic. The processes covered can be extended to the other fonns if nccessary. After completing this section, you should be able to • Add signed binary numbers . Explain how computers add strings of wmbers • [)cfine olle/flolV • Subtract signed binary numbers . Multiply Signed binary numbers using the direct addition method . Multiply signed binary numbers using the panial products method . Div ide sign(.""ti binary numbers
Addition The t\','O numbers in an addition arc the addend and the allgend. The result is the slim. There
2. Positive number with magnitude larger than negative number
3. Negative number with magnitude larger than positive number 4. Both numbers negative
LeI's take one case at a ti me lIsing B-bit signed numbers a .. examples. The equivalent decimal numbers are shown for reference. Addition of tI.vo poiili\.e numben yields a poiitiYe number.
Both numbers positive:
00000 111
+ 00000 100
+
7 4 II
000010 11
TI"lC slim is posilive and is therefore in true (un<.:omplemented) bill
Positive number with magnitude larger than ncgath'c num ber:
+ Discard cany'-----> I
15
OOUO Ill1 11111010 0000 1001
The final carry bit is discarded. The sum is positivc and thererore in true (uncomplcmcnted) binary. Addition of a positive number and a larger negative number or tI.vo negative numbeu yields a negative number in 2's complement
Negath'c numbe.· with magnitudc larger tlmn posith'e nmnhcr: 000 10000
+ J 1101 00Q 11 111 000 The SlIlll is negativ<.: and thererore in 2'5 complement rorm. Both numbers ncgativc: 11111011 11110111
+-9
.............. I IlllOOIO
- 14
+ Di!>Card carry
- 5
ARITHMETIC OPERATIONS WITH SIGNED NUMBERS
•
69
The fin al curry bit i" d iscarded. The sum is negative and therefore in 2's complement fOllll. In a compUler, the negalive numbers are stored in 2'soomplcment form so. a~ you can ~e. the addition process is very simple: Ad" Ille two nlfmbt:".~ tll1ll {Ii.w.:ard Ullyfilllll ctlrry bit. Overllow umdition When two num bers are added and the number of bits required to represent the Sl1lTI exceed s the number o f bits in the two numbers, an onrllow results a'i indicated by an incorrect sign bit. An overnow can occur only when both numbers are positivc or both numbers arc negative. The fo llowing 8-bit example will illustr.atc this condition. 0 1111101 + Q() 11101O 10110111 - - - ----'i
125
±..2!i 183
T
Sign incorrect - Magnitullc incorrect - - - - -- "
In this cxample the sum of 183 requircs e ight magnitudc bits. Since thcre arc seven magnitude bi ts in the numbers (one bit is the sign), thcre is a carry into the sign bit which produces thc ovcrflow indication. Numben Are Added Two a t a Time
Now lei's look at the addition of a stri ng of numbers. added two at a limc. 1l1iscan be accomplished by adding the fi rstlwo num bers, thcn add ing the thinln umber to the sum of the first two, thcn adding Ihe fourth number to this result, and so on. This is how compulers add sirings of num bers. The addit ion or numbers laken two at a ti me is illustr""
I
EXAMPLE 2 - 19
Add the signed numbers: 01 000 100, 000 11011, 0000 1110. and 000 10010. Solution
The equivalent decimal additions are given for reference.
68 i.l1
Related Problem
+
95 + 14 109
0 1000 1Q() 000 1lQ11 OlUl 11 11
i
OOOOIIIQ
±....l.Ii
± 00010010
127
011 lIlJ]
0 1101101
Add ISllwO numbers lsi sum Add 3rd number 2nd sum Add 4th nu mber Final sum
Add Q() J IQ()I I, / 0 1111 1 J, and 0 11 000 11 . These arc signed numbers.
Subtraction Subt mction is a ~pcc i a l case of addition. For example. subtracting + 6 (thc subtrahend) from + 9 (the minuend ) is equivalent to adding - 6 to + 9. Basically.lhe slIbtraction ope/"lIIion clumges tile sigll of the .mblmhel1ll alld adds il to tht: 111;1111(:1/([. The resull o f a sub!raction is called the diffcrCIlct!. The sign of a posith·c or negath ·e binary number is changed by taking its 2's ('Ompicment. For example. when you take the 2's complement o f the pm itivc nu mber ()()()(X) 100 ( + 4), you get 11 111 100, which is - 4 a<; the following sum-of-weights evaluation shows: - 128 + 64 -1 32 + 16 + 8+4 = - 4
Subtraction il addition with the ~ign of the ~ubt:rahend changed.
70
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NUMBER SYSTEMS, OPERATIONS, AND CODES
As another example. when you take the 2's complemcnt ofthc negative number 1110110 1 (- 19). you get 000 1001 1. whieh is + 19 as the fO llowing sum-of-weightsl.:valualion shows: 16 + 2 + I = 19 Since sublmclion is simply an addit.ion with the sign o f [he subtrahe nd changed, the process is stated as follows: To subtnll1 two signed IIIlmbers. takt! the 2's I'Ompiement of tile subtnlhcnd nnd add. Discard any final carry bit. Example 2- 20
illustrate.~
the subtmction process.
Perform each of the following subtractions of the signed numbers:
Solution
(n) 00001000 - 000000 11
(b) 0000 11 00 - 11110 11 1
(c) 111 00 111 - 00010011
(d) 10001000 - 11100010
Like in other examples. the equivalent decimal subtmctions are given for reference. (a) In this case.
8 - 3 = 8 + ( - 3) = 5.
0000 1000 11111101 Discanl carry - - - ; ) J 00000101
+
(b) In Ihisease, 12 - ( - 9) = 12
+
+9=
0000 1100 0000100 1 00010 101
21.
+ (-
111 00 1 I I + 11101101 Di scard carry----;) I 11(110100
(d) In this ease, - 120 - (-30) = - 120 10001000 000 111 10
10100110
Related Problem
Difference ( +5)
Minuend (+ 12) 2's complement of subtrahend ( +9) Diftcrcncc (+2 1)
(c) In this case, - 25 - (+ 19) = - 25
+
Minuend (+8) 2's complement of subtruhend (-3)
19) = - 44. Minuend (- 25) 2's complement of subtrahend (- 19) Diffcrcncc(- 44)
+ 30 =
- 'Xl.
Minuend ( - 120) 2's complement of subtrahend (+ 30) Difference ( - 90)
Subtract 0 1000 111 from 010 11000.
Multiplication The numbers in a multiplication arc the multiplicand, the multiplier, and the pnxlul'l. llrese are illustmted in the following deeima1multiplication:
8 MultipliCCltion jJ equivalent to adding a number to itself a number of times equal to the multiplier.
X 3
24
MU1l'iplicand Multiplier Product
The multiplication operation in most computers is accomplished using addition. As you have already sccn, subtraction is done with an adder; now lei's see how mult iplication is done.
ARITHMETIC O PERATIONS WITH SI G NED NUMBERS
•
D irectlltlditioll andpclrlia/ p1Vducl~' arc two basic methods for perfonning multiplication using addition. In the direct addition method. you add the Illultiplicand a number of times equal to Ihe mUltiplier. In the previous decimal example (3 x 8), three multiplicands arc added: 8 + 8 + 8 = 24. The disaclvantage o f this approach is that it becomes very lengthy if the multiplier is a largc number. For cxmnplc, 10 multiply 75 X 350, YOUIllUSI add 350 to itself 75 ti mes. Incidentally, this is why the term limes is used 10 mean multiply. When Iwo binary numbers are mUltiplied, both num bers mllst be in IIl.le (uncomplcmented) fonn. Thcdircct addition method is illuSlmtcd in Example 2- 2 1 adding two binary numbers al a time.
Multiply the signed binary numbers: 0100 11 01 (mul1 iplicand) and 00000 100 (multiplier) using thc direc t addition method .
wlution
S ince both numbers are positive, they are in true form, and the product w ill be positive. The decimal valuc of the multiplier is 4, so the multiplicand is added to itself four times a~ follows:
01001101
+ QlOOIIQI 100 11010
+ QlOO ll QI 111 00 111
+ 0100 1101 10011OJOO
1st ti me 2nd li me P'
Since the sign bit of the multiplicand is 0, it has no effect on the outcome. All of the bits in the product are magnitude bits.
Related Problem
MUltiply 0 1100001 by {)()(XJ() I IO using the di rect addition method.
The IXll1iai products method is perhaps the more common one because il reflects the way you multi ply long.hand. T he multiplicand is multiplied by each multiplier cligit beginning with the least significant digit. The result of the multiplication of the multiplicand by a multiplier digit is called a pan;(l/ product. Each successive partial product is moved (shifted) one place to the left and when all the partial products have been prtxluccd, they arc added to get the final product. Here is a decimal example. 239 123 7 17 478 + 239 29,397 X
M ultiplicand Mult iplier 1st pru1ial product (3 X 239) 2nd partial product (2 x 239) 3rd partial produc t ( I X 239) Final product
The sign of the product of a mUltiplication depends on the signs of the multiplicand and the multiplier according to the fo llowing two rules: If the signs are the same, the prod uct is positi ve. If t he signs a l'e different, the product is negative. The basic steps in the pm1iai products method of binary multiplication al"(' as follows: Step 1. Oetennine if the sig.ns o f the multiplicalld and mulliplier arc the same or different. This detennines what the sign of the product will be.
71
72
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NUMBER. SYSTEMS, OPER.ATIONS, AND CODES
Step 2. Change any negative number to true (uncomplemented) form. Because most computers store negat ive numbers in 2's complement. a 2's complement operalion is req uired [ 0 ,ge[ [he negative number into true form. Step 3. Staning with the least significant mu ltiplier bit. generate the partial products. When the ITllllli plicrbit i)' I . the par1 ial product is the sallle as the multiplicand. When the multiplier bit is 0, the partial product is zero. Shift each successi' "e partial product one bit to the left. Step 4. Add each successive partial product to the sum of the previolls partial products 10 get the fin al product. Step S. If the sign bit that was determined in step I is negativc. take the 2'scomplcment of the product. If positive. leave the product in true fonn. Attach the sign bit to the product.
I
EXAMPLE 2-22
Multi ply the signed binary numbers: 0101001 1 (mUltiplicand) and 11000101 (multipli er). Solution
Step l:
The sign bit of the multiplicand is 0 and the sign bit of the multiplier is I. The sign bit of the product will be I (negative).
SIt'p 2: "Ja.h· the 2's complement of the multiplier to put it in tllle fonn. 11 000101 ------) 00 11 101 1 Sleps 3 and 4: The multiplicalion proceeds as follows. Notice that only the magnitude bits ,Ire used in these steps. 101 00 11 X 0 111 011 10100 11 + 1010011 1111 1001
+ ()Q(!(!()(!() 0 11111001 10100 11 111 0010001 + 1010011 1000 11000001
+
+
I OJoo l1
100 11 00 100001 + 0000000 100 1100 10000 1 Step 5:
Multi plicand Multipl ier Ist partial product 2nd pan ial product Sum of 1sl and 2nd 3rd partial product Sum 4th panial product Sum 5th pal1ial product Sum 6th pal1ial product Sum 7th partial product fi nal proc.luct
Since the sign of the prtxiuct is a I as determ ined in Step I, lake the 2'5 complement of the product. 1001 100 100001---» 0 11 0011011 111 Attach the sign bil ~ J 011001l01lJlI
Related Problem
Verify the multiplication is correct by convening to decimal numbers and pctfonning the multiplication.
AR ITHMETIC O PERATI ONS WITH SIGNED NUMBERS
•
Division T he numbers in a di visiun tire the dividend, the divisor, and the Ijuotient. These
=......:L -
14 7
7
=......:L
o
Dividend I st subtraction of divisor I st partial rcmainder 2nd subtraction of divisor 2nd partial remainder 3rd subtmction of di"isor Zero remainder
In this simple example. the divisor was subtracted from the dividend three times before a remainder of zcro was obtained. TherefOl"C.the quoticnt is 3. TIle sign of the quotient de[X!nds on the signs of the dividend and the divisor according to the following two ru les: If the signs IH'! the. sume, thc Quoticnt is posit ivc. If the signs arc different, the Quotient is negative.
When two binary numbers arcdividcd. both numbers must be in true (uncomplcmcmed) form. The basic steps in a division process arc as follows: Step I. Determine if the signs of thc d ividcnd and d ivisor me the same or different. This determines what the sign of the quotient will be. Initial ize the quotient to zero. Stell2. Subtract the divisor from the dividend using 2'scomplement addition to get thc fi rst pmlial remainder and add I to the quotient. Ifthis par1 ial remainder is positive, go to step 3. If thc parti;\! remainder is ,..em or negative. the division is complete. Stel) 3. Subtmct the divisor from Ihc pal1ial remainder and add I to the quotient. If thc result is positive, re[X!at for the next palt ial remainder. Ir the I"CSUlt is zero or negativc, the division is complete.
Cont in ue to subtract the divisor from thc dividend and the partia l remainders until thcre is a ,..ero or a negative result. Count the number of ti mes thatlhe di visor is subtracted and you have the quotient. Example 2- 23 ill ustrates these steps using 8-bit signed binary numbers.
DjvideO I1 00 l OO by 000 1 100 1. Solution
Stcp 1: The signs of both numbers are posit ive, so the quotient will be positive. The quotient is initially zero: ooOOOOeXl
73
74
•
NUMBER SYSTEMS, OPERATIONS, AND CO DES
Step 2:
Subt mct the divisor from the dividend using 1's complement addition (remember that final carrics are discarded).
+
01100 100 111 00 111 01001011
Add 1 10 quotient: OOOOOOOO Step 3 :
Dividcnd 2's complement of di v i ~or Positive 1st panial remainder
+ 00000001 =
0000000 1.
Subtract the divi.~or fll)lll the Ist partial remainder llsing 2's complement addition. 01001011
+ 11100111 00 11 0010
1st pmtial remai nder 2's complement of di visor Positive 2nd partial remainder
Slep 4: Subtract the di visor from the 2nd partial remainder using 2's complement addition. 001100 10
+ 11100111 000 11001
Add I to quotient: 000000 10
Step 5:
+ 00000001
= 0000001 1.
Subtract the divisor from the 3rd partial remainder using 2's complement addition. 000 11 00 1
+ II 100 1 II OOOOOOOO Add I to qUOlient: 000000 11 process is complete. Related Problem
2nd partial re mainder 2's complement of d ivisor Positive 3rd partial remainder
3rd pal1ial remainder 2's cumplement of divisur Zero remainder
+ 00000001
= 00000100 (final quotient). 111c
Verify that the process is correct by cunverting to decimal num bers and JX!rforming the division.
1. list the four cases when numben are added. 2. Add 0010000 1 and 10111100. 3.5ubbact OO 11 00 10fromOl110111 . 4. What is the sign of the product when t'J.IO negative numbeo are mu ltiplied?
5. MultiplyOl111111 byOOOOOtOI. 6 . What is the sign of the quotient v.--hen a politive number is divided by 11 negative number? 7. Divide 00110000 by()(H)()1100.
HEXADECIMAL NUMBERS
_
7S
HEXADECIMAL NUMBERS
2 -8
The hexadecimal number system has sixteen char'dcters; it is used pri marily as a compact way of d isplaying or writing binary numbers because it is very easy to convcr\ between bin
• U st Ihc hexadecimal characters - Count in hcxadecimal - Convclt from binary 10 hexadecimal - Convcll from hexadecimal to binary - Convcrt fro m hcxadecimallo decimal _ Convcrt from decimal 10 hexadecimal - Add hcxadecimal numbers _ Dctennine the 2's complement ofa hexadecimal number - Subtract hexadecimal numbers
The hc~adccim ul number system has a base of sixteen; thai is, il is cum posed of 16 numeric and alphabetic charucters. Most dig ital systems process binary data in groups thai arc multiples of four bilS, making the hexadecimal number very convcniem because each hcxudecinml digit represenlS a 4-bil binary num ber (as listed ill Table 2-3). TABLE 2 - 3
DECIMAL
BINARY
HEXADECIMAL
0
UOOO
U
2
3 4
000 1 0010 0011 0 100
I
2
3 4
,
010 1
5
0110
7
0111
8 9
1000 1001
6 7 8 9
10
1010
A
II
101 1
B
12
1100
C
IJ
11 01
0
14
1110
E
15
1111
F
5
Ten numeric digi ts and six alphabetic characters make up Ihe hexadccimal number system. The use of lettcrs A. B. C, D, E, and r- to represent numbers may seem strange al first, but kecp in mind thai allY number system is only a set of sequential symbols. If you understand what qunntitics these symbols represent, thcn the f0I111 of the symbols themselves is less important oncc you gel accustomed to llsing them. We w ill use the subscript 16 to designate hexndecima l numbers to avoid confusion with decimal numbers. Sometimes you may sec an "h" follov.'ing a hexadeci mal number.
The hexadecimal number J)'Stem consists of d igits 0-9 and letters A- F.
76
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
Counting in Hexadecimal How do you counl in he::xlIdecirna l once you gel 10 P! Simply stan over with another column ,lI1d continue as foll ows: range, specifying a memory address in binary is quite , cumbenome. For example, it takes 32 bits to specify an address in a 4 GB memory. It is mucn easier to express a 32-bit code using 8 hexadecimal digits.
10. II. 12, 13, 14. 15. 16, 17, 18, 19, IA. IB, IC, ID, IE. IF, 20, 2 1. 22, 23, 24, 25,26, 27,28.29. 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, . .. With two hex"dl."Cimnl digits. you c,m count up to ff 16• which is dedmal 255. To count beyond this, three:: hexlIdeci mnl digi t ~ are needed. For instance. 100 16 is decimal 256. 101 16 is decimal 257, and so fOllh. 1llt.~ maximum 3-digit hexadecimal num ber is FFF I6 , o r decimal 4095. The maximum 4-digit heXlldecimal number is FFFF16 , wh ich i~ decimal 65.535.
Binary-to-Hexadecimal Conversion Converti ng" binary number to hex"decimal is a stfilightforward procedure. S imply break the binary number imo 4-bit groups, starling al the right- most bit and rcplllce each 4-bil gro up wi th the equivalent hexadecimal symbol.
I
EXAMPLE 2-24 Converllhe following binary numbers to hcxlldedmnl: (a) 1100101001010 111
SolutiOI1
(b) 1I1 I 11 000101 l{J lOOI
(a)!.J.m.!Q!..OOlQ!Q!!!
!
!
!
!
C
A
5
7
= CAS7 11>
Two ze::ros have bt:en ,ldded in p,ln (b) to mmplete a 4-bit group ,It the left.
Related Problem
Convel1 the:: binary nu mber 10011 11 01 111 001 11 00 to he xade::cimal.
Hexadecimal-to-Binary Conversion Hexadecimal i5 a convenient way to represent binary numben.
I
To convert from a hexadecimal number to" bimlry number. fe vcrse the process ,lIld replace each hexade::cim
EXAMPLE 2-25 Determine the binary nu mbers for the following hexadecim,ll numbers: (e) 9742 16
Solution
(a) l
OA
~
'.J.!! 1000010100100
(b) C
F
8
E
!
!
!
!
~
1100111110001110
(e)
9
7
4
2
~ 1001011101000010
In pmt (a). th e:: MSB is understood to have three zeros preceding it, thus formi ng a 4bit grou p.
Related Problem
Convert Ihe hexadecimal number 6803 to binary.
HEXADECIMAL NUMBERS
It should be d ear thai il is mUl:h ea~ ier 10 deal wi th a hexadecimal number than with the (.'quivalenl binary number. Sil1l:c conversion is so easy, the hexadecimal system is widely used for representing binary numbers in programming. pr into uts. and displays.
•
COll'll'enion between hex~dedm~] ~nd bin~ry
is direct
and e~sy.
Hexadecimal-to-Decimal Conversion One way to find the dccimal equivOl]em of ul1t:xOldeci mal number is to first convert the hexOldecimal number to bina\)' and then convert from binary to decimal.
I
EXAMPLE 2-26
Convert the following hexadecimal nu mbers to decim:l]:
(b) A85 16 Solution.
Remember. convert the hexadecimal number to binary first, then to decimal. C
(a)
t
t
0001 1100 = 24 + 23 + 22= 16 + 8 + 4 = (b)
A
8
5
t
t
t
2810
'iOfa~ = 21 1 + 29 + 27 + 22 + 2° = 2048 + 512 + 128 + 4 + I = 2693 10 Related Problem
Convert Ihe hexade(.;mOllllumber 6BO to d(.'("imal.
Another way to convert a hex'ldecimal number 10 ils decimal equivalent is to multiply the decimal value of each hexadecimal d igit by its weight and then take the sum of Utesc products. 'Ille weights of a hexadecimal number are increasing powers of 16 (from right to left). r-or 11 4-digil hexadecimal number, lhe weighls are 163 4096
16 2
16 1
16°
256
16
1
I
EXAMPLE 2-21
Com'crt the following hexadecimal numbers to decimal:
(a) E5 16 Solution.
(b) B2F8 16
Recall from T'lble 2- 3 Umt letters A through 15, respectively. (a) E5 16 = (Ex 16)
(bl 82£'8 "
Related Problem
Convert
+ (5x
~
to decimal.
represent decimi.l l
I) = ( 14x 16)+ (5x I) = 224
( 8 X 4(96) = ( 11 X 4(96) = 45,056
6OA16
r
+ (2 + (2
+
77
llumb~rs
10 through
+ 5 = 229 10
X 256) + (F X 16) + (8 X I ) X 256 ) + ( 15 X 16) + (R X I) 5 12 + 240 + 8 = 45.816 10
78
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
,' "
Powers of 16 Find the value of 164 .
&Dmple
Step l.
'1'1-86
Step 2.
Step I.
TI-36X
Step 2.
aaa amml aa 0
16 1\ 4
65536
65536
a 8
Decimal-to-Hexadecimal Conversion Repe
I
EXAMPLE 2 - 28
Convert the decimal number 650 to hexadecimal by repeated division by 16.
Solution
Hexadecimal re mainder
650
16 = 40.625----+0.625XJ6 = JO =
A---,
~
40
-
= 2.5 - --» 0.5 X 16 = 8 =
'~
2 -16 = 0. 125 ...----to. 125
L Rela ted Problem
X 16
=2 =
Stop when whole !lllmber quotient is zero.
:=J 8
MS D
A
Ilexadecimill number
L LSD
Convel1 decimal 2591 to hexadecimal.
Hexadecimal Addition Addition can be done directly with hcxadecimal numbers by reme mbering that the hexadecimal d igits 0 through 9 arc equi valent to decimal digits 0 through 9 and that hexadecimal digi ts A lhrough F are equivalent to decimal numbers 10 through 15. When "dding two
HEXADECIMAL NUMBERS
•
hexadecimal numbers, uSt: the fo llowing m les. (Decimal numbers are indicated by a subscript 10.)
l. In any given column of an addition problem, think o f the IWO hexadecinml di g il~ in te rms of their decimal values. For inslance, 5'b = 51() and C 16 = 12 '0' 2. If the sum of these two digits is I 5 10 0r less, bring down the colTes ponding hexadecimal digit. 3. If the sum o f theSt: two digits is greater ,him I 5 u,. bring down the amount of the sum that excl.:cds 16 '0 and carry a 1 10 the next column.
A c.alculator can be used to perfonn arithmetic operations with hexadecinal numbeB.
COllwrsion of a Decimal Number to a IIexadl.ocimal Number Convert deci mal 650 10 hexadecimal.
&0""'"
BASE
Slep 3.
sam aaa m
Slep 4.
lEi!
Step I.
D @J
Step 2.
aaa
Step 3.
DGJ
Step 1.
TI-86
Step 2.
650 .. Hex
,BAh
DEC
TI-36X
HEX
28A
Add the foll owing hexadecimal numbers: (a) 23 '6 + 16 16
Solution
(b) 58'6 + 22'6
(e) 2 B I6 + 84 16
(d) DFI6 + AC I~
(0)
23 16 + 16 16 39 16
right column: left colu mn:
3 16 + 6 16 = 3 10 + 6 10 = 9 10 = 9 16 21f> + l ib = 2lU + I lu = 310 = 31(>
(b)
58' 6 + 22u; 7A I6
righl column : left column:
8 16 + 2 16 = 8 10 + 2 10 = 10 10 = AI6 516 +216= 5 10+ 210= 7 10= 716
2B I6
right column: left column:
Bi b + 4 16 = 11'0 + 410 = 15 10 = Fu; 2 16 + 8 1b = 2 10 + SIO= IOI!) = A lb
right column:
F I6 + elf> = lS I!) -I- 12 10 = 27 10 2710 - 16 10 = 1110 = BI6 with a I calTY Duo, + Al b + 116 = 13 ro + IO ro + 110 = 24 ro 24 10 - 16 10 = Sill = Sib with a I carry
(e)
+ 84 16 AF 16
(d)
DFlb
+ AC 1b 18B II>
Rela ted Problem
left column:
Add 4C 16 and 3A 16.
79
80
•
NUMBER SYSTEMS, OPERATIONS, AND COD ES
Hexadecimal Subtraction As you have learn<.'{\. the 2's complement allows you to subtract by adding binary num bers. Since a hexadecinml number cnn be used to represcnt a binary num ber, it can also be used to re pn:sent the 2's complement of a binary number. There arc three ways 10 gclthe 2's complement of a hex:ldecimal number. Method I is the most common and easiest to usc. Methods 2 and 3 are nilernnte methods.
Melhod l.
Convert the hexadecimal number to binary. l ltke the 2's t~ompleme nt of Ihe binary number. Convert the result 10 hexil(lecimal. This is illustrmed in Fillllre 2-4.
I---'
HCJla(k:cirnaJ
Bin;!!y
r---
2'8 cumplement in billa!)'
-
2's co mplement in hexadec imal
Example:
L-___ 2 _A____
~~L
___ OO_IO_ I_O_IO__
~~L
___ 1I_0_IO_I_'O__
~~L ~ ~ ________
FIGuRE 2-4
Getting the l's complement of a hel
Method 2.
Hexlldecimal
Subtract the hexildedmal number from (he tmtximum hexadecimal number and add I. This is ill ustnttL'{\ in Figure 2- 5.
r---
Suhim<.:\ from maxi mum
-
J's m mplemcnt in hexadecimal plus I
-
2's complement In hex~d(l:;rnal
E.xample:
2A
H H H FF - 2A
D5+ t
Db
FIGURE 2 - 5
Getting the 2's complement of a hexadec'rTI
Method 3_
Write the sequence o f single hexadecimal digits, Write the sequence in reverse below lhe fonvaru sequence. The I's complement of e:lctJ hex digit is the d igit di rectl y below it. Add I to the resulting number to gel the 2's (~olllpicmen t. 'I"his is ill us trated in Figure 2--6.
HEXADECIMAL NUMBERS
Hexadecimal
r---
0 1 234 5 678 9 f1 B C OEF FE OrBA9 8 7 65 4 3 2 I 0
~
, 89 ~ B C DEF
~
l 's oomplcmcm in hexadeci mal
pills I
-
2's com plc"'<'m in hcx8l~('Cima l
-
06
Example:
O I ~ 3 456
F E D CRA 9
7
76 5 432 1 0
D5 + I
FIGURE 2_6
Getting the 2'1complement of a hexadecimal number, Method J.
I
EXAMPLE 2-30 Subtmcl the following hexadecimal numbers:
Solution
(u) 2AI6 = 00 101010
2'5 complclllcnl of 2 A I6 = 11 0 101 10 = 06 16
(using Method I)
84"
+ D6 16 /SA I6
Add
Drop carty. as in 2's complemenl addition
The differencc is SA lt>. (b) OB I6 = 000010 11
2's complement of OB I6 = 11 11 0101 = F5 16
(using Method 1)
C3 16
+ F5 16 ,iB8 1f>
Add
Drop carry
TIle differe nce is 88 16,
Related Problem
I
SECTION 2-8 REVIEW
Subl racl 173 16 from BCD I6.
1, Convert the following binary numbers to hexadecimal:
(a) 10110011
(b) 11 00111 01000
2. Convert the following hexadecima l numbers to binary:
(a)
57 16
(b)
(c) F80B I6
3A5 16
3. Convert 9B301/"; to decimal. 4. Convert the decimal number 573 to hexadecimal. 5. Add the following hexadecimal numbers directly:
(a) 18 16 + 34 16
(b) 3F I6
+ 2A16
6. Subtract the (allowing hexadecimal numbers:
(a)
75 16 -
21 16
(b)
94 16 -
5C r6
•
81
8Z
_
2-9
NUMBER SYSTEMS. OPERATION S. AND CODES
OCTAL NUMBERS Like the hexadecimalnurnber syslem, the octal number system provides a conveniem w
The octal numbe r system is composed of eight digits, which aTe
0, [, 2.3,4.5.6.7 To count
10, II , 12. 13, [4. 15. 16. 17.20.2 1•. ,. The octal number ,},stem has a base of 8.
Counting in octal is similar to counting in decimal. exccpl lhm the digits Sand 9 are nOl usN. 'Ib di!
Octal-to-Decimal Conversion Since the octal nllmber system ha" a base of eight. each s uccessive digit position is lin increasing powe r of eight, beginning in Ihe righi- most colu mn with 8°. The evalumion of an oclal nu mbe r in terms of its dt.'clmal equivllleni is lK'{;omplished by multiplying each di git by i l.~ weight and summing the products, as illustrated here for 2374~, Weighl: 83 82 8 1 8° Octal numbe r: 2 3 7 4 237411 = (2 X 8
3
)
~ (2 X 5I2)
=
1024
+ (3 X 8') + (7 X 8' ) + (4 X 8") + (3X64)+(7X8) + (4X I) + 192 + 56 + 4
Decimal-to-Octal Conversion A method of converti ng a decimal num ber 10 an octal number is the repeated di vision-by8 method, which is similar to the me thod used in the l'onvcrsion of decillllli numbel"S to binal}' or to hexadecim:t1. To s how how il works, Jet's convert the decimal number 359 to octal. Each successive division by 8 yields a re mainder that becomes a digit in the eqU iV.llent QCtlll nllmber. The fi rst remainde r genemted is the least signific:Ult digit (LSD).
359 = 44 ,875 -)00.875
8.--J ~ 1. J
44
8
0 .625
T
-0.5 X 8 ---+{) 625
Stop when whole number quoticnt
i~ /CHI
RCIll:tinder 8 = 7 ---,
5
8
~=
x
~
4'll
X8= 5 4 7
MSDJ
l
Oclal
L~D
nUIl1~ r
OCTAL NUMBERS
•
83
Conversion of a Decimal Number to IiID Ochtl Num ber Convert decimal 439 to octal.
&nmpk
439 .. Oct 6670
BASE
'1'1 ·86
Step I.
.am
Step 2.
aElEl
Slcp 3.
m
Slcp4.
I&l DEC
TI ·36X
St('p I.
D~
Step 2.
alUJ
SI('p 3.
D
OCT
667
II
Octal-to-Binary Conversion Because each octal d igit c.m be represented by a 3-bil binary number, it i ~ very easy to convert from octal (0 bina ry. Each octal digit is represcnt(xl by three bits as shown in Table 2-4.
Octill is il cofl\lenient way to represent binilry numbers, but it is not iU commonly used ill hexilde cimal.
TABLE 2 _ 4
Octili/binary convenioo. OCTAL DIGIT BINARY
o
I
2
000
00 1
010
3 011
4
5
6
7
100
lU I
11 0
III
To cOllve/t an octnlllumher 10 a binary number, simply replace ench ocllll digi t w ith the lIpproprillte three bits.
i
EXAMPLE 2 - 31 Convert ellch of Ihe fo llowing oclnl numbers to binary: (a) 138
Solution
(a)
(b) 258
3
J, J,
mmm Related Problem
(b)
(c) 14(ls
2
5
J, J,
olofOl
(c)
(d)
4
752(~
0
J, J, J, OOIlO0000
(d)
7 5
2
6
J, J, J, J, mloiOiOfiO
Convert each oflhe binary numbers to decimal and verify that ellch vallie ag rt:es with the decim:J1 value of the corres\Xlnding octal number.
Binary-to-Octal Conversion Conversion of 11 binary number to an octal nwnbe r is the reverse of the ocwl-to-binary conversion. '!lte procedure is as follows: Slart with the right-most group o ft hrce bils and, moving from right 10 left , convert each 3-bit group to the l"luivalenl oct.,1 d igit. If the re are not th ree bits avai lable for the left-most group,
84
•
NUMBER SYSTEMS. OPERATIONS. AND CODES
I
EXAMPLE 2-32
Conver! each of Ihe following binary numbers to OCla\: (a) 110101
Solution
(a)
(b) 1011 11 00 1
UQ.!.Q!
(b)
J- J6
(d) llOHXXX) l oo
!illW ID! J- J- J5
5 = 65,
TTTT 4 6 3 2 = 4(132
7
1 = 57111
(d)¥T~!f
(e) 100 110011010
ReJated ProbJem
(e) 100 1100 11010
8
3
2 0
4 = 3204H
Convert the binary number 1010101000 11111 00 1010 octal.
1. Convert the following octal numbel"l to decimal: (,) 73, (b) 125, 2. Convert the following decimal numbel"l to octal: (a) 98 10 (b) 163 10 3 . Convert the following octal numberl to binary:
(,) 46,
(b) 723,
(e) 5624,
4. Convert the following b inary numben to octal:
(a) 11 01011 11
2-10
(b) 1001100010
(c) 10111111001
BINARY CODED DECIMAL (BCD) Binary coded decimal (BC D) is a way 10 expre.,>s each of the decilll,,1 digits with a binary code. There arc only ten code groups in the BCD system, so it is very emiY to convcrt betwcen dccim'll and BCD. Because we likc to read nnd write in decimlll, the BCD code provides an excellent interface to binary systems. Examples of such interf.aces are kcYJXld inputs and d igital rClldou ts. After completing this section, you should be able to • Convert each decimal digillO BCD . Express decimal numbers in BCD . Convert from BC D 10 decimal • Add BCD numbers
The 8421 Code In BCD. 4 bib represent each
decimal digit.
The 842 1 code is a Iype of nco (binary coded decim
BINARY CO DED DECIMA L ( BCD)
BCD
o
DECIMAL DIGIT
3
2
4
5
0000 0001 0010 00 11 0 100 UWl
6
7
8
9
0110
0111
1000
100 1
Dedmal/BCD conversion.
Invalid Codes You should realize that , with four bits. sixteen numbers (0000 through J il l) cm} be re presented but that. in the 8421 code. only ten of these are used. The six code combinations that are not used- 1010, 1011, 1100, 110 1, 111 0. and I I I I-are invalid in Ihe 842 1 BCD code.
To express any decim.1I number in BCD. simply l-eplace each decimal d igit with the ap-propriate 4-bil code. as shown by Exmnple 2- 33.
I
EXAMPLE 2-33
Convert each o f the following decimal numbers to BCD: (}I)
Solution
(a)
35 3
(e) 170
(b) 98
(b)
5
! ! 00110101 (e)
1
7
9
8
!
!
IoomiiiO 0
(d)
! ! ! 00010i"nOOOO Related p,.oblem
(d) 2469
2
4
6
9
! ! ! ! oOloO.i OOolloIOtIT
Convert the decimal number 9673 to BCD.
It is equally easy to determine Hdecimal number rrom iI BCD number. Start at the rightmost bit and break the code into groups of fom bits. ll1en write the decimal digit represcntt.'d by eHch 4-bil group.
i
EXAMPLE 2-34
Convert each of the fo llowing BCD codes to dl.."1.·imal :
Solution
(a) HXXXl l lO
(b) 00110101000 1
(a) 10000110
(b)
TT 8
Related p,.oblem
6
~ II OlO l ooo.....!
(c) l OO IOIOC() l ll(XX)() (c)
IOOIO IOOO1 11(ffi)
~
!
!
!
!
!
!
!
3
5
I
9
4
7
0
Convert the BCD code 1000001000 1001 1101 10 to decimal.
BCD Addition BCD is a numerical code and can be used in ari thmetic operations. Add ition is the most important opemtion because the other three operations (subtmction , multiplicalion, and divi sion) elln be lIccomplished by the usc o f ildditioll. Here is how to add two BCD numbers: Step I. Add the lWO BCD numbers, using the rules for binary addition in Section 2-4. Step 2. If a 4-bit sum is equal to or less than 9, it is a valid BCD number.
•
8S
86
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
Step 3. If a 4- bit sum is greater than 9, or if a carry out o f tile 4-bit group is generated. it is an invalid result. Add 6 (0 110) 10 the 4-bil sum in order to skip the six invalid states and relurn the code to 842 1. If a carry results when 6 is addc-'
i
E)(AMPLE 2-35 Add the following BCD numbers :
(b) 00 1000 11 + 000 1010 1
(3) 00 11 + 0100
(c) 10000 110
Solution
+ OOU l oo11
(d) 0J(XX)1 01(XlOO
+ 010000010 1I J
The dl.~ i mal num ber addit.ions arc shown for comparison. (a)
3 +4 7
00 11
±JlJ.lI!l 0111 (e)
1000
(b)
0 110
86
+ 0001 00 11
±..ll
1001
99
1001
(d)
00 10
00 11
23
+ {lX) 1
OIQI
±J2
0011
1000
38
0100 0101 (XXX) + Q100 0001 0 111 1000 0110 0111
450 +-t17
867
NOle Ihal in eaeh (.:asc the sum in any 4-bit column docs not exeeed 9. and the results arc valid BCD numbers.
Related Problem
i
Add the BCD numbers: 100 I(XXJOO J(XX)(J 11
+ O
EXAMPLE 2-36 Add the following BCD numbers (3) I LXlI
+ OJ(X)
(e) 00010 110
Solution
(b) 1001
+
+
100 1
(d) 01 10011 1 + 010 100 11
Ihe decimal number additions are s hown for comparison .
)00 )
(a)
9
+ 0 100 1101
+ OI l!} 0011
0001
~
~
.l
.l
H Invalid BCD nu mber ( > 9) Add 6 Valid BCD number
13
3 (h)
+
100 1 IO(H 00 10
+ (l lW 0001
1000
~
~
.l
.l
"
9
±.2 Invalid because of carry Add 6 Valid BCD number
18
DIGITAL CODES
(c)
+Q!:}Q I
0 11 0 OIQI
(X) I O
10 11
OO()I
+0110
0011
0001
L
L
~
~
•
16
±...li 31
Righi group is invalid (> 9), left group is valid. Add 61n invalid code. Add carry. 000 I. to next group. Valid BCD numlx:r
3 (d)
0001
~
0 110 + 0101 1011 + !lIIO 0010
Relnted Problem
I
SECTION Z 10 REVIEW
67
±...TI
1010
~
L
0111
!lllll Both groups arc invalid (>9) Add 6 to both groups Val id BCD num hcr
+ !} II Q 0000 ~
L
L
2
0
Add thc BCD nu mbers: OHX)1000
120
+ 00 11 0100.
1. Whclt is thc binary weight of each 1 in the following BCD numben;?
(,) 0010 2.
Con\ICrt
(,) 6
(b) 1000
(e) 0001
(d) 0100
the following decimal numbers to BCD;
(b) 15
(e) 273
(d) 849
3. Whclt decimal numbers are represented by each BCD code?
(,) 1000 1001
(b) 001001111000
(e) 000101010111
4 . In BCD addition, when is a 4- bit sum invalid?
2 -11
DIGITAL CODES
Many spl.'cializt:d codes arc u$(.'<1 in digi lal systems. You have just learned about the BCD code: now let's look at a rew others. Some codes arc strictl y numeric, likc BCD, and others lire alphan umeric; Ihal is, they arc USI..'
The Gray Code The Gray ('ode is unweighwd and is not lin arithmetic code; Ihal is, there arc no sJX'Citk weights assigned to the bil positions. The important feature of the Gray code is Ihat it exhibits ollly a single bit changefrom one COlle IVOrd 10 the next ill .~eq!fellce. This propert)' is important in mall}' applications, such as shan position encoders, where error susceptibil ity increases wit b the numocr of bit changes belween adjaccnt numbers in a sequence.
The single bit ch
87
118
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
Table 2-6 is a lisling oflhe 4-bil Gray code for dl:cimal numbers 0 Ihrough 15. Bin;)ry numbers arc .~ h{)wn in the t;)ble for rcferenl:e. Like binary numbers. rlie Gmy Lode can lJ(!ve allY number of bil.~. No tice the single-bit change betwt:cn succc~sivc Gray code words. For instance, in going from dt:cimal 3 to d(:cimai 4, the Gray cede changes from 0010 to Ol i O, while the binary code changes from 00 11 to 0 100, a change of three bits. The only bit change is in the third bit from the right in the Grdy code; the others remain the same.
TABLE 2 - 6
Four- bit Gray code.
DECIMAL
BINARY
0
0000
I
000 1
2
001 0
J
0011
,
DECIMAL
BINARY
0000
8
1000
11 00
000 1
9
100 1
1101
00 11
10
1010
I I II
00 10
11
lOl l
111 0
0100
0 11 0
12
11 00
1010
0101
01 11
]J
t 10 1
1011
6
0 11 0
010 1
14
1110
I ()() I
7
0 111
0100
"
! 111
1000
4
GRAY CODE
GRAY CODE
Bmary-to-Gmy Code Convenion Conversion between binary code and Gray code is sornetimt.'S useful . The fo1Jowing ruk'S cx pl;)in how to convel1 from a binary number to a G ray code word:
J. The most signifil:anl bit (left-most) in the Gray code is the same as the corresponding MSB in the binary number. Going from left to righI, add each adjacent pair of bi nary code bilS 10 gctthc next Gray code bit. Discard carries.
2.
For example, the conver.;ion o f the binary number 101 10 to Gray code is as follows: I-
+-)0 1 ---1 -)0 1 - +-)0 0
t
t
t o
B i OiIl"}'
t G",y
TIle Gray code is 11101 .
Gray- to- Binary Convenion To convert from Gray code 10 binary, usc a si mi lar melhcxl; howevcr, there arc some diffcrcnl:es. The following rules apply:
1. The mosl significant bit (left -most) in the hinary code is Ihe same as the corresponJ ing bit in the Gray code.
2. Add each binary code bit generalt.'d position. Discard carries.
10
the Gray code bit in the next adjacent
For exnmple, the conversion o f the Gray code word 11 0 II to binary is as fol lows:
I
G",y
"'t u The binary number is UXlIO.
Binary
DIGITAL CODES
•
I
EXAMPLE 2 37
(a) Com'el1 the binary number 11000110 to Gray code. (b) Convert the Gray code 10101 111 to binary.
Solution
(a) Binary to Gray code:
1- +--)- 1-+ --)- 0 +_ 0 - + - 0- +-+ 1 .j,
1
.j,
+ --)- 1- + --)- 0 .j,
.j,
o
.j,
'"
o
",0
....,, 1
o
'"
.j,
o
(bl Gray code to binary: ,
", 0
", J,'
'"1/ + '"1 / + 0 Relnted Problem
/
+ J, + 0/
(al Convel1 bi nary 10 110! to Gray cooc.
.j,
....,, 1
+ J,
,/
0/
,
...." I
.j,
,/
...." I
+ J, 0
(hI Convert Gray code 100 111 to binary.
An Application A simplified diul,1ram of a 3-bit shafl position encoder mechanism is shown in FiguI"C 2-7. Basically. there are thn.:c concentric conductive rings thut arc segmented inlo eight sectors. The more SL'CtOrs there arc, the more at.:curately the position can be represented. but we are using on ly eight for purpoSt.'S o f ill ustration. Each sector of each ring is fixed at either a high-lcvel or a low-Icvel voltagc to represent Is and Os. A I is indicated by a color St.'Ctor and a 0 by a white sector. As !llc rings rOlate with the shaft, they mllke contact with a brush arrangement that is in a fixed position and to which output lines areconnt..'Cted. As the shaft rotates counterclockwise throug h 360· , the e i~ht sectors move past the three brushes producing a 3-bi t binary ootpul thai indicates thc shaft position.
("Unl:lce I1nl,llI:'<; in :l fi,C
;;;~~~~~~~~ ur tile locating cl>nllu.:thc ring, 3·bil
J.bil
"'!l1ar)
(ir;!}
c,otJ,>
(aJ Dinary
(b) Gray colle
FIGURE 2 - 1
A iimplified iUuitration of how the Gray code sol~ the error problem in shaft pOlition encoder!.
89
90
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
In Figure 2-7( a), the sectors arc arrangt..'Cl in a straight binary pattern. so tilat the brushes go From 000 to 00 1 to 0 I 0 to 0 11 . and so 00. When the brushes are on color sectors, they output a I und when on white St!ctors, they output a O. If one brush is slightly ahead o f the others during the transition from one sector to the next, an erronl."Ous output can occur. Consider what happens when the brushes are on the I I I sector and !lbout to enter the 000 sector. If the MSB brush is slightly ahcad. the position would be incorfl'c tl y indicatl.'Cl by a transi tional 0 11 instead of a I II or a (XX). In this type of application. it is virtually impossible to maintain pn.·cise mechanical alignrn t· nt o f a ll the bru slw~: therefOR'. some error will always occur at many of the transit ions between SL"CIOrs. The Gray codc is used to eliminatc the error problem w hich is inherent in the binary code. As shown in Figure 2-7(b). the Gray code assures that only one bit will change bctWl."Cn adjacenl Sl."Ctors. This means that evcn though the brushes may nOl be in precise alignment. there will never be a transitional error. for example. let's again consider what happens when the brushes are on the 111 sector and about to move into thc ncxt St."Ctor, 101. The only two possiblc outputs duri ng the transit ion are I I I lind W I. no matter how the brushes arc aligned. A si milar situation occurs at the transitions between each of the other St."Ctors.
Alphanumeric Codes In order to communicate. you need not only numbe".. but also kitcrs and other symbols. In the strictest sense. alphanumeric Cool.OS arc codes that represcnt numbers and alphabetic characters (lctters). Most such codcs. however, also represcnl othcr charactcrs such as symbols and v
ASCII
to detect when ~ key has bei'!n preswd i1nd relei1sed. A uniq ue Kdn code is produced by computer software representing that pi1rOCuli1r key. The scan code is then converted to an i1lphanumeric code (ASOI) for use by the computer.
i
ASCII is Ihe abbreviation for American Standard Code for Infonnlltion Interchange. Pronounced "askce." ASCII is a universally accepted alphan umeric code uSt.'Cl in most computers and otherclectronic l'quipment. Most computer kcyboanls are standardized with the ASCII . When you cnter a letter. a nu mber, or control command. the corresponding ASCII code goes into the computer. ASCU has 128 characters and symbols represe nted by a 7-bit binary codc. ACluall}, ASCII can be considered an 8-bit code with the MSB always O. This 8-bil code is 00 through 7F in hexadl.'Cimal. 1llC fi rst thirtY-fwo ASCII characters arc nongnlphic commands thaI arc never printed or d isplaYl.-d and lire used onl y for control purpoSt."S. Examples of thc control characters are "null." "Iine fecd," "start of text." and '·cscape." 1lle other characters arc graphic symbols that can be prinll.-d or displayed and include the lettcrs of [hc alphabet: (Iowerca~ and uppercase). Ihe len decimal digit£. punctuation signs and other commonly used symbols. Table 2-7 is a listing of the ASCII codc showing the dl."Cimal. hexadecimal, and binary representations fnr each character and symbOl. The left St."Ction of Ihe table lists the names of the 32 cont rol characters (OO Ihroug h I F hexadecimal). TIle graphic symbols are listed in the resl of the table (20 through 7F hexadecimal).
TABLE 2-7 American Standard Code (or Information Interchange (ASCII).
NUL
II
I.
2
0000010
,,,
ETX
3
113
UtlUUlOO
'"
32 33
0100000
20
@
64
HlOClI)(1O
40
01()()u()1
21
A
41
34
0100010
B
6f)
III()()()IO
42
#
35
0100011
22 23
"
lOOlOOI
C
4J
..
36 37
0100100
24
D
"
J()I)(lIlll
44
IOOUIOI
45
0100110
"
E
"I,'
1000100
OIOOJOl
U,
r
70
!OlIUI JO
46
Sp.:l<.:C'
01
,
EOT
,
OOO(K)II
[l NQ
S
OOOOlOl
ACK
(,
IKMMl1lO
nEL
, 7
(KIIKl1ll
01
"
39
0100111
27
G
71
leOOI[1
47
OX
40
0101000
2R
H
72
1001000
HT
,
()(XHOO() ()(KlI()()1
0101001
I()O I(1I11
"
10
()(KliOW
•
42
0101010
"2A
73
Lr
74
IOCJ IOIO
4A
vr
II
U(JllIO! I
'" '"nB
41
+
43
OJOIIH I
20
K
F1'
12
tk)OllllO
UC
44
0101100
2C
I.
100 1100
'"
CR
13
()(XliIOI
110
45
0101101
20
M
" "n
1(lIJIUl I
}(lOIIOl
4C 40
SO
14
(1()()II1O
DE
4(,
01011 10
213
N
78
1001110
4.
Sf
15
OOIllII I
OF
(
47
0101111
4F
](,
OUIOOOO
IU
o
30
p
OJ
10 1(00)
DCI
17
I)(JI(UJI
II
"
0110000
"
100 1111
DLE
'"
o
31
Q
81
]()j()(xll
DC2
001(11)[11
12
2
0110010
32
R
52
13
01 10ClI I
n
14
34
NAK
21
IMJllllOl
15
53
0110101
l5
u
SYN
22
lMtlllll 1l
16
,
"
0110100
S T
WHlIlll
01/](1100
,
51
"' ""
1010010
I)()IIIOI )
DC'
" " 20
"so
{)1100u1
54
0110 110
36
ETB
23
oolOl! I
17
7
55
0110111
J7
v w
""87
CAN
24
tk)lmll) 0011(0)
57
UlllOUI
"
26
I)()I 11110
IA
58
0111010
" "
!O ll cm
25
"
011 1000
EM SUB
"
R
ESC
2J
111111011
IB
59
01110 11
3B
rs
"
OOIII1)()
Ie
60
0111100
3C
2" 111
()(1l1101
10
61
O[ 1110 1
3D
00111 ]0
IE
62
0[[1110
31
()(JIIIII
3'
IF
63
0111111
3F
•S
DC3
GS RS
US ~
01 KlI )000 O::)(xXlIll
STX
SOH
US
'.
19
&
3
5
, < >
,
3A
x y
z
"'
"'
,
d
,
,•
II()IUII)
~I
97
lJ(U)()1
61
" "
1HUlj()
62
I I(lCIIII {
1111)
1100100
'"
IOJ
II(M)lOI
()5
IU2
IIUOllU
,~
r,7
IOJ
lICl)I! I
104
11n)(IIMI
105
I ICIJ(II)I
,~
'"
'"
1101011
l>8
lOS
I tnl 100
6C
">J
1101101
on
IIU
1101110
6E
o
III
1101 111
6F
so
r
70
q
112 113
IIWOOO
51
1110001
71
"' 115
111I1Il1O
72
53
1110011
73
1Il 10loo
54
11111100
74
!OHlIOI
55
,
11 (;
117
IllUlOI
75
JOIUIIO
56
I" 119
76
57
"
1110110
)(l IOII I
1110111
77
IU) 1110
SE
"
1011111
SF
'"
,
%
IIOWIO
101lOCll
92
,
49
" " " 'Xl
,
JUIIOIO 1011011
59
5A SB
k
m
"
w
,
y
,
".
107
120
II I 1000
121
II] 100 I
6A
"
79
122
1111010
7A
12J
11111I1 I
1.
lUI 1100
5C
124
11111I1Il
7C
10111 01
SO
125 IU,
11111n1
7n
111111U
7G
127
1111111
7F
Dol
92
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
i
EXAMPLE 2-38
Determine Ihe binary ASCII codes that are cntered from the computer's keyboard when the fol lowing BASIC program statement is typed in. Also express each code in hl'xadccimal.
20 PR INT "A=";X
Soluticn
The ASCII code for eaeh symbol is found in Table 2- 7. Symbol
Hinary
Hcxadlocimal
2
0110010
32 16
()
01
[(XXX)
30 16
Space
01 ()()()()()
20 16
P
1010000
50 16
R
1010010
52 16
100 100 1
49'6
N
100 111 0
4E I6
T
1010100
Space
0100000
54 " 20 16
0100010
22)6
100000 1
4 1'6
011 11 0 1
3DI 6
Ol oooiO
22 16
01 11011
38 16
10 11 000
58 16
A
X
Related P'oblem
Dclcl'mine the sl"qllcncc of ASCII codes rcquirl'(] for the following program statemcm and express them in hexlldc<:imai: 80 lNPUTY
The ASCII Control Ola,aden The first thilly-two codes in the ASCII lable (Table 2-7) represent the control characters. These arc used to allow devices such a<; a computer and printer to coml11UniCllle with each other when passing information and data. Table 2- 8 lists the comrol characters and the control key function that allows them to be entered di rectly from an ASCII keyboard by prl"Ssing the contro l key (CTRL) und the corresponding symbol. A brief description of each contro l character is also given.
Extended ASCII Characters In addition tothe 128 standard ASCII characters, there arc an additional 128 characters that were adnp\(.'(] by lAM for use in thei r PCs (personal computers). Because of the popularity of the PC, these particular extended ASCII characters arc also used in applicalions other than PCs und have tx.ocome essentially an unofficial standard. The extended ASCII cimf3Clers arc representc..'(] by an 8-bit code series from hexadecimal 80 to hexadecimal FE
DIGITAL CODES
... TABLE 2 - '
NAME
DECIMAL
HEX
KEY
NUL SOH
0
CrRL@
null character
CrRLA
stan of header
STX
CTRLB
stan of text
BEL
2 3 4 5 6 7
00 01 02
BS
8
ETX Ear ENQ
ACK
I-IT
I
•
DESCRIPTION
03 04 05
erRLC CTRLO
end of text
CTRLE
enquire
06
CfRLF
acknowlc
07
CTRLO
boll
08
CTRL I-I
backspace
09
erRL I
horizolllallab
CfRL J
line feed
CTRLK
vertical tab
LF
10
VT
II
OA OB
end of trnnsmission
FF
12
DC
CTRLL
fonn feed (new page)
CR
13
CTRLM
carri
SO
14
CTRLN
shift out
51
IS
OD OE OF
erRLO
shift in
OLE
16
10
CTRLP
data link c.'iC
DCI
17
II
CTRLQ
device control I
DC2 DC3 DC4
IS 19 20 21 22 23 24 25 26 27 28
12
CTRLR
device control 2
13 14
CTRLS
device control 3
CTRL T
devicc control 4
IS
CTRLU
negativc acknowledge
16
enu.v
sYllchronize
NA" SYN
ETB CAN EM SUB ESC FS GS RS US
17
CTRLW
end of transmission block
CrRLX
(;[l1l\:C1
2.
IR I. IA IB IC ID
30 31
CTRLY
end of medium
crnLZ
substitute
CTRL!
escape
eTRU
file separator
CTRLI
group separator
IE
CfRL"
record separator
IF
CTRL
unit separator
The extended ASCII contains ch;mlclcrs in the following general categories: 1. Foreign (non-English) alphabet ic characters
2. Foreign currency symbols 3. Greek letters
4. Mathematical symbols 5. Drawing characters 6. Bar gmphing characters 7. Shading characters
Table 2-9 is a list of the extended ASCn character set with the decimal and hexadecimal representations.
ASCII control ch"r"cten.
•
93
94
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
TABL E 2 - 9
Extended ASCI I char.>ct.e...
SYMBOL
DEC
HEX
SYMBOL
DEC
HEX
SYMBOL
DEC
HEX
SYMBOL
DEC
HEX
c;:
128
80
160
AO
l
192
LV
EO
129
RI
16 1
AI
193
"p
224
, • • ,• ,, ,
•
225
EI
no
82
6
162
A2
194
r
226
E2
13 1
8'
(,
163
A'
E3
IN
164
A4
195 196
227
132
228
E4
il
,
A
A E
o o ; b
o
,
£ ¥ P,
f
165
A5
-+-
197
CI C2 C3 C4 C5
100
A6
198
C6
167
A7
f II
199
D
''''
A8 A9
200
Ol
169
201
C9
"> e
170 17 1
202 203
CA
n
AO
BC
172
AC
'"'
8D
173
AD
142
8E
174
AE
143
8F
175
90
176
145
" '''' 9293
m
147
178 179
148
94
ISO
149
95
lSI
150 15 1 152 153 154 155 156 157 158 159
96
1S2
97 98
183 184 185
"'
88
216
B9
217
"6
BA
2 18
DA
187 IRR
BB
I
219
DB
•
220
oc
1S9
221
DO DE OF
133
85
134
86
135 137
87 88 89
'" 139
80
140
136
144
• N •
, Q
SA
99 9A
•
II II
9B
9C 90
AA
I~
CB
,
,
E5
130
E6
23 1 232
E7
233 234
235
E8 £9
FA EO
237
EC ED
238
EE
239
EF
240
H)
2(W
CC
205 206
CD CE
AF
W7
CF
00 01
208
DO
209
DI
24 1
FI
82
210
D2
242
>'2
2 11
D3
212
04
243 244
F4
05
213
D5
245
F5
B6
21 4
06 07 08 09
246
F6
8'84
BC
9E
190
OD BE
9F
191
UF
I!!I!!I!II!~. -
,
IT
229
21 5
I I
•
222 223
236
••
n
F3
247
>"7
248
F8
249
F9
250
FA FB
j
251
"
252
K
253
•
254
FD FE
o
255
FF
--1. Convert the following binary numberi to the Gray code: (. ) 1100
(b) 1010
(0) 11010
2. Convert the following Gray codes to binary: (.) 1000
(b) 1010
(0) 11101
3. What ii the ASCI I representation for each of the following charade ..7 Express each as a bit pattern and in hex.xledmal notation. (b) , (. ) K (0) $ (d) +
ERROR DETECTION AND CORRECTION CODES
2-12
•
95
ERROR DETECTION AND CORRECTION CODES
I.n this sr.:ction, two methods for adding bits to eodes to either dett.'C t a single-bit error or detect and correct a s inglt.... bit error are discus${.·d. The parity method of CITOr detection is introduct.-d. and the Hamm ing method of s ingle-errordctcction and cOITL>ctian is covered. Whcn a bit in a given code word is found to be in elTOr, it can be carrL>cted by simply invel1ing it. After completing this Sl."Ction, you should be able to • Determine if there is an elTor in a code based on the parity bit . Assig n the proper parity bit to a code . Usc the Hamming code far single-error detection and correction . Assign the proper parity bi t~ for single-error colTt..'Ction
Parity Method for Error Detection Many systems use a parity bit as a means for bit error detection. Any groop of bi ts contain either an even or an odd number of Is. A parity bi t is attachl-d to a grou p of bits to make the total number of Is in a group always even o r always odd. An even parity bit makes the total number of Is eyen, and an odd parity bil makL-'S the total odd. A given systcm o pcratL"S wit h even or odd pa,·ity, but not both. For instance, if a system OpenlleS with even parity, a check is made on each group of bits n.'Cei VL-d to make sure the tolal numbcraf I s in that group is even. !fthere is an odd numbcr of Is, an elTOr ilas occurred. As an iJi ustmlion of how parity bits arc attachL'
.... TABL E Z - U )
EVEN PARITY P BCD
0 [
0
oroo root
ODD PARITY P BCD
oroo 0
roo t
0010 0011
0
0[00
0
0010 0011 0[00
0
0101
0
0 11 0 0111
[
lroo
0
[OO[
The BCD <:odc with parity bits.
1
0101
0110
0 0
0111
1()()() [OO[
The parity bit can be attachL.rJ 10 lhe code at either the beginning or the end, dq)Cnding on system dL"Sign. Notice that the tOlal number of Is, includi ng the parity bit, is always even forc"e ll parity and always odd for odd parity.
Detecting an Error A p:lrity bit provides for the delL'Clion of a s ingle bit elTOr (or any odd numbe r of errors. whi<:h is very unlikely) but cannot cht."Ck for two errors in one group. For instanL"C, lei 's assume thai we wish 10 transmit the BCD code 0 101. (Pari ty can be used with
A parity bit tell! if the numbe r o( 15 is odd or L"ocn.
'16
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
any number of bits; we arc using four for illustration.) The total code transmiued. including the even parity bit, is Even purity bit
.l 00 101
L
BCD code
Now Ict's assume that an error occurs in lhe third bit from the left (the 1 becomes a 0). l~~- E\en
purity bit
0000 1
L
Bit crrror
When this code is received. the pari ty check circuitry determincs that there is only a single I (odd number), when there should be an even num ber of Is. Becaure an even numhcr o f I s docs not appear in the code whcn it is received. an error is indicated. A n odd parity bit also provides in a similar manner for the detl.:etion of a single error in a given group ofbil s.
Assign the proper even purity bil la Ihe followi ng code groups:
Solution
Related Problem
I
(a) 1010
(b) 111 000
(d) 1000 1I lOOI()()1
(c) 10110 101111 1
Make the parity bit eilher I or 0 as neccssary parity bit will be Ihe len-most bit (color). (a) 0 1010
(b) 111 1000
(d) 0 100011 100 101
(c) 1 1011010111 11
(c) 10 11 01
10
mOlke the LOtal number of Is even. 1lle (c) 0 101101
Add an even parity bit to the 7-bit ASCn code for the letter K.
EXAMPLE 2-40 An odd parity system receives Ihe following code groups: 10 110, 11010, 11 00 11, 110101110 100, and 11 00010 1010 10. Dctennine which groups, if any, arc in error. Solution
Since odd plirity is rtXJuired. liny group with an even number of Is is incorrect. The following groups arc in error: 110011 and 1100010101010.
Related Problem
TIle following Ascrr characler is received by an odd pHrity system: 001 10 111. Is it correct?
The Hamming Error Correction Code As you have seen, a si ngle parity bit allows forthe detection of single-bit errors in a code .....,ord. A single parity bit can indicate that there is an error in a certai n group of bits. I.n order tocorrect a detected error, more infomlation is required because the position of the bil in error must be identified before it can be com."Cted. More than one parity bit must be included in a group of bits to be able to correct a dctectederrof. In a 7-bit code. there are seven possible single-bit errors. In this case, three parity bits can not only detect an error but can specify thc position of the bit in crror. 'The Halmning code provides for single-error correction. TIle following coverage illustrates the construction of a 7-bit Hamming code for single-error correction.
ERROR DETECTION AND CORRECTI ON CODES
lfthe number of data bits is designated d, then the number of par~ ity bits, p, is dctcrmincd by thc following relationship:
Number of Parity Bits
&juation 2- 1
2P ?:.d+p+ 1 For example, if we have four data bitS, then p is found by trial and error with Equation 2- 1. Let p = 2. Thcn
'l!'= 22 =4
'""
d+p+l = 4 + 2 + 1 = 7
Since 21' must be equal to or greater than d + P + I, the relationship in ...::quation 2- 1 is 1101 satisfied. We have to try again. Let IJ = 3. T hen
2" = 2] = 8 and
d+p + I = 4 + 3 + 1 = 8 This value of p satisfies the relationship of Equation 2- 1, so three parity bits arc required to provide single-crror l:OlTC{:tion for four data bils. It should be noted here that error detc(.1ion and (.-oITCl1ion arc provided for (If{ bits, both parity and data, in a code group; that is, the parity bits also Chl'Ck themselves. Now that we have found the number of parity bits required in our particular example. we must arrange the bils properly in the code, At this (X)int you should rcal i.....c that in this example the code is mmposcd of the fourdal3 biLS and the thrcc parity bits. 111e Icft-most bit is designated bit /, the next bit is bit 2. and so on as follows: Placement of the Parity Bits in the Code
bi t I,
bit 2,
bit 3,
bit4,
bit 5.
bit 6,
bit7
he parity bi ts arc located in the positions that arc numbered corrcs(X)nding 10 ascending powers of t ~'() ( I, 2. 4, 8, ... ). as indicated: PI.
he symbol
P2 • p~
D I•
P3,
D 2•
D3•
D4
designates a particular parity bit. and Dn designates a particular data bit.
Finally, we must properly assign a I or 0 valuc to each parity bit. Since each parity bit provides a check on cenain other bits in the total code, we must know the value of these others in order to assign the parity bit value. 10 find the bit values, firs t number eaeh bit position in binary. that is, write the binary number for each decimal lX)sition number, as shown in the second t\\'O rows of Table 2- 11. Next, indicate the parity and dala bit locations. as shown in the first row of Table 2- 11. Notice that the binary position number of parity bit P I has a I for its righi-most d igit. This parity bit checks all bil positions. including itself Ihat hllve I .~ ill the same loclltion inllle billllry positioll I!lImher.~. '111crcJo re. parity bit PI checks bit IX);itiom; I, 3. 5. and 7. Assignment of Parity Bit Val ues
TABLE 2 - ' 1
Bit pcnition table for a 7-bit error correction code.
Parity
bit~
(P.)
•
97
98
•
NUMBER SYSTEMS, OPERATIONS. AND CODES
TIle binary position number for parity bit P z has a I for its middle bit. It checks a ll bit positions, includ ing itself, Ihat have Is in this same position. Therefore. parity bit P2 checks bit positions 2. 3, 6, and 7. T he binary position number for parity bit P3 has a 1 for its Icft-most bit. It checks all bit posi tions, including itsclf. that have I s in this same position . Therefore, parity bit P l checks bit positions 4, 5, 6. and 7. In each case, Ihe parity bit is assigned a value to make the quantity of Is in the set of bits that it checks either odd orcvcn, depending on which is specified. The following examples should make this prcx:cdllre clear.
I
EXAMPLE 2 - 41
Determine the Hamming code for the BCD numtx:r 1001 (data bilS), using even parity. Solution
Step 1: Find the number of parity bits req uired. Lei P = 3. Then
2" = 23 =8
d + p + I = 4 + 3+ 1= 8 Three parity bits arc sufficient. Total code bits = 4 Step 2:
+3=
7
Construct a bit position table, as shown in Tablc 2- 12. and enter the data bits. Parity bits arc determined in the following sleps.
• TABLE 2-12
Parity bits
Step 3:
Determine the parity bits as follows : Bit PI checks bit positions 1, 3,5, and 7 and must tx: a 0 for there to tx: an even number of I s (2) in this group. Bit PI checks bit positions 2, 3, 6, and 7 and must be a 0 for there to be an even num ber of Is (2) in this group. Bit p ] checks bit positions 4,5,6, and 7 and must be a I for there to be an even number of I s (2) in this group.
Step 4: These parity bits arc entered in Table 2- 12, and the resulting combined eode isOOl l00 1. Related Problem
Determine the Hamming code for the HCD number 1000 using even parity.
ERROR DETECTI ON A ND CORRECTI ON CODES
I
•
EXAMPLE 2-42 Detcrmine thc Hamming code fo r the data bite; 10 110 using odd parity. Solution
Step 1: Detcn ninc the number of parity bits req uired. In this case thc number of data bits. d, is five. From the previous cxamplc wc know that f1 = 3 will not work. Tryp = 4: 21' = 2" = 16
d + p + I = 5 + 4+ 1
10
Four parity bits are sufficient. Total code bite; = 5 Step 2:
+4 =
9
Construct a bi t position table, Table 2~ 13 , and enter the data bits. Parity bits arc determincd in the following. Sleps. Noticc that P4 is in bit position 8.
TABLE 2-13
BIT DEStGNATlON P, 1 BIT POSITION BINARY POSITION NUMBER , 0001
I
P1 2 0010
D, 3 0011
I'. 4 0100
Dl 5 0101
I
D, 6 0110
I
o
Dllta blls
D4 7 0111
P, 8 1000
D} 9 1001
o
Parity bits
Step 3:
Determine the parity bits as follows: Bit P, ehecks bit positions 1,3,5,7, and 9 and must be l.I I for there to be an odd number of Is (3) in this group. Bi t P2 checks bit positions 2. 3, 6. and 7 and must be a 0 fo r there to be an odd number of Is (3) in this group. Bit PJ checks bit positions 4, 5, 6, and 7 and must be a 1 for there to be an odd number of Is (3) in this group. Bit P4 checks bit posi tions 8 and 9 and must be a I for there to be an odd number of Is ( I) in this group.
Step 4:
Related Problem
These parity bits are entered in the Table 2- 13, and the resulting combined code is 10110111 0.
Determine the Hamming code for 11 00 1 using odd parity.
Detecting and Correcting an Error with the Hamming Code Now that the Hamming method foreonstructing an error-correction code has been covered, how do you use it to locale and correct an error? E..1ch parity bit, along with its corresponding group of bits, must be checked for the proper parity. If there arc three parity bits in a code word, then three parity checks are made. I!" there are four parity bits. four checks must
99
100
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
be made, and so on. Each parity check will yield a good or a bad resu lt. Thc total rcsull of all the parity checks indicates the bit. if any. that is in error. as follows : Step t. Stan with the group checked by PI' Stcll2. Check the group for proper parity. A 0 represents a good pilrity check, and I represents a bad check. Stcll3. Repeat step 2 for each parity group. Stell 4. The binary number formed by the results of all the parity check:-. designates the position of lhe code bit that is in error. This is the er ror posi/ioll code. TIle first parity eheck generates the least significant bit (LSB). If all checks arc good, there is no error.
Assume that the code word in Example 2-4 1 (00 II 00 1) is transmined and that 00 10001 is received. The receiver docs not "know" what was transmitted and must look for proper paril ic.~ to delemline if the code is correct. Designate any en"Qr that has oceurred in transmission ifeven parity is used. Solution
First, make a bit position table, as indicated in Table 2- 14. TABLE 2 - 14
Firsl pori/y check:
Bil P I checks positions L 3, 5, and 7. There arc two [s in this group. P'drity check is good. - - - - - - - - - - -- - - - - - -+, 0 (LSB) Secolld pllrity check:
Bit P2 checks posilions 2. 3. 6. and 7. There arc two Is ill th is group. Parity check is good. - - - - - - - - - - - - - - - - - - - - + > 0 Thinl pfll"ity check:
Bit P l checks positions 4 , 5. 6. and 7. There is one I in this group. Parity check is bad. - - -- - - - - - - - - - - - - - - - - +
1 (MS")
Result: TIle error position code is 100 (binalY fou r). T his says that the bit in position 4 is in error. II is a 0 and should be a I. TIle corrected code is 00 11 00 1, which agrec.<; with the transmitted l:we. ReJ.ated Problem
Repeat the process illustrated in the example if the received code is Oil [(Xl i .
ERROR DETECTION AND CORRECTION CODES
j
•
101
EXAMPLE 2-44
The code 10 1 JOiOlO is received. Correct any errors. There are four parity bilS, and odJ parity is used. Solution
Fi rst. make a bit IXlsitioll table like Table 2-15. TABLE 2 - 15
u
Received code
First po rit)' check: Bit P I checks positions 1,3,5,7, and 9. T here are two Is in this grou p. Purity chcck is bad. - - - - - - - ------------»
I (LS B)
Secmu! jxl/'ity check: Bit 1'2 checks positions 2, 3, 6, and 7. 'n lcre arc tWO Is in this group. Parity check is bad. - - - - - - - - - - - - - - -- ---> Third pMir." check: Bit P J checks positions 4. 5, 6, and 7. There arc two I s in this group. Parity check is bad. - - - -- - - - - - - - -------»
I
F()lIrth parity check: Bit P4 checks positions 8 and 9. There is one 1 in this group. Parity check is good. - - - - - - - ------------» 0 (MSB)
Result: The error position code is 01 11 (binary seven). This says that the bit in position 7 is in error. The corrected eooc is therefore 1011 0 111 0. Related Problem
I
SECTION 2 - 12
REVIEW
111C code 10 1111 00 I is received. Correct any crror if rod parity is used.
1. Which odd-pilrity code is in e rror?
(.) 1011
(b) 1110
«)
(d) 1000
0101
1.. Which even-poulty code is in erro r?
(.) 11 000110
(b) 00101000
«)
10101010
-I (d) 11111011
3. Add an even pilrity bit to the end of each of the followin g codel.
(.) 1010100
(b) 0100000
«)
1110111
(d) 1000110
4. How many pilrity bib are req uired fOf data bib T101 0 using the Hamming code?
5. Create the Hamming code for the data bib 0011 using even parity.
102
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
•
A binary number is a weighted number in which the weight of eac h whole nu mber digi t is a positive power of two and the weight of each fractional digit is a negative power of twO, Thc whole number weightS increllsc from right to left-from least significa nl dig it to moS( significant.
•
A binary number can be converted to a dl!Cimal number by summing the decima l values of the weights of all the I s in the binary number.
•
A decimal whole number can be convertetl to binary by using the sum,of·weights or the repeated division-by·2 method.
•
A decimal fraction can be converted to bi nary by using the sum-of-weights or the repeated multiplication-by-2 mct hod.
•
The basic rules for binary addit ion are as follows:
0+0 = 0 0+ I= I 1+ 0 = 1 I
•
+
1 == 10
The bas ic
rulc~
for binary subtraction are as foll ows:
O ~ O = U
J - I = 0 1- 0= 1 10 - J = I
Os 10 Is.
•
TIte I 's com plement ofa binary number is dt:ri ved by changing Is 10 Os and
•
'Ilie 2's complemcnt of :1 binary number can be derived by addi ng I to the l 's complement.
•
Binary subtraction can be. accomplished with addition by using the I's or 2's complement method.
•
A positive binary nu mber is represented by a 0 sign bit
•
A ncgative binary nu mber is represented by a I sign bit.
•
For arithmetic operations, negalive binary numbers are represenled in I's complemenl or 2's comp lemenl form.
•
In an add ition operation, an overnow i~ po~sib le when both numbers arc positive or when both numbers are negatlvc. An mcorrect sIgn bit in the sum mdicatcs the occurrence 01 an overflow.
•
The hexadecimal number system consists of 16 digits and characters. 0 through 9 followed by A through F.
•
Onc hexadecimal dig it rcprt:sems a 4-bit binary number, and its primary usefulness is in simplifying bit plillems and milking them easier to read.
•
A decimal number can be converted to hexadecimal by the repeated di vision-by- 16 method.
•
The octal number system consists of eight digits. 0 through 7.
•
A decimal nu mber can be converted to octal by using the repeated division-by-8 method.
•
Octal-to-binary conversion is accomplished by sim ply replac ing each octal digit with its 3-bit binary equil'lllent. Thc process is reversed for binary-tO-OCWI conversion.
•
A decimal number is converted to BCD by replacing e-dCh decimal digit with the appropriate 4-bil binary code.
•
The ASCII is a 7-bit alphanumeric code that is widely U5(:<1 in comp!Jter systems for input an d output of infonnat ion.
•
A (h1rity bit is used to detect an crror in a code.
•
'Inc Hamming code provides for Single-error detcction and correct ion.
SELF-TEST •
KEY TERMS
103
Key te rnu and other bold terms in the chapter ;ue defined in the end--of-book glouary. AlplmnUllleric Consisting ofnumernls. leller.;, Hnd other characters.
AScn American Sumdard Code for Information Interchange; the most widely ~I alpha numeric code.
nco Binary coded dt'Cimal; Il di gil
digit~.
0 through 9. is repre-
Byte A group of eight bits. Flooting-poinl number A numbe r representation b
Oclal Describes a number system with H Imse of eight.
Parity In relation to binary codes. the conditioo of evennc~s or oddness of the number of
I .~
in 11 code
group.
Answer! are at the end of the chapter.
1. 2x tOI + 8xllfisequallO (a) 10
(b) 2110
td) 2R
(c) 2.8
2. The binary number I J 0 1 is cquill to the decimal number (a) 13
(b) 49
(c) I I
(d)3
3. TIle binary number 110 11101 ;s eq ual to the dec imil l nu mber (a) 12 1
(b)
22 1
(c) 44 1
(d) 256
4. The decima l number 17 is equal to tbe binary number (a) 10010
(b) 11000
(d I(XXH
(d)O IOO I
5. lbe dec imll l number 175 is cqulli to the binary number (a)IIOO I I I I
(b) 10 1011 10
6. The su m of 11010 (a) 101 001
+ 0 1 J II
(e) 10101 111
(d) I I IO I I II
equals
(b) 1010 10
{el 11010 1
(d) lO HXX>
7. Thedifferenceof ll O - OIOequll ls (a) 001
(b) OIO
(c) 101
(d) 100
8. The I's complemen t of lO l l 100 1 is (a )O HXXHII
(b)0I OOOI 10
(e) 11 000 110
hi) 10101010
(c)OI OO IOOO
(d ) 00 111000
9. The 2'5 complement of 11 00 1000 is (a)OO I JOII I
(b) 001 1000 1
I(). TIle decima l number (a) 0 11 1 10 10
+ 122 is ex pressed ill the 2's com plement form a~
(b) 11 11 1010
{c)OIOOOIOI
(eI ) HXXXl IOI
J 1. The decima l number - 34 is ex pressed in the 2's comple ment fonn as (a) 010 111 10
(b) 10 100010
{cl ll OIiII O
(d)OI OIi IOI
12. A sing le-preci~ion Om:lling-poim biffi!ry nu mber has a lotal of (a) 8 bits
(b)1 6bits
(e) 24 bits
(d) 32 bits
13. In the 2 's complement fonn . the binary num be r 100 1001 I is equal to the decimal number (a) - 19
(b)
+ 109
(e) +9 1
(d) - 109
104
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
14. The bi nary number IOI IUO I I I (X.II OIOIOIXlOI elln be written in oclal as (a) 547 1230e
IS.
'rne
(b) 547124 18
(el 263452 18 (d) 23 1fi2501 s binary number 1000110101000110111 1 can be wrilten in hexadecimal as
(a) AD467 16
(b) 8C46F 16 (e) 8D46F!6 16. The binary number for F7A916 is
(d) AE46F I6
(a) 11110111 1010 100 1
(b) 11 10111110101001
(c) 11 11 111010110001
(d) 111101 JUlOlUlool
17. TIle BCD numberfordecimal473 is (a) 111011010
(e) 01000 11 100 11
(b) 110001110011
(d) 0100 11 11001 1
18. Refer to Table 2-7. The command STOP in ASCII is (a) 101001 11 0 10100 1001111 1010000
(b) 1010010 100 1100100 11 1010 10000
(c) 1001010 1101 10 1100 11 IOIOJ(XX}I
(d) 101001 11010 100 100 1 J 10 1100100
19. The code that has an even-parity error is (a) 10 100 11
PROBLEMS SECTION 2 - 1
(b)
110 1000
(c) 1001000
(d) 1110111
Answer'! to odd-numbered problems are at the end of the book.
Dec::imal Numbers I . What is the wei:,;ht of the digit 6 in each of the fol lowing dec imal numbers? (a) 1386 2.
Expre.~s
(b) 54.692
(e) 671,920
each of the following decimal numbers as a power of ten:
(a) 10
(b) 100
(e) 10.000
Cd) 1,000.000
3. Give the val ue of e.ach di git in the following decimal nu mbers: (a) 47 1
(b) 9356
(el 125,000
4, How high can you count with four decimal digi ts?
SECTION 2 - 2
Binary Numbers S. Coovert tlK' following binary nllmber; 10 decimal: (a) I I
(b) 100
(e) II I
(d) WOO
(e) 1001
(0 11 00
(g) l Ol l
(h) JI ll
6. Convertthc following binary numbers to dl:cimal: (a) 1110 (b) 1010 «(:) 11100 (d) I((XX) (C) 10 101
(0 11 10 1
(g) 10111
(h) 11111
7. Convert each binary numbe r lO decimal: (a) 11 00 11.1 1
(b) 1010 10.0 !
(e) l COJOO 1.l 11
(d) 11 11 000. 101
(e) 1011100. 10 101
(0 11 1000 1.0001
(g) 10 11 01 0. 1010
(h) 111111 1.11 11 1
8. What is the highest decimal number that can be rcprescll too by each o f the following numbers of binary digi ls (bit~r! (a ) two
(b) three
(e) four
(d) fi ve
(e) six
(0 seven
(g) eight
(h) nine
0) ten
(j) cleven
9, How many bilS are required 10 n:prcscm the following decimal numbers? (a) 17
(b) 35
(e) 49
(d) 68
(e) 8 1
(0 11 4
(g) 132
(h) 205
PROBLEMS
•
10. Generate the binary sequence fOJ each decimal sequence:
(a)
o through 7
(b) 8 through 15
(d) 32 through 63
SECTION 2-3
(e) 161hrough31
(e) 64 through 75
Decimal-to-Binary Convenion 11. Con~ert each decimal number 10 binary by using the sum-of-y,-cights method:
(a) 10
(b) 17
(e) 24
(d) 48
(e) 6 1
(I) 93
(g) 125
(h) 186
12. Con\·ert each decimal fmctionto binary using the sum-of. weighl~ method: (a) 0.32
(b) 0.246
(c) 0.098 1
13. Convert each decimal number to bina ry using repeated division by 2:
(a) 15
(b) 2 1
(C) 28
(d) 34
(e) 40
(0 59
(g) 65
(h) 73
14. Convert each decimal fracti on to binary using repeated multiplication by 2: (a) 0.98
SECTION 2 - 4
(b) 0.347
(e) 0.9028
Binary Arithmetic 15. Add the binary numbers:
(a) 11 + 01
(b) 10+ 10
(e) 101 + I I
(d) 11 1 + 110
(e) 100 1 + 10 1
CO
11 0 1 + 1011
16. Use direct subtraction on the following binary numbers: (a) 11 - 1
lb) 10 1 - 100
(e) 110- 101
(d) 1110 - 11
(e) 11 00 - 1001
(0 11 0 10- 10 111
17. Perform the fol lowing binary mul tipliclltions: (a)llxl l
(b) IOO x IO
(e) ll lxlOl
(d) 1001 x 110
(e) 1101 x 1101
(fJ II lOx 11 01
HI. Divide the binary numbc ..~ as indicated: (a) 100 + 10
SECTION 2 - 5
(b) 1001 .,. I I
(e) 1100 + 100
t's and 2's Complements of Binary Numbers 19. Dctennine the l ·s complement of each binary number: (a) 10 1
(b) 110
(e) 1010
(d) 110101 11
(e) 1110101
(f) Drol l
20. Determine the 2·s complement of each binary number using either method:
SECTION 2 - 6
(a) 10
(b) I II
(e) 100 1
(d) 11 01
(e) 11 100
(f) 100 11
(g) 1011 0000
(h) 00111 101
Signed Numbers 21. Express each decimal number in binary as an 8·bit sign-magnitude numOC r: (a) + 29
(b) -85
(e) + 100
(d) - 123
22. Express each decimal number as an 8-bil number in the I 's complement fonn:
(a) - 34
(b) + 57
lC) - 99
(d) + 115
23. Express each decimal number as an 8-bit number in the 2's compiernem form: (a)
+ 12
(h) -68
(e)
+ 101
(d) - 125
24. Determine Ihe decimal value of each signed binary number in the (a) 1001 1001
(b) 0 1110 100
(e) 101 11l 1l
sign -m~gnitude
foon:
105
106
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
25. Detemlinc the decima l mlue of eoch signed binary /lumber in Ihe I's compleillem form :
(a) 100 11 00 1
(h) 01 11 0100
(e) 101 11111
26. Determine the decimal \'alue of eael! signed binwy number in illC 2's complemcnr form: (a) 10011001 (II) 01110100 (e) 10l 11! ! ] 27. Express each of the following sign-magn it ude bina!)' numbers in si ng le-prcc~ion noatingpoint formal:
(b) 10011000001 10Cl0
(a) 0 1I I I 10000 10 1011
28_ Detenninc the \, .. hlL'5 of the follOWi ng single-pn!cision nOilting-poin t numlx;rs: (a) I lOOCOXlI 0100 100 11lOOOI{)(X)(ffiX»
(b) 0 11001100 l000011 11101OCHOOOOOOOO
SECTION 2 - 7
Arithmetic Operations with Signed Numbers 29. Con\'ert eilch pair of deci mal numbel1i to bina ry and add using the 2's complcmcm fonn:
(b) 56
(a) 33 and 15
(c) - 46 .. nd 25
(d) - 110
30_ Pe rfonn each addit ion in the 2's complement rOm):
(a) 000 10 110
+ 00 11 00 11
(b) 01 11000l
+ 10101111
31. Perfoml each ..udition in the 2"s complemL111 foml:
(bl 11011001 + 11100111
(a) 1000 1100 + 0011 1001
32. Perfonn e
(a) 00 11 0011 - 000 10000
(b) 01100 101 - 11101000
33. Multiply 0 1101010 by III IIXX)I in the 2's com plement form. 34. DiviueOlUOOlOU by OOOIIOUI in the 2's complement form .
SECTION 2 - 8
Hexadecimal Numbers 35. Coovert e
(c) A14'6
(f) FB1 7'6
(g) 8A9D'6
36. Com'ert e..ch binary number l]) IlClladecimal :
(a) 1110
(b) 10
(c) 101 11
(d) 1010011 0
(e) 111111 0000
(f) 100 IUXXXXlI 0
37. Convert each hL"Xadec imal number to decima l:
38. Cunvert e
(a) 8
(b) 14
(l~)
(e) 284
(0 2890
(g) 4019
33
(d) 52 (h) 6500
39_ Pcrfonn the following ooditions:
(a) 37,~
+ 29,~
(b) AO , ~
+ 6B'6
40. Perform the following subtmctioos:
(a) 5 1'6 - 40'6
SECTION 2 - 9
(b) CS '6 - 3A'6
Octal Numbers 41. Com'ert each octal number 10 d(:'Cima l: (b) 27~
(c) ~
(g) 163~
(h) 1024,
(e) 1 03~
42_ CoovCrt each decimal number to oct:JI by repeawd division by 8:
(a) 15
(b) 27
(e) 46
(d) 70
(e) 100
(f) 142
(g) 219
(h) 435
PROBLEMS
•
107
43. COOVCr1 each oclal num/:lCr to binary:
(a ,
(b)
13ti
57~
(d) 32 1s
(e) IO l g
(f) 4ti53 x (g) 13271& (h) 45~ 44. Conn." each binary number 10 oClal:
(b) IU
(0) III
SECTION 2 - 10
{e}
.54t\
(i) 1002138 (e) 110 111
(d) JOlUJO
«)
(g) 10 11000 11 001
(h) 10 11 0000011
(f) 10 11110
11 00
ii) 1111 11 10 111 1000
Binary Coded Decimal (BCD) 45. Coover1 each of thc foll owi ng m:<:imal num/:lCrs 10 842 1 BCD: (a) 10 tb) 13 te) [8 (d) 2 1 (e) 25 (0 36 (g) 44 (h) 57 (i) 69 (k) 125 (I) OJ 9'
''''
46. COOVL'I1 each ofthc dL'Cimal numbers in Problc...m 45 10 slr.t ighl binar)'. an d l:o mpme [hc number of bils requ ired with Ihat required for BCD.
47. Coo\"cr1 the following decim:!lnumbers to BCD: ~) I ~
~)128
Win
~) I ~
(e) IRe.
(0 210 (g) 359 (h) 547 (i) 1051 48. COIWCIl each of lhe BCD numbers 10 decimal: (b) 011 0
(e) 1001
(d) 0001 1000
(e) UJUI l lIUI
(f) UUll00 1U
(g) 01000101
(h) 10011000
(i) I(XX)U I I HXX)O
(a) 000 1
49. Coo\"ert each oflhc BCD nUll1 0crs 10 decimal: (a) IIXXXXXXl (b) 001000 [ 10111 (e) 00 11010001 10 (d) OI OOXJ IIX)OO I (e) 0 11 10 10 10100
(f) 1
(g) 100101 1ll OUO
(h) 000 10110 100000 11
(i) IIXlI (()()()(xXl I IOU)
(j) 011 00 1100 1100111
50. Add Ihe following BCD numbers: (a) Olto + 0001 (b) 0101 + 0011 (e) 0111
+ 00 10
(d) 1000
+ txXlI
( e) 000 I J(Xx!
+
000 ](XXlI
(0 01 1QOI(X)
+ 0011(X) 11
(g) 0 I()()(X)OO
+ 01 000 [ I I
(h) [OCOOJOI
+ 000[0011
5 I. Add the following BCD numbers:
(a) 1000 + 01 10 (e) 1001
+
1000
(e) 00100101 + ool tXl III
(b) OJ I I
+ 0101
(d) 100 1 + 0 11 1
(0 OIOJ(XJU I
+ UIOI I OUU
(g) 100 11000 + 100[0 111 (11) 010 1011 ()(XX) 1 + 01 1](lI"()() IOOO 52. Convert cach pair of decim al numbcn; to BCD, and add a~ indic;ltL-d: (a) 4 + 3 (b) 5 + 2 (e) 6 + 4 (d) 17 + I:! (e) 28 + 23 m 65 + 58 (g) 11 3 + 10 1 (h) 195 + 157
SECTION 2-11
Digital Codes 53. In a cert:!in llpplication a4-bil binilry sequence cycles rrom 11 11 to ()(XJ() periodically. -nler\: arc four bit changc~. and bt.'Causc of circuit delays. these chungcs may nOl occur at the same installt. For example. if the LSB chanj!l.."S firs t. the number wi ll appear as 1110 during the trallsition fmrn 11I I to 0000 and ffi:!)' be misinterpreted by [he system. III ustr.tte how Ihe Gr.ty code a\"Oids this problem.
108
•
NUMBER SYSTEMS, OPERATIONS, AND CODES
54. Convcrt c!\ch binary number 10 Only code:
(b) 1001010
(a) 11011
(c) 1111 011 10111 0
55. Convert cach Gray code 10 binary: (c) I 10000 1(XXH (a) 1010 (b) n JO lO
56. Convcrt cOlch of lhc following decimal nu mbers to ASCn . Rcfer to Table 2- 7.
(a) I
(b) 3
lC) 6
(d) 10
(I) 29
(g) 56
(h) 75
(i) [07
(e) [3
57. Dctennine e
(b) 100 101 0
(d) 01000 11
(e) 01 11 110
(e) 0 11110 1 (I) HXX)(HO
58. Decode the following ASC II clxk"
~tOllemen t
to ASCII:
30 TNPlJf A. B
SECTION 2 - 12
Error Detection and Correction Codes 61. Dctennine which uf the foll owing even parity coclcs arc in error: (a) 1001100 10
(b) 0 11101010
(c) 101111 11 010001010
62. Detcnnine which of the following odd parity (a) 111101 10
(b) 00 11000 1
Cllde~
OIre in error:
(e) 010 10101 0 1010 1010
63. AUach the proper ewn pari ty bit to each o f the follcl\\.'jng bytes of da ta: (a) 10 100100
(b) 0000100 1
(c) 11 111110
64. DctemliflC the even-parity Hammi ng cude for the dOlta bits 1 100. 65. Dctenninc the odd-pari ty Hamming code fOf the datil hits IUlOl . 66. Com:ct any error in eilCh of the following Halll ming codes with evcn p<,rily. (a) 11 101 00
(b) 1000 11 1
67. Correct any error ill each of the following Hamming cudes with IxkI parity. (a) I 10HXXlI I
(b) J(XXXlIIOI
SECTION REVIEWS SECTION 2-1
Decimal Numbers 1. (a) 1370: 10
(bl 6725: 100
(e) 7051: I{XJO
(d) 58.72: 0. 1
2. (a ) 5 1 - {5 x lO) + (1 x l) (b) 137 = (\ x l OO)+ (3x lO)+(7x l) (e) 1492 = ( I x 1000) + (4 x 100) + (9 x 10) + (2 x I) (d) 106.58 = (I x 100) + (0 x 10) + (6 x I ) + (5 XO.I) + (8)( 0 .01)
SECTION 2 - 2
Binary Numbers 1.
2~ - 1
= 255
2. Weight is 16. 3. 10111 101.011 = 189.375
ANSWERS
SECTION 2 - 3
=:
10 111
2. (a) 14 = 1110
SECTION 2 - 5
1 09
Decimal-to-Binary Convenion 1. (a) 23
SECTION 2-4
•
(b) 57 == 111 00 1
(e) 45.5
(b) 2 1 = IUIO I
(e) 0.375 = 0.011
=:
10 110 1.1
Binary Arithmetic 1. (a) 11 01 + 1010 = 101 11
(b) 101 I I + 01101 = 100 100
2. (a) 11 01 - 01 00 = 1001
(b) 100 1 - 011 I = 00 10
3. (a) I lO x 111 = 101010
(b)
11 00~OIJ = I OO
1'$ and 2's Complements of Binary Numbers 1. (a) I's comp of 000 1 1010 = 11 IlXlI 01
(b) l 'scompofl l l lOl ll = CXXXl 1000
(e) 1's comp of 10001 101 = 01 11 0010
2. (a) 2's comp of 00010110 = 111010 10
(b) 2'scom pof l l l llloo = OOOCK:llOO
(CJ 2's comp of 100 10001 = 0 110 1111
SECTION 2-6
Signed Numbers 1. Sign· omgn ilude : + 9 = 0000 1001 2. l 's (:omp: - 33 = 110 11 110
3. 2's<:om p: - 46 = 1101 00 10 4. Sign bil, exponcnI. and manlissa
SECTION 2-7
Arithmetic Operations with Signed Numben I. Cases of llddition: posilive number is larger, n,---gu!ive number is Iilrgcr, both are pOl'iti\'c, both are negative 2. 00 100001 + 10 111100 = 1101 1101
3. 0 11 101 II - 00 1100 10 =: 0 1000 10 1 4. Sign of product is pos itive. S. 00100 10 1 x 0111 11 11 = 0 1001 1110 11 6. Sign of quotien t is negati ve. 7. 00 I 10000 ~ 00001100 = (XXXXH 00
SECTION 2 - 8
Hexadecimal Numbers (b) 11 0011101 000 = CEB I6 (b) 3A5 16 = 00 1110100101
1. (a) 101 100 11 = B3'6 2. (a) 57 u• = 0 10 101 I I
(e) F80BI~ = 111 11 0000000 101 1
SECTION 2 - 9
3. 9830]6 = 39,728 1(1 4. 5731(1 = 23D I6 S. la) 18 16 + 34'6 = 4C I6
(b)
3FI~
+ 2AI6 =
6. (a) 75 16 - 21 \f, = 54] ~
(b)
94 1~
-
Octal Numbers I. (a) 73 8 = 59 1(1
(b) 125B = 85 10
2. (a) 98]0 = 142a
(b) 163 10 = 243 8
3. (a) 46s = 1001 JO 4. (a) 11010 1111 = 657~
SECTION 2 - 10
69 16
5C l~ = 38 1~
(b) 7238 = 111010011
(e) 56248 = 10 111 00 10100
(b) 1001100010 = J 1 42~
(e) 10 11111 1001 = 2771 1
Binary Coded Decimal (8CD) I. (a) 0010; 2
(b) lOOl: S
(e) 000 1: J
(d) 0 100: 4
11 0
•
N UMBE R SYSTEMS, OPERAT IONS, AND CODES
(e) 273 10 = 00100 11 10011
2. (a) 6,0 = 01 10
(b) 15 10 '" 000 10 10 1 (d) 849,0 = 10001)1001001
3. (a) lOOOHXl I .... 8910
4. A 4-bit sum
SECTION 2-11
i~ i n\~.llid
~
1571(1
Digital Codes: I. (a) I lOO:! = 1010 GI".IY 2. (a) I
(e) I 101O~ = 101 J I GrdY
(b) 101(l:! "" III I Gl'ay (b) 1010 Gray = 11 00:.
(e) 111 01 Gray = 101 10;.
(b) r: 11100 10 • 72 16
3. (a) K: 10010 11 - ' 4B 1b (e) $; OI()()J()() -.24,6
SECTION 2-12
(e) tXXllOIOIO III
(b) OO I()()J ' 11000 = 278 10 when it is grcmcr tha n 91<1'
(d) +; OIOIOJ I ..... 2B !(>
Error Detection and Correction Codes I. (e) 01U! has;.ln cnor.
2. (d) 1l lll Ol llmsancrror. 3. (a) 10 10 1(}()1
(b) 0 1000(X)1
(e) 1110 1110
(d) 1000 11 01
4. Four pari ty bils 5. 1 0 0 I) 0 I I (pmity hi ls 3rt: red)
RELATED PROBLEMS FOR EXAMPLES 2--1 9 has a value of9
+I=
2-4 10. 11 1 = 2 + 0.5 + 0.25
145
115 ~ 64 + 32 + 16 +8 + 4+ 1 = 1 1 [ 1I 0 1
111 1 + 1 IO:J = 11U 11
2--81 11 - 100 = 011
I JO I x 10 10 = IQCXXXl IO UlOO(XXXJ
2.875
2--9 IIU - 10 1 = 001
2--11 1100 -:- 100 = J I
2-14 SccTllblc2- J6.
+ 0 .125 =
2-639 = JOOIII 2- 12 0011010 1
2--1501 1101 11 =
+
119 10
TABLE 2 _ 16
SIGN-MAGNITUOE
+ 19 - 19
1'S COMP
2'S COMP
[
000100 11
(X)() IO:J I 1
JOU lOOl1
l l lO ll ()()
111 01 10 1
(XX) I ()() I
2- 161110101 1 =- 20 10 2-17 11010 111 = -4 110 2- 18 llCXXX>lOOOIO IOO I1 !XXXXXXXX) 2-19 0 10 10101 2--21 1001000 11 0 2-23
2-20 lXXl l000 1
2--22 (83){ - 59) = - 41197 (1 011001 [0 1111 1 in 2°s comp)
lOO ~15 = 4COlOO)
2-25 01 1010111 10 1O:JI 11
2--26 6BD 16 = 0I1010 1111 01 ~ 2 10 + 29 + 21 + 2s + T + 23 + 2~ + 2° = 1024 + 5 12 + 128 + 32 + 16 + 8 + 4 + I = 1725 111 2-27 6UA 16 = (6)< 256) + COx 16) + ( lOx I) = 15461() 2-28 259 1,0 = A IF16
2-29 4C,(, +
2- 30 BCD1(> - 173'6 = ASA lb 2-31 (a) 00 101 11 = !i 10 = 1 3 ~ (e) 2-32
OO I I~=% IO = I ~
1250762~
3AI ~ = 86 1~
fb) 01010 12 = 2 110 = 25 ti (d)
2-33 l OO10 11 ()() II IOO II
2-35 l00 I1 00IOI IOI()(X)
2-36 10000010
I 111tJ 10 1 U I I~
= 3926 10 =
752~
2-34 82,276'0 2-37 (a) t 1101 1 (Gray)
(b) IIIO I
ANSWERS
•
2-38 The sequence of COOL'S for 80 rNPlITY is 381 630 ,~20 1~4 9' 64E I .,50 1 ~5 16541 620, ,,59' 6
2-39 010010 11
2-40 Yes
2-41 11100CXl
2-420010 10001
2-43 The bit in position 0 10 (2) is in error. Correct to 001 1001 . 2-44 The bit in position 0010 (2) is in Crrol~ CotTCctlo 11 1 [11000.
SElF-TEST 1. (d)
9. (d) 17. (0)
2. (a) LO. (a)
3. (b)
4. (e)
5. (e)
6. (al
7. (d)
8. (b)
II. {el
12. (d)
13. (d)
14. (b)
15. (e)
lb. (a)
HI. (a)
19. (b)
111
I CHAPTER OUTLINE
CHAPTER OBJECTIVES
3- 1 3-2 3-3
The OR Gate
3-'
The NAND G
3-5 3- 6 3-7 3- 8 3-9
The NOR Gate
Descnbe the operation of the i~rter. the AND gate, and the OR g
The Inverter
TheANO Gate •
The Exclusive-OR and Exdusive·NOR Gates ProgramrTlClble
Expreu the operatiOl1 of NOT, AND, OR. NAND, and NOR gat~ with Boolean algebra
•
logic
Fixed-Function logic Troubleshooting
Describe the operation of the NAND gate and the NOR gate
Describe the operation o f the exciulive-QR and excluliveNOR gates
•
Recognize and use both the d iltinctive ~hape logic gate symbol! and the rectai1guli)r outline logic gate symbol! of ANS IIIEEf
Sundard 91- 1984
CoOitruct timing diagraml d-.owing the proper time relatiomhipl of inpub and output! for the varioU! !ogk gates
DilCU!! the balic concepti of programmable logic Make balic comparisons between the major Ie technologiesCMOSandm bplain how the different seriel within the CMOS and m families differ from each other Define propagation delay time,
pclWC' dinipation,
speed-power
product, and fan-cut in relation to logic gam
lilt IpeciflC fIXed-function integrated circuit devK:es that contain the varioul logic gates
VIe each logiC gate in limple applicatiOn! Troobleshoot logk gates for opens and Ihorts by using the oscilloscope
KEY TERMS
INTRODUCTION
The e mpha~is in this chapter is on the operation, application, and troubleshooting of logic gates. The relatiomhip of input and output waveforms of a gate using timing diagrams is thoroughly covered. Logic symbols u~d to repre~nt the logic gates are in accordance with ANSI/IEEE Standard 91-1 984. This standard has been adopted by private industry and the military for u~ in intemal document.1tion as we ll as published literature. Both programmable logic and fixed-function logic are discu!~d in this chapter. Bec
Inverter
fuse
Truth table
Antifuse
FIXED- FUNCTION LOGIC DEVICES
Timing diagram
EPROM
(CMOS AND TTL SERIES)
Boolean algebra
EEPROM
Complement AND gate
74XXOO
74XXOZ
74)(X"04
SRAM
74XX08
74XXlO
74XX 11
Target device
74XX20
74XXZl
Enable
fTAG
74XX30
74XX32
74XXl7 74XX86
OR gate
CMOS
NAND gate
ill
NOR gate
Propagation delay time
Exclusive-OR gate
Fan-out
Exclusive-NOR gate
Unit load
74XX266
~
VISIT Ttll, COMPANIO,," WEBUn:
Study akh for this chapter are available at http://www.prenhall.comlfloyd
AND array
113
114
_
lOGIC GATES
3 -1
THE INVERTER 'Ibe inver1er (NOT cireuil) performs the operation callcd inversinn or cmnplementatinn. 'Ole inverter changes one logic level to the opposite level. In tenus of bits, it changes a I toaOanda Otoa I. After completing this section, you should be able to _ Identify negation and polarity ind icators _ Identiry an inver1er by either its distinctive shape symbol or its rcctangularoutli ne symbol - PrOOuce the trUlh Hlble for an inver1er _ Describe the logical operation of an inver1er
Standard logic symbols for the ill\"erter arc shown in Figure 3- 1. Part (a) shows the disliIlCli1-'e ~'hll,)e symbols, and part (b) shows the recllll1glll ar ott/line symbols, In this text-
book, d istinctive shape symbols are generally used; however. the rectangular outline symbols arc found in many industry publications, and you should hccome ramiliar with them as well . (Logic symbols arc in accordance wilh ANSl!IEEE Standanl9 1-1984.) FIGURE 3- 1 Standan:llogic S)fflboll for the
ioverter (ANSI/ IEEE Std. 91- 1984).
(8) Distinctive shape symbols wit h negation indi<:alors
(b) Rcct:;ngular oultinc: s)'mbol$ with polarit), indi~-alors
The Negation and Polarity Indicators 111e negation indicator is a "bubble" (0 ) thm indicates im'ersion or COIIIIJ/emellf(t/ioll when it appears on the input or output of any logic clement, as slmwn in Figure 3- I(a) ror Ihe inver1er. Generally, inputs arc on Ihe left ora logic symbol and the output ison the right. When apperui ng on the input, the bubble means thaI 11 0 is the active or as.,·erled input state, and the input is callcd an acti ve-LOW input. Whcn appearing on thc OUlpUl, thc bubble me an~ that a 0 is the active or asserted output ~tate . and the output is called an active-LOW output. Thc abscnce of a bubble on Ihe input or outpUi meam that a I is the active or asserted statc. and in this case, the input or output is called act ive-HIGH. The polarity or level indicator is a "triangle" (t::::..) that indicates inversion when it appears on the inpul or output of a logic element, as shown in Figure 3-1(h). When appearing on thc inpul, il means that a LOW level is the active or asserted inpUi statc. When appearing on the output, it means thilt a LOW Ie\'el is the active or asserted output slate. Either indicator (bubble Or triangle) can be used both on d isti nctive shape symbols ruld on rectangular outline symbols. Figure 3- 1(a) indicates the p.ineipai inverter symbols used in Ihis texl. Note that 11 change in the placement of the ncgation or polarity indicator docs not imply a change in the wayan inver1er operates.
TABLE 3 - 1
Inverter truth table.
Inverter Truth Table INPUT
OUTPUT
LOW (0)
HIGH (II
HIG H ( I)
LOW (0)
When a HIGH level is applied 10 an inverter input. a LOW level will appear on its output. When a LOW level is applied 10 its input, a HIGH will appear on its output. This operation is summarized in Table 3-1, which shows Ihe output for each possible input in terms of levels and corresponding bits, A table such as this is called a truth table.
THE INVERTER
•
11 S
Inverter Operation Figure 3-2 shows the output of an inverter for a pulse input, where / , and'2 indicate the corresponding points on thc input and output pulse waveforms. When the input Is LOW, the output is HIGH; when the input is HIGH, the output is LOW, thereb}' producing an i1werted output pulse.
-,
HJ(iH (I)
r
L-J
LO\V (0)
I[
HIGH (I) 10\\ (0)
11
0 mpuTpulsc
InputpulSC FIGUR E 3 - 2
Inverter operation with a pulse input. Open file F03-02 to verify inve rter operation.
Timing Diagrams Recall fro m C h
tnpuT OuTpuT
n, , ~
time
FIGURE 3 - 3
Timing diagram for the case in Figure 3-2.
,,
'[
I
A timing diagram shows how two or more wavero rm~ re late in
'1
EXAMPLE 3-1
A wavefonn is applied to an inverter in Figure 3-4. Determine the IJUtput wavefonn eOTTCsponding 10 the inplll and show the timing diagmm. Acconling to the placement of the bubble, what is the active output state? FIGURE 3 - 4
InpuT
Solution
-C>o---
Output
TIle output wdvcfOnn is exactly opposite to the input (inverted), as shown in Figure 3-5, which is the basic timing diagram. The active or asserted output state is O.
116
•
LOGIC GATES
fiGURE 3 - 5
Input
Out put
Related P,oblem·
' .Jn
o
I
U I
n
L
,,I ,
I
' -1LJH LJr-
0
If the inverter is shown with the negative indicator (huhhle) o n the input instead of the output, how is the liming diagram affected? •Answers arc
logic Expression for an Inverter Boolean algebra use! va riilbles and operators to describe a logic circuit
In Boolcan algcb.·u, which is the mathematics of logic circuits and will be covered thorough ly in Chapler 4, a variable is designated by a letter. The (."Omplcmc nt o f a variable is designated by a bar ovenhe Icller. A variable can take on a value o f e ither I orO. if a given variable is I. its comple me nt is 0 and vice versa. The operation of an inverter (NOr circuit) can be expressed a.~ follows: If the input variable is called A and the output variable i~ called X, then
X=A T his exp rcs.~ i on slates thallhe OUlput is the complement of fhe input,!>O if A = 0, then X = I, and j f A = I, then X = O. Figure 3-6 illustrates this. The complemented variable A can be read as "A bar" or '"not A."
FIGURE 3- 6
The irrvertCf" complemenu an input
A-(:>o- X-A
variable.
An Application Figure 3-7 shows acircllit for producing the I 's co mplemenl oran 8-bit binary number. The bits o f the bi nary number are applied to the inverter inputs and the I's complement of the number arpears o n Ihe outputs.
FIGURE 3 - 7
Example of a I 's complement circuit uling irrverten .
B Ulilr)'
o
numbcr 000
11111111 11
o
11
I' s complement
o
THE AND GATE
jsECTION 3-1 REVIEW
-
117
1. When a 1 is on the input of an inverter, what is the output?
Amwc n are at the e nd of the
2. An active HIGH pulse (HIGH level when asserted, l OW level when not) is required on an inverter input.
chapter.
(a) Draw the approp riate log;€; symbol, using the distinctive shape and the negation indkato r, for the inverter in this applic:ation.
(b) Desnibe the output when a positive-going pu l~ ii applied to tile input of an inverter.
3-2
THE AND GATE
The AI\If) gate is o ne of the basic gates that can be combined to fonn any logic function . An AND gate can have two or more inputs and performs what is known as logical multiplication . Afte r completing this section. you should be able to _ Identify an AI\If) gale by its d istinctive shape symbol or by its rectangular outline symbol - Describe the operation of an AND gate _ Ge nerate the truth table for an AI\!' O gate with any number of inputs _ Produce a timing diagmm for an A N D gate with any specified input waveforms _ Write the logic expression for an AND gate with any number o f inputs - Discuss examples o f AND gale ap plications
The term gate is used to describe a circuit that performs a basic logic operation. The AND gate is composed of two or more inputs and a single output, as indicated by the standard logic symbolS shown in Figure 3-8. Inputs are o n the left , anti the output is on the ris ht in each symbol. Gates with two inputs are shown; however. an AND gate can have any number of inputs greater than olle. Allhough examples of both distinctive shape symbols and rectangular oulline symbols are shown, the distinctive shape symbol. shown in part (a). is used predominantly in this book.
in a computer, with the exception of certain ~ of memory, are implemented INith
A
--f&l
B~
(a) Disti ncti, ·c
~hape
x
(b) Rectangular outl ine wi th the AN D (& ) qualifying symbol
log;c gatc1 used
o n a ~ry large Ka le. FOI example, a micro prOCCiSOf, which is the main part of a computer, is made up of hundrem of thousands o r even milliom of logic gates.
fiGUR E 3-8
St and.l rd logic symboli for the AND gate showing two inputs (ANSIIIEEE Std. 91 - 19811.
Operation of an AND Gate An AND gale produces a HIGH o utput only when all of the in puts are HIGH. When any of the inputs is LOW. the output is LOW. Therefore, the ba.<.;ic pwpose of an AND gate is to detennine when cenain conditions are sim ultaneously true. as indicated by HIGH levels o n
all of ils inputs. and 10 produce a HIGH on its output to indicate that all these conditions are true. The inputs of the 2-input AND gale in Figure 3-8 are labeled J\ and B. and the output is labeled X. The gate operation can be Stilted as follows: t'or a 2-inp ut AND gutc. outpu t X is HIGH only when inputs A a nd 8 are HIGH; X is LOW when either A or B is LOW, or when both A a nd 8 an! WW.
An AND gate can have more than two inputs.
118
•
LOGIC GATES
Figure 3-9 iIIustmtes a 2-inpul i\!\!TI gate wi t.h all four possibi liTies or' input combinations and the resulting output for each.
0W lOJ 1. = D - LOW \0) LOW (0)
I "GII ( I )
I IIGI , ( I)-----r--\_ LOw (0) ~ 1.0\\ (0)
HIGH (I) = D HIGH ( I ) IIIGII (I)
LOW {U) = D -
. LOW {O)
FI GURE 3-9
NI possible logic 'eve'! for a 2-inputAND gate. Open file F03-09 to verify AND gate operation.
AND Gate Truth Table For a n AND gate, aU HIGH inputs make a HIG H output.
'1l1C logical uperation of a gate Cim be expressed wi lh a truth table that liSis all input combinat ions with the corresponding outputs, as illustrated in Table 3- 2 for a 2-inpul AND gate. The truth table can be expanded to any number of inputs. Although the tenns HIGH and LOW tend to give a "physical"' sense to the input and output states, the truth table is shown with Is and Os; a I·UGH is equivalent to a I and a LOW is equivalent to a 0 in positive logic. For any AND gate, regardless of the number of inpms, the output is HIGH Oll/Y when all inputs are HIGH.
TABLE 3-2
Truth table for a 2-inputAND gate.
INpun
OUTPUT
A
B
X
o
o
o o
o
0
o
1 = HIGH. 0 = I£1W
The 10tal number of possible combinatiolls of binary inputs to a gate is determined by the following formu la: Equation 3-1
where N is the number of possible input combinations and ables. To illustrate. For two input variables:
II
is the number of inplI! vari-
N = 22 = 4 combinations
For three input variables: N = 2) = 8 combinations for four illptlt variables:
N = 24 = 16 Combinations
You can determine the number of input bit combi nations for gntes with any number of inputs by using Eqllation 3- 1.
THE AND GATE
.
119
I
EXAMPLE 3-2
(a) Develop the tnlth table for a 3- input AND
~ate.
(b) Delennine the total numrer of possible input combinations for a 4-input AND gate. Solution
(a) There are eight possible input combi nations (2 3 = 8) for a 3-input AND gate. The input side of the truth table (rable 3- 3.1 shows all eight combinations of three bits. The output side is all Os except when all three input bits arc Is. TABLE 3 - 3
A
INPUTS 8
o o o
o o
o
I
o
C
OUTPUT X
o
o o
o
o o
o
o o
o
o
o
(b) N = 24 = 16. "Illere are 16 possible combinations of input bits for a 4-input ANDgatc. Related Problem
Develop the truth table for a 4-input A ND gate.
Operation with Waveform Inputs In most applications, thc inputs to a gate arc not stationary levels but arc voltage waveforms that change frequen tly between H IGH and LOW logic levels. Now let's look at the operalion of Al\'O gates wi t.h pu lsc wavefonn inputs, keeping in mind that an AND gate obeys the tmth tablc operation regardless of whcther ils inputs are constant levels or levels tha! change back and fonh . Let's examine the waveform operation of an A ND gate by looking at the inputs with respect to each other in order todctemlinc the output level at any given time. In Figure 3-10, inputs II and 8 arc both BlGII (1) during the time interval. 'I, making output X HIGH ( I) during this illlerval. During time intcrval input A is LOW (0) and input 11 is HIGH ( 1),
'2.
r-;-l~ t :I t o :I !
A~
' J ,
8
I I I
I
I
i
, : I I I
i
,: 1 I 1
'
i' I I
:
:
I I I
I I I
u ~ () \
4-7I '5 -:I
>-' I - - 'i - : - / 3- : - 1 I I I
, I
x
, I
I
()
()
,r :
FIGURE 3-10
A--r___ B-
-L_/
x
Example of AND gate ope ration with a timing diagram J~lOwing input and output Idillionlhips.
120
•
lOGIC GATES
so the output is LOW (0). During time interval 13' both inputs are HIGH (i )again, and therefore the output is HIGH (J). During lime interval ' 4' input A is HIGH (1) and input B is LOW (0), resulting in a LOW (0) output. Finally, during time interval /so input A is LOW (0), input B is LOW (0), and the out put is therefore LOW (0). As you know, a diagram of input and output waveforms showing time relationship!; is cal1ed a timillg diagram.
I
EXAMPLE] ]
If two wavcfonns, A and B, are applied to the AI\IJ) gale inputs as in Figure 3- 11 , what is the resulti ng output wavefoml?
A
HIG H
LOW
8
HIGH LOW
X
HIG H LOW
A
• ~
~
~
x
~
AlIOd B ~rc bUlh HIGtl durio!,: lhl.~ fuur [illte inter- ab . TIlCrcf'MC X i, HIGH .
FIGURE 3 - 1'
Solution Related P,obwm
·Ine output wavefoml X is HIGH only when both A and B waveforms arc HIGH a!; shown in the timing diagmm in Figure 3-11. Determine the output wavefoml and show a liming diagram if the second and fou rth pulses in waveform A of Figure 3- 11 are replaced by LOW levels.
Remember, when analyzing the waveform operation of logic gates, it is important (0 pay careful attemion to the time relationships of all the inputs with respeci to each {)lheralld to the output.
For the two input waveforms, A and B, in Figure 3- 12, show the output wavcfoml with ils proper relation \0 the inpl1ls.
Inputs
A HIGH LOW 8 HIGH
LOW
OUI!>'.II
FIGURE J - 12
X
HIGH LOW
r--r---l
--i
:
1
1
fIl
Tl----i----f'J I I I
1 1
r---:l
r------1 : :----i
1
I
i
I
I
I I
1-'--I
"
I
: i-
[II
I
I
I
1 I
I
~
I
I
I
I
I
I
I
I
I
I
I
I
1
I
I
I
I
I
I
I
I
,
,
"
I
x
THE AND GATE
Solution
Related Problem
I
•
121
Tile output waveform is HIGII on ly wilen both of the input waveforms are HIGH as shown in the timing diagram. Show the output wavefonn if the B input 10 the ANI) gate in Figure 3-1 2 is always HIGH.
EXAMPLE 3 - 5
For the 3-input AND gate in Figure 3- 13. determine the output waveform in relation to the inputs.
A~ ,
,
,
,
,
,
"
"
I
I
I
I
I
I
,
"
"
I
I I
I-+H : : I-+H : : 1-++-1
B--1
j : , I ,
C
Ll.lJ :: Li.lJ : j
L
" 1
I I I
I I
" I I
I I
" "
A -,-----.., H
C--L'-/
1-r1'1111:rh--W+f-++', I
I
I
x-Lfl
,
n
~-'-'-'~
.&. FIGURE 3 - 13
Solution
Related Problem
The output wavefonn X of the 3-input AND gale is IUGH only when all three input wavefonns A, B, and C are HIGH. What is the output waveform of the AI\'D gale in Fig ure 3- 13 if the Cinpm is always HIGH?
logic Expressions for an AND Gate The logical At-.'D function of two variables is represented mathematically either by placing a dot bet ween the two variables, as A . 8, or by simply writing the adjacent lellers wil hout the dot, as AB. We wi ll normally use the laller nO\;llion because it is ca'iier \0 write. Boolean muUipliculion follows the same basic rules governing binary multiplication. which were discussed in Chapter 2 and are a'i follows:
0-0
~
0
0· 1 = 0 '-0 = 0 I-I = I
Boole·.tn multiplication is the same as the AND funclio n. The operation of a 2-i npl1t AND gate can be expressed in equation form as follows: If one input variable is A. the other input variable is B. and the output variable is X. then the Boolean expression is
X = AB
I~:;;~;:~:::o;p;':ratioOi
i~
when it nC(;esJ.ary to selectively manipulate certain bib in one or more bytes of da ta. Selective bit manipulatiOn! arc done with a mtuk. for example, to clear (make all O!.) the richt fou r bib in a data byte but keep the left four bib, ANDing the data byte with 1111 0000 will do the job. Notice that any bit ANDcd with zero will be 0 and any bit ANCed with 1 will rema in the QffiC . If 101010 10 is AN{)cd with the malk 11110000. the resu lt is 10100000.
122
•
l OGIC GATES
Figure 3- 14(a) shows the AND gale logic symbol with Iwo input variable indicated.
:=O(.)
X o< A1J
variab l ~
and the OUtput
A
2 ~ X "," A8CD
~ ~ X "' A1JC
f)
(, )
(b)
fiGURE 3-14
Boolean expressions for AN D gaw with two, tnree, and foul inpub.
When vClriClbles Clre shown together like ABC, they Clre ANDed.
To extend Ihe AI\I{) expressiOil lo more than Iwo input variables, simply use a new leiter for each input variable. The function of a 3-input AND gate, for example, can be expressed as X = ABC, where A, B, and Care the input variables. The expression for a 4-input AND gate can he X = ABCD, and so on. Parts (b) and (c) of Figure 3--14 show AND gales wilh three and foor inpuI variables, respectively. You can evaluate an AND gate operation by using the Boolean expressions for the outpul. For example, each variable on the inputs can be either a I or a 0; so for the 2input AND gate. make substitutions in the equation for the output, X = AB, as shown in Table 3-4. "111i s evaluation shows that Ihc outpul X of an AI\I{) gate is a I (H IGH) o nly when both inputs are Is (HIGHs). A similar analysis can be made for any number of input variables.
TABLE 3 - 4
A
B
AB "" X
o
o
0·0 = 0
o
O· I = 0
o
·0 = 0 I·J= I
Applications The AND Gate as a ' l Enable/Inhibit Device A common application of the AND gate is to enable (that is, to allow) the passage of a signal (pulse wavefonn) from one point 10 anolher at certain ti mes and to inhi bi t (prevent) the passage at other times. A simple example of this panicular use of an AND gate is shown in Figure 3- 15, where the AND gate controls the pa.<;Sl.lge of a signa l (waveform A) to a digital counter. The purpo~e of this circuit is to measure the freque ncy of wave formA. The enable pulse has a width ofprcciscly I s. When the enable pulse is HIGH. wavcformA pa<;ses thmugh the gate to the counter; and when the enable pulse is LOW, Ihe signal is prevented from passing Ihrough the gate (inhibited). During the I second (I s) interval of the enable pul se, pulses in wavefoml 1\ pa.ss lhrough the AND gate to the counter. The number of pulses passing through duri ng the I s interval is equal to the frequency of waveform A. For example, Figure 3-15 shows six pu lses in one second, which is a fn:quency of 6 J·k If 1000 pulses pass through the gate in the I s interval of the enable pul se. there are 1000 pu lses/s. or a frequency of 1000 Hz. The counter counts the number of pulses per second and produces a binary output that goes to a decoding and d isplay circuit to produce a readout of the frequency. The enable
THE AND GATE
A
=D~
Enahl"
R=,
C{Xllltcr
m~m _::1--;----'
Register, decoder.
between enable pvlscs. frcq"cllCy display
FIGURE 3-1 5
An AND g<'Ite performing an ena blefinhibit function for a frequcncy counter.
pu lse repeats at certain intervals and a new updated COlin! is made so !h
HIGH = On LOW = Off
Ign"ion A s" il ch
H[GH = Uobuckled
LOW = Bucklt.od
S""I 8 bell
C
Audibk: alarm circuit
)-L-
HI GH ncli\"~ ~I;\ml.
'!illlcr
'"
~
Ignilioo on = I [I(i l l fnr JU, FIGURE 3-16 A 5implc Icat belt alarm circuit Uling an AND gate.
i
SECTION 3 - 2
REVIEW
1. When i! the output of an AND gate HIGH? 2. When i! the output of an AND gate l OW? 3. DeKribe the truth table for a 5-inputAN D gate.
•
'23
124
-
3-3
lOGIC GATES
THE OR GATE The OR gate is another of the basic gates from which all logic funct ions are constructed. An OR gate can have two or more inpLLl.. and perfonn s what is known as logical addition. After completing this section. you should be able to _ Identify an OR gate by its distinctive shape symbol or by ils recta ngu lar outline symbol _ Describe the opemtion o f an OR gate _ Generate the truth table for an OR gate with any number of inpuls _ Proollce a timing diagram for an OR gate with any specified inpul waveforms _ W rite the logic expression for an OR gate with any number of inputs _ Discuss examples of OR gale applications
An OR gate Qn have m ore t hom two inputs.
An OR gate has two or more in puts and one output. as indicated by the standard logic symbols in Figure 3- 17. where OR gales with Iwo inputs are illus trated. An OR gate can have any numbe r of inputs greater than o ne. A lthough both diStincti ve shape and rectangu lar out line symbols are shown. the distinct ive shape OR ga te symbol is used in this textbook.
FIGUR E 3 - 17
AH~X ~
Sta ndard logiCsymboll for t he OR gate showing two inputs (ANSI/IEEE Std. 91- 1984).
(a)
Distinctive shape
(b) Rectangular outline wi th the OR ~ J) qUBlifY;11l Synlixlt
Operation of an OR Gate An OR gate produces a HIG H on the oUlput when (my or the inputs is HIGH. The output is LOW only when all of the inputs are LOW. Therefore, an OR gate determines when one or more of its inputs are H IG H and proollces a HIGH on its output to indicate this condition. llle inputs of the 2-input OR gate in FiguI'C 3- 17 arc labeled A and B. and the output is labeled X. The operation of the gale can be stated as follows :
For 11 2-input OR gHte, output X is HIGH when either input A or input B is HU;n, or when hoth A and B arc HIGH; X i<; LOW only when both A and B arc LOW. The H IGH level is tht: ilctive or a<;scrtcd output level for the OR gate. Figure 3-18 illtlstr.lleS the operdtion for a 2-inpul OR gate for all four possible input combinations.
LOW (O) = D LOW U LOW (0) ( )
HIGH ( I ) = D LOW (0)
tUGH
(1)
LOW ( O ) = D HIGH I tI1 GH (1) ( )
III GH (I) = D HIGH (1) HtGH { t ) - -
.. FIGURE 3 - 1'
AUpossible logic levels fur a 2-input OR gate. Open file F03-18 to verify OR gate operation.
THE OR GATE
•
OR Gate Truth Table 'nle operation of a 2-inpul on gate is described in Table 3- 5. l bis trul h table can be expanded for any number of inputs; but regardless of the number of inputs. the output is HIGH when one or more of the inputs are HIGH.
TABLE 3 - 5
INPUTS A B
o
OUTPuT X
o
Truth tablc for a 2-inputOR gatc.
o
o o 1 "' H1GH,O "' lOW
Operation with Waveform Inputs Now let's look nI the opcr.ltion of an OR gate with pu lse waveform inpuls, keeping in mind its logical opcr.tt ion. Agai n, the important thing in Ihe analysis of gale operation with pulse wavcfomlS is the time relationship of all the wavefonns involved. For example, in Figure 3- 19, inputs A and B are both H IGH (I ) duri ng lime interval f l ' making oulpul X HIGH (I ). During lime intervul f 2, input A is LOW (0), but beC
x
FIGURE ] - 19
Example of OR gate operation with a timing dii'lgram Ihowing input and output time rclatiomhips.
In this illustration, we have applied the truth table operation of the OR gale to each of the ti me intervals during which the levels are nonchanging. Examples 3-61hrough 3--8 further illustrate OR gate operation with waveforms on the inputs.
For an OR gate, at leait one HIGH input mekes a HIGH output.
125
126
•
LOGIC GATES
If the two input waveforms, A and B, in Figure 3- 20 arc applied to the OR gate, what is the resulting output waveform?
A
B -
Oulput X
-L--,
x
, " " ' " JLJ1..JLSL --..,...... '--' ~ '--' When c ilhcr inpul " r ro h inpul~ un: I IICH. the ,XJlpUl i~ I IICI I.
FIGURE 3 - 20
Sdution
Related Problem
I
The output waveform X of a 2-input OR gate is HIGH when either or ooth input waveforms are HIGH as shown in the timing dia1.!ram. In this case, both input waveforms are never HIGH at the same time. Determine Ihe output waveform and show the liming diagram if input A is changed such Ihal il is HIGH from the beginning of the existing firsl pulse 10 the end of the existing second pulse.
EXAMPLE 3 7
For the two input waveforms, A and 11, in Figure 3- 2 1, show the outp ut waveform with its proper relation 10 the inputs.
A Inputs
,, ,,,
B -HrtTW-~ , ,
Outpul X
FIGURE ]-21
Solution Related P,oblem
When eilher or oolh input wavefOlms are HIGH, the output is I·UGH as shown by the output waveform X in the liming diagram. Determine the outpul wa\'eform and show the timing diagram if the middle pulse of inpul J\ is re placed by a LOW level.
THE OR GATE
I
•
127
EXAMPLE 3-8
For the 3-input OR gate in f iguft, 3- 22, detemline the output waveform in proper lime relation 10 the inputs,
" C
,,
x " " "
I , I
I " "
" , I
, I I
--'-'-;..;..;-;..,1 1 "" ,, ," , ,, ,
x FIGURE l - ZZ
SolIltion
Related Problem
Thc output is HIGH when one or morc of the input wavefonns arc !-UGH as indicated by the output waveform X in the tim ing diagram. Detcnnine the output wavefonn and show the timing diagram if input C is always LOW.
Logic Expressions for an OR Gate The logical OR functi on oftlVo variables is represented mathematically by a + between the two variables, for example, A + B. Addition in Boolean algebra involves variables whose values arc either binary J or binary O. The basie rules for Boolean addition are as follows:
0 + 0 + 1+ 1+
0= 1= 0= 1=
When vil riilbles ilre sep
0 I 1 1
Boolean addition is (he same as the OR function. Notice that Boolean addition differs from hinar), addition in the ea~e where two I s arc added. There is no clIrry in Boolean addition. The operation ofa 2-input OR gate can becxprcsscd as follows: If onc input variable is A, if the other input variable is lJ, and jfthe output variable is X, then the Boolean expression is
X=A+ B figure 3-23(a) shows the OR gate logic symbol wi th two input variables and the Output variable labeled.
"=D/I
,.)
X : A+R
~ ~ X "'A +IJ + C
~
,b)
,<)
FIGURE 1 Zl Boolcan c)(prcssiom for OR gatcs with two, tJlrcc, and four inputs.
ID-
X =A +B+C +D
128
•
lOGIC GATES
Another rrtalk operation
.
I used in computer programming to ! ~Iectivdy make certain bib in a
data byte equ
I
To extend the OR expression to more than two input \'ariables. a new letter is used for each additional variable. For instance. the function of a 3-input OR gate can be expressed as X = A + B + C. The expression for a 4-input OR gate can be written as X = A + [j + C + D, and so on. Parts (b) and (c) of Figure 3-23 show OR gates with three al10 four il1put variables. rcspt.'clivcJy. OR gate operation can be evalualCd by using the Boolean expressions for the output X by substituting all possible combinations of I and 0 values for the input variables. as shown in Table 3- 6 for a 2-input OR gate. This evaluation shows that the output X of an OR gate is a I (HIGH) when anyone or more of the inputs arc I (HIGH). A simi lar analysis can be extended to OR gates with allY number of input variables. TABLE 3 - 6
I
A
B
A+B=X
o
o
0+0=0
o
0 + 1= 1
o
1 + 0= 1 1+ 1= 1
An Application A simplified portion of an intrusion detection and alann system is shown in Figure 3- 24. This system could be used for one room in a home-a room with twO windows and a door. The sensors are magnetic switches that produce a HIGH output when open and a LOW output when closed. As long as the windows and the door arc secured. the switches are closed and all three of the OR gate inputs arc LOW. When one of the windows or the door is opened. a HIGH is produccd on that input to the OR gate and the gate outpul goes HIGH. It then activates and latches an alarm circuit to wam of the intrusion.
FIGURE 3 - 24
A limplified intru!;oo detection
system using
BIGH = Open LOW = Closed
HIG II ;K.1 ""1C-,tl;lIm.
-----~=r=>-~-1
i
SECTION 1 - 3 REVIEW
L When is the output of <'In OR g.ate HIGH? 2. When is the output of an OR g.ate lOW! 3 . Describe the truth table for a 3-input OR gate.
AI~
circuit
THE NAND GATE
3-4
•
THE NAND GATE
The NAND gate is a popular logic clement because it can be uscd as a universal gate; that is, NAND gales can be used in combination to perform lhe AND, OR, and inverter operations. The universal property of the NAND gate will be examined thoroughly in Chapter 5. After completing this section, you should be able 10 • Identify a NAND gale by its distinctive shape symbol or by its rectangular outline
symbol . Describe the operation of a NAN D gate . Develop the truth table for a NAi\'D gate with any number of inputs • Produce a timing diagram for a NAND gate with any specified input wavefonns _ Write the log ic expression for a NAN D gate with any number of inputs _ Describe NAN D gate operation in terms of its negative-OR
equivalent . Discuss examples of NAN D gate applications
The term NAND i s a contraction of NOT-AN D and implies a n AND function with a complemented (inverted) ou tput. The standard log ic symbol for a 2-inplll NAND gate and its equi valency to an AN D gate followed by an invcrter are shown in Figure 3- 25(a), where the symbol ;: means equivalen t to. A rectangu lar outl ine symbol is shown in part (b).
(a) Disti nctive shape, 2-input NAND gate and its NU ffAND C
(b) RectJllgutar oUlli ne, 2- inpul NAND ga le with pol arity indicator
FIGURE 3-25
Standard NAND gate logic symbols (ANSI/IEEE Std. 91- 1984).
Operation of a NAND Gate A NAND gate produces a LOW output only when allthc inputs arc HIG H. When any of the inputs is lOW, the output will be HIGH. For tile speci fie case of a 2-inpul NAND gate, a~ shown in Figure 3--25 with the inpUis labe led A and /J and the output labell..'(} X, the 0peration can be stated as follows: For a 2-input NAl\'V gate, outlm! X is LOW only when inp uts II and B are HIGH;
X is HIGH " 'hen either A or 11 is LOW, or when both II and B lire LOW.
Notc that this operation is opposite that of the AND in terms of the output level. In a NAND gme, the LOW level (0) is the active {Jr asserted {Jutpul level, as indicated by the bubble on the output. Figure 3--26 illustrates the operation of a 2-input NAND gate for all four input combinations, and Table 3-7 is the truth tablc summarizing the logical operation of the 2inplll NA ND gate.
The NAND is the 1
129
130
•
lOGIC GATES
lO\\ \ O ) = D I
ow (0)
LOW (O) = D HIGII (I) HIGH (I)
HIGH ( I )
H IGH ( I ) = D HIGH (I ) l OW (0)
HIGH ( I ) = D -
111GB ( I)
lOW 0
( )
FIGURE 3 - 26
Ope.aoon of a Z-input NAND gate. Open fire F03-Z6 to verify NAND gate opE.ation.
TABLE 3-1
Truth table for a Z-input NAND g
INPUTS A B
o
OUTPUT X
0
o o
1
o I '" HIGH, 0 '" IJ:JW.
Operation with Waveform Inputs Now lei's look al lhe pul se waveform operation of a NAND gale. Remember from Ihe [ruth lable thai the only time a LOW output occurs is when all of the inputs arc HIGH.
I
EXAMPLE 3-9
If the two waveforms A and fj shown in Figure 3- 27 are applied to the NAND gate inpUis. determine the resulting output waveform.
A
R
,
,
A --r-~
:
:
8
--Jt:-:--LJ::1L
x
o, ~,-----,
l~u,*,lc
hldicalL"
an XlI\C I OW tlUlput .
x
................
........ ........
A ,mrJ 8 arc bUlh HIGH tlurlll.!! IOC~ fuur lim" inlCf\"I~ . Th~rcf"re X i~ U)W. FIGURE 3 - 21
Solution
Related Problem
OUlpUI waveform X is LOW only during the four lime intervals when both input wavefOf"tns A and B arc HIGH as shown in the timing diagram. Determi ne the output wavefOim and show the liming diagram if inpul waveform B is inverted.
THE NANO GATE
•
Show the out put wavcform for thc 3-input NAND gale in Figure 3- 28 with ils proper time relationship to thc inpuls.
A
8
0 0 0
c~
0
0 0 0
o 0 0 0 0 0
x
A
LJ
0 0 0 0
-----u
B C
X
t-
u
FIGURE 1 - 28
Solution Related Problem
Thc output waveform X is LOW only when allthrec input wavefonns arc HIGH as shown in the timing diagram. DClcnninc thc output wavcfonn and show the timing diagram if input waveform A is inverted.
Negative- OR Equivalent Operation ofa NAND Gate Inhcrent in a NAND gatc's operalion is the fact that one or more LOW inputs produce a HIGH oUlput. Table 3- 7 shows that output X is HIGH ( I) when any of tile inputs. A and B. is LOW (0). From thh. vicwpoint, a NAND gatc can be used for an OR operation that requires one or more LOW inputs to produce a HIGH output. This aspect of NAND operation is referred 10 as negative-OR. The term negoril'e in this context means that the inputs are defined 10 be ill the active or asserted statc when LOW. t~OI·
a 2-input NAND gate pclfonning a m 'gative-OR .. openllion, output X is HIGH
when either inllUt A or input /J is LOW. or when both A und /J arc LOW.
When a NAND gale is used to detect one or more LOWs 011 its i npul~ rather than all HIGHs, il is pcrfonning the negative-OR operation and is represcmcd by the swndard logic symbol shown in Figure 3-29. Although the IWO symbols in Figure 3--29 represclllthe same physical gate. they serve 10 dcfinc its role or modc of operalion in a parlicular application, as illustrated by Examples 3-11 through 3- 13.
FIGURE 1 - 29
NAND
Negat ive-OR
Standard ..,..-nbols representing the two equivalent operation~ of a NAND gate.
131
132
•
LOGIC GATES
I
EXAMPLE 3-11
A man ufactu ring pllUu U.-.eS two tanks 10 Slore certain liquid chemicals thl1l arc required in a manufacturing process. Each lank ha~ a scnsor Ihat detects when the chemical level d rops to 25% of fu ll. The scnsors produce a HIGH level of 5 V when the tan ks are more than o ne-quarter fu ll . Whe n the volu me of chemical in a tank d rops to one-quarler full , the scnsor puts out a LOW level of 0 V. It is requi red that a si ngle green light-emitting diooe (LED) on a n indicator panel show whe n both ranks are more than one-qua rter full. Show how a NAND gate can be used to implement this fu nction.
Solution
Figure 3- 30 shows a NAND gale wilh its I WO inpuls connecled 10 the tan k level and its output connecled to the indicator panel. The operdtio n can be stated a" fol lows: (flank A olld lank B arc above onc-quartcr fu ll. the LED is OIl.
:.enso~
Level sensor
... FIGURE 3 - 30
As lo ng as brnh sensor outputs are HIGH (5 V), indicating that both tanks arc more tha n one-quarter full. the NAND gate output is LOW (0 V). The green LED circuit is arranged so that a LOW voltage turns it on.
Related Problem
How can the circuit of Figure 3-30 be modified to monitor the levels itllhrec tan ks ra ther than two?
The supervisor of the manufacturi ng process described in Exa mple 3- 11 has decided thai he would prefer to have a red LED display come on when at least one of the ta nks falls to the quarter-ruHlevel rathe r than have the green LED display indicale when both are above o ne quaner. Show how this requireme nt can be implemented.
Solution
Figure 3- 31 shows a NAND gate operati ng as a negative-OR gale to detect the of at lea."t olle LOW o n its inputs. A sellsor puts OUI a LOW voltage if the volume in its lank goes to o ne-quarter fu ll or less. Whe n this happens. the gate OUlpUt goes HIGH. The red LED circuit in the panet is arnlllged so thai a I-lIGI-i voltage turns it 011. The operation can be Slated a<; follows: If lank A or tan k B or both are below one-quarter fu ll , the LED is Oil .
ncCl llTf' n ce
THE NAND GATE
•
133
,..,
J
....
HIGH
HIGII
LOW
~ ~,...
:
T"nk B
........
Rttl lighl indicat,-s OrIC til" boIh
lanh;u-e k"s lhan 11-1 fu ll
=
.-J
FIGURE 3 - 31
Notice that, in this example and in Example 3- 11. the same 2-input NAND gate is used, but a different gale symbol is used in the schematic, illustrating the diffeI"Cm way in which the NAND and equivalent negative-OR operations are used. Related Problem
How can the circuit in Figure 3- 3 1 be modifiL-d to monitor four tanks rather than two?
For the 4-input NAND gate in Figure 3- 32. operating a~ a negative-OR. determine lhe out put with respect to the inputs.
A
LJ ,, , ,
B ~ ,,
, ,,
Buhhle-. ,m],c'IlC :k;llw -IOW inptlls.
,,Ll,
•
A
8
C ~~~U,r--~~~w--,
D ~~~~:'U
-C,,- ,
£-<1.._ -"
x
LI
x FIGURE 3 - 32
Solution
The output wavefonn X is HIGH auy lime an input wavcfonn is LOW a<; shown in the liming diagram.
Related Problem
Delennine the output waveform if input waveform A is invcn cd before it is applied 10 the gate.
134
-
LOGIC GATES
logic Expressions for a NAND Gate A bar over a variable or variables indicates an inveuion.
The Boolean expression for the output of a 2-input NA ND gate is
x=
All
This expression says that the two input variables. A and 11, arc 1i rst ANDed and then complemented, as indicated by thc bar ovcr the AND expression. This is a description in equ ation form of the operalioll of a NAND gate with two inputs. Evaluating this expression for all possible values of Ihe two input variables, you gctthe results shown in Table 3- 8. TABLE 3-1
A
B
0
0
AB =X
0, 0 = 0""
0-1 = 0=
0 0
I
'· 0 = 0 = \ \.\ = \ = 0
Once an exprcssio n is determined for a given logic function, thal function can be evaluated fo r all possible values o f Ihe variables. The evalu
I
SECTION 3-4 REVIEW
1. When is the output of a NAND gate lOW? 2. When is the output of a NAND gate HIGH? 3. DeKribe the functiona l differences between a NAND gate and a negative-OR gate, 00 they both have the Qme truth table? 4. Write the output expression for a NAND gate with inputs A, 8, and C.
3-5
THE NOR GATE The NOR gate, like the NAN D gate, is a usefu l logic e lement b.!c::Jusc it can also he lIsed a~ a universal gale; thaI is, NOR gates can be used in combination to perform the AND. OR. and invcrtcr opcralions. Thc univcrsal property of the NOR gatc wi ll be e,.;mnincd thoroughly in Chapter 5. After completing this section, you should be ablc to • Identify a NOR gale by its distinctive shape symbol or by its rectangular outline symbol - Describe the operation of a NOR gate _ Dcvelop the trllth table for a NOR gate with any nu mber of input1> _ Produce a timing. d iagram for a NOR gale with any specifie d input waveforms _ Write the log iC expression for a NOR gale with any number of inputs - Describe NOR gale operation in lenns of ils negative-AND equ ivalent - Discuss examples of NOR gate applications
THE NOR GATE
The tcrm NOR is a contraction of Nar.·OR and implies an OR func tion with an inverted (complemented) ompul. The standard log ic symbol for a 2-input NOR gate and its el]ui valent OR gate followed by an inverter arc shown in Figure 3-33(a). A rectangular outline symbol is shown in part (b).
fa)
Di.~li nCli,'e ~hapc .
2-inpul NOR !!31e and
il~
Nm·IOR
fbi
Rcce un~ulM
NOR
eqllil'aiem
g~ e ..
Oluelioc. 1-inpul wilh polarily indicalOT
FIGURE 3-33
Sbnd"rd NOR gate logic I)'ITIbols (ANSI/IEEE Std . ." -1984).
Operation of a NOR Gate A NOH gatc produces a LOW output when lilly of its inputs is HrGH. Only when all of its inputs are LOW is the output HIGH. For the specific case of a 2-input NOR gate, as shown in Figure 3- 33 with thc inputs labeled A and IJ and thc output labeled X. thc operation can be stated as fo llows:
For a 2-input NOR gate, output X is LOW when either input A or input IJ is HIGH, or when bot.h A and JJ arc HIGH; X is HIGH only when both A and B art' LOW. Th is operation results in all omput level opposite thaI of the OR galC. In a NOR gate, thc LOW omput is the active or as.<.erted output level as indicmed by the bubble on the ompul. Figure 3-34 illustrales the opemtion of a 2-input NOR gate for all four possible input combi nations, and Table 3- 9 is thc trut h table for a 2-input NOR gate. Lo\\ (O)~
I OW ( O ) = I > -
LOW (Ol ~ HIUH (I)
HIG11 ( ll = I > I.tlW (O)
FIGURE
H1UII III
LOW 0) (
~IIGII (l)~
LOW (0)
HIGII ( I ) ~ 1.0""' (0)
]-)4
Opc,.,tiOll of" 2-input NOR g<)te. Open file F03-34 to verify NOR g"tc oper"UOIl.
TABLE ]-9
INPUTS
A
8
o o
0
OUTPUT
X
Truth t"ble for <) 2-input NOR g.. te.
0
u
0
o I .. HIGH. 0 _ LON.
Operation with Waveform Inputs The nex( two examples illustrate the operation of a NOR gate with pulse waveform inputs. Again, as wilh the other tyJX!s of gates. wc will simply follow the tmth table operation to detcnnine the output wavefonns in the proper time relationship to the inputs.
•
135
The NOR is the same as the OR except the output is inverted.
136
•
LOGIC GATES
I
EXAMPLE 3 - 14
If the two waveforms shown in Figure 3--35 are applied to a NOR gate, what is the resulting output waveform?
A
---f1---------,
B --r-+--jr-lr-~l,---r,, ,
A
- - r___
B
- -L--"
x
, ,
X~ FIGURE 3 - 15
Solution Related Problem
I
Whencver any input ofthc NOR gate is HIGH, the output is LOW as shown by the output waveform X in the timing diagram. Invert input Band delCnnine the output wavefunn in relation to the inputs.
EXAMPLE 3 15
Show the output waveform for the 3-input NOR gate in Figure 3-36 with the proper time relation to the inputs.
A
----11-'------
A- -r____
•
C-
-L./
x
c-t,------1-ii, , ,,,
X -,~
________
,, ,
~,__
FIGURE 3- 36
Solution
Related Problem
The output X is LOW when any input is HIGH as shown by the output waveform X in the liming diagram. With the B and C inputs inverted, determine the output and show the timing diagram.
Negative-AND Equivalent Operation of the NOR Gate A NO R gate, like the NAN D, has another aspect o f iL>; o peration that is inherent in the way it logically functions. Table 3-9 shows that a HIGH is produced on the gate output only when a ll of the inputs are LOW. From this vieWpOint, a NOR gate can be used fOf an AND operation that requ ires all LOW inputs to produce a HIGH outpUl. This as pect of NOR operation
THE NOR GATE
•
is callcd ncgalivc-AI\'D. The term lIegarive in this context means that the inputs are defi ned to be in the act ive or assel1ed state when LOW.
«-or a 2-inlml NOR gale pcrlonning a ncgath'c-AND operation, output X is HIGH ollly whell both inputs A and II arc LOW. When a NOR gate is used to detect all LOWs on its inputs rather than one or more HIGHs, it is performing Ihe negative-AND operation and is represented by the standard symbol in Figure 3- 37. It is important to remember that the two symbols in Figure 3- 37 represent the same physical gate and servc only to distinguish between the two modes of its operation. The following three examples illustrate this. ... FIGUR E 3 - 37 NOR
I
Negalive-ANI)
Standard symboll representing the two equivalent operation! of a NOR gate.
EXAMPLE 3-16
A device is needed 10 indicme when two LOW levels occur simu ltaneously on its inputs and to produce a HIGH output as an indication. Specify the device.
Solution
A 2-input NOR gme operating as a negative-AND gate is required to produce a HIGH output when both inputs are LOW. as shown in Figure 3- 38. FIGURE 3-3' LOW ~
LOW ~ llI G H
Reillted Problem
I
A device is needed to indicme when one or two li IGH le ....els occur on ils inputs and to produce a LOW Output as an indication. Specify the ucvice.
EXAMPLE 3-17
As part o f an ai rcraft's functional monitoring system, a circuit is required to indicate the status of the landing gears prior to landing. A green LED display rums on if all three gears are properly extended when the "gear dow n" switch has been a(.1ivated in preparation for landing. A red LED display turns on if any of the gears fail to extend properly prior to landing. When a landing gear is extended. its sensor produces a LOW vollage. When a landi ng gear is retracted. its sensor produces a HIGH voltage. Implement a circuit to mectthis requirement.
Solution
Power is applied to the circu il on ly when the "gear down"" switch is activated. Use a NOR gate for each of the two re
137
138
•
lOGIC GATES
Sl:nSor is detected by the NOR gate . which produces a LOW output 10 tum on the red LED warning display.
Landi ng gcar SCI\M)fl;
Elo: tended '" LOW Retr..cte(t '" HIGH
Red LEO ~
(i.>,ar TCIroICIOO
Grttn LEO ~ A U gcafCKtcmlcd
FIGURE ]-39
Related Problem
~ANDS
• N
.
What type of gate should be used to detect if all three landing gears are retracted after takeoff. a<;suming a LOW output is required to activate
When driving a load such as an LED with a logic gate, consult the manufacturer's data sheet for maximum drive capabilities (output curre nt). A regular IC logic gate may not be capable of handling the current required by certain loads such as some lEOs. logic gates with a buffered output such as an open-collector (OC) or open-drain (00) output. are available in many type of IC logic gate configurations. The output current capability of typical IC logic gat~ is limited to the JLA or relatively low mA range. For example. standard m can handle output currents up to 16 mAoMostLEDs require currents in the range of about lOrnA to 50 rnA.
For the 4-input NOR gate operating as a negati ve-A ND in Figure 3--40, determine the output relal'ive to the inputs. A ~r-------
,
H
1LL.-r---,
c
lW----...r- -
f)
I~:
,,
_+-____
,
x ~
FIGURE 3-40
j---
_ __ _ __
x
THE EXCLUSIVE-OR AND EXCLUSIVE-NOR GATES
Solution
Related Problem
_
Any time all of the input waveforms arc LOW, the output is HIGH as shown by output waveform X in the timing diagram. Determine the output with input D inverted and show the timing diagram.
logic Expreuion.s for a NOR Gate The Boolean expression for the output of a 2-input NOR gate can be wriften as
X = A+B This equation says that the two input variables are first OReeI and then complemented, a~ ind icated by the bar over the OR expression . Evaluating this expression. yo u get the results shown in Table 3- 10. The NOR expression Clm be extended to more than two input varia~ les by including additiOllallelters to represent the other variables. TABLE 3-10
A
8
A+8=X
u
u
0 + 0 "" 6 ",,
o
0 + 1 "" 1 = 0
o
1+ 0 = 1 = 0
T+"T = I = O
I
SECTION 3 - 5 REVIEW
1. When is the output of a NOR gate HIGH? 2. When is the output of a NOR gate lOW? 3. De«:ribe the functiona l difference between a NOR gate and a negative-AND gate. Do they both have the same truth table? 4. Write the output expression for a 3-input NOR with input variables A, B, and C.
3-6
139
THE EXCLUSIVE- OR AND EXCLUSIVE - NOR GATES
Exclusive-OR and exclusive-NOR gales are formed by a combination of other gales a lready di scus~, as you wi ll see in C hapter 5. However, because of their funda mental importance in many applications. these gates are o nen treated a'> ba<;ic logic clements with their own unique symbols. After completing Ihis section. you shou ld be able 10 • Identify the exclusive-OR and exclusive-NOR gales by their distinctive shape symbols or by their rectangu lar outline symbols - Descri be the opcr
14 0
•
l OG IC GATES
The Exclusive-OR Gate Standard symbols for an exclusive-OR (XOR fo r ~hortJ gate are shown in Figure 3-4 1. The XOR gatc has only IWO inputs. fonn an adder circuit a ll ow a computer to perform addit ion, lubtr;)ction, multiplication, " nd divilion in ib Arithmetic logic Un it (AlU). An exclulive-OR g"t e combines balic AND, OR, "nd
A
8
(a) Distinctive shape
--GIl
-L-I-- X
( b ) Rcctantu tar omlinc with the XOR
N OTtogi<:. FIGUR E 3 - 41
Standa rd logic Jymbol! fo r the exclusive-OR ga te.
Fo r an exduJive-OR gate, opposite inputs nklke the output HIGH
' 1l1C o utput o f an cxl'Iusivc-OR gatc is HIGH ol1ly whcn thc two inputs are at oppositc logic leve ls. This opemtion can be stated as fo llows with reference to inputs II and B and OUiput X:
FOI· a n cxclusi\'e-OR gate. output X is HIGH when input 1\ is LOW a nd inp ut H is HIGH, or n'hen inpul /1 is HIGH and input II is LOW; X is LOW when A and II arc both HI GH or both LOW. The four possible input combinations and the resulting outputs fo r an XOR gate are illustrated in Figure 3-42. The HIGH level is the active or asscncd o utput 1e"e1 and occurs only when the inputs arc at oppositc levels. The operation of an XOR gate is summari /.ed in thc tmth table shown in Table 3-1 I. FIGURE 3 - 42
LO~ (O) ~ ____
All possible logic levels fo r a n exclusive-OR gate. Open file F03-42
LOW (O) ~ I .OW (O)
LOW (O) ~ __ HIGH (I ) ~ HI GH ( I )
to verify XOR gate oper;)tio n. HIGH ( I )----\~ LOW (0) ~ HIGH ( I)
HIGH ( I ' ~
II I GH ( I )~ LO\\' {O)
TABL E 3 - 11
Truth table fo r an exclusive-OR gate.
, INPUTS A B
o
o
OUTPUT X
o
o o
o
A ccnain system contains two identical circuits operating in parallel. As long as both arc operating properly, the outputs o f both c ircuits are always the S
Solution
The OUlputs o f the circuits arc con nected to the inputs o f an XOR gatc as shown in Figure 3-43. A failure in either one orlhe circu its produces diITering ou tpu ts, which
THE EXCLUSIVE-OR AND EXCLUSIVE · NOR GATES
•
cause the XOR inputs to be at opposite levels. This condition produces a HIGH on thc output o fthc XOR gatc, indicating a fa ilure in one o f the circuits. l-HGH
I
CirclliCA.~ L _ _ _-' Ci reu i18
I :
tttGll lirxlicnlcs failutc) LOW
FIGURE 1 - 41
Related Problem
Will the exclusive-OR gatc a lways detCt:t simu ltancous fa ilures in both circuits of Figure 3-43? If not, under what condition?
The Exclusive-NOR Gat e Standard symbols for an exclush'c-NOR (XNOR) gat(' are shown in Figure 3-44. Like the XOR gatc, an XNOR has o nly two inputs. The bubble on the out put o f the XNOR symbol indicatcs that ils output is opposite that of the XOR gatc. When thc two input logic levels arc opposite. the output or the exclusive-NOR gate is LOW. Thc operation can be stated as fo llows (A and B arc inpuL<;. X is the output):
For an exclus ive-NOR gate, output X i" LOW whcn input A is tOW lmd input /J is HIGH, or when A is HIGH and H is LOW; X i" HIGH whcn A and H arc both HIGH or both LOW.
A
------GIl.
B~-X
(b) RCCI<\l1llu ti\r oul1inc. fIGURE 3 - 44
Standard logic l)'I'I'Ibols (or the exclulive-NOR gate.
T he four possible input cumbinations and the resulting out put:. for an XNOR gatc are shown in Figure 3-45. The operation of an XNOR gale is summarized in Tablc 3--12. Noticc that the output is HIGH when the SlilnC level is on both inpuLs.
Lo\\ (O)~
LOW (O)~ HJGH ( t )
IOW (O)~ HIGH (t) ~ LOW {O)
t~~\~ ~~;=D- LOW (Uj
I HGH (I)
l IIG I I (J )~
-IL-/"
11lGH (1)
ftGURE 3 -45
All poslible logic levels fOF an exclulive-NO R gate. Open file F03-45 to verify XNOR gate operation.
141
142
•
l OG IC GATES
TABLE 3-12
INPUTS
Truth table for an e,,;dulivc-NOR gate.
A
B
o o
0
OUTPUT X
0
o
o
Operation with Waveform Inputs As we have done wi lh Ihe other gates, Jet's examine thcopcration of XOR and XNOR gates with pulse wavefonn inputs. As before, we apply Ihe trut h table operation during each distinct time interval of the pulse waVef0n11 inputs, as illustrated in Figure 3--46 for an XOR gate. You can sec Ihat the input wavefonns A and B are at opposite levels during time intervals '2 and '~. Therefore, the output X is HIGH during Ihese two times. Since both inpuls arc at Ihe same level, either both HIGH or both LOW, during time intervals'l and ,), the outpul is LOW during those limes as shown in Ihe timing diagram.
FIGURE 3 - 46
Example of exdu.ive-OR gate oper;)tion with pu l~ waveform
A
,
,, ,
inpub. B
,,, ,
J
• ,,,
A
•
0
,, ,,
I
I
I
I
I
, ,,, ,
,,
,,
,,
,,
!-II --"'-- '2~t)~I~ ---,
t
X
I
I
I
I
I
0
EXAMPLE 3-20
Dclermi ne the output waveforms for the XOR gate and for the XNQR gate, given the input wavcfonns, A and B, in Figure 3-47.
A
" XOR
XNOR
FIGURE 3 - 47
:] )
X
PROGRAMMABLE LOGI C
Solution
Related Problem
Detennine the ou tput waveforms if the two input waveforms. A and B, arc inverted.
An exclusive-OR gale can be used a~ a two-bit adder. Recall from Chapter 2 that the basic ru les for binary addition arc as follows: 0 + 0 = 0,0+ I = I, I + 0 = I, and I + I = 10. An examination of the truth tablc for an XOR gate will show you that it~ out put is the binary sum of the two input bits. In the case where the ill puts are both Is, the output is the sum 0, but you lo:se the carry of I. In Chapter 6 you will sec how XOR gates are combined to make complete adding circuits. Figure 3-48 iIIustr
A B
o
o
Output (sum)
An XOR gate
Uled
to add two bill.
I o
o
o o
t without I carry)
LJoJ I
SECTION 3 - 6 REVIEW
1. When is the output of an XOR gate HIGH? 2. When is the output of an XNOR gate HIGH? 3. How can you use an XOR gate to detect ......nen two bib are djfferent?
3- 7
143
Thc output waveforms arc shown in Figure 3-47. Notice that the XOR output is H IGH only when both inputs arc at opposite levels. Notke that the XNOR output is HIG H only whcn both inputs arc the same.
An Application
Input bib
•
PROGRAMMABLE LOGIC
Programmable logic was introduced in Chapter I. In this section, the basic concept of the programmable AND array. which form s the basis for most programmable logic. is d iscussed, and the major process techno logies arc covcred. A programmable logic dcvil:c (PLD) is onc that doc.." not initially have a fixed-logic function hut that ean be progmmmed to implement just abou t any logic design. As you havc tearned. two typc:; of PLD arc the SPLD and CPLD. In addition to the PLD, the other major category or programmable logic is thc FPGA. For simplicity, all of these devices will be refcrred to as PLDs. Also, somc important concepls in programminE are discussed. After complcting this section, you should be able to • Describe the concept of a programmable AND array _ Discuss various process technologies • Discuss text entry and graphic ent ry as two methods for programmable logic dcsign • Describe mcthods for downloadi ng a design to a programmable logic devicc • Explain in-system progrnmm ing
144
•
lOG IC GATES
Basic Concept of the AND AlTay Most typcsofPLDs usc some form o r ANDarr".l). Basically. this array consists of AND gates ant! a matrix of interconnections with progrrunmab[e links at each eross point. as shown in Figure 3-49(a). The purpose of the progmmmable links is to either make or break a connection between a row linc and a column [inc in the interconneClio n matrix. Forcach in put 10 an AND gate. only one proglammable link is lert intact in order 10 eonncclthe desired variable 10 the gale input . Figure 3-49(b) illustmles an array after il has been pro!l'
B
-
Ii,,).. A
/I
-
....
•.
•
x,
'.
"
H
A
x,
r,
.Y.~ = III
.... - -
" (al Unprogrommed FIGURE ] - 49
Basic concept of " progr<>ffirlJ
i
EXAMPLE 3-21 Show tl~ AN D ~I1Y in Figure ~~9(a) programmed for the following o ut puts: XI = A B. X2 = A B. a nd X J = A B
Solution
See Fi gure 3- 50. /I
'., <,
x,
.-.
x,
FIGURE 3-50
R.elated Problem
1low many rows. COI Ulllll S. and AND gate inpuls are requ ired for th ree input variables in a 3-A ND gate a rray?
PROGRAMMABLE lOG IC
•
Programmable link Process Technologies Several d ifferent process techno logies arc used for programmable links in PLDs. Thi s was the origina l programmable link technology. It is still used in some SPLDs. The fuse is a metal link that connects a row and a column in the interconneclion l11alrix. Bdore programm ing, there is a fused conncction at each intersection. To progrmn a device, the selected fuses arc opened by pa.~ sing a CUiTent through them sufficient to " blow" the fu se and break the connection. The intact fu ses remain and provide a connection between the rows and columns . The fu se link is ill ustrated in Figure 3- 51. Programmable logic devices that usc fuse technology arc o ne-time programmable (OTP). FUJe Technology
FIGURE 3 - 5 1
The progrommable fule link.
(a) Fu5C intact bcfOfC programming
(b) I'mgrammillj; curren!
(c) Fn se open after progra mmi ng
Antifme Technology An antifusc programmable link is the opposite of a fuse link. Instead ofblCi.lki ng the connection, a connection is made during programming. An antifuse starts out as an open circuit wherca<; the fuse starts out a<; a 5h0l1 circuit. Bcfore programming, there arc no connections between the rows and columns in lhe interconnection matrix. An ,mtifuse is ba<;ically twoconduetors separated by an insulator. To program a device with anti fuse technology, a programmer tool applies a sufficient voltage across selected antifuses to break down the insulation betwccn the two conductive materials. causing the insulator to become a low-resistance link. The .mt iruse link is illustrated in Figure 3- 52. An anlifusc device is also a one-time programmable (OTP) device.
¥
'"I;
Contacb
FIGURE 3-52
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EPROM Tec:hnowgy In certain programmable logic devices, the programmable links arc similar to the memory cells in EPROl\h (eleclrically progmmmable read-only memories). This type of PLD is programmed using a spcciill lOOI known as a device programmer. The device is inserted into the programmer, which is connected to a computer m nning the programm ing software. Most EPROM-based PLDs are one-time programmable (OTP). However, those with windowed packages can be erased with UV (ultraviolet) light and reprogrammed using a standard PLD programming fi xture. EPROM process teChnology uses a spccialtypc of MOS transistor, known as a noating-gate transistor, as the programmable link. The noating-gate device utili zes a process called Fowler-Nordheim tunneling to place electrons in the floating-gate structure.
145
146
•
lOGIC GATES
In a progmmm
FIGURE 3 - 53
A ~implc AND array with EPROM technology. Only one gate in tnc array i~ shown fer simplicity.
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Ek'Ctricilll y erasable programmable read-only memory !(.'!:hnology is similar to EPROM because it illso U.~es a typcofOoating-gate tra nsistor in E2CMOS cel ls. l11C difference is thai EEPROM can be enl-"Cd and reprogmmmed electrically wit hout the need for UV light or special fi xlUres. An E~CM OS device can be programmed after being installed on a printed c ircuit bo.1rd, and many can be reprogrammed while operming in a system. This is called in-system programming (ISIl). Figure 3- 53 can also be used a!\ an cxample to represent an AND array with EEPROM tcchnology. A fla sh arruy is a type of EEPROM amlY that not only can be emscd much faster than with standard EEPROM te<:hnology but can al!\o TCSult in higher de nsity devi<."CS.
EEPROM Technology
M:rny FPGAs and some CPLDs usc a process technology simi lar to thill used in SRAMs (static random-access memories). T he bilSic concept of SRAMbased prognunmable logic arrays is illustrated in Figure 3- 54(a). A SRAM -typc memory cell is used to turn a transistor n il or olJ lO connect or disconnect rows and columns. For example, when the memory cell contains a 1 (green), the transistor is 011 and connects the associated row and column lines, as shown in part (b) . When the memory ce ll contains a 0 (blue), the transi stor is off so there is 110 connection between thc lines. as shown in part (cJ. SRAM technolo,gy is different from the other process technologies d iscllssed Ix:cause it is a volatile technolo~')'. This mel.lllS that a SRAM cell docs not retain datil when power is tumed off The progmmming data must be 1000\ded into a memory: and when power is ItImed 011, the d,11a from the memory reprograms the SRAM-bascd PLD. The fusc, 'lI1lifuse, EPROM, and EEPROM process technologic.s arc nonvolatile, SO they retain their programmin£ when the power is off A fuse is permanently open. an anti fuse is permanent ly closed, and floati ng-gale transistors USI...'{] in EPROM and EEPROM-based armys can retain their 011 or off slate indefinitely. SR.AM Technology
Most 'Y'tem-lcvcl dcsigns incorporate a variety of devicel such
I",
PROGRAMMA BLE lO GIC
8
A
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•
147
FIGURE 3 - 54
/I
Basic concept of an AND array with SRAM technology.
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'1
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Device Programming 1lle gene ..,! concept of programming WllS introduced in Chapler I. and you Imvc S(.-'CII how interconnCCliOIl t< can be made in a simple army by opening o r dosing the programmable li nks. SPLDs, CPLI)s, and FPGAs arc programmed in essentially the snme wHy. The devices wi th (rrp (one-time programmable) process tCChnologies (fusc. amifusc, or EPROM) mllst be programmed with a special hardware fi xture called IIIJfOgrammer. 111e progmmmer is connected 10 a (;()mpu\cr by a standard interface cable, as shown in Figure 3- 55. Dcvclopmcnl software is installed 011 the computer, and the device is inscrtL"tI into the prob>r.llnmcr socket. Mosl programmers hll\'e adaplcrs, such as the o ne shown, thal allow diffcrclI1lypcs of packages to be plugged in,
---'---"-----.
FIGUR E 3 - 55
Setup for programming a PLD in a progra mming /i>:ture (programmer),
CompUl.:r ruulli llt! I'Ll) di:vdOp'I1CIll S(lflWall.'
- 1
148
•
LOGIC GATES
EEPROM and SRAM-bas<:d programmable logic devices are reprogrnmmable and can be reconfigured multiple limes. Although a device prognlmmer can be usc
Programming sctup for reprogrilmmilblc logic devices.
Design Entry As you learned in Chapter I, design entry is where the logic design is progr'
In-System Programming (ISP) Certain CPLDs and Rl(JA~ can be prognuTIllled after they hllYe been installed on II ~y s tern printed circuit bo.1rd (PCB). After a logic design has been developed and fully tested on it development board, it canthcn be programmed into a "blank" device thaI is al ready soldered onto a system board in which it will be operating. Also, if a design change is required, the device on the system bo.ard can be rccontigurcd to incorporate the design modifications. In a production situation. programming a device on the syslem board mi nimi7..cs handling and elimi nales the need for keeping stocks of preprogrammed devices. It also rulcs
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FIGURE 3 - 57
oomplcs of design cntry of ,10 AND gate.
OUl lhc possibi lity of wrong parts being placed in a product. Unprogmnlllll.:u (blank) dcvicc.'i can be kepi in the warehouse and pll)gmmmed on-board as nl.'Cded. This minimi7..cs Ihecapilal a bltsincss nCLxls for invcntories and enhances the quality of ils products. The standard established by the Joint Test Action Group is lhe common ly used name lor IEEE Std. 1149. 1. The J TAG slandard was developed to provide a simple method. called boundary scan, for testing programmable devices for Functionali!y as well as testing circuit board!'> for bad cOrllK'Ctions-shorted pins, open pi ns, bad InLeCS, and the like. More rece ntly, JTAG has been used a..; aconvenient way of l:onfiguring programmable devict;'!s insystem. As the demand for IicJd-u pgradable products increases. Ire usc of JTAG as a convenient way of reprogramming CPLDs and FPGAs will continue 10 increasc. JTAG-compliant devices have internal dl.xlicalLxI hardware Ihat inlerprels instructions and data provided by rour dedicated signals. Thcse signalS arc defi ned by the JTAG slandar
}TAG
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FIGURE 3-58
Simplified iIIustr ... tion of in~tem programming via aJTAG interfacc.
ITAG hardware insi
.
•
149
150
•
l OGIC GATES
Embedded Procenor Another approach to in-system programming is the usc of an embedded microprocessor and memory. The processor is embedded within the sySlem along with the C PLD or FPGA and othcrcircuitl)'. and it is dedicated to the purpose of in-system configuration of the programmable devicc. As YOll have IcamL-d, SRAM-based devices arc volati le and lose their progmmmed data when the power is tumed off. It is neCL'Ssa ry 10 store the programming data in a PROM (pro~ rammable read-onl y memory). which is nonvolatile. When power is turned on. the emtx:dded processor takes control of transferring the stored data from the PROM 10 thc CPLD or FPGA . Also. an embedded processor is sometimes used for reconfigll ration of a prognlmmable device while the system is mnning. In this casco dL"Sign changes arc done with software. :lnd the new data tire then loaded into a PROM wi thout disturbing the operation of the system. TIle processor cont rols the transfer of the data to the device "on-the-fly" at an appropri
FIGURE ]-59
Simplified block di... gr... m of a PLO with an embedded processor ... OO memory.
PROM
Pn>gmmmabk logic
1. list fIVe process technologies used for programmable links in programmable logic. 2. What does the term volatile mean in relation to PlDs "nd which process technology is volatile? 3. What are t\IIO design entry methods for programming a PlDs and FPGAs? 4. OefineJTAG.
3-8
FIXED-FUNCTION LOGIC Two major digital imegnlled circuit (IC) leehnologies that me used 10 implement logic gate~ are Cf\.·\OS and TrL. The logic oper.llions of NaT, AND. OR. NAND, NOR. and exclusive-OR mc the smne regardless of the IC lechnology u~ed : Ih
YOll
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10
• Iden tify the most common CMOS "nd TfL series . Compare CMOS and lTL in terms of device Iypes and performance parameters . Define pmpaxario/l {lela.\" lime . Define power lli.fsipation _ Define/all-ollt _ Define speell' pOlver product • Interpret basic dala sheet information
FIXED- FU NCTION l OGIC
CMOS stands for Complemeillary Metal-Oxide Semiconductor and is implemented with a type of ficld-cffcclll,msistor. TIL stands for Tnmsislor-TmnsiSlor Logic and is implemented with bipolar junction t ransist~ . Keep in mind that CMOS and TIL differ only in the type of circuit components and vdluL'S of parameters and not in the basic logic operation. A CMOS AND gale has the same logic opcmtion as a TTL AND gate. This is true for all thc OI:her basic logic functions. The difference in CMOS arxl TrL is in pcrfonnancc chamcleristics such as switching speed (propagation delay), power dissipation. noise immunity.•md OI:I-cr paramcK'rs.
CMOS T here is little disagreeme nt about which cireuit technology. CMOS or TTL. is the most widely used. It appears that CMOS h
CMOS Seriel The categories of CMOS in lerms of the dc supply voltage arc the 5 V Ct-.'IOS, the 3.3 V CMOS, Ihe 2.5 V CMOS, nnd the 1.8 V CMOS. The lower-voltage CMOS fillnilie s are ;\ more recent development and arc the result of an e ff0l1 to reduce the power dissipation. Since power dissipation is proportional to the square of the voltag.e, a reduction from 5 V 10 3. 3 V, for example. ClllS Ihe power by 34% with other faclOr!'> remaining the ~ame. Within each supply voltage category, several ~ri es of CMOS logic gates are avnil"ble. T hese series wilhin the CMOS famil y differ in the ir p.!rformance chamcleristics and are designated by the prefix 74 or 54 followed by a leuer or leiters that indicate the series and then it number thai indicates the type of logic device. TIle prefi x 74 indicates commerci
74BCf-BiCMOS 74A BT- Advanced BiCMOS 74LVT- Low-vlJltage BiCMOS 74ALB- Advanced Low-voltage meMOS
•
151
152
•
LOGIC GATES
TTL TTL has been a popular d igitallC tcchnology fo r many years. One advantage ofTrL is that it is not sensit ive to ek.'Ctrostalic diseharge as CMOS is and, therefore , is more pnlctical in most lnbormory experimentation and prolotyping becausc you do not have to worry about handling precautions.
TTL Series Like CMOS, several series o f TIL logic gates are available. all which operate from a 5 V de supply. These series wi thin the TTL family d iffer in their performllnce characteristic!> and arc designmed by the pretix 74 or 54 fo llowed by a leller or leiters thm indicate the series and a number thm indicates the type of 10bic device withi n the series. A TIL IC eem be distinguished from CMOS by the lellel>l that follow the 74 or 54 prefix . The basic TIL series and their designations arc a<; fo llows:
74-sl
Types of Fixed-Function logic Gates All of the basic lot;icopcrations, NaT, AND, OR, NAND, NOR, exclusiv(."-OR (XOR), and exclusive-NOR (XNOR) arc available in both CMOS and TIL In addition 10 these, buffe red output gates are also available for driving loads that require high currenL<;. The types of gate configunltions typically available in Ie packages arc identified by the [astlwo or three digits in the series designation, For example, 74LS04 is a low-power Schottky hex invelter package. Some of Ihe common logic gate configufiltions and their standard identifi er di gits arc as fo llows: Quad 2-inpuf NAND-OO
Dual 4-input NAND-20
Quad 2-input NOR-02
Dual 2-inpllt AND- 2t
Hex invcrter--04
Triple 3-input NOR-27
Quad 2-input AND-08
Si ngle 8-input NAND- 30
Triple 3-input NA ND- tO
Quad 2-illPllt OR- 32
Triple 3-input AND-ll
Quad XOR- 86 Quad XNOR- 266
Ie Packages
All of the 74 .
FIXED-FUNCTI ON l.OG I C
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153
154
•
LOG IC GATES
Sinfl.e-Gaw Logic A limited selection of CMOS gates is available in si ngle-gale packages. With one gate 10 a package., this series comes in tiny 5-pin packagcs that arc intcnded for llse in last-minute modifications for squcezing logic into tight spots where avaihlb1e space is limited. Logic Symbols The logic symbols for fixed-fu nCtion imegr.ltoo circuits usc the standard gate symbols
Vcr
I ( 14)
(I)
(3)
(5)
(9)
(II ) ( 13)
(2)
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(2)
(3)
(4)
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(6)
(9)
(8)
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(4)
( 13)
(12)
(8)
R oc ran~lI l ar ourline logic symbol with polarity indicators. "Ille in\'crt<,;r qWllifying sy mbol ( I) "ppears in the lop block and aJlf!I;c~ 10 ,dl blocks
bcklW.
1(7)
(5)
( 10)
( 12) ( 13)
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(I)
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(2) (4) (5) (9) ( 10)
( 12) (1 3)
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(I)
(9)
( Ill)
(12)
Vcr
G ND l~ic
(a) He>. ;1l\,<,; r1cr
l b) Quad 2-inpul NAN D
FIGURE 3-62
Logic lymbob fOI hex in'V<'rtcr (04 wffix) and quad l-input NAND (00 luffix). The Iymbol app lics to the same device in any CMOS or TIl ~r;es.
Performance Characteristics and Parameters High-lpeed logic hal a lhort propagation delay time.
Several things define the pcrform
Propagation VeJay Time This parameter is a resu lt of the limitation on switching speed or frequency at which a logic circuit can operate. The terms low speed and high sp ped, applied 10 logic circu ils, refer to the propagation delay time. The shorter the propagation delay, the higher lhe speed of the circuit and the higher the frequency al which it can operate. Propagation delay lime, '1' of a logic gate is the time interval betwccn the application o f an input pu tse and Ihe occurrence of the rcsllhing OUlpul pulsc. There arc two d ifferent
FIXED - FUNCTI ON LOG I C
•
l SS
measurements of propagation delay time associated with a logic gale thai apply to all ihe types o f basic gales: ' PIli.: The time between a specifi ed reference JX)int on the input pu l ~ and il I;urresponding reference point on Ihe resulting output pulse, with the OUlplit changing froill the HIGl-llevel lo the LOW level (HL).
' pu/ The time between a specifi ed referc nce point o n the inpul pulse and a correspomling retc r<:nce point on the resulting OUlplil pulse, with [he omput changing from the LOW Jc"clto the HIGH level (LH).
Show thc propagation delay times of lhe inverter in Figure J--
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.. fiGURE 3 - 61
Solution
Related Problem
The propagation delay times, "'ilL and rp/Jlo arc indicated in pan (b) of the figure. In Ihis case , Ihe delays are measured belween the 50% JX)ints of the corrcsJX)nd ing edges of thc input and output pulses. T he values of ' pllt. and trw arc not necessarily equal but in many case.~ they are the .~a me. One ty ~ of logic gate has a s~ci fi L-d maximum InH and t PHL of 10 ns. For another ty pe of gale the value is 4 ns. Which gate can o~mte at the highest frequency'!
For standard-series T rL gates, the typical propagation deJay is 11 liS and for F-series gates it is 3.3 ns. For HCf-series CMOS, the propagation delay is 7 n5, for the AC series il is 5 ns, and for the ALVC series it is 3 ns. All s]X.'C ificd VU lllCS ure dependent 011 certain operating conditions as stated on a data shcct.
DC Supply Voltage (Vee) T he typical de supply voltage for CMOS is cill"ler 5 V. 3.3 V. 2.5 v, or 1.8 V, depending on the categOlY. An advantage of CMOS is that the supply volt ages can vary over a wider range than for TTL. The 5 V CMOS cun to lerate supply variations from 2 V to 6 V and still opemte pro~ rl y although propagation delay time and power d issipation arc signific antly affecled. T he 3.3 V CMOS can operate with supply voltages from 2 V to 3.6 V. Thc typical de supply voltage for TTL is 5.0 V with ,\ mini mum of 4.5 V and a maximum of 55 V.
156
•
LOGIC GATES
A lower power dinipation means len current from the dc supply.
Power DUsipation TIle power dissipation, PI» of a logic gate is the product of thc de supply vollageand thc averagc supply current Normally. the supply current when thc gatc output is LOW is Hreatcr than whcn the gatc output is HIGH. TIle manufacturcr's data shcet and for the HIGH stale usually dcsignatL'S the supply curre nt for the LOW output state as as ' CO l. TI1C aventge supply CUll"Cnt is dctcrmined ba..cd on a 50% duty cyclc (output LOW halft hc timc and HIGH half the time), so tnc averagc power dissipation of a logic gate is
'co..
Equation 3- 2
PI:J = Vee (
leeu + lca. ) 2
CMOS series gatcs have very low power d issipations comparcd to the TIL series. 1·lowcvcr, the powcr dissipation o f CMOS is dependent on thc frequcncy of q>cration. At zero frequcncy thequicscent power is typical ly in the microwattlgate range, and at the maximum opcrnt ing frcqucncy it can be in the low milliwan rnngc: therefore, powcr is sometimcs specified at a given fn.'(.juency. Thc HC series, for example, has a power of2.75 fJ-W/gate at Hz (quicscent) and 600 pW/gate at 1 MHz. POwer dissipation for rTL is independent o f frequency. For cxample, the ALS series uses 1.4 mW/gate regardless oflhe frequency and the F series uscs 6 mW/gate.
o
Input and Output Logic Leveu
V IL is the LOW level input voltage for a logic gate. and Vn1 is the HIGH level input voltage. The 5 V CMOS accepts a maximum voltage of 1.5 V as V IL and a minimum voltage of 3.5 V as VII I. ·fTL aecepts a ffiilXimum voltage of 0.8 V as V1L and a minimulll voltage o f2 V as VIIl • VOL i!> the LOW level outpUl voltage and VOII is the HIGH level ompUl voltage. For 5 V CMOS, the maximum VOl. is 0.33 V and the minimum VOH is4.4 V. For TTL, the maximum VOL is 0.4 V and the minimum Vou is 2.4 V. All values depend on operating conditions as specified on the data sheet.
Speed- Power Product (SPP) This parnmeter (speed-power product) can be usco as a measure of the performance of a logic circuit taking into account the propagat ion delay time and the power dissipaTion. It is especially usefu l for comparing the va rious logic gate series within the CMOS or TIL fami ly or for comparing a CMOS £ate to a lTL gate. The SPPof a logic circuiT is the produc1 of the propagmion delay time and the powe r dissipmion and is cxpres~d injou1es (1), which is the uni t of cnergy. Thc formula is Equation 3- 3
i
SPP =
(l'pU
EXAMPLE 3 - 23 A cel1ain gate has a propa£ation delay o f 5 ns and leal = I rnA and IccL = 2.5 mA with a de supply voltage of 5 V. Determille the :;peed power product.
So/ution
PI) = Vcc (
ICCH + fCCL ) 2
= 5V
(I rnA +2 2.5 rnA) = 5V( 1.75mA) = 8.75 rnW
SPP = (5 ns) (8.75 mW) = 43.75 pJ
Related Problem
Iftnc propagmion delay ofa gate is 15 ns and its SPP is 150 pJ, what is its ave ragc power dissipatioll?
Fan - Out and Loading TIle fall-out of a logic gate i .~ the maximum number of inputs of the Ie fam ily that clln be connected to a gate's output and still maintai n the output voltage levels within specitlL'(] limits. Fan-out is a significant parnmctcronly forTTL because of the type of circuit technology. Sincc vel)' high imp<:danccs are as:wciatcd with CMOS circuits, the fan-out is vel)' high but depends on frequency because of capacitivc effL'Cts. ~1.me series in an
FIXED-FUNCTION lOGIC
Fan-out is specified in terms of un it loads. A unit [oad for a logic gate equal s one input to a like circuit. For example, a unit load for a 74LSOO NAND gme equals one input to another logic gate in the 74LS series (not n<:cess
•
157
A higher fan -out means that a gate output can be connected to more gate inputs.
Ia.. 8.0 mA Ilnillo.1d" = = = 20 III . 0.4 mA
Figure J-64 shows LS logic gales driving a number of other gates of the same circuil technology. where the number of gales depe nds on the p;.lT1icular circuitlcchnolo!1-Y. For exwllp!e. as you have seen, Ihe maximum numlx:r of gate inputs (unit loads) thm a 74LS seric." lTLgatc can drive is 20. FIGUR E 3_ 64
Driving ga le
Load g:de
The LS m NAND gate output fam out to a maximu m of 20 LS TIL gate
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Data Sheets A typical dilta sheet consists of an information page Ihat shows, among other things, the logic diagmm and packages. Ihe t"l.'Commendl:d opemting conditiOfls. the electrical characteristics, and the switching o.:harao.:leristics. P::u1ial data sheels ror a 74LSOO and a 74HCOOA arc shown in Figurcs 3--65 and 3--66, respecti vely. The length o f data sh(.'Cts vary and some have much more informat ion than others. Additional data sh(.'C ts arc provided on the Texas In~l rumcnts CD-ROM accompanying this tcxtbook .
ANDS • N
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Unused gate inputs for TTl and CMOS ~hou ld be connected to the .,ppropriate logiC level (HIGH or LOW). For AND/NAND, it is recommended that unused inputs be connected to Vcc (through., 1.0 kn resistor ""';th TIL) and for OR/NOR, unused inputs should be connected to ground.
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1. list the two types of Ie technologies that are the most widely used. 2. Identify the following Ie logic de!ignaton:
(a) l5
(b) AL5
(e) F
(d) HC
(e) AC
(f) HCT
(g) LV
3 . Identify the following devices according to logic function ;
(a) 741504 (e) 7432
(b) 74HCOO
(f) 74ACT11
(e) 74LV08 (g) 74AHCOl
(d) 74Al510
4. Which Ie technology generally h..s the lowest power diHipation? 5. Wh..t does the term hex inverter mean? What does quad 2-input NAND mean? 6. A positive pulse is applied to an inverter input. The time from the leading edge of the input to the leading edge of the output is 10 os. The time from the trailing edge of the input to the bailing edge of the output is 8 ns. What are the values of fPlJj and tPHil 7. A certain gate has a propagation delay time of 6 os and a power di15ipation of 3 mW. Determine the speed-power product? 8. Define leo. and IWi . 9. Define V'l and VIH • 10. Define VO!. and VQI1.
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3-9
lOGIC GATES
TROUBLESHOOTING TrollbleshoOting is the process of recognizing. isolati ng, and com..-cting a fault or fai lure in a circuit or system. To be an effectivc troubleshootcr, you must understand how the circuit or sySlem is supposed to work and be able 10 recognize incorrect performance. For cJlample, 10 detcnnine whether or not a certain logic gale is fau lty, you must know what the output should be for given inputs, Aner completing this section, you should be able
10
• Test for interna lly open inputs and outputs in Ie gaks - RL'COgnjze the effect!'> of a shorted Ie input or outplll • Test for external faults on a PC board • Troubleshoot a simple fTL'quency counter using an osci llosopc
Internal Failures of Ie Logic Gates Opens and shorts ,Ire the most common types of intemal gale fai lures. These can nccm on the inputs or on the OUlput o f a gate inside the Ie package. Before attempting allY IIVI/hieS/lOoting, check for p l'Oper de SUIJply ,'o/tage Gild groul/d. Effects of an Internally Open Input An internal open is the result of an open component on the chip or a break in the tiny wire connecting the Ie chip to the package pin. An open inpul prevents a siEnal on thaI input from Eetting 10 the Output of the gate. as ill ustrmed in Figure 3-67(a) for thc C3..."-C of a 2-input NAND p:ale . An open TIL input acts cff<:ctivc1y as a HIGH level, so pulses applied 10 the good input get through 10 the NAND gatc output as shuwn in Figure 3-67(b).
Open inpul
JlJLJUL
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} - 1\0 pul..cs
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(a) Ap plication of pill S(:!; 10 100 ope n inpul wi ll prod uce 110 on th'" oulpuL
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A ppt ic~\tioo of pulses 10 the ~ood inpul will produce o utput pul ses fur TI'L NAND lind A ND glllL'S bet:lI.\I_"oe lin open inpullypicll.Uy acts as II HIGH . II is uncertai n foreMOS.
FIGUR E ] - 6 7
The effect of;Jn open input on a NAND gate.
Condih'om for Testing GateJ When Icsting a NAND gate ur an AND gale, always make sure that the inputs Ihat arc not bei ng pulsed arc HIGH to enablc the gate. Whcn checking a NOR gate or an OR gate. always make sure that the inputs Ihm arc not being pulsed are LOW. When checking an XOR or XNOR gale, the level of the nonpulSl.--d input docs not mUlier because the pulses o n the other input will force the inputs to alternate betweenthc same level and opposite levels. TroubleJhooting an Open Input Troubleshooting this type of fa ilure is easi ly accomplishL"" with an oscilloscope alld (llllClion generator. as demonstmled in Figure 3-68 for the case or a 2-inpllt NAND gate package. When measuring digital signals with a scope. always use dc coupling.
TRO UBLESHOOTING
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FIGURE 3 - 68
Troublehooting a NAND gate for an open input.
Thc first step in troubleshooting an Ie that is suspected of being lault)' is 10 make sure Ihm the dc suppl), voltage ( Vl"d and ground are m the appropriate pins of the IC. Nel(t. appl)' oontinuOlL" pu lses to one of the inpuL" to the gate. making sure that the othe r input is HIG II (in the case of a NAND gate). In Figure 3-68(a), start by applying a pulse waveform lo pin 13. which is one of the inputs to the suspected gate. If a pulse waveform is indicated on the output (pin I I in this case). then the pi n 13 input is nO( open. By the W'dy. this al~ prove.<; thai the nu tput is nO( open. Nel(t, appl y the pulse wuvefonn to the other gate input (pin 12). making sure the oth(:r input is HIGH. There is no pulse wavcfonn on the output at pin 11 and the OUtput is LOW, indicating thal lhe pin 12 input is open. as shown in Figure 3-68(b). lllC input not being pulsed must be HlG II for thc cascar a NAND gate or AND gate. If this were a NOR gale, IllC inpol not being pulSl.-d would have 10 be LOW. An internally open gale output pre \'cnts a ~ i g naJ on any o flhe inputs from Betti ng to lhe output. Thercfore. no matter what Ihe inplll conditions arc, the Out pul is unafic ct(:d . The level at the out put pi n of the Ie will depend upon what it
Effedl of an In ternally Open Output
•
161
162
•
LOG IC GAT ES
is ex temall y connected 10. It could be either HIGH. LOW, or n oot ing (not fi xed to any reference). In any case, there will be no signal on the output pin. Troubleshooting an Open Output Figure 3--69 ill ustrates trou bleshooting an open NOR Eate out put. In pari (a), one or lhe inpulsof lhe sus jX:cll.:d gate (pin I I in this case) is pulsL-d. and the output (pin 13) ha<; no pulse waveform. In part (b), the OIhe!" input (pin 12) is pulsed and again there is no pulse wuvcfoml on the output. Unde r the cond ition that the inputthm is nOI bcin!! pulsed is at a LOW level. this test shows lhat the out put is internally open.
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GND (a) rulse inpu l 011 pin 11. No pul!;e ou tp\,I.
lb) Pu lse input on pin 12. No pulse output.
FIGURE ] - 69
Troob'Clhooting a NO R gate for an open outpu t
5horted Input or Output Although not as common as an open. an internal short to the de supply voltage. the ground. another input. or an output can occur. When mt input or output is shorted to the supply voltage. il will be stuck in the HIGH slate. If an input or output is shorted to the ground. it will be stuck in the LOW slale (0 V). If two input.. or an input and an output ure shOrtL'(] together, they will always be at the same level.
TROUBlBHOOTING
•
External Opens and Shorts Many fa ilures invo lving d igital ICs are due to fau lts that £Ire external to the IC package. Thcse incl ude bad solder connections. solder splashes. wire clippings, improperly etched printt!Cled ofbcing fault y is the fi rst thing a technician should do.
I
EXAMPLE 3 - 24 You are checking a 74LS 10 Iriple 3-inpul NAND gale IC thai is onc of many ICs lociltt!rl on a PC bo'lrd. YOll have chL'1:kcd pins 1 and 2 and the)' arc both HIGH. Now you apply a pulse wavefonn to pin 13, and place you r scope probe fi rst on pin [2 and then on the connL'Cling PC board trace, as indicated in Figure 3- 70. Based on your ob.~crvati on of Ihc scope screcn. what is thc rIlo.~ l likcly problem?
InpUl
OUlpUt n" pm Inpul from fUllo,:I;"JIl gcllt'r.ltor
HIGH
....._ _ _ _ _ _,,
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HIGH
GNO
FIGURE 3-70
Solution
Related Problem
The waveform wilh the probe in position I shows Ihm there is pu lse adivily on the galc nutput at pin 12, but there m·c no pulses on the PC board trucc as indicatcd by thc probe in position 2. T he gatc is worki ng prope rl y, bullhe signal is nOI getting from pin 12 of the IC to the PC board trucc. Mosl likely Ihere is a bad solder connection between pin 12 of the IC and the PC board. which is creatin£ an open. You should resoldcr Ihal point and chL'Ck it again. If there arc no pulses at either point in Figure 3- 70, what fault(s) docs Ihis indicate?
163
164
•
lOGIC GATES
In most cases, you will be lTOubleshooting ICs that
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EXAMPLE 3-25 Arter trying 10 opcnlle thl' frequency counier shown in Figure 3-7 J, you find that it constantly reads oul all Os on its display, regardless of the input frequency. Determine the callsc of this malfunction. TIle enable pulse has a width of I s. Figure 3- 7 1(a) gives an example of how the frequency COLInier should be workins with a 12 Hz pu l ~ waveform on the input 10 the AND gme. Part (b) shows that the display is impruperly indicating 0 Hz.
FIGURE 3 - 71
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TROUBLE SHOOTING
Solution
•
165
Three possible causes arc
I. A constant acti ve or asserted level on the counter reset input. which kee ps the counter at zero. 2. No pulse si!;llal on the input to the counter because of an intemul open or shon in the counter. This problem would keep the counter from advancing after being re set to 7..ero.
3. No pu lse signal on the input to the counter lx'Cuuse of un open AND !!ate output or the absence of input si2nais. again keeping the counter from advancing from zero. The fi~t step is to make sure that Vee and ground are connecled to all the right places; assume Ihal they are found to be okay. Next, I.:heck for pul ses on both inputs to the AND gate. The scope indi..:atcs that there arc pm per pulses on both oflhcse inputs. A check o f the counter reset shows a LOW level which is known to be the unasscrt<:d level and, therefo re, this is not the problem. The next check on pin 3 of the 74LS{)8 shows Ihat there tire no pulses on the output of the AND gate, indicating thai the gate OUlput is open . Replace the 74LS08 Ie and check the operation again. Related Problem
i
If pin 2 of the 74LS08 AND gate is open. what indication shou ld you sec on the frequency d isplay?
EXAMPLE 3 - 26
The frequency counter shown in Figure 3- 72 appears to measure the frequency of input signals incorrectly. It is found thm when a signal wilh a precisely known
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166
•
lOG IC GATES
frequency is applied to pin I of the AND gme. the oscilloscope display indicates a higher frequency. Determine what is wrong. TIle readings Oil the screen indicate sec/di\'.
Solution
Related Problem
I
SECTION 3-9 REVIEW
Recall from Section 3- 2 that the input pulses were allowed to pass through the AND gate for exactly I s. The numbe r of pulses coullted in I s is equal to the frequ ency in hel1z (cycles per second). Therefore, the I s interval, which is produced by the enable pulse 0 11 pin 2 of the AND gate, is very critical to an accumle frequency measurement. The enable pulses are produced internally by a prec isic)Il o.'>Ci Ilator circuit. T he pulse must be exactly I s in width and in Ih is case it occurs every 3 s to updale Ihe count. Just prior 10 each enable pulse, the counter is reset to zero so Ihat it Slarts a new COU IlI each lime. S ince Ihe counter appears to be counting more pulses Ihall il should to produce a frequency readout that is 100 high, Ihe enable pulse is the primary suspect. Exact t i me~ interval measurements must be m:lde on the osci.lloscope. An input pul se waveform o f exactly 10 Hz is applied to pin 1 of lhe AND gale and the display incorrectly shows 12 Hz. The first scope measurement, on the output of the AND gate. shows that there are 12 pulses for each enable pulse. lnthe second scupe measurement, the inpul frequency is veri lied to be precisely 10 Hz (period = 100 illS). lnlhe third scope measure melli, the width of the enable pulse is found 10 be 1.2 s rather than 1 s. The conclLL~ion is Ihal the enable pulse is oul o f cal ibration roc some reaSOIl. What would you suspect if the readout were indicating a frequ ency less than it shou ld he?
1. What are the most <:ommon types of failures in IG7
2. If two different input waveforms are applied to a 2-input TIL NAND gate and the output waveform is just like one of the inputs, but inverted, what is the most likely problem7
3. Name two <:haracteristio of pulse waveforms that can be measured on the oscilloscope.
ANDS N
•
Proper grounding is very important when setting up to take measureme nts or work on a 6rc:uit Properly grounding the os6Uosoope protects you from shod<. and grounding yourself protects your 6r<:uits from damage. Grounding the oKilloKOpe means to <:onnect it to earth ground by plugging the three-prong power <:ord into a grounded o utlet Grounding yourself means using a wrist-type grounding strap, parti<:ularly when you are working with CMOS <:irwits. Abo, for accurate measureme nts, make sure that the ground in the drQJityou are testing is the same as the KOpe ground. This Uln be done by connecting the gJOund lead on the KOpe probe to a known ground point in the 6rcuit, su<:h as the metal <:hanis or a ground point on the <:irc:uit board. You can 0'110 connect the 6rCuitground to the GND ja<:k on the front panel of the s<:ope.
SU MMARY
•
1 67
Troubleshooting problems that are keyed to the CD-ROM arc available ;n the MuHisim Troubleshooting Praclice section of the end-of-chapter problerru..
•
The inverter oulput is the complemenl of Ihe inpul.
•
' lbeAND gale outpu t is HIGH only wilen a ll the inputs are HIGI I.
•
l be OR gale output is HIGH when any of lhe inpU ts is HIGI-I.
•
The NAND gatc oulput is LOW only when al! the inputs are HIGH.
•
The NAND call be viewed
11.\
a ncgmive-OR who:;c output is HIGH when any inpu t is LOW.
•
The NOR gatc outpu t is LOW when any of lhe inpuL~ is HIG H.
•
l loc NO R ean be viewed as II neglltive-AND whose ou tput is HIG H oilly when all the inputs are LOW.
•
TIle exclusive-OR gate Olitpul is HIGH when the inputs
•
The eltclusive-NOR gale output is LOW when the i n pul~ arc nol thc same.
•
Distinctive shape symbob and tmth tab les for in Figurc 3-73.
variou~
logic
gatc~
(limited to 2 inpUls) ilre shown
FtGURE 3-13
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0 I
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•
Most progmmmabk logic devices (PLDs) arc based 01\ somc fonn of AND a-ray_
•
Progrnmmable link technologics llfC fusc. an tifusc. EPROM. EE PROM. and SRAM.
•
A PLD Clln be programmed in a hardware fixture called a programmcr or mumtc
I
EAdusivc-NOR
•
PLJ>-, have an
•
Two mC lhods of design enlf)' us ing programming Sortware arc lext ell1 f)' ( I-IDL) and graphic (schemlltic) entry.
•
ISP PWs can be programmed after they are installed in a system.
•
JTAG stands for Join t TeSIAction Group and is an interfacc stundartl (IEEE Std. 11 49. 1) used for programming and testing PLDs.
•
An embedded proceSSor is used to fac iJitllle in-system programming of Pills.
•
CMOS is mllde with MOS licid-cffc(t traJl.~istOl's.
sort ware developlllCm package for programming.
16 8
•
lOG IC GATES
•
TTL is ma
•
As a rule, CMOS has a lower power consu mpt ion 1I111n 'ITL.
•
The a\'Cr"Jb'C power d issi pation of a logic gate is P o :; V(.'C
('= +2 '=)
• TIle speed-power product of a logic gate is
KEY TERMS
Key term~ and other bold terrru in the chapter are defined in the e nd-of-book gloslary. AND a rray An amiy of AND gates cOllsisti ng of a matrix of programmable AND gate A logic gate thaI
prod u c:e~
inten::on nection~.
a HIG H output only whe ll all oflhe illpl.lts arc HIG H.
Ant ifuse A type of PLO Ilonvolatile progra mmab le link that Ciln be leti open or call he shorlcd once as d irected by the program. Boolean a lgl'bra '111e milthematies of lugic dn;uits. Cr.'IOS Complcrncllttlry Il.etal-oxidc semiconduCtor; a c l ru;~ of integmted logic circuits that is implemenled wi th a type of ficld-cffect trans istor. Com plcment The inverse or opj)U'iilc of a number. LOW is the com plemcnt of HIG H, and 0 is the complcment of I. I<: I<:PROI\,I A type of nonvolatile PLD programmable li nk ba~ed on electrically erasable prognlnllnahie read,only mcmory ("ells and can be lurne
[PROM A type of PLD nonvolatile progrnmmable link based on electrically programmable read , OIlly memory n~ U s tmdcarl be tUI"I1I.:d ei ther on or 01T once wi th programming. f:xcl u~;\"e'.. OR
(XOR) g:lte A logic gate that prodUI."Cs a HIGH output onl y when
i l~
twn inpuls are
at opposite levels,
[xdllsh 'e-NOR gate A logic ga te that produccs a LOW only when the two in j:uts me at Clppollite levels. •'a n-oul The numbe r of eq uivalent gate inpu ts of the !X1me fami ly series thaI a logic gate can dri\·e. I:use A type of PLD 11011\'011l1ile prognunmablc link that can be left directed by the program.
~horted
or can be openoo once
a.~
Im'ere er A logic c ircuit tllll! inverts or complements its inpot . .lTAG Join t Test Action Group; an interface stalldard des ignatoo IEEE Std. 1149. 1. NANI) ga te A logic gll1c that produces a LOW oUlput only when aUlhe inpUis are HIG H. NOR gate A logic gate in which the output is LOW when onc or mofC of Ihe inputs arc HIGI-J. OR
g~le
A logic gate that produce:; a HIGH output when one or more in puts arc HIGH.
Prop ag;ll.ioll dela y lillle The time inten'
random-acces~
memory cellI; and
Target dClice A PLD mQunted on a progranunin g li xture or dcvelopmcnt homd inl0 whi ch a software logic des ign is 10 Ix: downloaded. Timill/;rl iagnull A diagram of wavefonns showing the proper timing relationship of all the wa\·cforms. Tmt.h tll ble A tahle showi ng the inputs and corresponding Olllput(S) of a logic c ircu it. rrL Transistor-Imnsistor logic; a class ofi ntegmted logic ciTClljL~ Itw.t U~ bipolar junction m lllsiMon>.
Uni t 1(l.IId A meru;u re ufflln-out. One ga te input reprc.\CIlts one unil load to the oUlput of 1I gatc within the same Ie fllm ily.
SelF-T EST
•
169
Answers
l. When the input to an invcrtcr is HI G H ( I). thc ou tpul is (a) HIGH or [
(b) LOW or [
(d) LOW orO
(e) HI G H orO
2. An im'Cl1er pcrfonns an operation known as (a) cumplemematiun
(b) a<;.Se rtiOll
(c) invers ion
(d) both answers (a) and (c)
3. The ou tput of an M'm gate with inputs A
OO A - l, B - I.C = 1
n, and C is a
I (HIGH) when
WA - Q8 - QC - O
~ A = I,8 = ~C - I
4. The output of an OR galc wit h inputs A 8, and C is a I (HIGH ) when
WA = I, B - I,C - I
~A = ~n - ~C = I
WA - RB = ~C = O
(e) only an~wers (II) and (h)
(d) answer!> (a). (b). and (c)
5. A pulse is applied 10 each input ofll 2- inpUl NAND gate. One pulse goes HIGH al t - 0 and goes hack LOW at t oo l illS. The other pulse goes H[G H at 1 "" 0.8 illS and goes back LOW at I - 3 ms. The Olltput pulse can be described as follows: (a) It goes LOW nr
t = 0 and hack HI G H OIt I = 3 ms.
(b) It goes LOW all -
u.~ m~
(el II goes LOW all - 0.8 ms and back HIGH al r - I illS. (d) [t goes LOW at I = 0.8 m.s and back LOW at 1 - I illS.
6. A pulse is applied 10 each inpu l of a 2-i nput NO R ga le. O ne pulse goes HIG H III t = 0 and goes back LOW at I = 1 ms. The other pulse goes HIGH at t - 0.8 ms and goes back LOW al I - 3 illS. The out put pulse can be described as follows: (ll) It goes LOW al t - 0 and hack HI G H at t = 3 nlS. (b) It goes LOW at t - 0 .8 ms and back HIG H al t = 3 m~.
(e) It goes LOW all = 0.8 ms and hack HI GH
(b) It goes HIG H 0\11 = 0 and bock LOW at (l'') [t goes HIGH at I
(d) boI h answers (b) and (c) i~ applied to an inverter. The time intcrval from the leading cdge of Ihe input to the leading edge of the output is 7 ns. This panuncter is
8. A positive-going pul!;C
(a) speed- power producl
(h) propagation del llY,
(e) propagat.ion dclaY,I,>UI
(d) pulse width
I I'HL
9. The purpose of
(e) disconnecl a row frOOl a column in Ihe affiI}' malrix (d) do all of the ahove
10. The tenn arr means (a) open lest poillt
(b) one-lime programmable
(c) output test progra m
(d) outlXl! lerminal posi tive
II. Types of PLD programmable link process technologies Me (ll) OIntifu sc
(1)) EEPROM
(e) ROM
(d) boIh (a) and (h)
(el bolh (a) and (c)
170
•
LOG IC GATES
12. A volati le programmable link leehnu logy is (a) fuse
(b) EPROM
(e) SRAM
(c1) EEPROM
13. Twu ways 10 cn ter a logic des ign using PLO development softwa re are (ll) text and numeric
(I)) tex t and graphic
(e) graphic and coded
(d) compile and SOIl
14. JTAG stands for
(a) Joint Test Ac ti on Group
(I) Java lop ArrllY
(e) Joint Te~ t Array Group
~d)
Group
Joint Time Anal)'si~ G roup
15. In-system programmi ng ofa PLO typicall y
Uli l i1.e~
(a) an em bedded clock generator
(b) an embedded processor
(e) an emhctldcd PROM
(d) both (a) and (b)
(e) both (b) and (c)
16. To measure the period of II pulse wa\'ef(mn, you must use (11) a OMM
(b) a logic probe
(e) an oscilloscope
(d) II logic pulser
17. Once you nlClIsurc the period of a pulse wavcfom l. the frequency is found by
PROBLEMS SECTION 3-1
(a) using another sellillg
(I) measuring the duly cycle
(e) fi nding the reciprocal of the period
(d) using another type of instnlment
Amwers to odd-numbered problem. are at the end of the book.
The Inverter I. The inpu t waveform !'.bown in Fi!'ure 3- 74 is IIpplied loan inverter. Or.IW the lim ing diag ram of the OUlput waveform in proper rclllliun tu tbe input.
FIGURE 3 - 74
HIGH
LOW
2. A network ofeascaded inverters is show n in Figure 3-75. If a HI GH is applied 10 point t\, de lenni ne the logic levels at points B through F. FIGURE 3 - 75 A
E
'-------1 :>O-- - F SECTION 3-2
The AND Gate 3. Dclelllline the output, X. fo r a 2-inpl.ll AND gate wilh the input w<\vefonns shown in Figo re 3-76. Show the pI"Oper relationship of oulputlo i llPU\.~ wi th II timing diagnllll. FIGURE 3 - 76
PROBLEMS
•
171
4_ Repeat Prob le m .1 fo r the waveforms in Fig ure 'J-77. FIGURE 3 - 77
A
8 5_ The in put wave fon ns nppl ie
6. The inpul wiI \'cforms ilPlllied 10 a 4-i npu t AND gate art:: a~ ind icated in Figure 'J-79. Show the
output wlwefonn ill proper relat io n FIGUR E 3 - 79
~ I I
.J : :: I
I
I I
I I
(0
the inpu ts wi th II timi ng diagram.
:: : L I
I I
I
-.lJiLln :~
)-x
~=tH=~'~'t~'J'=I'J' j'=j'= , ,
'
-.J SECTION 3 - 3
The OR Gate 7. Octennine the outpu t ror a 2-input OR gllle when the input wlwcfollllS arc as in Figure 3-77 a nd draw a ti ming d iagr.lm.
8. Repell t Problem 5 for II 3-input O R gate. 9. Repeat Problem 6 for II 4-input O R g;ne.
10. For the fi ve input wavefonns in Fig ure 3- 80. detenni ne the output for a 5-inpul AND gate iI.x1 the OU tput for a 5-inpul OR gale. Dr.lw the ti ming diagra m . FIGURE 3 - 80
"I
, ,
.
I
JJ,l_L' L'~~lt:tjtJ=~I I I
-i
Ii SECTION 3 - 4
•• I I
:
:
•• I
I
I
tt
I
,
'I
:~:r--;
I I
I I
I--f-+~·
I I
I I
' !
: H,----,-------,H : : H
I I
I I
'1
I
I
1 :
: 11
The NAND Gate II. For the SCI of input wavefonl1~ in Fig ure 3-8 1. dClen nine the output fo r the gate shown and draw the liming uiagrnm.
FIGURE 3 - '1
172
•
l O GIC GATES
12. Detennine the gate output for the input wavefomls in Figure 3-82 and drnw the timing di agram. FIGURE 3 - 8Z
A
"" rr' U rr "" '/l U ' ''"" ,U , "" "" '" '" ,, ""' ,, "'" , "" " '" """ " " I II
I
I I'
, ! ! ! ! ! ! !
" C
r !! r ! !! r
"
"" "" "" "
~3 )-x
13. I)etemline the outpu t waveform in Figure 3-83. FIGURE 3 - '3
A ....rTi
Ii C
-W ! !
i
I
. I
I ',
I
I
I
r
I
I
I
t---7----+--+---1
I
I
I I
I
-+--L-! :
D
ll
I
I
I
I
I
,
I
i
I
I
L..1...
I
I
I
~~x
D -~ -
L
.
14. As you ha ve Icarned. the two log ic symbols shown in Figure 3- 84 rc pl"CSCllt equivalent operations . The difference between the two is ~t r i ct l y from a func tional viewpoint. For the NAND symhol, 1001.: for two HIG Hs on the inputs to gire a LOW output. For the negativeOR, look for at least one LOW on the inputs to give a HIG H on the output. Using these two fu nctional viewpoims. show that each gale will produce the liiimc output for the given i npu L~ .
FIGURE 3 - 84 A IJ
SECTION 3 - 5
rTO I r--r--1"
I
I
I
-; I
I
I
I
r I
-,r-r--1rr-, I ~ r
I
I
I
I
A~_X II~
r
I
The NOR Gate
IS. Repeat Prohlem II for a 2-input NOR gate. 16. Determine the output wavefOnll in Figure 3- 85 and draw the timing diagram. FIGURE 3 - '5
~d
>--x
17. Repeat Problem 13 fIX a 4-input NOR gale. 18. The NAND and the Ilegative-OR symbols repfCSCnt cquivalelll operati ons, bUI they lI re functionally different. For the KOR symbol. 1001.: for at least one HIGH on the in pUis 10 gi\l! a LOW on theoul put. r or the negati\·c-AND, look for two LOW~ on the inputs to give II HIGH output. Using thc.~ IwO functional points of view, ~how that both gates in Figure 3-86 will produce the S
B
;=1::)-- x
PROBLEMS
SECTION 3 - 6
•
173
The Exdusive-OR and Exdusive-NOR Gates 19. How docs an exclusivc..()R galcdilTcrfrom an OR gate ill its logical operation? 20. Repeat Prob lcm II for an cllclusi\'c-OR gate. 2.1. Rcpeal Prob lcm II for an cXclusive-t\OR gale. 22. Determinc thc OlJlpm of an cxclusive-OR gale for lhe inputs shown in Figure 3-n and draw li ming diagram.
SECTION 3-7
II
Programmable Logic 23. In the simple programmed AND array wilh programmable links in Figure 3-87. deteoninc the Boolean out put clI prcssions. FIGURE 3 - 81
A
A
Ii
Ii
x,
x,
X,
24. Dctcnnine by row and column number which fusible links must be blown in the programmable At·m arr-
FIGURE 3 - 88
A
A
c
Ii
" ~.
2
• x,
',.
3 4
-
c
,
,
I,
...
5
,
•
r,
"
" .
6 7
"
"
"'
.
8
,
x,
h. 2
3
4
5
6
174
•
LOGIC GATES
SECTION 3 - 8
Fhted-Function logic 25. In the com parison of certain logic de\'ices, it i~ noted th ai the pov:er di ~si pation for one paJ1icular typl' increases as the frC
28. Gale A has ' ,'w = tNlL a higher freque ncy?
=:
6 ns. Gate B ha., t pw
= tPHL
= JO ns. Which gide can be operatcd at
29, If a logic gate operates on a dc su pply voltage of +5 V and drdws an average curre nt of 4 mA. wha t is its power dissipati on'! 30. The variable ICCH represen ts th e dc su pply cunenl from VC(' when all ou tpul~ of an Ie arc HIGH. T he \'a riable ICCL represents the de suppl y cun"CnI when aUoutpu ts are LOW. r'Or a 741.500 IC, determine the typica l power dissipatioll when all four gilt<: ou tputs are HIGH . (See dll la sheet in Figure 3- 65.)
SECTION 3-9
TroubleJhooting 31.
Ex~mine
the conditions indicmetl in Figure 3-90, and identify tlx! rau lly gates.
!~o
:==C)--o ,,)
,<)
,b)
(d)
:=c>-o ,,)
'0
FIGURE 3-90
32. Determi ne the faulty gates in Figure 3- 9 1 by anill)'"Ling the ti ming d iagroJns
JU1Jl.J"l ' ,,,
A
1.flf1.fu-
x~
A ~
A
H
IJ I"
11-+--1
Tm-i-tt-H
I I I I II , 1111111 11
X
B
,<)
,b)
FIGURE 3 - 91
----f1-.J I
I
L
'd)
PROBLEMS
•
175
33. Using an oscilloscope. you make the observations indicilted in Figure 3-92. For eilch obSCTv
FIGURE 3-92
Input ---'l~
Inpul - -"
GND
GND
(,)
(b)
34. The scat belt alarm circui t in Figll re 3-1 6 has malhul(;tioncd. You find thm when the ignition switch is IlImed on and the seat belt is unbuckled. Ihe alarm comes on and will not go off. Wh:ll is the most likel y problem? How do you troublesh()()( it'! 35. Every lime the ignit ion swi tch is turned on in the circuit of Figure 3- 16. the alllnll comes on for thirty seconds, even when the SCllt belt is buckled. What is Ihe moSI proVable cause of Ihis malfunction? 36. Whlll failurc( s) would you suspect if the output ofa 3-inpUl NAND gale slays HlG H no matter what Ihe inputs me?
176
•
lOG IC GATES
Special Design Problems 37. Sensors are used to mon itor the pressu re and the tempe ratu re of a c hc lllical solution stored in a vat. The circuit ry for each se nsor produccs a HIGH vohage when a sJlcdfied maximum v~! l uc is exceeded. An alarm requ iring a LOW voltage inpu t must be acth 'llted when eit her the press ure or the temperat ure is excessive. Design ,I c ircu it for this application.
38. In a certain !lutnmate
FIGURE 3-93
41. Design a circuit 10 fit in fhe beige block of Figure 3-94 fhllf wi ll Clll1.SC fhe headli ghts of all automobile to be turned off aulOmmica ll y 15 saff er the ignitio n switc h is fumed off, if the light switch is leff 011 . Assume thm a LOW is r'eqllil'C d tn lum the lights off.
FIGURE 3-94
Ignition switch Lighl SWilCh
42. Modify the logic ci rcuit for the intnlsion alarm in Figtll'C 3-24 so that fwO rHkli tionallooms, cneh with 111'0 windows ;l[](1 one door. can be protectc<1. 43. Further mod ify the logic circuit fmm Pmblern 42 for a change in the input sensors where Opcn '" LOW and Closed = HIGH.
Muilliim Troubleshooting Practice 44. Open file 1'0344, co nn ecl fhe Mu ltisim logic eOlwerter to the circuit, and ob.scf\'e the opcrntion of the AN D gale. Based on Ihe obsc n 'Cd inputs and Output, detcnn ine the most likel y fault in th e gate. 45.
Op.~n file 1'03-45. co nnect the Multisi m logic converter to the ci rcuil. and observe the opera tion of the NA ND gale. Based on the observed inputs and output, dctcnnin e the most likel y fau ll in th e gate.
46. Open file POJ·46, conncct the Multisim logic cOIwerler to the cirUl;t, and observe fhe openuion o f the NOR gale. Based on the obscrl'cd inpu ts and output, determine th e 1Il000t likely fault in the gate. 47. Open fi le P03-47. connect the Multisim logic eOlwerter to the circuil, and observc the opcrntioll of the exclusive-OR gate. Based on the obscn'c d inpul~ and output. determ ine the most likely f:lull in the gale.
ANSW ERS
•
177
SECTION REVIEWS SECTION 3-1
The Inverter L. Whcn thc invcrtcr input is I, the out put is O.
2. (a)
(b) A ncg'divc-going pulse is on thc output (HIGH to LOW and back HIGH).
SECTION 3-2
The AND Gate I. An AND gatc OUlpu t is HIGH onl y when all inputs are HIGH. 2. An AND gatc output is LOW whcn onc or more inputs are LOW. 3. Five- inpu t AND: X = I whcn ADCDE = 1111 1. and X = 0 for all other combinations of ADeD£.
SECTION 3-3
The OR Gate I. An OR gate oulput is HJOH when one or more in puts arc I-UGH. 2. An OR gate output is LOW only when a\l inpu ts are LOW. 3. Three-input OR: X = 0 when ABC = 000. and X = I for all other combi nations of ABC.
SECTION 3 - 4
The NAND Gate I. A NAN D outplll is LOW only when all inputs are HI01-l. 2. A NAND output is !-IIOl-! when one or mOTC inputs are LOW_ 3. NAND: acti ve-LOW outptlt for all HIGH inputs; negative-OR: acti \'e- l-Il0ll output for OlleOf more LOW inputs. T hey have the slIInc tnl th tables.
4. X = ABC
SECTION 3-5
The NOR Gate I. A NOR outpu t is I-UGI-I only when all inputs arc LOW.
2. A NOR outpu t is LOW whell one or mme
inptll~
,u'e HIGH.
3. NOR: octin:-LOW ou tpu t foron c or more I-UGH inputs: ncgati\'c-AND: acti vc-HIG H OlItput for all LOW inputs. They ha\'c thc samc tMh tabl es. 4. X = A + 8 + C
SECTION 3-6
The Exclusive-OR and Exclusive-NOR Gates I. An XOR ou tput is HIGH when thc inptlts arc at opPOSitc Ic\'c ls. 2. An XNOR output is HIG H when the inpu ts are at the same le\d~. 3. Apply thc bilS
SECTION 3-7
10
the XOR in puts; whcn the output is IIIGH, the bits arc diITcrcnl.
Programmable logic 1. Fuse, an tifusc, EPROM, EEPROM, (lnd SRAM 2. Vo/"tiJe means that all the claw arc lost when power is off and the PLD muSl be reprogrn mmcd; SRAM-based
178
•
l OGIC GATES
3. ' Iext t:nt l)' and gr-'Iphie entry 4. JTAG is Joinl 'lest Action GrOLlp: the IEEE Std , 1149. 1 for prognunming an d lest inlt:rfacing.
SECTION 3 - 8
Fixed-Function logic 1. CMOS and TIL 2. (a) lS-Low-power Schollky
(Il) ALS--Advanccd LS
(c) F- fasiTIL
(d) HC-High-speed CMOS
(t~)
(I) HCf- IiC CMOS TIL compatible
AC-Ad\'anccd CMOS
(g) LV- Low-voltage CMOS
3. (a) 74LS04-Hex inverter
(b) 74HCOO-Quad 2-input NAND
(c) 74 LV08-QUild 2-inpul AND
(d) 74ALS IO-Triple J-i nput N/\ND
(e) 7432- Quad 2-inJXlt OR
(f) 74ACT I I- Triple J -in pUl AND
(I;) 74AHC02-Qu;!{/ 2-input NOR
4. Lowest power-CMOS 5. Si",- inverter.; in a package: four 2-inpul NAND gates in a pack
8. lca.- dc supply cl1rrent for LOW output slate: ' ('o,-
9. V/L-LOW input
~ ol tage:
V,,,-HlGH input vollage
10. VOI. -LOW outptJtl'oltage: VOIr-I-IIGI-1 output voltage
SECTION 3-9
Troubleshooting I. Opens and shorts are [he l1lOSI 001l11ll0fl
fil il ure~.
2_ An op::n input which effecti vely makes input HIGH
3_ Amplit ude and period
RELATED PROBLEMS FOR EXAMPLES 3-1 The ti ming di agram is not affected. 3-2 Scc Table 3- 13.
TABLE 3- 13
INPun ABCD
OUTPUT X
INPUn ABCD
OUTPUT X
0000
0
\{XXJ
0
0001
0
1001
0
0010
0
1010
0
0011
0
1011
0
0 100
0
I J(Xl
0
0101
0
1101
0
0110
0
111 0
0
0 111
0
1111
ANSWERS
3-3 Sec fi gu re 3-95.
A~
FIGURE 3- 95
H
lJ -' ,
U ,
H
H
! ! H
H U , ,L ! ! ! H
LL.LJ
,
,
I
!
~
~
I
,
I
X -.J~L
3-4 ·Ihe ou tput w,l\'eform is the same as inpUl A. 3-5 St:c Figure 3-'JO. J....6 See Figure 3-97.
A
"
A~
x
B
c
,
n
FIGURE 3 - 96
... FIGURE 3 - 91
3-7 See Figure 3-')8.
3-8 Sec Figure 3- 99.
X
C=LOW FIGURE 3-9.
FIGURE 3-99
3-9 St:e Figure 3- 100. 3-10 See FigufC 3-10 1.
--fUl-fl-fUl. -j Ii I I
A
X
IL '
I
xs---u--L
C=lUGH
I
I
I
I
U
FIGURE 3 - 100
I
I
... FIGURE 3 - 101
•
179
18 0
•
LOGIC GATES
3-11 Usc a 3-inpul NA ND gate. 3-12 Usc a 4-i nput NAND gale opcrnling as a negative-OR gale. 3-13 See Figure 3- 102.
FIGURE 3 - 102
==
A-fl --t-t-.
B
i i I
I
u
:I
, v-1, C
X
nt,
U.--------l-:-I i ; Ur
I
I
I
I 1-----,U .---
,, uT1 ,, I
I
IS
' 'C- - - - -
iJ
U
3-14 Sec Fig ufC 3- 103. 3- 15 Sec FigufC 3-104.
A~
X
, ,
~
B
U_:_~ , ,
c
_----.lHL_ _
X __
FIGURE 3 - 103
.. FIGURE 3 - 104
--'HL__
3-16 Usc a 2-input NOR gate. 3-17 A 3-inpul NAND gate. 3-IR The {llitput is always LOW. The liming diagrntn is a stra ight line. 3-19 The cl(clusiu.:-OR gale will !l()t deicci sa me oulpu tS.
~illlul tancoliS
failures if both circuils prorluec lhe
3-20 Thc OIliputS arc unaffected. 3-21 6 columns, 9 rows,
" 'ilL
can operate at the highest frequency.
3-23 IOmW 3-24 The gate OUlplll or pin 13 input is inlclTlal ly open. 3-25 The di splay will show an eml tie readoLi t because the COllntcr continucs unti l reset . 3-26 TIIC enable pulsc is too
~hort
or the .::ountcr is reset 100 soon.
SELF-TEST 1- ((\)
2. (d)
3. (a)
4. (e)
5. (e)
6. (a)
7. (d)
8. (b)
10. (b)
II. (d)
12. (e)
13. (b)
14. (a)
IS. (d)
16. (c)
17. (e)
9. (d)
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION CHAPTER OUTLINE
4-'
Boolean Operation~ and Expressions
4-2
uws and Rules of Boolean Algebra
4-3 4-4 4-5 4-6
DeMorg,m's Theorems Boolean Analysis of logic Grcuib
Simplification Using Boolean Algebra
Standard Forms of Boolean Expressions
4- 7
Boolean Expressions and Truth Tables
4- 8 4- 9
The Ka rnaugh Map
4-10 4- 11 4-12
Karnaugh Map pas Minimization VHDl (optional)
I:III
Digital System Application
KoJrnaugh Map SOP Minimi~ation Five- V.ni3ble Karn
•
CHAPTER OBJECTIVES
INTRODUCTION
Apply the balic lilWt and rules of Boolean algebra Apply Dt:Morgan's theorerm to Boolean expreSiiom Del.cribe g;ate netVlOrkl with Boolean el
Convert rn,,"'gh map to limplify truth table f... nctions Utilize -don't C.-:lre condition! to limpljry logiCfunctionl H
In 1854, George Boole publi.hed a work titled An inve$tigation of the Laws of Thought, on Which Are Founded the Mathematical TheodeJ of Logic and Probabilities. It was in this publication that a "logical illgebra," known to(by ilS Boolean algebra, was formulated. Boolean algebra is a convenient and systematic way of expressing and analyzing the operation of logic circuib. Claude Shannon ~. the first to apply Boole's work to the analysis and design of logic circuits. In 1938, Shil nno n wrote a t hesis at MIT titled A 5ymbolic Analysu of Relay and 5witching Circuits. This chapter covers the laW), rules, ilnd theorems of Boolean algebra ilnd their application to digital circuits. You will learn how to define a given circuit with a Boolean expression ilnd then evaluate its operation. You will illso learn how to simplify logic circuib u~ing the methods of Boolean algebra and ~r"",ugh maps. The hard~re description language VHOl for programming logic devices is introduced.
Write a VHDl prog...m fO!' simple logie Apply Boole.. n "Igebr", the K..m .....gh ""'P method, "nd VHDl to a !)'Item application
KEY TERMS
VMiable
Product-of-sums (POS)
Complement
~rnaugh
5um term
MinimiUltion
Product term
-Don't care"
Sum-of-producb (50P)
VHDL
map
•••
DIGITAL SYSTEM APPLICATION PREVIEW
The Digital 5Y'tem Application iUu1tratcs concepn taught in thi.! chapter. The 7-iegment display logic in the tablet counting ilnd control l)l'ltem from Chapter I is a good way to il/u1tTate the application o f Boolean algebra and the ~rnaugh map method to obtain the limplest possible implemenbtion in the de'ign of logic circuits. Therefore, in this digital system application, the focus is on the BCD to 7-~gment logic that drives the two system di1pla)"l shown in Figure 1- 58.
Study aids for this chapter are available at http://www.prenha U.comlfloyd
183
18 4
•
4 -1
BOO LE AN ALG EBRA AND LOG IC SIM PLIFI CATION
BOOLEAN OPERATIONS AND EXPRESSIONS Boolean algebra ;s the mat hell\atic~ of digital systems. A basic knowledge of Boolean algebra is indispensable to the STudy and analysis of logic circuits. In the last chapter, Boolean operations and expressions in terms of their re lationship to NcrI', AND, OR, NAND, and NOR gales were introduced. After completing this section, you should be able to _ Define \'tlri/JJle _ Define literal - Idcntify a sum term _ Evaluate a sum term _ IdentiFy a product term _ Evaluate a product term _ Explai n Boolear, addition • Explain Boolean mulli plicat ion
In ... micro prou:nor, the .... it hmetic logic unit (ALU) performs .uithmetic ... nd Boole.-n logic oper... tiom o n digital data OIl directed by progr.lm imtructiom. Logical operatiom .-re equival ent to the oos;c gOlt e operatiom lh... t you are familiOlr with but dea l with a minimum of 8 bib at a time. Examples of Boolean logic imtructiom are AN D, OR. NOT, and XOR. \>Alich
I
The O R gate ;.1 a Boolean adde r.
Variable, complemell1, and lireml are ten us used in Boolean algebra. A variable is a symbol (usually m l italic u ppcrca~e leUer) used to represent a logical quamity. Any single variable can have a I or a 0 vailic. '1l1C oolllllJemenl is the inverse of a variable and is indicated by a bar over the variable (overbar). For example, the complement of Ihe vuriable;\ is A. If A = I, lhen A= O. If;\ = 0, then A= I. Thel.'omplelllc nt of Ihe variable;\ is read as "nol A" or "/l bar." Sometimes a prime symbol mlher than an ovcrbar is used to denote the complement of a valiable; for example, B' indicates the complement of B. In this book, only the overbar is used. A literal is a variable or Ihe complement of a variable.
Boolean Addition Recall from Chapler 3 thai Boolean addition is equivalent 10 the OR operalion and the basic rules are illuslmled with Iheir relation to the OR gale as follows: 0+0 = 0
0 + 1= 1
1 +0 = 1
1+1 = 1
QJQJQJQJ In Boolean nlgebm, a sum term is a sum of lilemls. In logic circui ls. asum term is produced by an OR
I
EXAMPLE 4-1
Detemline the values of A. B, C, and D that make the sum tenn A + [j + C + D equal toO. Solution
For the sum tem 10 be 0, each of the literals in Ihe term must be O. 111erefore, A = U, lso lhal B = O,C = U.and D = I so that D = O.
n=
A + B + C + D = U + I ~ O + I = O + O + O + O = O
Related Problem ~
Determine the \'aluc.~ of A and B that make the sum term ' A nswers nrc 111 Ihe end of the chapter.
A + B CQualto O.
LAWS AND RULES OF BOOLEAN ALGEBRA
-
185
Boolean Multiplication Also recall rrom Chapter 3 that Boolean multiplication is eCluivale ntlo the AND operation and the basic rules are illustmted with their relation to the AND gate a" rollows:
The AND gate is a Boolean multiplier.
In Boolean algebrd, a product (erm is the product of literals. In logic circu its, a prodllct term is produced by an ANQ operation w ~h ~ OR operations involved. Some examples of product tenns are /l B, AB, /l BC. and ABCD. A product term is equal to I only if each or Ihe literals in the term is I . A product term is equHI to 0 when one or mOle o r the literals are O.
Determine the vHlucs or J\, /3, L: nnd D that make the product term /lBeD equal to I . Solution
For the product ~"tTl to be I , each or the literals in .Q.Ie term must be I. Thererore, /I = 1, /3 Osothat /3 = I, C = I, Hnd D = 0 so that D l.
=
=
ABeD = 1·0 · 1·0 = 1·1· 1·1 = 1 Related Problem
I
SECTION 4-1 REVIEW Amwell ;:Ire
<:hopter.
4- 2
Detennine the "Hlues or A and B that make the product term A B equal 10 I.
1. If A = 0, wn
AeqU
2. Determine the values of A. B, and C that make the sum term A
+
B + C equal to O.
3. Determine t he values of A, B, and C that make the product term ABC equal to , .
LAWS AND RULES OF BOOLEAN ALGEBRA
As in other areas of mathematics, there are cenain well-dcvelope
laws of Boolean Algebra The basic laws of Boolean algebra-Ihe commutalive laws ror addition and Illultiplication. the a.. . . . ociali\·e law5 for addition
186
•
BOOLEAN ALGEBRA AND LOG IC SIMPLIFICATION
same as in ordinary algebra. Each of thc laws is illustrated with two orthree variables, but the number of variables is nOi limited to this. Commutative Laws
Equation 4-1
The (:omnm/Cllj,le lall' uf mldilioll for two variahles is written a"
A+B = B + A
This law states that the order in which the variables are ORed makes no differencc. Rerncmocr, in Boolean algebra as applied to logic circuits, addition and the OR opef""dtion arc the same. Figure 4- 1 illustrates the commutative Jaw as applied to the OR gate and shows that it doesn't matter to which inpul each variable is applied. (The symbol == means "equivalent to.") FIGURE 4-1 J\
Application of commutative Jaw of addition.
~_._.
H~
1+8
==
B
~. __ .
A ~
B+A
The cOlI/mllln/h·e law ojmlllliplic(l/ioll for two variables is
Equation 4- 2
AB = BA
This law states lhaltheorder in which the variablcs are ANDed makes nodiffercncc. Figure 4-2 illuslmtcs Ihis law as applied 10 thc AND gate. FIGURE 4 -2
Application of comlTll.ltative law of multiplication.
The associative law ofa(/(/;lioll is wliUcn as follows fOI" three variables:
Auodative Laws
Equation 4- 3
A +(B +C) = (A+B) + C
·Ih is law states that when ORing more than two variables, the result is the same regardless of the grouping of the variables. Figure 4-3 illustrates this law as applied to 2-input OR gates. FIGURE 4 - 3
Application of ;mociatNe lilW of addition. Open file f04-03 to verify.
: ~ ~-t-CH-t-C) _ A ~ A+B
; ~ (A+8)+C
c =L)J B+C
The associative law oj multiplication is wriUen as follows for three variables:
Fquation 4- 4
A(BC)
~
(AB)e
This law states thm it makes no difference in what order the variables arc grouped when ANDing more than two variables. Figu1"C 4-4 ill ustrates this law as applied 10 2- inpllt AN D gates. FIGURE 4-4
Application of 3110ciatNe law of multiplication. Open file F04-O'l to
A-- -- " H
- - r_____
C -
-
-L-'/
A~ '"
;
AB)C
Distributive law The distribulive law is writtcn for tlnee variables as follows:
Equation 4- 5
A(B ;- C)
=:
AB
+ I\C
LAWS AND RULES OF BOOLEAN ALGEBRA
•
This law SW\CS thm DRing two or more variablcs and then ANDing the rcsult with a single variable is C(juivalent to ANDing the single variable wit h each of the two or more variables and then DRing the products. Thc distributive law also expresses thc process of factoring in which the common variable A is factored oul of the product tcrms, for example, AR + AC = A(B + C). Fi gurc 4-5 illustrates Inc distributive law in terms of gate implementation.
, - -r___
FIGURE 4 5
Applica tioo of distobutive taw. Opeo file f{)4...()S to verify.
X = A8+AC
X:A(lJ+O
Rules of Boolean Algebra Table 4- 1 lists 12 basic mles thm arc useful in manipulating and simplifying Bo()lean expre...~ i()m;. Rules I through 9 wiU be viewed in tcrms of thcir application to logic gates. Ru lcs 10 through 12 will be derived in terms ofthc simpler n llcs and the laws previously discussed. TABLE 4- 1
7. A·A = A
I.A+O = I\
2. A
+
8.A
1= 1
9.A =
3.1\·0 = 0
BilSK: rules of BooJeilo i1 lgebril.
A=O A
4.A· 1 = A
IO.I\ + AB = I\
5.A+A = A
II . A + AB = A+B
6.A +A = 1
12. {A + B)(A + C) = A + BC
Rule 1. A + 0 = A A variable DRed wi th 0 is always equal co the variable. If Ihe input variable A is I , thc output vru·iable X is I, which is equal to A. If A is 0, thc output is 0, wh ich is also equal to A. This rule is ill ustrated in Figure 4-6, where the lower input is fi xed at 0.
A=0 =1>o
... FIGURE 4 - 6
x=o
X=A+O=A
=
Rule 2. A + 1 1 A variable DRed with 1 is always cqual lo I. A 1 on an input CO an DR gatc produccs a I on the output, regardless of the value of the Variable on the other input. This rule is illustmted in Figure 4- 7. where the lower input is fixed at 1.
A=',=1>-
X=1
,.0=1>x= ,
X=A+l=t
FIGURE 4 - 7
t
18 7
188
•
BOOLEAN A LGEBRA AND LOG IC SIMPLIFICATION
Rule 3. A ·0 = 0 A variable ANDed witll 0 is always equa l to O. Any time one input to an AND gate is 0, the output is 0, regardless of the value of the variable on the o ther input. This rule is illustrated in Figure 4-8, where the lower input is fixed at O.
FIGURE 4 - '
A='o =O-
x",o
'=0o --r--'\ --L.J- -
x=:o
Rule 4. A . 1 = A A variable ANDcd with I is alw.JYs equal to the vari:Ible. If A is 0 the output of the AND gate is O. If 1\ is I, the output of the AND gate is I ix.-'(ausc both inputs are now Is. This rule is shown in Figure 4-9, where the [owa- inpul is fixed at I.
FIGURE 4 - 9
.=0,=0-
X:=O
A=',=O-
x:]
X=: A· I =: A
Rule 5. A + A = A A variable ORed with itse[f is always eqllal lo the variable. If A is 0, then 0 + 0 = 0; and if 1\ is I , then I + I = I. This is shown in FigufC 4- 10, where both inputs are the same variable.
FIGURE 4 - 10
A=' =O-
X",I
11= I X = II +11 = 11
Rule 6. A + A = 1 A variable ORed with its I.:omplement is always equal to 1. If A i ~ 0, tbenO + O = O lo l = I. U1\ is I, then I + 1 = I + 0 = I. See Figure4- 11, whereone input is the complement of the other.
FIGURE 4 - 11
A=0 =O-
11=1
X=I
_ =O- x= A='
,01=0
I
Rule 7. A . A = A A variable ANDcd with il<;elf is always equal 10 the variable. Lf A = 0, men 0·0 = 0; and if A = I, then J . I = I. Figurc4- 12 illustrates this rule.
FIGURE 4 - 1Z
A=0=O- x=o A_' A='=O-
A=O
X = A ° 11 = ,01
X=I
LAWS AND RULES OF BOOLEAN ALGEBRA
•
Rule 8. A . A = 0 A variable ANDed with ils complement is always equal to O. Either A or A wi ll always be 0: and when a 0 is applied to the input of an AND gate. the output will be 0 also. Figure 4- 13 illu"trates this rule.
."_ =0- x'" A=O
A.0=O_
0
A=J -
FIGURE 4 _ 13
X:: O
\' = A · \ = 0
Rule 9. A = A 'Ille double complemenl of a variable is always equal to the variable. If you slart wilh Ihe variable A and complement (invert) il once. you gel A. If you then take A and complement (invert) it. you gct A. which is the original variable. This rule is shown in Figure 4- 14 using inverters. FtGURE 4 - 14
rl = A
Rule 10. A + AB = A rule 4 a" follows: A
+ AB
This mle can be proved by applyi ng the distributive Jaw, rule2. and
~
A( I + B)
Factoring (distributi ve law)
=
A· I
Rule 2: ( I + B) = I
~ A
RuJc4:A'I = A
The proof i" shown in Table 4-2, which shows the tmlh table and the resulting logic circuil simplification.
A
I
0 0
S
AS
,
0 0 0
0 0
I
:£PA-====;-
A +AB
0 0
!
~! rnigh!
~-qu31
Rule 11. A A
t
+ AB = A + B This rule can be proved as follows:
+ AB = (A + AB) + AB = (AA + AB) + AB
Rule 10: A = A + AB Rule 7: A
:=:
AA
= AA+AB+AA+AB
Rule 8: adding M = 0
~ (A
Factoring
+ A)(A + B)
~ '· (A + B)
= A+B
Ru le 6: A + A = Ru le 4 : drop the I
conn(..c!i
TABLE 4-2
Rule 10: A + AB - A. Open file TM-02 to verify.
189
190
•
BOOLEAN ALGEBRA AND LOG IC SIMPLIFICATION
TIle proof is shown in Tablc 4-3, which shows the truth table and the resulting logic cirellit si mplification. TABLE 4 - 3 A
Rule l1:A +A8 = A + 8. Open fil e T~-O] to -.erify.
o
o
o
J
o
o
o
o
o o
Rule 12. (A + B)(A + C) = A + BC This ru le can be proved as follows: (A
+
B)(A
+
+ AC + AB + Be + Ae + AB + Be
Distri butivc law
C) = AA
= A =
~
+ AB + BC
A( I .,. C)
= A· I
+
RllIc7:AA = A
+
AB
Factoring (distributive law) Rule 2: I
Be
A( J + B) + BC
+
C = I
Factoring (distributivc law )
+B
= A· I + Be
Rule 2: I
= A + Be
Rulc4:A- 1 = A
= I
T he proof is shown in Table 4-4. which shows the truth table and the resulting logic circuit simplilicalion.
TABLE 4 - 4
Rule 12 : (A
0 0 0 0
0 0
0 J
0
+ 8)(A + C) =
A+B
A+C
0 0
0 J
0
A
(A+Bj(A+C)
0 0 0
BC
A+8C
0
0 0
0 0
J
0
0
0 0 0
0
t
SECTION 4 - Z REVIEW
0
J
0
j
+ Be. Open file T01-04 to \'efify.
equal
t
-, 1. Apply the auodative law of addition to the expression A 2. Apply the distributive law to the expression A(B
+C
+ (8 + C + oj.
.1- 0).
OEM ORGAN'S THEOREMS
4- 3
•
191
DEMORGAN ' S THEOREMS
DcMurg.m, a malhe matician who knew Boolc., propnscd iwo Theorem.. That are an important pan of Boolean algebra. In pmetical (enns. DeMorgan's theorems provide mathematical verifi cation of the equivalency of the NAN D and negative-OR gates a nd the equivale ncy of the NOR and negative-AND gatc.~ , which were discussctl in Chapter 3.
A rter completing this section, you should be able to • Stme DcMorgan's theorems - Rclme DeMorgan's theorems to the equivalenc y of the NAND and negative-OR gatcs and to the equivalency of the NOR and negative-AND gale!'> • Apply DeMorgan's thcorem~ 10 the s implifi cation of Boolean expressions
One of DcMo rgan's theorems is sla ted as follows:
The complement of a product of variables is equal to the sum of the complements of the variables. Sialed another way. The complement oftw() or more ANDed variables is equivalent to the OR of the comph'me nls of the individual \'ariables. The fonnula for expressing Xy = X
+
thi .~
theorem for two variables is
Y
Equation 4- 6
DcMorgan's second theorem is stated as follow s: The complement of a sum of vmiables is equal 10 the product of the complements of the \'a riables. Stated another way.
The complement of two or mOl't ORed variables is equivalent to the AND of the complements of the individual variables, 111e formu la for expressing thi s theorem for two variables is
X
+
y=
Xy
Equation 4--7
Figure 4- 15 shows the gale equiValencies and IIUlh tables for Equations 4-6 and 4-7. fiGURE " - I~
Inpub
X ,. =D--
XY _
-
-
XYXYX+Y X ~
_
y ~ x+Y
N AN D
o o
Ne~mive· OR
0 I
I
I
o
o
Inputs
I
I
I I I
o
Outpu~ _
XYX+YXY
x~ I ~ X+I ' =
NOR
Output
o o Nel!",ivc' A ND
0 I
o
I
o o o
I
o
o o
GOlte equivOl len(i~ .,nd the corresponding buth tablel that iUUltrOlte DeMorg.,n'l theorems. Notice the equality of the two output (:olumnl in e."h tab le . Thil IhOWl that the equivall:'nt gates pl:'rform thl:' lame logk function.
192
•
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
As stated, OcMorgan 's theorems also apply to expressions in which trere are more than two variables. The following examples iUustmte the application of OcMorgan 's theorems to 3- variablc and 4-variable expressions.
I
EXAMPLE 4-3
Apply DcMorgan's theorems to the expressions xrz and X
+
Y + Z.
XYL = X + Y +Z
Solution
X + Y+ Z=X Y Z Related Problem
I
Apply DeMorgan's theorem to the expression X
+ Y + Z.
EXAMPLE 4-4
Apply OcMorgan's theorems to the expressions lVXl'Z and W
Solution
X
+
Y + Z.
lYXY2 = lV + X + Y + Z W+ X
ReltJted Problem
+
+
Y ,. Z = lVX YZ
Apply OcMorgan's theorem 10 thc cx pression lVX YZ.
Each variable in DcMorgan's theorems as stated in Equations 4-6 and 4-7 can also represent a combinmion of other variables. For example, X can be equal to the tCl111 AB + C, and Y can be equal to the lenn A + BC So if you can apply DeMorgan's Iheorem for two variables as stated by XY = X + Y 10 the expression (A B + C)( A + BC), you gCllhe fo llowing result:
(A B + e)(A + Be)
~
(A B + e) + (A + Be)
Notice thai in the preceding result you have two terms, AB + C a nd ~ + BC, to each of which you can again apply DeMorgan's theorem X + Y = Xl' individ ually, as follows:
(AB + e) + (A + Be) ~ (AB )e + A( Be) Notice that you slill have two terms in thc expression to which DeMorgan's theorem can again be opplied. Thc.,>e terms are liB and BG. f\ fina l opplieation of DcMorgon's theorem
gives the follow ing result:
Although this re.-mlt can be si mpl itied fUlthcr by the use o f Boolean rule.<; and laws, DeMorgan's theorems cannot be used any more.
Applying DeMorgan's Theorems The fo llowing procedure illustrates the application of DcMorg nn's algebra fo the specifie expression
A
t heor~ ms
and Boolean
+ BC + D( E + F)
Step I. Identify thc tcrms to which you call apply DeMorgan's theofCms, and think of each term as a sing le variable. Let A
+
Be = X and D( E
+ F)
= Y.
DEMORGAN'S THEOREMS
Step 2. Since X
+ y=
•
XY.
(A + Be) + (D(£ + F))
~
(A + BC)(D(E + F))
Step 3. Use rule 9 (A = A) locanccl the double bars over the left term (this is not pru1 of DeMorgan's theorem).
(A + BC)(D(E + F)) ~ (A + BCH D(E + F)) Step 4. Applying DcMorgan's thcorem lo the second term,
(A + BC)( D(E Step 5, Usc rule 9
(A
(A =
+ E))
~ (A
+ BC)(D + (E + F))
A) to cancel the dou ble bars over the E +
+ BC )(D + E + FJ
~ (A
F part of the term.
+ BC)(D + E + F)
TIle following three examples will further illustrate how to II SC DcMorgan's theorems.
I
EXAMPLE 4 - 5
Apply OcMorgan's theorems to each of the following expressions: (a)
Solution
(A + B + C)D
(b)
ABC
+ DEF
(a) letA + B + C = X and D = Y. Thcexpression (A XY = X + Y and can be rewriuen a'l
+
(A
B
+ C)D
+ CD + EF
(c) AB
= A
+
+B+
B + C)Disofthe form
C
+D
Next, apply DcMorgan·s theorem to the term A + B
+
C.
A + B + C + D = A B C+ D
(b) Lei ABC =_~ and DEF = Y. The expression ABC X + Y = X Y and can be rcwriUen as
+ DEF is orlhe form
Next, apply OcMorgan's theorem to each oflhe terms ABC and DEF.
(c) Let AB = X. CD = !:,~ ~d EF = Z. The expression All fo nn X + y + Z = X Y Z and can be rewritten as AB
+
CD
+
+ CD + EF is or ille
FF ~ (AB)(CD)(EF )
Next, apply DeMor~an's theorem to each of the terms An, CD, and £ F.
Related Problem
Apply DeMorgan's theorems to tile expression ABC + D
+
E.
193
194
•
BOOLEAN A LGEBRA AND LOGIC SIMPLIFICATION
i
EXAMPLE 4-6
Apply DeMorgan's theorems to each expression: (a) (A
Solution
B)
+C
+ il ) + CD
(b) (A
(c)
(A + 8)C I) + E + F
(aJ
(A + B) + C "" (A + B)C = (/\ + 8 )C
(b)
(A + il ) + CD ~ (A + B)eD ~ (AB)(C + 15) ~ AB(C + 15)
(e) (A
Related Problem
+
+
B)CD
+
E
+
F ~ «A
+
il )C /J)(E
+ F)
Apply DcMorgan's theorems 10 the expression /\B(C
~
(AB +
+ I) +
C
+
D )EF
E.
The Boolean expression for an exclusive-OR gate is AR + liB. With this as a starting point, use DcMorgan's theorems and any other rules or laws that are applicable to develop an expression for the exd usive-NOR gale. Solution
Start by complementing the exclusive-OR expression and then applying theorems as follows: AB
+
Ail ~ (AS)( A8 ) ~ (A
DcM0f!:~ an 's
> 8)(A + S) ~ (A + B)(A + Ii)
Next, apply the distributive law and rule 8 (/\ . A = 0).
M + AB + A 8 + BB = AB + All The linal expression for the XNOR is All + AB. NQ(e that this expression equals I (.4 + 8)(A +
B)
=
any time both variables are Os or both variables arc Is.
Related Problem
I
SECTION 4 1 REVIEW
4-4
Starti ng with the expression for a 4-input NAND gate. use DcMorgan's Iheorem:-> to develop an expression fo r a 4-input negative-OR gate.
1. Apply DeMorga n'~ theo rem~ to the (ollowing C)(pressiom:
(a) ABC + (0 + E)
(b) (A + B)C
(e) A ..--c +'B'+o-rC + DE
BOOLEAN ANALYSIS OF LOGIC CIRCUITS Boolean algebra provides a concise way to express the operat ion ofa logic circuil formed by a combination of logic gates so thm the output can be determined for various combinations of input values. After completing this section, you should be able to • [)etcrmine thc Boolean expression for a combination of gates . EvaJuaie the logic operation of a circuit from the Boolean expression . Construct a ((uth table
BOOLEAN ANALYS IS OF LOGIC CIRCU ITS
•
19 5
Boolean Expression for a Logic Circuit To derive the Boolean expression for a given logic circuit, begin at the left-most inputs and work toward the tinal OUlpUI, writing Ihe expression for each gate. For the example circuit in Figure 4-16, the Boolean expression is determ ined as fo llows:
A logic circuit Ciln be described by a Boolean equation.
I. T he expressio n for the left-most AND gate with inputs C and D is CD. 2. The outpllt of the Ieft-mosl AND gale is one of the inputs to the OR gate and B is the other input. Therefore, Ihe expression for the OR gate is B + CD. 3. The output of Ihe OR gale is one o f the inputs to the right-most AND gale and A is the other input. Therefore, the expression for thi s AND gale isA(n + CD). which is the final output expression for the entire circuit.
C
- --r-----.
,, -
FIGURE 4 - 16
-L_/
A logic circuit showing the development of the Bool~n expression for the output
" - - - - -L.-' ,\W +
('I))
Co nstructing a Truth Table for a logic Circuit Once the Boolean expression for a given logic circuit has been detemlined. a truth table that shows the OlltPlit for all possible values of the input variables can be developed. The procedure requires that you evaluate the Boolean expression for all possible combinations of vailies for the input variables. In the case o f' the c ireuit in Figurc4- 16, there are four in4 pUI variahl e.~ (A , n, C, and D) ,lnd therefore sixleen (2 = 10) combinations of value!: arc possible. Evaluating the Expreuion To evaluate the expression A(B + CD), firsl lind the values of the variables that make the expression equal to I . using the rules for Boolean addi tion and multiplication. In this case, the expression equals I only if A = I and B + CD = I because 11(8
+ CD)
= I .I = I
Now determine when the n + CD term equals I. The tenn B + CD = J if e ither B = I or CD = I or ifboth B and CD equal I because B + CD = I +O= I B+CD = O + I
B + CD = I + I = The term CD = I onlyifC= I andD = I. To summarize. the expression A(B + CD) = I when A = I and n = I regardless of the values of C and D or when A = I and C = I and D = 1 regardless o f Ihe value of B. The expression A(B + CD) = 0 for all other value combinmions of the Variables. Putting the Results in Tndh Table Fomwt The IIrst step is to list the sixteen input variable combinations of I s and Os in a binary sequence as shown in Table 4~5. Next. place a I in the output r.:olumn for each combination of input varillbles that was determined in the eva luation. Finally, place a 0 in the output column for all other combinations of input variables. These results are shown in the Iruth table in Table 4-5.
A logic circuit CCln be described by a truth table.
196
•
BOO LE AN ALGE BRA AND LOGIC SIMPLIfiCATION
TA BLE 4 - 5
Truth t"ble fo r the legit: circuit in Figure 4- 16.
INPUTS ABC
D
0
0
0
0
0
I
I
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 0
0
0
0
0
0
I
0
0
0
0 0 0
0
0 0
I
SECTION 4 - 4
REVIEW
1. Replace the AND gates with OR gates and the OR gate with an AND gate in Figure 4- 16 and determine the Boolean expression fo r the output 2. Construct a truth table for the circuit in Question 1.
4-5
SIMPLIFICATION USING BOOLEAN ALGEBRA Many times in thc application of Boolean algebra, you have to reduce a particular expression 10 its simplest form or change its form to a more cOJlvenicnt o nc to implcment thc exprc...sion most cfficient ly. The appro.1e h laken in this section is 10 use the ba..ic laws, m les, and Iheorems of Boolean algebra 10 manipli iale and simplify an expression. 'Ib is mcthod depends on a thorough knowledge o f Boolean algebra and considerable practice in its appiicalion. nol 10 mention a lillie ingenuity and cle\'cme.~s . After completing this section. you should be able 10 • Apply the laws. rules, and thcorcms of Boolcan algebra to simpli fy gencral cxpressions
A simplified Boolean expression uses the fcwest gates possible 10 implemcnt agivcn expression. Examples 4-8 lhrough 4- 11 il lustrate Boolean simplification.
SIMPLIFICATION U SING BOOLEAN ALGEBRA
I
•
1'J7
EXAMPLE 4-8
Using Boolean algebra techniques, simplify this expression: AB
Solution
+ A(B + C) + B(B +
C)
The followi ng is nOlnecessarily Ihc only approach. Step I:
Apply UIC distribulive law to Ihe second and third terms inlhe e)(pression , follows: AB
Step 2:
ll.~
+ AB + AC + nn + DC
Apply rule 7 (BB = 8) 10 the founh Icml.
AB + AB +AC+ B + BC Step 3:
Apply rule 5 (AB
+ An
= An) to the first two terms.
AB + AC+ B + BC Step 4:
Apply rule 10 (B
+ BC =
B) to the last two terms. AB + AC + B
Step 5:
Apply rule to (AB +
n=
8) to the first and third terms.
n +AC At Ihis point the expression is simplified as much as possible. Once you gai n cxperience in applying Boolean algebra, you can o ften combine many individual steps.
Related Problem
Simplify the Boolean expression AB
+ A(B + C) +
Figure 4--17 shows thai the simplification process in Example 4--8 has significantly reduced Ihc number of logic gales required to implemenllhe expression. Part (a) shows thai five gates arc required to implcmenllhe cxprcssion in its original form ; however, only two gates are needed for the simplified cxpre..;sion. shown in part (b). II is impOitant to realize that these two gale cireuits are e
MI + AlR+ Cl + filii + CI
n
8+ \('
,I - - r--, C(,)
-L-'
t
FIGURE 4 - 17
Gate orcl1ib for Example 4-8. Open fife F04-17 to ve rify e
(b)
B(B
+ C) .
Simplification means fewer gates for the ~me function
198
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BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
I
EXAMPLE 4 - 9 Simplify the following Hooletln expression:
[AB( C + BD ) + ABl C Note that brackets and parenlhescs mean the same Ihing: Ihe tenn inside is mulliplied (ANDcd) with the tenn outside. Solution
Step 1: Apply the distri butive law to the terms widli ll the brackets. (ABC + ABBD + A B) C Step 2:
Apply ru le 8 (liB = 0)
\0
(ABC Step 3:
Ihe second term within the parentheses.
+ A-O·D +
AB)C
Apply rule 3 (A · 0· D = 0) to the sl.:cond term wi thin the parentheses.
(ABC + 0 + AB)C Step 4:
Apply rule I (drop the 0) within the parentheses.
+ A B)C
(ABC Step 5:
Apply the distri butive law.
+ ABC
ABce Step 6:
Apply rule 7 (CC = C) to the first term. ABC
Step 7:
Factor out
+ A BC
lic
BqA + A) Step 8 :
Apply rule 6 (A
+ A = 1). BC· I
Step 9:
Apply rule 4 (drop the I).
Be Related P,oblem
Simplify the l300lcan expression [A B(e
+
BU)
+ AB le D.
Simplify the following Buule'lIl expression: ABC' Solution
+ AB C + A B C + ABC + ABC
Step I: Factor Be oul of the first and last lerms.
Step 2:
BC(A + A) + ABC + ABC + ABC Apply ru le 6 (A + A = l) 10 the lerm in parentheses, and factor All from the second and last lerms. BC· 1 + AB(C
+ C) + ABC
SIMPLIFICATION USING BOOLEAN ALGEBRA
Step 3 :
Apply rule 4 (drop the I) to the first tenn and rule 6 term in pun::nthc.-.:cll.
C = I ) to the
+ AB ·l + ABC
BC Step 4:
(C +
•
Apply rule 4 (drop the I) to the second term.
BC + AB + ABC Step 5:
Factor B from the second and third terms.
BC Step 6:
Apply rule II (A
+ AC =
+ B(A + AC) A
BC Step 7:
I
EXAMPLE 4
+ B(A + C)
Use the distributive alld com mutative laws to get the following cxprclision:
BC
Related Problem
+ C) to the term in parentheses.
Simplify the Boolt:i\n cxp~.~~iun
+ AIi + BC
/lBC + ABC + ABC + ABC.
11
Simplify Ihe following Boolean expression:
AB Solution
+ AC + ABC
Step I:
Appl y OcMorgan 's theorem to the first term.
Step 2:
Apply DeMorgan's theorem to each term in pl.Ircntheses.
(A + B)(A + C) + ABC Step 3: Apply the distributive law to the two terms in parentheses.
AA + AC + AB I· BC +A BC Step 4;
Apply ru le 7 (A A = A)
lAB + ABC
=
(0
AO( I +
the firslterm, and apply rule to
C) =
AB] to the third and last lemu;.
A+AC + AB + BC Step 5:
Apply rule 10 [/\
+ AC
=
A( I + C)
=
AJ 10 the lirst and second lerm~.
A.+AB+BC Step 6:
Apply rule 10 (A
+ Ali
=
A(I + Ii) A +
Related Problem
Simplify the Boolean expression AB
=
AI to the first and second terms.
Be
+ AC + A B e.
199
200
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BOOLE AN ALGEBRA AND LOGIC SIMPLIFICATION
I
SECTION 4 - 5 REVIEW
1. Simplify the follOlNing Boolean expressiom if possible:
(a) A + AB + ABc
(b) (A
+ B)C + ABC
(e) ABc(BD + CDE) + AC
l
2. Implement each expression in Quertion , as originally stated with the app ropriate logic gates. Then implement the simplified expression, and compare the number of gates.
4-6
HANDARD FORMS OF BOOLEAN EXPRESSIONS All Boolean expressions. regardless of their form . can be converted into either of two stulldard fomlS: the sum-of-produel<; form or the produet-of-sums form. Standardi-/.3tion makes the evaluation, simplificatio n, lind implementat ion of Boolean expressions much more systematic and easier. After completing this section. you should be able to - Identify a sum-of-produets expression - Dctennine the domain of a Boolean expression - Convert any sum-of-products expression to a standard form - Evaluate a standard sum-of-products expression in terms o f billary values _ Ident ify a product-ofsums expression - Convert any product-of-sums expression to a standard fonn • Evaluate a stand:mf product-of-sums expression in tenns of binary values - Convert from one standard form to the other
The Sum-of-Produ..u or more ANDs.
A product te0l1 was defined in Section 4- 1 as a term consisting o f the pmduct (Boolean multiplication) o f literJ.ls (variables or their complements). When Iwo Of more produet terms arc summed by Boolean addition. Ihe resulting expression is a 5lnn-of-products (SOP), Some examples are
+ IIBC IIBC + CDE + BCD liB liB
+
ABC
+ AC
Also, ,Ill SOP expression can contain a single-V'driable tenn, as in A + ABC + BCD. Rcfer to the simplification examples in Ihe lasl sl.:clion, and you will sec that eadl of the final expressions was either a single product tcnn or in SOP fon n. In an SOP expfCssion. a single overbareannot extend over more than one variable; however. more than one variable in a term c
The domain of a gcneral Boolcan expression is the set of variables contained in thc expression in ei.!..hcr cOIlJllemented or uncomplemented form. For example. thc domai n of the expression An + IIBC is thc sel of variables II, B, C and the domain of the expression ABC + CDE + BCD is the sct of variables II, B. C, D, E.
Implementing iln SOP expression simply requires GRi ng the outputs of two or more AND gates. A product tCt1n is produced by an AND operation, and the sum (addition) of two or more product terms is produced by an OR operation. Therefore, an SOP exprcs~ ion can be implemented by AND-OR logic in which the outputs of a number (equal to the number of product terms in the expression) of AND gatcs connect to the input.~ of an OR gate, as shown in Figure 4- 18 for the expression AB + BCD + Ae. The output X o f the OR gate equals the SOP expression. AND/ OR Implementation of all SOP fxpreJlion
STANDARD FORMS OF BOOLEAN EXPRESSIONS
.. FIGURE 4 - 11 1/ Ii
c
f)
Implementation of the SOP expression AB + BCD + AC
-L-.-/
- -r-,
L-<""____
-
r -<-/
-L_/
X :,W+/KV+ -K
NAND/NAND Implementation of U/1 SOP &prcjJjon
NAND gates can be used to implement an SOP expression. Using only NAND gates. an AND/OR runction can be accomplished, as illustrated in Figure 4- 19. The first level of NAND gates reed into a NAND gate that acts as a negative-On gale. The NAND and negalive-OR inversions cancel and the resu ll is effectively lin AND/OR circuit. FIGURE 4 - 19
... --r----." Ii
- --i._ -"
11
- --1----..
( f)
X: \IJ + 11(,1> + ,\('
---i._-"
Thil NAND/NAND imptemenbtion il equivatent to the ANDIOR in Fig\lte 4-18.
Conversion of a General Expression to SOP Form Any IOFic expression can be changed into SOP form by applying Boolean algebra tcchniques. For example. Ihe expression A(B -I- CD) can be converted 10 SOP form by applying the distributive law: A(B -I- CD) = AB
+ ACD
i
EXAMPLE 4-12
Convert each or the folluw ing Boolean expressions to SOP rorm :
SolutiO/1
(a) AB
+ B(eD + EF)
(u) An
+ B(CD + EF) = + B)(B + C + D)
(b) (A (e)
Related Problem
(A +
(b) (A
+ B)(B + C + D)
+ BCD + BEF AB I- AC + AD + BB
~==--c
(e) (A -I-
AB
=
... BC
+ BD
Bl + C = (A + BlC = (A 'BlC = AC + BC
Convert ABC
+ (A
-I-
8)(B
+ C + AB) to SOP form .
The Standard SOP Form So far. you have seen SOP expressions in which some or the product terms do not contain all of the variables in the domain or thc expression. For example. the expression ABC + ABO + ABeD has a domain made up of the variables A, B, C. and D. However, notice that the complete sct of varia~es in the domain is no( represented in ~e fi rst two terms of the expression: that is. D or D is missing from the first teml and Cor C is missing from thc second lerm . A SWill/art! SOP expressioll is one in which all thc variables in the domain appear in each product Icrlll in Ihe expression . For example. ABeD + ABeD + ABeD is a standard SOP expression. Standard SOP expressions arc important in constructing truth tables. covered in Section 4--7, iUld in the Kamaugh map simplification method, which is covered
B) + C
•
201
101
•
BOO LE AN ALGEBRA AND LOG IC SIMPLIfi CATION
in Section 4- K Any nonstandard SOP expression (referred to simply a<; SOP) can be converted 10 the standard form using Boolean algcbra.
Converting Product Terms to Standard SOP Each product tenn in an SOP expression that docs nOi contain a ll the vllriables in the domain can be expanded to standllrd fonn to include all variables in the domain and their complcments. As stated in the following steps, a non st ~dard SOP cxpression is converted into standard form using Boolean a lgebra rule 6 (A + A = I ) from Table 4- 1: A variable added to its complement equals I .
Step 1. Multi ply each nonslandard product Icnn by a tcrm made up of the sum of II missing variable and its complemcnt. This results in two prod uct terms. As YOll know, you can mulliply anythi ng by I without changing its value. Step 2. Repeat Slep I until all resulting produclterms contain aU variables in the domai n in either complemented or uncomplemcnted form. In converting a product term to standard form, the number of product terms is doubled fo r each missing variable, as Example 4- 13 shows.
I
EXAMPLE 4-13
Convert the following Boolean expression into standard SOP fom}: ABC
Solution
+ A B + ABCD
The do,!!ain of this SOP expression ~ A, B. C, D. Take one tem at a ti me __Thc fin-I lerm , ABC, is missing variable IJ or D, so multiply the fi rst (erm by D + D a<; follows: ABC = ABC( D + D) = ABCD
+ ABCD
In this case, two stan~a.!:1 product tcrms arc the res1::!.t. llle second tenn. l2.B. is missing variables Cor C and Dol' D. so fi rst multiply the second tenn by C + C as fo llows: A B = AB( C + C) = ABC The J)
+
+ ABC
I ~O
J)
rcsulti n2 tcrm~ arc missing variable D or V , so multiply both terms by as follows:
+ ABC( D + D) + ABCD + A B CD + ABe D
AB = ABC + ABC = A eC( D + D ) = ABCD
In th is ca.\c, four stan'!..an:l prod uct terms arc the result. The third (crm. ABeD, is already in standard form. The complete standard SOP form of the original expression is as follows: ABC
+ ,\ B + ABCD
Related Problem
=
ABCD + ABeD
Convert the expression WXY
+ A BCD + A BCD + ABeD
+ .KIT +
-I-
ABeD + ABCD
WXY to standard SOP fonn .
Binary RepYeJentatiOll of 0 Standord Product Tenn A standard product term is cqua/ Lo ) for only one combination of variable values. For example, the product term ABCD is equal to I whcn A = I . B = 0, C = I, D = 0, as shown below. and is for all othcr combi n ali on ~ of values for the variables.
°
ARCD = \ ' 0· 1· 0 = 1· 1· 1· 1 = I In Ihis case. the producl lerm has a binary value of 10 10 (deeimallen). Remember. a product tenn is implemented with an AN D gate whose OUlput is I only if each of its inputs is I . Invel1ers are u'iCd to prod uce thc compieme nl<; of the variables a<; requ ired.
An SOP expression is ellUal to I only if one or more of the product ter m!'! in the expression is equal to I.
STANDARD FORMS OF BOOLEAN EXPRESSIONS
i
•
203
EXAMPLE 4 - 14
Determine the binary valucs for which the following standard SOP expression is cqualto I: ABCD
+ ABeD + ABeD
The term ABCD is eqllalto 1 whcn A = I. B = I. C = I. and D = 1.
Solution
ABCD - I·I· t · I - ]
The term ABeD is equal to 1 whcnA = I. B = O. C = 0, and D = 1. ABeD = 1·0·0·1 = \· 1· 1· 1 = 1
The lermABCDisequal lo \ when A = D. B
= D. C =
O. and D
= O.
ABeD = 0·0·0·0 = I· 1· 1·1 = I
The SOP cxprcssion equals 1 when any or all of thc three product lenns is I. Determine the binary values for which the following SOP cxpression is equal to I:
Related Problem
XYZ
+
Xyz
+
Xyz
+
Xyz
+
XYZ
Is this a standard SOP expression'?
The Product-oF-Sums (POS) Form A sum term was dcfined in Section 4- 1 as a tcrm tonsisting of the sum (Boolean addition) of litcmls l variables or their complements). When two or more sum temlS are multiplied. the resulting cxpression is a proouct-of-sums (JlOS). Somc cxamples arc
(, + B)(A + Ii + C) (A + Ii + C)( C + 15 + £)(ii + C + D) (A + B)(A + Ii + C)(A + C)
e
A pas cxpression can contain a singlc-variablc tcrm, as in A(A + B + C)(B + + D). In a POS cxpression. a singlc ovcrbar cannot cxtcnd over more than one variablc; hov.-·cver. more than one~ari;~le il.!...a teml can have an ovcrbar. For example. a PUS expression can have Ihe term A + B + C butnot A + B + C. Impleme/1tatlotl of a POS 6pression
Implementing a POS expression simply requires ANDing the outputs of tWO or morcOR gatcs. A sum tcnn is produced by an OR operation. and the prod uct of two or more sum terms is produced by an AND operation. Therefore, a POS expression can Ix:: implemcnled by logic in which the outputs of a number (equal to thc number of sum terms in the expression) of OR gates COllnCCltO the inputs of an AND gatc, as Figure 4-20 shows for thc expression (A + 8 )(B + C + D)(A + C). 111C output X of the AND gate equals the PUS expression .
... FIGURE 4 - 20
B -....-~
C /J -
-L..-'
.,
--r~
C
- -L--,
Implementation of the POS expression (A + B)(B + C + D)(A
+ C).
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BOO LE AN ALGEBRA AND l OG IC SIMP LIf iCATIO N
The Standard POS Form $0 far, you have seen PUS expressions in which .~omc of the sum terms do nOI eomain all of the variables in the domai n of the expression. For example. the expression
(A
+ Ii + C)(A + B + D)(A + Ii + C + D)
ha.~ a domain made up o f the variables A. B. C, and D. Notice Ihat the complclc sel of V'
(A +
Ii + C + D)(A + Ii + C + D)(A + B + C + D)
is a standard POS expression . Any nonstandard POS expression (referred tosimply as POS) can be converted to the standard fonn using Boolean algebra. Converting a Sum Tenn to Standard POS Each sum tcml in a POS expression that doc.~ nol contain all the variables in the domain can be expanded 10 standard fon n to incl ude all variables in the domain and their complements. As staled in the following steps, a nonstandard POS expression is converted into standard tom using Boolean algebra rule 8 (A . /\ == 0) from Table 4- 1: A variable multiplied by its L'Q mplemem equals O. Step I. Add 10 eaeh nonstandard prod uct lerm a term lIlade up of the product of the m issi ng variable and its complemcnt. Th is res ults in two sum terms. As you know, you can add 0 to anything wi thout changing its value. S tep2. Apply rule 12 from Table 4-1: A + Be == (A
+ B)(A
Step 3. Repeat Step I un til all resulting sum terms contai n in either complemented or uncomplemented forlll.
Convcl1 the follow ing Boolean expression imo standard
(A + Solution
I· C)
an variables in the domain
pas form:
n + C)(B + C + D)(A + n -I- C + D)
TIle domain oflh is !lOS expression is A, B. C. D. Take one term aI a time. 1bc fi rst lelm, A -I- B -I- C, i~ missing variable IJ or D. SO add DD and apply rule 12 as follows:
A+
8+
C = A -I- Ii
The second teml, rule I::! as follows:
n -I-
-I-
C
C + DD
+ 0,
=
(A + Ii + C + D)(/i. +
n + C + u)
is missing variable A or A, so add All. and apply
Ii + C + D = Ii + C + D -I- AA = (A + Ii + C -I- D)(A -I- B -I- C + D) The third teml. 1\ -I- B + C -I- D, is already in standard forlll. TIle standard POS form of the original expression is as follows: 0+B + q~+C + ~0+j+C + ~ -
0 + i + c + ~0 + i + c + ~0 + i + c+~~ + Ii+c'~0 + Ii +c +~ Related Problem
Convert the expression (A -I- B)(B
+ C) \0 slandard
POS form.
Binary Representation of 0. Standard Sum Tenn A standan:l sum lenn is cqUlII 10 0 for only one combination of variable values. r'Orexample. lhe sum term A -I- Ii + C + D is 0 when A = 0, B = I. C = 0, and D = I. as shown below. and is I for all other combinations of values for the variables.
A+B + C + D = O-l- T + o +T = o+o + o + O = O
STANDARD FOR MS OF BOOLE AN EXP RESSIONS
•
In this case, the ~u m tcrm ha.~ a binary value of 010 1 (decimal S). Rcmember, a sum term is implemented wi th an OR !!ate whose uutput is 0 only if each of its inputs i:;; O. InvCl1ers are us(:d to produce I.he complements of the variables as required.
A POS expression is equal to 0 only if one or more of the sum tnms in the expres..·!ion is equal to O.
I
EXAMPLE 4-16
Determine the binary values of the variables for which the followi ng standard POS expression is cqual to 0: ~+B + c+~~+i + ~ + ~~ +j+~+~ Solution
The tenn A + B + C + D is equal to 0 when A = O. B = O. C = 0, and D = O.
A + B + C+D = O+ O+ O+ O= O ThctcrmA + B + C + D is C
=:
I,and D = I.
A + B +C + D = I + I + I + I=O + O + O + O = O The POS cxpression equals U when any of the Ihree sum terms equals O. Related Problem
Determine the binary values for which thc fo llowing POS expression is equal to 0:
(X + Y + Z)(X + y + Z)(X + Y + 2)(X + Y + 2)( X + Y +
Z)
Is this a standard POS cxpression?
Converting Standard SOP to Standard POS The binary values of lhe product lerms in a given standard SOP expression arc not present in the equivalent standard POS expres!.ioll. Also, the binary values that are not represcnted in Ihe SOP expression are present in the equivulent POS eXIJrcssion. Therefore. to convert from standard SOP to standard POS. the following steps UIe taken: Step I. Evaluate eaeh produCI term in (he SOP expression. Thai is, determine the binary numbers that represent the product terms. Step 2. Determine all of the binary numbers not included in the evaluation in Step I. Step 3. Write the equivalent sum (eml for each bi nary number from Step 2 and express in POS foml. Using a similar procedure. you can go from POS to SOP.
I
EXAMPLE 4-17
Convert [hc following SOP expression to an equivale nt POS expression:
ABC + ABC + ABC -I Solution
ABC + ABC
The evaluation is as follows: 000 + 010 + 0 11 + 101 + III Since there arc three variables in the domain of thi s expression, there are a total of eight (2 3) possible combinat ions. The SOP expression contains fi ve of thesc combinations, so the POS must contain the other three which are 00 1, 100, and 11 0.
20 5
206
_
BOOLEAN ALGEBRA ANO LOGIC SIMPLIFICATION
Remember, these are the bi nary values that make the sum tenn O. The equivalent POS expression is
(A + B + C)(A + B + C)(A + Ii + C) Related Problem
I
SECTION 4 - 6 REVIEW
Veri fy that the SOP and POS expressions in this example arc equivalent by substituting binary values into euch.
,. Identify each of the following expreu;om a~ SOP,
~tandard
SOP, POS, or ltandard
P05:
(a) AB + ABD + (e) ABC + ABC
.lieD
(b) (A + jj + C)(A + B + C) (d) A(A + C)(A + BI
2. Convert each SOP exprenion in Question 1 to standard form . 3. Convert each POS expreuion in Question 1 to standard form.
4-7
J
BOOLEAN EXPRESSIONS AND TRUTH TABLES All slandard Boolean expressions can be easi ly converted inlO truth table formal using binary values for each term in the:- expression. The truth table is a comlllon wuy of presenting, in a concise format, the logical operation of a circuit. Also. siandard SOP or pas expressions can be determined from a truth table. You wi ll find truth tables in data sheets and other literature related to the opcmtion of digital circuits. After completing this section. you should be able to - Convert a standard SOP ex pression into truth table format - Convert a standard pas expressi on into truth table fo rmat - Derive a standard expression from a truth table - Properly interpret Iruth lable data
Converting SOP Expressions to Truth Table Format Recall from Section 4- 6 that an SOP express ion is equal to I on ly if at least one of the product ICons is equal 10 I. A truth table is simply a lisl of the possible combinatio ns of input variable values and Ihe eorres{Xlnding outpul values (lor 0). For ml expression wit h a domain of two variables, there arc four differe nt combinaliolls of those variables (2 ~ = 4). For an expression with a domain of Ihree variables. there arc ei~h l di ffere nl combi nations of those variables (2 3 = 8). For an expression with a domain of four variables. there arc sixteen di fferen t combinations of those variables (2~ = 16), and so on. The firsl step in conslnlcting a Iruth table is to list all possible combinations of binary values of the variables in the expression. Next, convert the SOP expression to standard form if it is nOi already. Fi nally, place a I in the output column (X) for each binary value Ihat makes the standard SOP expression a I and place a 0 for all the remaining binary values. This proc-ed ure is illustnlled in Example 4- 18.
BOOLEAN EXPRES SIONS AND TRUTH TABLES
Develop a truth table fOr the standard SOP expression Solution
•
ABC + ABC + ABC.
There are three variables in the domain. so there are eight pos~ible combinations of binary values of the variables as listed in the left three columns o f Table 4--6. The £!~ry values...!~t make the product temlS in the expressions cqualto I arc ABC: 00 1; AB C: 100; and ABC: 111 . For each of these binary values, place a 1 in the outp ut column a'l shown in the table. For each o r the remaining binary combi nations, place a 0 in the output column.
TABLE 4 - 6
INPUTS ABC
o o o
o o
o
o
1
1
o
o o
o
o o
OUTPUT X
PRODUCT TERM
ABC
o o o
o ABC
Related Problem
Create a truth table for the standard SOP expression ABC
+ ABC.
Converting POS Expressions to Truth Table Format Recall that a POS expression is equal 10 0 only if at lea."t one of the sum terms is equal to O. To (.'Onstruct a tru th table from a POS expression, list al.1 the possible combinations of binary values o r the variables just as was do ne for the SOP expression. Next, convert the POS expn:ssion to standard form if it is not already. Finally, place a 0 in the outp ut column (X) for each binary value that lllakcs the expression a 0 and place a I for all the remaining binary values. This procedure i~ illustrated in Example 4- 19.
I
EXAMPLE 4-19
DcteOlli ne the truth table fOr the follOWing standard POS expression:
0+ B + q0+i + q0+i + ~~+B+~0 + i + q Solution
There are three variables in the do main and the eight possible binary value.~ are listed in the left three columns of Table 4-7. The binary values that make the sum terms in ~e exprcs~on cqual loi! arc~ + B + C: (0); A + 8 + C: 010: A + B + C: 0 11 ; A + B + C: 101 ; and A + B + C: 110. J-or each of these binary values, place a 0 in the output column as shown in Ihe table. For each of the remaining binary combinations, place a I in the output column.
207
208
•
BOOLEAN ALGEBRA AND LOG IC SIMPLIFICATION
TABLE 4 - 7 INPUTS
.
i
ABC
0
0
0
0
0
X
I
SUM TERM
0
0
(A+ IJ +C)
0
0
(A + 11 + C)
0
(A ·I B + C)
0
(1i + B -t- C)
0
(A + Ii + C)
0 0
OUTPUT
0
0 0
Notice that the truth table in this example is the same as the one in Exam ple 4- IK This means that the SOP expression in the previous example and the POS expn:ssion in Ihis example are equivalent.
Related Problem
Develop a truth table for the followin g standard POS expression:
(A + B + C)(A + B + C)(A + B + C)
Determining Standard Expressions from a Truth Table To determine the standard SOP expression re presented by a truth table, li st the bina/)' values of the input variables for which the output is I . Convert each bi nary value 10 the correspondi ng product term by replacing each I with the l.'Orresponding variable and each 0 with the conesponding variable wmplemcnl. f'Or example. the binary vmue 1010 is converted 10 a product term ns follows: 1010 ------).
ABCD
If you substitute. you can sec Ihal the product (erm is I:
ABCD =
1·0·1·0 = I · I · I · I = 1
To determine the standard POS expression represented by a truth table, li st the bimlry values fOr whieh the output is O. Convert each b inary value to the corrcspond ing sum term by re placing each I with the corresponding variable complement and each 0 with the corresponding variable. For example. the binary value 100 1 is eonverled to a sum terIll as follows: 100 1
~
A
+ B+ C+
I)
If you substitute, you can sec thai the sum tenn is 0:
A + B + C + D = 1+0 + 0 + 1 = 0 + 0 + 0+0 = O
i
EXAMPLE 4 20
From the tru th table in Table 4-8, determine the standard SOP expression and the equivalent standurd POS expression.
BOOLEAN EXPRESS IONS A ND TRUTH TABLES
•
TABLE 4_' A
INPUTS 8
C
o
o
o
o
o o
o o o
OUTPUT
o
X
o
o
0
o
I
o
o
Solution
There arc four Is in the output column and the corresponding binary values are 01 1. 100. 11 0. and I I I. Convert these binary values 10 product lemlS as fo llows:
oII
-----'I-
l OO _
ABC ABC
I IO _
ABC
III -
ABC
The rc:,;ulting standard SOP t:x pl"Cl;:,;ioH for the output X il; X = ABC
+ ABC + ABC + ABC
For the PaS expression, the output isO for bi nal)' values 000. 00 1. 010, and 10 1. Convert these binary values to s um terms as fo llows:
OOO ----+ A + B + C 001 ------)0 A + B + C 010 _ A + B+ C 101 The resulti ng standard
----+ /\ + B
+
C
pas expression for the output X is
X - ~ + B + q~ + B +~ ~ + j + q ~ +B + ~ RehJted Problem
I
SECTION 4-7 REVIEW
By ~ u bsti t u li o n of binary values. show thai the SOP and the POS expressions derived in this example arc equivalent : thai is, for any binary value they should either both be 1 or both be O. depending on Ihe binary value.
1. If a certain Boolean expression has a domain of five variables, how many binary values will be in its truth table? 2. In a certain truth table, the output is a 1 for the binary value 011 O. Convert thil binary va lue to the corresponding product te rm using variables VI, X, Y, and Z. 3. In a certain truth table, the output is a 0 for the binary value 11 00. Convert this binary value to the corresponding sum term using variables VI, X, Y, and Z.
209
2 10
•
BOO LEAN A LG EBRA A N D LOGI C SIMPLIFICATI ON
4- 8
THE KARNAUGH MAP A Kama ugh map provides a systematic method for simpl ifying Boolellll expressions and, if properl y used. will produce the simplest SOP or POS expression possible, known a" the minimum expression. As you have seen, the effectiveness of algebraic simplification depends on your familiarity with alJ the laws, rules, and theorems of Boolean algebra and on your ability to apply them, The Kanmugh map, on the other hand. provides a ··cookbook" method fOr simplifi cation. After completing this section, you should be able to • Construc t a Kar naugh map for three or four variables _ Determinc the binary value of each cell in a Karnaugh map _ Determinc the standard product term re presented by each cell in a Karnaug h milp - Explain cell aqiacency •.IIld identi fy adja(;ent cells
The purpose of
A Karn8ugh map is similar to a truth table because it presents all of the possible values of input variables and the resulting output for each value. Instead o f being organized into {;olumns and rmvs like a tmth table. the Kamaugh map is an army of (.-ells in which each cell reprcscnts a binary value of the input vuriables. The cel ls are arranged in a way so thnt simplification of a given expres.<;ion is simply a malter ofpropcrly grouping the u:lIs. Kamaugh maps ean be used forexprcss ions with two, three, fo ur, and live V'
The 3-Variable Karnaugh Map The 3-variable Karnaugh map is an array of eight cei1 s, as shown in Figure 4-21(a). In this ca'ie, A, B, and C arc used for the variables although other 1ctte~ could be used. Binary values of A and B arc along the left side (notice the sequence) and the values of C are acro.'iS the top. The value of a given cel l is the binilry values of A and B at the left in the :.ame row combined with the value o f C at the top in the :.ame column. For exall1ple. the cell in the upper left corner has a binary value of 000 and the cel l in the lower rig ht com er has a binary value of 101. Figure 4-21{b) shows the standard product terms that are re presented by each cell in the Karnallgh map. FIGURE 4 - 21
A 3-v<1riable Ka ma ugh map shol.viog
C All
pfOdud terml.
0
I
c A8
0
I
IJU
00
' 11("
WC-
01
01
' IIC
. IHC
"
"
1/1("
·1lJ(
10
10
",11("
lfJe
'"
(bl
The 4-Variable Karnaugh Map The 4-variable Karnaugh map is an army o f sixteen cells, a'i shown in Figure 4-22(a). Binary values o f A and B arc alo ng the left side alld the values of C and J) are across the top. The value of a given cell is the binary values of A and B <.It the left in the same row com-
THE KARNAUGH MAP
CD
0'
CD
'0
"
"
01
00
WO '
~H( { t
o
0'
\ /JCi ' 1/10
"
"
t/W / '
wu , AlI{"N IIlen
10
'0 W( I '
I HOI '\/If I I \/lU I
()()
00
A Ii
,
(.,
211
FIGURE 4 - 22
10
()()
A8
•
"flO
,80 1
\I/O
18CO
A 4-variable Kamaugh ITI
(bi
bined wilh the binary vulues of C and D at the top in the same column. For example. the cell in the upper right corner has a binary value of 00 I0 and the cell in the lower right corner has a binary value of 10 10. Figure 4-22(b) shows the standard product terms that are represented by each cell in Ihe 4-variable Karnaugh map.
Cell Adjacency The cells in a Karnaugh map are arranged so that there is only a single-variable change betwccn adjacent cells. Ad.iacency is dcfined by a single-variable change. In the 3-variablc map the 010 cell is adjaccnt to the OOOeell. the Oil cell, and the 11 0 cell. The 010 cell is not adjacent to the 00 I cell , the I I I cell. the 100 cell. ol"lhe 10 I cell. Physically, each cell is adjacent to the cells thaI arc immediately next to it on any of its four sides. A cell is not adj acent to the cells that diagonally touch any of its (;OmefS. Also, the cells in the top row are adjacelll to the corresponding cells in the bottom row and the cells in the outer left column arc adjacent to the corresponding cells in the outer right column. This is called ··wrap-around·· adjacency because yo u can think of the map as wra pping around from top to bollOIll to tonn a cylinder or from left to righ t to fonn a cylinder. Figure 4-23 illustrates the cel l adjacencies with a 4-variable map, although the same rules for adjacency apply to Karnaugh maps with any number of cells.
Celli that differ by only one variable are adjacent Cells \Vith vallJes that differ by more than one variable are not adjacent.
FIGURE 4-21
A 8 CI)
'00 ""<;---:;or ""
" It, "ro
D Adjocent cells on a K;,maugh map
-,-- , . , .•. -•- ., . D '" · •'. .,'. .••. .'• . D Co· '. ,. .,-' D ~
(0'
. •_ .. ,. ,
• I.
I
"
'
I
f
I
are those that differ by only one variable. Arrows point between adjocent cells.
•
\)JVJ L In a 3-variable Kamaugh map, wnat il the binary value for the cell in each of the following locations:
(a) upper left comer (c) lower left corner
(b) lower ri'ght corner (d) uppe r right corner
2. What is the standard product term for each cell in Question T for variables X, andZ?
3. Re peat Question 1 for a 4-va riable map. 4. Repeat Question 2 for a 4-variable ma p using variables VI. X.
Y. and Z.
y.
212
_
4-9
BOOLEAN ALGEBRA AND LOGIC 51MPliFICATION
KARNAUGH MAP SOP MINIMIZATION As stated in the last section, the Karnaugh map is used for simplifying Boolean expressions to their mi nimum fonn. A minimized SOP expression contains the fewest possible tenns with the fewcst possible vnriables per term. Generally, a minimum SOP expression can be implemented with fewer logic gates than a standard expression . After completing this scction,
}'Oll
should be able to
- Map a sWlldard SOP expression on a Kama ugh map - Combine the I s on the map inlo maximum groups - Detennine the minimum product term for each gruup un the map - Combine the mini1l1um produetterms to fonn a minimum SOP e~ pression - Convert a truth table into a Karnaugh ml.lp for simplification of the reprcsented expression - Use "oon', care" conditions on a Kamaugh ma p
Mapping a Standard SOP Expression For an SOP expression in standard form , a I is placed on the Karnaugh map for each product term in the expression. Each I is placa.!.in a cell correspond ing to the \"dlue of a product tenn. ror example, for the product te rm ABC. a I goes in tbe !OI cell on i'. 3-variable map. Wben an SOP exprcssioll is completely mapped. there will be a number of Is a ll the Karnaugh map equal to the number of product tenns in the standard SOP expression. The cells that do not have a I arc the cel ls for which the expression is O. Usually, wilen working with SOP expressions. the Os arc left off the map. The following steps and the iJlustration in Figure 4- 24 show the mapping process. Step 1. Detennine the binary value o f each product Icon in the standard SOP expression. After some practice. you can usually do the evaluation of terms mentally. Step 2. As each product teon is cvaluated, place a I all the Kamaugh map in the cell having the same value as the product tenn.
FIGURE 4 - 24
C
Example of ffi<\pping a standard 50P cxprcuion.
All
I
0
(0)
,~
1-
"
1-
1---1-
10
1-
-
00 01
I
AIJC
+
A BC
00 1
+
AHC
110
+
II//e
100
~
EXAMPLE 4 - 21
Map the follOWing standard SOP expression on a Ka rnaugh map: ABC SoiJJtiOI'l
+ ABC +
ABC
+ ABC
Evaluate the expression as shown below. Place a I on the 3-variable Karnaugh map in Figure 4-25 for each standard product term in the expression.
ABC + ABC + ABC 'I ABC 00 I 0I0 I 10 I I I
KARNAUGH MAP SOP MINIMIZATION
. FIGURE 4-25
c A8
0
I
00
I'
UI
I.
"
I,
,
i
Map Ihe standard SOP expression ABC
.- Alil - Mil
I'
-
,
1'-
10
Related Problem
•
+ ABC + AB C on a Kamaugh map.
EXAMPLE 4 - 22
Map the following standard SOP expression on a Karnaug h map: ABeD Solution
+ ABeD + ABeD + ABeD + ABeD + ABeD + ABeD
Evaluate the expression as shown below. Plaee a I on the 4-vllriable Karnaugh map in Figure 4-26 for each Siandard product t(:nn in the expression. ABeD 00 11
+ ABeD + ABeD + 0 100
I [01
ABCD + ABeD II [J 11 00
+ AB CD + ABCD OOO [
10 10
FIGURE 4-26
CD A8
AlJef)
01 /
OIl
,I
00
01
10
"
-
1-
..IHO)
I ~
,\fl( f) / '
"
~
I
I I
AHO) / '
I
10
,\II("/J
Related Problem
I
•
\
,
A IJ( /)
Map the fo llowing standard SOP expression on a K:lrnaugh map: ABCD + ABCD
+ ABC D + ABCI)
Mapping a Nonstandard SOP Expression A Boolean expression must first be in standard fonn befOre you lise a Kamaugh map. If an expression is not in st.mdard fonn, then it must be convCl1ed to stnndard form by the procedure covered in Section 4-6 or by numerical expansion. Si nce an expression should be eval· uated before mapping anyway, numclical expansion is probably the most elTicient approach. Numerical Expansion of a Nonstandard Product Te,m Recall that a nonstandard product term has one or more missing variables. For example, a"sume that one of the product
1-
- AlJCD
213
214
•
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
terms in a certain 3-variable SOP expression is AB. "Ibis tenl1 can be expanded nu merically to standard fonn as follows. First, write the binary value of the IwO variables and an ach a 0 for the missing variable C: 100. Next, write the binary value of tile two variables and auucl1 a I for the missi ng var~~e C: 1Q.l. The two resulting binary numbers are the values of the standard SOP terms ABC and ARC. As another example, a~sume tha t one o f the product lenns in a 3-variable expression is B (remember that a single variable counts as a product term in an SOP expression). 111is term can be expanded numerically to standard form as follows . Write the binary value of the variable; then au ach all possible values for the missing variables A and C as follows: B
010 011 11 0 II I
The four TCSulting binary nu mbers are the values of tile standard SOPtelms ABC, ABC, ABC. and ABC.
I
EXAMPLE 4-23
Map the fo llowing SOP expression on a Kamaugh map: A Solution
+ AB + ABC
The SOP expression is obviously not in standard fonn because each prodUct tenn does not have three variables. The first term is missing two variables. the second term is missing one variable, and the third tcnn is standard. First expand the terms nume rically as follows:
A
+ AB + ARC
000
100
00 1
101
110
010 011 Map each of the resulti ng binary values by placing a I in the appropriate cel l of the 3variable Karnaug h map in Figure 4-27. FIGURE 4-27
c
0
I
00
I
I
01
I
I
"
I
10
I
Ali
ReIo.ted Problem
Map the SOP expression Be
+ AC on a
I
Karnaugh map"
KARNAUGH MAP SOP MINIM IZATI ON
i
•
215
EXAMPLE 4-24
Map the fo llowing SOP expression on a Karnaugh map:
BC + AB + ABC + Solution
ABCD + A B CI) + ABCD
The SOP expression is obviously not in standard fOrm because each product tenn docs not have four variables. The first and second terms are both missing two variables, the third tenn is missing one variable, and the rest of the terms arc standard. First expand the tenns by incl uding all combinations of the missing variables numerically as follows: BC
0000 000 1 1000
100 1
AB
1000 1001 10 10 J0 I I
+ ABC + A BCI) + ABeD + ABCD 1100 I 10 1
10 10
000 1
10 11
Map each of the resulting binary values by pl acing a I in the appropriate cell of the 4variable Karnaugh map in Figure 4--28. Notice thai some of the values in the expanded expression arc redundant .. FIGURE 4-28
,
00
01
00
I
I
II
I
I
10
I
I
CD
AI
II
10
,
I
01
Related Problem
Map the expression A
+ CD + ACD + A.BCD on a Karnaugh map.
Karnaugh Map Simplification of SOP Expressions The process thai results in an expression comaining the fewest possible terms with the fewe st possible variables is ealled mini m i7-
I . A group must contain either I, 2,4, 8, or 16 cells, which are all powers of twO. In the case of a 3-variable milp. 23 = 8 cel ls is the maximum group. 2. Each cell in a group must be adjacent to one or more cells in that samc group. but all cells in the group do not have to be adjacent to eaeh other. 3. Always include the largest possible number of Is in a group in accordance with rule I.
216
•
BOOLEAN ALGEBRA AND LOGIC SIMPLIFI CATION
4...::ach I on the map must be included in at least one group. The Is already in a group can be included in another group a~ long as the overlapping grou ps include noncomJllon Is.
i
EXAMPLE 4-25
Group the Is in each of the
c A8
00
0
1
C
0
1
00
1
1
1
U1
1
1
11
AI
1
01
11
,
1
10
10
(.1
CD
Karnau~h
00
01
()()
1
1
01
1
1
A8
maps in Figure 4-29.
11
1
10
1
11 1
1
1b)
10
1
1
CD
00
A8
00
1
01
1
11
1
10
1
11
01
10
1 1
1
1
(d(
(0)
FIGURE 4 - Z9
Solution
The groupings arc shown in Figure 4-30. In some cases. there may be more than one way to group the I s to fonn maximum grou pings.
, C
A8
00
0
10 1. )
1
,
1
CD
C 0
1
111l
1
1
1
01
1
1
11
(0
01
11
1
\\ r:' .......lnlUlIl' :Io,1J"'"''''''
AI
10
1
1~
01
00
1
)
01
1
1
,\ Ii
1
11
1
10
kJ
1b1
1
11
1
1
10
1
CD A8
,00
01
11
\
10
00
1
01
1
1
1
11
1
1
1
11)
1
1
1
1
1d1
FIGURE 4 - 30
Related Problem
Determine if there are other ways to group the Is in Figure 4-30 to obtain a minimum number of maximum groupi ngs.
Determining the Minimum SOP bpreJu'on from the Map When alltre I s representing the standard prtXiuct terms in an expression are properly mapped and grouped, the process of determining the resu lting minimum SOP expression begins. The following rules arc applied to find the minimum productterills and the minimum SOP cxpression:
1. Group the cells that have Is. Each group of cells containing Is crcafcs one product term composed of al l variilblcs that occur in only one [DIm (either uncomplcmentcd
KARNAUGH MAP SOP M INIMI2ATI O N
•
217
or oomplemenled) within the group. Variables that occur both unoomplemcnted and complemented with in the group are eliminmcd. These are called cOlllmdictOl)' v(lrjllhles.
2. Dclennine the minimum product tcrnl for cach group. a. For'l 3-variable map: (1) A l-cell group yic\d~ a 3-variable product teml (2) A 2-ccll group yields a 2-variable product tcon (3) A 4-cell group yields a I-variable tern) (4) An 8-ccll group yields a value of I for the expression b. For a 4-variable map: (I) A I-cell group yields a 4-variable prOOuct term (2) A 2-ccll group yields a 3-variable producl leml (3) A 4-cell grou p y icld~ a 2-vHriable prodoct teon (4) An 8-ce\l group yields a I-variable term (5) A l6-ccll group yields a value of I for the expression 3. When all the minimum producttenns are derived from the Karnaugh map, they are summed to form the minimum SOP expression.
Detennine the product tenns for the Karmmgh map in Figure 4--3 1 (lnd wri tc the fCSulting minimu m SOP expression. FIGURE 4 - 31
CD A8
00
" '"
01
""
1
01
1
1
1
1
"
1
1
1
1
10
1
\
Solution
1
Am
Eliminate variables that arc in a grouping in both comp1cmcnlcd and uncomp1cmenled fOnTIs. In Figure 4- 3 1, the producttc!!"I1 for th~8-cc l1 group i:; B becausc thc eclls withi n Ihat group contain both A and A, C and C, and D and D, which arc e1iminatcd. The 4-cell gro up contains B, D, and 15, leaving the variables Aand C. wh~ h form the product tcrm A'c. The 2-ccl ~g roup contains B and Ii, \cavi ng variables A, C, and D which form the product term IICD. Noticc how overlapping is used to maximi%e the si%c of the groups. The resulting min imum SOP expression is the sum of these product (cmlS:
n,
8 + Related Problem
Xc +
ACV
For the Kamaugh map in Figure 4- 3 1. add a I ill the lowerright cell (JlIJU) and lIetennine lhc resulting SOP cxpression.
218
•
BOOLEAN ALGEBRA AND LOG IC SIMPLIFICATION
I
EXAMPLE 4-27
Determine the produet teons for eaeh of the Karnaugh maps in Figure 4- 32 and write the resulting minimum SOP expression.
c AU 00
0'
"
ne , / / 1( , , , , 0
'0
,.,
c AB 00
0'
" '0
0
I'
,I"
cn
, --
00
, , "
01
, , , ,
AB
,
AC
, , ,
00
I'"0'
"
'0
AU
'"
00
/
" '0,
0'
, , , , 0' , , , " , \ , , to
An
\
"
\
n
00
, ,
lO
,b)
cn
/1(
Cd)
' HC
FIGURE 4 - 12
Solution
Related Problem
I
The res.ulting minimum produellerm for caeh group il> shown in Figure 4-32. The minimum SOP expressions for eaeh of the Karnaugh maps illihe fi gure are (a) A8
+
BC
+ ABC
(b) 8
(eJ AB
+
AC
+
(d)
ABO
+ A C + AC
D + ABC + BC
Fonhc Karnaugh map in Figure 4-32(d), add a 1 in the Ot II cell and determine the resu lti ng SOP expression.
EXAMPLE 4-28
Usc a Kamaugh map to minimize the following standard SOl' exprcs.,ion:
ABC + ABC + ABC + ABC + ABC Solution
The binary values of the expression arc 10 1 + 0 11
+ 0 11 + (XX) +
I(X)
Map the standard SOP expression and group the eells as shown in Figure 4-33. FIGURE 4-31
c M/
00
0
,
0'
" '0
,
,
, ,
-
,
-
"
KARNAUGH M AP SOP M I N IM IZATION
•
21 9
Noticc the "wrap around" 4-cell group that includes the top row and the bonom row of Is. The remaining I is absorbed in an overlappi ng group of two cel ls. The group of four Is produces a single variable term, ii. This is determined by obscrving that within the group, is the only variable QIl11 docs nm change from cell 10 cell . The group of two Is produces a 2-variablc term A C. 111is is determined by observing Ihat within the group, Ii and C do not change from one cell to the next. TIle product term for each group is shown. The fCS ulting minimum SOP expre ssion is
n
B + AC Kcep in mind lhal this mi ni mum expression is equivalent to the original standard expre ssion. Related Problem
Usc a Karnaugh milp 10 simpl ify Ihe following slimdard SOP expression: Xl'Z + Xl'Z + X l'Z + Xl'Z
I
+ XYZ + Xl'Z
EXAMPLE 4-29
Usc a Kamaugh map 10 minimi;r.c the following SOP expression: BCD Solution
+ ABeD + ABe D +
A BCD
+
ABeD -I- A BCD
+
ABCD
+
ABeD
+
ABCD
"ille firsllcrm lic D must he expanded into AnCD and AileD to get the standard SOP expression, which is then mapped; and the (;ells arc grouped as shown in Figure 4-34. FIGURE 4-34
CD AH
Be
0'
00
, , , " ,
,
00
",
'0 (
-I)
'J
,
01
, ,
10
I ,,'
Notice Ihm both groups exhibit "wmp around" adjacency. The group of eight is formed because the {.·c1ls in the outer columns afe adjacent. T he group of four is formed 10 pick up the remaining Iwo Is because thc top and bottom cel ls arc adjacent. The product term for each group is shown. The res ulti ng minimum SOP expression is
D + Be Kccp in mind that this minimum express ion is equivalent to the original Standmd expression. Related Problem
Use a Kurnaugh map to simplify the following SOP ex pression: \VXYZ
+
\vXYZ
+
\vXl'Z
+
WYZ
+
\vXYZ
220
•
BOOLEAN ALGEBRA A ND LOGIC SIMPLIFICATION
Mapping DirectJy from a Truth Table You have SCCn how to map a Boolean expression; now you will learn how to go d irectly from a truth Ulblc toa Karnaugh map. RecaU that a tnuh table givcs the output of a Boolean expre~sion for all possible input variable combinations. An example of a Boolean expression ,-Ind its truth wblc representation is shown in Figure 4-35 . Notice in the truth table thHI the outpul X is I for four different input variable combinations. Thc I s in the output column of the truth table are mapped directly onto a Ka rnaugh map into the cells corresponding to the values of the associaled input variable combinations. as shown in Figure 4-35. In Ihe figure you can see thai the Boolean expression, Ihe truth table, and the Karnaugh map arc simply different ways to represent a logic function. FIGURE 4 - 35
X = AlJ(' + "HC + Aile + AHe
Example of mapping directly from a truth table to a Karnaugh map.
ABC I o0 0 o0 t o 0
o
1 1 0 I
o
o
X I 0 0 0 I 0
o
c 00
I
0
All
Inputs ' Output
0)
I 01
0) 0) ~ 0) I II
,
-
--
N
"Don't Care Conditions Sometimes a situation arises in which some input variable combinations are nol allowed. For example. recall that in the BCD code covered in Chapter 2. Ihere arc six invalid combinations : 1010, 101 1, 1100, 110 1, 111 0, and 1111. Since Ihese unallowed states will never occur in an appliclllion involving the BCD code, they can be treated as "don" care" terms wi th respect to their effect 011 the output . Thal is, for these "don't care" terms either a lora 0 may be assigned to the output: it really docs not mailer since they will never occur. The "don' t care" lerms c;:m be used to advanttlge on the Karnaugh map. Figure 4-36 shows that for each "don' t care" tenn. an X is placed in the cell. When grouping the Is, the Xs call be treated as Is to make a larger grouping or as Os if they eannol be used to advantage. The larger a group, the simpler the resulting tenn will be. T he tmlh table in Figure 4--36(a) describes a logic function that has a I output only when the BCD code for 7,8, or 9 is present 011 the input ~. If the "don' t carL'S" are used as Is. the resulting expression for the function is " + BCD. as indicated in part (b). If the "dOIl '1 cares" are not used as Is, the rc.~ulti n g expression i~ + ABCD: so you can see lhe ad\'anlagc of using "don't care" terms to get the simplest expression.
"Be
J SECTION 4 - 9 REVIEW
1. Uy out Kamaugh maps for three and four variables. 2. Group the l s and write the simplified SOP expreuion for the Karnaugh map in figure 4~25. 3, Write the original standard SOP expresioOl (or each of the Karnaugh maps in figure 4-32.
KARNAUGH MAP POS MINIMIZATI ON
•
221
FIGURE 4 - 36
&.Imple of the use of "don't care~ Condition! to !implify <10 e)(pression.
0 0 01 0 010 0 01 I 0100 010 I oI I0 oI I I I 00 0 00 I 010 I 0 I I I 100 10 1 I 10 I I I
0
0 0 0
CD
0
"00
0
I X X X X
01
01
11
10
1
f- -
11
X
X
X
X
10
I
1)
X
X
.
AHC/) fUD
Don' l cares
X
X
(al Trulh lable
4 - 10
00
/ AHe
, A
(bl Wilt)()UI "don't c ares~ Y '" A BC ~ A flCD Wilh "don ' t cares" Y '" A + BCD
KARNAUGH MAP POS MINIMIZATION
In the last seeti(ID, yuu studied the minimization of an SOP exprc.o;sion using a K
Mapping a Standard POS Expression For a POS expression in standard form, a 0 is placed on the Kamaugh map for each .c;um term in the expression. Each () is pla':..,ed in a ce ll corresponding 10 the value of a sum Icnn. For example, for the sum term A + B + C, a () goes in the 010 cell o n a 3-variabl e map. When a POS expression is completely mapped, there will be a numocr of Os on the Karnaugh map equal 10 the number of sum terms in the standard POS expression. The cells that do not have a Darc the cells for which the expression is 1. Usually, when working with POS expressions, the Is arc left off. The follow ing sleps and the illustmtion in Figure 4-37 show the mapping process. Step I. Determine the bi nary value o f each sum term in the standard POS expression. This is Ihe binary value that makes the term equal to O. Step 2, As each ).,um term is evaluated, place a 0 on the Karnaugh map in the corresponding cell.
222
•
BOOLEA N ALGEBRA AND LOGIC SIMPLIFICATION
c
FIGURE 4 - 31
1
Example of ~pping 01 It.1ndOlrd POS exprellion.
00
n· -
01
n.
II
n.
10
i
I
0
!,\ +8+CM ,\
000
+ IJ ... ("M I + 8+ 110 010
C~A ~H
101
~
--
I
I
n·
EXAMPLE 4-30
Map !he following s!anclard POS
Solution
(A + Ii
+
expres~ion
on a Karnaul!h map:
Evaluate the expression as shown below and place a 0 on the 4-variable Karnau,gh map in Figure 4-38 for each standard sum tenn in Ihe expression.
c + D)(A +
11 00
B + C + D)(A + B + C + D)(A lOll 0010
+ B + C + D)(A + B + C + D) II II
00 11
FIGURE 4-38
CD A8
00
II
01
/
•
n
00
10
n·
- A+II+C+O
01 II
n'
10
•
"' I
'\+I1 + ("+n
Related Problem
A+H+C+f)
0 -
•
-
\+8+C + /)
Map Ihe followin g stand tucl POS expression on a Kanmugh map:
Karnaugh Map Simplification of P~S Expressions The process for minimizing a POS expressiun is baskally the same as for an SOP expression exf,;cp' that you group Os toprocluce minimum sum tcrms inste;ld of grouping Is to produce mi ni mum produc! terms. The rules for grouping the Os arc Ihe same as Those for grouping Ihc Is that you learned in Section 4-9.
pas M IN I M IZATI ON
KARNAUGH MAP
i
•
223
EXAMPLE 4-31
Usc a Karnaugh map to minimize the following standard POS expression:
0+·+q0+B+~0+i+00 + i+~~+i + q Also, de rive the equivalent SOP expression.
Solution
The combinations of binmy values of the expression " re (0 + 0 + 0)(0 + 0 + 1)(0+ 1 + 0)(0 + I + 1)(1 + 1 + 0 ) Map the standard
pas expression and group the cells as shown in Figure 4-39.
FIGURE 4 39
,c
0
I
00
0
0
01
0
0
II
0
I
10
I
I
AI
11+, -
.
~
A
-
AC
/ A8
Notice how the 0 in the 110 cell is incl uded into a 2-ccl l group by utilizi ng the 0 in the 4-ceJl group. T he sum term for each blue group is shown in the figure and the res ulting min imum POS expression is
A(i + C) Kcep in mind that this m ini mum POS expression is equivalent to the original Siandard
pas expression. Grouping the 1s as shown by the gray areas yields an SOP expression thai is cquivHlcnt to grouping the Os.
AC + Related Problem
An = A(i + q
Usc a Ka rnaugh map 10 simplify the following slandard POS expression:
(X + Y + Z)(X + Y +
I
Z)(X + Y + Z)(X + Y + Z)
EXAMPLE 4-32
Usc a Kaillaugh map to mi nimize the followin!,! POS expression:
(B + C + D)(A + Solution
/J
+ C + D)(A + B +
C
+ 15)(A + Ii +
C
+ D)(A + ii +
C
+ D)
The tirst term musl be expanded illlo A + B + C + D and A + B + C + D 10 gel a standard POS expression, which is Ihell mapped: and the cells arc grouped as shown in
224
•
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
Figure 4-40. The sum term for each group is shown and the resulting minimum POS expression is (C
+
D)(A
+ B + D)(A + B + C)
Keep in mind that this minimum POS expression is equivalent to the original stilIldard POS expression . .. FIGURE 4 - 40
CD A8
Related Problem
,\ + II
01
00
00
0
01
0
"
0
10
0
I.
"
-
'0 "
i-
f)
,/
C ... fl
0
Usc i\ Karnaugh map to simplify the following POS expression:
(W +
X+
y
+ Z){W + X + Y + Z)(W + X+ Y + Z)(W + X + Z)
Converting Between POS and SOP Using the Kamaugh Map When a POS expression is mapped. it cml easily be converted to the equivalent SOP form directly from the Kamaugh map. Also, given a mapped SOP expression. an (Xluivalent POS expression can be derived d irt..'Cl ly from (he map. This provides a good way 10 compare both mini mum fomlS of an expression 10 delennine if one of them can be implemented with fewer gates Ihan the other. rOr a POS expression. aU the cells that do not conli:tin Os conll.lin Is, from which the SOP expression is derived. Likewise, for an SOP expression, al l the cells that do not contain [s contain Os. from which the POS expression is derived. Example 4-33 illustrates this conversion.
I
EXAMPLE 4 - 33
Using a Karl1ilUgh map. convert the following standard POS expression into i\ minimum POS expression. i\ standard SOP expression, and i\ min imum SOP expression. ~ + i + C + D )(A + j + C + D) ~ + B + C + ~)
(A + B + C + D)(A + B + C + D)(A + B + C + DJ Solution
The Os for the standard POS expression arc mapped and grouped 10 obtain the minimum POS expre<;.~ i on in Figure 4-41(a). In Figure 4-4 1(b), Is arc added to the cells that do not contain Os. From each cell containing a 1. a standard product tenn is ohtaillcd as indicated. These product tcons fonn the standard SOP expression. In Figure 4-4 I(c), t.he Is are grouped and a minimum SOP expression is obtained.
FIVE- VARIA BLE KARNAUGH MAPS
CD
A8
00
00
01
0
"
0
01
II
10
0
0
0
,
CD
I
A /I
I or
II/
10
0
0
00
,I
0
III
0
I
I
"
0
I
I
10
,I
,
,
/I
/ 0
,
"'let)
(a) Min;lnuIllI'0 5: \A + B + C)(8 +- C + Il)(/I + C +
CD
0)
ABcn
,-I -
AlJeIl
\ \IICf)
1I1("f)
IHC"
(b ) Slaooard Sop: ABCD + ABCD + AfJCV + AIlCD +AIlCD + A/KD + AiiEi5 + AfJe D + ABeD + All CD HI>
00
01
"'
10
00
I
0
0
0
III
0
I
I
I
II
0
I
I
,
10 1' 1
0
I
I
A8
,
I
/
\ H+C+O
ABCI)
I - - AIlCl)
\
I
/
,---
u+c+/)
10
225
,J,llcn
AH('I)
00
•
/Ie
\ H( "f)
(c) Minimum SOP, AC + IJC + 1m + flCD FIGURE 4 - 41
Related Problem
Use a Karnaugh ma p to eonvcrl the fo llowing express ion to min imum SOP form:
(W + X + Y + Z)( IV + X + Y +Z)( IV + X+ Y+Z )( IV + X + Z )
I
SECTION 4-10 REVIEW
1. What ii the diffe rence in mapping a POS e xpres.lio n and a n SOP expreSiio n? 2. What is the standard sum tenn expressed with va riables A, B, C, and 0 for a 0 in cell 1011 of the Kamaugh map?
3. What is the stdndard product tenn expresred with variables A. 8, C, and D fo r a 1 in cell 0010 of the Karnaugh map?
4- 11
FIVE-VARIABLE KARNAUGH MAPS
Boolean fUTlCtions with tive variab les can be simplified using a 32-cd l Kamaugh map. Actually, Iwo 4-vanablc maps (1 6 cells each) are used to construct a 5-vruiablc map. You ah-c
226
_
BOOLEA N ALGEBRA A N D LOGIC SIMPLIFI CATI O N
Aftcr complet ing this scction. you should be able to • Determinc (:ell adj acencies in a 5-variable map _ Form maximum cell groupings in a 5-variable map _ Mini mize 5-variable Boolean expressions usi ng the Karnaugh map
A Kamllugh map for five variables (ABeDE) can be constructed using twO 4-variable maps with which you are already famiJillr. Each map contains 16 cells with all combinalions of variables B. C. D. and E. One map is for A = 0 and the other is for A = I. as shown in Figure 4-42. fiGUR E 4 - 42
A 5-varia ble Kamaugh map.
nC
DE-
uu
00
" "
IU
IIC
DE-
" "
00
00
UI
UI
"
"
10
10 11 = 0
10
11 = I
Cell Adjacencies You already know how tn de tcnnitle adjao.:ent cells within the 4-variable ma p. The besl way to visual i,..c cell adjacencies belween the IwO 16-ccll maps is to imagine thai Ihe A = 0 map is placed on lOp ofthc A = 1 map. Each cel l in the Ii = 0 map is adj acent to the cell di rectl y below it in the A = I map. To illustrate, an c)(ample with four groups i!': shown in Figure 4-43 with the maps in a 3d imensional arrangement. The I s in the ycl low cells form an 8-bi t group (four in theA = 0 f i GURE 4 - 43
liIustr.>tion of groupings of II in adjacent cells of a 5-variable map.
nC
DE-
00
01
"
10
,, ,, ,
I
00 I
01
I
I
II
"
I
I
I
IU
I
I
I
,, ,, ,,
,,
,,
,, \
.Jcp
,,,
"
,,
- 00
1)£
C
01
1I
,,
l
10 '
,
00
,, ,, ,," , I', ,
,, ,
,,
I
I
I
I
, 1 I
I
II = I
fIVE-VARIABLE KARNAUGH MA PS
•
map l"Ombincd with four in the A = I map). lllC Is in thc orange cclls form a 4-bit group. The 1s in tnc light red cel ls form a4-bil group only in lheA :: 0 map. llle I in the gray cell in Ihc A = I map is grouped wilh Inc I in Ihe lower right lighl red cell in thc A :: 0 map 10 form a 2-bir group.
Determining the Boolean Expreuion The original SOP Boolean expression thaI is ploucd on the Karnaugh map in Figure 4- 43 contains seventccn 5-variable le rms because there arc seventeen I s on the map. As you know. on ly Ihe variab les Ihal do nOI change from uneomplemented to com plemented or vicc vcrsa within a group rcmain in thc cxpression for thai group. The simplified cxpression laken from the map is developed a.~ follows: 1l1C Icm for the yellow group is DE. The term for the orange group is BCE. The telm for the light red group is /\1315. Thc Icon for the gray cell grouped with thc red ccll is BC DE. Combining these tennS into the simpl ified SOP expression yields X = DE
+ BCE + ABO + BC DE
I
EXAMPLE 4-34
Usc a Kamaugh map to minimize Ihc following standard SOP 5-variablc cxpression:
ABCDE + ABCDE + ABcD"E + ABCOE + ABCDE + ABCOE
X =
+ Solution
A13CDE + ASCDE
+ ABCDE + ABCDE +
ABCDE + ABCDE
Map the SOP expression. Figure 4-44 shows the groupings and their corresponding lenns. Combining thc tcmlS yields thc following mini mizcd SOP cxpression: X
+ ADE + JJCD + BCE + ACDE
FIGURE 4-44
/' DEC
00
01
00
I
I
01
I
"
I
10
I
"
,
II! J)
- 00
I)r
10
C
00
I
01
I
"
10
I
01
I
]]
I I
~.
ACvE
I
10 A= 1
Related Problem
Minimize the following expression:
ABCDE + ABCOE + ABCD"E + ABCDE + AHCDE + ABCDE + ABCDE + AlicDE + ABCDE + A BCDE + ABCDE + AJJCDE + AHCDE + ABCDE + ABCDE + ABCDE
Y ::
227
228
•
BOOLEAN A LGEBR A AN D LOGIC SIMPLIFICATION
.... 1111111111111. . .SECTION 4_11
I
REVIEW
-1. Why dOf"..J; a 5-vilriable Kamaugh map require 32 cell~7 2 . What is the expression represented by a 5-variable Kam augh map in which each cell conta ins a 17
J 4 - 12
VHDl (option a l) This oplional section pl"Ovides a brief introduclion to V HDL and i!-l not meant to teacn lhe (.'Ompletc structw-e and syntax of tile J angua~><:. For more dClai led informatio n a nd instnl(.1ion. refcr to the footnote. Hardware descriptionllmguages (H DL~) arc tools for logic design elll!),. called text el1lf)'. thm arc used 10 implement logic dcsigns in programmable logic devices. Although VHOL pmvidc.<: mUltiple ways todcscribc a logic circuit, only lhe simplcsi and mOSI direct pmgr.unming examples oftcxt enlly are discussed hel't~. Aftercornpleling this section. you should be able to • S iale the essential clements o f V I·IDL • Wrile a simplc VHDL prog ram
TIle V in VHDL* slands for V IISIC (Very High S(X!ed Inlegralcd Circuit) and Ihe HD L. of cou~e . slallds for hardware descriplion language. As mentioned, VHDL is a standard language ado pted by the IEEE (lnstitule of Electrical and Eleetronies Eng ineers) and is designatcd i EEE Std. 1076- 1993. VHDL is a complcx and eom prehcnsive lang uage and us ing it to its fu ll potential involves a lo t of effon and expcli e nce. VHDL provides three basic a pproaehcs to dc<;cribi ng a di g ital circuit usi ng software : bellllliiom/. (fmC/flow. and .\'Iruclu ml. Wc will reslricl lhis discuss ion to the data Ilow approach in which you w rite Boolean-type statements todeseribc a logic cireui t. Keep in mi nd that VI-lDL. as wel l as the other HDLs. is a tool for implement ing d ig ital designs and is. therefore. a mcans 10 a n end a nd not an e nd in itself. It is relatively easy to w rite programs to describe simple logic circui(.~ in V HDL. The logical operators are the following VHDL keywords: and. or, not, nand, nor, xor, and xnor. 1llc IWO cssenti.al ele l11CIlIS in any VHDL progrdlll are the enti ty and the architeenlre. and they must be used together. The entity oc<:Clibcs a given logic fun(.1 ion in toollS o f its e)\temlll inputs and o ut put<:, called pons. 'Ille architl'Cture describes the intemal o(X!Tlltion of thc logic fUnclion. In its s implcst form. tile enlity c1e me nl consisls of three statell1CnlS: The firSI statemcnt assigns a name to a logic function: the second statemclll, called thcpon statement whic h is indented. s(X!ci fics Ille inpuls a nd o ut puts: and the Ihird statement is Ihe end statement . A lthough you would probably not wri tc a VI-IDL program for a sing le gate. il is instructivc to start with a s imple example such a .. a n AND gale. Thc V IIDL c mit y declaralion for a 2-input AN D gatc is Colons and semicolons must be u~ed appropriately in aU VHDl program~.
elltity AND_Gatc2 is port (A. 8: in bit: X: out bit); end entity AND_Gatc2:
1llc blue boldlace tenns arf' VHDL keywords: the o lher lenns are identifiers that you as.<:ign: and the parentheses. eoloos. and semicolons arc requ ired VHDL syntax. As you can sec, A and B arc specified as input bits and X is specified as an output bit. The port identi fiers A. B. and X as well as the entit y name A.l\fD_Gate2 arc user-clefi ned and can be renamed. As in all HDLs. the pla(."Cl1lCnl of colons lUld semicolons is crucial and lIl u..1 be strictly adhered 10. The VHD L architeelure clcment of thc prog ra m for the 2 -input AND gate dc<;eribcd by till: l:J!tity is ~M1.'
,,·iII.
"loyd. Thomas, 1003. Digital I'lmdilmelltafs VHDL l>n",tio.."(' 11;,11; F\,lkri". D>o,"jd "nd Ta,'kor. 1997. VIIDI. Mmle & S)'! Prl'I.tkt, lIall; Ilhask.,r.JR)'RnoIlL Im.A VUDI. Primer, 300.I·rc"ti<:r HaiJ.
o.:)"~
VHDl
•
229
architecture LogicFullction of' AND_Gate2 is bt.-gin
X
¢:::
A and B;
end arehitldun: LogkFul1(.1ion; Again, the VHDL keywords arc blue boldface, amI the scm i(.'Olons and the assignment operator ¢::: arc rC{juircd syntax. The lirnt stalement of the architecture clement mU5>t rcferelJ(.X: the entity name. The entity and the architcctu re arc combined into a single V HDL program to describe an AND gate, ~IS illustrated in Figure 4-45 . FI GURE 4 - 45
A VHDl progr.3m for.3 2-input AND
prn1 (A. S: ill bil : X: oot bit);
gate. an:hitooure Log icl'unc lioo uf AN D_ Galc2 ;5 bq:io X <= A :md B: l'IId an:hitt'dILI'C LoglcPunctioo:
Wn·ting Boolean Expres.siollS in VHDL As you saw, the expres5>ion for a 2-inpu t AND gale, X = AB. is written in VI-IDL as X ¢::: A aud B;. Any Boolean expression can be written using VI-IDL keyword5> not, and, or, Hand, nor, xor, and xnor. ror example, the Boolean expression X = A + 8 + C is written in V I-I D L a~ X ¢::: Aor B ore:. The Boolean expression X = AB + CD can be written as the VI-IDL statement X <:= (A and not B) or (not C and D);. As another example, the VHDL stalement for a 2-input NAND gate e,1I1 be written as X ¢::: not(A and B); or it can be written as X <:= A nand B;.
i
EXAMPLE 4 35 Write a VI-IDL program to describe the logic circuit in Figure 4-46. FIGURE 4-46 A
8
-
-L--'
x
c - -r-__ /) -
Solution
This AND/OR logic circuit is desc ribed
ill
-L_
/
Boolean algeb'd
lL~
X = AB + CD The VHDL program follows. TIle entity name is AND_O R. cntily AND_O R is I)Ort (A, B, C, 0: in bit; X: out bit); ~nd
l'ntity AND_O R;
architecture LogicFunclion of AND_OR is
begin X <= (A llnd B) o r (C and D); end architecture LogicFunction:
RelaW Problem
Write the VI-IOL statement to describe the logic circuit if a NOR gate replaces the O R
gate in Figure 4-46.
230
•
BOOLEAN ALGEBRA AND LO GIC SIMPLI FICATION
1. What is a n HDL?
2.
Name the two essential design elements in a VHDL program.
3. Wha t does the entity d o?
4. What does the architecture do?
Iow-Ievel voItagt! in order to activate a FJven
segment. \Nhen
common-cathode ilmmgement requires the
driver to provide a high-level voIt.lge to i>Ctivilte iI segment. When iI HIGH is ilpplied to a segmtrt input. the LED is turned on ¥ld there is current through it.
FIGURE 4 - 41
Seven-segment display forma t showing arrangement of segments.
dioda (~) arranged as ~ in figure Seven-lI"gment displays a re med in many types of producb. The tablet-cou nting and contml system that was deu:ribed in Chapter I ha. two 7-segment d isplays. The$e disp l¥ are Uled with logic circuitl that decode a binary coded decima l (BCD) number and activate the appro pria te digiti on the di.pl~. In thi. digita llYltem application, we focus on a minimum-gate d~ign (o r this to illustra te an application of Boole
4-4'J. Each segment is an LED that etT1Ib light when there is current through illn Figure 4-4'J(a) the cOl'l""ll"l"lOr"node arrange-
ment requires the driving ciraJit to prtMde a
LCD DiJplil)'J Another common type of 7-segment display il the liquid crystill d isp lily (LCD). LCOs operilte by pola rizing light 10 that a nonactivated segment reflects incident light ilnd thu l ilppeilrl invisible
n= n= nnllnnnnn - - fi- - - = - -
U U UU U UU U UU FIGURE 4 - 48
Displ of the ten digits by ming
LED Di'Pi"Y' Doe common type of 7-.egment display consists of light-emitting
FIGURE 4 - 4 9
+v
Arungements of 7-segment LED displays.
! L b :J'=~::!~~1 g
l:
l.
<:
-:==:w=~
I e
, h
"
<
ti
d ...J
d-'
(II) Com rnon·nf>odc
(bJ Common·cathode
DIGITAL SYSTEM APPLICATION
cannot be leen in the dark, while LEDI can. Segment Logic Each segment is Uled for van'oul dedma l digiti, but no one legment is used for;"lll ten digib. Therefore, each legmen t must be
output colu mn! of the table indicates an activated segment.
Expr~liom (or the other segmenb can be similarly developed. k you GIn lee, the
Since the BCD code does not iodvde thebinaryvaJue1 101O, lOll. 1100, 1101, 11 10, and J III, th~combinal:iom will
expression fOf" segment a hal eight product teffill
neve.- appear 0f1 the inputs and can therefore be treated as "don't caret (X)
the BCD inpub that activate that segment Thi\ meaOl that the standard SOP implementation of segment-a logic requ;rel an AND-OR circuitcomilting of eight 4-inputAND g..teJ and one 8-input
conditions, as indicated in the truth t able. To conform with the pr.lCtice of most IC manufacturers, A repreenb the least significant bit and D represents the most 5igniftcant bit in thil. parOwlar application,
Truth Table (or the Segment Logk The segment decoding logic requires (our binary coded decima l (BCD) inputs and Se\len outputs, one for each }egment in th e display, as indicated in the block diagram of figure 4- 50. The multiple-output truth tab le, shown in Table 4- 10, is actually seven truth table; in one and could be separated into a sepa rate table ; (or each segment. A , in the legment
OR gate. The implementation of segment-
e logic ~uireJ fOUl 4-inputAND gates and one 4- input OR gate . In both calCl, four inverters are required to produce the complement of e
Boolean Expressioru (or the Segment Logk From the truth table, a stanc:brd SOP o r POS expression can be written for each segment. For example, the stanc:brd SOP exprt'S$ion for legment a is
OeM + oeM + OCM + OeM + OeBA + oCaA' + oCM
a = DCBA +
and the standard SOP expreslion for legmente is
e = DCBA
+
oeM '1 DceA" + oCBA
KoImaugh Map Minimization or the Segment Logic Let'l begin by obtaining a minimum SOP exprelsion for legment a. A Kamaugh map for segment a il shown in Figure 4-5' and the following lteps are carried out; Step 1. The Is
TABLE 4 _ 9
Active segments for each decimal digit.
•
DIGIT
SEGMENTS ACTIVATED
0
(I.
h. c. d, e.f
.,r 2
1I. b. d. e. 8
3
lI, b, C, fl, 8
4
b.
tJ
g
5
(I .
t ',
(I, /. g
6
1I, c, d, e,/. g
7
(I,
b, (.
8
( I,
h, c, (I, e, /. g
9
fI,
b, c, fl,/. g
fiGURE 4-50
Block diagram of 7- segment logic and dilplay.
7-scgmclll decodi ng logic Bi ndl)
,,"'ol
/J C
dCl';mal II jur ur A
"b
,
d
,
,f
II
,=, 7-$Cgmellt
di~rlay
231
232
•
BOOLEAN A LGEBR A AN D LOGIC SIM PLIFIC ATION
TABLE 4 _ 10
Truth t"ble fOf" 7-scgment logic.
DECIM .... L DIGIT
0
INPUTS C B
A
0
0
0
0
0
0
0
0
2
0
0
3
0
0
4
5
"
6
0
7
0
a
0
0
0
0
0
0
0
0
9
0
0
'0
0
II
0 0
"
0
0
0
"0
0
0
0
0
0
0
X
X
0 0
, ,
X
0
U
12
0 0
0
8
g
0 0
14
0
15 o.~",~
SEGMENT OUTPUTS , d e (
0
"0 "
0
b
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
- I """llOSstpnml is llCIiy.... edlnn)
Outpur _ 0 ,,"",,,,,,, SL'tt',,,,,,r ;" nor: IItti w" oo ,.,11) o.~puI
-
X ITK'aIIs " don'l care"
Step 2. Al l of th e -do n' t c.ues- (X ) " re
celli are utilized to form the largest groups poss ible.
pl"ced o n the map, Step 3. The Is are grouped "I IhOWl1. "Don't ures aod overlapping of
St e p 4. W..'te the minimum product term fo r each group and lum
M
Standard SOl'
the terml to fo rm the minimum SOP ecpreliio n, Keep in mind that "don't ures- do not h;we to be included in" group, but in t h" QlSC a n of them are used. Also, notice t h..:lt the I s in the comer cells "re grouped with a "don't ",reM uling the "wrap a,ound"
cxpres.~ion :
vf:iiA -+- iXBiI -+- IXBA -+- DeliA -+- DCM -+- DelIA -+- f)ciiA -+- {"iCM 1M
DC
00 CA
(A ~,
~
'" " '0
x
U, I
II
'0
I , ~ , , ,
x
x
X
, ,
x
X
, "
-II
Mini mum SOP expression: D -+- 8 + CA -+-
~ =====:;] c
l~=====[) L.<- ,
" -
"
eX fiGURE 4 - 52
FI GURe: 4 - Sf
Kil rn.augh map m;nimi~tjon of the
The minimum logic implementiltion for legtnent a of the 7-segment dilpl1ly,
SUMMARY
Minimum Implementation of Segment-a logic The minimum SOP expression taken from the K4lrn.lugh map in Figure 4-52 for the segment-a logic ;1
D
+ B+
G4
+ CA
Thil exprenion Ciln be implemented with two 2-inputAND gil t~, one 4input OR g;,te ilnd two inverten iii Ihown in Figure 4-52. Comp1lre thil to the d:andilrd SOP implementiltion for segment-
•
ilnd
g) (;an
be obtilined with a simil il r
•
System Auignment
approilch .
• Activity 1." Detem1ine the minimum logic for segment b.
VHDL Implementation (optional) All of the segment logic GlIO be deSCTJbed by VHDl fa..- irrPementation in a progr..,nmable logiCdevice. Segment-a Iogiccan be described by the follO\.Ving VHDL progr.>m:
• Activity 2: Determine the mtnimum logic fOf" segment c.
• Activity 3: Determine the minimum logic for segment d.
entity SEGLOGIC is
• Activity 4: Determine the minimum logic for segment e.
port (A, B. C, 0 : in bit; SEGa: out bit); end entity SEGLOGIC;
• Activity 5: Determine the minimum logic for segment f.
architechJre LogicFunction of SEGlOGIC is
• Activity 6: Determine the minimum logic for segment g.
begin
• Optional Aclivity: Complete the VHDl pfOgr
SEGa <= (A and C) or (not A and not C) or B 01" 0;
including each segment logic dc«:riplion in the arcntecture.
end architecture logicFunction;
Gale symbols and Boolean e xpress ions for the o ut puts o f an inve r1 er and 2-i.:put ga tes arc shown in Fi gure 4-53.
'D-A8 "
A ~ /J
_
--L-/'""" AB
FIGURE 4 - 53
+B= B A 13 = lJA
+A
•
Co mm utat ive l aw.~: A
•
Associati ve laws: II
•
Distributive law: 11(8 + C) = AH +AC
•
+ (lJ + C) = (II A(BC) = (AB)C
l.
Boolelll1 ru les:
A
+0=
A
2. A I 1 = 1 3. A · O = 0
•
+ lJ) + C
7.
II·A = A
8. 11·11 = 0 9.
11 = 11
4.
A· I = A
/0. 11 + I1B = 1I
5.
II + 11 "' A
II.
A + AB = A + IJ
6.
II + A = J
12.
(11
+ 8 )(11 + C) = 11 + BC
OcMo rga n's Iht!orc ms: I. The complement o f a prod uc t is c
Xy = X +
Y
233
234
•
BOOLEAN A LGEBRA AND LOGIC SIMPLIFICATION
2 ' Ibe complement of" sum is C
X + Y = XY •
Kamau~h
fmm
IWO
rnups for 3 and 4 variubles ure shown in 1'I;:!ure 4-54. A 5-variable map is formed 4-variable maps.
fiGURE 4 - 54
C
U
I
CD H
00
00
01
01
"
"
10
10
00
KEY TERMS
The !xlS ie desi!!"n element in VHDL
i~
"
10
4-variabl"
3-vari"ble •
III
a n enlity/arclli te<:turc pair.
Key term! and o ther bold term~ in the ctl
"Don't care" A l'o mbinati on of input literals Ibat can not occur and citn be uscd as a I or it Oon it KarnSion imd useo for it ~ystemal ic simplification of lhe express ion.
M inimil..alion TI1C pll)Cess that results in an SOP or POS Boolean expression Ihat contains the fewest fllls.~ i ble liter.. ls pcrlcrm. Producl-of-sums (POS) A form of Booleiln cxpression Ihal is bu~ica ll y the ANDing of ORCli terms. Producllerm TIle Boolean prod uct of IWO or rTKJre liter111s equivitlen t to an AN D operation. S um-ut~products (SOP)
A foml of Boolean expression tha I is basica ll y lhe ORing of ANDed tenns.
Sum term The Boolenn slun of two nr more litemls equivalenl to a n OR opef'".,ltlon.
Varia ble A symbol used to represent 11 log ical quami ly that ca n have:.\ \·ah.!c of J or 0. Ilsuall y i~nated by an ilalic leller. VIIDL A s tml(\ard hardwilrc descript io n languuge. I.EEE Sid. 1076- 1993.
Amwen
I. The (omplerncDl of a variable is always (.1)0
(b) I
(e) equal to the "Minblc
2. The Bocllean expression A + (H)
(I
slim tcrm
(a) a sutllterm
B + C is
(bl ,\ lile nll Icrlll
3. TIle Boolean expressio n (b)
(I
tel) thc illverse of the variable
(e) :.\ product term
hll a COl11plCmellied term
ABeD is pmduCllerm
tc, a literal term
(d) always I
dc~
SELF -TEST •
+
4. The dOnl3 in o f fhe expression ABCD + A B (aJ A and J)
(bJ
I)
CD
+
IJ
(e) A, B, C, and D
only
235
i~
(d) none of these
5. Ac(.'Ord ing to lhe commut ative law o f additioll, (a) AB = BA
(b) A =: A + A
(c) A + (8 + C)
=:
+C
(A + 8)
{ell A + B = /3 + A
6. Accordi ng to the as~oc i3l i \'e law of mu ltiplication, (a) IJ = IJB
(d) 8
(c)A + I3 = IJ + A
(b) A{IJO = (A8K
+ OW +0)
7. According to the distribu tive law, (a )A(B
+ C) =
(b) /I(BC) = A Il C
AB + AC
(c)/I(A
+
I) = A
(d) A + AlJ = A
8. Wh ich one of the following is 110/ a valid n Ile of Boolean algebra'! (II) A + I = I
(b) A = A
(d) A+ O = A
(e) /lA = A
9. Which of the foUowi ng ru les st..1tes that if one input of an AN D gate is always I , the output is equal to the other in put ? (a) A+ I - I 10.
(b )A+A = A
Al,;l,;ording 10 DeMorgan's
(a ) AB = A+B (e) A
+
B
{c) A·A = 1I
t heorem~,
(b) X),Z
+ C =: ABC
I I. TIlt: Boolean ex press ion X
(d) A·I =: A
the fol1 owi nl;; ellua lif Y(S) is (ate) =
X
I,;U/T(...::I :
+ Y+ Z
(d) all of these AIJ + CD represen ts
=
(Il) two O Rs AN Ded together
(b) a 4-input AND gme
(e) two ANDs ORed together
(d) an exclusive-OR
12. An e)(ample of a sum-of-prOOucts expression is
+ B(C -, D) (c) (1\ + /J + C )(A + Jj + c) (II) A
13. An examp le of a
pJ"oduct -of-sum~
+ C) + Ae + 11 + J)C
(bJ liB
+ Ae + ABC
(d) bo th answers (a) and (b)
expression is
+ 8 )(A + B + C)
(a) 11( 8
(b) (II
(c) A
(el) both ;ms wers (a)
14. An exam ple of a standard SOP expression is
A/J + II BC + A /JD (e) liB + liB + AB
+ ACD (d) AIJeD + AB + II (b) AlJC
(a)
15. A 3-variablc Kamaugh map has (a) eight l'cHs
(b) three cells
(c) sixteen cells
(d) fou r cells
16. In a 4- vari able Kamau gh map. a 2-variable product term is produccd by (a) a 2-<.-e1l group of I s
(b) an 8-ccll group of I s
(c) a 4-ccll group of Is
(d)
a 4-cell group of Os
17. On a Kamaugh map. grouping the Os prod uces (a) a product-o f-sums expression
(b) a sum-o f-prod ucts e)(prcssioo
(c) a "don' t care" condition
(d) AND-OR logic
18. A 5-vllria ble Kamaugh map has
(a) sixtCCn cells
(b) thirty-h \lO cells
(c)
.~i xty-four
cells
19. An SPLD that has a programmable AN D array and a fh cd OR UlTay is a (a) PROM
(b) PLA
(c) PAL
(d) GA L
20. VHD L is a Iype of (a) progra mmable logic
(b) hardware descri ption language
(c) progrnrnmabJe array
(el) logical mathematics
21 . In VHD L. a port is (a) a type of entity
(b) a type of architectu re
(c) an input or ompul
(d ) a type of variable
236
•
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
PROBLEMS SECTION 4 - 1
Aoswen to odd-numbered problems are at the end of the book.
Boolean Operations and Expressions I. Us ing Boolean nOTill ion. wri Te an expression That (A. B. C, and OJ itTe 1s.
i~
a I whenever one or more of its variables
2. Write iln expression that is a I only if aU of its varia bles (A. B. C, 0 , and £) are Is. 3. Wrile an expression Ihal is a I whcn onc or morc of ils variablcs CA. 8 . and Cl are Os. 4. Evalume the following opewtions:
+I+
(a)O + O + 1
(b) I
(d) I . I . I
(e) I ·0· I
(e) 1 · 0·0
I
(I") 1 · 1 f.O · I ·
5. Find the values of the vari!lblcs that make each producl tenn I and each sum tenn O.
(a) A8 (e)
II + '8
f. C
(b) ABC
(e) A + IJ
(0 A + 8
(g) ABC
II +
(d)
IJ + C
6. Find Ihe value of X for all possible villues of the variables.
SECTION 4-2
+ OlC (A + IJC)(8 + C)
(a) X "" (A
+ OlC + IJ
(b) X = (A
(dJ X = (A
+ IJ)(1I + 13)
(eJ X =
(e) X = ABC
+ AB
Laws and Rules of Boolean Algebra ,. Identify the law of Boolean all;ebril upon which each of the following equalities is b.1~:
+
(a) AB
(el
+ AC D
CD
(b) ABGD
of
AlJ(CD
f. IJ = IJ
ABC = DOJA
+ EF + Glf)
+
+
An
+ iCD +
CD
Cl lA
= A IJCD
+
A BEF
+ ABGH
8. Identify the Booleilll ru le(s) 011 which each of the following equalities is based:
SECTION 4-3
+ m '- = AlJ + CD + EF
= ABC
(b) AIIB
+ A BC
(e) A(BC + BC) +-AC=A{BC) + AC
ld)
(e) AB + ABC = Ali
(I) ABC
+ C) + AC "" All + AC + AlJ + ABCD = A BC +- AB + 0
+
(a) AlJ
CD
+- ABB
AlJ(C
DeMorgan'J Theorems 9. Apply DcMorgiln's theorems to each ex pression: (a) A
f-
(e) A ( lJ
10. Apply
B
+ C)
DcMorgan'~
(a) AlJ( C (e) (A
(bJ AIJ
(e) ,4- +;-;; B--;+- C "
(d)
(0 A B + CD
(g) AB I CD
(11)
theorems to each exprc~~ ion :
+ D)
(b) "A8"(Cr.D " +"" a"')
+ "'+""' Jj C::-:+""D") + AiiCD
(e) AlJ( CD
Mc (A + lJ)(C + D)
+ EF)(AH +
(d) (A + lJ + C + D)(A B CD)
CD)
J1. Apply DeMorgan's theorems 10 the following: (a) (AlJC)(EFG) 1- (l1lJ)(KLM)
(e) (A
SECTION 4 - 4
+ B )(C + D )(£ +
F)(G
(11) (A
+
+
IJC
+
CD)
+
BC
H)
Boolean Analysis of Logic Circuits 12. Write Ihe BuolC
,"IV- ,
FIGURE 4-55
C
(0 )
(bJ
(0 )
(d)
PROBLEMS
•
237
13. Write the Boolean expression for each of the logic ci rcuils in Figure 4-56.
AD ~
-- x
D
,.)
,,)
,b)
'd)
FIGURE 4-5 6
14. Drdw the lugic circuit represented byc.u:h of the following expressioll i>: (~ )
/I
+ B+r
(b) ABC
(d) IIIJ +CD
(c) AB + C
15. Draw the logic circ ui t represented by each expression: (a) /18 + AB (h) AB + A H + ABC
+ 15)
(e) AIJ(C
(d) A
+
BrC
+ D(l1
... e))
16. Construct a truth table for each of the following Boolean expressions: (b) IIIJ
(a) /I+ 11 (d) (II
SECTION 4-5
+ 8)C
(e) IIIJ+ BC
(e) (A , B )(H ..j. C)
Simplification Using Boolean Algebra 17. Us ing Boolean algebra techlliques, simplify the following expressions as Illuch as possible:
+ B) II(A + AB)
+ AB) AHC + ABC + A8C
(a) A(A
(b) A(A
(d)
(e)
+
(e) BC
BC
18. Using Boolellll algebra. simplify the fo llowi ng expressions: (a) (/I
+
B)(A
+ C)
(e) AB + ABC'" A (e) All
+ (/\
I-
(b) All .... ABC
(d) (/I
+ A BCD + A BeDE
+ A)(AII + AliE)
8)C + All
19. Using Boolean algebra, simplify e,!ch expression:
(a) liD + B( D + E ) + 15(D + F) (e) (lJ
+
+ BC)(B + D) + C(lJC + AC)]
BC)( B
(b) ABC
+ (A + B + C) + ABCD + A B(CD) + (AlJ)CD
(d) /l BCD
(e) ABqAlJ 20. Determine which of the logic circuits in fi gure 4-57
ill'C
C
FIGURE 4 - 5 7
R-
- - -L /
A -------L~
,.,
x x
'0'
p ~>-, (cl
A
II A C
"
,d)
,
238
•
BOOLEAN ALGEBRA AND l OG IC SIMPLIFIC ATION
SECTION 4 - 6
Standard Form.s of Boolean Expressions 21. CollVcrt (he following expressions 10
+ B)( C + 8)
(.. ) (II
(h) (II
sum-of~produci
+ DC)C
(SOP) forms:
(e) (II + C)UIll + AC)
22. COlwcI11hc follo\\ ing cxpressions 10 SLim-of-product (SOP) f011115: (1I) IIIJ
+
CD(1I8
+
(b) AB(B(:
CD)
+ 1JD)
(e) A + 8 [IIC + (B + C)DJ
23. Define Ihe domain of each SOP cxpre!osion in Problem 2 1 i1nd COnVl"f1 the expression to Sl
SECTION 4-7
Boolean Expressions and Truth Tables 29. Deve[op a tru th table for each of the follOWing standard SOP expressions:
(b, XYL + XYz + XYZ +
(a) IIBC + :\lJ(: + ABC
xYz + xrz
30. Develop a !rulh table for each of the following stand.1rd SOP expressions:
(a) ABCD (h) WX¥Z
+ A8CD + ABCD \· 1\8(;15 + IVXtZ + ",;\')'Z + II'xrz +
WX}'Z
31. Develop a tru th tahre fo r each of the SOP expressions: (a)
A8 + ABC + A(; + ABC
(h)
X + rZ + wz + XYZ
32. Develop a truth table for each of lhe stnndurd POS expressions: (a) (A +
(b) (A
+
B + C)(A + B + C)(A + "ij + C) IJ + C + D)(A + Ii + C + (5)(A + B + C + D)(A
t· II
+ C + D)
33. Develop a trUlh lable ror euch of (he standard POS expressions:
(a) (II (b) (A
+ U)(A + C)(A + /J + C) + BHA + "ij + (;)( IJ \- C + DHA +
8
+ C -I D)
34. For each Truth !able in FIgure 4-58. derive a standard SOP and ,I stilndard POS ex pression.
0000 000 1 0010 00 [ [ U l 00
oI a J ot [ a o[ [I
OuO
0
00 1
I
OIU UI I
0 0
100 101 10
I I
000 001 0 10
oI
I IU O
101 10
0
I I I ("
fiGURE 4 - 51
1000 1001 [ 010 10 1 I [ 100 J 101 I I 10 [ I 1I
0 0 0 0 0
I I I (bJ
('J
0000
I
Door
0
U010 00 [ 1 01UU a 10 1 a J 10 01 11 1000 1001 1010 [U I I [ 10 0 1101 I I 10 IIII
U I 0
0 I
0 0 I U
0 0 (dJ
0 0 I
0 I U I
0 0 0 I 0 0
PROBLEMS
SECTION 4-8
•
239
The Kamaugh Map 35.
DrdW
11 3-variltbk Kamaugh map and label each cell according 10 ils bimuy value.
36. Dmw
SECTION 4 - 9
Kamaugh MAP SOP Minimization 38. Use a KUl11uugh map to lind the minimum SOP fonn for e
ABC + ABC + ABC A( BC + BC) + A{BC + BC)
(a)
(e) 39. Usc
{aJ
(hJ (d)
AC(B + C) ABC + /l8C + ABC + ABC
Kurnaugh map to simplify each expression loa min imum SOP form:
ABC + ABC + ABC + ABC
(b)
AqB "'"
lJ (lJ
+
ell
(e) DEF + DEF + D£F 40. Expand cach cJ(prcssion to a staJldurd SOP (orin: (a)
(b) A + IJC
AB + ABC + AlJC ACD + BCD + ABCD
(e) /lBCD +
(dl
AB + iHCD +
CD
+ rCD + AlJCD
41 . Minimize eneh expression in Problem 40 wi lh a K"rnaugh map. 42. Usc a Karnaugh map to reduce each (a) II
expres.~io'l
to a minimu m SOP (unn:
+ BC + CD
(b) ABCD + ABCD + !\IJCD -I AIlCD (e)
(d) (e)
AB(eD + CD) + AR(CD (AB + AB ){CD + CD) All + AB + CD + CD
i CD)
+ ABCD
43. Reduce the function sp!:cified in the truth table ill rigUtC 4-5910 ils mi nimum SOP form by usi ng a Kamaugh map. 44. Use the Kamaugh nmp melhod 10 implement the mi nimum SOP ex pression for the logic function specified in the tru th table in Figure 4--60.
Inputs
Output
ABC
X
000 0 0 0 1 0
I
o
I
0
I
o0
0 0 0 0
0 0 0 0 0 I 0 0 0 0 0 0
0
I
0
I 0 I I
0
0 0
FIGURE 4-59
0 I I
I I
0 I I
0 0
0
0
0 0 0 0 0 0 0 0 I 0 0
0 I 0
I
0 I
0 I
0
FIGURE 4 - tJO
45. Solve Problem 44 for a si(uatioo in which the last six hi nary combiml.1 ions are not allowed.
240
•
BOOLEAN ALG EBRA AND LOGIC .s IMPLIFICATION
SECTION 4-10
kamaugh Map POS Minimization 46. Use a Karnaugh map to find the minimum POS for each expression :
+ B + C)(A + 8 + C)(A + B + C) (X + Y)( X + Z)(X + Y + Z)(X + Y + Z) A(B + C)(A + C)(A + 8 + C)( A + IJ + C)
(a) (A (b) (e)
47. Use a Kamaugh map to simplify eac h expression 10 minimum POS fon n:
B + C .J. D)(A + B + C ~ + Y)(W + Z)(X + Y + Z)(W
+ B + C + 15)
(a) (A +
D ){A
(b) (X
~ X+ Y
Z) 48. For the funct ion spI:cificd in Ihe truth table of Figure 4-59. dete rmine the minimum POS expression using
I-
,I Karnaugh map.
49. Determine the mini mum PO..<; expressio n for the fu nct ion in the truth tab le of Figure 4-60.
SO. Cunvert coch of the following POS expressions Kflmflugh map: (aJ (A I- 8 )(A + C)(A + Ii + C) (b) (A .\ /J){A + Ii + C)(E + C + D){A
SECTION 4 - 11
[0
min imulll SOP expre~s ions using a
+ U + C + D)
Five-Variable Kamaugh Maps 51. Minimize the following SOP expression using 3 Karnaugh nmp:
X = AIJCDE + ABe D£ + ABGDE + ABCD e
+ AnCDE + ABCDE
+ ARCDE + AReDE + ABeDf; + ABeDE 52. App ly the Kamaugh map method
10
Illinilllil.e Ihe followinJ:! SOP e x prcs.~ ion :
+ VWXYl + VWXYl + n vxYz + IIWX rZ + VWXYZ + V\VX }'Z + VWXYZ + VWXYZ
A "" V WXYl
SECTION 4-12
VHDL (optional) 53. Write a VHDL prognun for the logic circuit in Fig ure 4-6 1. FIGURE 4 - 61
,\H - -r-"
C - '_ /
"=C)-£ , F
x
54. Write II progn,m in VH DL for d lC exp.-eK~jOn
Y = ABC + ABC + ABC + AIJC Digital System Application 55. Ir you iJre required to choose a type of digi wl di~pliJY for low liJ:!ht conditions. will yoo select L ED or LCD 7·scgrnem di spl,,),s? Why"!
56. Explain why the codes 1010. JO I I. I [00. 1101. 11 10. lIIld [ III fall into the "don' t care" category in 7.segmem display applications. 57. Forseg1llenl b. how mml)' fewer gates and inverters does it take to implement the minimum SOP expression than the stand;ud SOP exprcssion'! 58. Repeat Proble m 57 for the logic for segrne ms c through It.
Special De sign Problems 59. The logic for segmcl1l ll in Figure 4- 52 prodUl'CS a HIGH outpu t to acti vate the segment and so J o Ihe cirell ils for each of the other segments. If a Iype o f 7-scgment display is used that req uires a LOW to llClivate eltch segment, modify the ~egmenL logIC accord ilJgly.
ANSWERS
•
24 1
60. Redesign the logil;: for segment a using a min im um POS IIpproach. Which is simpler, min imum POS or the mi nimu m SOP?
61. Repeat Problem 60 for segments b th rough K. 62. Summarize the results of your redesign effol'! in Problems W and 6 1 and reccmmend the best design based on fewer ICs. Speci fy the I)' PCS of ICs.
Multisim Trouble shooting Practice 63. Opcn file 1'04-63, appl y input signals, and observc the operation o f the logic circui t. Dclemlinc whethcr or not a fault exists. 64. Opc n file 1'04-64. apply input Sigllills, and observe the operm ion of the logic dreuil. Dctcnninc whelhcr or 001 a faliit exists. 65. Open filc 1'04-65, appl y input signals, and observe Ihe ope rati on of the logic circuit. Dclcnninc whether or not a faul t e xisL~.
SECTION REVIEWS SECTION 4 - 1
Boole an Operations and Expressions I. A "" O = I 2.A = I.B = I,C = O;A+ B + C = 1+ I + O = O+ O + O = O 3. /\ = I, B = O. C = I;IIBC = )· 0 '1 = ) . ) . J = 1
SECTION 4 - 2
Laws and Rules of Boolean Algebra I. /\ + (lJ + C+ D) = (/\ + B+ C) + 0
SECTION 4 - 3
SECTION 4 - 4
2. A(B
DeMorgan's Theorems I. (a) 1iiK: + (0 + £) = A -I B + C + DE (e) II + B + C + D E "" ABC I- 0 I- E
+C+
(b) (II
D) = li B I- IIC
+ liD
+ B)C = A B + C
Boolea n Analysis of Logic Circuib I. (C + D)8 +11 2. Abbreviated tnlth tabJe: The expression is a J whcn 11 is J or when B and C are Is or whcn B and D are Is. The expression is 0 for all other variable combillatiolls.
SECTION 4 - 5
Simplification Using Boolean Algebra I. (8) II + II IJ + ABC = II ( h) (A + B)C + IIBC := C(A + /J) (e) ABC( BO + CDE) + ;\C = II(C + n DE) 2. (a) Original: 2 AND gates. I OR gate. I inverter; Simplified: No gi!lCS (stmigh t connection) (bJ Origillal: 2 OR gales, 2 AN D gales, t inve rtcr; Simplified: I OR gate, I A ND gille, 1 invel'!er
(c) Original: 5 AN D gatcs. 2 OR gates. 2 invcrters; Simplified: 2 AND gates. 1 OR gate, 2 inverters
SECTION 4 - 6
Standard Forms of Boolean Expressions I. (a ) SOP
2. (a) ABC D (e) Already
(b) sI311dardPOS
+ ABCD + ABCD
ee) slandardS OP !.
(d) POS
ABCD + ABCD + ABCD + ABCD + ABCD
~tandard
3. (b) Already standard
00 0+~+~~+i +~( II +B +~ ~ + B +0
242
•
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
SECTION 4 - 7
Boolean Expressions and Truth Tablet 1. 25 = 32
SECTION 4 - 8
2. 0110
-t
WxrZ
3. 11 00
1V
-t
+ X+ Y + l
The Kamaugh Map I. (u) upper left cell : 000
(b) lower right cell : 10 1
Ie) lower left cell: 100
(d) upper righ t cell: 00 1
2. (u) upper left cell : XYZ
XYZ
(b) lower right cell: Xl'Z
(e) lower left (;ell:
(b) lower ri gh t cell: 10 10
(c) lowerleftccll: 1000
(d) tipper ri ght cell: X Yl
3. (a) upper left cell : 0000 (d) upper ri ght cell: 00 10
4. (u) upper left cell : I~..!'~ (d) uppcrri g ht cell : IV XYZ
SECTION 4-9
(e) lower left cell:
WXYZ
Kamaugh Map SOP Minimization I. l;oi-(:e ll map fo r 3
2. li B
3.
(u) (b )
(e)
(d)
SECTION 4-10
(bl lower rig ht cell: IVXl'Z
v~riables:
1(')«11
m~p
fo r 4 vHillbles
+ li e + ABC ABC + A IJC + II BC + AlJC A BC + A lic + AllC + ABC + ABC + ABC A BeD + ABeD + ABe D + ABCD + A/K D + ABCD + ABCD + AllCD ABeD + Aile D '" II BCD + Ail eD + II Be D'" AllCD + AileD + A BCD + ABeD + ABeD + Alien
Kamaugh Map POS Minimization I. In nw ppin1! a POS ex pressio n. Os :lre placed in cells whose value makes the sl:lnd:lrd sum tcnn lc ro: and in mapping an 501- cxpre~sion I s are plao.:nl in (."f;lIs having the SlIme valueS as the product tmns.
2. O inthe 1011 cell: A + B + C + D
SECTION 4-11
3. I in Ihe 0010 cell: A BCD
Five-Variable Kamaugh Maps I. Thcre
SECTION 4 - 12
VHDL (optional' I . An HOL is a hllrdware de.~cri ptiOiI lang uage fo r progr.unmable logic. 2. Enlit y and arc hitectu re
3. The enti ty spt:cifi es the inplltl> and ou tput s of a logic function. 4. 11lc: architec tu rc spl."Cifies o perntiOiI of a I01!ic function .
RELATED PROBLEMS FOR EXAMPLES 4-1 A + B = OWhcll A = I and IJ = O. 4-2 IIB = Iwhen A = O andB = O. 4-4 IV + x + Y +z
4--3Xrz
4-5 ABeD E
4-7 AllCD =A+ B + C+D
4-(i
4-8 AH
(A +
B+
4-9 CD
4-10 ABC + AC + Ali 4-11 A + B + C 4-12 ABC + All ·' AC + AB + 4-13 1VXl'Z
+
IVX rz
+ WXtZ + WXr-L +
4-140/ 1, 101 , 11 0, 0 10, I!LYes
CD)£.
IVXJZ
+
Be
IVXYZ
ANSWERS
4-1 9 See Table 4-12. TABLE 4- 12
TABLE 4 - 11
A
0
0 0
2 43
4--17 SOP and PQS expres~iolls arc eq uivalent.
4--16010, tOO, 00 1, 111, OI 1.Yes
4- 18 Sec Table 4- 11.
•
0
0 0
0
0
C
X
0
0
0
0
n
,
0
,
0
0
0
0
0
0
0
8
0
0
0
0
0
n
0 0
0
0 0
0
4- 20 The SOP and POS CXprcSSiOlls arc C
4-22 See Figure 4-63.
4-23 See Figure 4-64. 4-26 X - B ,- Xc
4-25 No olher ways
4--21 Sec Figure 4-62.
4-24 See Figure 4-65.
+ lieD +
CD
4-27 X = D + ABC + 8C + AlJ 4-28 Q = X + Y 4-29 Q = XYZ
+
U.~
+ WI'Z
4--30 Sec Figure 4-66. C
A
Ali
0
CD
1
8
1
01
11 1
1
FIGURE 4 - 6Z
CD
00
11
01
11
M1
01
C
10
00
01
11
10
" "
o1
"
,
1
0
AU 1X1
1
1
01
1
,
11
00
00
10
00
,
CD A8
1
1
01
1
1
11
10
FIGURE 4 - 63
FIGURE: 4 _ 64
'0
, , , 1
• FIGURE 4- 65
4-31 Q = (X
X
+
y + Z)(\v + X
+ Y +Z)
4-34 Y = DE+AE + 8Ct:
4-35 X
¢::: (/\
:JIId B)
!I01"
(C liod D);
11
SELF-TEST 10
FIGURE 4 - 66
"
01
00
10
+ Y)(X + Z)CX' + Y + Z) 4-,.12 Q = (X + y+ Z)(W+X -\- 2 )( W + 4-..13 Q = YZ -I- X Z + IVY + XYz
00
I. (d )
2. (a)
3. (b)
4. (e)
5. Cd )
6. (b)
9. (d)
10. (d)
J J. (e)
12. (b)
13. (b)
14. (e)
17. (a)
18. (b)
19. (e)
20. (b)
21. (e)
7. (a)
IS.
(a)
8 . (0)
16. (e)
11
10
1
1
1
,
,
CHAPTER OUTLINE
5-1
Basic Combinational logic Circuits
5-2
Implementing Combinationallogit:
5- 3
The Universal Property of NANO and NOR Gates
5-4
Combinational logit: Using NAND and NOR Gates
5- 5
lOgit: Circuit Operation with Pulse Waveform Inputs
5-6
Combinational logit: with VHDl (optional)
5-7
Troubleshooting
I:EC
Digital System Application
CHAPTER OBJECTIVES Ao
Use AND-OR and AND-OR- Invcrtcircuib to implement Ium-
of-prodU<;b (SOP) and product-of-IUITK (POS) expressions Write the Boolean output expression (or any comhination.al logic circuit Develop a truth table from the output e>
Ule the K
Design a combinatianallagic circuit far a given Boolcan output
INTRODUCTION
expres.ion
Design a combinational logic circuit far a given truth t,jb!e Simplify a cam binational logic circuit ta it. minimum form UH' NAND gatEi ta implement any combinational logic function Ule NOR gates to implement any combinational logic function Write V1-iDl programs for simple logic cin::uit. Traubloooot ~ulty logic circuit. Troubleshoot Jogic circuit. by using lignal tracing and waveform analysis Apply combinational logic ta a system applic.
In Chapters 3 and 4, logic gates were diiOJlsed on "n individu", wlil " nd in simple combin"tionl. You were introduced to SOP and POS implementations, which are basic forms of combination"llogic. When logic gates "re connected together to produce" spedfied output for cemin specified combinations of input variables, with no Itor"ge involved, the resulting circuit is in the Qtegory of combinational'ogic. In combin"tion"l logic, the output level il "t "II times depende nt on the combination of input levek This ch"ple r exp"nds on the m"ten,,1 introduced In earlier chapters with " cover"ge of the "Il.llysll, design, " nd troubleshooting of various combin"tion"llogic circuits. The VHDlstructul7I1 "pproach is introduced "nd "pplied to combination",logic. •••
KEY TERMS Universal gate
Signal
Negative-OR
Node
Negative-AND Component
• Signal tr"dng
DIGITAL SYSTEM APPLICATION PREVIEW
The Digitill System Application iIIustr"tes the concepts tilught in this ch"pter by demonstrilting how combinational logic c.Jn be used fo r" specific purpose in " p,"ctic.J1 "pplication. A logiC circuit is used to control the level "nd temper"ture of" fluid in " stor"ge tank. By operating inlet and outlet valvel, the inflow and outflow " re controlled based on level-remor inputs. The fluid temper"ture is controlled by turning a he"ting e lement on or off b"led on temper"ture-semor inputs. As an option, the use ofVHDl for describing the logic is disculled.
"'SO
WfBJIT~
Study "ids for t his ch"ptcr "re "vail"ble "t
Ihttp://www.prenhall.com/floyd
24'
246
_
5-1
COMBI NATION AL l O GI C A N ALYS IS
BASIC COMBINATIONAL LOGIC CIRCUITS In Chllptcr 4, you lcamed that SOP expressions are implemenled with an AND gate for each prod UL1 leon and one OR gHte for summing all of the product tenns. As yOll know. this SOP implemenllltion is C
AND- OR Log;c AND-OR logic produces an 50P expresw'on.
Figure 5- I(a) shows an AND-OR circui t consisti ng o f two 2-input AND gales and onc 2-input OR gate; Figure 5- l(b) is the ANS I standard rect,mgular outline symbol. The Boolean expr~sions for the AND gate outputs
FIGURE 5 - 1
An example of AN~-OR logic. Open file F05-0 1 to verify the operatio n.
,\
, ---<- --H-
SOP
--L_/
"
X = AB+C/)
c - -r-"
C
n-
D
--L--'
(a) t..ogil.· d i,,::r:un (ANS t SI" n,\:ml ,'i~!ir\lC!i\"e
&
{bl ANSI
"
x
&
~!;"I(l;Jrd
reclanI;:ul ar outline
~hapc ~ymbols,
TABLE 5 -t
Truth ta ble for theANO- O R logic in
Figure 5-1 .
INPUTS ABC
D
AB
OUTPUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CD
X
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
1
\
U
0
U
0
0
1
0
0 0
0
0
0
\J
0 0
0
0
0
0
1
0
0
0
0
0 0
0
0
0
~Yl1lbol
BAS IC CO M BINATION A L LOGIC CIRC UITS
•
An AND-OR cirCJti, directly imp/emellfs (1/1 SOP expression. aSSllming 'he comp/emems (if any) of the )lariable.~ are ami/able. TIle opcT
For a 4-input AND-OR logic ci rcuit, the o utput X is HIG H ( I) if both input A a nd input IJ arc HlGH (1) or both input C and input D a re HIG H (1).
I
EXAMPLE 5-1 In a l:erlain chcmical-pr
.1
B
C
I G,
J G'8 j
Y-
I G,
FIGUR£ 5-2
Related Problem·
Write the Boolean SOP expression for the AN D-OR logic ill FiEurc 5- 2. - A nswer.; are at the end of the chapter.
AND-OR-Invert logic W hen the OUl pot of an AND-OR c ircuit is complemellled ( inverted ). it results in an AND-OR-Invert circuil. RecHl1 thai AND-OR logic directl y implements SOP expressions. POS expressions CHn be implemented wi th AND-OR-Invert logil:. This is illustrated as fo llows, starling with a POS expression and deve loping the l:orresponding AN IJ-OR-Itl\'ert expression.
x ~ (X + 8He + D)
~ (AB)(CD) ~ (AB)(CD ) ~ AB
+ CD ~ AB + CD
Low-tevel indica!....
24 7
2 48
•
COMBINATIONAL LOG IC ANALYSIS
The logic di<1gram in Figure 5- 3(<1) shows an AND-OR- Invert circuil and the developIllen! of the POS out pul expression. The ANSI standard I"t-'Ctangu!af outline symbol is shown in part (b). In general, an AND-OR-Invertcircuil can have any numbcr of AND gates c
An ANO-OR-Invert circuit produces a POS output. Open file F05-03 t o verify the operation.
"
FOS
,\B+cn
B
,IB + cn = 1,1 ... Bid" + ii,
A
&
>1
B
C
C
n
n
(,)
(b)
&
T he OfXmtion o f the AND-OR-Invert circuit in Figure 5- 3 is slaled as follows:
For 11 4-input AND-OR-I nvert logic circuit, the output X is tOW «(I) if both input A and input lJ ~Ire lUGH (1) or both inl)ut C a nd input D m"C lUGH (1). A truth lablecan be developed fro m the AND-O R truth table in Table 5- 1 by simply changing all Is to Os and all Os to Is in the outpllt column.
I
EXAMPLE 5 - 2 TI1C scnsors in the chemical tanks of Example 5- 1 arc being replaced by a new model that produces a LOW voltage instead of a HIGH voltage when the \evel of the chem ical in the lank drops below a critical point. Modify the circuit in Figure 5-2 to opcmte with the different input levels and still produce a HIGH output to activate the indicator when the level in any two o f the tanks drops below the critical point. Show the logic diHgnull. Solutlon
T he AND-OR-Invert circuit in Figure 5-4 has inputs from the sensors on tanks A. B. and C as shown . The AND gate G 1 checks the levels in tanks A ,md B. gHlt! G 2 checks tanks A and C, and gate G3 checks tan ks Band C. When the chemicallevcJ in any two of the tanks gets too low, each AND gflte will have ;t LOW on HI least one input causing its oufputlO be LOW and, tim", the linal output X fro m the inverter is HIGH. This HIGH outpu t is then used to llctivatc an indicator.
A
II
C
~>~
J.ow·Jc,·el indi<:alor
I I G, r FIGURE 5-4 Related Problem
Write the Boolean expression for the AND-OR-Inven logic in Figure 5-4 and show thm the OUtput is H1GH ( I) whell any twO of the inputs A, B, and C are LOW (0).
BASIC COMBINATI ONA L LOGIC CIRC UITS
•
249
Exclusive-OR logic T he exclusive-OR gmc was introduced in Chapter 3. Although. because of iL<; importance. this circuit is considcrcd a type of logic gutc with its own uniquc symbol. it is aClually a combination Of lwO AND gales, one OH gate, and lwO inverters. as shown in Figure 5- 5(u). Thc two ANSI standard logic symbols are shown in parts (b) and (c) .
The XOR gate is actually a combinatioo of other gates.
.\- -r.:--r,
... FIGURE 5 - 5
ExduWe-O R logiC diagram and symbols. Open file F05-05 to verify the operation.
X ", AIJ + MJ
:JD-- x
/I -,~'-----L"'-/
(n)
Lo~i",
(b) ANS I dist inctive ~ h :J.pe symbol
oingrarn
(el ANS I rcctllo!!ulnr
outline symbol
The output expression for the circuit in Figure 5- 5 is x = AB
+
AB
Evaluation of Ihis expression resufls in the truth table in Table 5-2. Notice thai the out put is HIGH only when the two inputs are at 0.l?J)()S~ levels. A special exclusive-OR openttor ED is oflen used, so the expression X = AB + AB can be Slated as " X is equal 10 A exclusive-OR /)' and can be written as X = AeB TABLE 5 - 2
Truth table for an exclusive-OR.
o o
o
o
o o
Exclusive-NOR Logic As you know, the complement of the exclusive-OR func tion is the exclusive-NOR. which is derived as follows:
x ~ AB + AB ~
(AB)(AB) ~ (A + B)(A +
Ii)
~ AS
+ AB
Notice that the out put X b HIGH only whcn the two inputs. A and ll. itfC m the Silmc level. The excl usive-NOR can be implemented by simply inverting the o utput of..£l!!'CXcfusivcOR.
FIGURE 5 - 6
Two equivalent way. o f implementing the exclusive-NOR. Open file F05-06 to verify the operdoon. 11 (3) X ", AU +A B
(b) X "' AR+AB
250
_
COMBINATIONAL lOGIC ANALYSIS
SECTION 5-1 REVIEW Amwers are at the end of the chapter.
1. Determine the output (lor 0) of a 4-variable AND-OR-Invert circuit for each of the following input conditions:
(a) A = 1, B = 0, C (e) A ~ O. 8 ~ I. C
= 1,
. .
.
( b)A ~ 1 8 ~ 1 C ~ OD ~ I
D= 0
~ I. D ~ 1
2. Determine the output ( l or 0) of an exclusive- OR gate for each of the following input conditions:
(a) A (e) A
~
1. 8
~
0
(b) A ~ I. B ~ 1
~ O.8 ~ 1
3. Develop the tfuth_tilble ~r a cerpin~-inpu~ogic circuit with the output expr~ion
X = ABC
+ ABC + ABC + ABC + ABC.
4. Oraw the logic diagram for an exclusive-NOR circuit.
5-2
IMPLEMENTING COMBINATIONAL LOGIC In th is section. examples are used to illustrate how to implemem a logic cirellit from a Boolean expressio n o r a trulh tahle. Minimi73\ion o f a logic c ircllit us ing the me thods covered in Chapler 4 i)o a lso included. A fter completing this section . you s hould be ab le to _ Implement a log ic c ircu it fro m a Boolcl.m ex pression _ Implement a logic circuit from a trut h tub le - Mi n imize a logic ci rc llit
From a Boolean Expression to a logic Circuit For every Boolean exprenion there is a logic circuit, and for every logic circuit there is il Boolean expression.
Many control i logic operatiom to be performed by a computer. A driver prog... m n. iI control program that is used with compute, peripher.lli. For example, '" mouse driver requires logic tests to determine if '" button hal been pre1!oo and further logic operatiom to determine if it hal moved, either horizontally or vertically. Within the heart of a mi
Let's examine the fo llow ing Boolean expressio n:
X = AB+ CD£ A brief inspection shows that th is expression is composed of two te rms. AB and CDE, with a domain of fi ve variables. The first term is formed by ANDing A with B, and the second term is forme d by AN Ding C. D. and £. The IwO te rms are then ORed to form the o utput X. These operations are indicated in the structure o f the expressio n as fo llows:
j.rx ~
AB
-'r-
+
-
-
ANIJ
CD£
~ - - OR Note that in this p
Logic circuit for X = AB
+ eDE. X = IH+CDE
IMPLEMENTING (OMBINATtONALLOGt(
•
As another example, let's impicment the following exprel'lsion:
x~
AB(Cb
+ EF)
A breakdown of this expression shows that the terms AB and (CD + EF) are ANDed. The term CD + EF is fo rmed by fi rst ANDing C and Dand ANDing E and F, and then ORing these two tenns. This Slructure is indicated in relation to the expression as follows:
llL,-----
X = AB(eD
+
AND
NOT OR
EF)
t
t
AND
Before you can implement the linal expression, you must crellle the sum Icnn CD + EF; but before you can get ~ i s term ; you Illust.£fcate the prodm.:t terms CD and EF: but before you can get the term CD, you must create D. So, HS you CIUl sec, the logic opemtions must be done in the proper order. The logk gales required to implcmcnt X = ARCCD + EF} arc liS follows: 1. One inverter to form D 2. Two 2-input AND gates to form CD and EF 3. One 2-input OR gatc to form
CD +
£P
4. One 3-input AND gate to fDlm X TI1C logic circuit for this expression is shown in Figure 5- ti(a). Notice thm there is a maximum of fom gates and an inverter between an input and output in this circuit (from input D to output). Often the total propagation delay tilTIe through a logic circuil is a mHjor cOllsidernlion. Propagation delays are l1dditivc, so the more gates or inverters between input and outplll. the greater the propagation delay t~e. Unless an intermediate term, such as CD + £F in figure 5-8(a), is required as an output for some other purpose. it is usually bcslto red uce a circuit to its SOP foml in order to reduce the overall propagation delay lime. TIle expression is com'en ed to SOP as follows, and the rcsulting circuit is shown in Figure 5-8(b).
AB( CD + EF) = ABCD + ABEF
H----------------c ----"---; - ,
X = A8(CV+EI' )
/J
/J
X = A8('f) + ABI:.F
F --~
F'- - - - -- l_
(.,
1M Sum-of-products impleme ntation of the cirt:u it in
FIGURE 5 - ' LogiC ciR:uib for
X "" AB( CD
+ EF) = ABCD + ABU.
From a Truth Table to a logic Circuit Ir YOll begin with a truth wblc insl!:lld or an expression, you can write the SOP expression from the truth table and then impleme nt the logic circuit. Thblc 5-3 specifies a logic function.
p3r1
(a)
251
252
•
COMBINATIONAL LOG IC ANALYSIS
TABLE S- 3
INPUTS ABC
0
0
0
0
I
0
I
PRODUCT TER.M
0 0
0
0
OUTPUT X
0
ABC
0 0
ABC
0 0
0
0
0
0
The Boolc,m SOP expression obwi ned from Ihe tmlh lable by DRing the product terms for which X = I is X = ABC
+ ABC
The first lenn in the expression is formed by ANDing th~t hree ~ari ables A. B. IUld C. 1lle second term is formed by ANDing the three variables A. B. and C. ~heJogic g~les rCtluircd to implement Ihis expression are as follow~ three in\'~~rs to form the A, B. and C variables: two 3-input AND !,!ates to form the tenns ABC aoo AB C; and one 2-input OR gate to fonn the fi nal output function, ABC + ABC. T he im plemenl
Logie circuit for X = ABC + ABC. Open fil e FQ5-09 to verify the operation.
H-t+t---1
X = IIHC+AlJC
c--Y
I
c
All(
EXAMPLE 5-3
Design a logic (..;rcuit to implernenllhc oper
INPUTS ABC
0
0
0
0
0
0
OUTPUT X
i PRODUCT TERM
0
0 0
0
0
ABC
0
0
0
0
ABC
0
ABC 0
IMPLEMENTING COMB INATIONAL LOGIC
Solution
Notice that X = expression is
•
253
for only three o r the input conditions. Thererore, the logic
x=
ABC + ABC + ABC
T he logic gales rCtluired arc three inveners. three 3~ inpul AND gates :md onc 3-illput OR gate. The logic circuit is shown in Figure 5- 10. FIGURE 5-tO
C
H
A
Open file F05-10 to verify the oper.,tion.
~\~~
AHC
IHC
)
x
-\lIe
Related p,.oblem
i
Determine iflhc logic circuit of Figure 5- 10 can be simplilicd.
EXAMPLE 5-4
Develop a logic circuit with rour input variables Ihal will only produce a I out put when exactly three input vmiables are Is. Solution
Oul of six teen \X>Ssible combinations of four variables, the combinations in which there are exactly three Is (Ire listed in Table 5-5, along with the corresponding proouct term rOT each.
TABLE 5 - 5
ABC
D
PRODUCT TERM
o
ABCD ABCD ABeD ABel)
o o o
The product terms are ORed to gel lhe following expression:
X = ABeD + £iiCD + Alicv + ABCD This expression is implemented in Figure 5-11 with AND-OR logic.
254
•
COM8 1NATIONAl lOGIC ANALYSIS
FIGURE 5-11 J)
Opeo file FOS-11 to verify the operation.
C
H
II
j
I
I
~
vvy AHCI)
".BCD ~
AHCt)
.. Hcn Related P,oblem
I
DClermine if the logic c ircu il of f.igure 5 I I cnn be simplified.
EXAMPLE 5 - 5
Reduce the combinational logic circuit in Figllre 5- 12 to a minimum form. FIGURE 5 - 12
Open file F05- 12 to verify tholt thK circuit i~ eqoNalent to the circuit in figure 5- 13.
H
x
Solution
The expression for the output of the circuit i:; X =
(ABe)C + ABC +
0
Applying I)eMorgan's theorem and Roole.Ul algcbm.
+ B + qc + A+ B + C+ 0 = AC + BC + CC + A + B + C + 0 = AC + BC + C + A + 8 + I: + D = C(A + B + I ) + A + B + D X=A+B +C+ D X = (/\
The simplified c ircuit is a 4- input OR gare as shown in Figure 5- 13. FIGURE 5-1)
Related Problem
Verify the mini mized cxpres:;ion A + B
+C
I D using a Ka rnaugh map.
x
IMPLEM ENTING CO M BINATI ONAL LO GI C
•
Minimize Ihe combinalionallogic circuil in Figure 5- 14. Inverters for the complemented variables arc not shown. FIGURE 5-t4
Solution
The outpUl expression is X =
ABC + ABeD + ABCD + AB CD
Expanding Ihe fi rst term to include the missing variables D and D.
ABC(D + D) + ABCD + ABCD + "ABcD ABeD + ABeD + ABeD + ABeD + ABeD
X = =
This expanded SOP expression is mapped and simplified on the Karnmlgh map in Fig ure 5- 15{a). The simpli fi ed impleme ntatio n is shown in pan (b). Inverters are not shown . CD
00
00
01
I
I
" -
10
-
-
/1(
A (
- ---i, '
,, - --lLJ
01
"
I
IU
I
-
-
I
loJ
If- ACt)
11 - -.--___ , - ---!._-' (bl
FIGURE 5-t5
Related Problem
I
SECTION 5-2 REVIEW
De velop the POS equivalent of the circu il in Figure 5- 15(b).
1. Implement the following Boolean expreuiom as they are stated:
(. ) X = A8C+AB + AC
(b) X = AB(C + DE)
2. Develop a logic circuit that will produce a I on its output only when all three inpun are 1s or when all th ree inputs are Os.
J . Reduce the circuits in Question 1 to minimum SOP form.
255
256
•
COMBINATIONAL LOGIC ANALYS IS
5-3
THE UNIVERSAL PROPERTY Of NAND AND NOR GATES Up to this point. you have studied combinational circuits implemcnted with AND gates. O R gates. and inverters. In this section. thc univcrsal property of the NAND gate and the NOR gate is discussed. The universality of tile NAND gate means thai it can be used as an inverter and that combinmions of NAND gates can be used to implement the A ND, O R, and NOR operations. Similarl y, the NOR gale can be used to implement the inverter (NOT), AN D, OR, and NA ND operations, After completi ng this section, you should be able to • Usc NA ND gales to implement the invel1er, the AN D gate, the O R gate, and the NOR gate . Usc NOR gates to implement the invel1er, the AND gate, the OR gate, and the NA ND gate
The NAND Gate as a Universal Logic Element NAND gates can be used to produce any logic function .
The NAND gate is a unh'crsal gute because il can be used 10 produce tnc Nar. the AN D, the OR. and tnc NOR functions. An inverter can be made from a NAND gate by con llCcting all of the inputs together and creati ng. in effect, a single input. as shown in Fi!:urc 5- 16(a, for a 2-input gale. An AND function call be genemled by ttx: U!>C of NA ND gates alone, as shown in Figure 5- I6(b), An O R f unction can be produced with only NAND gates. as illustrated in part (d. Fi nally. a NOR fu nction is produced a<; shown in part (d).
FIGURE S-U
Universal application of NAND gates. O pen file! F05- 16(a), (b), (c), and (d) t o verify e
(n) One NA ND ~ale IMd as ru1 in\'t:n er
equivalenciel.
(b) T\Om
NA ND glltet; used lIS an AND gUie
A
H
(el l1m~ NAND g:IIC!> u...cd
...
.\
H
(d) Four NAND gHtes used lIS a NOR gale
In Figure 5- I6(b), a NAND gate is used 10 inve rt (complement) a NAND outpu( to form the AN D funct ion, as indicated in the followi ng equation:
X = I\B = I\B
TH E UN IVE RSAL PROPE RTY OF NAND AND NO R GATES
•
257
In FigurcS- lb(c), NAND gates G I and G2 arc used to invel1 the two input variables before they are applied 10 NAN D gate G). T he Iina1 OR output is derived as follows by applicaTion of J)eMorgan's theorem:
X = AB = A + B In Figure 5- I6(d ), NAND gate G~ is used as an invener connected 10 the circuit of pM (c) to produce the NOR operation A + B.
The NOR Gate as a Universal Logic Element Li ke the NAND gate. the NOR gate can be used to produce the Nor. AND. OR. and NAND functions. A Nor circuit. or invel1er. can be made from a NOR gate by connectin~ all of the inputs tDgCther 10 effeClivc\y create a ~ inglc input, a)' ~hown in Figure 5--17(a) wilh a 2-input example. Also, an OR gate can be produced from NOR gales, a~ illuslmled in Figure5- 17(b). AnAND gate call bcconslrucled by the usc of NOR gates, as shown in l-igure5- 17(c). In this case the NOR gates G I and G l arc used as invenen;, and the final output is derived by the usc o f [)CMo'Ean's theorem as follows:
NOR g.ltcs C.ln be used to produce any logic function .
X = J\-IB = AB Figure 5-I7(d) shows how NOR gates ure used to fon n a NAND fU I1I.:tion . FIGURE 5 - 17 Un r..er~1 appliC.lOOn of NOR gates. Open filel F05- 17(a), (b), (r:), and (d) to verify each of t he equivalendes.
(a) OOle NOR gm" """d a~ :W I i ,....,n"r
A~ '8
"
(b) Two NOR
~ S mc~
used as an OR
A."
g~l c
'\=D"
8
AR
Cc) Thn:e NOR £Il1C>. used as an AND gate
,\ A ~
AB
_
H ~ AB
R
(dl Four NOR
I
SECTION 5 3 REVIEW
~;uc,;
U>;l..-d
a.~
a NAND gale
1. Usc NAND gates to implement each expression;
(a) X ~
Ii + B
(b) X ~
AB
Z. Usc NORg.ltes to implement C
(a) X ~
Ii + B
(b) X ~
AB
258
_
5-4
COMBINATIONAL l OGIC ANAlY51S
COMBINATIONAL lOGIC USING NAND AND NOR GATES In this section, yo u will see how NAND and NOR gates can be used to implement a logic funct ion. Rccall from Chapter 3 thatlhe NAND gate also exhibits an equivalent operalion called the negative-OR and that the NOR gate exhi bits all cquivaienl operation callcd the ncgative-AND. You will see how the usc o f the approp riate symbols 10 represenllhe equi valent operations makes "reading" a logic d iagram easier. Afler complet ing this section, you should be able 10 _ Usc NAND gates to implement a logic function _ Use NOR ga te~ to implement a logic function - Use the appropriatc dual symbol in a logic diagram
NAND Logic As you ha\'e lcarned, a NAND gate can function as e ithcr a NAND or a negmivc-OR because, by OcMorgan's theorem,
AB NAND---,T
A
+B T
negative-OR
Consider the NAND logic in Figure 5- 18. The output expression is developed in the fo llowing steps: X ~ ~ (A"' B~ )(C ""D"') ~
(A + B)( C + D)
~ (A
+ 8) + (C + D) AB + CD
= = AB
+ CD
FIGURE 5 - 18
NAND logic for X = AB
A
+ CD.
- -r-..
H -~_/
X = A8+ C/)
As you can sec in Figure 5- 18. the output expression, A8 + CD. is in the form of two AND lenns ORcd together. 1llis shows thm gales G2 and G) act as ANI) gates and Ihal gatc G I ac ts as an OR gate. as illuslrated in Figure 5- 19(a). This circui t is redrawn in p.'lrt (b) with NAND symbols for gates G2 and GJ and a negative-OR symbol for gale G I • Notice in Figure 5- 19(b) the bubble-la-bubble connections between the ou tpu t~ of gates G2 and G.\ and the inputs of gate G I . Sillce (J b/lbble represell1.\· {In im'e'sioll, two cOlllleete(1 bub/'ll's represent (I dOl/fJie illlle1:5;olllllld therefore calleel ellch olher. This inversion cancellat ion can be seen in the previous development of the output expression A8 + CD and is indicated by the absence of barred tcnns in the outpul expression. Thus. the eirt:uit in Figure 5- 19(b) is e./feclil'e(l· an AND-OR circuit. a.~ .~ hown in Figure 5- 19(e). NAND Logic DiagmlYU Uling Dual SymbolJ A ll logic d iagrams using NAND gates should be d rawn with each gate represented by eilher a NAND symbol or the equivalent negative-OR symbol 10 reneet the operation of tnc gate withi n the logic circuit. The NAND symbol and the ncgatil'c-OR sy mbol are called (hlld Sl'lI/bols. When drawin" a NAND logic diag ram, always USe thc gate sym bols in such a ~ay thai every connccti~n
COMBINATIONAL LOGIC US I NG NAND AND NOR GATES
•
259
FIGURE 5 - 19 D~lopment of the AND-OR equivalent of the circuit in Figure 5- 18.
~::j~G~')>--- A8 + 0)
( - --1--::" 1> - --.---,
G ,acl~!II;OR .,J
G) aclJ; as AND (u) Original NAND logic diagram showing effectivc grJlC opcr,uioo n,:lntive 10 Ihe O.UpUI e~pn;.sslOtl
Bubble; c3l1CC 1
A- -' - "
n- -,---,
H - - - ._
AH+ 0) ( -
../
All + Cf)
c - --I- . ,
--,"-,
/J - - ,---,
/J - --._../ RIlbblc~ c~,"ccl
( b) Equivalcm NAN DlNcg~l"e-OR 100ic diagram
(e) AND-O R l",!u j'':3 lcn l
between a gate output and a gale input is either bubble-to-bubble or nonbubble-IOnonbubblc_A bubble output should not be connected to a nonbubble input or vice versa in a logic diagram. Figure 5- 20 shows all arrangement of gates to ill ustrate the procedure of using the appl"OprialC dual symbols for a NAN D circuit with several gale levels. Although using all NAND symbols as in Figure 5- 20(a) is correct. the diagram in par1 (b) is much easier 10 " read" and is the preferred method. As shown in Figure 5- 20(b). the output gate is rcprcscnted with a negative-OR symbol. Thcn thc NAND symbol i., used fo r the level of gates right before the output gatc and thc symbols for successive levels of gatcs arc alternated as you move away from the output.
FIGURE 5 - 2()
lIIultration of the ule of the appropriate duaJ.oymbob in a NAND
n -,-~ v~psml_-F
= rABcm+f1
/.
= ,\ 80) + 1:"1. '"' !AD+OO + /T
- 1,\8 +01J + Ef (ll ) s.:,-crJI 800lcwl steps nre reqlljroo to arrh-c 11\ filia l 001",,1 cAprcssioll. AN I) Bubtlle CllllceiS bar
AN D
Bllbbleadds bar to C
,AH + elf) + Ef
E - -<-'
OR
f · - - L__
canceb bar OR
AND (b) OuIPUl exprcssiOll C".m be obwincd directly from lhe. fUnclion of each gate sy mbol in Ihe di~grwn.
logic diagram.
260
•
COMBINATIONAL lOGIC ANA LYSIS
The !': hapc of the gme indie'lles the way its inpu\:o; will appear in the output expression and Ihus shows how Ihe gate funeli ons wilhin Ihe logic circuil. For a NAND symbol , the inPUiS appear ANDcd in Ihe oUlput expression ; and for a negalive-OR symbol, the inputs appcar ORed in Ihe oUlputexpression. as Figure 5- 20(b) iIluSlrates. The dUJ'l I-symbol diagram in p..'u l (b) makes it easier to delennine the outp ut expression di lt:Clly from the logic diagram because each ~ate !':ymbol indicates the relationship of il!': input variable!': as they appear in the outpul expression.
i
EXAMPLE 5 7
Redraw the logic d iagram and develop the OUlput expression for the cin:uit in Figure 5- 2 1 using Ihe appropriate dual symbols. FIGURE 5 - 21 A H
C X /J
£ F
Solution
Redraw the logic diagram in Figure 5- 21 with the use of Ct]u ivalent negative-OR symbols as shown in Figure 5- 22. Writing Ihe ex pression for X directly from the indicated logic operalion of each gate gives X = (.4 + 8)C + (D + E)F
H
-c<-.-_
r - ------' /J -
"''''
>-""-'or-.,
" -<'--F -------'
.. FIGURE 5-22
Related Problem
Derive the output expression from Figure 5- 2 1 and show it is eguivalcnl to the expression in Ihe solulion.
Illlplcmenl each expression with NI\ND logic using appropriate dual symbols: (a)
Solution
ABC
+ DE
Sec Figure 5- 23.
(b) ABC
+
D
+E
COMBINATIONAL LOGIC USING NAND AND NOR GATES
B,,,,",..
~~ \BC ~I,""
Bubble cancels bar
' _-r~
II
C --L_~
ABC + J)f:
/J -~-'
c --L~
•
IJ I B ( " V ' t " F I.
HubbIes add bars '0 /) and E
B ubble cancels bar
101
(a)
FIGURE 5 - 21
Related Problem
Convelt the NAND circuits in fl gufC 5- 23(a) and (b) to cquivalent AND-OR logic.
NOR logic A NOR gate can fu nction as either a NOH or a theorem. A
+
B
as
~how n
by DeMorgan's
AB
t
j
NOR
ncgativ~AND,
negat ive-AN D
Consider the NOR logic in Figure 5- 24. The output expression is developed as follows:
X - A
+8 +C+
D - (A
+ 8 HC +
D) - (A
-,B -----~ -Lj
+
8)(C
+
0)
FIGURE 5-2"
NOR logic for X = (A
+ B)(C -I
DJ.
c - -r-, G,
/J - - l--'/
As you can see in Figure 5-24. the output expression (A + IJ)(C + D) consists of IwO OR terms ANDcd together. This shows that galc." G 2 and G} act as OR gales and gate G , llcl<; aSlln AN D gate . as illustrated in Figure 5- 25(a). Th is circuit is rcd mwn in p3rt (b) with a negative-AND symbol for gate C,.
Bubbles cancel
II - L :-
G, G, ""Is
,,'
(A + B}(C+V) ,~,
ANI) Bubble!< cancel
G:! a<.1S;OS OR
'bI
NOR Logic Diagram Uling Dual Symhob As with NAND logic. the purpose for usi ng the utlll1 symbols is to make the logic d iagram easier to rend and analyze, as illustrated in the NO R logic circuit in FigufC 5- 26. When the c ircuit in p... rt (a) is redrawn wi th (lual symbols in pan (b). not ice that all output-Io-input l:onncct ion.~ between gates are bubbJeto-bubble or nonbubble-to-nonbubblc. Again. you can see that the s h a~ of each gate symbol indil:Cites the type of term (AND or OR) that it produl:cS in the output expression, thus making the output expression cll:')ier to determine and the logic dillgram easier to allaiY7.e.
FIGURE 5 - Z5
261
262
•
COM81NATIONAllOGIC A NALYS IS
FIGURE 5 - 26
Illustr
B -
L/
ilppropriilte dUill l)TT1bob in iI NOR A + 8 + C+iJ~E + F
logic di
""1A+ B+C+iJ)(E+f) "',,A I B + C I OKE + f.
"""" (fA= + JJ)C + iJ )( t:. ... /-) (( II
+ BIC + 0 1(1:.-
~leps.
(a) FI nal uotput cxpress iun is obtained a ti('f !;C\el1!1 Bo<.)II'"" o
OR
Bubblc adds oor to C
£+f
Bubble ca ncel s
AND
""
OR
(b) Output crpression can be obIai!>Cd directly from the fUllc tiu lI of each gate symbol in the diagmm.
Using appropriate dual symbols, red raw the logic diagram and devcJop the output expression for the circ uit in fi gure 5- 27 . fiGURE 5 - 27 A
B -
L-':"-
, - ---' v
-~~
x
'b--r-~
E
F - -- -' Solution
R(.'<.Iraw the logic diagram with the cquivalent negntive-AND symbols as shown in Figure 5- 28. Writing Ihe expression for X d irectly from the indicatcd operation of each gatc,
x ~
P)
; =~~)-~IG;' c - ----' X ""
(Aii .,. elIDE + 1-1 = IAn + CWI:; .,. FI
~ =1G;)...!l'i...)2 F -----' Related Problem
Prove thai the outpUl of the NOR circuit in Figure 5- 27 is the same as fo r the circuit in Figun: 5- 28.
I /-)
lOGIC CIRCU IT OPERATION WITH PULSE WAVEFORM INPUTS
i
SECTION 5-4
REVIEW
1. Implement the expression X = (A
+
B
+q
2. Implement the cxpreuion X = ABC + (D
5-5
_
DE by uling NAND logic.
+
E) with NOR logic_
LOGIC CIRCUIT OPERATION WITH PULSE WAVEFORM INPUTS
Scveral examples of gcncral combinat ional logic circuits with pulsc wavcfonn inputs arc examincd in this section. Keep in mind that thc operation of each gate is thc same for pulsc wa\"cfonn inputs as for constant-level inputs. 1l1e Output of a logic circuit at any given time depends on the inputs at that particu lar time, so the relationship of the limc-varying inputs is of primalY imponance. After completing this section. you sho uld be able to _ Analyze combinational logic circuits with pulse wavcfornl inputs _ Develop a liming diagmm for any g iven combinational logic circui t with specified inputs
The operation of any gale is Ihe same rc2ardless of whcther ils inputs arc pulsed or constant levels. T he nature of Ihe inplils (pulsed or consumt levels) docs not alter the truth lable of a circuit . The examples in this section illustrate thc analysis o f l:Ombinationallogic c irc uits wilh pu lse waveform inputs. The following is a rcview of the ope ration of individual gates for use in analyzi ng combinational circuits with pulse waveform inputs:
1. 1l1e output of an AN D gate is HIGH o nly whcn all inputs arc HIG H al thc same time. 2. The output of an OR gate is HIGH only when at least one of its inputs is I-IIGI-!. 3. TIle output of a NAND gale is LOW only when all inputs un: HIGH at tile samc timc. 4. T he output of a NOR gate is LOW only when 'It lelsl one of its inputs is H IGH.
I
EXAMPLE 5 - 10
Determine tilt: final o utput waveform X for the circuil in Figure 5- 29. with input wavcforms A B. and C as shown .
A - --
- [______
;n--rr
x FIGURE 5-29
I ,
I II
"
I II
I II I II
I II III
x
263
264
•
COMBINATIONAL lOGIC ANALYSIS
Solution
Related Problem
T he output expression, AB + A C. indicates that the oUlpUI X is LOW when both A and B are HIGH or when both A and C are HIGH or when illl inputs are HIGH . The output waveform X is shown in the ti ming diagram of Figure 5- 29. The intermediate waveform Y at the output of the OR gate is also shov.'n. Dctennine the output waveform if input A is a constant HIGH level.
Draw the timi ng dingmm for the c in.;uit in Figure 5- 30 showing the outJX.lts of G" G!, and G3 with the input wavefonns, A, and B, as indicated.
FIGURE 5 - 30
Solution
When both inputs are HIGH or when both inputs arc LOW, the OUipul Xis HIG H as shown in Figure 5- 3 1. Noti!.:e that this is an exclusive-NOR circuit. The intennediate outputs of gates Gj and G.1llre also shown in Figure 5- 31 .
A
FIGURE 5-31
Related Problem
i
Determi ne the output X in Figure 5-30 if input B is inverted.
EXAMPLE 5-12
Determine the output waveform X for the logic c ircuit in Figure 5- 32(a) by first lindi nfl the intermediate waveform at each of points Y" Y2• YJ , and Y~. "be inpul waveforms arc shown in Figure 5- 32(b).
LOG IC C IRCU IT O P ERATI ON WITH PU LSE WAV EFORM INPU TS
fiGURE 5 - 12
C, )
265
~5~, t4
V
, , 8U ,, c ,' ,, 0:, ,,, ,, y , ,, ,,
,, j , .JL
A
(b)
•
I, I,
i:---LJ ,,
,,,
,,
,, ,
U
,
,
U
r, r, r. (c)
Solution Related Problem
I
X
U
H , , LJ
All thc intermediafe waveforms and the final output waveform arc shown in the timing diagram of Figure 5- 32(e). Dctemline the waveforms Yl> Y2• Y3• Y4 and X if input wavefonn J\ is invcl1c(1.
EXAMPLE 5-13
Detcrmine thc output wavcfonn X for the circu it in Example 5- 12, Figure 5- 32(a), directly from the output expression. Solution
The output expression for the cireuit is developed in Figure 5- 33. TIle SOP form ind icates thallhe output is HIGH when A is LOW
FI GURE 5- 13
266
•
COMBINATIONAL LOGIC ANALYS IS
·Ine rcsull is shown in Figure 5- 34 and is Ihe same as the one obtained by the imero1t:diale-wavcfonn meth
.
BC
CD ~
A
-
'---+_ : _~'--l---+---11
U - L-...L---,-S-'---"---JUf---'---jU: D ,-
I
I
I
X "'.\C+RC + CD _ FIGURE 5- 34
Related Problem
i
SECTION 5 - 5 REVIEW
Repeat this example if all the input waveforms arc invelted
1. One pulse with lw = 50 III il applied to one of the inputs of a n exdulive-OR circuiL A second positive pulse.....;th t IV = TO JJI is applied to the other input beginning 151lS after the leading edge of the first pulse. Show the output in relation to the inputs. 2. The pulse waveforms A and B in Figure 5-29 are applied to the exclusive-NOR drcuit in Figure 5-30. Develop a complete timing diagram.
5-6
COMBINATIONAL lOGIC WITH VHDl (opt;onal) T he purpose of describing logic using V HDL is so Ihal it can be programmed inlo a PLD. The data flow approach to writing a VHDL program was described in Chapler4. In this optional section. both the data flow approach u~ing Boolean expressions and the structural approach arc uS(.'(\ to develop VHDL rode for describing logic circuits. The VHDL component is int rud ucL'd and used to illustmte structural dc~criptions. Some aspects of software development tools are discu:.sed. After completing this sL'Ction. you should Ix: able to • Describe a VHDL co mponent and discuss how it is used in a program . Apply the structul".tl approach and the data flow approach 10 writing V HDL code . Describe two basic software development tools
Structural Approach to VHDL Programming Th~ stmctumi upprooch 10 writing a VHDL description of a logic function can be compared 10 mstallmg Ie devices o n a c ircuit board and intcrconnecting them with wires. With the
CO MBINATI O NAL l OG IC WITH VHDl
structllml upproach, you describe logic runctions and specify how they arC', connected together. '111e VHDL cOlnl>onelll is a way to predefine a logic fUllct ion for repeated usc in a progmm or ill othe_r programs. The component can be used to describe anything from a simple logic gatc to a complex logic function. The-VHDL signlil can be thought of as a way to srx:eify a "wirc" connection between components. Figure 5- 35 pro\lides a simplillcti comparison of thc structural approach to a hardware implemcntation on a c ircuit board. Inpl1l~
dctinccl ill porI ~mICI1lCIII
rn lcrco.mn~"I;l iOlI'
Si!!n,tI~
IC Delice A
VHDL C()mpOllcnl ICDevlu (
VHDL
compollem
Ie DeIKt' B
VH DL cOIllfXlJ\£'nl
OIlIP" l uCllr'1Cd
in por1 M3'cmem (~)
H;uu warc
implcmcnl~l iOIl
Il ilh tixcd.-fUr'lClion logic
(b) VHDL ~I "'cluml implcmc nllll ion
FIGURE 5- 35
Simplified comparison of the VHDl structural approach to a ha rdware implementation. The VHDl signals corr~ pond to the in terconnections on t he circuit board, .md the VHDl componenb correspond to the Ie devices.
VHDL Components A VHI)L component describes predefi ned logic that can be Slof(xl as a package declaration in a VHDL library and called as many times as necessary in a program. You can use comjXllle_nts to avoid rcpeating the same code o\ler and over within a program. For example, you can create a VHDL collll)Ollent for an AN D gate and then usc it as many times as you wish without ha\ling to wri te a program for an AND gate,cve_ry time you necd one. YHDL components arc stored and are available for use when you write a program. This is simil ar to ha\ling, for example-, a stonlge bin of ICs a\laila ble when you arc constructing a circu it. E\lery time you need to usc o ne in your circuit, you reach into the storagc bin and place it on the circuit board. Thc VHDL program for any logic function can become a component and used whenever necessary in a larger progmm with the use of a component declamtioll of the following general form. Component is a YHDL keyword. component name_oCcompone.nt is port (port definitions); end componcnt nmne_oLcompol1ent: For simpl icity, let's assume that there arc predefined YHDL data flow descriptions of a 2-input AND gate with thc entity name AND--2ate and a 2- input OR gate with the emity name OR...salc, as shown in Figlff'C 5-36. Next, assullle th at you are writing a program for a logic c ircuit that has se\ler.!! AND gates. Instead of rewriting the prog ram in Figure 5- 36 O\ler and over, you can usc
•
267
268
•
COMBINATIONAL lOGIC ANALYSIS
FIGURE 5 - 3 6
('ntil) AND_gate I port IA. 0: in bit: X: 01.11 bin: end entit~ ANO_!;ute;
Predefined progralTU fur" 2-input AND g" te "nd " 2-input OR g"te to be used "I componenu in the d"t" flow "pprwch.
nni1 ilorl ur~
2·inllU l AND gale
ANDfunction ,r AND_ gate is
X<=A a nd B; end nrchilC\'lllrc ANDfuoctiofl:
OR_gale D port (A , B: in bil: X : 001 bil):
., nlil~
t'lld enlil~ OR_~me:
nrdlileclure ORfuocl;on (,f OR_SOlie is bo.-gin X<=A ur O; end archited un' ORfu oction:
2·inpul OR ga le
a component declaration \{) specify the AND gatc. The porI state men! in the component declarati on must cOlTCspond to Ihe port statement in the e ntity declar.ltion of the AND gate. compol"K'nl AND..,galc is
IJorl (A, B: in bit ; X: out bit): ('nd cOIllPonent AND..,gale;
Using Components in a Program To use a component in a program. you must write a componelll instantiation statement for each instance in which thc component is usetl. You can Ihillk of a component instantiation as a request or call for the componem 10 be used in the main prof!.mm. Forexamplc. the simple SOP logic circuit in Figure 5- 37 has two AND gales and one OR galc. Therefore. Ihe VHDL program for this circuit will have two com· ponents and three component instantiations or calls. FIGURE 5-31
INI -
--<-
'
IN2 ---t_~
OUI')
(N3-- - < - ' IN' -
-1":::':'-
Signal; In VI-lDL, signals arc analogous to wires that intercon nect components on a cir· cu it board. The signals in Figure 5- 37 arc named OUT I and OUT2. Signals arc the il/lemal connections in the logic circuit and are lreared diffcrently than thc inputs and outputs. Whereas the inputs and outputs are declarl.'d in the entity declaration using the pon state· ment , the signals are declared within the architecture using the signal Slatement. Signal is a VHDL keyword. The Program as fo llows:
The progr.lm for the logic in Figure 5-37 begins with an emiry declanltion
--Progl1llll for the logic circuit in Figure 5-37
('nlity AND_OR_Logic is
port (fN r, IN2. IN.1, IN4: in bil; OUT3: OUI bit): end enlity AND_O R_ Logic;
COMBINATI ONA L l OG IC WITH VHDl
The architeclUrc declaration contains the component dcdamtions for the AND gatc and the OR gale, the signal dcJinilions, and the component instantiations. archih.'Clu re LogicOpcffilion or AND_OlCLogic is component AND...,gale is
port (A. B: in bit): X: oul bil);
Compooenl declaration lor
~ the AND gate
end component AND...gale; component OR~atc is IHlrt lA. B: in bit: X: oul bit);
Component declaration k>r
~ the oR gale
end component O~atc; siglllil OUT I , OUT2: bit;
.';.-- - - 5 ig08I decleralloo
l>Login G I : AND...,gate port nlap (A = > IN !. B = > IN2. X = > OUT]);
~
_ C~t
G2: A N D...,gmc POI'I nlllp (A = > IN3, B = > lN4. X = > OUTI):
instantlQtlOIlS
G3: OR...galqX)rt Ill OUT! , B = > OU12. X = >OU1'3); end Ilrchitl'ClUre LogicOpcmtion; Let's look al the component instanliations. First. notice that the compollCnt instanlialions appear betwecn the keyword lJc1,>in and the end stateme nt. For cach instantiation an identifier is defined. such as G I, G2, and G3 in this case. Then the companenl namC is specified. The pon map cs...em.ially makes all the connections for the logic function using the opcrutor = >. Fur example, the first instantiation, Component lrutantiations
GI : AND...,gate port nUlp (A = > IN I , B = > IN2, X = > OlIT l ); can be explained as fo llows: Illput A 0/AND gllfe G I is cOIIIJectell to iI/pIli IN I. illput B o/tlle gllte is cOllllecu:d 10 iIlPIII IN2, lIIlIl ti,e Olllpill X o/the gale is C:Ol/l1ectelllO tile signal OUT/.
The three instantiation statemcnts together completely descri be the logic circuit in Figure 5- 37, as illustmted in Figure 5- 38. FIGURE 5 - 38 Ulustlation of the instilntiiltion
ItiltemenfJ ilnd port ffiilpping ilpptied to the AND-OR logic. Signilll are Ihown in red.
Although the dala now approoc h using Boolean e-xprcssions would have lx..'Cn easier and probably the best way 10 describe Ihis particular circuit, we have used this simple circu it 10 e",plain the concept of the structuml approach. Example 5- 14 compares the structuml and data now llpprooches to writing a VHDL progmm for an SUP logic circuit.
•
269
270
•
I
COMBINATIONAL l OGIC ANALYSIS
EXAMPLE 5
14
Write a VHDL progmm for the SOP logic c ircuit in Figure 5- 39 using the siructumi approach. Assume thai VHDL comp()ncl1ls for a 3-i npul NAND gate and for a 2-inpul NAND are available. Noticc the NAND gale G4 is sh()wn as a negative-OR. FtGURE 5-39 IN I
tN2
---.-~
t N3-<'-~
INS IN4 IN6 IN7 I N8
Solution
P"= '--,
G2 G4 =3:~0o!'''''"-~[~
alIT4
---.-~
_l'~?"'-"..J
The components and component instanliati()ns arc highlighted. --Prognull for the. logic c ircuil in Figure 5- 39 entily SOP_ Logic is port (IN L IN2. iN3 . IN4. iNS. IN6. IN7. iN8 : in bil; Ol'T4: out bit); end entity SOP_ Logic: architecture LogicOper.ltiOll or SOP_L()g ic is -- componcnt dL'C lamtioll ror 3-input NAND gate component
NAND~ale3
is
port (A. S, C: in bit X: out bit); end component
NA N D~atc3 ;
- eomponenl dL'Clumtion for 2-input NAND gatc component NAND-£:atc2 is port (A. B: in bit; X: out bit); end component NAND-tate; signal OUT I. OUT2. OUT3: bit; begin G I: NAND~l;lI c3 port limp (A = > IN1. B = > IN2. C = > IN3 . X => OUTIl:
02: NAN D~!l Ic3 port map (A = > IN4. B = > INS. C = > IN6. X = > OUT2):
03: NAND-!;ateZ port map (A = > iN7. B = > INS. X = > OlIT3): 04: NAND...,gate3 port map (A -=> OlIri. 8 = > OlIT2. C => OUD. X => Ol!T4):
end architecture Lug icOpcmti()n;
rvr comparison purposes. let's write the progmm for the logic circ uit in Figure S- 39 using the data flow approach. entity SOP_ Logic is
port (I N I, IN2. IN), IN4, INS. IN6. IN7, INS : in bit; OUT4: out bit); end entity SOP_ Logic;
COMB IN ATIONAL LOGIC WITH VHD L
•
271
archih."Cture LogicOpcmtion of SOP_ Log ic is ht:gin OUT4 <= \lNl
~nd
IN2 and IN3) 01' (IN4 and IN5 and IN6) or (IN7 and IN8);
end IIrchitccture LogicOpe.r.ltion ; As you can see, the data flow approach rc."ults in a much simpler code for this particular logic function, However, in situations where a logic function cunsists of Illany blocks of complex logic, the structural approach might have an advantage over the data flow approach. Related Problem
I[ another NAND gate is added to the circuit in Figure 5-39 with inputs IN9 and IN IO, write a component illstantiation to add 10 the program. Specify any other necessary changes in the program as a result.
Applying Software Development Toors As you have le.arned, a soft ware development package must be. used to implement an lIDL design in a target dcvicc. Once the logic has been described usinE an HDL and entered via a software 1.001 called a code or text editor, it can be tested using a simulation to verify that it performs properly before actually programming the target device. Using software dcvelopmen ltools al lows for the design, development, and testing of combinational logic before it is commined to hardwarc. Soft warc developmcnt t{Xlls arc explored furt her in Chapter II . Typical soft ware de"elopment tools allow you to input VHDL code 011 a tcxt-based cditor speci fi c to the p
I
File
j
,I ,
I
Edil View Pr010CI Assignments Processing Tools
entity Combinational is. . port ( A , B, C, 0 : In bIt: X, Y: out bit ); end entity Combinational; architecture Example of Combinational is begin X <= (A and B) or not C; Y <= C or not 0; end architecture Example ;
FIGURE S - 4()
A VHDL progr
th~t
il
After the program has becn written into the tCXt editor, i( is passed 10 the compiler. Thc compiler take.s thc high-level VHDL code and eonvelts il into a file that can be downloaded to the target device. Once the progmm has been compiled, you can create a si mulatiOIl for testing. Simulated input values are illscned into the logic design and allow for verification of the outpUI(S).
272
_
COMBINATIONAL lOGIC ANALYSIS
You sp<.'C iry thc input waveforms on a software tool called a waverorm editor. as shown in F igure 5-4 1. The output wa"erorms arc generated by a simu lation o f Ihe VHDL codc [hm you entered on thc text ed itor in Figure 5--40. The wavcrorm simulation providcs thc res ulting outputs X and Y for the inputs 1\ . B. C. and /J in all sixtcen combinations rrom 00002 tO I I I 12 ,
Name:
50.0 ns
100.0 ns
150.0 ns
200.0 ns
250.0 ns
""ElEI 300.0 ns
C
_
6
....,... A
"""-' Y -L. X
• FIGUR E 5 - 41
A typic~1 w.weform editor tool o;howing the o;imulatcd w.wefonrn for the logic circuit described by the
VHDl code in Figure 5-40.
Recall from C hapter 3 thattherc arc scver.....1 performance chal"olcteristics of logic circuits to be considcn:d in thc creation of any digital system. Propagation delay. for example. determincs the speed or frequency ut which a logic circuit can opcr..tte. A timing si mulation can be used to mimic the propagation delay through Ihe logic design in thc target device.
I
SECTION 5 - 6 REVIEW
1. Whi!lt i$ i!I Vl-IOl component? 2. St
5-7
TROUBLESHOOTING The preceding sections havc given you some insight into the operation o f combi national logic c i n:uil~ and the relutionships of inputs and outputs. This type of understanding il\ esscntial when you tro ubleshoot digital c ircuits because you must know what logic leve.ls or wavefonns to look for throughout the circuit for u given set of input conditions. In this scetion, an oscilloscope is used to [roublcshoot a fixed-function logic circuit when a gatc output is connected to several gate inputs. Also, an examplc of signal tracing and waveform analysis methods is presented lIsing a scope or logic analyzer for locati ng a fault in a cOl1lbinationallogic circuil. Afier completing this section. you should be able to - Delinc a circuit node - Use un oscilloscor~? to find a fau lty circuit node _ Use an ~ i"oscopc to find all open gate output . Use an oscilloscope to tind a shorted gate mput or Olltput - Usc an oscilloscorx: or a logic analyzcr for signal tmcing in a combinalional logic circuit
TROUBLESHOOTING
•
273
In a combinational logic circuit, the output of one gal('. may be connected to two or mOl'C gate inputs liS shown in Figure 5-42. The interconnecting paths share a common electrical poi nt known as a node.
FIGURE 5 - 42
IlIvstJiltion of iI node in iI logic
circuit.
G,
Gate G 1 in Figure 5-42 is d rivi ng the node, and the other gales represent loads connecled to Ihe node. A driving gate can drive a number of load gale inputs up to ils specified fanout. Scveml types of fai lures arc possible in this situation. Some OfUlCSC fail ure modes are difficult 10 isolate 10 a single bad gate because all the gales connected 10 the node are affectcd. Common types of faill1res arc the. foll owing:
1. Open ollipul in tlm 'illg gal e. ll1is failure wiil cause a loss o f signal to all load gales. (J loatl gate. This failure will not afTecllhe ope.rdtion of any of the other gales connected to the node. but it will result in loss of signal output from the fault y gate.
2. Open illlJUI in
3.
Sfl(m(~lI UII/P ut
in (/ri ving gole. This failure c
LOW state (shol't to ground) or in the HIGH state (shol1l0 Vc.."C)' 4. Shurlet/ illlJ/II ill II load gOle. This fai lure can also cause· the node to be stuc k ill the LOW state (shOlt to ground) or in the HIGH Siale (shOtt to Ved.
Troubleshooting Common Faults Open Output in Dn·vingGate In lhis situation there is no pu lscactivityon the node. With circuit power on. an open node will nonnally result in a " n oating" lcvcl. which is o ften indicated by no ise. a<; illustrated in r:igure 5-43.
ANDS
ON
When tro ubleshooting logic circuib, begin with a visua l check, looking (or obvious problems. In addition to compone nb, visual inspection should include connectors. Edge connectors are frequently used to bring power, ground, and signals to a circuit board. The mating surfaces of the connector need to be clean and have a good mechanical fit. A dirty connector can cause inte rmitte nt or complete bifure of the circuit. Edge connectOR Can be cleaned with a common pencil er.3ser and wiped clean with a O-tip soaked in alcohol. Aho, all connectOrJ should be checked for loosefitting pim.
274
•
COMBINATIONAL LOGIC ANA LYSIS
Then. an: pul.<.e.~ nn lhe g"le inptJl with Ih~ OI he r inplll HIG H.
S~"'I'" ir\di<:" tes nQ plll~ acti vity
at ~ ny point 00 the: node:. Scope: mOly indical., "no:tling" Ie".,..
Oulput Of lh ls g:tte in Ie I is open 14
13 12
I". 9 8
74AHCOO pin diagnliTl
If the:re: is no PI-,Ise activity at lhe: g;lte outpu t r in 00 le i . lhen- is un inte:n~ll O("'n. If Iht:re is pulse activily tl irecll)" on the OlllpUI pin 001 not on lhoe node imcroon""" l ion~. lhe connect ion belWttn Iht: pin IUld Iht: board is opt:n.
fronl ililla sheel
FIGURE 5 - 43
Open output in driving gilte. For simplicity,
i1SIUme iI
HIGH fI on one gilte input
Pi" 4 inpul of til is gale in lC2 i~ open I
,-"c.;:o,
,m--,,, 'Q}-d. , 2
"
I! ,~" 11 13 12
"
~=-'II \0
, 9
74A HCOO pin tli~g"'JlTl from d.am
~hect
IIICII Otecl; lhe oUlpll1 pin of each g,lfe connc:cled 10 the notk wilh oc her £ille i nput~ HIGH. No pul ~ "clivil)" on an OUlput indicales lIn open ~iI1~ input or open gale OlltpUt.
FIGURE 5 44
Open input in iI load gate.
Open Input in a Load Gate If the chc..'Ck for an opCn driver OUlput is negative. then a check for an open inpUi in a load gale should be pcrfooned. Apply the logic pulsertip 10 lhe node with all nonpulsed inpul.<; HIGH. Then chexk [he output of each gale for pulse aclivity with the logic probe. a<; illustrntCf./ in I-igure 5-44. If one of thc inpuL~ lhar is IlOnnally conrx:crcd to the node open, no pulses will be dclL'Clcd on Ihut gate's output.
TRO UBLESH OOTIN G
•
Z75
Output or Input SilOrled to Ground When the output is shorted to ground in the driving gute or the input to a load gute is shorted 10 gmund, il wi]1causc the node to be-stuck LOW, us prcv iOll~ ly mentioned A quick check with a scope probe will indicate this, us shown in Figure 5-45. A short to ground in the driving gate's output I)r in any lood gute input will cause this symptom. and fLUther checks rnustlhercforc be made to isolate the short to a pmlicular gate. FtGURE 5 - 45
Shorted oo tjXJt in the driving gi! te or morted input in i! load gi! te.
1llere is a LOW lewl at all points connected to the nfde.
14 13 12
" 10
9
"'L_
j'-' 8
Signal Tracing and Waveform Analysis Although the methods of isolating an opcn or a short at a node point arc velY useful from time to time, a more generaltTOubleshooring teChnique called sign!lJ trueing is of vulue in j ust about every tro ubleshooting situation. Waveform measurement is accomplished with an ~illoscopc or a logic analyzer. Basically, the signal tmc ing method requi res that you observe the wavefol1ns und their time relationshi ps al ull accessible po ints in the logic circ uit. You can begin at the inputs and, from an analysis of the waveform riming diagram fOI" each point, determi ne where nn incorrect wavcfoml fi rst occurs. Wi th this procedure you can us ually isolate Ihe fault to a specific gate. A procedure beginning al the oul put and working hack toward Ihe inpu t~ can also be used. The genenll proCl..>(!urc for signalt mcing starting D.t the inputs is outlined as fo llows: Wilhin a systcm. define the sectioll of logic that
i~
suspected of bc.ing fau lty.
Stan at the inputs to the section uf logic under e-xaminatioll. We ass ume, for this discussion, that the input wavefomls coming fro m other sections of the system have been found to be COITI.:·ct. For each gate, beginning al the input and working toward the output of the logic c ir· cuit, observc the output waveform of the gate and compare it with the input waveform s by using the oscilloscope or the log ic analyzer. Determine if the output waveform is com~ct, using your knowledge of the logical opC-n1tion of the gate. If the output is incorrect, the gate under tcsl may be faulty. Pull the IC containing the gate that is suspected of being faulty, and test it out-of-circuil. If the gate is found to be faulty. re place the IC If it works correctly, the fault is in the external circuitry or in another Ie to which the tested one is connected. If the output is correct, go to thc next gate. Continue checking cach gate until an incorrect wavcfon l1 is observed.
276
•
COMBINATIO NAL lOGI C A N A LYSI S
Fig ure 5-46 is an example that illustrates the general pmcetlure for a specific logic cirin the following ste ps:
CUi l
Step I. Observe the OUtput of gale G, (Iesl point 5) re lalive 10 the inpu ts. Ifi l is correcl. crn..'Ck Ihc inve rter next. If the o utput is not COlTcct. the gate or its conncclions arc bad; o r, if the output is LOW, the input to glltc G1 111ay be sho rted. Step 2. Observe the output of the inverter (TP6) re lmi ve
10 the input. If it is cOITCCI. check gate G2 ncx t. If thc o utput is not correct, 'hc inverte r or its connections arc bad; or. if the o ul put is LOW. the input to gate G) may be shorted.
Step 3. Observe the o utput of gate G 2 (TP7) relative 10 the inputs. Jfit is cOITCCI, c heck gale G) next . Ifl he output is not comet, the gate or ils con nections arc bad: or. ifthe o ut put is LOW, the in put to gate G4 may be sho rted.
5,,,1' I
o If ~I, go 10 step 1.
o If incorrect, tCSt to and connections.
s.....,Pl' i, e ~l erlln ll y l ri ~cred from U:M PO'I11 TPO TI~
12 13
G,
II
I"IPS I
SICI,2 o I Fcorrect, go 10 slep 3. 0 If incorrecl, test le i and connc<.1 ion~.
I ITI' I ).
10
9
G, 6
In'6 l
"
5lep 3
o If Corred. go to step 4. 0 If incorrect, tesl 10!llld oonnect ion~.
,
§Y'
W 'l
~
G,
.......,,-'-'@-..."-~
5'''1'4
Srt:f,j
o If COCJ"eCt. go to srep 5.
o If OOITtcl. circu;t is OK.
o Ifinc<1ITIXl. leS! 1C2 and cOl1 occtioos.
o if ir"ICorre<:1. tet;t lC2 and conrJeCliOflS.
FtGURt 5-46
Examp le of signal tracing and wavefo rm a nalysis in a portion o f a p rinted circu it board . TP indicatel tel l point.
TROUBLESHOOTING
•
Step 4. Observc the output of gate G) (TPH) relative 10 the inputs. If it is correct, check gale G~ next. If the out put is not correct, the gate or its connections are bad; or, if the output is LOW, the input to gale G~ (TP7) may be shorted. Step 5. Observe the output of gatc G 4 (TP9) relativc to the inputs. If it is correct, [he circuit is okay. If the output is not correct. the gate or its connections Clrc ba.d.
I
EXAMPLE 5 - 15
Determine the fHu h in the logic c ircllit of Figure 5-47(a) by usin!] waveform analysis. You have observcd the waveforms shown in green in Figure 5--47(b). The red waveforms are correct and arc provided for comparison.
U,
,,, ,
,,, ,,, , ,,
U ,
U ,
U ,
,, :t,, , ,, ,,,
I, I, I,
,I,
I, I,
,, ,, , G 1 UUlpllt
,, [nvcner , ,
OUlpllt
":~~ :J n
.
,.)
G 0utpllt 2
,,
G ) OUlplll :
(;4 0 Ulpul
U
,, ,, ,,
I,, i ,i ,i , ,
,
U
(b)
fiGURE 5 - 41
Solution
1. Dcten nine what the correct waveform should be for each gate. The correct waveforms are shown in red, superimposed on the actual measured waveforms, in Figure 5-47(b). 2. Compare wavcforms gate by gate umil you find a meHsured waveform that docs not mHtch the CQlTect wa\'Cform . In this cxample. everything tested is correct until gale G3 is checked. The output of this gate is not correct as the differences in the wHvcforms indicate. An analysis of the wavefonlls indicates thai if the D input to gate G 3 is open and acting as a HIGH, you will get thc output waveform measured (shown in red). Notice that the output of G4 is also incorrect due to the incorrect input fm lll G). Replace the Ie containing G1 , and check the circuit's o peration again.
Related Problem
For the inputs in Figure 5-47(b), determine the output wavcfonn for the logic circuit (output of G4 ) ifthc inverter has
277
278
•
COMBINATIONAL lOGIC ANALYSIS
~ANDS
• N
As you know, testing and troubleshooting logic drcuib often require observing and comparing t'W'O digital waveforms simultaneously, such ;u an input and the output of a gate, on a two-channel osci ll~ope . For digital waveforms, the scope should a lwa~ be set to DC coupling on each channel input to avoid -shifting" the ground level. You should determ ine where the 0 V level is on the screen for both channel!. To compare the timing of the waveforms, the scope should be triggered from only one channel (don't use vertical mode or composite triggering). The channel selected for triggering should a lways be the one that has the low-est frequency waveform, if possible.
1. List four common internal failures in logic gates. 2. One input of a NOR gate is externally shorted to +Vcc. How does this condition affect the gate operation?
3. Determine the output ofgate 6 4 in Figure 5-47(a), with in pub as shov.n in part (bJ. for the follov.1ng faufb: (a) one input to 6 . shorted to ground (b) the inverter input shorted to ground
(c) an open output in 6 3
Troubleshooting problems that are keyed to [he CD-ROM arc available in the Multisim Troubleshooti ng Practice section of the end-of-chapter problems.
the fluid within a certain range and i"ue an illilrm if any of the level or temperature senson fail. BaHc System Operation
In this digita l system appJie<>tion, the digital control logic for contrOlling the fluid in a storage tank il developed. The purpo.c of the logic i , to maintain an appropriilte level of fluid by controlling the inlet and outlet villvcs. Allo. the logic mud control the temperilture of
The outpub of the ')'Item control logic control the fluid input.. fluid output. and fluid temperilture. TI,e control logic operates iln inlet Vtes when the fluid ii too hot, and the other indicates when the fluid il 100 cold. The control logic turn! on a hCilb·ng element jf
the tcmper"turc semon indiCdte the fluid il too cold. TIle control logic keep. tht! outJetv"lve open M long"'s the low-level sensor il imme.se<:/ and th" fluid IS at,) proper temperature. When the fluid level drops below the low-levellenIOf. the control logic dOles the outlet valve. Operational Requirements
The maximum;mel minimum fluid levels are determined by the positiom of the level semoo in the tank. The output of eadllemor is HIGH wf,en it il immersed in the fluid and is LOW wflen not immersed. When the high-level =>sa output is LOW, ti>c control logic produces,} HIGH and the inlet valve Opem. When the high-level sensor output is HIGH. tJ,e control logic produces a lOW and the in/etV
DIG ITAL SYSTEM APP LICATI O N
•
FIGURE 5 - 41
Fluid storage L'lnk with level and lempera tv re lenson and controll.
\\
I AlanTI
A
COrll rullugic and intcrfa.:e
VOUTl£r
TA BLE 5 - 6
Tank cootrollogic inpub a nd outpu b .
INPUTS TO CONTROL lOGIC Vuriuble
Description
ACIh-e lew l
Commcnls
4,
High-Icvel sensor
HIGH (I)
Sensor is inunerscd
{~
LOIV-levei scnsor
HIGH (I)
Sensor is im mersed
Too
Hi gh-temp scnSOl·
HIGH (I)
Tempcrntu rc 100 hot
7(:
LOIV-temp scnsor
HIG I-I (I)
Tem perature too eoh!
OUTPun FROM CONTROL lOGIC Vll riubl c
is opened. One sensor produces a HIGH whe n the temperature iI too hot, and the ot he r tcmpct"atv re senIor produce! a HIGH when the temperature il too cold . The control logic producelO a HIGH to turn on 3 tJ~l.ing e lement whe n a too-cold condition i! indicated; o tnerwilC, the heating element is turned off. When a too-hot condition is ind icated, a n alarm is activated. When t he low-level sensor produce! a HIGH output ( indi~ting that it i! immer~) ;,nd when the (lutput of ooth
l)e;criptiull
Act il"C Ic\cl
Co mmcnts
V1N1..ET
Inlet valve
HIG II (I)
Val ve open
VOUl1.I:r
Outlet val \Ie
HIG H (I)
Valve open
H
Heating e lement
HIG H (I)
Heat on
A
Alarm
HIG H (I)
Sensor failu re or too-hot (."{)Ild ilion
tcmpt!",ture se mon a re lOW ( indi~ting a correct temperatvre), the control logic openl the ou tlet valve. If the low-level !emar o utput goc. l OW o r if e ither temperature !emor output! go lOW, the control logic doses the outlet va lve. If the control detects a failure in .)ny (If the !oenlDn or a too-hot coodition, an alarm is activated. A level-iensor failure i! indicated when the high-level
time. Figure 5-48 sho\.I.1 the til nk con tro l Iystem. TI,e S)'Item inpu b ;,nd outputs are summarized in Table 5-6, 3nd the trut h table i! shown in Table 5- 7.
!.lrTIC
D~ign
of the Control logic
There are four se parate outputs: one for the inlet valve, one for the outlet valve, one for the hca te r, 3nd one for the ala rm. We w ill approach the design a. four ICpilrate logic circuits.
2 79
280
•
COMB IN ATIONAL l OGIC ANALYSIS
TABLE 5-7
Tru th table (or ta nk control logic..
INPUTS Ltl
Ll
Ttl
Tc;
0
0
0
0
0
0
0
0
0
0
0
0
0
H
A
0
0
0
Fill/heat off
0
Fill/hem on
0 0
0
0
1
1
0
0
0
0
0
0
1
0
HlIlheat off/alarm
0
Temp M:nsor (all itialam i
0
0
0
0 0
0
0
0 0
0
Fill and drnin/hem olT
0
Fi1Ilheat o n
0
0
Filllheat off/alarm
0
0
0
Temp sensor fllili tiahiffil
0
0
0
Level sensor fau lt/a larm
0
0
0
Le"e1 sensor fau lt/lllann
0
0
0
0
0
0
1
Mul tiple semor faulti
0
0
Drninlheat off
0
Heat on
0
0
COMMEN1S
VOUTlH
0 1
0
I
OUTPUTS VINLET
0
0
0
I
Level sensor fllu ltia laml
0
0
1
0
0
0
Heat off/lllllrm
0
0
0
Temp sensor faul tia larm
FIGURE 5-49 K<>.rllitugh ~p limplifiuoon and impleme ntation for the in te t valve logic.
'", , " ", , , 0 , 0'
00 01
"
0
0
0
0
0
0
0
0
0
'" -
-
Irlt-I FT
LH 'lI+LI(T(
(3) Mnp for VIf', I£'f
(b) Lugic CirellI!
!ign ing t he logic c ircuit fo r th e inle t
a re
The inputvariablCl, 4t. Lv THo a nd Tc ~p variabl.,., 3nd the .utes o f VINl.(f
villve logic relulb in the NAND
valve . Th e output o( t hil logic cin::;u it is
Me
plotted
implemCfllation
the varia ble V;NIEf' The fir'lt , te p i, to transfe r t he data from the truth table to
Figure 5-49(a). The Os o n the ~p are fOf the input conditionl wh en the inlet valve
a Ka rnaugh map a nd develop <,n SOP exprenio n.
conditionl whe n the inletvalvc is open.
Inlet V<'ive logic
l eI' , begin by d e-
3nd
grouped .11 !hown in
i, c10!0Cd, and the I, are fat- the input
The relUlting SOP Cl
mown in part (b).
OvtIet Valve logic Next. ret's design the logic cirOJit for t he oullet valve. The output of this logic cil'OJit is the Vilriable VOUTUT'
DIGITA L SYSTEM APPLICATION
•
28 1
FIGURE 5-50
K.!rnaugn m
..
ro
01
00
0
01
10
0
" 0
I
0
0
0
"
I
0
0
0
10
U
0
"
U
0
'. - ----, \ (11'1"1 I 1
( It) M ~p
fOf Vouru::r
f b) logic ci r~uil
Again. the first slep" to t l'ilmfe\" the data from the truth table to .. KarfliWgh map and develop an SOP expr~sion. The input variables. L." LIJ T1" and Tc are map variables and the stales o f VOUTUT are plotted and grouped as shown in Figure 5- 50(a). The Os o n tile m
-
the input conditions \.\/hen the outlet va lve is d osed, and the Is are for the input conditions when the va lve is open. n ,e resulting SOP expression for the outlet va lve logic resulu in the NAND implementation shown in part (b). VHDl Code (Of" the Inlet and Outlet Valve Logic (optional) A single entity a nd architecture describes
the inlet valve logic a nd the outlet valve logic using the data flow approach '" the prog,..,m shows.
A photo of .. s~ tank mock- up in the electronic' I.. h at Yuba CoII~ in California. Tht, control Iogil; hal been progl'illflmed into .. PLD on ~ development boord a.nd is connected ro the tank fIXture! ro control the filling '}nd emptying of the t ank. Photo courte
entity TankControl il
port (u. LH, TH, TC in bit; Vinlet, Voutlet: out bit); end entity TankControl; architero..e VaIvclogOc ofTankControi if begin
been written. Now it's your tu rn to
and inverter! to implement the
complete lrn: remaining control logic design fo r the he.,ter control .,..d the
c ircuit.
a larm and to write the VHDl progl'ilm lo implement the logic in a ~rgel device.
Vinlet <= ( not LH and not TH) or
(not LH and not TC);
System Auignment
Voutlet< = LL and not TH and not TC; end architecture Vi.lIveLDgic; The inlet .. nd outlet V
• Activity 1 Using Table 5-7 a nd th e Karnaugh map method, de'ign the Jogic for co ntrolling the heat ing element in the ti.lnk. Use NAND gales
• Activity 2 Design the logic fo r activa ting the a larm. • Activity 3 Combine the logic fo r each of the four tank control {u,lctions into a complete logk diagram. Wnle the \lHOl entity and .. rdlibxbJre for ti le complete logic by modifying the code prevKxnly developed fat- the inlctand outlet valve logic.
• OptiOtlaf kJ.M'ty
282
•
COMB INATIONAL l OGIC ANALYSIS
•
AND-OR logi!.: producc," an output expression in SOl' fonn.
•
AND-O R- hwert logic produces
•
The operational symbol for exclusive-OR is Ell . An cxclusive-OR e"pression can be stateU in two equivale-n t ways:
llii
KEY TERMS
+ A8
= II
iI
complemented SOP fOim. which is actua lly a
pas fOlm.
eB
•
To do l\ll ann lysis of II logic circuit. start wi th the logic circuit. nnd develop the Boole-nn out put ex pression or the tmth table or both.
•
Implcmentation of II logic circuit is the process in which you StlU1 with the Boolean out put ex pressions or thc truth t
•
All NAND or NOR logic diagmms should be drawn using
•
When t.....o negat ion indicators (bubbles) are coonected. they elTec th 'ely cancel each Olher.
•
A VHDL component is a predefined logic function stored for liSt' Ihroughout n program 01' in other program~.
•
A component
•
A VHD I.. signal effectively acts as nn imernal in terconnection in description.
in~tantialion
is used to cnll fOf" a component in a progl1lm. 1\
VHD L structural
Key terrTH and other bold term! in the chapter ,ue defined in the end--of-book glosyry. Componenl A VHDL fCllture thaI Clln be used to predefine a logic funct ion for mu ltiple usc throughout a program or programs. N"cgath'c-AND The dua l operation of (l NOR gatc when the
inp\J t ~
are active-LOW.
Ncgath'c-OR The dual operation of a NAN!) gate when the inputs are IlCtive-LOW. Node A ..."o mmon connection point in n circuit in whic h 11 gate outpu t is conntlCted to one or mo.-e gate inpu ts. Signal A w3veroml; a type of VHDL objttt Ihnt ho lds dala. Signultral"ing A troubleshooting tcchn ique in whic h waveforms 11ft' cbserved ina step-by-step mo nncr beginn ing aL the inpu t and working toward the- output or vice vt:l";a. Al ead, poi nt Ihe obsc f"l'ed wavdonn is Cfll\lPllrcd wi th the correct signn l for thul point.
Unh 'crsal g.lIe Either a NAND gate or 11 NOR gntc. The term ullil"el".mJ refers to the property of a gat e Ihnt pemli ts nny logic function to be im pleme nted by thaI gMe or by II combination of gllles of that kind.
AnSW"e11 are at the end of the d"klpter. I. 111e ou tput expression for an AN D-O R circuit hav ing one AND gate with inputs A. B, C, and D and one AN D gale with inptlls E ruld F is
(a)ABCD£F
(c)(11 + /3 + C
(b) A
+ D)(E + I-l
+ B+
(d) IIBCD
2. A logic circuit wilh an output X = ABC
C
+ 1J + £+ F
+ £I:
+ lie consislS of
(a) two AND gntcs nnd one OR gnle (b) two AND gMes, one OR gale, and
tWO
inverters
SELF-TEST
(e) Iwo OR gmes, one AND gate, and Iwo invel1crs (d) twO AND l;atc5, one OR gale, lind nn e invCT1er
3. To imp!emenl the expression ABCI)
+ ABCI) + AlieD, ilta kcs one OR gate and
(a) one AND gale
(b) thn.."e AND gal c.~ (d th ree AND gates and four inve rters (d) three AND grtles and three inverters
4. The expres.~ ion ABCD
+ ABCD + ABCD
(a) cannot be simpJifit."d (b) call be simplified to
ABC + AS
(el can be ~ implified to ABCD
+ ABC
(d ) None or these a nswers is correct.
5. The output expression fo r an AJ'\JO -OR-lrn:ert circuit ha ving one AND ga te with and D and one AND gate wi th inputs E and F is
e.
(a)ABCD
+ EF
+ I) + E -t F + C + D)( E + F) (d) (1\ + Ii + C + D)(£ + F) (b) A + B + C (e) (A
+
8
6. An exclusi\'e-OR function is
+ AB (e) (Ii + B)(A + 8)
(a)AB
expre~.~ cd
as
(b)AB + AB
(d)(1i
+ 8) + (A + 8)
7. The AND operntion ca n be produced with (a) two NAN D gales
(b) Ih ree NAND gales
(e) one NOR gate
(d) three NO R £Illes
8. The OR opemtion can be produced wi th (n) two NOR gates
(b) th rcc NAND gates
(e) fnur NAND gates
(d) mth illlSWCrs (a) and (b)
9. When using dual ~Yll1bol s in II logic diag illm. (a) bubble outputs are col1Jlt:Cted \0 bubble inputs (b) the NA ND symbols produCt" the AND operatio llS (e) the negative-OR symbol s pro
(d) A ll of these answers arc true. (e) None of these answe rs is true.
10. All Boolean expl"Clisions call be imple mented with (Ill NAND gat e~ (111). (b) NOR gates only (e) combinations of NAND and NOR g lll es (d) combinations of AND gates, OR gllles. and inva1ers
(e) nny of the sc 11, A V HDL cm npnnc nl (~)
can be lISed once in cach program
(b) is II predefined dcscript ion of a logic function (e) ca n be tI~ multiple times in a pm£lam (d) is part of a data flow descri ption (e) answer!; lb) and (cJ
i nput~,
A, B,
•
283
284
•
COMBINATION A L LOGIC A NALYSI S
12. A CQmponem is calk-d for use in
H
progrlilll by using a
(u) signal
(b) VOl riOlblc (c) component ins tan tiation (d) architecture declarntiun
PROBLEMS SECTION 5 - 1
AniwefS to odd-numbered problem! are at the end of t he book.
Basic Combinational Logic Circuits I . Draw Ihe ANS I di51incti ve shapt: logic diagrOl m for a 3-wide, 4-in put AN D-O R-Invert circuil. Also draw the A NSi stanool'd rectangulilr ou tli ne sy mbol. 2. Wri te the output e};pre~sion for each circ uit in Figure 5- 5 1_ 3. Wri te the output expression fm- each circuit a.. it appcurs in Figure 5- 52 .
,
.
H~
>o-x
'r=== Ib)
I') FIGURE 5 - 5t
A
h " 11 D- x " 11 (.)
>U-x
(b)
A--l>o H
P- '
Ie)
A
., 8
"
" 1I
C (d)
~x
(e) FIGURE 5 - 52
H
X
C
'"
4. Write the output expres~ ion for CIIc h circuit a.~ it appears in Figure 5- 53 and then change each circuit to an equivillem AND-O R configurati on.
S. Deve lop the trut h table for each ci rcuit in Figure 5- 52. 6. Develop the tru th table for ellch ci rcuit in Figu re 5-53. 7. Show thai an exclus ive-NOR circuil prodU<.'t:s a PUS ou tpul.
PROB LEMS
•
:_D~ C ~~ ' -
f)
D - -- - - - L __
--1._/
(b)
"J
•
" C D
<,I
, "
i???=>p·
f)
X
E
c
G
(c)
/I (0
FIGURE 5 - 53
SECTION 5-2
Implementing Combinational logic 8. U.se AND gates, OR ~'\Ie". ellpressions as stated:
<)f
com binations of hoth to impkmcnt tb e follf:Wing logic
(a) X = AB
(b) X = II
+B +C
(c) X - A 8
(d) X = ABC+D (e) X = A + B + C (OX =A BCD (g) X = A(CD + 8) (h) X
=
A8(C + DEf)
+ CECA + B + F)
9. Use AND I;!ates. OR gates. and invcrter1\ as needed 10 implclllC."nt Ihe following fo/;!ic expressions 11.~ staled:
+ Be AB + AB
(b) X = /\ (8
(e) X =
(d) X = ,\Be + B( EF
(e) X = A[BC(A + B + C + 0) 1 10.
+ C)
(a) X = AB
U~
NAND gales. NOR gates.
(I) X ~ B(CDE
orcombinati()l1~
expressions a~ stalt'd: (a) X = AD + CD + (II (b) X = ABeD + Dff (e) X = A[8
+ 8)(ACD + BE)
+ IIF
+ C(O + E)l
+ C)
+ EFG)( AB + C)
of both 10 implement tht: followi nl;! log ic
285
286
•
COMB INATIONAL l OGIC ANALYSIS
11. Implement a logic circuit for the tnnh table in Table 5-8.
TABLE 5- 8
A
o o o o
INPUTS 8
o o
C
I
OUTPUT
I
X
o o
o o o
o
o
o
o
12. ImpleOlCm a logic circuit
fOT
the truth table in Table 5- 9.
TABLE 5 _ 9
A
INPUTS 8 C
0
a~ much as po.~s ibl e. and verify that the simplified circ uit is equivalent to the original by showillg that Ihe truth tables aTC identicaL
13. Simp lify the cin:uit in Figure 5-54
14. Repeat Problem I3 for the circuit in Figure 5-55.
PROBLEMS
•
287
n
x
c FIGURE 5- 55
FIGUR£ 5-54
IS. Minimin.' the gates requi red to implement Ihe funclions in c;lch part of Problem Y in SOPforffi. 16. Mi nimi ze the
gatc ~
rctju ircd to implcmCl1llhe functions in cu.:h pllrt of Problem 10 in
SOP form. J7. Minimize the gates required 10 implement the function of the circuit in each part of Figure
5-53 in SUP ram .
SECTION 5-3
The Universal Property of NAND and NOR Gates 18. Implement the logic circ uit~ in Figure 5-5 1 US ilig only NAND galcs. 19. Implement the logic circuits in FigllfC 5-55 using o lily NAND gates.
20. Repeat Problem 18 using only NOR galcs. 21. Rc(X'
SECTION 5-4
Combinational Logic Using NAND and NOR Gates 22. Show how the fol lowing expressions can be implemented M Sialed using only NOR gates: (a) X = tlBC
+ B +C t\B(C(DE + AB) + 8(:1.:"]
(d) X = A
(g) X =
(b) X = ABC
(e) X = AB +
(e) X = A
CD
+B
(f) X = (A + B)(C + D)
23. Repeat Problem 22 using only NAND l;atcs. 24. Implemelll em:h fu nction ill Problem 8 by
u~ingonly
NAND gme~.
25. Implement each ftlnction in Problem 9 by using only NAND gatt:s.
SECTION 5-5
logiC Circuit Operation with Pulse Waveform Inputs 26. Gh
FIGURE 5 - 56
fiGURE 5 - 57
288
•
COMBINATIONAL LOGIC ANALYSIS
211. For Ihe illpul waveforms in Figure 5-58. whallogic ci rcu il will gcne rme lhe outpul waveform show n? FIGURE 5 - 51
A
InpliiS
OUlput X 29. Rcpeat Problem 28 for the waveforms in Figure 5- 59.
A ~~
FIGURE 5 - 59
" ...J~::::::::::::::::~±j=r=== ,
I","" CI Output
I
---'HL _ _ __
X ______
30. For the circuil in Figure 5--60, draw the waveforms al the li umbered poi nt~ in Ihe proper relationship 10 C3l;h Olher. 3 1. Assumi llg a propagation delay through each gale of 10 lIanoseconds (n~). detenniue if Ihe lfesirelfoutpu l wavcfonn X ill Figure 5-6 1 (a pulse wi lh a minimum/IV = 25 liS POSiliollcd as shown) will be generaled properly wilh the given inpu ts.
A
....r:Tl--fT:L.
n ~
- <: : H !..i-rl " '" I.!!..l /} : n : : n : C E
::11l::::f: :r:::: ~
r~
A~ J
B
C
~r _
4
2 _ _ _ _ _-',-1---/ ~x _ __
FIGURE 5 - 60
~ I G'~G ~ G 3
E -----------1~
X
FIGURE 5 - 61
SECTION 5 - 6
Combinational Logic with VHDL (optiooal) 32. Write a VHDL prog ram u., ing the dala now approach (Booleall expressions) 10 describe the logic circuit in FiEu re 5-5 lib). 33. Wri le VHDL progrnms using the data flow approach (Boolean expressions) for Ihe logic circuits ill Figure 5-52(e) and (f).
PROB LEMS
•
289
u.~ing the ~tntctural approach for the logic cin:u it in Figure 5- 5311.1). Assume component declarations for each type of g
34. Wri te a VI-IDL prog ram
35. Repeat Problem 34 for the logic circuit in Figu re 5--53{f) . 36. Describe (he logic represemed by the truth !able in 'Ulble 5-8 usin g VHDL by first convert ing it to SOP form. 37. Develop a VHDL program for the logic in Figure 5-64 (p. 290). using both the data now and the structural approach. Compare the resulti ng programs. 38. Devclop a VHDL program for the logic in Figure 5--68 (p. 291). u~ing both the data nnw and the struclUral approach. Comp.1TC the resulting program s.
39. Given the follo..... ing VI IDL program. create the truth table Lhat d=ribcs the logic eircui t. "nt ily CombLogie is port CA. B. C. D: in bil; X: Ollt bi t):
rod enlity CombLogic; architecture Example Or CombLogic is
ht.';n X <= nol« nOI A a nd not B) or (not A 311d not C) or {not A and not DJ or
(nut D Dnd nol C) or( nol 8 a nd nul DJ or (nol D and IIOt C» : end archilecture Example:
40. Describe the logic circuit shown in Figure 5-62 with a VI-IDL program. lL<;ing the data n O"'1 approach.
41.
SECTION 5 - 7
Rc~at
Problem 40 using the structural approach.
Troubleshooting 42. For the logic ci rcllit and the inpu t waveforms in Figure 5-63. the indicated oulpul waveform is observed. Determi ne if this is the COITCCI QUlpul wavefOTm.
FIGURE 5-63 A
n
---fl-f1, ,
---rT1--+:
:
I
A
IJ
I
c~
C
D ~
D -L-~
,, ,, , ,
X ~
290
•
COMBINATIONAL LOGIC ANALYSIS
43. The output wavefo rm ill Figure 5--64 is incorrect for the input'i Ihal arc applied to tOe c ircuil. Assuming Ihat one gale in the circuit has failed. with ils output either an apparen t constant I-IIGI·[ or a constant LOW, determine the fau lty gale and the type offai lure (OIJtput open or shorted).
FI GURE 5- 64
A-/
~
A
8-t--n, , c" c~
{) -tl---ri-£~
,, ,,
D
£
X~
44. Repeat Problem 43 for the circuil ill Figure 5-65. with illput and output wavefonns as shown. 45. By examining the connections in Figure 5--66. determine the driving gate and load ~atc(s). Spedfy by device and pin numbers.
A A ~
8~ ,
"
C~ /J ~ ,
0
"" , ""
"" ,, "HF J"lli..n..hJi.. "" ""
E
,,
",
C
X
E
G,
F-
x ~
FIGURE 5 - 65
FIGURE 5 - 66
46. Figure 5-67(a) is a logic circuit under tes\. Figure S-67(b) shows the waveforms as obM!r\'ed on a logic analyze r. The output wa\'eform is incorrect for tOe in pllls thai arc upp lied 10 the circuit. Assuming Ihat ant: gate in tOe c ircuit has fai led. with its output either an apparent constant HIGI-I or a constant LOW. determine the faulty gate and the type of fa il ure.
FIGURE 5 - 61
A B A
B
c D £ F
c G, G, G,
{)
,
G
X
E F
X
,,'
,b)
~
,,
JI
,,, , I
11
H
I
,,
L
PROBLEMS
47. -Inc logic c ircuit in
Fi~ urc
5-68 has the inpu t
wa\"efonn~
•
291
shown.
(a) Determine the corree! output waveform in re lation to the
inpul~.
(b) Dete rmine the ovlpul waveform ifthc output of gate Gl is ope n. (c) Determine Ihe out put waveform if the upper inpullo gale G\ is shot1 ed to ground.
fiGURE 5-~6~',-_ _ __
_
A ~ B
I I
' I
I I
II I I
I
~ ~
c !!
~ I
i
I
~!
~
~
: :----:-; ~
:!
I--+-i :
H r
D~ ! ~ : £ '
I
I
'I
:
x
c D
----=-----'=E>-~
E -- --
-
---'
48. The logic circuit in Figu re 5-69 has onl y one intermediate lest point avai lable besides the output, as indicated . for the inputs shown. you observe the indicatc
fiGURE 5-69
TP
8:'"J::::[}:::;:=i: ,,;,~ !! ! H :: c ~~ A
: : D "~,-.-, ! ~ E:---t-4 : ~ ; ; I--i--l " F r~ I I I I I r I
r
I
!
TP
I
I
~==:[=)
x
I
LJ
Digital System Application 49. Impleme nt the in let va lvc logic in Figure 5-49(b) using NOR gates and inverte rs.
50. Re peat Problem 49 for the oullet valve logic in Figure 5- 50(b). 51. Implement the heater logic and the alarm logic using NOR gates and invcrters.
Special Design Problems 52. Design a logic ci rcuit to prod uce a HIG I-I outpu t only if the input. represented by a 4-bil binary number. i~ greatcr th an twelve or less than three. First deve lop the tn,t h tHble and then dl'3.w the logic d iagrnm.
53. Dcvdop the logk circuit neces.<;.lI1)' 10 rnccl lhe followi ng req uire ments: A hmlcly-powercd Iil mp in a room is to be operaled from two switches, olle at thc back door and one at the fron l door. The lamp is to be on if the front switch is on alld the mlck swilc h is 01T. or if the front swilch is off and lhe back swi tch is on. The lamp is 10 be 01T if both switches arc olT Of if both switehcs are on. let a I-IIGH output rcprescnt lhe on conditi on and a LOW output represent lbe ofT (;ondit ioll.
54. Design a ci rcui t 10 enable a chemical ad diti ve to be introduced into the fluid Ihrough anQ{her inlet only whcn the tcmperatu re is nOI too cold or 100 hot and the fluid is ahove the hig hlevel sensor.
55. Develop the NAND logic for a he xHOecimal keypad encoder thai will convert eac h key closure to biliary.
292
•
COMBINATIONAL lOG IC ANALYS IS
Multisim Troubleshooting Practice 56. Opcn fi le P05-56 and tCSl lhc logil' circuillO dclennine if lhere is a fault. If there is a fau lt. ident ify it if possible. 57. Open file 1'05-57 and i
[~Ithe
logic circuit to determine if there is a fault. If there is iI fau lt,
58. Open fi le P05-58 and test the logic circuit to determine if there is a fault. If there is 11 fault. identify it if possible. 59. Open file P05-59 and test the logic circuit to determine if \hcl"C is a fault. If there is a fault, idellt ify it if possible.
SECTION REVIEWS SECTION 5 - 1
Basic Combinational logic Circuib (c)
+ AB + CD = O·] +
(3)
Ali+AB = 1,0+ 1,0 = I
(c)
AB + AB = O' I
I. (a) A8
2.
+
CD = ]·0
1·0 = I
(b) A8
+ CD
(b) Ali
+ AB = J. 1 + I · I
(d) Ali
+ A8
= ].]
+
0, ] =
°
I·] = 0
+ O' J =
I
.. 0
= 0·6 + 6· 0 = 0
3. X = I whenA8C = 000,0 11.101. J 10. and II I: X = o when ABC = 001. OJ O. and 100 4. X = AI] + AB: thccircuit consists of two AND gales, one OR gate. and I \~O inveners. Sec Figure 5-6(b) for diagram.
SECTION 5 - 2
Implementing Combinational logiC l. (a) X = ABC + AB + AC: th ree AND !;ates. one OR gate
(bJ X = A/J(C + DE): three AN D gales, OJJC OR gate
2. X = A8C + ABC; two AND !!ate~. one OR g
SECTION 5-3
The Universal Property of NAND and NOR Gates I. (a) X = A + 8: a 2-input NAND gate wilh II and B on its inputs. (b) X = 118: a 2-input NAND withA and 8 on ils inpu l~ , follO\\"Cd by one NAND used as an ill\"erter.
2. (al X =
A + 8: a 2-inplll NOR witn inputs A lind B.
followed by oue NOR uscd ~ an
in\~rler.
(b) X = AB: a 2-input NOR with A and B on its inputs.
SECTION 5-4
Combinational Logic Using NAND and NOR Gates I. X "" (A + B + C)D£: a 3-inpul NAND Wilh inputs, A, B. and C. wi th ils outpUi conlK-"'Cted to a second 3-inpul NAND with two other illPUIS, D and £
2. X = ABC + (D + E): a 3-input NOR with illpulS A, B. and C. wilh its output connected 10 a SCi:tlnd 3-inpu l NOR with two ()(her inpu ts. D and £
SECTION 5-5
Logic Circuit Operation with Pulse Wavefonn Inpub I. The c"dusive-OR output is a IS/iS pulse rollowed by a 25 /-IS pulse, Wi lh a between the pulses.
separ~tion
or IUJJS
2. The out put o fthc exclusivc-NOR is HIGH when both inputs are HIGH or \\hcl1 both inputs arc LOW.
SECTION 5-6
Combinational logic with VHDL (optional) I. A VHDL componL'f1t is a predefined program describinB a specified logiC" runction. 2. A component inSiantia/iOn is used 10 call lor a sp.:dfied component in a program architectUl'e
ANSW ERS
•
293
3. Interconnections between components are rrmde using VI-IDL sig.nals. 4. Components arc
SECTION 5-7
u~d
in the structural approach.
Troubleshooting J. COlll mon gate fa ilure s ure illput or output ope n: input or ou tput shoncd to ground. 2. Input shoned to Va: causes outpultO be stuck LOW. 3. (3) G~ output is 1·IIGU IJlui l rising edg.e ofscvcnth pulse. the n it goes LOW. (b) G., output is the same as input D. (e)
G., outplll is the invcrsc of the G~ output shown in Figure 547/b).
RELATED PROBLEMS FOR EXAMPLES 5-1 X = AB+JlC + BC 5-2 X = AB + AC+ BC If A = O,mdB = O.X = O·O + O· 1 +0· 1 = 0 = I If A = OandC = O. X = 0 · 1 + 0 ·0
I
Iff) = O.lJ1dC = O. X = I ·n
I
5-3 Cannot be simplified
+ 1·0 = 0 = + I·n + 0 ·0 = 0 =
5-4 Cannot be simplilied
5-5 X = A+B + C + Disvalid. 5--6 Sec Figure 5- 70.
FIGURE 5 - 70
H- -.-L /
?==~::::~_J 5-7 X
=
(A BC) (DEF) = (AB)("
+ (DE)F
=
(A + B)e + (D +
E)F
5-8 Sec Figure 5-7 L FIGURE 5 - 71
7.' ~ H C
'b,
'0' 5-'J X = (A + 8 + C) 5-10 Sec Figure 5- 72.
A
ABC+tJ.f:
ABC. Of
lH
+ (D + E + F)
= (II + 8 + C)(V + E + F) =
5-11 SceFigure5-73.
()1l - - - - - - - - - - - -
,,
/I C
X
"
FIGURE 5 - 72
FIGURE 5
13
(AB
t
C)(DE-t F)
294
•
COM8 1NATlONAllOGIC ANALYS IS
5-12 Sec Figure 5- 14.
5-13 Sec Figure 5-15.
A L-IL-f'~ I.
"
==t:j C:t==~JL~::~':j--+--t:j' ~ , ' ,!' /) r--u ,:::;--;::::::;::::ti' ::~I~i__tf-ij U" :: y, ' t::W:~+!J ,
I :
I
•
I I
,
Y1
I - ,
Y) ,
I
I
, ,
I
--f-+--+--f-+-+-iL.l......fi ' , , I'~rI
X
'L
--'---'---'
FIGURE 5-74
FIGURE 5-75
5-14 G5: NAND...,g IN9, 0 - > IN IO, X - > OUT4);
5-15 Sec figure 5--76.
FIGURE 5-16
SElF-TEST I. (d)
9. (d)
2.. (b) 10. (e)
~eJ
4. (a)
II. (e)
12, (e)
3.
S. (d)
6. (bJ
7. (aJ
8. lO)
CTI
F
CHAPTER OUTLINE
6- ' 6-2
Basic Adden
6- 3
Ripple CalTY venus look-Ahead Carry Adders
6- 11
Troubleshooting
I:m
Digital System Application
Pilrallel Binary Adden CHAPTER OBJECTIVES
6- '
Comparators
Dilon&uilh between half-adder! and fu ll-adder!
6- 5
Decoders
Use full-adden. to implement multibit p
6- 6
Encoders
6-7
Code Converters
6- 8
Multiplexers (Data Selecton)
6- '
Demultiplexers
6- 10
Parity Generato rs/Checkers
Explain the djffere~ between ripple Qfry .)nd look-ahead Q rry ~Qltel adders
•
Ule the magnitude comparator to determine the relationship between two binary number! and use asc.xIed compariltOr! to handle the ccmP"'rilon of larger numbers
Implement a bask bin
INTRODUCTION
Us.e BCD-to-l- .egment de(oders in displ"f s)'\tems
App ly a dec: ilTlOll-to-BCD priority enooder in i'I simple keyboi'Ird i'lppliation Convert from binary to Gr"f c:ode, and Gray code to binary by ming logic:: devi(eI
In this chapter, several types of combinational logic circuit! are introduced including adden, compar
Apply multiplexen in data selection, multiplexed di!pl¥, logic function generation, and simple (ommuniatiom lysteJru
FIXED-FUNCTION LOGIC DEVICES
Use dec:cden al demu ltiplexers &pli'lin the meaning of parity Us.e parity genefiltors i'lnd c: hed
74XX42
74XX47
74XX85
74XX138
74XX 139
74XX 147
74XXT48
74XX 151
74XX 154
74XX157
74>0<280
74XX283
systeml
Implement a simple dab communiatiom Iystem Identify glitc:he, (Ommon bugs in digital ,),\teJru
kEY TERMS
Half-adder
Encoder
Full-adder
Priority encoder
CaKading
Multiplexer (MUX)
Ripple carry
Demultiplexer (DEMUX)
look-ahead carry
Parity bit
Decoder
Glitch
•••
DIGITAL SYSTEM APPLICATION PREVIEW
The Digital System Application illustrates concept! from this chapter and deals with one portion of a traffic light control system. The system applications in Chapters 6, 7, and 8 focus on various part! of the traffic light control system. BaSically, this system controls the traffic light at the intenection of a busy street and a lightly traveled side street. The s~tem includes a combinational logic section to which the topics in thii chapter apply, a timing circuit section to which Chapter 7 applies, and a sequential logic section to which Chapter 8 applies.
i'.
VISIT TH E COMPANI O N WE8S1Y"' - - - - - - - - -
Study a ids for this chapter ilre available ilt http://www.prenhall.comlfloyd
297
298
•
6-1
FUN CTIONS OF COMBINATIONAL LOGIC
BASIC ADDERS Adden. are importam in compulers and also in other types of digital systems in which numerical data are processed. An undeThtandi ng of the ba ~ic adder operation is fundamen tal to lhe study of digital systems. In this sect ion. the half-adder and the fu lladder are introduced. Arter completing this section. you should be able 10 • Describe the function of a half-adder _ Draw a half-adder logic diagram • Describe the function of the rull-adder • Draw a fu ll-adder logic diagnun using half-adders • Implement a fu ll-adder using AND-OR logic
The Half-Adder A half-adder add! I:w'o bib and produceJ a IUrn and a carry output
Recall the basic niles for binary addition as stated in Chapter 2.
0 + 0= 0 0 + I= 1+ 0 = I
+
I = 10
The operations are performed by a logic circu il called a half-adder. The half-adder accepts two binary digits on its inputs and produces Iwo binary digits on its outputs, a sum bit and a carry bit. A half-adder is represented by the logic symbol in Figure 6--1. FIGURE 6 - 1
r
logic
A
r SIIIlI
}
Oull'tJl~
C" I1""1
Half- Adder Logic From the operation of the half-adder as slated in Table 6- 1, expressions can be derived for the sum and the output carry as functions of the inputs. Notice thai the output carry (C....,,) is a I o nly w hc n both A and B arc l .~: thel cforc. CUll' call bcclipl essed a~ the AND of the input variables.
Equation 6-1
C",,, = AB TABLE 6 _ 1
Half-adder truth table.
A
B
C O"'
E
o o
o
o o
o
o
o o
"<~ C_ '" 0Il1p\l1 cany
A IlJId IJ - mpul variOOle$(ope<:m}
BASIC ADDERS
•
299
Nowohscrvc that the sum output (1:) is a I only if the input vari
'nl C
L = A EB B
Equation 6- 2
Frum Equations 6- 1 and 6-2 , the logic imple mentation requi red for the half-adder function can be developed. The output carry is produced with an AND gate with A and n on the inputs, and the Sllm output is generated with an exclusi ve-OR gate, as shown in Figure 6-2. Remember th m thl' excl usive-OR is implemented with AND gates, an OR g
Half-adder logic diagram.
The Full-Adder The second caLCgUlY of adder is the full -adder. T he full-adde r accepts two input bits and an input carry and generates a sum output and an QullJut carry. The basic difference between a full-adder and a half-adder is that the fu ll-adder accepts an input carry. A logic symbol for a full-adder is shown in Figure 6-3, and the truth table in Table 6-2 shows the operation of a full-adder. FIGURE 6 - 3 Inpm { h'b
, -
-s..,,,
logic .-;mOOI fOf.1l full-adder. Open file F06-03 to verify operation .
•
TABLE 6 - 2
A B C," 0
0
0
0
0
0
1
0
0
0
0
1:.
C
rull-adder truth table.
0
0
0 0
0
0
0
0 0
0
Coo'" ;npul t·arry. ,..,.,....1i~dt:!;il!1\4led II!i Cf
C... - WIJllII QJ.rry. "'-lIl1<.1hncs dcslgnulC
L=
co
>Urn
II and IJ - input wriOOlcs {op•."ronds )
FuJI- Adder logic;
llle fu ll-adder must add the two input bits and the input carry. From the half-adder you know that the sum of the input bits A and B is the exclusive-OR of those two
A fu ll-adder hal an input carry while the half-adde r does not.
300
•
FUNCTI ONS OF COMB INATIONAL l OGIC
variables, A@B. foor the input carry (Cin ) to be
This means that to implement the fu ll-adder sum fu nction. Iwo 2-inpul exclusive-OR gales can be used. The first IIllISI generate the term A @ B. and the second has as its inpUis thc oUlpul of the first XOR gale and Ihe input carry. a<; i ll u.~tralcd in Figure 6-4(a).
1 ~ \fI
'" \/Ii
" =--_ 'L/~ LD- 'o'
II>
(a ) Losie l"C(j uired to fo rm the Mlill of lhret: hils
(h ) Complelc 10j!1C eireuil for a full -adder (cach holf-oddCf
i~
coe tQ!;Cd
by 0 shaded arca)
:FIG ;1£ 6-4
FuJI-adder logic. Open file F06-04 to verify operation.
The OUlput carry is a I when hath inputs 10 the first XOR gate are Is or when both inputs to the second XOR gate are Is. You can verify this fact by studying Table 6-2. The outpot carry oflhe fu ll-adder is therefore pnxluccd by the i npul~ A ANDed with B and A @B AN Ded with C,,,. These IWO terms arc ORed. as expressed in Equation 6--4. This hmction is implemented and combined with the sum logic to form a complete fu ll-adder circuit, as shown in Figure 6-4(b). C"", = AB
Equation 6-4
+ (A@B)C;n
Notice in Figure 6-4(b) therc are two half-addcl"S. connccted as shown in the block diagra m of Figure 6-5(a). wit h thcir Oll/put carries ORed. The log ic symbol shown in Figure 6-5(b) willnorm
UDt f-uddcr
r
-
A
-
/J
,
r E
C_
"
E
A
C_
B
R,(·
I "
~
"
8
1 .'1 ...
(0) Arr"nl:!cmc,u oflW
h~lf-uddcrs
r A
10 fonn a full-atltlcr
FIGURE 6-5
Full-adder implemented with half-adder<.
E
C_
Cin (b) Full-adder logic
~ymbol
PARALLEL BINARY ADDERS
I
•
30t
EXAMPLE 6 1
For each uf the three rull-adders in Figure 6-6, dClcnnine the OlllplllS for the inputs shown.
,--
A
n
B
E
E
E
A
"
L
11 - - Cin
B
c,. II
C_
n
C.
"
B
C_ Coo
'bI
(a)
A
,<)
FIGURE 6 - 6
Solution
(a) l11e input bils arc A = I. B = 0, and Cin = O.
1 + 0 + n = I with no carry Thererore,1: = 1 and COlli =
o.
(b) The input bilsare/\ = I.B = I,and C", = O. I + I + O = Owithacarryofl
Thererore. 1: = 0 and Cc ... = I. (cl The input bit<; are A = I,
B = O. and Cin
= I.
I +0+ I = O with acarryu r l
Therefore. r = 0 and Related Problem '
C OllI
= J.
What are the foil-adder outpots for A = I . B = I . and Cin = I'! *AnswCrli arc at the end of the chapter.
I
SECTION 6 1 REVIEW
Answer) are.a>t the cod of the
1. Determine the ~um (1:) and the output carry (CouJ of a ha/f-adderfor each set of input bib:
(.) 01 (b) 00 2. A fuJI-adder has Cit>
ch.a>pter.
(e) 10 =
(d) 11
1. What are the sum (r) and the output carry (CouJ when
A = 1andB = 17 ---~
6-2
PARALLEl BINARY ADDERS
Two or more full-adders are connected 10 form parallel binary adders. In thi s section, you will learn the basic operation of this type of adder and its associated input and outpUI fu nctions. After completing Ihi.<;
~ection.
you !>hould be able 10
- Use fu ll-adders to implement a parallel binary adder _ Explain the addition process in a parallel binary adder _ Usc the truth table tor a 4-bit parallel adder . Apply two 74LS283s for the addition of two 4-bit numbers _ Expand the 4-bil adder 10 accommodate 8-bit or J6-bil addilioll
302
•
FUNCTIONS OF COMBINATIONAL lOGIC
Add ition is performed by c;omputers on two numbers at a time. ailed operandJ. The JOurce operand is a number that is to be added to an existing number called the destinoticm operand, I \.Iki ic;h is held in an AlU register, suc;h ill the ac;UlmI.Jlatm. The rum I of the two numberl is then stored ba<:k in the acc:umulator. Addition is performed on intege r numbers or floating-point numben using ADD or fADD instructions respectively.
As you saw in Scction 6- 1, a single full-adde r is capable of adding t wo I-bit nu mbers and an inpUi caJTy. To add binary numbers with mo re than one bit, you must usc additional fu ll-adders. When one biliary num ber is added to another, eaeh column generaleS a sum bit and a I or 0 carry bit 10 the next column to the left, as illustrated here with 2-bit numbers.
I
CaIl) bi! from right column
"
+ 01
100 In this ca.~. the ~ carr) bit f mill second column becorm..'S a su m bit.
I ,
I
To add two binary numbers, a full-adder is requi red for each bit in the numbers. So for 2-hit Ilu mbers, IwO adde n. arc needed; fur 4-bit nu mbers, four adders are used; and so on. The carry out put of each adder is connected to the Catry input of the rleXt higher-order adder, as shown in Figure 6-7 for a 2-bit adder. Notice that either a half-adder can be used for the least signilicant position or the canoy input ofa full -adder can be made 0 (grounded) because there is no carry inpu t to the least significant bit position.
FIGURE 6 - 7
Block diagram of a basic 2-bit parallel adder using two full-adders. Open file F06-07 to verify operation.
~ncntl
tormal. a
A,A 1
+ 8, 8 1
A
LII:~I:I
"
8 C'"
(MSB)!,
In Figure 6-7 the least signilicant bits (LSB) of the two Illimbers are represen ted by At and B I . The next higher-order bits are represented by A2 and B2 . The three sum bits arc rl . ~. and 2::,. Notice t.hat the output carry from the left -most fu ll-adder becomes the m~t significant bit (MSB) in the sum, L.!.
I
EXAMPLE 6-2 Determ ine the sum gcncl"
"
"
r'-!:--:',A
8 C;,
A
-
"
"
,
8 Cin
I
""
PARAllel BIN ARV ADDERS
•
303
lhe LSBs oflh e IWO numbers are added in Ihe right-most fu ll-adder. The sum bit" and Ihe illlenncdiate carries are indicated in blue in Figure 6-8,
Solution
What are the sum outputs when I I I and 101 arc added by the 3-bit parallel adder?
Related Problem
Four-Bit Parallel Adders A group of fo ur bits is called a nibblc. A basie4-bit pamllel adder is implemented with four full-adder stages as shown in Figure 6-9. Agai n. the LSBs (AI and 8 1) in each number being added go into Ihc right-most futl-adder; the higher-order bils arc applied a~ shown 10 the succes.~ i\'ely higher-order addcr!), with the MSBs (A~ and B~ ) in each number bei ng applied 10 the left -most full -adder. The carry o utput o r each adder is connected to the carry input of Ihe next higher·order adder as indicated. These are called illfemal carriel'. I
R;~~{
A, 8,
IIUllllxT ,\
,(MSB
,
,\
e, .. ~
II
c.
A
r
I
,-
,C~
~ c,
A
IJ Cin
r
I
c..." ~ c_
n
Cm
I A
r
C~
I ~"
(u ) Bloc k diagram
II
C.
l 3 4
C;,
R,.," {
,,-Sill
num""'r tJ
r
..
I "
Inl'tlI ~
rU }H" ~ um
D" C,
C,
Output carT}
(b, Logic symbol
FIGURE 6-'1
A 4·bit parallel adder.
In keeping with most man ufacturers' data sheets, thc input labcled en is the input carry to the least significant bit adde r; C4 • in the ca..e of four bits, is the output carry of the mOSt significant bit adder: and r l (L..IiB) through r 4 (MSB) are the sum outputs. The logic symbol is shown in Figure 6-9(h). In terms of the method used to handle carries in a parallel adder. there arc two types: the ripple em.,-)" adder and the carry l ook-a head adder. These arc d iscusscd in Section (,-3.
Truth Table for a 4-Bit Parallel Adder Table 6-3 is the truth table for a 4-bit adder. On some dala sheets, truth tables may be called filllc/iolJ wbles orjllllctiollal /mrh tablel'. The SUbscript " represcnts the adder bi t" and can TABLE 6 - ]
0
0
0
0
0
0
0
0
J
0
0
,
0 0
0 U
0
0
J
0
0
0
0
Truth table for each Ibge of a 4-bit pa ra llel adder.
304
•
FUNCTIONS OF COMBINATIONAL l O GIC
be I, 2, 3, o r 4 for the 4-bit adder. Cn _ 1 is the carry frum the previuus adder. Carries C C2 , " and C) arc ge nerated inte nla lly. Cn is an external c an}' input and C4 is an uu tput. Example 6-3 illustrates how to usc Table 6-3.
I
E}(AMPLE 6 - 3 Use the 4-bit para llel adder truth tablr (Table 6-3) to ti nd the sum and o utput carl}' fur the additio n of the following two 4-bit n umbe~ if the input cany (en_I) is 0: A~y40,
Solution
For II
=
I : A,
= 1100
and
= 0, 0 , = 0, and C"_I = O. 1:, = 0
8 4 8)8 2 8 , = 1100
From the I st row of the ta ble. and
C, = 0
For 1/ = 2: A2 = 0, B2 = 0, and Cn _ 1 = O. From the 1st row of lhe table,
L.! = O a nd For 1/ = 3:
A3
C2 = O
= I, 8 ) = I, and Cn _ 1 = O. From the 4th row of the ta ble,
L) = O and For n = 4:A4 =
1 , B~
C) =
)
= I , a nd C,,_I = I. From Ihe last row of the table. ~ =
I
and
C4 = J
C4 becomes the output cany; the sum of 1100 and 1 100 is I 1000.
Related Problem
Usc the truth table (fable 6-3) to fi nd the resuh of adding the binary numbers 101 1 and 101 0.
THE 74L5283 4-BIT PARALLEL ADDER An example of a 4-bit parallel adder that is available in IC fonn is the 74L5283. For the 74LS283, Va: is pin 16 and gmund is pin 8. which is
Four- bit parallel adder. (l6) (5)
---.i!L ( 14) Vox
(12)
63
(6)
A3
rJ
(2)
(15) (J I)
A4 (7)
B4
'"
}
E
,4,
'e
3
}
4
C,
C, (8)
C4 GND (
(OJ 74 LS21i3 tugic symbol
'"
(1 3) ( IO)
(9)
PARAllel BINARY ADDERS
•
305
Ie Data Sheet Characterirtics
Recall that logic gates ha ve one specifi ed propagation de lay time, t p • from a n inp ut to the o ut pul. For Ie logic, the re may be several differe nt specifications fo r I,~ The 4-bil paralle l adder has the four ' " specifi catio ns shown in Fig ure 6- 11. which i ~ part of a 74LS283 data sheet. FIGURE 6 - 11
Limits P3 rurn ~kf
Symbo t
Mi n
Typ
l\'lax
16
24
I'rop.~;).tion
tlclay. Co input lO any!oot pul
tl~.H
tPi tl
tl1tl.
Propall:!lion delay. C4 0utpu l
' PI • H
tl'ltl tl'lJ I
t he 74l5l83. ~
24 24
e" input 10
"'
17 22
ProPlll!alioo del:.)". uny A or B input 10 C~ o ulpu t
I"U.
Unit
" " "" "" "
PropagiltiOil delay. any A or 8 input 10 ! oulpUI~
,~
"'
17 17
12
Pro pagation d e lay c haracteristic! for
"'
Adder Expansion Adders can be expanded to handle more bits by cascading.
11lC 4-bit parallel aJder t.:an be expanded to handlc the addition of two 8-bit numbers by us ing Iwo 4-bit adders. The carry input of the low-order adder (Co) is connected to ground because there is no ca rry into the le,L<;t significant bit position. and the carry output of the low-orde r adder is connected to the carry input of the high-Older adder, a .. shown in Figure 6-12(a). This
.
,,,,
,4 3 2
,
I C..
'--.---' '--.---' 8
, , • ,,
(;,
,,,, 8
,-----..,
c_
~
3 2
, , ,-----.., •,, ,
I Co,
'--.---' '--.---'
C• --.J
-
, (a) Cascading of IWO 4-hit adders 10 rorm an 8·bit
~ddcr
H, 1/ . R. fl.
4 )
2 8
:2 I
4 )
t
'--.---'
4
)
,
:2
1 C'"
'--.---' '--.---'
,
8
,
4 3 2
t
4 3 2 1 C..
,
'--.---' '--.---' 8
,
,-----..,
,-----..,
,-----..,
4 )
4 3 :2
4 3 :2 t
2 1
' .. (b) Cascading offour 4-bil adders FIGURE 6 - 12
Examptel of add e r expam ion.
\0
form a J()·bit adder
I
.
~
'. I
4 1 :2 1
4 1 2 1 C..
'--.---' 8
'--.---'
Co.
8
--
306
•
FUNCTIONS OF COMBINATIONAL LOGIC
process is known as CR....-;;Id ing. No! icc that, in this case, !he OUIPUl carry is designllled Cs because il is generated from tIle eighth bit position. The low-ordcr adder is the one that adds !he lower or less significant four bits inlhe numbers, and the high-order udder I!' the one Ihat adds [he higher or more significant four bits in the 8-bit numbers. Similarly, four 4-bit adders can be cascaded to htUldle Iwo 16-bilnumbcrs as show n in Figure 6-- 12(b). Notice tllal the output carry is designated C 16 OCCHUSC it i5 generated fro m the sixteenth bit IXlsition.
I
EXAMPLE 6-4 Show how two 74LS283 aducrs can be connected to fonn an 8-bit parallel adder. Show output bits for the following 8-bit input numbers:
Solution
(5)
",
A, O
AI ()
(14) (12)
A,
(1 ,
(3)
:} 3
Two 74LS283 4-bit paral lel adders arc used to implemenl the 8-bit adde r. TIle on ly connection bc!ween the two 74LS283s is the cany output (pi n 9) of Ihe low-order adder to the can·y input (pin 7) or the high-order adder. as s hown in Figure 6-- 13. Pin 7 of the low-order adder is grounded (no carry input). '111e sum of the Iwo 8-bit numbers is
A
4
r
(6)
U
(15) ( II )
{'
:
4
(2)
1< , 1< , 1<,
,
~
(' ) (13) ( 10)
UI<
r, , r, >': ,
"
r,
". R, II,.
117 (I
(14) ( 12)
(9)
C,
Co Low-ordcr a
DA
(4)
(6)
<{:
(2)
4
(15) ( 11)
1<.
(7)
"
(4)
A, A. A,
('l (3)
3
DB
(
( to)
(9)
(7)
C,
C.
<,r,,
r
" r,
High-ordcr adder
FIGURE 1\-1)
Two 74L5283 adder! connected al an a-bit parallel adder (pin numberl are in parenthesc!).
Related Problem
Usc 74LS283 adders to implement a 12-bi. parallel adder.
An Application An exmnplc of fu ll-adde r and parallel adder application is a simple vOling system thai can be used to si mul lancollsly provide [he number of "ycs" votes and the Iluml:er of "no" \"Otes. This type of syslem can be uscu whe re a group of people are assembled and there is a need for immediately dctermining opinions (for or against), making decisions, or voting on ccrtain issues or other matters.
PARALLEL BI NARY ADDE RS
•
In its simplest form, the system includes a switch for "yes" or " no" seleclion at each posidon in the a<;scmbly and a dig ital display for tile numbcrof yes votes and one for the number of fl O votes. The basic system is shown in Figure 6-- 14 for a 6-position setup, but it can be expanded to any number of positions with additional 6-position modules and additional parallel adder Hnd display circu its. In Figllre 6-- 14 each full-adder can proou<..'C the sum of up to three voles. The sum and oul pul carry o f each full -adder [hell goes to the two lower-order inputs of a paralle l bi Ilary adde r. The twO higher-o rder inputs o f the parallel adder arc connected to ground (0) bccausl: there is never a l:HSe where Ihe binary input exceeds 00 11 (decimal 3). For this
Six· Position Adder Module
,
I .OkD
L
0-- A
YF~ 0
X B
c
NO
~
i--J
C.
YES Fu ll·adder t
.r-
,
NO A
YES
tt-
X
,---""
r<>-
NO
/I
c~f-
e,n
BCD 7·St:gment
J
"'-.-
*
II U
c,
t- c, YES
'"
xU
ill<
I'nrnllcl atltlcr I
""
Full-adOcr 2
YES
YES
i}A
lo~ il
NO
L
YES
L
A
r /I
NO 0--. -C
r-
ein
C;.. f-I
r-
t-
YES
Full·adder 3
NO Swi tch
~
Ar
tt-
X /I C OOl
C," Full -a<.Ider 4
I--
l xU :} )
BCD <0
I- -
B
4
c,
t- c, ~
NU
Pafllllci !\dOcr 2
NO IogLC R c~i",ors ~hou l d
be conncctcc.l from Lhe Inputs
to ground.
FIGURE 6 - 14
A voting I)'Jtem using fu ll -adderl a nd para llel binary a dder...
of~
full-addcn.
J
7-seg""' '' l
c.lcoodcr
II U
307
308
_
FUNCTIONS OF COMBINATIONAL LOGIC
basic 6-pusition system, the out puts of the parallel adder go to a BC D-to-7-segment decoder that dri vcs the 7-scgmcnl d isplay. As mc ntioned. additional circu its must be included when the system is expanded. The resistors from the inputs of each full-addcr to ground assure that cach inpul is LOW when the switch is in the neutral posi tion (CMOS logic is used). Whcn a switch is moved to the "yes" or to the "no" posi tion. a HIGH lcvel (Ved is applied 10 the associated fu ll-adde r input.
I
---,
SECTION 6 - 2 REVIEW
1. Two 4-bit nu mben (1101 and lOT 1) are applied to a 4- bit ~ralleJ adder. The inputJ carry i~ 1. Oetermine the sum (L) and the output cany. 2. How many 74LS283 adden \.VOuld be required t o add two binary numberJ each representing decimal numben up through l000 ul
6-3
RIPPLE CARRY VERSUS LOOK-AHEAD CARRY ADDERS As mentioned in the laSt section. parallel adders can be placed into two categorics based on the way in wh ich internal carries fmm stage 10 st.age arc handled. Thosc calcgoric~
The Ripple Carry Adder A ripple carry adder is one in which thecaIT)' outp ut of each full -adder is connected 10 the c.'lny input of the next higher-order stage (a stage is one fu ll-adder). The sum and the output carry of any stage cannot be produced unti l tIle input cuny occurs; this causes a lime delay ill the addition process, as illustrated in Figure 6- 15. The carry propagation delay for each fu ll-adder is the lime fTOm the application oft.he input CillT)' until the OUlput curry occurs, assuming thaI the A and B inpu ts arc already present.
o
FIGURE 6 - 15
o
u
A 4- bit p;,,.., lJe l ripple ca rry adder
showing ' worst-case" cany
r:---7.-::'1 '-:
prop;,gotion dcloy..
A
I , MS B FA4
._
•• "
C~ tI , -. '
.•.
H" C;.,
FA]
8 ,, - -+ - - 8 n~
•'- .....
-
..tI FA2
'_. - .... -
" ,
LSB
FAI
--+- - 11 n~ ---r-- 8",
1--- -- ----- ---- .nn~-- -------- _
RIPPLE CARRY VERSUS LOOK-AHEAD CARRY ADDERS
•
309
Full -adder 1 (FA I) cannot produce a potential output carry until an input carry is applied. Full-adder:! (FA2) Cannot produce a potentia l output carl)' umil full -adder I produces an output carry. Full -adder 3 (FA3) cannot produce a potential OUlput carry until an output cany is produced by FAI followed by an OUlpul carry from FA2, and so on. As you can see ill Figure 6--- 15, the input carry to the least significant stage ha<; to ripple through a ll the adders before a linal sum is produced. The cumulative delay through all the adder stages is a "worst-case" addition ti me. The lolal delay can vary, depending o n the carry bit produced by each ful l-adde r. If two numbers arc added such that no cam !:'s (0) occur between stages. the addition ti mc is simply the propagation time through a single full-adder frolll the application of the data bits on the inputs to the occurrence of a sum output.
The look-Ahead Carry Adder The speed with which an additio n can bc performcd is limitcd by the timc required for the carries to propagate, or ri pple, through all the stagcs of a pamllel adder. One method of speeding up the addition process by el iminating Ihis ripple carry dclay is called looklIhead carry addition. The look-ahead carry adde r anticipates the output carry of each stage, and based on the inputs. produces the output carry by either carry gencration orcarry propagation. Glrr)' g~Jlerution occurs when an output carry is produced (generated) internally by the full -adder. A cany is genemted only when both inpllt bits arc Is. The genemted carry. CIf' is expressed as the AND funct ion of the two input bils. A and B. Equation 6-5
Cg = AB
Cur ry propagation occurs when the input carry is rippled to becomc Ihe output carry. An input carry may be propagated by the full -adder when e ither or both of the input bits are Is. The propagated carry. e", is expressed a~ the OR ftlnc tion of the input bits. Equation 6-6
CI'= A+B
The conditions for carry generation and carry propugmion arc iIIustmted in Figure 6- 16. The three arrowheads symboli7.c ri pple (propagation).
u
II
II
FIGURE 6 - 16
IIIUltr.ltion of condition1 for carry gcncra b'on and carry pro paga tio n. A
JJ C,n
A
• ••
(~
Generall'd tun),
IJ Con 1:
Propllgaled carr}'1 Gcnl11l100 l'urry
A
8 Cin
• •• t
C~
Pll)p~guled
co",
TIle output carry of a full-adder can be expressed in terms of both the genemted CaJTY ( CF )
+ CI'Cin
Equation 6-7
310
•
FUNCTIONS OF COMBINATIONAL LOGIC
Now let's see how lhis concept can be applied to a paraJlcl auder, whose individual stages are shown in Figure 6-17 for a 4-bit example. For each full-adder, the outpu t carry is depe ndent on the generated carry (C, ), the propagated cany (Cp )' and its input Cliny (Cin) . T he CK and Cp functions for cach stage arc immcdialely available as soon as the input bits A and B and the input carry to the LSB adder are applied because they arc dependent only on I he.~e biK The input cany 10 each stage is the output carry of lhe previous stage.
FIGURE 6 - 11
A~
II~
A
"
A, 6,
Ca rry generation and Cilrry propagation in terml of the input bib to a 4-bit adder.
C,,~
FA4 C~
A~
II.
A
"
C;..~
C; .. ,
H C in
A
C;n
,
,
FAJ C~
C_,
C_,
FA2
COl"
('-
C in
FAt
,
C~
,
C_,
!
l'ull -adder 4
Fu tl-adder 3
Full-adder 2
Futt-lI<.k!er t
C,.", A 4H4 Cp4 = A4 +B4
C,) =, A311.1 Cp3 = A J +B3
C, 2 = A 28 2 C,>2", A2 +112
Cp1 = A ( +BI
C~ I = A I IiI
Based on L11is amllysis, we can now develop expressions for tile output carry, C.,..., of each full-adder stage for tile 4-bil example.
Full-udder l: COUll = C.~ I
+ C"I C;nl
Full-adder 2: Cin2 = COIJII C""'l = C,Il + Cp2C in2 = Cg2 + CplC...... = CK2 = C II2 I- Cp1Cgj + C pZ C p lCinl
+ CpZ(Cg1 +
C p jC;nl)
Full-adder 3 :
CinJ = Co,,,2 C",otJ = CK3 + Cp)C;nl = C83 + C,>lC_ 1 = Cg3 + C,>1(Cs2 + C,,2C81 + Cp2CplCinl) = CgJ
+ C,>lC82 + CplCp2CgI + Cp3CplC,>jC,nl
Full-adder 4:
C,n-I = COI.l3 COIJ14 = CS 4 + C,>4Cin4 = Cg4 + Cp 4 C"'"3 = C84 + Cp4(Cg3 + C"JCg2 + Cp3C,,2CCI + CpJCp2CplCinl) = CR4 + C/>4C!!'l + Cp4C,,3C,2 + C,..lCpJ Cp2 C, 1 + Cp-lC"3Cp2 C,,IC;nl Nolice that in each ofth e.~c expressions, the outpUl cany Cor each full -adder stage is dependent only oll lhc initial input carry (Ci n,), the C , and C " functions of thai stage. and the Cs and CI' func tions of the preceding stages. Si nce each of the CI( and Cp functions can be expressed in lerms of lhc A and B inputs 10 the fu ll-adders. alJthe OUlput call"ies arc immediately available (except for gate delays), and you do not have to wait for a cany 10 li ppJe through all the slages before a final result is lIchie\'ed. 'nms, the look-ahead eany technique speeds up the addition process.
COM PA RATORS
•
311
T he COllI equations arc implemented with logic gate...; and connected to the full -adders to create a 4-bit look-ahead earry adder, as shown in Figure 6-18. ,_
IS .
' -n 'ret
'n 'ret
,- ,
'n ,- , ,
rr
n rG
'c.
iC1 ~
-
'-cr: ,- , , r '~ , , fa
' -(L
,c.
,c.
'n
~
c.
~
-r1 '---t"
, FIGURE 6 - 18
"
l ogi( diagram fOf" a 4-'ltagr: look-al'w ad .:arry adder.
Combination look-Ahead and Ripple Carry Adders The 74LS283 4-bil adder Ihm was introduced in Section 6-2 is a look-ahead cany adder. When these adders are cascaded to expand their capabili ty to handle binary nu mbers w ith more thun four bits, the output carry of one udder is connected \0 the input carry of the next . 111is creates a ripple carry condition between the 4-bit adders so that when two or more 74LS283s arc cascaded. the resulting adder is actually acombination look-ahead and ripple carry adder. The look-~,h ead carry opcnuion is internal to each MSI adder and the ri pple carry feature comes into play when there is a carry out of one of the adders to the next one.
1. The input bits to a fu ll-adder are A = T
6- 4
COMPARATORS
The basic function of a comparator is to compare the magnitudes of twO binary quantities to determine the relationship of those quantities. In its simplest form. a comparator cireuit determines whether two num bers arc equal. Aftercomplcting this seclion, you should be able to • Use the exclusive-OR gate as a basic comparator • Analyze the internal logic of a magnitude comparator thai has both equality and inequality outputs . Apply the 74HC85 comparator to compare the magnitudes Ofl wo 4-bit numbers . Cascade 74HC85s to expand a comparator to e ight or more bits
c.
312
•
FUNCTIONS OF COMBIN ATIONAL lOGI C
Equality As you learned in Chapler 3, tht! cxclusivc-OR g
"=D"
~
O l1lC inpUi bill; are equal.
',' ~ ' ~
'1l1c input
bil~
=D-
I TIle input bils arc nO( UjUlll.
are not equal.
FIGU RE 6 -19
B'lIic comparator operation,
In order to compare binary numbers conlaining IWO bils each, an additional exdusiveOR gate is necessary. 111e two least significant bits (LSBs) o f the IWO numbers lire compared by gale G" and the two mosl significant bits (MSBs) are compared by gale G~, as shown in Figure 6-20. If the two numbers are equal, their corresponding bits are Ihe same. and the oUlput of each exclusive-OR gale is II O. If the corrcslXlTlding sets of bits are not equal. a I occurs on thut exclusive-OR gate outpul. FIGURE 6 - 20
logic diagrDm for equillity com~riJ.On
LS Ih
H _ "--'-/
t =fI
of two 2-bit numbcfl.
H IGtl i,ttli.:.u,,~ ftju.i!it} .
Open file F06--20 to verify operiltion.
MSth Gcocl"".11 rnmrul : Simi!)· number ,\ --)0 AI-tn 8mmy numi"er 11--. II,Hu
A comparator detellTline if two binilry numbers ilre equal or unequal.
I
In order to pnxlucc a single outp ut indicating an equality or inequality of two numbers. two inverters and a.n AND gate can be used, a1> shown in Figure 6-20. The output of eaeh exc\u1>ive-OR gate is inven C
EXAMPLE 6-5
Apply each of the following sets of binary numbers 10 the comparator inputs in Figure
6-2 1, and determine the output by rollowing the logic levels through Ihe circuit . (a)
10 and \0
(b) rl and lO
COMPARAT ORS
•
3 13
III = I - --", --
III = 1
- -hL./P-- ( b)
la) A FIGURE 6-Z1
Solution
(~)
TIle output is 1 for inputs 10 and 10. as shown in Figure 6-2 I(a).
(b) The output is 0 for inputs I I and 10, as shown in Figure 6-2 1(b).
Related Problem
Repeat the process for bi nary inputs of 0 1 and 10.
As yo u know from Chapter 3. the ba"ic comparator can Ix: expanded to any number of bils. The AND gate set" the condition that all corresponding bits of the two numlx:rs must be equal if the two nu mbers themselves arc equal.
Inequality
Ib.~~" ,'" central procening
In addition to the equality output. many IC comparators provide additional outpul$ lhat indicate which of the two binary numbers being compared is the larger. Thai is, there is an output that indicates when number 11 is gremcr than number B (11 > B) and an output that indicates when number 11 is less than number 8 (11 < 8), as shown in the logic symbol for a 4-bit comparator in Figure 6-22. COMP ~,
A, A, A,
'" 1<,
H,
H,
} }
FI GURE 6 - ZZ
logic symbol for a 4-bit comparatOr' with inequa lity indica tion. II > IJ
11 = 8
A
To delemUne an inequality of binary numbers II and B. you fi rst examine the highcstorder bil in eaeh number. T he following condit ions are possible:
t. Jr Aj = I and 8 3 = 0, number 11 is greater than number B. 2. If 113 = 0 and B3 = I. number A is less than number B. 3. If Al = 8 3• then you must exami ne the next lower bit position for all inequali ty. These three operations Me valid for eaeh bit Ix>silion ill the numbers. 'Ine gcnernl procedure used in a comparator is 10 check for an inequality in a bit position, starti ng with the
(CPU) ilnd U,e slower main
I"'~,o"'. The CPU requests data out its addreH (unique in memory. Part of this . called ... tag. The tag
'h.
the CPU with the tilg the cache directory. If the the add ressed data is . the cache and is [fthe tags the dilta must be from the main memory il much dower rilte.
3 14
•
FUNCTIONS OF COMBINATI ONAL l OGIC
highest-order bits (MSBs). When such an ineq uality is found, the relationship o f the two numbers is establ ished, and any other inequalities in lower-oroer bit positions must be ignored because it is possiblc fo r an OPIX)site indication to occur: the highesl-o lder i"dico lioll IJIllsl 1ake precedellce.
Dclen ninc Ihe A = n, A > n, ano A < B outputs for the input numbers shown on the comparator in Figure 6-23. FIGURE 6-Z1
COMP
o
"3 }A
o
A >R 1\ ; 8
~
_
_
}
A< 8
Solution
The nu mber on the A inputs is OlIO and the number on the B inputs is 00 11. The A >B output is HICH and the other outputs ure LOW.
Related Problem
What arc the compamtor outpu ts when A:0:0lAO= 100 1 and 11:JJ2BlBo = 1010?
THE 74HC85 4-BIT MAGNITUDE COMPARATOR The 74HC85 is a comparator thai is B. These inputs al10w se\'cral comparators In be cascaded for comparison of any number of bits greater than four. To expand the compa.rator, the A < B,
... FIGURE 6 - Z4 ( IO)
Pin diilgrilm i1nd logic I)'fTlbol for the 74HC85 4- bit magnitude comparator (pin numben are in
(1 2)
(1 3) ( IS)
parcnthc1e).
(4) A > H.,
Ca~adilli! { mpu l,
A > 13"",
(3)
(2)
(9) A = H"",
(II }
( 14) (I)
(b)
~ic ~ym bol
COM!'
} Ae R
A >B 1\ ; 13
A
A < /J
A > 11
}
(5) (6)
(7)
Voc (l 6), G!'\D(8)
COMPARATORS
•
315
IL = n. and A > B output!'> of the lower-order comparator are connected to the corresponding cascading inputs o f the next higher-order comparalor. The lowcst-order coml).'U"ator nUl.~ t have a HIGH oll IJ1C IL = B input and LOWs o nlhe IL < Band IL > B inputs, This device may be availab le in other CMOS or TTL families. Check the 'Ihas instrumelllS website at www.ti.com ortlle1'1 CD-ROM accompanying this book.
I
EXAMPLE 6-7
Usc 74HC85 compamtors to compare the magnitudes of two 8-bit numbers. Show the r.:;omparators with proper interconncctions. Solution
FIGURE 6 -2 5
Two 74HC85s are requ ired to compare two 8-billlumbers. 'n ley arc connected as shown in Figure 6- 25 in a cascadcd aJTangemclll. [ SB,
MS fh
An 8- bit magnitude comparator
ming two 74HC851.
JO'' '
LI
, -
8, I< I< ,~
Related Problem
I
SECTION 6 -4 REVIEW
,,,-
A >B A >II A : IJ A= H A
}
H
' -
74HC85
IP
:F
-
A> B A >H A = 8 A =B A
II~ -
1< fI, _ 1< -
]. 74HCSS
Expand the circuit in Fi gure 6-25 to a 16-bil comparator.
1. The binary numbers A = 1011 and B = 1010 are applied to the inputs ofa 74HC85. Determine the outputs.
Z. The binary numbers A -= 11001011 and B = 11 010100 are applied to the 8-bit comparator in Figure 6-25. Determine the states of output pins 5, 6, and 7 on each 74HC85.
~ANDS
IN
Most CMOS devices contain protection circuitry to guard against damage from high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltages higher than maximum rated voltages. For proper oper<'ltion, input and output voltages should be between ground <'Ind Vee. Also, remember that unused inputs must always be connected to an appropriate logic level (ground or Vc:J. Unused outputs may be left open.
,
-
3 16
_
f U NCTI ONS Of COMB INATIONAL l OGIC
6-5
DECODERS A decoder is a digital circuit that dete<:ts the pre:;ence of a .~pecified combination orbits (code) 011 its inputs and indicates the presence ortha! code by a sJX:cified Olltput level. In its general form, a decoder has II input lines to handle n bi t~ and from one to 2n output lines to indicate the presencc of one or more n-bit combinations. In this scction, scvcrnl decodcrs are inlrOOuced. The basic principles can be extended to other types or decoders. After completing this section. you should be able 10 - [)cfine decoder - Design a logic circuit to decode any combi nation of bil~ _ Describe the 74HC 154 binary-to-dccimal decoder _ Expand de<:oders to accomnlcx.k,te larger Ilumbers of bits in a code - IA~ribc the 741..S47 BC])-to-7-scgment decoder _ Discuss zero suppression in 7-segment displays - Apply decoders to specific applications
The Basic Binary Decoder An imtruction
:,,~:::~~
wha t operation to perform. Instruction, are in machine code ( 11 and 01) and, in orde r for the computer to c.nry out an instruction, the instruction mUlt be decoded. Instruction decoding i, one of the steps in instruction I pipelining, whiCh are as follOWlO; Instruction is read from the memory (instruction fetch), instruction il de.:::oded, operand(l) il (are) read from memory (operand fetch), instruction is executed, and resu lt i. written b ..ck to memory. &siCillly. pipellning all~ the next imtruction to begin procesling before the current one is completed.
Suppose you need todetenninc when 11 bi nary 1001 occurs on the inputs cTa digi tal ci rcuit. An M 'D gatc can be uscd a~ the ba<;ic decoding e lemcnt because it pruduces a H IGH output only when a ll of its inputs are HIGI-I. TIlere fore. you must make sure that all of the inputs to the AND gate are H IGH when the binary number 1001 occurs; this can be done by invcrting the twO middle bits (the Os). as shown in Figure 6-26. fI_,\ B)
", 0
--, 0
A, - - X = A \A1A ,A ..
A,
",
It-ISB)
(oJ
(bJ
FIGUR E t. - 2 6
Decoding logic for the binary code 1001 with an active-HIGH output.
The logic equation for the dL"'COde r of Figure 6 - 26(a) is dcvclopt.'{] lIS il lustrated in Figure 6-26(b). You should veriFy that the output is 0 except when Ao = I, AI = 0, A 2 = 0, and A3 = I arc applicd to the inputs. Ao is the LSB and A3 is the MSB. In the represento./ion 0/0. bino.r.y nllmber or other weigh/ell COlle in this book, the LSn is Ihe righI-most bit in 0. horizontal armngemenl and the IOfJmo.~1 hit in a vcr/ieal armllgement, IInless .~pecified othenvi~·c.
If a NAND gate is used in place o r the AND gate in Figure 6-26, a LOW output will indicate the presence of the proper binary code, which is 100 1 in th is casc.
i
EXAMPLE 6-8 Detennine tIle logic required to decode the binary number 10 11 by producing a !-UGH level on the output. Solution
The decoding fu nction can be fonned by complement ing only the variables that appear as 0 in the desired binary number, as fo llows:
(10 11)
DECOD ERS
•
3 17
This function can be implemellted by connecting the true (uncomplcmcntcd) \'nriables Ao. AI, and A} directly to the inputs of an AND gate, and inverting the variable A2 before applying it to the AN]) gate input. TIle decoding logic is showl1 in Figure 6-27. FIGU RE 6-27
,'. - - - - ,
Decoding rogic for producing a HIGH output when 1011 is Ofl th e inputs.
A, ---~-\ A, - - - --'
Related Problem
Develop the logic req uired to detect the bi nary code 100 I0 and produce an activeLOW output.
The 4-Bit Decoder In order to decode illl possible combinations o f fou r bits. sixtccn decoding gates arc required (2 4 = 16). TIlis type of decoder is commonly called either a 4-line-ru- J6-1ille decoder because there are four inputs and sixtccn outputs or a l -of- /6 (Jecocfer hecause for any given code o n the inputs, one of the sixteen outputs is activated. A li st of the sixtccn binary codes and thei r corresponding decoding fu nctions is given in Table 6-4. If an active-LOW output is required for each decoded number, the entire decoder can be implemented with NAND gales and invert.en;. In order 10 decode each of the sixteen binary codes, sixteen NAND gates are required lAND gates can be used to produce active-HIGH outputs).
TABLE 6 - 4
Decoding functions and truth table (0( a 4- line-to-l 6-line ( 1-cl-16) decode< with active-LOW outpub. DECIMAL DIGIT
0
BtNARY INPUTS A]
0
0
0
0
110:01110
0
0
0
1
.4:0:011111
0
11y1:i\II111
2
0
0
0
0
,
0
0
0
0
6
0
7
0
4
8
0
AY\~ll1o
AY\0~ o
A:0:i\II111 A:0:01"0
0 0
10
U
11
0
0
0
A0:zAl l1o 110 ;;\JAn
0 U
A0:zJ\ JAo Ay1~IAu
12
0
13
0
15
- ---
A0t\l l1 o
0
9
14
FUNCTION
AI
3
Ao
I DECODING
Az
0
AY\0 1 ~
0
AY\:i\IAo
AY\~IAn AY\~ll1o
0
1
2
0
1
3
4
S
6
OUTPUTS 7 8 9 10
II
12
13
14
lS
0 0
0 0
0
1
0
1 0
0
0 0
0 0 0 0
0
J 18
•
FUNCTIONS OF COMBINATIONAL lOGIC
A logic symbol for a 4- li ne~to- I 6- l i ne (l -of~ 1 6) decoder with active-LOW outputs is shown in Figure 6-28. The BIN/DEC label indicates that a binary input makes the corre~ spo nding decimal output activc. Thc input labels 8, 4, 2, and I represent the bimuy weigill.<; of the input bits (2~ 1i2'1. FIGURE 6 - 28
BINtDEC
o
l ogic symbol for iI 4-line-to- l 6-line ( l -of- 16) decoder. Open file F06-28 to verify oper" tion.
I
2 3
, 4
6 -- 2
7
4
,
8
, 10
"12 13 14
" THE 7 4HC 154 1-0f-16 DECODER The 74HC I54 is a good example of iln Ie dl:uxlcr. The lo~ ic symbol is shown in Figure 6-29. TIlere is an enable function (EN) provided on this device, which is implemented with a NOR £alC used a.'\ a negative~AN D. A LOW level on each chip select input, CS I and CS2, is required ill o rder 10 make the enable gate output (EN) HJGH. The enable gale output is
FIGURE 6 - 29
XIY
Pin diagram and logic symbol for the
0
II) (2)
74HC154 1 -of~ 16decoder.
2
3
, 4
YO Yl
Vcr AO
Y2
AI
(23 )
" 'I (22) I, A.
(2 1)
'" ,
(20)
I
6 7
2
,
4
8
Y3
A2
Y4
AJ
Y>
CS2
10
Y6
CS!
Y7 Y,
YI5
"12
YI4
13
R
14
YI3 ( 18)
YIO
GND {oJ Pill dillgram
(\1
YII
C\~
&
(19)
(b) Logic sYlllhol
"
EN
(3) (4)
(5) (6) (7) (8) (9)
( 10) (11) (l3)
(14) (I ~)
(16)
(17 )
DECOD ERS
•
319
connected toan input of eflch NAND gate in thedecooer, so it must be H.IGI-J for the NAND gates 10 be enabled. If the enable gate is not activated by a LOW on both inputs, then all sixteen decoder outputs (Y) win be HIGH regard less of the slales of the four input variables, Ao. AI> A 2 , and A). l11is device may be available in other CMOS orITL famil ies. Chl.:ck the Tcxas Instruments website at www.t i.comor theTJ CD-ROM accompanying this book.
I
EXAMPLE 6 - 9 A certain applicalion requires that a 5-bit number be decoded. Use 74HCI54 dccO
Solution
Since the 74HCI 54 can handle on ly four bits, two decoders mus.!..!>c usc~ decode fi ve bits. The E ft h bit, A 4 , is connected to the chip select inputs, CS1 and CS2• of One dccooer, and AJ is connected 10 the CS 1and CS2 inputs of the other deeooer, as shown in Figure 6-30. When the decimal number is 15 or less, A4 = 0, the low·order decoder is enablcd, and the high-o r~er decoder is disabled. When the decimal number is greater than J 5, A4 = I so A4 = 0, the high-order decoder is enabled. and the loworder decoder is disabk'(l.
FIGURE 6 - 30
A 5-bit decoder using 74HC154s. BlNfDEC
BINmEC
llil!h ·order
l..ow·onlt....
OP-1P-2P--
Op-- 0
1P-- I
2 p--- 2 3 p-- 3
,
' p-' p--
I 2
7P-- 7 gP-- g
,
,
'=' CS.
f& I'J'J
12 13
CS A,
r-'
74HC J54
Related Problem
" " " " p-p-- " 14 p-" " I>-~,
II p-- II 12 p- I ~
CS,
"
20
oP-7P-- 1J ' P-' P-to P-II P-- 27
,
9 p-- 9 to P-- IO
13 "14 p-p-- 14 " p-- "
17
3p-- 19
4p-- , ' p-- , Op-- 0
I 2
16
CS~
f&
EN
29
Jl
74HC t54
Determine the output in Figure 6-30 thm is activatcd for the binary inpul 10110.
An Application Decoders are used in many types of applicalion.~. One example is in computers for input/output scll..'c tion as depicted in the general diagl1llll o f Figure 6-31. ComputerS must communicate with a variety of extemal devices called peripherfl/.~· by sendi ng and/or receiving data th rough what is know n as input/out put (110) pol1s. These
32 0
•
FU NCTIONS OF COMB INATI ONAL l OGIC
InputlOulpul
FIGUR E 6 - 3 1
""~
A simplified computer I/O port
!)1tcm with a port "ddrcSi decoder with only rou r ",ddrclI lines ihown.
COlllroiler &
Pri mer IfO
Data bus
pro=o<
EN Kcyboanl
I/O
EN MorJilor
BINIDEC 0
110
I
EN
2
3
,
l\lodcm
4
~ 110 "'" ~ ,llIdrcss ~ ~
IKl !'i.-quest
~
VO
6 7 >- .
I 2
, ;:
, 4
9
10
;:
EN
nlCSC 1Iala l inc~all: el\ her
" >-
unu....'
J3
pOl" ....
"14 >->-
'"&
EN
15 >- .
Pon address decoder
Scanner
110
EN ExL disk
IfO
EN Mi sc.
I/O
EN
,
external devices includc printers, modcms, scanners, extemal disk drives, kcyboard. video mon itors, and othercomputcrs. As inJicalcd in Figure 6-3 1, a decoder i ~ used 10 seleci the 110 port a" determined by Ihe computer so that da ta can be sent or received from a specific cxternal device. Each I/O port has a number, called an address, which uniquely identifies it When thc computer wants to communicate with a particular device, it issues the appropri ate address codc for lhe 110 pori to which that particular device is connected. This binary port address is decoded and Ihe appropriate decoder output is aClivmed 10 enable Ihe I/O port, As shown in Figure 6-3 1, binary data are transfcrred wilhin Ihe computcron a ditla bus, which is a SCI of parallel lines. For example, an 8-bit bm con si ~ts of eight parallcllines thai can carry one byte of dala 111 a lime. The data bus goe~ to all of the 110 ports, bu t any data comi ng in or going out wi ll only pass through the pol1 that is enabled by the pon addre~~ decoder.
The BCO-to-Decimal Decoder The BCD-ta-decimal decode r convel1S each BCD code (842 1 codeJ inlo one of ten possible decimal digit indications. II is frequcntly referred as a 4-/ille-to-/O·/il/e decoder or a /-0/-/0 (fecoder. The method of implementation is the same a" for the l-of- 16 decoder previously discussed, except thai only ten lleeuding gates are reqllired because the BCD code represent>; only the tCIl decimal digi t.~ 0 through 9. A list of Ihe ten BCD codes and their corresponding dccooi n£ ru n ct ion~ is given in Table 6-5. Each o f Ihe.se dccoding functions is implemented wilh NAND gates to provide aClive-LOW outputs. If an aclive-HIGH outpul is
DECODERS
•
TABLE 6-5
DECIMAL DIGIT
0
I
!
A)
BCD CODE Al A,
0
0
0
0
0
0
Ao
DECODING FUNCTION
0
A)AZAIAo A;4~,t\,
0
A:0:t\ IAo
I
I
Ay4Y\ IA u
0
0
0
Ayi\1AIAu
,
0
0
7
0
2
0
0
3
0
U
4 5
BCD de<:ooing ruoc Vons.
Ay'l2AIAu 0
0
Ayi\Y\ IAu Ay'lyl iAu
8
0
0
9
0
0
A01AIAu
0
A~ 2A IA u
required, AND gales are uscd for decoding. TIle logic is identical to that of the first ten decoding gates in the I-of- Io decoder (.~ce Table 6-4).
I
EXAMPLE 6 - 10
The 74HC42 is an integrated cin::uit BCO-to-dccimal decoder. T he logic symbol is shown in Figure 6-32. If the input waveforms in Figure 6-33(a) an:: appliecl lo the inputs of the 74 HC42. show the output wavefo rms.
BCD/DEC
( I)
0 I
( IS)
2 3
I
(1 4)
, ,,"
2
( 13)
,
( 12)
7
(3)
HtU
4
inpul'
_
E
-{-_
-{-_
(9)
0
(It)
2
"
, r 's ' ,
-:--_
L _:_ L
I L.
I
1
I , I
" " "
W
,
~~-+--+--+--+
6
--------~LJr~-:---~
7
LJ
_ , _ _ _ _ _---=w=;L.J 8
(b)
-:--_
"
~LJ~-T~~7--:---~
,m .• 1 4
tlUlpU",
"
-J~~~7--:---~'~-T~
3
-ll
'.
I
,,,
(7 )
The 74HC41 BCD-to-c!ecimal de<:ooer.
_
I
(1 0 )
"
I
(6)
74HC42
flC;'
"
AI A2
(S'
4
4
" "
A,
(2)
FIGURE 6- 33
321
322
•
FUNCTI ONS OF COMB INATIONAL l OGIC
Solution
Related Problem
The output waveforms arc shown in Figure 6--33(b) . As you can see. the inputs are sequenced through the BCD for digits 0 through 9. The output waveforms in the liming d iagram indicate that sequence on the decimal-value outpuls. Construct a timing diagmm showing input and outp ut waveforms for the case where the BCD inputs sequence through the decimal numbers as follows: D. 2. 4. 6, 8. 1. 3. 5. and 9.
The BCD-to-7-Segment Decoder The BCD-to-7-scgmem decoder accepts thc BCD codc on ils inpul<; and provides outputs to dri vc 7-segment di.<;play devices 10 produce 11 deci mal readout. The logic d iagmm for a basic 7-segment decoder is shown in Figure 6--34. .. FIGURE 6 - 34
logic symbol for a BCD-to7-segment decoder/driver with active-lOW outpub, Open file F06-34 to ve rify operation.
BCDn-scg
BCD 1Ll('ll1
r
"b
,
I
"f
2
tI~
4
A,
8
Output
lire,
conl'M;'O;I IO
d
7."','1:1110"01 di-;play lIc\'k.-e
,
,f
THE 74LS47 BCD-TO-7-SEGMENT DECODER/DRIVER The 74LS47 isan example of an IC device that decodes a BCD input and drives a 7-segment display. In add ition 10 its decoding and scgmem drive capability. the 74LS47 has scveral addi tional features as indicated by the LT, RBI. m j RBO functions in the logic symbol of Figure 6-35. As indicated by the bubbles on the logic symbol. all of the Ol1tputs (0 through ~) an: active-LOW as a rc the LT (lamp test), RBI (ripple blanking inplLt), and Bl / RBO (blanking input/ripple blanking outPllt) fmlCliOllS. The OlltputS can dri ve a com mo n-anode 7-segment display di rectly. Recall that 7-segmcnt displays were d iscussed in Chapter 4 . In addition to decoding a BCD input and producing the appropriate 7-segment outputs. the 74LS47 has lam p test and zero suppression capabil ity. This device may be available in other TIL or CMOS famil iei>. Check the Texas Instru mcnts we bsite at www.ti .com or thc T I CD-ROM accompanying Ihis 000k. FIGURE 6 - 3 5
Pin diag.-;,m and logic symbol for the 74LS47 BCD-to-7-segment decode'{driver.
I
{l6)
Vu;
BCDI7-scg
f
,
(7)
•
HeD
b
inPJ"
(I)
(2 )
(OJ (3)
d
,
I .T
R8/
(5)
( 13)
"
~}
b
,
d
,
,f
LT
RBI
1(8) GND
(al Pin d iagrdm
(4)
811N80
(b) Lngic sym tloJ
(12) ( 11) (10)
(9)
(15) (1 4)
Hilli80
DECODER.S
•
Lamp Test When a LOW is appl ied 10 tile LT input and the BI/ RBOis HIGH. all of the 7 segmenrs in the display are turned on. Lamp test is used to verify that no segments are burned out.
Zero suppression rcsulb in le
Zero Suppression Zero suppression is a feattu"e used for m uh idigil displays 10 blank out unnecessary l.eros. For example. in a 6-digit d isplay the number 6.4 may be displayed as 006.400 if the zeros arc not blanked out. Blanking the zeros at thc fron t of a number is called/cading zero slIppression and blanking the zeros al the bac k of the number is called /raiJing :cro ~·l!ppn~ssioll. Keep in mind that only nonessential zeros are blanked. With l..cm sUPPI"ession. the number 030.080 will be displayed as 30.08 (the essential zeros remain). Zero suppression in the 74LS47 is accomplished using the RBI and Blj REO functions. RBI is the ripple blanki ng inpl!!...?nd RBO is the ripple blanking output on the 74LS47; these are used for zero suppression. BI is the blanking input that shares the same pin with RBO; ill other words. the Blj RBOpin can be used asan input or an oulpul. Whcn used asa BI (blanking input). all segment outputs are HIGH (nonacti ve) when BI is LOW, which overrides all Olher inpms. The BI function is nOI pari of the zcro suppression capabi lity of the device. All ofthc segment outpulS o f the decoder are nonactive (HIGH) if a zero code «()()()() is on i l~ BCD input!\ and if its RBf is LOW. Th i .~ causcs the display to be blank and produces a LOW REO. 'I1le logic diusram in Figure 6-361.a) illustrates Jeadins zero suppression for a whole number. The highest-order digit positio n (left-most) is always blanked if a zero code is on
o0
"
o0
0 0
o0
n
0 0
display.
I 0 () 1
I I
RIIl II
74 LS47 tf
..
6
74LS47 "
ll
74LS47 d
DIJRf)()
~
6
u
IIIIRDO
d
-
Blanked
~
,-,-, -
-,-,
llI:mkL'tI
~.
6
0
I!lIR/JO
(a) II luM rn tioo of lcading zero suptlfcssion
o
IIII
o
~
o
t 0 I
"
~
4
~
"
74lS47 ~
f
.'
rl
,
b
,-
TTTTT •
=r
a
-. TTTTT -,, o
I
HIJRHO
,,
o f)
I 1 I
IIII
~
~
Z
74LS47
rl
..
b
a
HIffIIlO
,
,
/I
.
•
~
•
74LS47 d
•
b
4
!
I
.
74LS47
w
~=
~
,.,
"
fJIJRDO
L, TTTTT ~ TTTTT ~
dp
fb) llIustrntion of trailing
I'I'I'I ..G' "
IIII
o •• a
I
0 0
Bl anked ~cro suppre!'~ i()ll
fiGUR E 6 -3 6
E)c"mpJel of zero iupprOliQfl uling the 7q15q7 BCD to 7-segment decoderfd river.
323
324
•
FUNCTIO NS O F COMB INATI O NAL LOG IC
ils BC D inputs because the RBI of the most-significant decoder is made LOW by connecting iI to ground. The REO of each decoder is connected to the RBI of the next lowest-order decoder so that all zeros to the left of the first nonzero digit are blanked. For example. in pan la) of the figure the two highest-order di2its are zeros and thereFore are blan ked. Thc remai ning two digits. 3 and 9 are displayed. The logic diagram in Figure 6-36(b) illustratcs trailing zero suppression for a fract ional number. TIle Inwest-order digit (right-most) is always blanked if a zero code is on its BCD inputs becuuse the RBI is COllnected 10 gro llnd . The REO of ei\l·h decoJer is connected to the RBI of the next highest-order decoder so that all 7.eroS to the right of the fi rst nonzero digit are blanked. In part (b) of Ihe fi gure, the IWO lowcst-order digits are zeros and thereFore are blan ked. The remai ning IwO digits, 5 and 7 are di splayed. To combine both leading and Imilin!! zero suppression in one displuy and to have dccimal point capability, additional logic is required.
I
SECTION 6 5 REVIEW
1. A 3-line-to-8-line decoder Q n be used for octaHo-dedrll
2. How many 74HCT 54 l-of-16 decoders are necessary to decode a 6-bit binary number? 3. Wou ld you select a decoder/driver with active-HIGH or active-LOW outputs to drive a common-cathode 7-segment LED display?
6-6
ENCODERS An encoder is a combinatiollallogie circuit that essentially performs a '·reverse" decoder fUllc tion. An encoder acccpts an acti Ve! level on onc of its inputs representing a digit. such as II decimal or octal digit , and convens it 10 a coded output, sllc h a<; BCD or binaly. Encoders call also be devised 10 encode various symbols and alphabetic characters. The process of eonvel1ing from familiar symbols or nu mbers to a coded format is called ellcodillg. After completing this section, you should be able to • Detemline the 10f;ic for a decimal encoder . Expl
The Decimal-to-BCD Encoder ·ll1is type of encoder has len inputs-one for each decimal digit- and four OUlputs COrresponding to the BCD code. as shown in Figure 6-37. This is a ba<;ic I O-line-t0-4-line encooer. "The BCD (842 1) code is listed in Table 6-6. From this ta ble you can de termine the relationship bel ween each BCD bit and Ihc decimal digits in order to anal yze the logic. For instance, the most significant bit o f the BCD code, A) , is al ways a I for decimal digit 8 or 9. An OR ckpression for bit A) in tenns of the decimal digits can therefore be written as
ENCODERS
•
325
FI GURE 6 - 37
DEC/BCD
logic symbol for iJ decimal-to-BCD encoder.
0
2 3 ()e(oimaJ in put
4
2
S
4
6
8
} OCD ''''!PUI
7
8 9
• TABLE 6- 6
DECIMAL DIGIl
0
I
A)
BCD CODE Al AI
0
0
0
0
0
0
Aa
0
2
0
0
3
0
0
4
0
0
5
0
0
6
0
0
7
0
J
0
8
0
0
9
0
0
0
0
Bil A2 is always a I for decimal digil 4, 5, 6 or 7 and can be expressed as an OR function a" follows:
A2 = 4 + 5 + 6+7 Bi! AI is always a I for decimal d igit 2, 3, 6, or 7 and can be expressed as AI = 2
+3+6 + 7
Finally. Ao is always a I for decimal digit I. 3. 5, 7. or 9. TIle ex pression for Ao is
Ao = I + 3 + 5 + 7 + 9
enccder because it the mnemon ic with which a program and carri~ out the mnemonic to iJ machine
Now leI's implement the logic circuitry requi red for encoding each decimal digit 10 a BCD code by using Ihe log ic expressions just developed. It is simply a maucrofORing Ihe appropriate decimal d igit inpul lines 10 form each BCD output. The basic encoder logic resulting from these ex pressions is shown in Figure 6-38. FIGURE 6-18
Basic logic diagram o f.;) decimal-toBCD encoder. A O-digit input;1 not needed bealuse the BCD outputs are all lOW when there iJre no HIGH inputs.
(r>.ISB)
~;j:';,;:::,::~: (senel ofamh and
I underst and.
computeof mnemonic instructioru for .;) microproc~sorareADD, MOV (move daU), MUl (multiply), XOR, )MP (ju mp), and O UT (output to.;) port). ~mpfes
326
•
FUNCTIONS OF C OMBINATIONAL lOGIC
The basic operation of the circuil in Figure 6- 38 is as follows: Whe n a HIGH appears on one of the d(.'Cimal digit input lines. the appropriate levels occur on the four BCD output lines. For instance. if input line 9 is HIGH (a.<;slIming all other input lines an:: LOW). this condition will produce a HIGH on outputs Ao and A ~ and LOWs on outputs A! and A 2• which is the BCD cUlle (1 00 1) for (k'Cimal 9 . The Dec.imal-to-BCD Priority Enroder This type of encoder penonns the same ba.'>ic encoding function as previously discussed. A prim·ity encoder also offers additional flex ibility in that it can be usc."tI in applications that require priority detection. The priority function means that the encoder will produce a BCD output corresponding to the IIiglleslorder decimal digiT input that is acti ve and will ignore any other lower-order active inputs. For instance, if the 6 and the 3 inputs are both active, the BCD outpul is Oi l 0 (which represeniS deci mal 6).
THE 74HC147 DECIMAl-TO-BCD ENCODER The 74HCI47 is a priority encoder with acti ve-LOW inputs (0) for decimal digits I throug h 9 and active-LOW BCD outputs as indicat(.-d in the logic symbol in Figure 6-39. A BCD zero output is represented when none of the inpms is active. The device pin numbers arc in parent h(.'S(.'S. Th is device may be available in other CMOS orm.. families. Ch(.'Ck the Texas Instrumenl'> website at www.ti.oom or the TI CD-ROM accompanying this book.
FIGURE 6 - 39
I
Pin diagram and logic s}'Ulbol for the
(t6 )
7
'" 134 1)5
(12)
113 III
" 13 4
D8 A2
HI'RIII3C D
, I
3 4 5
I
2
4 S
I,
1
,,0 ,
" 7l
6
o-ili<-
(5)
9
1(8)
GN!) (II) I'm diagrnm
GND (b) Logic diagl1lm
THE 74LS148 8-lINE-TO-3-lINE ENCODER The 74LS 148 is a priority encoder that has eight active-LOW inpllls and three active-LOW binary oulputS. as shown in Figure 6-40. This device can be used for convertin£ octal inputs (recall thallhe octal digits are 0 through 7) to a 3-bit binaf)' code. To enable the device. (he £ 1 (enable input ) muSt he LOW. It also has (he EO (enable ourput) and GS output for expansion purposes. The £0 is LOW when the EI is LOW and none of the inputs CO through 7) ;s active. GS is LOW when EI is LOW and any of {he inputs is active. This device may be ilvHi lllblc in oth(.'T "ITL or CMOS farn iJi(.'S. C h(.'Ck the "Iexas Instruments website at WWW.li.COIll or lhe TI CD-ROM accompanying this book.
ENCODERS
logic 1}'ITlboi for the 74LS 148 8-linc-to-3- line encoder.
1( 16)
( 10) (J I) ( 12) (13) ( I) (2) (3)
(4)
HPRJ/BIN £0
EI
as
0
327
FIGURE 6 - 40
I'oc
(5)
•
,
I
2
2
3
4
( 15) ( 14) (9) (7) ]6)
4
5 6 7
1'8) a ND
The 74LS 148 can be expanded to a 16-linc-I0-4-linc encoder by connecting the EO o f the higher-ord<.'J" encoder to Ihe £1 of lhe lower-order encoder and ncgative-ORing Ihc corresponding bi nary outputs as shown in Figure 6--41. The EO is used as Ihe fourth and mosts ignificant bit. This particular configuralion produces active-HIGH o ut puts for the 4-bit binary number. 0 I 2
.~
4 5 (, 7
,, •, •, 741-" 148 , ,• '0
0
7
8
t:1
~
0
f;U
FIGURE 6 - 41
l) I0111213141~
, ,7 • ,•, " 74LS I48 , ,•
A 16-line-t0-4 ,jne encoder uling 74LS1481 and erlemal logic
~
lf LOW levels appcar on pins, t. 4, and 13 of lhc 74HC I47 shown in Figure 6--39. indicate the stale of the four outputs. All o ther inputs arc HIGH.
Solution
Related Problem
Pin 4 is the highcst-order (\<.'C ima l digil input having a LOW level and rep"CSe nts decimal 7. T herefore , the OlllpUllcvcls indicatc the BCD code for decimal 7 where /\0is the LSB and 1\J is the MSB. Output /\0 is LOW, AI is LOW, 1\2 is LOW, and A) is HIG H. What arc Ihe outputs of the 74HC I47 if all it ~ inputs arc LOW? Ifall its iJlputs arc J-nGH ?
328
•
FUNCTIONS OF COMBINATIONAL LOGI C
An Application A clas...;;!c application example is a keyboard encooer. The ten dL--cimal digits on the keyboard (If a computer, for example, must be encoocd for proces.<;ing by the logic circuitry. When onc of the keys is pressed , the decimal digit is encock-'d 10 thc conesponding BCD cooc. Figure 6-42 shows a simplc kcyboard cncoocr anangemcnt using a 74HCI47 priority cncodcr. Thcy kcys arc represcnted by ten push-bulton switches.. each with a pull-up resistor to + V. The pul l-llprcsistorcnsllres thal lhe line is HlG H when a kcy is nOI depressed. Whcn a key i~ depressed. the linc is connL"Ctcd to ground. and a LOW is applied to the come's ponding cncoder inpuL TIle zcro kcy is nol connccted bL-cause the BCD output represents zcro when none of the other kcys is depressL-'d. The BCD complcmcnt OUi pUI of thc encoder goes 11110 a storage device. and cach SllCcL>ssivc BCD code is stored ullIil the entire number has becn entcTL-'d. Mcthods of storing BCD numbers and binary data are COVCrL-'d in latcr chaptcrs. FIGURE 6 _ 42
+v
A simplified keybo;lrd encoder. H,
7
IH.
't
t,It
r-
H.
8
IR,
' IR,
R,
9t
HI'RUBCI)
I
,, , 2
R.
"t
~
6 7 8
,,I g::= A,~, 8
g::=
-
A,
}
Flel) ~"nrpkmcm
A,
9
74HC I47
R,
't 't
H,
All BCD(.'t)InptelllcnllillCl> ~re HIG H ind ic,uinl! a O.
i-JI-
r
I
SECTION 6-6 REVIEW
No t~lCOding rle(:essary.
1. Suppose the HIGH levels are applied to the 2 input and the 9 input of the circuit in Figure 6-38. (a) What are the states of the output lines?
(b) Does this represent a valid BCD code? (c) What is the restriction on the encoder logic in Figure 6-38? 2_ (a) What is the A02A1AOoutput when lOWs are applied to pins 1 and 5 of the 74HC 147 in Figure 6-39? (b) What does this output represent?
l
CODE CONVERTERS
6-7
•
329
CODE CONVERTERS
In this section, we will examine sollle methods of convert from olle code to another.
u.~ing
combinational logic circuil.~ 10
After completing this .'iCCtion, you should be able 10
• Explain the process for conven ing BCD to binary - Use exclusive-OR gates for conversions between binary and Gray codes
BCD-to-Binary Conversion One method of BCD-to-binary code conversion uses adder circuits. 1lle basic conversion proc'Css is as fo llows:
1. The value, or weight, of each bit in the BCD number is represented by a binary number.
2. All of the binary representations of the weights of bits that arc Is in the BCD number are added. 3. The result of this addition is the binary (:'Guivalcnl of the BCD number. A more concise statement of this operatioll is
The binary numbers I"Cpresenting the wcighl.. of the nCD bits arc summed to produce the tol....1 binary number. Let's examine an 8-bil BCD code (one Ihat rcpn."SCnls a 2-digil decimal number) Lo undel"stand the relationship belWl.."Cn BCD and binary. For instance, you already know that the decimal number 87 can be exprl..osscd in BCD as I(XX)
DIl l
~~
8
7
The len-lTlost 4-bit gmup represents 80, and the right-most 4-bit group represents 7. Thai is, the left-most group hasa weight of 10. and the rigbt-mostgmup has a weight of I. Within each grollp, the bi nary weight of each bit is as follows; Ten... Digit
80
Weight:
Bit designation:
B]
40 B2
Units Digit
20
10
BI
13,
The binary equivalent of each BCD bit is a binary number representing the weight of that bit wilhin Ihe lotal BCD number. This represen tation is given in Table 6-7. (MSS) BCD BIT
A, A, A, A,
BCD WEIGHT
2
64
BINARY REPRESENTATION 32 16 8 4 2
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
8
0
0
0
0
0
0
IJ.,
10
0
0
B,
20
0
0
8,
40
0
H,
SO
0 0
0
0
•
(LSB) 1
0 0 0
0
0
0 0
0
0
0
0
0
0
0
0
TABLE 6-7
Binary represcntiltioni of BCD bit wdghu.
330
•
FUNCTIONS OF COMBINATIONAL lOGIC
If the binary I"(:presentations for the weights o f all the Is in the nco number are added, the rcsull i .~ the binary number Ihat corrcsponds to the BCD number. Example 6-12 iIIustraics this.
Convert the BCD numbers 00100 111 (decima l 27) and 10011000 (decimal 98) to binary.
Solution
Write the binary represcntations o f the weights o f all Is appearing in the numbers, and then add them together.
80 0
40 20 0
10 8 4 2 0 0 1 I
1
~
()()()()(I() I
I
00000 10 0000 100
2 4 20
+ 0010100 0011011
80
40 20 0 0
Binary number for dt.'"Cima[ 27
10 8 4 2 I 0 0 0 '---~>
000 11lO()
8
'----------» 000 IU IU I U '---_ _ __ _ _ _ --> + 1010000 80 1100010 Related Problem
Binary number for decimal 98
Show the process of converting 0 I00000 I in BCD 10 binary.
With this basic procedure in mind. let's see how the process ean be implemented with logic circuits. Onee the binary representation [o r each I in the BCD number is determined. adder circuits can be used to add the Is in each column of the binmy representation. The Is occur in a given column on ly when the corresponding BCD bit is a I. Tile occurrence of a BCD I can therefore be used 10 generate the proper binmy I in the appropriate column of Ihe adder stmcture. To handle a two-decimal-d igit (two-decade) BCD code. eight BCD input lines and seven binary outputs arc I"cquired. (il tak<..>s seven bits to represent binary numbers throug h ninety-ni ne.)
Binary-to-Gray and Gray-to-Binary Conversion The ba"jc process for Gray-binary conversions was cowred in Chapter 2. Exclusive-OR gales can be used for Ihese conversions. Programmable logic dcv ices (PLDs) can also be programmed for these eode conversions. Figure 6-43 shows a 4-bit binary-to-Gray code converter. and Figure 6-44 illustrates a 4-bit Gray-to-binary t."Onvertcr. FIGURE 6-43 fo ur-bit billary-to-Gray c::onvenioll logic. Open file F06-43 to verify op
Bill;!n
B.
" " "
Grn}
C, tLSBI C, G,
G,
(MS B I
MULTIPLEXERS (DATA SELECTORS )
G"'~y G(\
Binar)' ,~~
~,
(LSBJ
FIGURE 6 - 44
FOtJr-bit Gray-to-bil"li'lry convcnion
logic. Open file F06-44 to vcrify opcr.ltion.
G,
B,
I
EXAMPLE 6-13
(3) Convert the binary Ilum ber 0101 to Gray code with exclusive-OR gates. (b) Convel1 the Gray code 101110 binary with excl usive-OR gates.
Solution
(a) 010 12 is 011 1 Gray. See Figure 6--45(a). (b) 10 11 Gray is 1101 2. See Figure 6--45(b). ... FIGURE 6 - 45 Om'lf}·
Gmy
o
u ~---o (b)
Related Problem
I
SECTION 6 - 7 REVIEW
How many cxclusive-OR gates arc rcqu ired to convCl1 8-bi! binary to Gray?
1. Convert the BCD number 10000101 to binary. 2. Draw the logic diagram for converting an 8-bit binary number to Gray code.
6-8
MULTIPLEXERS (DATA SELECTORS)
A multiplexer (MUX) is a device thaI allows digital information from several SIlUrces to be l"OutL"
•
331
332
•
FUNCTIONS OF COM BINATIONAL lOGIC
In a multiplexer, data goes from leverallines to one line.
A logic symbol for a 4-input multiplcxer (MUX) is shown in Figure 6--46. Notice that lhcre arc two data-sek'Cl lines becau.<;c wilh I wO select bits. any Olle of the four data-input lines can be sck-c((.>d.
fiGURE 6 - 46
MUX
:}
LogX: symbol fo r a l -of-4 oo ta lelectO<'I multip lexer.
n,
Om3 inplll\
r
o
01 - fJ, 2
\. fJ ,
Dala "Ulpul
3
In Figure 6--46. a 2-bit code on the data-selcct (5) inpu ts will a llow the data on thc scIcct(.-xl data inpllt to pass through 10 the dataoll tpllL If a binary 0 (SI = 0 and So = 0) is appli(.o(] to the data-seIL'Ct lines. thc data o n in put Do appear on the data-outp ut linc. If a binury I (S1 = 0 a nd So = I) is applied to the data-se k-'Ctli nes, the data on in pllt D, appear Oillhe data output. If a binary 2 (S, = I and So = 0) is applied, the data on D l appear Oil the o ulput . If a binary 3 (SI = I a nd S" = I) is a pplied. the data o n D) arc switched to the output line. A summary of this operation is given in Table 6-8.
TABL E 6 - 11
Data
~Icctioo
DATA-SELECT INPun Sl So
for a l -of-
4-multiplexcr.
o
INPUT SElECTED
o
Do
o
V, D,
o
D,
~
~ A bUJ is an intcrnal patnway alo ng
IIg.li!4Iiil@o!l
wtlkh clectrical signa l! arc ~nt from one part of a (;omputcr to anothe •. In (;ompute. networks, a Jlmred bw il one that il connected to aU the microproce",o n in the I~tcm in order to ex<:hangc data. A shared bus may (;ont ain memory and inpu tloutput devi(e< that can be I acce<~d by all the miooprocesson in the f)I'I tem. AC(C!I to the Ihared bul is contro lled by a bUl arbitcr (a multiplexer of sorts) that a(l~ o nly one miaoprocCSKl r at a time to uK: the s~tcm' •• harcd bus.
I
Now let's look at the logic circuitry r(.-q uired to perform this multiplexing operation. The data Olllput is e q ual to the statC of the .\'e1ecred data input. You can therefore. derive a logic exprcssiOfl for the output ill terms of the data input and the sck'Ct inp uts. T he data outpul is equal to Do o nly if S. = 0 and S" = 0: Y = DoSIStI' T he data output is eqllalto DI o nl y if SI = 0 und So = I : Y = D I5\So. TIle data output is equal to D~ only if SI = I and So = 0: Y "" D 2S ISO'
T he data output is equal to D l o nly if SI = 1 and So = I : Y = D 35 1So. When thesc terms are ORed. the total expression for the data output is
Y = D~,So + DISI So
+ D~rSo +
DJS1So
TIle implementatio n of this equation TL"Quires four 3-input AND gates, a 4-inpul O R gate, and t wo inveners 10 generate the complements of SI and S()o as show n in Figure 6-47. Bccau.<>C data can be sek c tcd from anyone of the inp ulli nes, this c ircu it is also refeH(.-'(j to as a data seledor.
MU LTI PLEXERS ( DATA SELECTORS )
FIGURE 6 - 47
~,
s..
•
l ogic d iagr
S,
I" D, y
D, f).1
I
EXAMPLE 6-14 The data-input and data-select waveforms in Figure 6-48(3) are applied 10 the muhiplcxcr in Figure 6--47. Dctcnninc the output w
FIGURE 6-48
n"'
,
f), I
:
0,
I
.I ""LJ
'----t--',
i---u
I
Lf:
D,
s.
I,'
Solution
S,
"
0
"
0
The binary SICi tC ofille dala-select inpu ts during each interval determines which data input is selected. Notice that the data-select inpu ts go through a repetitive binary sequence 00, 0 1, 10. 11.00.0 1, 10. 11. and so on. TIle resulting output waveform is
shown in Figure 6-48(b). Related Problem
Construct a timi ng diagram showing all inputs and the output jf the So and S, wavcfon ns in Figure 6-48 are illlcrchangt."{\.
THE 74HC157 QUAD 2-INPUT DATA SELECTOR/MULTIPLEXER The 74HC 157. as wel l as its LS version. consists of fou r separate 2-input multiplexers. Each of the fou r multiplexers shares a common data-select line and a common Enable. Because there arc only two inputs fo be selected in each multiplexer, a single da ta-select input is sufficient.
333
334
•
FU N CTI ONS OF COMB INATIONAL lOGIC
A LOW on the E/Jable input allows the sek'Cted input data to pa..s thro ugh to thc output. A HIGH on the Enoble input prevcnts data from going through to thc output; that i.~ . it di~ abIes the multiplexers. Thisdcvice may be available in other CMOS orl fL fami lies, Check the Texas In st nllnenl~ website at www.ti.comor the TT CD-ROM accompanying this bDok. Y
The pin diagram for the 74HC157 is shown in Figure 6-49(a). The ANSI/IEEE logic symbol for the 74HC I57 is shown in Figure 6-49(b). Notice that the four multiplexers :IfC indicated by the partitioned outli nc and that thc inputs common to all four mUltiplexers are indicuu_-'d as inputs to the notched block at the top, wh ich is called the commoll cOlllrol block Aillabcls within the upper MUX block apply to thc olher blocks below it.
The ANSI/IEEE Logic Symbol
FIGURE 6 - 49
Pin diagrilm ilnd logic Iymbol (or the 14HC 151 quadruple 2-input d.)u w:lcd.or/multiplcxer.
DATA SElECr [
Vee
IA
ENABLE
IR
4A 4'
2A
4Y
2.
3A
3. 3Y (a) Pin di~ram
Elklbi..
Dmd
( 15)
( I)
E.N
GI
...,!t:\:l
IA 18 :!A
28
(2)
3)
T
(5)
MUX
(4) (7)
(6)
~ (II) ),8 (10)
-IA ( 14) 46 (13)
"
(12
lY
" J),
4Y
(b) Logk symbol
Not ice the I and I labels in the MUX blocks and the G I labcl in Ihc com mon control block. Thcse labels arc an example of thc dependency nohliion system specified in the ANSI/IEEE Standard 9 1-1984. In this case G I in'-!!catcs an AND relationship between the daw-select input and the data inputs with I or I labels. (The I means Ihat thc AND relationship applics to the complemclll of the G I input.) In Dther words. when the datasekx:t input is HIGH, the /J inputs of the multiplexers arc sclectL-d; and when the dataselect input is LOW, the A inputs arc selected. A "G" is always used to denotc AND dependency. Other a.<;peCl<; of depcndency nolation arc introduced as appropriate throughout the book,
THE 74LS151 8-INPUT DATA SELECTOR/MULTIPLEXER The 74LS 15 1 has eighl data in puts (On- V 7) and. therefore, three data-select or address input lines (So-S"), Three bits are r(."'quirL"(ilO select anyone of thc eight data inputs (2 3 = 8). A LOW on the Elloble input allows the selec ted input data to pass through 10 the Olilpul. Notice that the data output and ils complement are both available. The pin diagram i ~ shown ill Figure 6-50(a), and the ANSUIEEE logic symbol is shown ill part (b). III this ca'\e there is no Ill:cd for a common cOllirul block on the logic symbol becausc there is only one nmltiplexer to be controlled, not four as in the 74HC 157. The G ~ label wi thi n the logic symbol indicateS the AND relationship between the data-select inputs and each of the data inputs 0 through 7. 'Inis device may Ix! available ill other 'ITL or CMOS fami lies. Ch(.'Ck the Texas Instru ments website at www.ti.comor theTI CD-ROM accompanying this book.
MU LTIPLE XERS (DATA SELEC TORS)
I
/'o.'IUX 1:.l/aMi' v~
""
D2
DS
Dr
.~J
s, S:
V"
D,
DO
V,
(7) (II) (10) (9) (4) ( J) (2)
n,
(I)
SO
D,
( 15)
-ENABLE - -
51
n,
GND
52
Y
( 14)
(13) 0 (1
(II)
Pin
(~
(12)
•
335
FIGURE 6 - S0
Pin diagram and logic symbol for the
EN
14t5151 8- input data
}¥ 0
sclcctor/multiplC)(er.
(5)
r
(6)
2 3 4 S
y
>'
(,
7
(b) Logic symbo l
I
EXAMPLE 6 15 u~ 74LS l5 1s and any olher logic n(.--cessary 10 mulliplex 16 dala lines onlo a single dala-output line.
Solution
An implemenlalion oflhis system is shown in Figure 6-5 1. Four bits arc required to ~k.-'CI one of 16data inputs (2~ = 16). In this application the Enable input is used as the most siF-n ificant dala-select bi t. When the MSB in the data-sck:ct code is LOW, Ihe le ft 741..S 151 is enabled. and one of Ihe data i nput~ (Do through D 7 ) is ~I ecl<..>d by the OIher three dala-select bits. When Ihe data-sck'Ct MSB is HIGH. Ihe right 741..S 15 1 is enabled, and one of the dala i np ut~ (D8 through D.s) is selected. The selected inpul data arc then passed through to the negative-OR gale and ontO Ihe single output line.
• FIGUR E 6-51
A '6-input multiplC)(cr. M UX SU
s, s, s,
n, ('
,
D, D,
"D, ", n_
EN
:}G4
:}Gt D"
0
r
no
2 3
V ro
2 3
0
, S 6 7 74 LS t ~'jJ
Related Problem
MUX
EN
V"
•
D I!
,
D I~
S 6
V"
7
/)1 '
>' Y
114 74HCOO
74LS15 1
Determine the codes 011 the select inplils rcquin"rl .. to sclect each of lhe rol\owing data inputs: Do. 0 4 , D~, and Do.
336
•
FUNCTIONS OF COMBINATIONAL LOGIC
Applications A 7- Segment DiJplo.y MtJtiplexet" Fi~ure 6-52 shows a simplified method of multiplexing BCD numbers to a 7-segment display. In this example, 2-digit numbers are displayed on the 7-scgmcnt readout by the usc of a single BCD-to-7-segme nt dL'Coder. This basic method of display muhipJexing can be extendcd to dis plays with any number of dig its.
FIGURE 6-52
Simplified 7 ~gment disptay multiplexing logic.
r-=
LOW1>CIa.'t~A\A ~ A l'\I'
~'R ' R ' R ' R n
D:lla M!1c~1
r '"R"
EN
BCDI7-seg
GI
-,,
MllX
1
A, Ii, ,t .
-
,
R.
r
" -
A
-
B
-
C
-
D
b
,
d
, I
,
,-,,-, ,=,,-, -
R., 74LS t 57 LSD UCD: A) A 2" I Ao MSD BCD: 8 3 £1 2 1i , li u
74LS47
COllimon"":IItll110C
displays
LOW cnahk~ l.SD
/
Dccotlcr
A,
1Y,
IY,
R, °A ddili"nHI buffer dri,·" ,; rcuiuy may toe fC(jui rc
lidi g il (MSD)
I l tG tl cllaJ:ok~MSD
° °
A ltig il
(LSD)
,
1Y, 0 - -
Cil {EN}
or,
0--
LOW, ':lIllolc L"mm"n-al"llXk
1-"1; di-play. }14LS139
The basic operation is as follow s. Two BCD digits (A02A IAo and 8)8 28.80) are applied to the multiplexer inputs. A square wave is applied 10 the data-selCf.:lline, and when it is LOW. the A bits (A ..A0 JAo) are passed through to the inputs of the 74LS47 BCD-to7-scgmcnt decoder. The LOW on the data-se lect also puIS a LOW on the AI input of the 74LS 139 2- line-to4-linc dL"Codcr, thus activating its 0 output and enabling the A-digit display by effectively connL"Cting its common terminal to ground. The A digi t is now on and the B digit is off.
MULTI P LEX ERS (DATA SELECTORS)
•
When Ine data-select li ne goc'S HIGH. the B bits ( H;3~I Bu) are passed through to tne inputs of the BCD-to-7-scgment decoder. Also, tne 74 LS 139 decoder'~ I output is activated, thus enabling the B-digit display. 'J1lC /3 digit is now 011 and Ihe A digit i ~ off. Thecycle repcat~ al tne frequency of the data-sek'u square wave. Th is frequcncy must be high enough (about 30 Hz) to preve nt visual fl icker as the digit displays are multiplexed. A Logic function Generator A useful application oh he data selector/m ultiplexer is in the generation o f combinational logic functions in su m-of-products form. When uS(...o in this way. the device can replace di screte gates, can often greatly reduce the number o f les. and can make design changes much easier. To illustrate, a 741..$ 15 1 8-input data sc I Cl~to r/mu ll iplexer can be used to implement any sJX>('ifit-xI 3-variable logic fu nction if the variables arc connected to the data-select inputs and each data input is sct to the logic level requ ired in the tmth table for that function. For example, if Inc function is a I when thc variablc combination is A0lAo. the 2 input (seIct11.:d by 0 10) is eonnt-'Clcd to a HIG H. This HJGH is passed throug h to the output when this particular t~ombin ation of variables OCC UI"!' on the dala-.~ck'Ct lint-'S . An example will help clarify this application.
Implement tnc logic Function speci lied in Tab le 6-9 by using a 741..5 15 1 8-input da ta se!eelorfmultiplexer. Comp.lre this method with a d iscrete logic gate implementation . .. TABLE 6-9
AI
INPUTS AI
Ao
Y
o
o
o
o
o o o
o
o
o
o
o
o o
OUTPUT
o o
Solution
Notice from the lruth table that Y is a I for the followi ng input variable combinations: 00 1,0 11 , 10 1, and 110. r or all other combinations, Y is U. For this Function to be implemented with the data selector, the data input selected by each of Ihe above-me ntioned co mbinations must be connected to a HIG H (5 V). All the other data inputs must be connt-'C tt."
337
338
•
FUNCTIONS OF COMBINATIONAL LOGIC
FIGURE 6 - 53
MliX
Data J.t:1.,ctor/multiplexer
r- } 1 ~
connected al a 3........ariable logic function generator.
tnpul
l.wk..
EN
A I
A~ -
0 I
+5V
r- y '"
2
-
A ~AIA"
-
-
+ A 1,jIA!) + AY\ IAU + A, AIA I·
3 4 5
6 7 74LS ISI
Rela ted Problem
Use the 74LS I5 1 10 implement the following exprL"SSion:
Example 6- 16 illustrated how the 8-input dala selcctor can be used as a logic function generator for Ihrcc variables. Actually, this dL'Vice can be also used as a 4-variable logic function generator by the ulilization of one of the bits (Aol in conjunction with the dam inputs. A 4-variable truth table has sixteen combinations of input variables. When an 8-bit data selector is USI.:d, each input is scll..·'(:ted twice: the ti rst time whenA o is 0 and Ihe second time when Ao is I. With Ihis in mind. the foll owing ru les can be applied (Y is the output. and Ao is the least signifil:ant b it): 1. If Y = 0 both limes a g iven data input is selected by a certain combinat ion of the input variables. AY\~ I' connect that data input to ground (0).
2. If Y = [ both ti mes i1 g iven data input is selected by a certain cumbinat ion of the input vilriables, AY\ Y\I' connccl the data input to + V (I ).
3. If Yi s d ifferent the two times a given data input is selected by a cenain combination of the input variables. AY\:!"11. and if Y = Ao, COIHK'Ct that data input loAo_
4. If Y is different the two times a given data input i:<: sel ~ led by a certain lXlI,!!bination or the input variables. A02"\1' and ir Y= Ao. connect that data input to AI).
I
EXAMPLE 6-17
Implement the logic function in Table 6- 10 by using a 74lS 15 1 8-input data selel·lOr/mu ltiplexer. Compare thi s method wit h a discrete logic gate implementation. Solutioll
The data-select inpu ts are AY\:.0 I' In the fi r.;t row of the table, AY\:!"\ 1= 000 and Y = Ao- In lhe second TOW. where A .~:0 1 again is 000, Y = Ao- Thus. Ao is con nected to the 0 input. In the third row of the tahle. ~..A 2AJ = 00 1 and Y= Ao. Alsu. in the rOllrth TOW. when Ay\.0 1 again is 00 [, Y=A o. Thus. Ao is invened and
MU LTIP LE XE RS ( DATA SelECTORS )
TABLE 6 - 10
DECIM A L
I
INPUTS
•
339
OUTPUT
DIGIT
Al
A2
AI
Ao
u
0
0
0
0
0
0
0
I
Y
o
0
2
0
0
3
0
0
4
0
0
5
0
U
6
0
1
0
o 0
u
0
8
0
0
9
0
0
'0
0
"12
0
o 0
o 0
13
0
0
0
14
0
o
15
connected to the I inpul. Thi s analys is is continued unt il each input i .~ properly connected according to the spec ified ru les. The impleme ntation is shown in Fi gure 6-54 . • FIGURE 6-54 MUX
DaI.
J;'
4> V
EN
:}oj ,
0
2
-
-
-
-
Y = A,A?ilIAI' + A","AIAn + A,A~AIA, + A,iI~AIA" + A,A~A JA" + iI,A~1I 1 AII
3
, 4
+ 1I.l1I2'"\IAo + A.1A~AIAo + A .,iI~A I'\ o + A,A111I A u
6 7 741..5 15 1
If implemented with logic gates, Ihe function wo uld require as many as ten 4- input AND gates. one lO-input OR gate, and four inverters. although pos.'lible simplifica tion would reduce IIli s requirement. Related Problem
I..n Table 6- 10, if Y = 0 when thc inputs are al/ zcros and is alternately a J and a 0 for thc remaining rows in the table, usc a 74LSI 5 1 to implement the resulting logic fu nction.
]40
_
FUNCTION S OF CO MBI NATIONAL LOGIC
J SECTION 6-8 REVIEW
1. In Figure 6-47, Do = I,D, = 0, O2 = 1, 0 ] = 0, So = " and S, = 0. What is the output? 2. Identify each device.
(.) 7415157
(b) 7415151
3. A 74LS I 51 ha~ o2Ilterno2lting l OW o2I nd HIGH levels on its do2lta inputs beginning with Do = O. The do2lto2l-lelect lines o2Ire sequenced through a binary count (O(JO, 00 1, 010, and 50 on) at a freque ncy of 1 kHz. The enable input is lOW. Describe the do2lta output waveform. 4. Briefly describe the purpose of each of the fo llowing devices in Figure 6-52:
(.) 7415157
6- 9
(b) 74L547
(,) 74L5139
DEMULTIPLEXERS A demultiplexer (DEMUX) basically reverses the mul ti plex ing fun ction. It takes digital information fro m one line and distlibutes il to a g iven number of output lines. For Ihis reason, the demultiplcxcr is also known as a data distri butor. As you will learn, dccoders can also be used as demultiplcxers. After completing this sct"tion, you should be able to - Explaillihe basic operation of a demUltiplexer - Describe how the 74HC I 54 4-line-to- l6-linc dl.'"Coder ean be used as a dcmultiplexer - Develop the timing diagmm for a demultiplexer with spt.!cificd data and deM! selection inputs
In a de multiplexer, data goe~ from one line to leveral linel.
FIGURE 6 - 55
A '·linc-t0-4-linc demultiplexer.
Figure 6-55 shows a 1-line-to4-line demult iplexer (DEMUX) circuit. The data-inpu! linc goes to all of the AND gates. The two data-select lines enable only one gate at a time, and the data appearing on the data-input line will pa<;s through the selected gate to the assodated data-output line.
o-.!l" _ ____-...-,-- , inplll
D,
Dma '>tLlpUI
'>'
I
line.
EXAMPLE 6-18
The serial data-input waveform (Data in) and data-select inputs (So and 5,) are showll in Figure 6-56. DclenJline the data-output waveforms on Do through D3 for the dcmu ltiplexcr in Figure 6-55.
DEMULTIPLEXERS
FIGURE 6-56
Dala
r-rI ! H
in --I
So:, S, '
n
,
I, I,
I,
•
r-r:
I---r--l
, ,
I I
:
:
! :
: , ,
I
Oo --tli__"-"-':~ ' : "~_:"-T:~
0,
V2 D,
1-1-' ---+-JilIt)-':: ,
,
1 r,
I
j
j
'
~--!~---1M
__,' -;
"
---+~"~'I
rw I
I
1 111
SolutiOl!
NOlicc that the select Iilles go through a binary .~equcnce so that each ~ucccssivc input bit is rou ted to V I» 0,. 2, and V 3 in sequence, as show n by the output waveforms in Figure 6-56.
Related ProbLem
Develop the timing diagram for the demult iplexer if the Su and 5, wavcfOims arc both inverted.
°
THE 74HC154 DEMULTIPLEXER We have already discussed the 74J-1C154 decode r in il ~ appl ication as a 4-line-to- Ib- line decoocr (St.-c lion 6---5). This devie{.' and other decode rs can also be ust.'d in demu ltiplex ing applications. 111e logic sy rnool for Ihis device w he n used as a demuUiplcxer is shown in Figure 6 - 57. In de muili plexer applications, the inpullint.'S are used as the data-select lines. One of the chip selel·t inputs is used as the data-input linc, with the other chip select input held LOW to enable the internal negative-AND gate at the bOllom of lhe diagrarn.This device may be available in olherCMO~ or TTL families. Cheek Ihe Texas Instruments web· site at www.li.com 01' the Tl CD-ROM accompanying this book. FIGUR E 6 - 57
DEMUX 0 I
2 ]
4
S
~ S . I~ S~ ~ ..QQL S"
Daw .,.:1«1 loll<"; {
S,
6 7
}*
8 9
10
"12 13
r
14
"'"'" ~~ EN
15
(I ) (2)
(3 ) (4)
(5) (6) (7) (8)
(9) (10) ( II ) (13)
(14)
(15) ( 16) ( 17)
Du D,
n, n, n,
n, n"
n, D,
".
1)'11
D" f)l ~
D"
°11
n"
Tho: 74HC154 do:coderwo:d OM demu ltiplexer.
01
341
342
•
I
FUNCTIONS OF COMBINATI ONAL lOGIC
1
SECTION 6 9 REVIEW
6-10
1. Generillly, how Ciln iln decoder be used ill il demultiplexer?
2. The 74HC154 demultiplexe r in figure 6-57 has d biodry code of 1010 00 the ddtd-select lines, dnd the data-input line is LOW. What are the states of the output lines?
PARITY GENERATORS/CHECKERS Errors can occur as digilal codes are being transferred from onc point 10 another within a digital system or whi le codcs are being transmitted from one system to anoth"T. Thc crrors take the form ofundcsircd changes in the bits that make up thc coded informmion: thaI is. a I can change to a 0, or a 0 10 a I. becausc of component malfunctions or elccu;cal noise. In most digital systems. the probability that even a singlc hit error wi ll Ol;cur i.~ vcI)' small. <1nd Ihe likclihlxxl that more than nne wi ll occur is ,,'Veil smaller. l\'evenheiess, when an error occurs undetected, il can cause serious problems in a digital systcm . Artcr completing this section. you should be ablc to • Explain the conccpt of parilY • Implement a basic parity circuit with exclusive-OR gates . lA'SCribc the operation of basic parity generating and checking logic • Discuss the 74LS280 9-bit parity generator/checker . Discuss how error detection can be irnplement,,>(j in a data transmission
The parity method of error delL'c tion in which a par ity bit is attached to a group of intormation bits in order to make the total number of Is either even or odd (depending on the system) was cover,,'(] in Chapter 2. In addi tion to parity bits, scveral specific coJ~ (llso provide Inherent error detcction.
Basic Parity logic A parity bit indiCiltes if the number of I ! in d code is €\len o r odd for the purpose of error detection.
In order to check for or to generate the proper parity in a given code. a basic principle can be uscd:
Tile sum (disregarding curries) of an even numbu of Is is always 0, lind the sum of an odd number of Is is ah\'ays 1. Therefore, to dClcrminc if a givcn codc has c,·cn panty or odd parity, all the bits in thaI code arc summed. As you know, the sum of two bi ts can be generated by an exclusive-OR gate, as shown in Fi gure 6-58(a); the Sum of four bits can be formed by Ihrccexclusive-OR gates connect,,-d as shown in Figurc 6-58(b); and so on. Whcn the numhcr o r Is on the inpUIS is even. the outpur X is 0 (LOW). When thc number of Is is odd, the output X is r (H IGI-I).
A,,- "---
FIGURE 6-58
' ,--'L_'
A, -
(a) Summing or two bilS
e,,"''
, , - , c" L...-'
(b) Summing of four bits
x
PARITY GENERATORS/CHECKERS
•
THE 74L5280 9- 81T PARITY GENERATOR/CHECKER The logic symbol and function table for a 74LS280 are shown in Figure 6-59. This pruticular device can be usetl to check for odd or even parity o n a 9-bit co
~ (9)
( 10) ( 11) f),,(a
inpta
( 12)
( 13)
(0 (2) (')
A
8
C D E F
(5)
(6)
~
E.en
r: O•.lII
G
"
(lI) Tt-.wi lional logic
symbot
(b) Funclion lable
FIGURE 6 - 59
The 7415280 9-bit p<'I rity generator/checker.
Parity Checker When Ihis device is used as an even parity chL'C kcr, the number of input bits should always be e ....en; and when a parity error (x:curs, the 1: Even output goes LOW and the 1: Odd outpul goes HIGH. When it is USL'd as an odd parity chL'Cker, fhe number of input bits shou ld always be odd; and when a parity error occurs, the 1: Odd output goes LOW and the 1: Even output goes HIGH. Parity Generator If this device is lISL-'
A Data Transmission System with Error Detection A simplified data transmission system is shown in Figure 6- 60 to illustrate an application of parity generators/checkers. as well as multiplexers and demultiplexL'rS. and to illustrate the need for data storage in some applications. In this application, digilal data from .~e\'ell sources are multiplexed onto a single line for trans missiun 10 a distan t point. 111e se\'en data bits (Do through /)6) are applied to the IZlll ltiplexer dala inputs and, at thc samc lime, to thc evcn pari ty generator inputs. The r Odd output o f Ihe parily generator is used as the even parity bit This bit is 0 if the num ber of I .~ on the inputs A through I is even and is a I if the number o f Is 011 A through I is odd. Th is bit is D7 of the transm illcd code. The data-select inpuls are repeatedly cycled through a binary sequem;e, and each da ta bit. beginning with Dr). is seriall y passed through and 01110 the transmission line (Y). 111
343
344
•
FUN CTIONS OF COMBINATIONAL lOGIC
f"Ollr-oondU<.1or trnnsmi sskln line
/ Em..- = I
MUX
-,FEN S" SI
-
O}
DE!I.'IUX
~ O }G~ 0,
G~
2
D" D, D,
3
0 ,
4
D,
3
5
D,
D,
4
6
1>"
D_,
5
7
D,
Dt.
6
5. --------------1' D"
~
- - - - -'. ------j 0
DI
I
D:
2
D,
I>
r-;-
-
f
7
74LSIJII
E'ell paril}" bit (1).1
7.U5151 I~wn
2
parily bil
L - _--jA
A
"-----1 8
B
' - --Ie L-_ _ -j D L-_ _ ---j E L -_ _ _--jF L-_ _ _--jc
e D
E
"'old
r
F.,e n
F G
-
H
H
~
I
I
--
10\ lor.: puril~ d .....·u...
I;\T:>. JI'lrll\ gencr~ IUI"
c7-U.s:>8tJ)
· Su)r.J.ge dL... ·i~, are inlnxl"cL"(\ in Ch'lpler 9;tnod
u~1
c74LS2li())
in other later dmplcrs.
f iGURE 6 - 60 Simplified data trammill;on !Yitem with error detection .
The Pentium miuopnx:alOf
perforll'll int ernal parity dlednd addrell buses. In a re.Jd operation, the externaol S)'Item a m tr.>rufer the p;!rity in(orm.Jtion
together with the data byteJ. The Pentium check! whether thr:: fClulting parity i1 even and lend! out the corresponding 'igrnl. wtx:n it wndl out .J/'l addrCli code, the Pentium doe! not pr::rform an iiddr~ parity dlcd<, bu t it does generate an I even p:lrity bit for the .Jddre!.S..
I
this example. the transmissio n line cO/lsist<; of four conducto rs: on\! canies the serial data and three carry the timing signals ldata selects). There are more sophisticated ways of sending the timing information. but we are using this direct melhod to illuslrate a basic princi ple. AI the demultiplexer end of the system, the data-select signals and the serial data stream arc applied to the demultiplexer. The data bits arc distributed by the demu ltiplexer onto Ihe OUlput lines in the o rder in which they occurred on the multiplexer input s. That b. Do comes OU t on Ihe Do ompul. Dr comes out on Ihe D, outplll , and so on. The parity bit cOllies out on the 0 7 outpu!. These e ight bits are temporarily sto red and applied to the even parity checker. Not all of the bi ts arc present o n t.he parity checker inputs unt il the parity hit D7 comL'S uut and is stored. At thi s time, the error gate is enabled by the dalaselecl code I I I. If Ihe parit}' is correct, a 0 appears o n lhe r Evcn ou tput, keeping Ihe Error outpul at O. If the parily is incorrect, all I s appear on the error gate inputs. and a I on the Error Output results.
TROUBLESHOOTING
•
345
This particular application has demonstrated the nl.:<.-d ror data i\lOrage so that you will be better able to appr{."Ciale the usefulness ofthe storage devices that will be introduct!tl ill
Chapter 7 and u~-d in othcr later chapters. The timing diagram in Figure 6--61 illustrates a specific case in wh it·h two 8-bit words are transmitted, one with correct parity and onc with an error.
o
FIGURE 6 - 6 1
2l4567012~4.'i67
Example of d~ t/l I:riJrnmiuion with without error for the \)'Stem in Figure 6-60.
~nd
Bil rttd,·.:d incOfTocl ly (0 "a' Ir
Dala sm..·am al
oct'>tl..X inpul l lTur
----1
i nCTION 6-10 REVIEW
1. Add an even parity bit to each of the following codes:
(a) 11 0100
(b) 01100011
Z_ Add an odd p
(a) 1010101
(b) 1000001
3. Check each of the even p.'Irity cod~ for a n error.
(a) 100010101
6 - 11
(b) 1110111001
TROUBLESHOOTING
In this sct~t ion. the problem or decoder glitches ii\ introduced and examined from a troubleshooting standpoint. A glitch is any undesired vultage or current spike (pu lse) of very shon du ration. A glitch can be interpreted as a valid signal by a logic circuit and may caUS(' improper operation. After completing this S<."Ction, you should be able to • Explain what a glitch is • Detcrminc the cause of glitches in a decoder application • Usc the method of output strobing to eliminate glitches
The 74LS 138 was used as a DEMUX inlhe data tr8lL'imission system in Figure 6-60. Now the 74HC I38 is used as a 3-line-to-8-line decoder (binary-to-octal) in Figure 6-Q2 to ill ustrate how g litches occur and how to identify the ir cause. T he A~ IA o inputs of tht' decoder are sequenced through a bi nary count. and the resulting waveforms of the inputs and Ollfputs can be displayed on the SCIT"C1l of a logic analyzer. as shown in Figure 6-Q2. A2 lransilions arc delayed from AI transit ions and AI transitions arc delayed from Au transitions. Thi ~ commonly ou;urs when waveforms arc generated by a binary counter, as you willieam in Chapter 8. The output wa ....eforms are correcl excepl for Ihe g litchcs lhat occur on some of the output signals. A logic analyzer or an oscilloscope can be used to di splay g litches. which arc normally very di rfic ultto SI..'C. Generally, thc logic analyzer is preferred. es(X.'Cial ly for low repetition rates (less than 10 kHz) andlor irregu lar occurrence because most log ic analyzers have a glitch captllre capability. Oscilloscopes can be used to observe g litches with
346
•
FUNCTIONS OF COMB INATI ONAL lOG IC
FIGURE 6 _ 62
Pl)im I
Point 2
Point 3
l'oim 4
Ck:coder w.w<-form. with ootput glRdlel. BINKXT
A, A, I,
I
0
2
,
,
,3
+V~
,
&
liN 6 7
o I
2 3
,
,
74HC138 6
7
reasonable success, particularly if the glitches occur at a regular high repeti{;on rate (greater than 10 kHz). The points of intere...t indicated by the highlighted area.. on the input wavefonns in Figure 6--62 are displayed as shown in Figure 6-63. At point I there is a transitional state
l'oin t 3:
wa"erol m~
{)f1
e ~l'anded
II,~
time ba
I ]() 100 FIGURE 6 - 63
Decode, IlliJl.'eform displilyS showing how tramitional input st ate p!'"oouce glitche in the output '-"<>VCforlTli.
TROUBLESHOOTING
•
347
ofOC() due 10 delay differences in thc waveforms. This causes the first glitch on the Ooutput of the decoder. At point 2 there are two tmnsitional state!';. 0 10 and OC(). These cause the glitch Oil the 2 output of the decodcr and the second glitch on the Oo utP~I . lespectivcly. AI poi nt 3 the transitio nal state is 100. which causes the firsl glitch on the 4 o utput of '~e decoder. AI point 4 the two I nm s ili~n al states, 110 and 100. resul t in the glitch on the 6 output and the second glitch on the 4 output. respectively. One way to e liminate the glitch problem is a method called strobing, in which the decoder isenablcd by a stro be pulse only during the times whe n the waveforms are nOI in transil ion. This method is illustrated in Figure 6-64.
Strohc
... FIGURE 6-64
A"
Application of a strobe u.r.J\Ieform to eliwinilte glitches on decoder
A,
OUtpUll.
BIN/OCT
0
.1 "
I
A, A.
2
0
2
4
3
, 4
&
Slrut>.:
EN
(,
7
74ttCJ38
-
I
SECTION 6 - 11
REVIEW
A,
I
2
J 4
, "7
1. Define the term glitch. 2. Explain the basic cause of glitches in decode r logic. 3_ Define the term strobe.
Troubleshooting proble ms that are keyed 10 the CD-ROM are available in the Multisim Troubleshooting Practice section of the end-or-chapter problems.
ANDS
-
'N
In addition to glitches that are the result of propagation delays, as you have seen in the case of a decoder, other types of unwanted noise spikes can also be a problem. Current and voltage spikei on the Va and ground tines are ca used by the fast switching wa-.eforms in digital circuits. This problem can be minimized by proper printed circuit board layout Switching spikes can be absorbed by decoupling the circuit board with a 1 pF capacitor from Va to ground. Also, smaller decoupling capacitors (O.OllIlF to 0.1 IlF) should be di~tribut:ed at va rious points between Va and ground aver the circuit ho.1rd. Decoupling should he done cspedally near devices that are switching at higher rates or driving more loads IUch a-; oscillators, counters, buffers, and hm drivers.
1
348
•
FUNCTIONS OF COMBIN ATIONAL LOGIC
light fO<" a minimum of 25 • or as long a. tht:re il no vehicle on the side street. The side Itreet is to have a green light until there il no vehicle on the ,ide street or for a maximum of 25 I . There is to be a 4s caution light (yelloW) between changes from green to red co both the main sb<.>et and on the side street. These requirements are illustrated in the pictorial diagram in figure 6-65.
interva ll of 25 sand 4 s that are required in the system and to generate a clock lignal for cycling the system (timing circuits). The time interva ls (long and short) and the vehicle sensor are inputs to the lequentiallogic because the Ulquencing of states i, a function of these variables. logiC circuits are also needed to determine which of the four statel the s)'ltem is in at any given time, to generate th e proper outputs to the lights (,tate decoder and light output logic), and to initiate the long and lhort time interval!. Interface circuits are included in the traffic light and interf<>ee un it to convert the output levels of the light output logic to the vo ltages and currenb required to tum on each of the lights. Figure 6-67 ., a more detailed block d iagram showing these eslential e lements.
Developing a 8ktck Diagram of the System In this digital l'yitem application, you begin working with a I.r.lffic light control S}'Item. In this section, the S}'Item requirements are est3bli!hed, a gene r31 block diagram is developed, and a state diagram il Geated to define the sequence of operation . A portion of the system ill\
traffic light OIt the intencction of 01 bUly main sbeet and an occasionally UH."
from the requirements,}Ou can develop a block diagram of the l'yitem. First;.}Ou know that t he system mUlt control We different pain of lights. These are the red, yellow, and green lights for both directions on the main street: and the red, yellow, and green lights for both directions on the side street. Also, )'OU know thdt there is one externa l input (other than power) from a side street vehicle sensor, Figure 6-66 il a minimal block diagram showing thee requirements. Using the minimal Iy$tem block di3gram, you can begin to fill in the ddails. The sy$tem hal four states, al indicated in figure 6-65, 10 a logic circuit is needed to control the iCquence of statt.'I (~quentia llogic) . Also, cira.tits are ne<...:fed to generate the proper time
The State Diag....", A ltate diagram graphiGllly shows the
sequence of states in a Iystem and the conditionl for e.x:h state and fur trarnitiorn from one state to the next Actually, Figure 6-65 is a form of state diagram because it 1hoWi thc sequence of states;mel the conditions. Definition of Variable.! Before a traditionalstate diagram can be developed,
j Main
o o
Side
0 0
M Di n
-
Firsl Slale: 25 sccon<.ls min imum or lIS long a, rhue is no vehicle on
Side
M ain
Side
Mai n
Side
0 0 0 0 0 0 - 0 0 -
o
Second s.tOllC: 4 secood..
s ide <,treel
FIGURE 6-65
Require ments for the traffic light lequence.
'n lird ~tale : 25 seconds max imum or unlit
iherc is no vchicle 00 $ide srrecl
I~mh ~IaIC:
4 seconds
OIGITAl SYSTEM APPLICATION
FIGURE 6 - 66
•
TI1'Jfic lighl and ir le n ace unil
A minilT01 system block diagram.
Traffic lighl control logic
{
Main
Rcd
Yellow
.
G=,
Vehicle Sl·nsor
R~
{
Side
Yellow ~I
Grcc l>
I T mffic light conlrollogic
Truffie liJl hl and inlerface uni l Combinalionallogic
S£llucntiallogic
{ Vehicle
50
Gm, code
sensor inpU I
Main
Side
1 1 1
Roo Yel low
G=,
Cloc k
,-""
;
Green
S, {
Shon limer
Roo Yell ow
limer Long lriggL'f
Timing cirCllits
Short Irigger
r-
:
1
o
Completed in this ChaPl er
0
0
Completed in Olnpler 7
Completed il> O1aplcr 8
FIGURE 6 - 67
System block diagram showing the enenti31 elements.
the variables that determine how the system sequences through its states must be defined. These variables and their symbols ilre listed as Iollo~ :
• Vehide present on side street = V, • 25 s timer (long timer) is on =
1i.
• 4 s timer (short timer' il on = Ts
The usc of complemented Vilriables indicates the oppcxite conditioos. For
example, V, indiutes thdt there is no vehide on the side street Tl indicates the
349
350
•
FUNCTIONS OF COM81NATIONAllOG I C
system remairn in this state for 4 s when the short timer II on (TJ and gee. to the next stlte when the short timer goes off ( TI ) .
long timer is off,1'5 indicates the snort timer is off.
Oeicription of the State Diagram A state diagram ilshown in Figure 6-68. Each
Third Jtilte The Gray code for this state il I'. The main street light il red and the side street light is green. The system re-
of the four stdtes is labeled according to the l-bit Graycode sequence, M indicated by the cirdes. The looping arrow at each
maim in thissbte whe n the long timer is on ilnd there is a vehicle on the side street
state indicates that the ~stcm remilins in that state under the condition defiJ"led by the associated variable or expreSiion. Each
(TlVj. The system goes to the next state when the l5 s have elopsed or when there is no vehicle on the lide street. whichever comes fiut (Tl + V,).
of the arrow! going from one stilte to the next indicates a date tra nsition under the condition defined by the associ<>ted variable Or expremon.
Fourth stale
The Gri!)' code for this
state is '0. The main street light is red and the side stree t light is yellow. The sY'tem remains in this state for 4 , when th e short timer il on (TsJ
First Jtate The Gray code for this Itate is 00. The main street light is gre en .md the side street light is red. The system remains in thi~ state for
to the first ltate when the Ihort timer goes 0(( (Ts).
timer is 0 ' 1 or as long as there is no vehicle on the side street I T~ + V, ). The system
A block diagram for the combilli"ltiolli"ll portion of the system k d~loped M
rogiC
the fiu! step in ckligning the logic. The three functions that thil logic mult perform are defined as foIIOWI, and the resulting di.-.gram...,;th a block fof"each of the thtee n..nctiofll iI shown in Figure 6-69; • Stale Decoder Decodes the l-bit Gr
• Light Outpul logic Ule! the decoded state to activate the appropriate traffic lights for the main and side street light units. • Trigger Logic Uses the decoded statel to produce lignals for properly initiating (triggering) the long timer and the IhOlt timer.
The Cornblr"l
goes to the next sbte when the 25 I timer is of{ and there is a vehicle on the side street (T~V.).
Second ltate
The Gray code fOf this stale is 0 I. The main street light is yellow (caution) and the side street light is red. The
The focus in this chilpter', ~stem
Implementation of the
applic;ation is the combiniltional logic
Combir"l
portion of the block di..grilm of Figure 6--67. The timing ilnd the sequentiill logic orcuits will be the slIbjed5 of the Iystem ilpplic;ation sectionl in Chapters 7 and 8.
Implementing the Decode.- logic The state decoder portion hal two inputs (2- bil Gray code) and an output for each
FIGURE 6 - 68
5bte diilgram for the traffic light control sY'tem showing the GriIY code sequence. Fimsl:lle (]()
r,
,.
l'cunh
r,
J\.1aill: gr«n Sid.- n'd
"
,,,
""""'-
~!1I~
0'
Milin: red Silk; )dlow
Main; )'cllo\\ Side; red
Third ~!a!e
"
Main: red Side:green
,,
DIG ITAL SYSTEM APP LICATION
IGrn)
l'Od,.')
-
S, S,
SlalC Oul plJl~
351
Li gb t output logic
State oIccolkr
State inpuh
•
Main {"~ Ycllow
'--
-Sid+': -
r
G~"
.')0 2
S0 3
SO,
G rcell
Long Trigg£ r logic Shol1
M" MY MG
Light outpu ts to interface
SI?
circuit in li gh t unit
SY SG
r - TO
r--
hUl in~
clrcllits
FIGURE 6 - 69
Block diagram of the combinational lOgic.
FIGURE 6 - 10
The state decoder logic.
S, Gf3y code statc inputs
, -L--J
--so,
{ S, -~-+---i .'if),
SI,,·C exltpu ts
.'iO,
so,
of the four states, iU shown in Figure 6-70. The two Gr
SOl = 5 lSu 502 = 5 15u
SOl = SJSo 504 = SISu The truth table fOf" this ,tate decoder logic i. , hown in Table 6- 11 .
Implementing the light Output logic The light output logic take, the fou r state outputs and produces li)( outputs for ilctiv.. ting the trilffic lighb. Thele outpub arc designated MR, MY. M6 (for moin red, main yellow, and main green) and 5R, 5y' 56 (for side red, side ye llow, and ,ide green). Referring to the truth table in Tab le 6- 11, you can .ee t hat t he traffic light outputs c.an be e)(pressed as
MR = 50) MY = 50~
MG = SOl
+ 50~
5R
=
501
+ 5Qz
5Y = 504
5G
= 5~
The outpu t logic is implemented as shown
in f igu re 6-7 1. Implementing the TriggN logic
"The
trigger logic produce! two outputs. The
1000g OUtput ;1 a l OW- to-H IGH transition that triggcn the 25 I timing Circuit wilen the $)'Item gocs into t ile first (00) or third state, (11). The Jhort output is a LOW-toHIGH transition that triggers the 4 I timing
352
•
FUN CTIO NS O F COMfl lN ATIONAl lOG IC
TABLE 6-11
TllJth table for the combinab'oo
STATE INPUTS ! STATE OUTPUTS 51 50 50 1 SOl SOl 50 4
0
0
0
0
0 0
0
0
0
0
LIGHT OUTPUTS MY MG 5R 5Y
MR
0
0
0
0
0
0
0 0
0 0
0
0
0
0
0
0
SG
()
()
0
0
TRIGGER OUTPUTS LONG SHORT
0 0
0
0 0
0
SI:lIC OOlpul$ are :Jo:'1iw, HIGH and li~1 0UIpu1l. an: acli>-c-HIGH. MR >t.'1I1d>. foc m,'U/1 SIred red. SO for side !itrect ~rttfl, etc.
-
MR
su,
MY
He
Il
SR
SY SC FIGURE 6 - 11
The light o u tput logic:.
SO'=D-
SO~
Slmrt
'"I
(b)
FIGURE 6-7Z
The trigger logic.
circu it when the ly!tem goes into the 1eCond (0 1) orfourth (10) It .. tes. The bigger outpubare.hown in Table 6-11 and in equation form iii folto~;
Long trigger = SOl
+ 50l
Short trigger = 502
+
50~
The bigger logic is Jhown in Fjgure 6-72(01). Table 6-11 aho lOOw! that the Long outputand the Short output .. re complemenb, K) the logic can .. IK) be
implemented...,.;th one OR gate and one
combinational logic and develop')/I o f
inverter. OIl IIlov.m in part (b). Figure 6-73 IhOWl the complete combin.. tional logic that combine! the lute decoder, ligh t output logic, ')nd
the output wavdorms.
trigger logiC.
• Activity 2 Show how )~tion,) 1 logic with 74XX functions. • OptiOOlltI ktivity Write,) VHDl progrom
System Aslignment • ktivity 1 Apply waveforml (or the 2-bit Grily code on the 50 <100 51 inpub of the
dell:ribing the combinational logic.
SUMMARY
Su
J
Gr:lycodc
slate inputs
UN } Main
,\,
35 3
1i~ht
group output
Mt·
1
•
"G
11
I
SN
~
J
I
Side II£ ht } group tJlllpLIt
Sf
SG
4>
Shurt tri~l!<:r
FIGURE 6 - 73
The complete combinationa l logic.
•
Half-adde r and fu ll-adder operations are su mma ri7..ed i n Figure 6-74.
•
Logk symbols with pi n number.; fo r the les used in this chilpler arc :-;hown i n Figure 6-75. Pin designations may differ from some manufacturers' data sheets.
•
Standard logic design.
FIGURE 6-74
rllnct ion~
from Ihe 74XX series arc availuble for use in u pmgr".un nlublc logic
H3I f· :Jddcr
Fu ll-adder
~
Ii:;"C~c--A
0 0
I
r
Carry Out
Sum
Carry In
Carry Out
c,,"l
I
A
B
c'n
Cout
0 0
0
0 0
U
0 0 0
0
0
0 0 0 0
0
I
I
0
0
I
0
Inpub
I
0 0 0
0 0
I
0 0 0
354
•
FU N CTIONS O F COM BIN ATI ON AL LOG IC
," "",
",
.,
" "
"
--, ....('4,
'" ,l,
'"
-~
".
~,
,"," •
,"
"" "'" II.,
,"'" ,",,, '"
.
•
.•
", ,"
,--
"" ,'" ,"
]-
."
""-
'"'"
.
... ..
~
, -~
~,
"" ". ".
~
, "', , "."• "..
~,
~,-
"" ,",
, "" ,I;'
.....!!L.
"',
-"-• '" -
," " '" ••
"
:., ......r........
".
...
", ••• ,"",
-mn·
,.". •
,.""'...
..." ,
D
""
"" ." '"", ,"",
, <,<.
""
;,
~ ~
~
",
.," ..
,",
'. <,
""
'
", ... " ~
, '"
~
"" •s ..!.!2... :)~
s:
~,
,~
("
V,
•.1J
,"'" ,,', ,'" ,~...'.!1!...
,,. ", '"".
•
," ,
. 0
v, ,", ,
_.
" .. "" •
..
0
~,":, ...
,"
,.'
·' - ' _ .L:CJ
," ," •...'"," ...~"","'"
." Qo..! .. -
.",. "
,.101(",,.,
"
~[
"', "
....
." ,," ,Il'
,
,• "
.",', " ," "
"
'"'
.........,-.....--...
....... ~......,........
,• ,
IF\·.... ,~
. , p :}. ,
.," ;, ),
""
"
"
~~
'"-
FIGUR£ 6-15
KEY TERMS
Key t erml and other bold terms in the chapter are defined in the cnd-of.-book glossary. Cu.
Decoder A digi tal ci rcuit that COllVerts coded information in to a f"miliar or noncoded fonn. Demult iplexer (DEMUX) A circuit that line~ in" speci fi ed time sequence.
swi td~
digi tnl (latn fmm one input line to several output
Encoder A digital circuit that converts information to n codeJ form. Full-lldde r A digital circuit that adds two bits anJ an input carry to produce a ~u m and an output c"rry. G litch A voltage or current spike of short du ration. ustmlly unimentionall y produced anJ unwan ted. Hlllr-uddcr A digital drcuit that adds two bi ts and produces a ~u m and an ou tpu t carry. It cannot handle input carries. t ook-ahead rn rry A method of bi nary addition whereby carries from prccl-d ing adder st"ges arc nn ti cipatoo, thus climinnting curry propagation delays. Multiplexer (/\lUX) A ci rcui t that swi tches digi tal da ta from sc\'eral inpu t li nes ooto It single outpu t line in n specified lime sequence. Pllrity bit A bi t attached to each group of information bi ts to make the IOtal number of Is odd or e\'en for eve ry group of bits.
SElf-TEST •
3SS
Priorit}' cncoder An encodcr in which only the highest value input digit is encoded and any other ~c tive input is ignored. Ripple carr}' A method of binary Ilddition in which the out pu t l:alTy from eilch addcr becomes thc input carry of the neltt higher-order adder.
I. A half-addcr is characterized by (11) twO inpms and twO ou tputs
(b) three inputs and two outpu L~
(c) two inputs and three out puts
(d) Iwo in puts and one output
2. A fu ll-adder is characterizcd by (II) two inputs and two outputs
(b) three in puts and two OUtputs
(c) two inputs and threc outputs
(d) h\'O inputs and one output
3. The inputs 10 II rUIl-lulder arc A
:0
1, B "" I , Ci" = O. The outputs arc
t = I.C"", = O
(a) 1: = I.C.. " = I
(b)
(el I: =O,CWI = I
(d) I: = O,C.,..=O
4. A 4-bit parallel ackIcr can add (II) two 4-bit binary nLimbers
(b) two 2-bit binary numbers
(c) four bits at a time
(d) fOLir bits in sequence
5. To cxpand a 4-bil parallel adder to an 8-bit parallel addcr. you must (II) usc four 4-bit adde!'s with no interconnectio ns (h) usc two 4-bit adders and connect the sum outptlt~ of OIle to the bi t in pllts of the other
(e) usc eight4-bil adders with no inten:onncc tions (d) use two 4-bit adders wi th the carry output of one connected to thc carry input of the
ot her 6. If a 74HC85 magnilllde com pa rator has A = 1011 and 8 = 1001 on
i L~
iU IlUL<;, the ou tputs are
(II ) A > I3 = O,A
(b) A>8 = I,A < B = O,A = B=O
(c) A > 8 = 1, A
(d) A >8 = O, A
7. If a l -of- 16 decoder wit h active· LOW out pulS exhibils a LOW on the dec imal 12 output. what arc the inputs? (II) Ay42"\,Ao = 1010
(h) A.v\:zA IAu = 1110
(el AY\ 0 IAo = 1100
(d) Ay\.t\ IAO= 0100
8. A BCD-t()-7 segn'oCn t decoder has 0 100 on its ill pulS. The aClive outputs are (n)
a. c./. g
(b) b,
c, /. g
(e) b. c,e.!
(d) 1). tI. e, R
9. If iII\ oclal -to · binary priority encoder has its O. 2. 5. and 6 inputs at the active level, the aCliveHIGH binary omput is (a) 110
(b) 010
(c) 10 I
(d) 000
10. In general. a mult iplexer has (8) a ile data input. several data ou tputs, and selection illPUIS
(b) Olle data input, oned
II. Data selectors arc basically the same as (a) decoders
(b) demult iplexers
(e) multiplexers
(d) encoders
12. Wh ich of the following codes exhibit even parit y? (a) 10011000
(b) 01 111000
(e) 111 11111
(d) 11010101
(c) all
(0 both answers (b):md (c)
356
•
FUNCTI O N S OF CO MBINATIO N A L l OGIC
PROBLEMS SECTION 6-1
An~wcrs
to odd-numbered problerm are at the end of the book.
Basic: Adde rs I. For the full-adder of FigufC 6--4, dctcnninc the logic stmc ( l or 0) at CllCh gate outpu t for the followi ng inpu ts;
(a) A '" t. B '" I. C.. = I
(c) A = 0 , B == I. C;. : 0
(b) A = 0, B = L Con = I
2. What are the ti l II-adder inputs that will produce each of the fol lowing outputs; (a) I = O, C"", : O
(b) l: = I, C.... = O
(c) I: = I , e"", = I
(d) I: = O. c.~= I
3. Detcrmine the ou tputs of a fli ll-addcr for each of the following in pllls:
SECTION 6-2
(3) A = I , B = O.C.. =O
(b) A = O.H = O.C", = I
(c) A = O. B = I. C.. = I
(d) A = I. B = 1. Cin = I
Par.llilel Binary Adders 4. For the parallel ad<.ler in Figure 6-76. <.Ietermine the com plete sum by ana lys is of the lo£ical operation of the circuit. Verify your result by longhand add ition of the two input nu mbers.
FIGURE 6 - 76
0
,-
,-
A B C,
-I
C
E
I
n.' A B C.
A B C.
-
C
~
C_
E
I
~
E
I
E,
5. RejXat Prob lem 4 for the circui t and input co ndi ti ons in Figure 6-77. FIGURE 6 - 77
u ()
u
,A
Cw,
I
B Cin
A
,
u
Cw,
()
, C.
,-
-
,
A
C~
u
,-
, C.
A
C_
E
I
-
Il
B Cin
A
E
C
I
-
B Cin
-
- ,I
E,
6. TIle inpu t wU\'L1"onns in l'1gurc 6-78 arc applied to a 2-bit ac:ltlcl: Determine the waveforms for the sum and the OI,J tpUl eafTY in relation to the inputs by conSl nlctinJ:! a liming diagmm. FIGURE 6 - 711
PROB LEM S
•
357
7. The following scq nen(;c s of bils (right-most bit fi rst) appe;lr on the inputs to a 4-bit pamllel adder. Dete mline the resnlt ing ~eq uencc of bi ts Oil each ~u m output.
A,
lotH
A,
111 0
A, A,
0000
B,
11 11
8,
J 100
10 11
1J,
1010
B,
00 10
8. In the process of checking a 74LS283 4-bil pmal lel adder, the followi ng vollflge levels arc observed on its pins: I-HIGH, 2-HIGH , 3-HIGH, 4- UlGH. 5-LOW, 6-LOW, 7-LOW, 9-HIGH, I{I-LOW, I I-HIGH , 12-LOW, 13-HIGH, 14-HIGH, fi nd IS-HIGH. Dctcrrninc if th e Ie is functioning properly.
SECTION 6-3
Ripple Cany Venus Look-Ahead Cany Adden 9. Each of the eight fu ll-adders in all S-bit pamllcl rippl e carry addcr exhibi ts Ihe following propag;lIion de lays: A to ra nd C"", :
40 ns
H to rand C..":
40 ru;
C;" 10 1::
35 ns
C;., 10
C'".,,:
25
ns
Delennine the max imnm total time for the addition of IWO S-bil numbers. 10. Show the addil ionallogic ci rcuitry necessary to make the 4-billook-ahead carry adder in Figure 6-18 into a S-bil adder.
SECTION 6 - 4
Comparators 11. Thc wflvefonlls in Figure 6-79 arc applied 10 the com paTlltor as shown. Octcmline the OUlput (A = 8) waveform.
FIGURE 6 - 19
COl\·]p
Ao ~rI..
Ao-
A, . H J j
.1 1 -
11,
, ,
,t--!,
,, ,-
:,-
, ,
BI ~
~}A
A",n
", - ~)n
-
flo -
12. For the 4-bit comparator in Figure 6-80, plot each ()J.tpul wa\'Cform for the in puts shO\\ln. '111e OUI PIll~ arc (lcti ve-HIGH . FIGURE 6 - 10
, , ,, A1.-LJ , , A2D, , AlI, T,
n..
AII ....J
I
A,
,,
, , , ,L.:...,
Bo ~~~ I
COM P
A"
,
-t--i....l
/J I ~ I
, , , ,, , , ,, , ,, I
n-
Ih
~
tll
! ! ~
A,
A,
} A > IJ
Vco
",
s,
/J~ -
B,
A >B
A = IJ
A: n
A < JJ
A < /J
} 741-1C85
358
•
FU NCTIONS OF COMBINATIONAL l OGIC
13. For each set of binary number.;. determine the output stmes for the com p3ra tor of Figure 6-22. (a) Av10 IAo = 1100
SECTION 6 - 5
(b) A)I\Y\IAo :; I()(X)
(c) AY\zA IAo = 0100
DKOden 14. When a HIGH i ~ o n the o utput of each of the dl!(;oding gates in Figu re 6--& 1. what is the binary code &ppc
FIGURE 6 - 111
~£p<,- - -- ----'
(a)
'b)
-,,, ~c
,:I ,~ ==
)-
(e)
,',- -<1 'I , _ _ _ _ _ _ _-'
(d)
15. S how the decoding logic for each of the fo llowing
L'OdeS
ifan activc-' -IIGH ( I) o utput is
i"C(luircd:
(a) 1101
(b) 1000
(c) 1/01 1
(d) 11100
(e) 101010
(I) 11 11 10
(g) 00010 1
(h) 1110 110
16. Solve Prob lem 15 . g iven that Ol n acti ve-LOW (0) o utput is required. 17. Yo u wish 10 dc«.'(;t only the prese nce of the codes 101 0. 1100. (X)() I. and 101 1. An active-HIGH o utput i~ required to indicate the ir presence. Deve lop the mi nimum decoding logic with a s ing le Oll tput that wi ll indicate when anyone o fthcsc codes is o n the inputs. For any other <:ode. {he output mu st be l OW.
18. If the in put wa veforms arc
fO the Uccodin}l logic as indicatl-d in Figllre 6-82. s ke tc h the Out put wave form in proper rc lOll io n to d ie inputs.
FIGURE 6 - 112
A"
A,
"
19. Bcn num ber.-; arc applied sequentially to the BC D-to-dcci maJ dcwder in Figure 6-83. Draw a liming d iagram. shOwing each output in the proper rel:lIiollshi p wi th the o i/lers and with the inputs.
PROBLEMS
FIGURE 6 - &]
•
359
BCD/DEC U
...,
2
A, A, I
A,
I
n
I
I
, 4
, 4
A,
L...!L...!'---JM L-'---'----'----.!...
3
2
6 J
8 9
7411C42
20. A 7-segmcnt decodcr/drivcr drh'cs thc di splay in I1gure 6-84. Ifthc WaVcfOnllS i1re applicd as indicated. detcrminc the sequence of digiL" tha t apPCi1rs on the display.
FIGURE 6 - &4
A, AI
A,
nCDn -seg
,
,
,
,,, ,,--
--+----rl ,
.-
,
, ,
A,
A"
I
"h
A, A, A,
2
c
4
d
,
8
,f SECTION 6-6
,-,,=,
Encoders 21. For the dccimll l-to-l3CD encoder logic of Figure 6-38. assu me that the 9 inputllfKIthc 3 input are both HIGH. What is the ou tput cnde? Is it a va lid BCD (842 1) code'! 22. A 741-1CI 47 cncodcrhas LOW levels on pins 2. 5. and 12. Whllt BCD code appc&rs nn the outputs i f all the Ql her inputs llre ('IIGI-I'I
SECTION 6 - 7
Code Converters 23. Convcrt the following decimal numbe rs 10 BCD and then to binllry.
(a) 2
(b) 8
(c) 13
(d) 26
(e) 33
24. Show Ihc logic required to convcrt a IO-bit binllry number 10 Gray code. and usc that logic to C()(}vcl1 thc following binary numbers to Gray code:
(a ) 1010101010
(b) 1111 100000
(c)
()()()(X)() I
I I0
(d) 111 11111 11
25. Show the logic required to corl\"cn a IO-bit GnlY code \\) binary. and usc that logic to convcrt Ihe following GnlY code words 10 binary:
(a) 101
(b) 0011001100
(c) l lllOOOl l1
(d) OOXIDXXlI
360
•
FUNCTIONS OF COMBINATIONAL lOGI C
SECTION 6-8
Multiplexers (Data Selectors) 2(,. For the rnulliplexer in Figure 6-85. determine the ou tpu t for the foll owin~ input slates: ~=QD, = ' . ~ = I . ~ = Q~ = I .~ = Q
FIGURE 6 - IIS
/'.'lUX
S" S,
U"
0) , t
G~
0
f),
f),
2
0,
J
27. If the dolla-sclect in puls to the multiplexer in Figure 6--&5 arc scqucm:e<1 as show n by the waveforms in fi gure 6--86. dete rmine the output waveform with the data inpuls specified in Proble m 26. FIGURE 6 - 16
"' -----:---! s, 28. 11lC waveforms in Fig ure 6-87 ;lTC observed on the inpuTs of a 74LS I 5 I 8-input mUltiplexer, Sketch the Y OUtput wavcfonn. FIGURE 6 - 87
'"
S,
Setecl illp"h
S, £nG/JI..
ro o
f),
/.}1
1)"1,,
rnpu"
j
D,
l
U,
f),
D,
D,
SECTION 6 - 9
Demultiplexers 29. [)cvclop the 100ailiming diagra m (inpllts and ou tplll~) for a 74HC 154 u:-ed in a
PROBLEMS
SECTION 6-10
•
361
Parity Gener.lltors/Checken: 30. ' I"e wavefonns in Figure 6-88 arc applied to Ihe 4-bit parity logic. Determi ne Ihe ou tput waveform in proper relation to the inputs. For !tIlW many bit times docs even parity occur. and how is il indicllled,! The timing diagram includes eight bit timcs.
FIGUR E 6 - 81
l3il lime
31. [)clcnnine thc 1: E ~·en and thc r Odd OUtputs of II 74LS280 9·bil parity gcner-.llor/checker fOT the inpuls in Figure 6-89. Refer 10 the function table in Figure 6-59.
FIGURE 6 - 89
Ai A,
,,
A,
i,, :
A,. A,
SECTION 6-11
,
Troubleshooting 32. The full-ocIdcr in Figure 6-90 is tested llIuler all inplll conditions with Inc input wavcforms shown. From your observation of Ihc r and C"", wa\'eforms. is il opcr-.lting properly. and if not. what is thc moslli kc ly faul t?
A
Ii
c. E C~
FIGURE 6 - 90
I i,,
,,
,,
, ~
L
-
A
-
B
-
Ci...
qCw -
362
•
FUNCTIONS OF COMBINATI O NAL lOGIC
33. List the possible faults for each decodcr/display in Figure 6-1)1 .
BCI)I7-seg
BCDn-M:g
I U
0 1-
I 2 4 8
"b
,
,
f
,.)
":,
0 0 0 I
, 4 8
"b c ,/
" f
,
,-,
,-,,:,
BCDn ·seg
L'
"b
,
U
c
2
I I
4
U
8
, f K
,oj
(b)
fiGURE 6 - 91
34. Develop a syste matic test proced ure to chec k. OU t the comple te C>pCrnti on of thl.' k.cyt>oard encodcr in Figure 6-42.
35. You an: tCStillg a BCD-IO- binary conve rter con~i sti l1g of 4-bil addcn. as shown in Figure 6-92. Fi[!;t verify [hat the circuit L'On,'ert s BCD to binary. The tel;t proceduTC call ~ for applying BCD nu mbers in scquent ial order beginning with 010 and chec k.ing for tnc COITCct binary ou tput. What ~ymptom or ~ymptoms wi ll appcar on the binary outputs in the c,'em of each of the following faults'! For what BCD lIumhc r i~ each fau h jir.\·/ detected'! (a) ' llIe A I input is opcn (top adder).
(b) The C"", I!". opc: n (lOp adder,. (e) 'Ille
r.. outpUl is shorted to ground (lOp 3dderl.
(d) The 32 output is shorted to ground (bot tom adder), FIGURE 6 - 92
l
4 3 2 [
4 3 2 I
B
A
'--v-----' '--v-----'
C_
o
c.."
,
~
432 1
,
A
~
4 3 2 I
7·"il "il'W) output
36. For the display multiplcxi ng sys tem in Figure 6-52, determinc Thc most likel y cause or causes for each of lhe following sy mptoms: (a) 'Ihe B·digit (MS D) display docs notlUm on al all. (b) Neither 7-scgmenl display IUms on.
PROB LEMS
•
363
(c) The I-seg ment of both di splay~ appears 10 be on HIIII IC tinle. (d) n lere is a "bible flicker on the di~pl ays. 37. Develop a SYslematic proced ure to fully test the 74LS 151 dllta selector Ie. 38. During the testing of the data tran~mission syste m in Figure 6-60, 11 code is appl ied 10 the Do through Dr, in put!> that contai ns itn odd number of Is. A single bit error is (!elibcratcly introd uccd on the serial dllta Irdllsmission line betwccn the MUX and the DEMUX, bu t tbe system docs nOI indicate an error ( CJTOf out put = 0), After some inves ti ga tIon. you check the inptlb to the even parity checker and find that Do through D~ cOntH;n an even number of 1s. as you \\Ould expccl. Abo, you lind that the D, pHrity bit is a I. Whlll are the po&ible reasons for the ~ystem nOl indicating the error? 39. In general, describe how you wou ld fully lest the data transmission systcm in Figure f>-6O, and specify a method for the int roduction of pari ty errors.
Digital System Application 40. Tbe light output logic clIn be imp lemented in the system application wi th fixed -function logic using a 741-')08 with the AND gHtcs operating
Special Design Problems 42. Modify the des ign of the 7-segment displllY mul tiplexing system in Figure 6-52 to accommodate two additional digits. 43. Usi ng 'Ia ble 6-2, write the SOP ex pressiolls for the I: and C"", of a full-adocr. Use a Kamaugh map to minimi7..c the expressions anu then implement them with invencrs ~nd AND-OR logic. Show how YOII can replace the AND-OR logic with 74LS 151 dala selectors. 44. Implement the logic function specified in 'litble 6- 12 by usin g a 74L,) 15 1 data selector.
TABLE 6 - 12
Al
Al
INPUTS A1
Ao
OUTPUT Y
364
•
FUNCTIONS OF COMBINATIONAL lOGIC
45. Using twO of the 6-posilion adder modu les from Figure 6--14, design 3 12. po.o;ition velting sy~tel1l .
46. The mhler block in the tab let·counting and t'Om rol system in Figure 6-93 pctforms lhe aUdition of the g·b it binary number from the coun ter and the 16-bit binary number from Register B. The resul t from the adder goe.~ bilCk into Register B. Usc 74LS2~3s to implement this function and draw a complete logic diagram including pin numbers. Refer to Chapler J system application to review the operat ion. 47. Usc 74HO!Ss to implement the Com parator block in the lablet cuunting an d cunlrol sy~tcm in Figure 6-93 and draw a complele log k diagram including pin numbers. The comparator compm'Cs the 8-bil binary number (actua lly only SC\'cn bits are required) from thc BCD-tobinary converter with the 8-bil binary number from lhe coo mer.
48. Two BCD-lo-7· segmem decoders are used in the tablet-counting and contro l system in Figure 6- 93. One is requ ired to drive the 2-digil tohlelJ//)(JII/e display an d the oth er to drive the 5·
rnrnm E"""'" mmW . • rnlIl ~ IIl Worn """'''' ,
~
41:>1t" _~.~
[A,\:lmal 10 BCD
.
I)""d"
..,,...+
Rc~iSlcr A
,. 2-digit BCD
nn
A
uu
BCD 10 7-seg
aCO in blIlH!)'
I
~ .
0
j1
.
-
111>11"
.
•
TOIal l
nnnnn
uuuuu Addcr L A
Coumer R·bil bilUlT)'
~
r+ "
I(,bit"
-
C
~ ,
t
Regi ~lcr B tlrbil binary
DeCoder
,
B
Binary BCD
BCD to 7·,;eg
'0
M ux t6
t"t~
-
t Switching !;(:(llJencc con lrol inpul
FIGURE 6- 93
.19, -l1le encoder shown in the system bloc k diagram of Figure 6-93 cm:ooes each decimal key clo~ure and converts it to BCD. Usc a 74HC l47 to implcment this function an
ANSWERS
•
365
50. -OIC system in Figure 6-93 requires two code converten;. The BCD-to-binary conve rter changes the 2-digit BCD nu mber in Reg isler A 10 an 8-bi t binary code (actually only 7 bits are required because Ihe MSG is a lways 0). Use appropriate Ie code COIll'Crlen; to implement the BCD-to-binary converter fuoe lion and draw a com plete logic diagram including pin numbers.
MULnSIM TROUBLESHOOTING PRACTICE 51. Open fil e P06-51 and lest the logic circuit to delennine if there is a fault. iflhere is a faul l. iden ti fy il if possible.
52. Open file P06-52 and test the logic circuillO determi ne if there is a fault. If there is a faull, identify it ifpossible.
53. Open file P06-53 and lest Ihe logic eireuilto detelmine if th ere is a fault. If there is a fau ll. identify il if possible. 54. Open file P06-54 and test the logic circui t lOdetcrmine if there is a fault. If there is a fault, ident ify iI if possible.
SECTION REVIEWS SECTION 6 - 1
Basic Adders I. (a)!: = I. C,.." = 0
(b) £ = O,C"",,= O
(e) £ = I.C.... = O
(d ) !: = O.C".= I
2. £ = ] . C"",= 1
SECTION 6 - 2
Parallel Binary Adders I. C... ~~rzr., = 11001
2. 'l1l1"Ce 74LS283s are required to add two IO-hi t numbers.
SECTION 6 - 3
Ripple Carry \'S. Look-Ahead Carry Adders 1_
C~ = O, Cp=
I
2. (.-:"' = 1
SECTION 6 - 4
Comparators I. 11>8 = I.A <8 = O.A = 8 = Owhen A = 101 1 andlJ = 1010
2. Righ t compam.tor: pin 7: A < 8 = I; pin 6: A - B = 0; pin 5: A > B = 0 left comparmor: pin 7: A < n = 0; pin 6: A =
SECTION 6 - 5
fj ,.. 0;
pin 5: A > 8 = I
Decoders I. Output 5 is active when 101
i~
on the inpUls.
2. Four 74HC I54s arc used to decode a 6-bit binary numlkr. 3. Active-LOW output drives a oornrnon-cathode LED display.
SECTION 6 - 6
Encoders I. (ll) Ao= 1. II ,= I. A2 = 0.II J = I
(b) No, this is nm: a valid nCD code. (el Only one input can he actinl for a va lid output.
2. (a) A) = O,A2= I.A,= r. Ao= I (b) The OUtput is 0 111 , which is the comp lemen t of 1000 (8).
366
•
FUNCTIONS OF COMBINATIONAL lOGIC
SECTION 6 - 7
Code Converters I. HXXXJIO I (BCD) "" 1O I01Oi l 2. An S-bit binary-to-Gray converter consists of scven that in Figure 6-43.
SECTION 6 - 8
e~clusi\'e-OR
Bates in an arrangemem like
Multiplexers (Data Selectors) I. Thc output is O. 2. (II) 74LS 157: Quad 2-input data selector (b) 74LS 15 1: II-input data selector 3. The data output al temutcs between LOW and HIGH as the data-selcct in puts seque nce through th e binary slates. 4. (II) The 74HC I57 mu lti plexes the tWO BCD codes to the 7-segmen t decoder. dccode~
(b) T he 74LS47
the BCD to energize the display.
(e) The 74LS 139 enables the 7-scgme11l dbplays ahenlmcl y.
SECTION 6 - 9
Demultiplexers 1. II deroder can be used as a Illulliple)(er by using the inpu t lines for data scloclion and an Enable li ne for data input. 2. 1bc outpull. arc aU HIGH
SECTION 6 - 10
SECTION 6-11
e~ccpt J), ~
which is LOW.
Parity Generators/Chec:kers I. (11) Even parity: 1 110100
(b) Even p1tri ty: 00 1100011
2. (11) Odd pari ty: 1 101010 1
[bl Odd parity: 11 00000 1
3. (II) Code is correct, four Is.
(b) Code is in error. seven Is
Troubleshooting I. II glitch is a vcry short-uumti oil voltage spike (usually unwanted). 2. GlitchCl; arc caused by transition stales. 3. Strolx is the enabling of a device for a specified period of lime whe n the device is not in tr.msition.
RElATED PROBLEMS FOR EXAMPLES
r = l.C<>JI ""
6-1
6-3 lOll
+
-
:}' . , = { ;} ,, " -
-
-
c,
C,
-
-
fff-
r-
I , r~
=
I
6--4 See Figure 6-94.
,
,
FIGURE 6 - 94
r
6-2 r , = o, r ! = o, r l =
I
1010 "" 1010 1
-
}
-
:} {
,,
Co
"
c,
-
,
:}• . = {= =} -
-
,
-
-
c,
C,
ANSWERS
6-S Sec Figure 6-95.
FIGURE 6-95
A/, '" I _-"c---~
n" '" 0 - --tL..-' ~ I '" 0
- -41C---'
n, '" I - --oc-/ 6-6 A>fi = O.A=fi=O,A
6-7 See Hgure 6-96.
r...... ... r"... " ...... ...}''''... ..,.. .,.
FIGURE 6 - 96
= =
H'
o
,
.,. h'
=} -
-
,- -
••• .«
}
1= 1=] . o.~, 1= 1= .., 1= •H'•• H' 1= h-' •H'•• 1= h ' e1= 1= 1 =} 1 =]II1fiPY_ odd
6-8 See Figure 6-97. 6-9 Output 22
FIGURE 6 - 91
x
6-10 See Figure 6-98.
H +---+=+-+-+-+--iur--i-+
, =:~~>--+-,-+-;6 C-
u-
-:-i
--+-;--i--;=U--:",,
7
8
-'---:-'-"':""';ur-";",,,,;--+--;.
9
.......-'--'---'=--'---'-iU
•
367
368
•
FUNCTIONS OF COMBINATIONAL LOGIC
6- 11 A ll inputs LOW: Ao= A ll
inpuL~
O. AI '"
I .A~= I.A)= O
I-II GH: All OU lputs HIGH .
6-12 BCD OIlXXXXJI
I
----->':
LI 00000oo I L-_ _---> OOlOlilOO
Bi nary
0010 100 1
40 41
6-13 $c"en CKdus1\·c·OR gatcs 6-14 See Figure 6-99.
FIGURE 6 - 99
6-15 Drj. 5l = 0. 52 = 0,51 = O.So= 0 D~:
5] - 0.52 '" 1. 5 1 '" O.Sy '" 0 0.51 = O. .\, = 0 D I): 51 = I , S2 "" 1, 5 1 = O,So = I D~: 5l = 1.5~ =
6-16 St:e
FIGURE 6 _ 100
.."
~
'. "
Figu~
6-HJO.
MUX
'" :}G~
,,
.~ v
,,.' ,. ~
74LS I)1
6-17 Sec Figure 6-101. FlGUR.E 6 _ 101
I~V
'.
;\ll'X
~
"'.'" :}OJ , ,,, ,, ,
r _
";,A""",.A.A,,,,,,,, tA ,..1;i ..... · A""A ,AtAfl • "",;i "'" • A ,A.A"",
.. "l"~"" " ")Al A"",
ANSWERS
6-18 Sec t'-l gure 6-102.
FIGUR E ' - t02
SELF-TEST I. (a)
2. (b)
9. (a)
lV. (d)
~c)
4. (a)
11 . (c)
12. (r)
3.
s.
(d)
6. (b)
7. (c)
8. (b)
•
369
LA C ES# P-FLOPS TIMERS CHAPTER OUTLINE
CHAPTER OB)ECTIVES
7- 1
latches
Ule logic /}'teJ to construct wlic latch~
7- 2
Edge-Triggered Flip- Flopi
Explain the d ifference between an 5-R Iiltch
7- 3
Flip-Flop Operating Characteristics
7- 4
flip-Flop Applications
7-5
One-Shot!
7-6 7-7
Tfle 555 TImer
Troubleshooting
IIIl
Digital System Applkation
~ognize
the difference between a latch and a flip-flop
Explilin how S-R. D. and J-K flip-flops d iffer
UndcrstiJnd the lignir.atnce of propag
Expl"in h
Conned: a 555 timer to OpelOte as either an astoble mu ltivibrator or" o nc-shot
Troubleshoot b.uic flip-flop cirwits
KEY TERMS
Late"
Preset
Bisbble
Clear
5ET
• Prop"g"tion de lay time
RESET
Set-up time
Clock
Hold time
Edge-triggeret:l f11-p-f1op
Power dissipation
Synchronous
One-shot
o flip-flop
Monostable
)-K flip-flop
Timer
Toggle
~bble
INTRODUCTION
This chapter begim a study of the fundamenbb of sequential logic. Bistable. monosbble. "nd asbble logic devices called multivib'otorJ are covered. Two categories of bist"ble devices are the I"tch and the flip-flop. Bistable devices have two stable sbtes. Gliled SET and RESET; they Gin retain either of these states indefinitely, making them useful as storage devices. The ba~c difference between latches and flip-flops is tIle way in which they are changed from one state to the other. The flip-flop ft a basic building block for counters, registers, and other ~quentia l control logic and is used in certain types of memories. The monostable multivibrator. commonly known as the one-shot, has only one stable state. A one-shot produces a single control'ed- width pulse when activated or triggered. The astable multlvibr"tor has no stable d:.,te and is used primarily as an oscillator, which is " self-susbined waveform generator. Pulse oscillators are used "s the sourceS for timing wavefonns in digital ~tems. fiXED-fUNCTION LOGIC DEVICES
74XX74
74XX279
74XX122
555
74121
7'lXX75
74XXl 12 •••
DIGITAL SYSTEM APPLICATION PREVIEW
The Digital System Application continues \.\lith the traffic light control system from Chapter 6. The focus in this chapter is the timing circuit portion of the ¥tem that produces the dock, the long time interval fo' the red and green lights, and the short time interval for the Glution light The dock is uled al the basic ~tem timing signal for adv.,ncing the sequential logic through its states. The sequential logiC will be developed in Chapter 8.
,I'M
~tUdy aids for this chapter are available at !http://\.\IW''#.prenharLcom/floyd v lslr rHI: COMPAN I ON
wlii'i'iTl-
371
372
•
7-1
LATCHES, FLI P-FLOPS, AND TIMERS
LATCHES The latch is a type of temporary storage device that has two stable states (bistable) and is normally placed in a category separate from that of flip-fl ops. Latches are similar to flip-flops because they are bistable devices that can reside in either of two states using a feedback arrangement, in which the outputs are connected back to the opposite inputs. The main difference between latche.... and flip-Il ops is in the mcthod used for changing their state. Afler completing this section, you should be able to • EXplain thc operation of a basic S-R latch . Explain thc operation of a gated S-R latch . Explain thc opcnnion of a gated D latch . Implcmcnt an S-R or D latch with logic gates . Describe the 74LS279 and 74LS75 quad latchcs
The S- R (SET-RESET) Latch
1M3-1M''' iiiioW- t ! ! Latches are sometimes Uled in
! ("omputer l}'Items (or multiple)Cing
Idata onto a bui. f or example, data being input to a compuber from an external loun;e have to lhare tl1e oota bui witl1 data fro m other !.OI.m:es. \\!hen the data bul be("omes unavailable to the ! extemal source, the existing data mult be tempor"iJrily stored, lind liltches placed between tile external source ilnd the dilta bul may be used to do tl1is . \\!hen the ! data brn il UI"\aV.1il.1ble to the I extetn
A latch is a type of bistable logic device or multivibrator. An active-HIGH input S-R (SETRESET) latch is f0!!'l~ with two cross-coupled NOR gates. as shown in Figure 7- l(a); an active-LOW input S-R latch is formed with IwO cross-couplcd NAND gates, as shown in Figure 7- 1(b). Notice that the output of cach gate is conneclcd to an input of the opposite gatc. This produces the rcgcnemtivc feedback that is characteristic of all latches and flip-flops.
I
Q
I
., _--LY----- o
!
I I
I I
(II) Active-HIGH input S-R latch
o (h) Acti\ll-LOW illput S-R
1~ll:h
FIGURE 1 - 1
Two veniom o( SET-RESET (S- R) Ja tchCl. Open fole f07-O l a nd verify tile operation of both l.1tches.
To explain the operation of the latch, we will usc the NAND gate S-R latch in Figure 7- 1(b). This latch is redrawn in Figure 7- 2 with thc nc~ativc.:..OR equivalent symbols used fOl' the NAND gates. This is done because LOW~ on t ~ Sand R lines an- tre activ~ing inputs. Thc latch in Figure 7- 2 ha.. two inputs. Sand R. and two outputs, Q and Q. Let 's start by assuming that both inputs and th~Q output are HIGH . Since thc Q output is connectcd back to un input of gate C 2• and the R input is HIGH, the output of G2 must be Law. This LOW output il1. couplcd back 10 an input of gate C t , ensuring that iL~ output is HIGH . FIGURE 1-2
NegatiYe-OR 1?
'-1(b).
When the Q output is HIGH, the latch is in the SET statc. It will remain in this statc indefinitely until ~ LOW is temporarily applied to the R input. With a LOW on the R input and a HIGH on S. the OUIPUI of gatc C 2 is forced HIGH. This HIGH Oil the QOUlput is coupled back to an input of Ct. and since the Sinput is HIGH, thcoulput ofG! goes Law. This
LATCH ES
LOW o n the Q OUl pUI is then coupled back to an in put of G z, e nsuring that the Q output remains HIGH even when the LOW on the R input is removed. When the Q o utpUi is LOW, the latch is in the RESET s!..ate. Now the latch remains indefini tely in the RESET state until a LOW is applied to the S input. In nonnal operation. Ihe outputs of a latc h arc always complements of each other.
•
373
A latch can (elide in e ither or ib two states, SET o r RESET.
When Q is HIGH, Q io; LOW, and when Q is LOW, Q is HIGH. SET means that the Q output is
An invalid condition in_the o~fation of an ar.:ti ve-LOW input S-R latch occur!> when LOWs are appl ied to both S and R a t the san~ time. As long as the LOW levels are simultaneous ly held on the inputs, both the Q and Q outputs are forced HIGH, thus violating the basic complementary operaljon of the OUi pUiS. Also, if the LOWs arc released s imu ltaneollsly, both o utputs will attempt to go LOW. Since there is always some s mall difference in the propagation delay lime of the gates, one of the gates will dominate in ils trans ition to the LOW o utput Sla te. This, in turn, fo rces the outpu t of the s lower gate 10 remain HIGH. In this s ituatio n. you cannot reliably pred ict the next state of the latch. Figure 7- 3 illustrates the active-LOW input S-R latc h operation f\T each of lhe four possible combinations of levels o n the input<;. (The first three combinations are valid, but the la<;t is not.) Table7- 1 summarizes the logic operation in truth table foml. Operation oft hc ac1i\'e-HIGH input NOR gale latch in figure 7- I(a) is similar but requires the usc of opposite logic levels. MOn""'nlllr)
,
I
RESET means that the Q output is lOW.
tOW
: U "-S;:J~~J ~ , ---
~S--;:::L~)-I-'!O ~ l'~lpuls make 1I<11ls ili oils
oU
HIGH_
whet1
No ttallsiti01S
S g<)e!; LOW alld remain in $:Ime I
'~:;j@)>--L'!
H
Q
latc h is
_
staTe after S bIle k HIGH.
~ 1:..~~S
ah'ead~'
SET.
~~
G,
(HIG!!)
l.:itC'h qart!. out SEr (Q '" I).
L!lch Slart.' nut J.!ESET (0 '= 01 .
(3) 1\"0 PQ$sibitities for the SET operati on
,~S~[S>I.EO ~ 1:-----
Outputs make lra nsitions ... hen Ii Soc» LOW a.1(I remain
'U "
IJ
_
in same state after Ii
(}
goes bock HIGH .
,"S;~S)-i£Q
~ "i_cL~.r--Q :O~"OM U
o' ~
oc,'"
because laleh i~
already RESET I...,t<:h
,1m,. oul SfT(Q :
II.
(b) Two possihi ti lie)i
1..1I1ch ,liUh Ul.1l RESEr (Q '" Ill. (01'
the RESET op"r~ti<)n
S ~Q OulpttlSdo ,~ """""!lot c hange
Q' ~ OulpU I stales
are unL't't1ai n "hen inpul LOW~ go back HIGH .
Mate. Latch remains SET i f
.'::~~>--l_Q~ ".. renmilL' pn:vioosJ~' SEr and Rr,sET if
I
~R
HIGHS on both inpuh (c) N.,.chanj;e
~~
previomly RESEr.
~'Qnd ition
Simliltane"u~
(d) 1""" lid condilion
fIGURE 7-3
The three modes of basic S-R '
I.OW. fin
t'(l(h
input~
37i
•
lATCHES, FLIP- FLOPS, AND TlMER.S
TABLE 1 - 1
Trut h table for an active-l OW input S-Rr;:loch.
INPUTS
5
OUTPUTS
if
Q
Q
NC
NC
o
COMMENTS No change. Latc h remains in
o o
o
present SlllIe.
Latch SET.
o
Latch RESET.
o
Invalid conditil)ll
Logic symbols for bmh the activc-H IG H input and the activc-LOW input latchcs are shown in Figurc 7.-4. FIGURE 1-4
l ogic I)OTIbok for the S-R ;:lnd S-R liItch.
s
Q
R
Q
(a) AClive- HIGH i!lplll
S-R b ."h
s
Q
H
(b)
Q
~,:!i\IC-LOW
input
S-R tmch
Examplc 7- 1 illustratcs how an activc-LOW input S-R latch responds to conditions on ils inputs. LOW Icvels are pulsed '2,11 eachJnpul in a certain sequence and the resulting Q output wavcfunn is ob.~crved . TIle S = D. R = 0 ~onditiun is "voided bcC
I
EXAMPLE 7 1
If the S and R waveforms in Figure 7- 5(a) are applicd to thc inputs ofthc latch in Figure 7-4(b). detcrmine the waveform that will be observed on thc Q outpu!. Assume that Q is initially LOW
I
,, ,
f-
(a)
R
(b)
Q
,, , ,, ,
Wi ,
1 ' ----]
~
L-_-'---_---'
FIGURE 1-5
Solution Related Problem -
See Figure 7- 5(b). Dctcnn ine the Q output of an active-H IGH input S-R latch i f thc waveforms in Figurc 7- 5(a) arc inverted and applicd 10 the inputs. t Answcrs arc at Ihe end of the chapter.
LATCHES
•
An Application The Latch as a Contact- BOUilce Eliminator A gooo example of an application of an S-R latch is in the elimination of mechanical switch contact "bounce." When the pole o f a switch strikes the Conlact upon swilCh closure, il physit:ally vibrates or bounces several times before fina lly making a solid contact Allhough Ihese bounces arc very short in duration, they produce voltage spikes that arc often not acceptable in a digital system. This situation is illustrated in Figure 7--6(a).
+v'"
R,
R,
2
-
S
l
R
s
Q
"
Pos;t;nn I 10 2
1',,,,i1 'on 2 to I
ttl) Contact-bou nce ~timina t"r eirc" il
(a) Switch CQlltoct bou nce FIGURE 7-6
The
S-I? [atdl usc.:! to eliminate switch con tact bounce.
An S-R lalch can be lIsed to eliminate the effects of~witch bounce as shown in Figure 7--6(b). The switch is nonllally in posi ti o~ I, kccping the R input LOW and the latch RESET. WheE the switch is thrown to position 2, R goes I!:'GH because of the pull-up resistor to I'ec, and S goes LOW on the first contact. Although S remains LOW for only a vely shOit time £cfore the switch bounces, this is sufficient to set the latch. Any funher voltage spikes on the S input due to switch bounce do not afft!cl the latch, and it remains SET Notice that (he Q OUlput of the latch provides a clean transition from LOW to HIGH, thus eliminating the voltage spikes caused by contact bounce. Similarly, a clean transition frolll HIGH to LOW is made when the switch is thrown back to position I.
THE 7415279 SET-RESET LATCH The 74LS279 is a quat! S-R latch represented by the logic diagram of Figure 7-7(a) and the pin diagram in parI (b), Notice that two of the latches each have lWO S input... (2) (3)
(1 1
lSI
(41
152
1Q
1" (6)
(5) (II )
( 12) ( 10 )
( 15) ( 14)
2S
J7)
4S
4R
4Q
352
lSI
IS2
to
2R
3R
3Q
2Q
2" 351
(9)
3S2
]Q
3.
4S
(13 )
4R
(a) L.ogi..- diagram
FIGURE 7 - 7
The 7415Z79 quad S-I? latch.
tR
(1:1) Pi n di agram
2S
2Q GND
37 S
376
•
LATCHES, fli P-FLOPS, AND TIMERS
The Gated S-R latch A gated latch requires an enable input. EN(G is also used todcsignate an enable input). The JoSic diaSr
FIGURE 1 - 8
A gated 5-R latch.
Q
(a) Logic diagram
s
Q
R
Q
(b) l..clgic symbol
Determine the Q out put waveform if the inputs shown in Figure 7- 9(a) are applied to a gated S-R latch that is initially RESET.
s~ R
(0)
,, ,, ,
I
EN ~ ,, ,,
(b)
Q~
I L ,,
,, ,
,,
~
,, ,
H
r-
FIGURE 1 - 9
SolUtiOll
The Q waveform is shown in Figure 7-9(b). When S is HIGH and R is LOW, a HIGH on the EN input sets the latch. When S is LOW and R is !-UGH. a HIGH on the EN input resets the latch.
Related Problem
Detemline the Q output of a gated S-R latch if the Sand R inputs in Figure 7-9(a) are inverted.
The Gated 0 Latch Another type of sated latch is called the D latch. It d iffers from the S-R latch because it has on ly one input in add ition to EN. Th is input is called the D (data) inpul. Figure 7- 10 contai ns a log ic d iagram and logic symbol of a D latch. When the D input is HJGH and the EN input is HIGH. the latch will set. When the D input is LOW and EN is HIGH. the latch will reset. Stated another way, the output Q fol lows the input D when EN is HI GH.
LATCHES
•
377
FIGURE 7 - 10
o
Q
" -+--+
Q
A gated D I.. ten.
EN Q
Q (a) logk diugrJm
I
(b) Logic sy mbol
EXAMPLE 1-3
Determine the Q output wavcfoml if the inputs shown in Figure 7- 11 (a) are applied 10 a galed D latch. which is initially RESET.
,, , ,,
o Co,
EN
Cb,
Q
---1LJL1lL----1
fiGURE 1 - 11
Solution
ReWted Problem
The Q wavcfoml is shown in Figure 7- II (b). When D is HIGH and EN is HIGH. Q goes HIGH. When D is LOW and EN is HIGH, Q goes LOW. When EN is LOW. the slate of the latch is not affected by the D input. Determine the Q output of the gated 0 latch if the D input in Figure 7- 11(a) is invcncd.
THE 74L575 D LATCH An example of a gated 0 latch is the 74LS75 reprerellte<1 by the logic symbol in Figure 7- 12(01). This de"icc has four l alc he~. Not ice that each active-HIGH EN input is shared by two latches and is designated a<; a control input (C), The truth table ro r each latch is shown in Figure 7- 12(b). The X in [he [ruth table represents a ',(lon't care" condition. In this case, when the EN input is LOW, it does not matter what the D input is because the outputs arc unaffected and remain in their prior stales. I/)
(2)
eN ~ C3l
!f)
.11J
bV
'"
(~)
C6,
~ (7)
'" FIGURE 7 - 12
(1 6)
In
CC
n 2f)
3/J CO
C4 4D
Logic symbol
10
cn ( 15)
The 74LS75 quiKI goted D latcho .
10
(t4)
Inputs D EN
ItO)
o
~
x
I
Outputs Q
Q
o
1
Qo
Qu
o u
I Comments RESET
SET No change
(9)
(8)
N",~: Qo j, Ihe prinroul pul le'·e l before lbc ;ndk 8l<"tl ,npUI ooncli l;on.' were e5lnbli.,ht."tl.
(b) Tnu h lab te (each
t~lch)
378
_
LATCHES,
F lI P~FLOPS,
I
SECTION 7-1 REVIEW Arnwers are at the end of the chapter.
7-2
AND TIMERS
1. list three types of latches. 2. Develop the truth table for the active-H IGH input S-R latch in Figure 7- 1(a).
3_
Whati~the
Qoutputofa D latchwflenfN = 1 and D = 17
EDGE-TRIGGERED FLIP-FLOPS Flip-flops are synchronous bistable devices, also known as bistabfe fIIull;l'ibrllIOn;. In this case, the term n"lIchronOlls means that the output changes state on ly at a specified poi nt on the triggering input called the clock (elK), which is designmed as a control input, C; that is, changes in the output occur in ~ynchroni zatio n with the clock . After completi ng this section, you should be able
10
- Define dock - Define eclge-lriggerecfj1ip -fiop - Explain the d ifference between a flip-nop and a latch - Identify an edge~ lri ggered nip~nop hy its logic ~ymbo l _ Discus.~ the difference between a posi ti ve and a negative edge-triggered flip -nap _ Discuss and compare the operation o f S-R, D, and J ~ K edge-triggered nip-nops and explain the differences in their tnlth tables. _ Discuss the asynChronous inputs o f a nip-flop - Describe the 74AHC74 and the 74HC I 12 flip-flops
The dynamic input indicator [>
means the flip-flop changes state only on the edge of a clock puise.
An cdgC-lriggcn.>d nip-nop changes state either at the positive edge (rising edge) or at the negative edge (fall ing edge) of the clock pulse and is sensitive to its inputs on ly at th is lransition of the clock . Three types of edge~triggered fli p-naps are covered in Ihis section : S~ R. D. and 1-K. Although the S-R n ip-flop is nOI available in Ie for m, it is the ba~ i s for Ehe 0 and J ~ K nip-naps. The logic symbols for all of these nip-flops are shown in Figure 7- 13. Notice that each type can be either positive ed2e~triggered (no bubble at C input) or negative edge-triggered (bubble at C input). The key to idenlifying an edgetriggered flip~no p by its logic symbol is the small trian£le inside the block at the clock (c) input. This triangle is called the c~m{/mic iI/pm ;IIdicafOl:
FIGURE 7-13
f),,,o"'"'' ;''''''' IrI<.lll:~I"r
Edge-triggered flip-flop logic symbols (top: positive edgetriggered; botto m: negative edgebiggered).
S
Q
-
'c Q
J
S
Q
I)
Q
- -c
K
Q
J
Q
--c Q
(b) 0
Q
C
P-- Q
R (;I) S-R
- Q
C
R
- -c
-
D
K
ee) J-K
Q
EDGE-TRIGGERED FLIP-flOPS
•
379
The Edge-Triggered 5-R Flip- Flop The Sand R inputs oflhe S-R tlill-flop arc called sYllchl"OIlOUS inputs because data on these inputs are trnnsfelTed to the flip-flap's outpu t only on the triggering edge of the clock pulse. When S is HIGH and R is LOW. the Qoutput goes HIGH on lhe triggeringcdgeoft.hedock pulse. and lhe nip-flop is SET. When S is LOW and R is HIGH. the Q OUiput goes LOW on the triggering edge of the clock pulse, and the nip-flop is RESET. When both Sand Rare LOW, the output does not change from its prior state. An invalid condition exists when both Sand R arc HIGH. This basic operation of a posi ti ve edge-triggered flip-flop is il lustrated in Figure 7- 14, and Table 7-2 is the truth table for this type of flip-flop. Remember.lheflifJ-flofJ call1lOf change sUlIe except on Ihe triggering edge of (I clock pulse. The Sand R inputs can be changed at any lime when the clock input is LOW or HIGH (exc(:pt for a very short interval around the triggering tntnsition of the clock) without affecting the output.
o o'F
s el K
JL
JL
'0
c
'0
'0
(a) S ", I, R '" 0 nip-fiop SETS 0 11 posit ive d oc k ed ge. ( If already SET , it .-email'S SET.)
'0
C
,--
Q
R
0
:,L
Q
s
0
R
Q
(b) S . O. R ", I fii p-fiop RESETS On po>:; ti,'e
ctoc k edgc. (If ahead )' RESET. it remaills RESET.,
An 5-R flip-flop a nnot have both 5 and R inpub HIGH at the IoilIme time.
r of memory il the Static I Random heelS Memory o r SRAM. I which ,,-e. flip-flops for the I Ito~ge ceUI beciluse a flip- flop wi ll retain either of it!; two ILlte! I indefinitely 1101 long aol de power ;1 .Jpplied, tnul the te rm static. ThO! type of memory il cI,mified al.J voWtlle memory because ao ll the ltored dati!
turned off. Another type of I
s
o
JL
r C
- -l>c o
memory. the Dynaomic Random hcCS\ Memoryor DRAM, uses the billie ItOI'i)g<: clemen t
,)1
Q
R
(c) S ~ O. R - 0 nip-fiop doe:; nOI challgc. (tf SET, it remains SET: if RESET, it remai ns RESET.) FIGURE 1 - 14 Ope~tion
of 110 polit:ivc edge-triggered S-R flip-flop. TABLE 1 - 2
S
INPUTS R
CLK
Q
Q
COMMENTS
0
0
X
Q"
Qo
No change
0
0
T T
0
OUTPUTS
i
.,
RESET
0
SET
?
Invalid
t "" clock lransilioo l.OW 10 HtGH X - ill"C1evant (""
Tbe operation and trulh table for a negative edge-triggered S-R flip-flop are the same as those for a positive edge-triggere<1 device except that the falling edge o f the clock pulse is the triggering edge.
Truth t
380
•
LATC HES, FLIP-FLOPS, AND TIMERS
I
EXAMPLE 7-4
Determine the Q and Qoutpu t waveform s of the flip-flop in Fit,'ll re 7- 15 for the 5, R and elK inputs in Figure 7- 16(a). A~umc that the posit ive edge-triggered flip-flop is initially RESET. .... FIGURE 7 _ 15
s
Q
- --!>c R
Q
I
Q 0 ---;---+---~ Q (b)
0
FIGURE 7 - 16
Sowtion
I. At dock pulse I. S is LOW and R is LOW, so Q does not change. 2. At dock pulse 2. 5 is LOW and R is HIGH. SO Q re mains LOW (RESET). 3. At dock pulse 3, 5 is HIGH and R is LOW, so Q goes HIGH (SET). 4. At clock pulse 4, 5 is LOW and R is HIGH, so Q goes LOW (RESE·I). 5. At clock pulse 5, 5 is HIGH and R is LOW, so Q goe~ HIGH (SET).
6. At clock pulse 6. 5 is HIGH and R is LOW, so Q stays H IGH. Oncc Q is determined, Q is ea.~~ fou nd since it is simply the complement o f Q. The resu lting waveforms for Q and Q are shown in Figure 7- I6(b) for the input waveforms in pan (a).
R.elated Probltun
Determine Q and Q fo r the Sand R inputs in Figure 7- I6(a) if the fl ip-flop is a negative edge-triggered device.
A Method of Edge-Triggering A simplified implementation of an edge-triggered S-R flip-flop is illustra ted in FiElIJ"(~ 7- 17(a) and is used to demonstnlte the concept of edge-triggering. 111is (:overage o f the S-R flip-flop does not imply that it is the most important type. Actually. the D flip-flop and the J-K fl ip-flop arc available in Ie fo rm and more widely used Ihan the S-R type. How-
EDGE-TRIGG ERED FLIP- FLOPS
•
381
ever. understanding the S-R is important because both the D and the J-K fl ip-flops are derived from the S-R flip-flop. Notice thai the S-R flip-flop differs from the gated S-R latch only in that it has a pulse tntnsition detector. FIGURE 7 - 17
Q e LK
JL
Edge triggering.
Pulse lraosi tion deleclOr
R-
Q
G,
--L-.CJ Slccring gates
Lmch
('I) A simplified locjc diagram for II I;l}l;irin: cdge-rri~crcd S-R nip-nop
Delay,
CLK ~
(b) A type
j
[>o-rL-...J
j =q
of pulse tr1msition deteCtor
Short pu lse (spike) produced by delay (when hoth gale inputs arc HIGH)
~
One basic type of pulse Iranl'ition detector is shuwn in Figure 7-I7(b). As you can see. there is a smal l delay on one inpUi lo the NAND gate so that the inverted clock pulse arrives at the gate input a few nanoseconds after the tnte clock pulse. Thi~ circuit produces a very short-duration spike on the posit ive-going trdllsition of the clock pulse. In a negative edgetriggered flip-flop Ihe clock pulse is inverted first. thus producing a narrow spike on the negari\'e-going edge. The circuit in Figure 7- 17 is partitioned into two sections. one labeled Steering gales and the other labeled Latch. The steeri ng gates direct. or steer, the clock spike either to the input to gate G3 or to Ihe input to gate G4 • depending on the state of the 5 and R inputs. To understand Ihe operation of this ni p-flop, begin with the assumptions that it is in the RESET state (Q = 0) and thattoc 5, R, and ClK inputs are all LOW. For this condition, the outputs o f gate G r and gate G2 are bo~ HLGH. The LOW on Ihe_Q output is coupled back into one input of gate G4 , making the Q output HIGH. Because Q is HIGH, both inputs to gate G) are HIGH (remember, the output of gate G! is HIGH), holding Ihe Q output lOW. Ifa pu lse is applied to the CLK input, the outputs of gates G t and G2 remain HIGH because they are disabled by the lOW~ on the 5 input and the R input; therefore, there is no change in the state of the flip-flop-it remains in the RESET slate. Let's now make S HIGH, leave R LOW, and apply a clock pulse. Because the 5 input to gate G 1 i .~ now HIGH, the output of gate G t goes LOW for a very short time (spike) when elK goes HIGH, causing the Q uutput to go HIGH. Both inputs to gate G 4 are now HIG H (remem~. gale G1 output is HIGH becausc R is LOW), forcin g the Qoutput LOW. This LOW on Q is coupled back into one inpu t of gale G 3, ensuring that the Qoutput will remain HIGH. The flip-flop is now in the SET slale. Figure 7- 18 illustrates the logic level transitions that take place within the fl ip-flop for this condition. Next, let's make S LOW and R HIGH and apply a clock pulse. Because Ihe R input is now mGH, the positive-going_edge of Ihe clock produces a negative-going selke on the output of gate G2 , causing the Q output to go HIGH. Because of this HIGH on Q, both inputs to gate GJ are now HIGH (remember, the output o f gate G 1 is HIGH because of the lOW on S) , forcing the Q output 10 go LOW. This LOW on Q is coupled back inlO one input of gate G4, ensuri ng that Qwill remain HIGH. The flip-flop is now in the RESET state.
I All logic operations that arc ! performed 1lIitJ, hardware can aJ~o be implemented in software. For ~ ~mple, the operation of aJ-K flip-flop un be periorrned with I specific computer in~tructions. If : two bib ~re wed to represent I the} ,lOd K inpub, the computer I would do nothing fOf" 00, a data I bit representing the Q output would be set (1) for 10, the Q r ebb bit would be cleared (0) for 101, allCl the Q data bit wou ld be complemented for 1 , . Although it may be unusua l to usc a computer to simulate a flip-flop, the point is I that a ll hardware operations can I be jJ·muJated using software.
382
•
LATCHES, FLI P-FLOPS, AND TIMERS
FIGURE 7 - 18
Flip-flop moking 0 tr.msition from the RESET sbte to the SET state on the politil.e-going edge of the dock
This gale 'senable
T riggering
S
11l1s spike SI?J'S flip- nop.
r.:/~ ~ T./
" ,,, 'G,,",,"-,-'
Q
"'Co
pube.
,\
el.K
un
Pulse transition delcct<)r
I
1_
~"\.---
41 --.1
Posi live
~pikc
0 1..
HIGH
This gate is disablC
Figure 7- 19 ill u.<;trate.~ the logic level tl1l11.<;ition.<; that occur with in the flip-flop for thi.<; cond ition. As with the gated latch. an invalid l:ondition exists if a clock pu lse occurs when both Sand R are HIGH at the same time. This is the Im~or drawback of the S-R flip-flop.
FIGURE 7 - 19
Flip-flop making a tramition from the SET state to the RESET sl:.Jte on the p<»itive-go ing edge of the dock pube.
This gate is dis:Jbled ~C-.lUse S is LOW. SIOV.101
Triggering edge
,\
eLK
li n
/
HIGH
G, Pulse I.... nsilion (\Clector
Q '
:c.~~=r~G~,=>~~-~:t~c)
R HIG Hll J
IT_______
"
"",0
,
--
- - II.....J
This $pike RESETS nip-nop.
This gale is enabled.
The Edge-Triggered 0 FI;p-Flop The Q output of a D flip-flop a"umei the 'State of the D input on t he triggering edge of the
T he I) flip-flop is useful when a single data bit (I or 0) is to be stored. The addition of an inverter to an S-R fl ip-flop creates a basic D flip- flop. as in Figure 7- 20, where a positive edge-tri£!!ered type is shown.
dock. FIGURE 1-20
A positive edge-triggered D flip-flop formed with an 5-R flip-flop and an inverter.
/) -~---ls
Q
CLK - f----I>C R
Q
Notice Ihnt the fl ip-flop in Figure 7-20 ha<; only one input, the D input, in addition to the clock. If there is a HIGH on the D input when a clock pulse is applied. the nip-flop will set, and the HIGH on the D input is stored by the flip- flop on the positive-going edge of the clock pu lse. If there is a LOW on the D input when the clock pulse is applied, the nipflop will reset, and the LOW on the D inpUi is stored by the flip-flop on the leading edgc
EDGE-TRIGG ERED FLIP -fl O PS
•
383
of the clock pllisc. In the SET state the flip- fl op is storing a I, and in the RESET state it is storing a O. The logical operation oflhe positive edge-triggered 0 flip-fl op is summHrizcd in Table 7- 3. The opemtion of a negative edge-triggered device is, of course, the same, except that triggering occurs on the fall ing edge of the clock pulse. Remember, Q fo llows f) at the active or triggering clock edge.
INPUTS D ClK
o
t t
o t -
OUTPUTS Q Q
o
d ock lr"dOSition LOW
I
l()
-<1 TABLE 7 - 3
I COMMENTS
Truth table for '\ prn i~ edgetriggered 0 flip-flop.
SET (SIOICS a I)
RESET (stores a 0)
HIGH
EXAMPLE 7-5
Given the wa\'efonns in Figure 7- 2 1(a) for the f) input and the clock, determine the Q OUlput waveform if the flip-flop start.. out RESET.
CLK:::j:_--==;-: ,, ,
tal
V
(h)
O~
/J
1---- 0
I
- --Pc P- Q
'---' FIGURE 7-21
Solution
Related Problem
The Q output goes 10 the state of the D input at the time of the posilive·goi ng clock edge. The resu lting output is shown in Figure 7- 2 1(b). Determine the Q OUlput for the 0 fli p-flop if the D input in Figure 7- 21(a) is inverted.
The Edge-Triggered J-K FI;p-Flop The J -K flip-nop is versali le and is a widely used type of fli p-fl op. ll1e functioning of the J- K flip-flop is identical to that of the S-R fli p-fl op in the SET. RESET, and no-change conditions of operation. The d ifference is that the J-K flip-flop has no invalid state as does the S-R fl ip-flo p. Figure 7- 22 shows the basic imernallogic for a positive edge-triggered J-K fl ip-flop. It differs from the S-R edge-triggered fl ip-flop in that the Q output is connected back 10 the in put of gate G2 • and the Qoutput is connected back to the inpul of gate G 1• l lle two control inputs are labeled J and K in honor of Jack Kil by, who invented the integrated circuit. A J-K nip-flop can also be of the negative edge-triggered type, in which case the clock input is inverted.
384
•
LATCHES,
F lIP ~ FlOPS,
AND TIMERS
FIGURE 7 -22 A simplified logic d~gram for a posii:Me edge-triggered J-K flip-flop.
J
eLK
---;:=;;:::::;i¥rfG~,5:=~~G~'>~-
Q
!'\Ibe Il"alls it;un deleetor
Q
Let's assume that [he flip-flop in Figure 7- 23 is RESET and that the} input is HIGH and the K input is LOW rather than as shown. Whcn a clock pulse occurs, a leading-edge spike indicated by CD is passed through gate G 1 becauseQ is I-I1GH and } is HIG H. This wi ll cause Ihe lalch portion of the flip-flop to change to the SET state. T he flip-flop is now SET. FIGURE 7 _ 23 Transition! illustrating the toggle operation when) "" 1 and K "" I. Pul~
transition delecto r
In the toggle mode, aJ-K flipflop changes state on every clock pulse.
If you make} LOW and K HIGH, the next d ock spike indicated by@will pass through gate G! because Q is HIGH and K is HIGH . This will cause Ihe latch panion of the flip-flop 10 change 10 the RESET slate. If you apply a LOW 10 both Ihe} and K inpms, the flip-flop will stay in its presenl ~tale when a clock pu lse occurs. A LOW on both J and K results in a lIo-challge condi lion. So far, the logical operation ofthel-K Il ip-flop is the same as that of the S-R Iype in the SET, RESET. and no-change modes, The difference in operation occurs when both the J and K inpul<; are HIGH. To see this. assume that the flip-flop is RESET. The HIG H on the Qenables gate G I ' so the clock ~pi ke indicated by @pa.<;.<,eS through to set the nip-nop. Now there is a HIGH on Q, which alIow~ the next clock spike to pass Ihrough gate G~ and rcsellhe !lip-flop. As you can ~ee. on each successive clock spike. the nip-flop changes to the opposite state. This mode is called toggle operation. Figure 7- 23 illustra1es the transitions when the nip-flop is in the toggle mode. A l -K nip-flop connected for toggle opemtion is someti mes called a T flip-flop. Table 7-4 summarizes the logical opemtion of the cdge-trig£ered J- K nip-nop intru1h table form. Notice that there i~ no invalid slate as there is with an S- R flip-flop. T he truth table for a negative edge-triggered device is identical except thai it is triggered on the fall ing edge o f the clock pulse.
TA8L E 7- 4
I
INPUT<.
Truth L1bte for a positive edgetriggeredJ-K flip-flop.
J
K
0
0
0 0
t
ClK
r r r r
clock tnlll.<.i~ion LOW 10 HIGH
Qc '" Olliput level rIfior !O clock Irnnsi~ion
OUTPUTS Q Q
I COMMENTS
Q,
Q,
0
I
RESET
0
SET
Q,
Q,
No change
Toggl e
ED GE-TR IGGER ED FLIP-flOPS
j
•
385
EXAMPLE 7-6
The waveforms in Figure 7- 24(a) are applied to the J, K, and clock inputs a~ indicated, Determine the Q output, assuming that the flip-flop is initially RESET.
I
eLK
0 I
J
Q
J
" I
eLK
(.J K 0
c K
(b)
Q
Q
,' ~ TOl'S lc
No
RC\CI
<;"""~C FIGURE 7-24
Solution
I. First, since this is a negative edge-triggered nip-nop, as indicated by the "bubble" at the clock input, the Q output will change only on the negalive-b'Oing edge of the clock pulse.
2. At the fi rst clock pulse, both J and K are HIGH; and because this is a toggle condition, Q goes HIGH, 3. At clock pulse 2, a no-change condition ex ists on the inputs, keeping Q at a HIGH level. 4. When clock pulse 3 occurs, J is LOW and K is HIGH. resulting in a RESET f,;{)ndition; Q goes LOW. S. At clock pulse 4 . .1 is HIGH and K is LOW, resu lting in a SET condit ion; Q goes HIGH. 6. A SET condition still exists on J and K when clock pulse 5 occurs, so Q will remai n HIGH. The resulting Q waveform is indicated in Figure 7- 24(bJ. Related Problem
I
Determine the Q output of the J-K nip-flop if the J and K inputs in r-igure 7- 24(a) are inverted.
EXAMPLE 7 7
The waveforms in Figure 7- 25(a) are applied to the flip-flop as shown. Determine the Q outpul, starting in the RESET state.
386
•
LATCHES, FLIP-FLOPS, AND TIMERS
Solution
Related Problem
TIle Q output assumes the Slate dcterminctl by the sliltes of the J and K inputs at the positive-going edge (triggering edge) of the clock pulse. A change in J or K after the triggering edge o r the clock has no effect on the output, as shown in Figure 7- 2S(b). Interchange the J and K inputs and determine the resulting Q output.
Asynchronous Preset and Clear Inputs: An active preet input make the
Q output HIGH (SET).
An ;)ctive dear input m;)ke the Q o utput lOW (RESET) .
For the flip-flops just discussed, the S-R. D. and J -K inputs are called synchrollous illpws because data on these inputs are transferred to the flip-flop' s outpu t only on the triggering edge of the c lock pu lse: that is. the data arc tr.l1lsferred synchronously with the clock . Most integrated eircllit nip-flops also have aSYIll'hrunous inputs. These arc inputs that affcct the stale of the nip-flop independent olrlle clock. They are normally labeled pl"e~1 (PRE) and clear (CLR). or (/i,.ecr S EI (51) and t/irec! YeSEI (R D ) by some manufacturers. An aClive levcl on the preset input will sctthe flip-nop, and an active level on the clear input wi ll reset it A logic symbol for a J- K flip-flop with preset and clear inputs is shown in Figure 7- 26. These inputs arc active-LOW. as indicated by the bubbles. These presct and clear inputs must both be kepI HIGH for synchronous opcnttion.
FIGURE 7- 26
logic symbol (or aJ-K flip-flop with active-LOW preset and dear inpub.. J
Q
- -I> c K
ClN
Q
EDGE-TRIGGERED FLIP-F LOPS
•
387
Figure 7- 27 shows the logic diagram for an edge-triggered J-K flip-flop with aCliveLOW preset (PRE) and clear (CLR ) inputs. This fi gure illuslmtcs basically how these in-
puts work. As you ..:an sec, they arc connected so that they override the effect of the synchronous inputs. J, K, and the clock. fiGURE 7 - 27
PRE J
Pulse
el K
....- -
------rE~F=;~=:::!~I_; transi ti on dellx:t"r
Q
logic diagram f~ a b'lIic)-K flipflop with active- LOW preset and d ea r inputs.
f---H-+
CI.R
I
EXAMPLE 7-8
For the positive edge-triggered J-K nip-flop with preset and clear inputs in Figure
7- 28. determine the Q output fOl"the inputs shown in the timing diagnllll in parI (a) if Q is initially LOW.
PRE
HIGH
),
rE
J C
pE
K
'( CLH
CLK ~, 4
,,
PRE
Ca)
Cw. Q
(b)
l:-_____~
I·--Pr I- l'. .cl ==.tl.:h=:t~·:r,:, },:=:::!=j.I:'
=i-I
=-;; 01;::1';<:';-
... fiGURE 7 - 28
Open file F07 -l8 to verify the operation.
Solutioll
J. Duri ng clock pulses 1, 2, and 3, the preset (PRE) is LOW, keeping the flip-flop SET regardless of the synchronous J and K inputs.
388
•
LATCHES, FLIP-FLOPS, AND TIMERS
2. For clock pulses 4. 5. 6, and 7, toggle operation occur.; because J is HIGH. K is HIG H, and both PRE and CLR
RESET rcgardless of the synchronous inputs. The resulting Q Olltput is shown in Figure 7- 28(b). Related Problem
If you interchange the PRE and CLR wavcfomls in Figure 7- 28(a}. what will the Q output look like'?
LeI's look at two spec ific t.'dgt..... triggered flip-flops. They arc rcprcl>Cntative o f the various types o f flip-flops available in IC form and, like most other devices. arc avai lable in CMOS and in T J'L logic fam ilies.
THE 74AHC74 DUAL D FLIP-FLOP This CMOS device contains IWO identical 0 fli p-flops Ihal arc independent or cach «her except for sharing Vee and ground . The fl ip-flops arc positive edge-triggered and havc active-LOW a~y n chronoo s preset and clear inputs. The logic symbols for the individual fl ip-flops withi n the package arc shown in Figure 7- 29(a), and an ANSII[EEEslandard sing le block symbollhal represcnts the entire devicc is shown in pan (b). t he pin numbers arc shown in parentheses.
14) IPRE
'" tU .K
S
(21
0
(3)
(5)
IQ
(6)
lQ
C
R
tCLR
II)
10
( to)
teLK
"!.PRI;
"!.IJ
b
s
~ 0 (Ill
!CI .K
I CI.R
~ ~Q
R
'D
(2)
(3 ) (I)
(10)
IQ
S
10 CI
(6)
IQ
R
( 12 )
(91
'Q
(/I)
(13)
".!. C/.R
(8)
'Q
~ ~Q
(13) "!. C1.R
(2) Ind i... iduat lo~ic
~PRf:
!C'I K
C
(5)
(4) I PRE
symbQls
(b) Si ngle bl()l:k log ic symbol Note: The Sand R in~idc rh~ block illdicate Ih;J1 PRE SETS and CLR RESETS.
FIGURE 7- 29
l ogic s)"Tlboh for the ]4AHC74 dV
EDGE-TRIGGERED FLIP-flOPS
•
THE 74HCl12 DUAlJ- K FLIP-flOP This
(4)
I PRE IJ
leLK IK I Cf H
logic symboll for the 74HCl1 2 dua l S
(2)
J (I)
'"
10
10 K
1K
!CI.R
flop.
C
( 3)
( 6)
K R
IQ
( 15)
II'H£
(10)
IJ
'!PRJ; OJ
neg
1('1 K
S
(1 2)
J
(9)
'0
(I)
1PRE
C (7)
( II )
K R
OK ICifi
'0
(1 4 )
"
~CLK
OK
'!CLR
(a ) Imli vidualloeic symbols
(4)
S IJ
(2)
(I )
CI OK
( 3)
(1 5)
(j)
(6)
R
(1 0)
(9)
( 12)
10 10 1(/
( 13 )
I7l
( II ) (1 4)
'0
(b) SillJ.!le block IOj1 ic symbol
T he iJ, I K, IClK. I PRE, and ICLR waveforms in Figure 7- 3 1(a) arc applied to one of the negative edge-triggered nip-flops in a 74HC I 12 package. Determine the IQ output waveform.
Pin I nCLK)
(a )
Pill 2 Pill )
(IK)
Pill 4
(I PRE)
( IJ )
-.iJd~i1-tjJ:h~:;-~~J -+----:-'=:;::::::=:::~-l,
;-'::::=",::::
Pin 15 ( ICLR)
(b) Pill 5
(I Q) _'---'
FIGURE 7 - 11
Solution
Related Problem
The rcsulting I Q waveform is shown in Figure 7- 3 1{b). Notice that each time a lOW is applit.-d 10 the IPRE or l CLR, the flip-fi op is sel or resel regardless oflhe slates of the Olher inpuls.
Determinc (he IQ output wavcform iflhc wavefonns for IPRE and J CLR are interchanged.
389
390
_
LATCHES. FLIP- FLOPS. AND TIMERS
I
SECTION 7- 2 REVIEW
1_ Describe the main difference between a gated S-R latch and an edge-triggered S-R flip-flop.
2_ How does aJ-K flip-fl op differ from an 5--R flip-flop in its basic operation? 3_ Assume that the flip-flop in Figure 7-21 is negatNe edge-triggered. Ot!scribe the output waveform for the same elK and D waveforms.
7-3
FLIP - FLOP OPERATING CHARACTERISTICS The performance. operating requirements. and limilations of flip-flops are specified by several opcmling characterist ics or parameters found on the data sheet for the devicc. Genemlly, Ihe sIX'Cificmions arc applicable to all CMOS and TIL flip-flops. Aftcr completing this St.'Ction, you should be Hblc to - Define propagation tle/ay lime - Explain the various propagation delay time specilications - Definc sel -lIl) lime and discuss how it limits flip- fl op opcr.nion - Defi ne hold li/lle and discuss how il limils flip-flop operation - Discuss the significance of maximum clock frequcncy - Discuss the variolls pulse width speci l'ications - Define power tlissipalion and calculate its valuc for a specific device - Compare various serics of fl ip-flops in tcmlS o f their opcmling p.'lrmncters
Propagation Delay Times A propagation delay time is tht: intcrval of time required after an input signal has been applied for the resulti ng OlltpUl changc to occur. Four categories of propagat ion delay limcs arc important in the operation of a flip-flop: I. Propagation delay fpU/ as measured from the triggering edge of the clock pulse to the LQW-to-I-IIGH t.ransition of the output. This delay is illustrated in Figure
7- 32(a). 2. Propagation delay IpllL as measured from thc triggering edgc of thc clock pu lse to the HIGH-Io-LOW transition of the output. This delay is illustratcd in Figure 7- 32(b). ~W"'
e LK
ruin! un
lJiI!~"rin~ ~'(]~c
\ ,----,
e LK
.50', puin!
---0-,- , Q
-
__-+_J: ,'- -',
50'".1 point ~m LOW-Iu-IIlGH
Q
tranMIlUU uf Q
1
,
5Q<.f pt"Iinl VII HIGH-Itl-I 0\\
:---:
' / '/)1
1/"111
(b) FIGURE 7-32
Prop<1gatiOfl delaYJ, clock to ovtput.
lrJu\iliun vf Q
,,------,-
FLI P-flOP OPERATI NG CHARACTERISTICS
•
39 1
3. Prop..'l.gation delay I l'Ifi as measured from the leading edge of the preset input to the LOW-to-H1GH transition of the output. This delay is illustr.:lIed in Figure 7- 33(a) for an activc-LOW preset input. 4. Propagation delay 'PIlL as measured from the leading edge o f the clear input to the HIGH-to-LOW transition of the output. This delay is illustrated in Figure 7- 33(b) for an active- LOW clear input.
\ 'ifY'+ .,..;nl
PRE
!
cu~
,, ,,, I~Y" puinl , I
Q
Q
i---i
\" PO'' ' ! \, 5O'k po;'" :- : ,
11'/11
INn
/b)
I' ) FIGURE 7 - 13
Propagation del¥, Pre!.et input to output and cleilr input to output.
Set-up Time The St't-up time (I,) is the minimum interval n."quircd for the logic levels to be maintai ned constll11tly on the inputs (1 lind K. or Sand R. or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the fl ip-flop. T his interval is ill ustratl..'(\ in Figure 7- 34 for a D fli p-Ilop.
o
/50'.
------' ,,
""im
,,
e lK
: _ _--'-J ;,
,,
5O'A !,
'---'
5..:1·1IP lime II,) FIGURE 1 - 34
kt-op time (t,). The logic level mUlt be pr~ nt on the D input fOl' a time equal to Of' greater than t, before the triggering edge of the clock pulse for reliable wl:a entry.
An adva ntage of CMOS i5 that it can operate over a wider range of de 5Upply voJtage! (typically Z V to 6 V) than TIL and, therefore, leu expemive power ~upplie! that do not have precise regulatio n can be u~ed. Also, batteries can be med as secondary or prima ry 50urces for CMOS circuits. In additio n, lower \IO l tage~ mean that the Ie diuipates les power. The drawback is that the performance of CMOS i5 degraded with lower supply \IOltage~. For example, the guaranteed maximum dock frequency of a CMOS flip-flop i5 much leu at Vee = 2 V than at Vee = 6 V.
J'lZ
•
LATCHES, FLIP-FLOPS, AND TIMERS
Hold Time The hold time (th ) is the mini mum interval required for thc logic levels to remain on the inputs after the triggering edge of the clock pulsc in order for the levels to be reliably clocked into the fl ip-flop. This is illustmted in Figure 7- 35 for a D flip -flop.
\,':"Il'k - - - - - -
FIGURE 7 - 35
Hold time (th ). The logic level mUlt remain on the D input for a time equal to Or greater than fh after the triggering edge of the dock puhe for reliable data entry.
D
Il"1111
,
L Maximum Clock Frequency Thc maximum clock frequency (f."",) is the highcst rale at which a flip-flop can be reliably triggercd. At doc!.. frequc ncies Hbovc the nmximum, the fli p-flop would be ullable to respond qu ickly enough, and its opcmtioll would be impaired.
Pulse Widths Minimum pulse widths (111" for reliable OlxTdlion are usually spec ified by the mallufactu re r for the clock. preset. and clear inputs. Typically, the clock is specified by its minimum HIGH time and its minimum LOW lime.
Power Dissipation The power dissipation of any digital circuit is the 100al power consumption of the device. For example, if the flip-flop operates on a + 5 V dc sourcc and draws 5 lilA o f current . thc power dissipation is p = Vcc xlcc = 5Vx5mA = 25mW
Thc power dissipation is very important in most applications in which the capacity of thc dc supply is a concenl. As all examplc. lct's assume Ihat you have a digital syslCm that requires a total or ten nip-flops, and each fl ip-flop dissipatcs 25 mW of power. T he total power requirement is
PT = IOx 25mW
=
250mW = 0.25 W
This tellFi you the output capacity required of the dc suppl y. If the flip -flops operate on +5 V dc. then the amount of eUlTCl1llhat the supply must provide is 1=
250rnW
5V
You must use a
= 50 mA
+ 5 V de supply I[mt is cHpablc of providing at leasl 50 rnA of currcnt.
Comparison of Specific Flip-Flops Table 7- 5 provides acomparisoll, in tcrms ofthc opcrdti n!! paramclersdiscusscd in this section, of fou r CMOS and TIL flip-flops of the same type.
FLIP-FLO P APPLICATIONS
-
TABLE 7-5 Com~rilon
of operating parameten for four Ie families of flip-flop! of the l.;,Ime type ilt 25°C.
PARAMETER
CMOS 74HC74A 74AHC74
TTl 74LS74A
74F74
1PH1. (CLK to Q) tpUi (CLK to Q)
17 M
4.6n8
40"
6.8
17
4.6 liS
25"
ROilS
tPHI. ( CLR 10 Q)
18 liS
4.8
liS
40"
9.0 liS
Ipw ( PRE toQ)
I S liS
4.8
li S
25 ns
6. 1 ns
I, (set-up ti me)
14
5.0
li S
20
2.0 ns
liS
liS
liS
liS
30ns
0.5 ns
5 ns
1.0 1)s
l w(CL K HIG H)
10 ns
5.0 ns
25 ns
4.0 ns
Iw(CLKLOW)
10 ns
5.0 ns
25 ns
5.0 ns
1M" CLRI PRE)
10 liS
5.0n8
251)s
4.0
170 MHz
25 MHz
100 MHz
44mW
88 mW
Ih (hold lime)
1._
35 MHz
Power, qu iescellt
1. 1mW
0.0 12 mW
Power, 50% duty cycle
i SECT' ON 7 - 1 REVIEW
liS
1. Define the following:
(a)
~t-up time
(b) hold time
2. Whic h specific flip-flop in Table 7- 5 can be Opefilted at the highest frequency?
7- 4
FLIP-FLOP APPLICATIONS
III this scctio n, th rcc gCllcr..t1 applicatio ns of nip-flo ps arc d iscussed 10 give you an idea o f how they can be used. III C hapters 8 a nd 9. fli p-fl op lIpplicatio ns in coun ters alld registers a rc covered in d etai l. After completing Ihis sec tio n, yo u sho uld be ab le 10 _ D iscuss the app licatio n of flip-flo ps in da ta sto rage - Describe how flip-flops arc llSed for freq uency di vis ion - E xplai n how flip-flops arc used in basic counte r applic at ions
Parallel Data Storage A commo n requ irement in d igital systems is to store seveml biLS of data from pamUd lines s im ulta neously in a group of ni p-nops. TIlis opem tion is illus trated in Fig ure 7-36(a ) us ing fo ur flip-fl ops. Each of the four p..'U"lIllcl d ata lines is con nected to the D input o f a flip-flo p. The clock inputs o f the flip-flops are connected together, so that each fl ip-Oop is triggered by the same d ock pu lse. In this example, positive edge-t riggered fl ip-flops a rc used , so the data on the /J inputs are s tored s imu llancously by the flip-flops Oil the positi ve edge of the clock, as indicated in the t iming d iagrdm ill Fig ure 7- 36(b). Also, the async hronous reset (R) inpllls arc co nnected to a com mon eLR li nc, whic h initiall y resets a ll the fl ip-flo ps .
393
3 94
•
LATCHES, FLIP- FLOPS , AND TIMERS
FIGURE 7 - )6
,
Example of f1ip-f1o pl uled in iI bilSic register for para llel data storage.
I- Q"
D
e
,
0" 0 R
n,
D,
0, '
f- 0 ,
"
D,
' 0
e
eLR
Parallel
P.uulld Jma
iliIIa
inpuh
outpul_
R
". ,
CLK
f-
D
00 Q1
e
elK
, ~nL_ ,~
--1=====
:
i
O' r'
O,::----~----------
Q, '
O' ~:----j
R
,
W
,, ,,
,
Q, '
O,"----~,---------
l- Q.
D
~
e
Flip-Il
D-J.1ll
c1ean..J
~101\:d
(b)
R
eu, (,j
This group of four fl ip-flops is an example of a basic register uS<.-'d for data SlOn ige. In digiUlI systems. data arc normally slon:d in groups orbits (usually eight or mUltiples thereof) that represent numbers, codes. or other information. RegislL'r s arc covered in detail in Chapter 9.
Frequency Division A nother applicatio n of a nip-fl op is dividing (reducing) rhe freque ncy of II periodic wavefOlm . When a pulse waveform is applied to the d ock inpm of a J-K flip-flop that is connected to toggle (J = K = I). the Q outpu t is a square wave with one-half the frequ ency of the clock input. Thus. a single nip-Oop can be applied as a dividc-by-2 device , as is ill ustrated in Figure 7- 37. As yoo can see, the fl ip-nop changes state o n each triggering clock FIGURE 7 - )7
IIJGH
The J-K flip-flop ii i iI dMde-by-l device. Q " one-n..lf the frequency ofCLK
, ---,
1-- 0 e LK
--IHl>e '-- K
e LK
Q
FLIP-flOP APPLICATIONS
•
395
edge (positive edge-triggered in this case). This ~ults in an output that changes at half the frequency of the clock wtlveform. Funhcr division of a clock frequency can be achicved by using the output of one fl ip-flop a<; the clock input to a s(.'Cond flip-Ilop. a'i shown in Figure 7- 38. The freq uency o f the QA output i.~ divided by 2 by flip-Ilop B. The Qn output is, thercfore, onc-founh the frequency of the original clock inpul. Propagation delay times are not "hown on the liming diagrams.
~ J
e
eLK
'---
.... FIGURE 7-38
HIGH
mG11
l
Q
('
'-
K
N
~ J
oomple oftwoJ- K flip-flops used to divide the dock frequency by 4. 0 " rs one-half ilnd 0 8 rs o ne-fou rth the frequency of CLK.
K
eLK
Q,
By connecti ng f1 ip-tlops in thi s way, a frequc ncy division of 2" is achieved. where II is the number of fl ip-fl ops. For example, Ihree flip-flops divide the clock frcquency by 2 3 = 8; four flip-fl ops divide the clock fr(."quency by 24 = 16; and so on.
Develop the!..." waveform fo r the circuit in Figure 7- 39 when an 8 kHz squarc wave input is applied to the clock input of fli p-flop A. HJGH
Q,
J
J,.
e
-
K
J
l
Q, e
-
K
J
l
Qc
-
e L
K
Flip-nop e
fiGURE 7-1'
Solution
Thc Ihr(.'C flip-flops are connected 10 divide the input ti"cqucncy by eight (2) = 8) and the! .... waveform is shown in Figure 7-40. Since these are positive edge-triggered flipflops, the outputs change on the positive-goinE clock edge. There i ~ o ne Output pu lse for every eight input pu lses, so the output frequcncy is I kHz. Waverorrn.<; or Q" and Ql/ are also shown.
396
•
LATCH ES, FLIP- flOPS , AND TIMERS
, Q.
,
~~ , ~---.-t=±~
f~ ~
!--------c~!
,--~-,-~-----,I
FIGURE 1 - 40
Related Problem
!-low many nip-nops are required to divide a frequency by thiny-two?
Counting Another imponant application of flip-nops is in digital cOlUlters, which arc covered in detail in Chapler 8. The concept is illustrated in Figure 7-4 1. Thc nip-flops are negative edgetriggered J-Ks. Both flip-nops are initi
Flip-flop!' uKXl to geocr;)te a binary count le
f-
01, 10, '1) are shown.
-
J
e LK
Q,
I ~
C
C ~
Q,
J
-
K
Hip-nopB
Flip-flop A
J
2
K
5
4
,
7
6
eLK
,,
, n , 0 ,' 0 ,,
0
2
3
0
, 0
2
.I,
3
L ,,
,,
RimlI) ~~"\jOCIl"C
Observe the sequence of Q" and Qs in Figure 7-4 1. Prior to clock pulse I, QA = 0 and Q8 = 0; after clock pu lse I. QA =:: I and Q8 =:: 0: afler clock pulse 2. Q" = 0 and Q8 =:: I ; and llfler clock. pulse 3, QA =:: I and Q8 = I. If we take Q" as the least sign ificant bit,
FLI P- FLOP APPLICATIONS
•
397
a 2-bit sequence is prod uced as the flip-flops are clocked. Th is binary sequence repeats every four clock pulses. as shown in the ti ming diagram of Figure 7-4 1. Thus, the flip-fl ops are counting in sequence from 0 to 3 (00, 0 1, 10, II ) Olnd then recycling bOld to 0 10 begin the sequence again.
I
EXAMPLE 7-11
Determ ine the output wavefonns in relation to the clock for Q", QH' and Qc in the circuit of Figure 7-42 and shuw the binary sequence re presented by these wave form s.
Q,
J
c
e LK
-
Q,
J
c
c
-
K
Q, -
J
K
K
fiGURE 1 - 42
Solution
The output timi ng diagmm is shown in Figure 7-43. Notice that the outputs change on the negative-going edge of the clock pulses. The ompul); go through the binary sequence 000. 001. 010,0 I I. 100, 10 1. 110. and I I I a<; indicated .
e LK
Q,
, ,, ,"
Q,
0 '
Q,
0 '
,
0
0 II
0
0
, f--2-
~
... FIGURE 7 - 43
Related Problem
i SECTION 1 - 4 REVIEW
How many fl ip-flops are required nu mbers 0 through 15?
10
produce a binary seq uence representi ng decimal
1. What is a group of flip-flops used for datil storage ca ned? 2. How must a J-K flip-flop be connected to function as a divide-by-Z device? 3. How many flip-flops are required to produce a divide-by-64 device?
398
-
7-5
LATCHES, FLIP- FLOPS, AND TIMERS
ONE-SHOTS The one-sho t is a monostablc ll1uhivibrator, a device with only one stable stale. A one-shot is nommlly in its stable state and will change to its unstable state only when triggered. Once it is triggered. the one-shot remains in its unSlnble state for a predetemlined length of time and then automatically returns to its stable state. The time thai the device stays in its unstable Slate determines the pul ~e width of its output. After completing this section, you should be ilble to - Dc~ribe the basic operat ion of a one-shol - Explain how a nonretriggerable oneshot works _ Explain how a retriggcrable o ne-~h ot works _ Set up the 14 121 and the 74LS 122 one-sho(." to obtain il specified output pu lse width _ Recognize a Schmitt trigger symbol and explain basically what it means
A one-shot produces a single pu lse each time it is triggered.
Figure 7-44 shows a basic one-shot (monostable rnultivibrator) thai is composed of a logic g
FIGURE 7 _ 44
A iimple one-mot circvit.
Q
The capacitor immediately begins to charge through R toward the high voltage level. The rme at which it ch:lrges is determined by the RC time constant. When the capaci tor charges to a certai n level. which
Basic one-mot logic symbols. ex and RX iUnd for external componenb.
Nt;Xl "
Ct:xr,
Q T,ig.get"
(.,
:o;-,
.n.
ex
Q
Rx/cX
Q
Q (b,
ONE-SHOTS
•
399
A nonretriggemble one-shot will not respond 10 any aJditionallriEger pulses from the lime it is triggered into ils unSlable slate unti l it returnl
Td"o, -Il'-____. .Jnl.. ____--'nL__
.. FIGURE 7 - 46
Nonretriggeroblc one-shot oction.
LJ (,)
_
Trilllocr
/-------~-/---
nL__--'n/
~'-_-'! ~
Tho>-
n OQc-~h,,'.
(b)
A re triggerable one-shot can be triggered before it times out. The result of retriggering is an extension of the pulse width as ill us tmted in Figure 7- 47. T"~o, -Il Q (, )
--.J
______________________--,n,--_____
.. FtGURE 7 - 47
Retriggerable one-shot action. , . . 1_
1--'11--1
_
_
_
__
----'
L
THE 74121 NONRETRIGGERABlE ONE-SHOT T he 74 121 is an example of a no nt"e triggerable Ie one-shot. It hm; provisions for external R and C, as shown in Figure 7- 48. The inpuls labeled A!, A2 • and B are gated trigge r inputs. The RINT input connects to a 2 kQ inrernaitiming resistor.
Setting the Pulse Wtdth A Iypical pulse width of aooul 30 liS is produced when no exlemal liming componems ,lre used and the internal timing resistor (RIl'I"I·) is connected to Vee. as shown in Figure 7-49(a). The pulse width can be set anywhere between about 30 ns and 28 s by the use of extemal components. Figurc 7-49(b) shows the configunnion using the internal res i ~ t or (2 kQ) and an external eapacilOr. Part (c) shows the configuration using an external resistor and an externtll capacitor. The output pulse width is set by the values of the resistor (R' NT = 2 kQ. and RF.>:T is se lected) and the capaci tor acx:ording [0 the fol lowing formula :
'\11 = 0.7RC8(T where R is either Rn.n or REn . When R is in kilohms (kQ) and CEXT is in picofarads (pF). the OUtput pulse width 1\11 is in nanoseconds (ns).
Equation 7- 1
400
•
LATCHES, FLIP- FLOPS, AND TIMERS
A, A, 4.
•
(3) (4 ) (5)
I ~
~
RI \ , IC1.\T
A,
(4)
•
CS)
&
"
1 -"-
-
(6)
Q
ff (I)
Q
(9)
81
R1""1
C hW
~Q
/Jff I>
(3)
(0) (1 1)
HI
~Q
ex HX/CX
(b) ANS I/ IEEE s.d. 91 - 19841Qgic symbol (X = non logic connec.ion). k l..n... - is the q ualifying symbol foc" oonrc:triggcra ble
(a} Tl"lldilional log ic sy mbol
onc·~hot.
FIGURE 7 - 41
Logic .ymboh for the 7412 1 nonretriggcril ble one-shot.
,1, A, B
"
A,
I~
&
Q
>1
A,
I~
Q
n
ff
&
A,
ff
~I
&
J ..n...
A, 8
Q
ff
i) 81
ex
RXlCX
(al No extcrnul co mponents HINT 10 Vee ,w : 30 115
Q
ex
Rf
RX!CX
RI
ex
RX/CX
(bl RINT ~rl
'IV= 0.7(2 kfllCul (el REXT and Ct:xT 'w=O.7REXT CEXl FIGURE 7 - 49
Three way! to set the
pul~c
width oh 74121.
fhe SC.hmitt- Trigger Symbol The symbol ff m(hclltes a SChmilt-lrigger mpul. This Iype of input uses a special lhreshold circuil Ihal produces hysteresis, a charnc leri .~ l ic Ihat prevenls ermlic switching belween stolles when a slow-changing trigger voltage hovers around the crilical inpul leve l. This allows reliable triggering 10 occur even when Ihe input is changing as slowly as 1 volt/second.
THE 74L5122 RETRIGGERABLE ONE- SHOT The 74LS 122 is:m example ofa relriggenlble rCone-shot with a clear input. It alsu has provisions for external R and C, a~ shown in Figure 7- 50. T he inputs labeled A" A2, B" and B~ are [he Bated [ri~ge r inputs.
ON E-S HOTS
•
& (\)
I,
( 2)
..I ,
(3) (4)
H, H,
(8) Q
~
J
>
I
RI~"r C
~ HI
T~
ex '" ~ RXICX
~Q
.!1 (6)
(6)
>-'- Q
CX
RHI1('l'<1I
c/.H
_-"('~J
Q
_
RXICX (1 1)
______-l________~==~---"
la) Tmdit;onal logic symbol
(b)
ANSIlI EEE .~U1. 9 1 - J984 lo~ic
symbol
(X = n<)lllo~ ic cOIlnet:lioll ). JL is the: Qu"l ifyin~ ~ymbol
for a rctriggcmble
logic symbol for the 74151 ZZ retriggerab le o ne-shot.
A minimum pulse width of approximately 45 ns is obtaincd with no external compoWider pulse widths are
fw
0.7) ( + Ii"
Equation 7-2
= 0.32RCExT I
where 0.32 is a constant determined by Ihe particulllr type of one-shot, R is in Hl and il> either the internal or the external resistor, C EXT is in pF. ;md is in ns. The internal resistance is 10 kn and can be used instead of an eXlemal resiSlOr. (Notice the difference between Ihi s fonnu la and thm for the 74 12 1, shown in Equation 7- 1.)
'w
J EXAMPLE 7-12 A certain appl ication requires a one-shot with a pulse width of approximmeJy 100 ms. Using a 74 121, show the conneclions and the COlllponem values.
Solu tion
Arbilmrily select R EX '!' = 39 kQ and calculate the necessary capacitance. t w = 0.7 R~EXT Iw
CEXT = ;;-;;-;:--
0.7 REXT
where CEXT is in pE NEXT is in kn. and I w is in ns. Since I(X) illS = I x I rI' ns, I X Iri" ns CEXT = 0.7(39 kD} = 3.66
_/)
x 10 pF = 3.66 Jil'
'
A standard 3.3 p.F capacitor will ~ive an output pulse width of9 1 ms. The proper connections are shown in Fi ~ u re 7- 5 1. To achieve a pulse widlh closer to lOOms. other combinations of values fOr REXT and CEXT can be tried. For example, R EXT = 68 kQ and CEXT = 2.2 p.F gives a pulse width of 105 illS.
401
402
•
LATCHES, FUP-FLOPS, AND TIMERS
FIGURE 1 - 5'
A,
&
I~
Q
A n
.u Q
RI
Related Problem
i
ex
HXJCX
Use an external capacitor in conjunction with RINT to produce an output pulse width of 10 Jis from the 7412 1.
EXAMPLE 7-13
Detennine the values of R EXT and CF.xr thilt wi ll produce a pul se width of I J.lS when connected to a 741..s 122.
Solution
Assume a value of CEXT =: 560 pF
= D.32REX"(,CEXT ( I = O.32REXT CEXT
REXT =
+ -0.7- ) REXT
= 0.32RF.xrCEXT
+
0.7
(0.32 Rm Cm )
RFJer
+ (O.7)(0.32)CEXT
'w
(O.7)(O.32)CEXT = - 0.7 0.32CEXT D.32CEXT 1000 ns
I I\' -
~ (0.32)560 pF - 0.7 ~ 4.88.0 Use a st
kn.
Show the connect ions and component ....dlues for a 74 LS 122 one-shot with an output pulse width of 5 J-tS. Ass ume C EXr = 560 pF
An Application One practical one-shot application is a sequential timer that can be used 10 illuminate a series ofli~h ts. This type of circuit can be used, for example. in a lane change directional indicator for highway con ~trl1cti on projects or in 'iCquential tum signals 011 automobiles. Figure 7- 52 shows three 74LS 122 o ne-shots connected as a seque ntial timer. This parlicular circ uit produces a sequence of three I s pu lses. The first o nc-"hot is triggered by :1 switch closure or a low-frequency pulse input. producing 11 I s output pu lse. When the first one-shot (OS I ) times out and the I s pulse goes LOW. the sccondone-shm (aS 2) is triggered. also producing a J s outpul pulse. W hen thi s second pulse goes LOW, the
THE SSS TIMER
•
403
third une-shot (aS 3) is triggered and the third I s pulse is pruduced. The output timing is illustrated in thc figu re. Variatiuns of this basic arrangement can be used 10 produce a variety of timed outputs.
Q ,I1-, ,,,
Q ,U L , 051
A,
I
>I
A,
R, H,
.n.
&
Q
-
0S2
A,
"1
n,
>
.If
n,
CLR
>1
A,
.n.
&
Q
-
B,
>
.If
H,
CX
RXJCX
RI
I II
'i
68 11 .
tJ &
.n.
p-
~
Q 3Uh t
S it ~ I
t
~ I
.If
CLR
CLR RI
A,
, ,,
OS 3
ex
I
47 H)
RXJCX
RI
RX/CX
I II
II
68 ~~
CX
47 t fl
(~ ~~
4nn
FIGURE 7 _ 52
A sequential timing circuit lIsing three 74L51 22 one-Ihots.
1. Describe the difference between a nonretriggerable and a retrigger-*,Ie one-shot 2. How is the output pulse width set in most Ie one-Ihots?
7-6
THE 555 TIMER
The 555 timer is a versatile and widely used Ie device because il can be configured in twO differenr modes as either a monosI
Basic Operation A functional diagram showing the internal components of a 555 timer is shown in Figure 7- 53. The comparatun; are devices whosc outputs ale HIGH when the voltage on the positive (+) input is greater than the voltage on the negalive (- ) input and LOW when the - input voltage is greater than the + input voltage. TIle voltage divider consisti ng of three 5 kn re· sistors provides a tligger level of ~3 Vee and a thresho ld level Of 1h Vee. The control voltage input (pin 5) can be used tu externally adjust the trigger and threshold levels to other values if nccessary. When the normally HIGH trigger input momentarily goes below Y3VCC. the
A 555 timer GV1 operate.u either ., one-shot (monostable) or a~ an oscillator (astable).
404
•
LATCHES. FLIP-FLO PS. A N D TIM ERS
output of comparator B switches from LOW to H1GH and sets the $-R latch. causing lhe output (pin 3) to £0 HIGH and turning the discharge lr.msislOr Q I off. The output will slay HJGH un til the normally LOW th reshold input goes above %Vee and causes the output of compamtor A to switch from LOW to HIGH. This resels the Imch. causing the output to go back LOW and tulTling the discharl,le tnlnSiSIOr on. The external resel input can be used to reset the I
of ~ 555
(8)
timer (pin numbers are in pilrefltila i1.).
555
R
"0 C'06C A ' _-I---1 ;-.;;Compamlor +
C
Thrcshuld
''l ('omml o-''''--+---1 :--
Lmch
lo l!;\gc
R
R 5k0
>--,,""-)-0 OuIPUI
s
Oulpt •• buffer
+ (1)
TtilQ'!cr 0-''''"_ -1---1
Q,
R Hn
(4)
(I )
GND
Rc,,",'
Monostable (One-Shot) Operation An external resistor and c
Equation 7-3
I IV =
10
the following fOlTllUJa:
I.J R I C.
FIGURE 7-54
The 555 timer connected ~I ~ one-
""'t.
1(4)
(8)
R, RES£1' (7)
(6)
C!)
V'-'C
DISCI!
555 O(ff
TIIR/~H
TRfG
GND
== C,
I
I
(I )
(3)
CON1~.c,
I
0,01 )I F ( decoupl ing opti onal)
THE 555 TIMER
The cOnlrol vohage input is not used and is connected to a decoupling capacitor C l tO preven! no ise from :lffecting the trigger and threshold levels. Derore a trigger pulse is applied, the output is LOW and the discharge transistor QI is 011. keeping C. dischargcd as shown in Figure 7- 55(a). When a negative-going trigger pulse is applied at In. thc output goes HIGH :lI1d the discharge tmnsistor llIrns off, allowing capacitor C. 10 begin charging through R. as shown in pari (b ). When C. c ha r~ es to 1/3VCC' the output goes back LOW a t ' I and QI tu rns 0 11 immedi
,~
,,~
555
,
' s)
"
""
(0)
(5,
555
,
(8)
"to,
A
HO A
<5, 1.0\\
"J '. U
OoJlpm
m
IUGlt
Trigger
(1)
(1)
'"
,.,
f'
(1) R
Q,
"" -'"
ON
]C,•
j
'"
Prior IV lriggerint;. (The <;UrTcnt pH lh
i~
indicated by the red mnJw.l
(bl When Iriggered
555
,S( R
" '"
s to •
IS)
"" Jl 'u "
I,
) U(j ll
1>; .....
.11'
O ne--shot operation of the 55 5 timer.
A
S
(2 )
~+---"'-+---j
t,
,
h:'I")'' ' '
(c) 1\1 end (}( charging
FIGURE 7- 55
((( ~
'n'
"
, ""
n"''l''''f
S" '
u,
intervat
Q,
ON
",
'"
Q, Off 41/"
'"
•
405
406
•
LATCHES, FLIP- FLOPS, AND TIMERS
i
EXAMPLE 7 - 14 What is the output pulse width for a 555 monoSlable circuit wi th RI = 2.2 kfl a nd C I = 0.0 1 j.LF?
So/.JJ.tiOIl
From Equation 7- 3 the pu lse width is fw
Related Problem
= URICI = 1.1(2.2 kfl)(O.OI j.LF) = 24.2ps
For C I = 0.0 1 j.LF. determine the value of RI for a pulse wid th of I illS.
Astable Operation
loOurce to provide accu .... te dock wavefOfms. The timing section control! aU ~tem timing and is responsible for the proper operation of the fYStem hardware. The timing section usually coru;sts of a c~ta l-controlled oscillator and counten fO<" frequency division. Using a high-frequency oscillate.- divided down to a lower frequency provtdes for grea ter accuracy and frequency Itability.
A 555 ti me r connected to opcmte as an ast.lble Illultivibrutor. which is a nonsinusoidal oscillator, is shown in fi gure 7-56. Notice that [he threshold input (THRESH) is now connected to the tri~er input (TRIG). lbe external components RI> R2• and C I form the ti ming network that sets the frequency of oscillation. 'Il1C 0.01 j.LF capacitor, C2• connected to the control (CONT) input is strictly for decoupling and has no effect on the opemtion: in some cases it can be left off.
(H)
(4)
(7)
HESET
v",
DfSCH
555
(0)
TliRESH
(3)
OUT
(2 )
>_---<0--""1 TRIG
CONT GND (I)
,,, I
C, 0.0 1pF (dccoopting opI iorulJ
FIGURE 1 - 56
The 555 timer conned:e<:l OIl an astable multivibrator (oscillator).
Initially, whe n the powcr is turned on. the capacitor (CI ) is lU"lcharged and thus the trigger voltage (pin 2) is at 0 V. This cau$Cs the o utput of com pam tor B to be HIGH a nd the output of compamtor A to be LOW. forcing the o utput of the latc h. and thus the base of Qh LOW and keeping the tnmsisto r oft". Now. C I begins charging throug h RI and R2 • as indicated in Figurc 7- 57. When the capacitor voltage reaches '/3VCO cornpamtor B switc hes to its LOW output stale; and whe n the eapacilOr voltage reaches ln Vcc. comparator A switches to its HIGH output state. This rc~ts the latch, causing thc base of QI to go HIGH and turning on the- transistor. This scquencc creates a discharge path for Ihe capacitor through R2 and the tmnsistor, as indicated. The capacitor now begins to disc hUlge. causing eompar'dlor A to go LOW. At the point whcre the capacitor discharges down to ~ l VCC. compamlo r B switches HIGH: fhis sets the latch, making the ba~e of QI LOW and turning off the tmn.sistor. Anolht:r charging cycle be.gins. and the enti re process repealS. The result is a recl
Equation 7-4
THE 555 TI MER
.I I I u" ~
407
----
' Vcr (8)
555
R (6)
+
A
(5)
" I
.~ ~
•
R
R,
I I I I R, I t 2 mCl) (i) , Vcr -rYi!i I + C .j voc --- ___ vc I - ,
(3 )
Q
R
+
S
•
ULf GlGlCllGl
(2)
-- --'" -
,.
V_
(7)
R
fI
(I)
GlGl
Oi schUJl:in!!
CllGlGlGl ~
Q,
(4 )
+
+vcr
FIGURE 1-51
Operation of the 555 timer in the astable mode.
FIGUR E 1 - 58
Frequency of oscillation ill a function of C, and RI + 2Rz. The doped Jines are values of R, + 2R~.
0.01
1--- +----hC-+ ,-------f>-:--+..,----1
0.001
'-----,-'::-_-':-_-:-":-_-,--"_---:"~--c'
0. 1
1.0
10
100
I.Ok
10k
lOOk
f (H~.}
By selccting RI and R2• the duty cycle of the output can be adjusted. Since C 1 charges through RI t- R2 and discharges only through R2, duty cycles approaching a minimum of 50 percent can be achieved if R2 > > RI so that the Charging and dischargi ng times are approximately equal. An expression for the duty cycle is developed as fo llows. The time that the output is HIGH (//f) is how long it takes C 1 to charge from ~/3 \'Cl; 10 2jJ Vcc. It is expressed as t l/
= O.7(R I
+ R 2)C,
Equation 7- 5
The time that the output is LOW (IJ is how long it takes C 1 to discharge from t,!3 VOC to Y, Vcc. II isexpn:.<;sed as
'L= O.7R2C
1
Equ
408
•
LATCHES , FLIP-FLOPS, AND TIMERS
The period, T, of the output waveform is the sum of IN and ' L . This is the reciprocal offin Equalion 7-4.
T=
IN + ' L
= O.7(RI
+ 2R2)C I
Finally. the duty cycle is
Duty cycle "" ( Rl + R2 ) 100'1{ Rl + 2R2
Equation 7- 7
To achieve du ty cycles of less than 50 pe rcent, the circuit in Figure 7- 56 can be modified so that C l charges through only Nl and discharges through R1 . This is achieved with a diode, D l • plac(."(] as shown in Figure 7- 59. The duty cycle can be made less than 50 percent by maki ng RI less than R1. Under this condition. the expression for the du ty cycle is Equation 7-8
R,
Duty cycle = ( RI
) 100%
+ R2
fiGURE 7 - 59
+I'cc
The addition o f diode Dr a UOW\ the duty cycle of the output to be adjusted to /o:! than 50 percent by making Rt < R2•
(4'
.R,
(7)
I
--T+ •
'"
RESJ,T
DISCI!
555
(0' TIfRI-;SU
I t I
(2)
OUT
p':o"_<>
CONT (5)
TRIG GNIJ
C,
",
C '
T om pF
i EXAMPLE 7-15 A 555 ti mer configured to run in the astable mode (osci llator) is shown in Figure 7-f:1J. Determine the frcl\uency of the output and the duty cycle. P'
FIGURE 7-60
+5.5 V
Open file FOl-60 to verify operation.
R, 2.2 kfl
1
RESer
Vee
DfSCU
~;r-
555 THRI-::SU TRIG
i
GND g1n2 }JF
1
01fT
CONTI] C,
I
0.01 pF
TRO UBLESHOOTING
Solution
1.44 (R I + 2 R~ )CI RI
DUlY cycle = ( HI
inCT'ON 7- 6
1.44 = 5.64 kHz (2.2 kO + 9.4 kO )O.022jJ. F
+ R~ ) (2.2 kfl + 4.7kO) + 2R2 IOOOk = 2.2 kO + 9.4 kO 100% = 59.5t,;,
Dctennine the dUly cycle in Figure 7- 60 if a diode is connected acros,'i R2 as ind icated in Figure 7- 59.
1. Explain the difference in operation between an astable multMbrator and a monostable multivibrator.
REVIEW
2. f or a certain astable multivibrator, cycle of the output?
7-7
409
Usc F,qualions 7-4 and 7- 7.
f =
Related Problem
•
tH
= 15 ms and T = 20 ms. What is the duty
TROUBLESHOOTING
II is starxlanl practice to tcst a new circuit dcsignto be sure lhat it is operati ng as specified. New fixed-function designs are "breadboarded" and lested before the design is I1nalized. Thc tcnn breadboard refers 10 a method of lempomrily hooking up a circuit so that ils operation can be vClificd and any fault :. (bugs) worked out before a protOlype unit is built. After completing Ihis section. you should be ablc 10 • Describe how thc liming of a cirellit can pnxlllCC erroneous glilches • Approach the troublcsh()()(ing of a ncw design with greater insight 1UJd awareness of potential problems The circ ui t shown in Figure 7-(1 1(u) gencmles two clock wuvcfonns (a~ K A and CLK B) that have an alternating occurrence of pulses. Each waveform is to be one-half the frequency of the original clock (CLK), as shown in the ideal timing diagmm in part (b).
I
+Va : Q
J
FIGURE 7 - 61
-I
Two-phase clock generatOl' with ideal w.we(orm5. Open file F07-61
eLK A
and verify the oper.ltion.
c
CLK
Q K
I
J
CLK8
(,)
--.l, oj ,
CLK
,, -j, CL K A CLKB (b)
J,, ,,
,
,1
,I
I,
I, I,,
,,, ,
,,
I,
I
410
•
LATCHES, FLIP-FLOPS, AND TIMERS
eLK CL KA
Q
n.KR
CLK A
/;I) OsciIiOlit.~ uisplay ofCL K A anu t."1.K B waveforms with
glitches indicated by the
( b) OscillOSl.:opc displ ay showi ns prop;og;uion delay lhm cremes glitch on el K A waveform
"~pikes".
FIGURE 1 - 62
OICiUOKOpe u ilp'ilyIo f~ the circuit in Figvre 7- 6 1.
When the circuit is lested with an oscilloscore o r logic analyr..cr. the eLK A and eLK B
wavefonns aprear on the display screen as shown in Figure 7-62(a). Since glitches occur on both wavefonns. somelhing is wrong wi th the circuit either in il~ ba~ic design or in the v.'Uy il is connCCled. Further investigatio.!!.reveals that the giilch(.'S arc eaused by a race (.'Ondilion between the elK signill and Ihe Q and Q signals at the inpub o f tI~ AND gates. A.~ displayCll in Figure 7-62(b). the propagation delays beN.cen eLK and Q and Q creatc a short--
I
Two-phone dock generatol uling
+Vcr
negative e
eJimill;}te glitchel. Open file anu ve.-ify the operation.
Q
J
FQ7~6J
1
CLKA
J
ClKB
c
CLK
Q
K
I ("
CLK ~ Q
,, ,'
Q
,,
CLK A
,, -ti- -r-------1 ,
DIG ITAL SYSTEM APPLICATION
/ SECTION 7- 7
•
411
1. Can a negative edge-triggered D flip-flop be used in the circuit of Figure 7-631
REVIEW
2. What device can be used to provide the dock for the circuit in Figure 7-637
-----Troubleshooting problems that arc keyed to the CD~ROM arc available in the Mu ltisim Troubleshooting Pract ice section of the end-of-chapter problems.
The traffic ligllt control ~~tem that w"" ,t:;Irte
was introduced in Cholptcr 6 i, shown olgain in Figure 7-64 for reference.
chapter. In the last ch"'pte<, the combin"'tiOOolllogic w"" developed. In thi, chapter, the timing circvits ",re
Timing C irctJib ReqoJiremenb
developed. Thee cir<:vits produce ol 4.1 time inte,voll for the G)ution light ",nd ol 25 I time intcrvoll for the red olnd green lights. AIIO, a 4 Hz clo<:k lign"" i, produced
the 4 s timer, the 25 I timer, olnu the 10kHz o,ci lJoltor-olS shown in the blo<:k diag... m in Figure 7- 65. The 4. time r and the 25 I timer arc implemented with
by the timing circuits. The 0Ye1<)1I trolffic tight control ¥tem block diolgl<)m that
(a) ",nd (b). The 10 kHz oscillator i,
The timing circuits consi51: of three p
74121 one-shots,)1 sho ...." in Figure 7- 66
Traffic light control logic
Trn nie light and interface u~i l
Combinationallogie AtR
St:fIU(·ntial logic Vehicle
MY
So
K n SOr
MG
S,
input
SR
SY
I I I Shurt limer
SG
Lung Clock ti mer Long trigger
Timing circuih;
Sho rt trigger
-
1
o
COlllplctcd in Chapter 6
0
Completed
FIGURE 7_64
Tl<)ffic light control l}'Item block diagram.
i~ this chaplcr
0
Completed in O tap!cr Il
4 12
•
LATCHES, fLIP- fLOPS, AND TIMERS
implemented with a 555 timer allhown in Figure 1-66(e).
----I
Slumlnr-;:cr
System Auignment • Activity ' Determine the extemal R and C v.;,luei for the 4 I tJmer in Figure
----I
" 01111 nll1f'cr
1-('6(a). • Activity 2 Determine the external R and C valuo fOf the 25 I timer in Figure 1-(,6(b).
• Activity J Determine the R anJ C v.;,Jues for the 10 kHz 555 ow"lIator in Figure 1-66(c).
FIGURE 7-65
Block diagram of the timing a"rcvib.
A, A.
8-
"
&
.1,
I.n. Q
ff
&
I n.
A, R
Q
ex
RXJCX
(61
R,
Q RI
(7)
ff CX
RESJ:.T
RXlCX
I
-
Vcr
DlSCf/
555
1""R£SII
'" nne
Q RI
(8)
'"
R,
C '
our CON"/"
GND (I )
(3)
'"
e, -- om pF
I
(
1'<0
Ibl 25 s lilllcr
(a)4 s limcr
Ie) 10 kJ 11. oscjll ~wr
F'GUR£ 7-66
The timing circuits.
G litches that OCCur in d igibl I)1tems are ve'Y fast (extremely short in duration) and can be difficu lt to see on an oscilloscope, particu la rly at lowersweep rates. A logic ana lyzer, however, Ciln show a g litch ealily. To look for glitches using a logic ana lyzer, select · ' atchH mode Or ( if available ) transitional sampling. In the latch mode, the analyzer looks for a voltage level Change. When a change occurs, even if it il of extremety short duration (a few nanoseconds), the informatiOn is · 'atched~ into the analyzer's memory as another samp led data point.. When the dat.:! are d isplayed, the glitch will show as an obvious change in the sampled dat.:!, making it easy to identify.
K EY T ER M S
• FIGURE 7-67
•
413
Symbols for latches and ni p- nops are shown in Figure 7- 67.
n 'n Qn °n ° V v : v : =[J-Q LJ-Q n : -rJ-Q n : fI: =[J-Q R
EN
o
OR
(a) Acti ve-HIGH input S-~ latch
(b)
R
~,:!ivc-lOW
Q
;npl,t
R
EN
0
Q
(c) Gated S-R lalch
(d)
GalL..I O la/cit
S-R latch
Q
= - - G K J,- Q
-=0-. °
(e) S-R cdgNriggcred
{f}
KEY TERMS
O oogc-triggcred nip-nop.~
nip-naps
(gJ 1- K edgc- trigg~ed
n ip-flop,;
•
LUlcht:s all: bistable dt:l' iL-es wllOSt: SI3\t: nonna lly depends on asynchronous inputs.
•
Edge-hi gb'Crcd nip-n ops arc bistab le Oevices wi th synchronous inputs whose sta te depends on the inputs only at the Iriggeri ng transi tion of a clock pu lse. Changes in the outputs occur at the trigge ri ng tnll1sition of the clock.
•
Monoslable mu ltivibrmon; (one-shots) have one slable SlatC. Whe n Ihe one-shot is triggered, thc Olll!lut gc:es to ils ul1swhle stale for a timc determined by all RC circuit.
•
Astable rnultivibraTors have no stable Slates and arc used as oscillators to generate liming wavefonns in digital systems.
Key terms and other bold
term~
in the chapter are defined in the e nd-of-book glos",ry.
Astable Having no stable state. An aSla blt: muh ivibnltor o~il l ales between two quasi-stable stales. Bistable Having two stable states. fl ip-Ilops and latches arc bistable mu ltivibralors. Clear An asynchronous inpulused to rcsel a nip-flop (make the Q nu lput 0). Clock TIle trig ge ring input of a nip-nop. D nil>-nop A type of bistable mu lti vibrmor in which Ihe Oltlput assumes the st~le of the the triggering edge of II clock pulse.
f)
inplll on
Edge- tri ~cn'd nip-not) A Iype of ni p-flop in wh ich lhe data arc entered and appear on the output on the same clock roge.
Hold time The lime interl'al required for the controllel'cls to remain on the inplls 10 a nip-- nop after Ihc lriggcri ng roge of the clock in ordcr to n::liably activatc the dcviCt:. J -K fli p.nop A type of ni p-nop thaI can opc!r".lle in Ihe SE""[ RESET. no-c hange, and toggle 1ll00es. Latcb A biswble di gi tal circuit used for sloring a bit. Monosta hlc Havi ng only one stable stme. A monoslablc Illullivibra tor, commonly called a one-sllOl, produCt:s a single pulse in response to a triggering in put. O ne--shot A monostablc mullivibrato r.
4 14
•
LATCHES, FLIP- FLOPS, AN D TIMERS
Powe r d issipalio n The amnunt of power lequiretl by
iI
ci rc uit.
Prcsc:1 An asy nc hronous inpul used to SCI a ni p- nop (make the Q OUIp!.lt 1). P ropag31iOl1 dela}' lime The inten'~11 of time req uiretl ilfter il n input signa l has been opplied fo r Inc re~u ltin g ou tpul c hilnge 10 occur.
RES ET The stille o f il ni p- no p
Of
liltc h whcn the ou tpu t is 0; the actio n of producin g
0
RESET
state.
SET llle sUite of a n ip-flop o r hitc h whe n the outpu t is I . the actio n of producing a SET state. Sel-up time TIle lime interva l re(lllired for the cont rol levels to be o n the i nput~ 10 a digital circuit. such as a ni p-flop. pri nr In Ihe Iri gge ring etlge of a clock pu he. SYlle hronllu s Hav ing a fixed time rcliltions hip. T imer A ci rc ui l lhat co n be used a~ a o lle-sho l o r as an osci ll ator.
Toggle '1l1e aclion of a ni p-flop w hen it c ha nges SUite on e'.lch cloc k pu lse.
Answers are a t the e nd of the
I . If an S-R latch has iI I 011 Ihe S inpu l a nd a 0 o n the R input and the n the S input goes latc h will be (a) set
(b) reset
(c) inval id
(d) clear
10
O. the
2. The inva lid slate of a n S-R latc h oc'Curs whe n (a)
s=
I.R = O
(c) S = I. R = 1
(b) S=O, R = I
(d) S = O. H. = O
3. Fo r a gated D latch. the Q ou tput Ol lways eq uals Ihe D input (11 ) before Ihe e nable p!.1[se
(b) during the enil ble pu lse
(e) im med imcl y afte r the e nab le pulse
(d ) a lhwe l'S (b) a nd (c)
4. Like the latch. the nip- flo p be long.~ to IT category 0 1' logic circu its known as ( a) rnonostable rnul livibraton;
(b) bistable muli ivibmtors
(c) astable l11ult ivibrntors
(d ) olle-sho ts
5, The purpose of the d oc k inpu t 10 1'I fli p-f1o ll is to (a) clear the dev ice
(b, sct the device (c) ulwuys (';lUse the output to change stilles (d) cause the OIllp!.lt to ussume a slate dependent on the controlli ng (S-R. J-K. or D) inputs.
6. For an edge-tri ggeretl D nip-nap. (a) a change in the SIMI.' of the n ip-flop cun OCCur o nly at a clock pulse edge
(h) Ihe s tat e thM Ihe ni p-n op ~oes 10 depends o n the D input (e) the ou tpot follow:. the input at eilc h d oc k pulse
(d) all of these HllSw ers 7. A feature that d i Sl il1~u ishes the J-K !lip-nop from the S -R ni p-nop is the (a) togg le cond ition
(b) presel input
(e) type of clock
(d) clear inllut
8. A ni p-nop is ill the togg le co nd iti on when (a) J = I. K = O
(bl J= I.K = I
(c) J = O. K = O
(d ) J = O, K = 1
9. A J-K n ip- flo p wi th J = I and K = I has a 10 kHz clock input. .Il1e Q outpu l is (a) cons ta nt ly HIG H
(b) co nSlantly l OW
(c) a 10 kHz SQlIllre WH\'f:
(d )
(l
5 kHz sq unre wave
PROB LEMS
•
41 5
10. A one-shot is II type of (a) monostable mu ltivibmtof
(b) astable mult ivibr.ttQl"
(d) answer.; (a) and (e)
(e) ,lI1swers (b) and Cc)
(e) timer
II. The output pulse width of a non retrigge rabl e one-shot depends on (1I) the trigger intervals
(e) 3 res istor and CilIlliCiIO(
(b) the suppl y volt3b't: (d) the threshold voltage
12. An astable muli ivi bralor
PROBLEMS SECTION 7 - 1
(a) requ ires a period ic trigger inpu t
(b) has no stable state
(el is an oscillator
(d) produces a periodic pulse ou tput
(el answers (a). (b). (e), and (d)
(I) answers (b). (e). and (d ) only
Answen to odd-numbered problems are at the end of the book.
Latches J. Ir the wavefor ms in Figure 7-68 ale applkxlto an [!(:tive· LOW input S-R l~tch , draw the resulting Q out put wal'efonn in rt:lmion to the inputs. Assume tllm Q starts lOW.
FIGURE 7- 68
s
s
Q
R
Q
R
2. Solve Proble m I fo r the in put waveforms in Figure 7-N) applie
FIGURE 7 - 69
s R
3. Solve Problem I for the input wavefonns in Figure 7-70.
FIGURE 7-70
- ~ ,,-------------------,,-
S
H
H
I t
I I
R
4. r'Qr a gated S-R la tch. dete rmine the Q and Q oUlpul<; for the inputs in Figure 7-7 I . Show them in proper rel~tion to the enable inpu t. Assume that Q starts LOW.
FIGURE 7 - 71
S
EN R
I, ,
~ ,
I
S
Q
EN R
Q
416
•
LATCHES, FLIP-FLOPS, AND TIMERS
S. Solve Problem 4 for [he inpulS in Figure 7- 72. 6. Solve Pmhlcm 4 fnrthc inputs in Figure 7- 73.
EN
s R
______~r-lL________
FIGURE 1-12
s
R____
~nL
______
~~
FIGURE 1 - 11
7. Hlf a gatecJ 0 latch. the waveforms shown in Figure 7- 74 are observed 011 its inputs. Draw the timing dillgram showing the OUtput w:wefonn yOll woulcJ expcct lO sec llt Q if the latch is initially RESET. FIGURE 7 - 14
EN D
SECTION 7-2
---.---fif-;------,,rl,1 ••• • • •
Edge-Triggered Rip-FlopJ 8. Two edge-triggcred S-R flip-flop: are shown in Figure 7- 75. If the in puts are as shown. draw the Q output of each flip-flop relat i\'c to the dock. and explain thc difference between the two. The flip-flops are initiall y RESET.
S
eLK
s
eLK
R
C
R (,)
S
Q eLK
Q
Q C
R
Q
fb)
FIGURE 1 _ 75
9. 'me Q omput of an edge-triggered S-R flip-flop is shown in relation to tht dock signal in figure 7- 76. Dctcnninc the input wavefoons on the Sand R inputs that llle requircd to produce this ou tpu t if the nip-flop is a posi tive edgc-triggered type. FIGURE 1 - 16
eLK
Q
10. Draw the Q output relative 10 thc clock for a 0 flip-flop with the inpUL'i as shown in Figure 7-77. Assume positi veedge·tri ggcring and Q initiall y LOW.
e LK
,, . D ~L-
,
FIGURE 1-11
_ _---'
PROBLEMS
II. Solve Prob lcm Ifl for the
input~
•
417
in Figure 7- 78.
e LK
D
FIGURE 7 - 78
12. For a positive (."(\gc-tri g,!!cred J-K nip-nop wit h inpu ts as shown in Figure 7-79. detcnninc th e Q output relativc to the d ock. Assume that Q starts LOW.
FIGURE 7-79
e LK
-fL-f"L -fLf1--f1---f1-I
J ~ I
K
!
I
!
!
!
'~ ' ---i-'- -
r ': ,, ,,, ! ,~
I
, ,, !
I
, ,
:
I
, ,
,
!
13. Solve Problcm 12 for the inputs in Figure 7- 8fl. 14. Detcrmine the Q wavcfonn relalivc to the clock if thc signals shown in Figure 7- 8 \ are applied 10 the inputs oflhe J-K flip-flop. Assumc Ihal Q is inilially LOW. 15. For a ncgative edge-triggered J-K n ip-n op wilh thc inputs in Figure 7-82, develop the Q output waveform re lative 10 the dock. Assume that Q is initially LOW. FIGURE 7-80
eLK 1 _ _ __
--1
_
K _ _ _ _ _ _--'
FIGURE 7 - 81
eLK
PRE
1 I
I
!
I
!
I
K JLJ~ ! I
PRE
! I
- - - iLJ
I I
':
, , LJ
_ _ _ _ _ _ _ _ __ _- - :'
CUi FIGURE 7- 82
e LK 1
K
,
Q
e
I I
:
-
1
Q
K
c' _ _ __
eul
418
•
LATCHES. FLIP-FLOPS. AND TlMER.S
16. The following serial data arc applied to the flip.flop through the AND gales liS indiCilted in Fi¥u rc 7-83. Determine the resultin g serial data thm appear on the Q output. lbcre is one dock pulse for each bit time. Assume that Q is initiillJy 0 and that PRE and CLR are HIGH. Rightmost bits arc applied fi rst.
J l : 10100 I I
h:O I 110 I 0 h
l l llOOU
K1:OOOI I IO K~ : IIOIIOO
K J : 10 10 1 0 I FIGURE 7 - 83
PRt: J, J.
J.
Cl K A, A. A.
---1
)-
r---- Q
J
C
---1
)-
K
P- Q
WI
17. f"Or the circuit in Figure 7-83. completc the timing diagr.lm in Figure 7- 84 by showing the Q output (which is initially LOW), Assume PRE and CLR rema in HIGH. FIGURE 7 - 84
elK J, J, J, K, K, K,
- l, ~
18. Solvc Pmblcm 17 wit h the same J and K inputs but with the PRE and CLR inputs as shown in Figure 7- 85 in relation to the clock. FI GUR E 7 - 85
elK
CLR
SECTION 7 -3
Flip-Aop Oper.tting Char.tcteriJtics 19. What detcrmincs the puwcr dis_~ipat ion of a nip-flop'! 20. Typically. a manufaclurer's data sheet spcci fic.~ fou r different prup.:lgation delay limes associ3led with a fl ip-flop. Name and describe each one. 21 . The oatl! sheet of a eenain flip-flop specifics Ih31 the min imum HIGH time for the clock pulse is 30 lIS .:lnd the min imum LOW time is 37 ns. What is the mruo:imum opcrJting frequency?
PROBLEMS
•
419
22. The flip-flop in Figure 1-86 is initially RESET. Show the re lation octwee(] the Q OIltput and the ctlx;k pul~ if propagatioll delay f,'U1 (ctock to Ql is 8 ns.
FIGURE 7 - 86
-
J
0
c
eLK K
o
23. The di rect cu rrent rcquirc
24_ For the cireuit in Figure 7- F:1 . determine the maximum frequency of the clock signal for reliable operation if the set- up time for each nip-nop is 2 ns and the propagation delays (It'LlI and ' PIIL) from ekx:k to output are 5 ns for each flip-flop.
FIGURE 7 - 87
HIGH
Q, J,
J,
C
f--
C- P.C
-
0, K,
K,
Flip-nopA
P-
!-l ip-nop B
eLK
SECTION 7- 4
Aip-Flop Applications 25. A D flip-flop is connected as shown in Figuit 1-88. Detern line the Q output in re lation to the clock. What specific function does this dev icc perform?
FIGURE 7-811
-
Q
D
e
~ 26. For the circuit in Figure 7-87. deve lop 11 timing diagram for e ight clock puiscs, showing the Q. . and Qs outputs in relat ion to the dock.
SECTION 7-5
One-Shots 27. Detennine Ihe pulsc width of a 74121 one-shot if the ex ternal resiStor is 3.3 kO ami the extemal capacitor is 2000 pF. 28. An out put pul:<.c of 5 p.s duration is to be generated by a 74LSI22 une-shOL Using II cap
420
•
lATCHES, fliP-F LOPS, AND TIMERS
SECTION 7-6
The 555 Timer 29. Create a one·shot,
u~ ing
a 555 timer that will pmduce a 0.25 s out put pulse.
30. II. 555 timer is configured 10 run Determine ilS frequency.
a~
an a~table Tnul tivibratof as shown in Figure 7- 89.
FIGURE 1 - .119
1(4) (8)
I"~,
F'~ 7)+_~
H, 1.U Ul
H,
2.2 1.:0
(6)
..Q.1. '
=
(5)
J
=C
4:-'''''''-" -=!="
L ---"
0.01 pF
3 1. DelCrmine the values of the ex tcrnal resiStOfS fOf a 555 timer u.<;(:{l as an astable mullivibralOr with an oUl put (r<-'"(Iueney of 20 kH z. if the extcmal eapilcitof C is 0.002 p. F and the duly cycle is to Ix: approxima te ly 75%.
SECTION 7 - 7
Troublelih ooting 32.
flip-tl op in Figure 7- 90 is tested under al l in pu t conditions properly? If out, what is the mus lli k.c ly raull'!
°nlC
.. -fLf1---f1---rl , , ~ ,
J
-fU1-Jl--fl-
c '--
Q
t' --'---
c
0-
K
K
j
Cal
(b)
-
--"-
J
JLJL.nSL I I I I I
shown. Is it opcntting
.v
0- J
I I I I I
a~
-fl--fl--fl--rl
c 0- K
F
0-
I I I I
I I I I
I I I I
I I I I
j
r---u---L
(0)
Cd) FIGURE 7 - 90
f-".-
J
c
.v -
K
p-
PROBLEMS
•
421
33. A 74HOX) quml NAND gate Ie is ust:d to construct a gated S-R latch on It protoboard in the lab as shoWI] in Figure 7- 9 1. The schematic in part (a) is used to conn(.>(:t the circuil in Pill1 (b). When you try to operdte the latch, yUIJ find thaI the Q output slays I-IJGH no maner what the inputs arc. Deter mine the problem. 34. Determine irt he flip-flop in Figu re 7- 92 is operating properly, and if not. identify the most probable fau lt
"
S
(4)
GND
V
(6)
(5)
...
Q R
(2) (3)
(I I )
R
Q
•
»
EN
•• •
'b'
(,)
)
• ••
ST:
EN
( I)
~
FIGURE 7 - 91
J
e lK
~
-'
1 :1
: Lr-J I
I
: I
I f: !L,.-1I f: !L.-
~ I
I
I
I
I
I
I
IlstrtrLrtrtrtrt I
I
I
I
J
I
I
:
:
I
I
, n '
" I
"
L . -J _
:: I
I
IL_i--__i--
J
-
Q
- 4>c K
Q
Q FIGURE 7 - 92
35, The pmallcl data storage circoit in Figure 7-36 docs not operate properly. To check it out. you fin;t make sure that Vee and ground are connected. an d then you apply LOW lcvcls to all the D inputs and pulse the cluck line. You check the Q outputs and find them alltt} be LOW: so far, so good. Next you apply I-UGHs to atl the J) inputs and agai n pulse thc cluck li nc. Whcn you check the Q outputS, they arc still all LOW. Whm is the problem. and what procedure will you use to isolate the fau lt to a single device?
422
•
LATCH ES, FU P-FLOPS , AN D Tl MER.S
3(1.
.5V
Thc flip -flop l:ircuil in Figure 7-93(a) is used to generate a bi nary c(}Un t sequcnce, 'me gales form a decode r that is supposed to produce a HIGU when a binary zero or a bi nary three stllte occurs (00 or I I), Whe n you ched the QA and Qn outputs, you get the display shown in part (b), whi" h fCveals gli tches on the decoder ou tput (X) in addition to Ihe corre<:t pulses, What is causing these glitches, and how can you eliminate them?
elK
.5 V
Q,
elK
Q"
J,
J,
x
e
e Q, K,
Q,
Q, K,
,
,
,
Q' ~,
I,
,I
X
,b,
(,'
I,
Glitch
I, H Glitch
FIGURE 1 - 93
37_ Determine the QA' QB and X outputs over six cltx;k pulses in Figure 7--93(a) for each of the following faults in the TIL circuils, Start wilh both Q1\ and Q/J LOW. (a) 1,., input open
(b) KIJ input open
(c) Q/l Outpolopen
(d) clock input to Hip-nOll B shOrteti
(c) gate
G~
O\llput open
38. Two 74 12 1 one-shots arc connected on a ci«.'uil board as shown in Fig ure 7-94_After observing the oscilloscope display, do you CQ(lcludc that the circuit is operating properly? If nOI, whal is lhe most li kely problem?
FIGURE 1 - 94
O_47J1F
0.22.-
47 U1
47'"
I'oc
CD
Q; GND
Digital System Application 39. Use 555 lime rs 10 implemenl lhe 4 s and the 25 s one'shots for the timing circuits portion of 'he ITartie l i~ht control system. ' [lle triggcr inptJt to Ihe 555 cannot slay LOW after its negative-going Imnsilion,."O you will have 10 develop a cirellit to produce very short neg.1 tivegoing pulses to (rigger Ihl: lOll!; and short timers when Ihe syslCm goes into each state.
ANSWERS
•
423
Special Design Problems 40. Devise a basic cOOllt ing ci rcuit that produces a binary Sl.-'(jucnce from zero throug h using negative t'dge-triggercd J-K flip-flops.
~cven
Ily
41. In the shipping department of a softball factory, the Ilalls roll down a conveyor and through a c/l ule single flIe into bo)(es for shipmcn\. Each ball pass ing throug h the chute activates a switch circuit that produces an electrical pulse. The capacity o f cach box is 32 ball s. Desi gn a logic circu it to indicate w hen a bo)( is fu ll so that an emply box can be movc d il1lo position. 42. List Ihe des ign challges that wou ld be necessary in Ihe traffic lig ht con trol sys tem to add a 15 s left tum arrow for the main st1'l:el. 'Ibe tum arrow will occur aft er the reO light and prior to the green lig ht. Modify the state diagram from Chapter 6 to show these changes.
Multisim Troubleshooting Practice 43. Open file P07-43 and test the latches to determine which o ne is fault y. 44. Opcn file 1'07-44 and test the J- K nlp-nops to dt-tenn ine which one is fau lty. 45. Open nl e 1'0 7-45 and test the D flip-flops to dctennine which one is faul ty. 46. Open file 1'07-46 and test the o ne-shots 10 de termine which one is faulty.
47. Opcn fil e 1'07-47 anll test the di vide-by-four circuit to determi ne if there is a faull. If there is a fault. identify it if possible.
SECTION REVIEWS SECTION 7 - 1
latc:hes 1. ' In ree typt'§ of latches are S-R, gated S-R. and gated D.
2. SR = OO, NC;SR = UI.Q = O;SR = IO.Q = I;SR = II . invalid 3.
SECTION 7-2
Q ~
I
Edge-Triggered Flip-Aops I. The out)Xlt of a gated S-R latch can change any time the gate enablc (EN, input is act ivc. ' 111e ou tput of an edge-triggered S-R flip. nop can change o nl y o n the triggering edge of a clock pulse.
2. The J-K !lip-flop doe; not have an inva lid slale as docs the S-R flip-nop . 3. Output Q goes HI G H on the trai ling t-oge of the first clock pulse. LOW on the trailing edge of the second pulse, HIGH on the tm il ing edge of the third )Xllse, and LOW o n the !railing edge of the fourth pulse.
SECTION 7 - 3
Flip-Aop Operating Characteristics I. (11.) Sct-up time is the time rcquirt'"
SECTION 7-4
Aip-Flop Applications 1. A g roup of data stornge Ilip-Ilops is a register. 2. For di vide·by-2 operation. the nip-Ilop must togg le (J = I, K = I). 3. S ix flip. no ps are uscd in a divide·by-64 l1evice.
424
•
LATCHES, FLIP- FLOPS, AND TIMERS
SECTION 7-5
One-Shots I. A nonretri ggerable one-shot times OUI befvI"C it can fCSpt)nd to another trigger input. A relri ggcrdble one-shot res(XJnds IV each (rigger inpul.
2. Pulse wid th is ....::1 wit h extemal R anll C compt)nents.
SECTION 7- 6
The 555 Timer I. An astable multivi brutvr has no slab le state. A monustable multivi brator has one stable stale.
2_ Duly C)1:1c = (15 ms/20 ms) I00% = 75%
SECTION 7-7
Troubleshooting I. Yes.
~stablc
u~d.
multivibrator using a 555 timer can be uscrl to provi lle [he clock.
RELATED PROBLEMS FOR EXAMPLES 7-1 TIle Q vutput is the same as shown in Figure 7- 5(b).
7-2 Sec Figure 7-95.
7-3 Sec Figure 7- 96.
7-4 See Figu re 7- 97.
7-5 See Figure 7-98.
FIGURE 1-95
,,, S , ,
FIGURE 1-96
eLK
R
,
,
,,
,
Q
if----j
Q
LJ-1
FIGURE 1 - 91
FIGURE 1 - 98
A NSWER S
7-fJ &'C Figurt: 7- 99.
7- 7 Sec Figure 7- 100.
7-8 Sec Figure 7- 101 .
7-9 Sec Figure 7- 1OZ.
•
425
eLK K
J Q
,,,
....!........J
FIGURE 7 - 100
FIGURE 7 - 99
l'IN l t l e L K) l'IN2( IJ)
e LK
CLR
,
l'IN 3 ( IK)
~
--lJ ,'
,
:r:,,
~ '
11;::::::~~=+==+==t~---L-
PRE -;:
l'IN 5( I Q)
Q
FI GURE 7-10 2
FIGURE 7 - 101
7- 10 Z, = 32. Five n ip- nops arc requin.-o. 7- 11 Sixlccn stales require fou r nip- nops (2' = 16). 7-12 CIOn = 7 143 pF connectl-o from CX to RX/CX of tl1l: 74121. 7- 13 CF.XT = 560 pF, R,~" = 27 kfl. See Figure 7- 103. 7-14 H, = 9 1 kfl 7-15 Duty cycle
~
32%
FIGURE 1 - 103
74 L..<;[22 &
,"
~
Q - - Qulpu! 1"'1",
Q
ex
HX/CJi.
(10)
(11 )
C£XT
R,.xT
S6Ill'F
27 ~n
SELF-TEST I. (a)
2. (e)
3. (d)
4. (b)
9. (d)
10. (d)
II. (e)
12. (f)
5. (d)
6. (d}
(6 )
7. (a)
I!.(b)
cou CHAPTER OUTLINE
CHAPTER OBJECTIVES
8- 1
Asynchronous Counter Operation
8- 2
Synchronous Counter Operation
DeKribe the difference between an asynd'IJOI"lOU' and a Iynchronous counter
8-3
Up/Down Synchronous Counters
Aoal)re (o.mtel' timing diagrams
8- 4
Oesign of Synchronous Counters
8- '
Cascaded Counters
8- 6 8- 7
Counter Decoding
8- 8
Logic Symbob wit'" Oependency Nobtion
8- 9
Troubleshooting
IJ:C
Digital System Application
•
•
~Iyze counter draJib
Expbin hoI.v prop<>gation del..ys affed the operation of a counter
Counter Applications
Determine the modulul of a countCf •
Modify the modu'm of a covnter
•
Recognize the difference between a 4- bit binary counter and a dec
Use an up/down counter to generate forward and reverse binory sequences Determine the sequence of a counter Use Ie counter! in vari01JI applicaboos Design a counter that will have any 1pe
KEY TERMS Asynchron(XJs
Terminal count
Recycle
St.:Ite machine
Modulus
Stilte diagram
Decade
Cascade
Synchronous
INTRODUCTION As}Uu learned in Chapter 7, flip-flops can be connected together to perform counting operations. Such a group of flipflops is a counte r. The nu mber of flip-flops used and tne way in which they are connected dete«nine the number of state: (called the mod ulus) and also the specific sequence of stiltes that the counter gQej through during each complete cycle. Counters are classified into two brO
•••
74XX93
74XX161
74XX162
74XX163
74XX190
74XX47
DIGITAL SYSTEM APPLICATION PREVIEW
The Digital S}'1tem Application illustrates the concepts from this chapter. It continues the traffic light control s}'1tem from the last two chapten. The focus in this chapter is the sequential logic portion of the ~tem that produces the traffic light iCquence ba~d on inpub from the timing circuib and the vehicle sensor. The portions of the sy'5tem dC'v1:!loped in Chapters 6 and 7 are combined with the Jequentiallogic to complete the s}'1tem.
VUlT THE COMPANION
Study aid, for thi, chapter are available at http://www.prenhall.com/floyd
427
428
•
8-1
COUNTERS
ASYNCHRONOUS COUNTER OPERATION The lcrrn asynchronous refers to evc nt ~ that do not have a fixed time relationshi p wilh each other and. gCllcrally. do not occur at the same timc. All asynchronous counter is one in which Ihe nip-nops (FF) within thc counter do not change stales at exactl y the same time because they do not have a common clock pulse. After complcting this section, you should be able to _ Describe the operation of a 2-bit asynchronuus binary counter _ Dt::sl:ribc the opCr.ltion of a 3-bit asynchronous binary counter _ Define r;f)ple in relation to counters _ Describe the operation of an asynchronous decadc counter _ Develop counter timing diagrams - Discuss the 74LS93 4-bit asynchronous binllry counter
A l -Sit Asynchronous Sinary Counter The clock input of an asynchronous counter is ah.v¥ connected only to the l5B flipflop.
Figure 8- 1 shows a 2-bi t counter connected for asynchronous operation. Notice thai the dock (ClK) is applied to the dock input (0 of Oll/Y the lirst flop-nop. FFO. whi c~ is always the Ie-1st s i~n ili cant bit (lSB). The second flip-flop. FF I. is triggered by the Qo output of A"O. FFO changes state at the posili ve-going edge of e~h clock pulse. but FF I chan~es only when triggered hy a positive-going lransition of the Qo output of FFO. Because of the inherent propagation delay time through a flip-nop, a transitiun of the input dock pulse (ClK) and a lransilion of the Onoutput of FFO l:an never occur at exact ly the same time. Therefore, the two nip-flups arc never simultaneously triggered, so the counter operation is asynchronous.
FIGURE 1-1
H tGH
A 2-bit. ;Jolynchrooous bir'l
FFO ~
elK
C-
J,
JLJlJLJL
FFI
C
-
K,
~
Q,
Q"
I
C-
J,
Q,
c -
K,
The Timing Diagram Let's examine the basic operation of the asynchronous counter of Figure 8- 1 by applying four clock pulses to FFO and obscrv in~ the Q output of each nipnop. Fi ~ ure 8- 2 illustrates the changes in the stmeofthe nip-flop OUlpUIS in response to the dock pulses. Both flip-flops are connected for toggle openllion Ii = I. K = I ) and are a~ sumed to be in itially RESET (Q LOW). FIGURE 1 - 2
Timing diagram fo r the CO<.Inter of
Figure 8-1. AI in previous crnptcrs.
output W;JoVe(Ol~ Me Ihown in green.
r Outpll!~ J Qu (L SB)
l
Q, (MSB)
Asynchronoul countefl are allO knOIMl M ripple counreu.
J ------'
The positive-going edge of elKI (dock pulse I) causes the Qo output of FFO to ~o HlG I·I, as shown in Figure 8- 2. At the same lime the Qu output goes LOW. but it has no ef-
ASYNCHRONOUS COUNTER OPERATI ON
feet on FFI because a positive-going transition must occur to trigger the flip-flop . After the leading edge of C!:K I , Qo = I and Q, = O. The positive-going edge of CLK2 causes Qo to go LOW. Output Qo goes HIGH and triggers FF I. causing QI to go HIGH. After the leading edge of ClK2. ~= 0 and QI = I . 'nle pOSitive-going edge of elK3 causes Qu 10 go HIGH again. Output Qo gl.lCS LOW and has no effect on FF I. Thus. after the leadi ng edge of ClK3. Qo = I and QI = I . The positive-going edge of CLK4 eauses Qo to go LOW. while goes HIG H and triggers FF I, causing QI to go LOW. Afler the leading edge of CLK4, Qo = 0 and QI = O. The counler has nOw recycled to its original slate (both t1ipflops are RESET). In the timing diagram. the waveforms of the Qo and Q I outputs arc shown relative to the clock pulses as illustrated in Figure 8-2. For si mpl icity. the tmnsitions of Qo- Q,. and the clock pulses are shown as simultaneous even though this is an asynchronous counter. There is, of course. wrne small delay betwccn the CLK and the Qo transition and between the transition and the Ql transition . Note in Figure 8- 2 that the 2-bit counter exhibits fou r different states. a~ you would expect with two flip-flops (2 2 = 4). Aloo, nOlice that if Qg reprcsellls the lca~ t significant bi t (LSB) and Ql represents lhe mOSI sign ificant bit (MSB), the sequence of cou nler slales represents a sequence of binary numbers as li sted in Table 8- 1.
•
42~
00
00
CLOCK PULSE
•
•
Initiall y
()
()
TABLE 8-1
Bi...... ry ltate le
()
2
()
3
I ()
()
Since it goes through a binary sequence. the counter in Figure 8- 1 is a binary counler. II actually counts the number of clock pulses up to thrcc. and on the fourth pulse il recycles 10 its orig inal slate (Qo = 0, Q l = 0). The tcnn recycle is commonly applied to
counter operation : it refers to the transition of the counter from its fi nal state back to its origi nal slate. A 3 - Bif Asynchronous Binary CDunter Thc stale sequence for a 3-bit binary counter is I.is{ed in Table 8-2. and a 3-bil asynchronous binary coumer is shown in Figure 8-3(a). lllC basie Opci
CLOCK PULSE
•
•
•
Initi ally
()
()
()
J
()
()
2
()
3
()
4
()
" "
5 6 7
8 (rccydt:s)
"
"
" " ()
TA BLE 8 - 2
State ~quenre fOf" a 3-bit binary counter.
In digital lOgic, On is alwa)ll the l5B unless otherwise specified.
430
•
COUNTERS
fiGURE 1 - 3
111m I
.-
Th ree-bit
OK
FFO ~
-
(./"
.-
C ~
....1'1 J,
-
C Q
K,
I
~
FF2
K,
(.I.
~
-
J,
c
~
-
K,
eLK
n
o n
o
n
~
n
,,
I
n
L
(b)
Ik"t:ydc_
ba.:~ ." 0
states, due to its three n i p- nop~. A ti ming diagmm is shown in Figure 8-3(b) for eight clock pulses. NOIice Ihm the COunier progresses thm uJ;l h a binary count of 7.cro through seven and then recycles to the zero stale. This counler can be easi ly exp.anded for higher count, by connccting additional toggle nip-nops.
Propagation Delay Async hronouscounleno arc commonly rcfencd 10 as ripple counters [or the [ollowing reason: The elTeel of fhe input clock pulse is first '·felf' by FFO. This effect cannot gel to FFI immediately becausc of the propagUlion delay through FFO. Then there is the propagation delay through FFI before FI-""2 can be triggered. Thus, the effect of an input clock pulse "ripples" through Ihe counter. taking some time, due to propagat ion delays, In reach the last nip-nop. To iilusll1lte, notice that all three Ilip- flo~ in the counter of Figure 8-3 change state on the leading edge of CLK4. This ripple d ocking effect is shown in Figure 8-4 for the tlrsl four dock pulses, with the propagation delays indicated. The LOW-ta-HIGH transition of Qu occurs one delay time (f"W) after the pOsitive-going tmnsition of the clock pu lse. The
FIGURE 1 - 4
Prop<>g
Q, Q1
-w----t-r-~i1~m ,
! , ---
-tc,C-------_+,~,,------------------~,-+,~,
--: i
" '111 IOXlnOn'
i i
.: - II'I/{I~_ KwQn ' if" ' I, Wn lu Q 1,
l
- : iii- 'NII (CLKltlQ,, 1 i ::T '''111 IQu lOQ IJ i i : :-''',11 (Q. tnQ , 1
ASYNCH RONOUS CO UN TER OPERATI ON
•
431
LOW-H>:!-IIGH transition of QI occurs one delay time (t1>Uf) afte r the positive-goi ng transition of (1. The LOW-to- HIGH transition o f Q 2 occurs one delay li me ('PUi ) after the positive-going transition of As you can sec. FF2 is lIot triggered lInt iltwo delay times after the posit ive-going edge of the clock pulse, CLK4 . ThllS, ittakcs three propagat ion delay limes for the effect of Ihe clock pulse, CLK4, to ripple through the counter and change Qz from LOW to III GH. This cumulative delay of an asynchronous counter is a major disadvantage ill many applications because it limi ts the rate at which the counter can be clocked and creates decoding problems. The max imum cumulative delay in a coun ter must be less than the period of the clock wavefonn.
'01.
I
EXAMPLE 8 - 1 A 4-bit asy nchronous binary counter is shown in rigurc g-5(a). Each nip-flop is negative edge-triggered and ha.<; a propagation delay for 10 nanosecond. (ns). Oc\'Clop a liming diagram showing the Q ompul of each flip-flop, and determine the total propagatio n delay ti me from the triggeri ng edge of a clock pulse unti l a correspond ing change can occur in the state of Q3. Also determine the max imum clock frequency at which the counter can re operated.
tilGU
l
A'TI
f- J"
I
FF I
f- J,
c
eLK
c
'----- K,
'-----
FF]
FP1
l
f- J, c '-----
K,
1
~
c -
K,
!:':..
J,
K,
(, )
eLK Yl--J21-filrJ4l-fslJ6l..l1l...fs1-J9·~I~W 4~~~i_ 1 1
Q" Q, Q,
Q,
1 I
1 1
1 1
1 1
1 1
1 I
1 1
1 1
1 1
1 I
1 1
,,
,,~ ~ L
(b)
FIGUR£ 8-5
Four-bit Mynduonous bini'lry cou ntef i'lnd its timing dii'lgr
432
•
COUN TERS
Solution
T he timing diagram with delays omined is as shown in r igure 8- 5(b). For the t()(al delay ti me. the e ffee l of eLKS or CLK 16 must propagate throug h fo ur flip- nops before Q.l changes, so
'pi,.,., = 4x IU ns = 40ns The maximum d ock frequ ency is
J. mu
Related Problem -
~
I
- -
~
'p(lOt)
I
--10 ns
=
25 M Hz
Show the timing diagram if a ll of the fli p-Oops in Figure 8- 5(a) arc positive edget rlgJ~ercd.
· i\nswcrs Me al lhc end of Ihe Ch:lplcr.
Asynchronous Decade Counters: A counter can have 2~ st
The modulus of a COUnler is the num ber of unique states through which the counter will scquence. The max imum possible number of slates (max imum modul us) of a coumer is 2", where n is the nu m be r o fn i l)-flop~ in the counter. Counters can be designed to have a numberof states in their sequence that is less than the maxi mum of 2". 111is type of sequence is called a TnmC(l1ell SelJllem:e. One common modulus for counters with tnlncated sequences is ten (called MOD IO). Counters with ten states in their sequence are called decade cuunters. A decade cuunter wi th a count sequence o f zero (0000) through nine (1001 ) is a BCD decade counter because its ten-state sequence produces the BCD code. This type o f counter is useful in di splay applicalions in which BCD is required for conversion to a decimal readout. To obtain a Inmcated sequence, it is necessary to force the counter to recycle before going throug h ail of its pOssible states. For example. the BCD decade counter must recycle back to the OOUO slate after the 100 1 state. A decade COU nter requires four !lip-nops (three flip-nops are ins utTicient because 23 = 8). Let's usc a 4-bit asynchronous counter such as the one in Examplc 8- 1 and modify its sequence to iilustr.Jte the pri nciple of truncated counters. One way to make the counter recycle after the count of nine ( 100 1) is to decode count ten ( IOIO) with a NAND gatc and con nect the Output of the NAN D gale to the elear (ClR ) inputs of the ni p-flops, as shown in Figure 8--6(01). Partial Decoding Notice in Figure 8--6(a) that only Q I and QJ are <:onnected to the NAND gate inputs. This armngemcnt is an eX:l1nple of /Jl/ r ,ial decodilJg, in which the two unique states (Q I = I and Q3 = I) arc sufficient to decode the count of ten because none of the other states (zero through nine) have both Q ! and Q l HlGH at the same li me. When the COunler goes into <:OUllt Icn (1010), Ihe decoding gate out put goes LOW and asynchronously resets all the nip-nops. The resulti ng liming diagmm is shown in Figure 8-6(b). Notice that there is a glitch on the QI wavefonn. 1bc reason for this glitch is that QI must fi rst go HIGH before the count of len can be decoded. Not until several nanoseconds after the counter goes to the CO U11l of len docs the OUlput of the decoding gate go LOW (both inputs are HIGH). Thus, the counter is in the 1010 state for a shol1 ti mt: Ix!fore it is reset to OOOO, lhus producing the glitch on QI and the resulting g litch on the CLR linc that resets the counter. Other tru ncated sequences can be imple men ted in a simil ar way. as Example 8- 2 shows.
ASYNCHRONOUS CO UNTER OPER ATION
LO dc<:ndcr
.el.K
.-
J,
r-< p.c c-
FF1
FFI
FFO
A
c-
K,
"
J,
f-
C
C
c-
K,
CLK
CLK
T
1
n
f-
J,
An alyrn:hronously docked decade counter wit" al)'OChronoul recycling.
A '3
v,
Q,
C
c-
K,
f---
J,
K,
CU I
Cl.H
r
r
Q, - - - - - ' Q, - - - - - - - - '
~ -------------------" CLR
GIII~h.../ (b)
I
EXAMPLE 8-2 Show how an asynchronous counter can be implementcd having a modulus of twelve with il straight binary sequence from 0000 through 1011.
Solution
Since three nip-flops can produce a maximum of e ight stales, lour n ip-flops arc requircd lo produce any modulus greater tha n cighl but less than or cqu..'ll \0 sixteen. Whcn lhe coullIer gelS to its last stale. l Ol l. it must recycle back to (X)()() rather Ihan going to its normal next slalC of 1100. as illustrated in the fo llowing sequence chart :
Q,
Q,
Q,
Q,
0
0
0
0
I
Rec)cles
0
I
I
0
0
I ~
433
FIGURE 8 - 6
-I )P
HIGH
•
Nonnal next state
434
•
COUNTERS
Observe lhat Qo and QI bolh go 10 0 anyway, bU I Qz and Q 3 must be forced 10 0 on the twelfth clock pu lse. Figure 8- 7(a) shows the modulul>- 12 counter. The NAND gate partially decodes count twelve ( 1100) and resets fl ip-flop 2 and fl ip-flop 3. TIlliS, on the twelfth clock pulse, the counter is forced 10 recycle from count eleven 10 count zero, as shown in the liming diagmm of Figure 8- 7(b). (It is in countlwclvc for only a few nanoseconds before it is reset by the glitCh on eU?) t2 d,..ooocr
J
JUG H FFI
FAl ~
Cl K
J"
-< I>c ~
rl
f-
c ~
K"
n
f-
J,
~
K,
FE!
FF2
~ f-
J,
c
CU,
CI.R
CLR
Y
Y
Y
F
J,
c ~
K,
f-
K, CU,
r
w ,
,.J
Q, ---------------------~
:,
,f-
~ ------------------------~~ ' --Ir
UUlput
~
~/
'" .. FIGURE 8-7
Asynchronously d ocked modulus- ' 2 counter with "synchronous recycling.
Related Problem
How can the counter in Figurc 8- 7(a) be modified to make it a modulus- 13 counter?
THE 741593 4- BIT ASYNCHRONOUS BINARY COUNTER The 74LS93 is an example of a specific integrated circuit asynchro nous counter. As the logic diagram in Figure 8- 8 shows. Ihis device actua lly cU/lSi.~ l s of a single fli p-flup and a 3-bit asynchronous counter. Th is arrange ment is for flexibility. It can be used as a tlivide-by-2 device if only the single flip-flop is used, or il ca.n be used as a modu lus-8 coumer if on ly the 3-bi t counter portion is used. '[11is device also provides gated resel in-
ASYNCHRONOUS COUNTER OPERATION
•
435
( 1)
eLK B
'-''-- -;:==:::;-- 1 f-
J, ( 14)
e LK A
-
J,
"-''-----qf> C
C
K,
H,
CI.R
OR
'(
'(
-
J,
c
-< I> c
K,
-
J,
K,
CLR
CLK
r
I'
CLR (8)
(9)
( 12)
Q,
Q"
Q,
I LStl )
(I
n
Q, II\IS8)
FIGURE I - I The HLS93 4--bit asynchronous binary cOtJ ntcr logic diag~m. (Pin nlJmbers are in parentheses. and a U) and I( inplJu are internally connected HIGH.)
puts, RO( I) and ROO). When both of these inputs arc HI GH, the counier is reset 10 the 0000 ~t ate CU ? Additionally, the 74LS93 can be used as a 4-bit modulus- 16 countCr (counts 0 Ihrough 15) by connecting the Qo output In the elK 8 input as shown in Figure R- 9(a). It can also be configured as a decade counter (counts 0 through 9) with asynchronous recycli ng by using the gated rcset inputs for parlia l decoding of COllnl len, as shown in Figure 8- 9(b).
eLK A
C
e rR D'V
el.KA--
'6
n.K R- fOI>C
B -- ~(> C
elK
RO(/ } _
RO(I } - _
R~21 -L--=====:r-rI-1
d,U,
(a ) 741.S 9] CflnnCCled as a mod u'us _ln COllnlcr
RU'"
-1~~3:Jl=[lrI , , , C
Qu Q 1 Q2 Q\ (h) 74 LS9] col1nCCle tl as a dt.'cade counK'f
FIGUR E 8-9 Two conrigm-atiom or the HLS93 asynchronoUi cou nter. t::ountc r with n states.)
j
(TIle qlJalitying label, erR ON n, indicat:el a
EXAMPLE 8-3
Show how the 74LS93 can be used as a mooulus-12 counter. Solution
Usc the gated resct inputs, RO(/ ) and R0(2), to parlially decode count 12 (remember, there is an internal NAND gate a....sociatcd with Ihcsc inputs). The count- 12 decoding is accomplished by connect ing Q3 to RO( J) and Q2 to RO(2). as shown in Figure 8- 10. Outpul Qu is connected to e lK B to crc.1te a 4-bit counter.
43 6
_
COUNTERS
~
FIGURE 1 - 10
CI KA--.¢~e~~C~r;R~D;'~V~';2-1
HLS93 <:an neded a.l a modu lu.I-l Z cou nter.
CJ K H -~e NOli ! _ NOm ~
I I
j
Immediatel y after the counter goes to count 12 ( 11 00), it is reset to CXJOO. The recycl ing, howe"l:r, res ults in a glitch on Q~ because the cou nter must go into the 11 00 state for several nanoseconds before recycling.
Related Problem
I ~ECTION
Show how the 74 LS93 can be connected as a modulus- I 3 counter.
1-1
REVIEW
Mwers are at the e nd of the
chapter.
8-2
SYNCHRONOUS COUNTER OPERATION T he term synchronous refers to events that havc a fixed timl: relationshi p wi th each other. A synch ronous counte r is o ne in which all the n ip-nops i n the counte r are clocked at the saml: time by a common clock pulse. After comple ti ng this sectio n. you s ho ulcJ be able to - Descri be the opemtion of a 2-bit synchronous binary counter - Dcscribt: the operation of a 3-bit synchronous binary counte r - Descri be the operation of a 4-bit sync hronous binary cou ntcr _ Describe the opemtion of a sy nChrono us decade counter - Develop counter timing diagrams - Discuss the 74 HC I63 4-bi t binary counter and the 74F I62 BCD decade countcr
A 2-Bit Synchronous Binary Counter Fig ure 8- 11 shows a 2-bit synchronous binary counter. Notice that an arrangemenl d ifferent from that for the async hronous counte r must be used for the l l and KI inputs o f J.."'F I in order to achieve a binary sequence. FIGURE I - I I
HIGt1 FFO
A l-bit synchroooui binary counter.
~
FFI
Q"
J,
e '--CTK
K,
l- Q,
J,
e
-
K,
>- Q,
SYNCHRONOU S COUNTER OPERATION
The operation of this :.ynchronous COunter is a<; follows: First. ass ume that the counter is initially in the binary 0 slale: Ihal is. both fli p-flops me RESET When the positive edge of the first clock pulse ;s applied, FFO will toggle and Qo will therefore go HIG H. What happens to FFI at the positive-going edge of CLKI ? To find out , let's look at the input conditions of I-r l. Inputs J j and K I are both LOW because Qo> to which they are connected, has not yel gone HIGH. Remember, there is a propagation delay from the triggering cd!,!e o f the clock pulse until the Q oulput actually makes a transition. So, J = 0 and K ::: 0 when the leadi ng edge of the first clock pulse is applied. This is a no-change condition, and therelo re FF I does not change slate. A limin2 detail of this portion of the counter oper;1tion is shown in Figure 8-12(a).
CL K2
Q,
(,'
(0'
~
0-------------------(b)
Cd'
FIGURE 1 - 12
Timing detail! for the 2-bit Iynchronous counter operation (the propagation dela)'1 of both are allumed to be equal).
f1ip-f1o~
AfterCLKI. Qo = I ilnd QI = 0 (which is t.he binary I state, . Whe n the leading edge of C l K2 occurs. FFO will toggle and Qo will go lOW. Since FF I has a H IGH (Qo = 1) on its J 1 and K1 inputs at the triggering edge of this clock pulse, the fl ip-flop toggles and Ql goes HIGH. Thus, after CLK2, Qo = 0 and Q l = J (which is a binary 2 state). The tinting detail for this condition is shown in Figure 8- 12(b). When the leading edge of C lK3 occurs. FFO again toggles to the SET state (Qo = I), and FF I remains SET WI = I) because its J . and K . inpUls are both lOW (Qo = 0). After this triggering edge. Qo = I and Ql = I (which is a binary 3 state). The timing detail i ~ shown in Figure 8-12(c). Finally, ill the lead ing edge o f CLK4, Qo and QI go LOW because they both have a toggle condition on their J and K inputs. The timing de tail is shown in Figure 8- 12(d). T he coun ter ha.<; now recycled 10 ils original Slate, binary O. The complete timing diagram forthecoumcr in Figure 8- 11 is shown in Figure lj- 13. Notice that all the waveform transitions appear coincident; Ihat is. the propagation delays are not indicated. Although [he delays are an important factor in the synchronous coun ter operation, in an ovemll timing di38ram they me normally omitted for sitnplicity. Major waveform FIGURE 1 - 13
Timing diagram for t he counter of Figure 8- 11.
Q,
•
The dock input goe\ to each flip-flop in a synchronous counter.
437
438
•
C OUNTERS
relationships res ulting from the normal operation of a circuit can be conveyed completely without showing sm'lll delay and timing differences. However, in high-spced digitnl circuits. these small delays are an impon anl consideration in design and troubleshooting.
A 3- Bit Synchronous Binary Counter A 3-bit synchronous binary counter is shown in Figure 8- 14. and its tim ing diagram is shown in Figure 8- 15. You can understand this counter operation by examining its sequence of states as shown in Table 8- 3. FIGURE 8 - 14
IlIGH
A 3- bit syrn:hronous binary cou nter. Open fole F08- 14 to verify the operation.
FFI
FFO ~
'"
Q"
J,
C
-
K,
I
QJ
jlUQI
r--- Q,
~ J,
C
-
ITI
C ~
K,
K,
eLK
FIGURE 8 - 15
Timing d iagram for the counter of
Figure 8- 14.
... TABLE 8 - 3
The TSC or time stomp oowrter in the Pentium is used fo r performance monitoring. v.tlich enables a nu mber of paramete~ important to the over-III perfOfI'1'1eer.ltion. fOI"l~x"lInple, it .::an be ac:c:ura tely detennined which of two or more programming sequence. i. more effooent Thi, i, a very useful tool for oompile. developen and I)'Stcm pr~mmen in produang the ~t e ffective <:Ode for the Pentium.
I
I
Binary state sequern:e (or a 3-bit binary coun ter.
ClOCK PULSE Initiall y
0
0
0
0
2
0
0
3
0
J
0
4
,
0
0
0
6
0
7 8 (l\.'Cycles)
U
0
0
F i ~ I , leI 's look al Qo. Notice Ihal Qo changes on each clock pu lse as the counter progresses from its original state 10 its final stale and then back to its orig inal stalc. To produce Ihis operation. FFO muSI be held in the toggle mode by constanl HIGHs un itsJ o and Kn inputs. Notice thai QI goes to the opposite slate fo llowing each time Qo is a I. This change occurs at CLK2, CLK4. C LK6. and C LKS. The CLKS pulse causes the coomer to recycle. To produce this operation. Qo is conncctoo to the J . and K . inputs of r·F!.
SYNCHRONO US COUNTER O PER ATION
When Qo is a I and a clock pulse occurs, FFI is in the toggle mode and therefore c hanges state. The other times. when Qo is a O. FFI is in the no-change mode and remains in its present state. Next . let's see how FF2 is made 10 change at the proper times accordi ng to the bi nary seque nce. Notice Ihat both limes Q! changes state. il is preceded by the unique condition in which both Qn and Q l are HIGH. This condition is detected by the AND gate and 'Ipplied to the h and K~ inpuls of FF2. Whenever bolh Qn and QI are HIGH. the output orlhe AND gate makes Iheh and K2inputs ofFF2 HIG H,aod FF2 toggles on the foll owing clock pulse. At all other times, the 12 and K2 inputs of FF2 are held LOW by the AND gale output. and FF2 does nol change state.
A 4- Bit Synchronous Binary Counter Figure 8- 16(a) shows a 4-bit synchronous binary counter, and Figure 8- J6(b) shows its liming d iagram. This part icular cuunter is implemented with m;gative edge-triggered nipOops. The reasoning behind the ) and K input control for the firs t three nip-Oops is the same as previously di ~ussed for the 3-bit counter. The fourth singe, FF3, changes on ly twice in the sequence. NOlice Ihal both of these Imnsilions occur fo llowing the rimes that QIl< QI' and Q~ are all HIGH. This condition is decoded by AND gate G 1 sotha! when a clock pulse occurs, FFJ wi ll change slate. For all other limes thel) and K) inputs o f FF3 are LOW, and it is in a no-chnllge condition.
HIGH
~
J"
Q,
Q"
J,
K"
~
K,
I
m
(/"Q I
I c, }-
t-
c
c '---
I
FF t
FFO
J,
Qn QI Q~
I c,
c
'---
'---
K,
(a )
eLI<:
I, -+--+--+--+
(b)
FIGURE 1 - 16
A 4-bit synd1 ro nou. binary counter and timing diagram. Poinb where the AND gate outpub are HI GH are indica ted by the shaded areM.
f-
J,
c
e LK
Q,
}-+-
tl~
FFJ
K,
•
439
440
•
COU NTERS
A 4-Bit Synchronous Decade Counter As you know. a BCD aecuae counter exhibits a truncated binary oSt:ljucnl:c ant! g~ from through the 1001 state. Rather than going from the 100 1 state 10 the 1010 state. it recycles to the 0000 state. A synchronous BCD decade counter is shown in Figure 8-17. The timing diagram for the decade counter is shown in Figure H- 18.
A decade counter has ten states.
()()(X)
1
HtGH
1'1'0 ~
i"
-J
}~
K"
]
i,
FF2 ~
<',
c
c -
I
A' I
Q,
'---
i,
I
J
)-
1' 8 ~
Q.
c -
K,
K,
i,
fQ;
c -
K,
Q,
r-'
CI K • FIGURE 1 - 11
A I)'nduQnOUI BCD deade cou nter. Open file F08-' 7 to verify operation.
You can understand the counter operation by examining the SC(jucnce of states in Table
S--4 and by foll owing the implementation in Figure 8- 17. First, notice that FFO CQO> togglt::.~ on each d uck puhe, so the lugic equation for ils J o and Ko inputs is Jo = Ko = I
111;S equation is implemented by connecting J o and Ko 10 a constant HIGH level. Next, notice in Table 8-4 tlmt FF I (QI) changes on the next clock pu lsc each time Qo = I and Q3 "" D. so the logic equation for the J I and K] inputs is J I = K. = QoQ3 This equation is implemented by ANDing Qo and 0) and connecting the gate OUlput lo the J I and K I inputs of FFI. Flip-flop 2 (Q2) changes on the nex t clock pulsceach time both Qo "" I and QI = I. This requires an input logic equation as (ollows: J1
=
K1
=
QUQI
This equat ion is implemented by ANDing Qo and QJ and connecting the gate OUlpul to the hand K2 inputs o f FF2.
SYNCHRONOUS COUNTER OPERATI O N
•
TABLE 1-4 State\ of a BCD decade counter.
Initially
0
0
0
0
0
0
2
U
U
3
0
0
,
0
0
0
0
4
0 0 0
6
0
0
7
0
I
8 9
to (recycles)
U
0
0
0
0
0
0
0 U
Finally, FF3 (Q3) changes to the opposite state on the next clock pulse each time Qo = 1, QI = I, and Q2 = I (stale 7). or when Qo = I
+ QuQ3
111is function is implemented with the ANDfOR logic connected 10 the ) .1 and KJ inputs of FF3 a~ shown inlhe logic uiagmm in Figure 8-17. Notice that lhe di lrerence~belween this decade counter and the modulus- 16 binary counter in Figure 8- 16 arc the QOQ3 AND gate, the QOQ3 AND gate. and the OR gate; this arrangement detects the OCCUITence of the IOC)] state and causes the counter to recycle properly on the next clock pulse.
THE 74HC163 4- BIT SYNCHRONOUS BINARY COUNTER T he 74 HC I63 is an example of an illlegrated circu il 4-bil synchronous binary counter. A logic symbol is shown in Figure 8-19 with pin numbers in parentheses. This counter has several features in addition to the basic functions previously d iscussed for the general synchronous binury counter. FIGURE 1 - 19
0-..101 mput, ~
The 701HCt 63 4-bihyrxh ronoul
Do VI V 2 1)3
CI..H
(I)
WilD ENT
(9) (10)
I:.""NP
(7 )
binary coun te r. (The q ualifying label CTR DIV 16 indicate\ a count er with iixteen states.)
erR D tV 16 TC= 15
( 15)
RCO
eLK--,(2~)'-I~c,-,_",J Qo Q I Q2 Q)
'------.------'
t>:ll
441
442
•
COUNTERS
counter wi ll assu me the state o f the data inputs on the next clock pulse. TIlUS, the counter sequence can be started with any 4-bit binary number. Also, there is an active-LOW clear input (CLR ), which synchronously resets all rour nip-nops in the counter. There are two enable inputs. /;""NP and ENT These inputs must both be HIGH for the counter to sequence thro u2h its binm)' states. When at lea.
----w U r - - - - - -- -- - - - -
D, _ _~__:_L[ -n
, I RCO
- --f,- --:-:-c-:---'----'M
,,, ,,: 12 :,11 "
t t
,,.
"
I n
1:, ,, ,
- - (\'unl - -_ . , -
hilibi!
FIGURE 8 - 20
Timing example fOf" a 74HC163.
Let's examine this limi ng d iagram in detail. TIlis will aid you in interpreting timing diagrams in this chapter or on manufacturers' data .
SYNCHRONOUS COUNTER OPERAT ION
•
THE 74F162 SYNCHRONOUS BCD DECADE COUNTER The 74FI62 is an example of a decade counter. " can be presct to any BCD coum by the use of the data inputs and a lOW on the PE input. A lOW on the asynchronom SR will reset the counter. The ~ n
The 74F I 6Z syncilr"Onou! BCD decade counte r. (The qua.lifying labe l CTR DIV 10 indicates a. counter with ten ltatel.)
(6) (I)
.\ R
"I:: CI::P
CIT
CTRD1V
(9)
liS ) TC-=9 - - TC
(7)
(to)
elK
to
(2)
C
SR
------ur - - - - - - - - - - - - u
PE
eLK
--hLj"
-=~1==1:'~+==+~+==+~+==PF=======;,--L-
CEp _ Cf.7
~: ~~~~th~; -+-~l-~--f-tr-------
(Mllul, {
Q, TC
-~==-t i LI~hltjj=tt~=
--7-:---c:--+--'HL~~~___'_+_---- ,, ,:T , 9 o ,
,
,,
1 ,!--- - I.
C lear FIGURE 8-22
Timing e>la.mple for
oil
74F162.
"""',
,
:,
Ctlunt
,, --~. 1- - In hibit ,
443
444
•
COUNTE RS
I
SECTION 8 - 2 REVIEW
1. How doe5 a lynchronous counter differ from an asynch ronous counter? Z. Explain the {unction of the preset feature of counten 5uch as the 74HC 16J.
3. Describe the purpose o{the ENP and ENT inputs and the RCO output for the 74HC16J coun ter.
8- 3
UP/DOWN SYNCHRONOUS COUNTERS An up/down counter is one that is capable of progressing in either direction th rough a certain sequence. An up/down counter, sometimes called a bidirectional counter, can have any specified sequence o f states. A 3-bit binary counter thai advances upward through its sequence (0, 1, 2,3, 4, 5,6,7) and then can be reversed so that it goes through Ihe sequence in the oppOSite direction (7, 6, 5,4,3, 2, 1,0) is an illustration of up/down sequential operation. After completing this section, you should be able to Di.~c u ss
• Explain the ba... ic opcr,lIion I)f an up/down counter _ up/down decade counter
the 74HC I90
In general, most up/down counters can be reversed at any point in their sequence. For instance, the 3-bit binmy counter can be made to go through the fol lowing sequence:
LP
--------
UP
-----------
~ 1 . 2,3.4.5 .4 , 3,2 ,3 ,~5 , ~7 , ~5,~ '---v--' '--r-'
OOWN
DOWN
Table 8-5 shows the complete up/down sequence for a 3-bi! binary counter. The atTOWS indicate the Slate-to-state movement of the counter for both ils UP and its OOWN modes of operation. An examination o f Qo for both the up and down sequences shows that FFO toggles on each dock pulse. Thus, the J o and Ko inputs of F1-""o arc Jo = Ko = I
For the up sequence. QI changes state on the next clock pulse when Qo = I. For the down sequence, QI changes on the next clock pulse when Qn = O. 11ms, the 11 and KI inpuls of FFI mUM equal I under the conditions expressed by the following equation: J, ~ K , ~ (Q,. UP)
+ (Q,. DOWN)
TABLE 8 - 5
UplDovm ~equetlce for a 3-bit binary counter.
CLOCK PULSE
UP
Oz
Q1
0
C C C C C C C C
0
0
0
0
2 3 4
5
6 7
0
0 0
0 0 0
0
0
0
0
DOWN
) ) ) ) ) ) ) )
UP/DOWN SYNCHRONOUS COUNTE RS
•
445
For the up sequence. Ql changes st;Ue on the next clock pulse when Qn = QI = 1. For the down sequence, Q1 changes on the next clock pu lse when Qu = QI = O. Thus. the 12 and K2 inputs of FF2 must equal I under the conditions expressed by the fo llowing equation: 12 = Kl = (Qu ' QI . UP ) + (Qu' QI . DOWN) Each of the conditions for the J and K inputs of each flip-flop produces a toggle at the appropriate point in the counter sequence. Figure 8- 23 shows a basic implementation of a 3-bit up/down bimlry coulller using the logic equations just developed for the 1 and K inputs o f each flip-flop. Notice that the UP/DOWN control input is HIGH for UP and LOW for OOWN. FIGURE ' - 23
i'P
Q,,'I II'
HIGH FFO
UP/DOli V
A M ic 3-bit up/down synchronous counter. Open file F08-lJ to verify operation.
FF2
FFI
Q!
'.
"
e
e
K,
K,
" e K,
On' DOW' O.K
I
EXAMPLE 8-4
Show the timi ng diagram and determi ne the sequence of a 4-bit synchronous bi nary up/down counter if the d ock and UP/ DOWN control inputs have waveforms as shown in Figure 8-24(a). The counter start~ in the a ll Os state and is positi ve edge-triggered.
I-
UPlDOIYN ----'1 - - l ;p _ -----0.'1'11(.)
Q,
Q~
(b)
,,
elK
Lp
Qj U! U I
(I
[),,,,"
" "
,
, ,, 41 ' 0 ' 0 ,,, ,
+
o
II
1 1 1
I
I I
I I
I I
I I
II 1CI 1() 1(I
I (I
1
, , , ,, O I O I {l I U
,
1 I 1 I I I I I r--1 I I I I U I 1 Il'e'"-, 0c'c 'e'c'-,'c' c' ,,0
FIGURE ' _ 24
Solution
The timing diagrmn showing the Q OU lput~ is shown in Figure 8-24(b). From Ihese waveforms, the counter sequence is as shown in Table 8--6.
0446
•
COU NTERS
.. TABL E 8 _ 6
0
0
0
0
0
0
0
0
0
0
UP
0
0
Related P,oblem
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0 DOWN
0
0
}
UP
0 0
}
IX>WN
SllOW the tililing di
invcrtetl.
THE 74HC190 UP/DOWN DECADE COUNTER Figure 8- 25 shows a logic d iagram for the 74HCI90. an example of an imegrated c ircuit up/down synchronous counter. The d irection of the count is determined by the levcl of the up/down input ( D/ U ). W hen this input is HIGH, the countercounbdown: whcn it is LOW. the counter counts up. Also. this device can be prc.~el to any desired BCD digit as determined by the stat!;:s of the d
The 74HC 190 lJp/dowolynchrollous deGIde counter. 'fE.\'
DIU LUMJ eLK
(4)
(1 2)
",,>,XIMIN
'Si CfR DIV 10
(11 )
(1 4)
c
(1 3 )
RCn
The MAXIMIN output produces a HIGH pulse when the Iconinal count nine ( 1001) is reached in the UP mode or when the terminal count zero (0000) is reached in the DOWN Imxle. This MAXIMIN output, along with the ripple clock output (RCO) and the count enable input (CTEN), is used when cascading counters. (Otscadcd counte~ are discussed in Section 8- 5.) Figurc 8- 26 is a timing diagram that shows the 74HCI90 counter preset to seven (01 11 ) and then going through a cou nt-up sequence followed by a cuunt-down seq uence. The
DESIGN OF SYNC HRONOUS COUNTERS
-
447
MAXIMIN output is HIGH whcn thc Counter is in e ither the all-Us stale (MIN) or the 100 1 slate (MAX).
0-.\13
inru l '
i----j
LOAD D,
~
D,
~
D,
~
TimingexiJmple for a 7'lHC 190.
lL :"I :"I :"I
D, eLK f)JU --,
cn:."11 --,
0>", { output,
~: ---~t , U:::LF.===i=Lt1J=Jr---+--+1 ,r
~]- -H , , ot ~==1'==+==P=====t=t==~~'==T==1 Q ! :! ~ I :: II 11'-:::=1=::;:== ---I !! ~ !! ~!
MAXIMIN - -
I
RCO
7 :: 8 9 : 0 II II
00,
"
'-.--'
2
:! 1
-
Count up ______ I... Inhibil I
:
::? : I I
~I
1
n : "
I I
H : 7 I
1- - - - C"u nt d",' n _______ I I
I
....>;,u
I
SECTION 8 - 3 REVIEW
1. A 4-bit up/do\.Vl"l binary counter is in the DOWN mode C1nd in the 1010 5tate. On the next dock pulw. to wn..t state does the counter go? 2. What is the terminal count of
8-4
DESIGN OF SYNCHRONOUS COUNTERS In this section. you will see how :-;equentiai circuit design tcchniques can be applied specifi cally to counter design. In general. sequential cireuits can he da'i..;ified intn two types: ( I) th usc in which the uutput or outputs depend only on the present internal slate (called Moore cirCtlils) and (2) those in which the output or out putS depe nd 011 hoth thc prc....ent state and the input or inputs (called Mellly circu its). Thi~ section is recommended for those who want an infroduction 10 counter design or to state machine de:;ign in general. It is not a prerequisite for any other material. After colllpleti ng this section, you should be able to - Describe a general sequential drcuit in tenns ofi !s basic pans and it.. inputs and outputs _ Dcvelop a sta te d iagram for a given sequence _ Develop a next-state tahle for a speci fi ed counter SCi.juence _ Create a Ilip-flop transition table _ Use the Karnaugh map method to deri ve the logic requi rements for a synchronous counter - Implement a coun ter 10 produce a specified sequence of ~la le:;
448
•
COUNTERS
General Model of a Sequential Circuit Bcfore proceeding with a specific counter design technique, let 's begin with a genernl definition of II sequential circuit or statt~ machine: A gcneral sequential circuit consists of a comhinalionallogic section and a memory section (flip-nops), as shown in Figurc 8- 27. In II clocked sequenti al circuit. there is a clock input 10 thc memory section as indicated. FI(;URE 8 - 27
eLK
j
E,citanun lin.:,
General docked u,quent,ial circuit.
r InpuI' ~
l
r I" I,
,,
I.
,• •
·
Inpul oorubinalion31
>,
logi('
t;.
•,
i
Q"
MClllor~'
• • •
""}
• II, :
UlllpUI~
· "" I
Q,
•• Q.
The infonnatioll stored in the memol)' section. as wel l as the inputs 10 the comhinational logic (/110 110 .... 1m), is required for proper operation of thc cireuit. At any givcn time. thc melllOlY is in a s tate called thepre.~·elll J/{tfe and wi ll advance 10 a nUl stale on a elock pulse as Jctermincd by eonJilit>us on lhe excitation lints ( YH• YI • .. . • YI' )' Thc present slatc \)f thc memory is represented by the state vdriahlcs (Qo. Qlo .. . , Q .). '~esc state variablcs. along with thc inputs (If), I t•... • 1m). detcrminc the system outputs (00 , 0 ..... . On)' Not all sequerllial circuits have input and OUlput variables as in the general model just discussed. Howcvcr, all have excitation variahlcs and slate variables. Counters are a special ca<;c o f clocked scqucntial circuits. In this section. a general design procedure for sequcntial circuits is applied to synchronous counters in a series of s teps.
Step 1: State Diagram Thc fir.;t stcp ill the dc,"ign of a counter IS tu creatc a state diagram. A state diagr.tm shows the progression o f states. Ihrough which the countcr advances when it is clocked. As an example. Figure 8- 28 is a state diagram for a basic 3-bit Gray code counter. Tnis particular circuit has no inputs olher than the clock and no outputs other than the outputs taken off eaeh flip-flop in the counter_You may wish to reviL", the coveragc ofrhe Gray code in Chapter 2 at this timc. FIGURE 8 - 28
State diagra m (or a 3-bit Gray rode counter.
100
~H
111
Step 2: Next-State Table Onee thc sequential circuit is defined by a state diagram. thc second s tep is to dcri ve a nextstate ta ble. which l i ~ t s each state of thc counter (present state) along with the corresponding next Slale. The next .~I{/Ie is Ihe stale Ihll ltl,e COl/trier 8ues 10 JlVm its present slate IIpon (lp-
OESIGN OF SYNCHRONOUS COUNTERS
•
449
plicatiOll Of a dock Pllise. The next-state table is derived from the state d iagram and is shown in 'rable 8-7 for the 3-bit Gray code counter. Qo is the least significant bi\. TABLE ' - 7
PRESENT STATE
O2
O.
00
0
0
0
0
0
Next-state tabl., for 3-bit Gray cod., count.,r.
0
0
0 0
I)
0
U
0
U
0 U
0 0
0
0
0
0
0
0
Step 3: Flip-Flop Transition Table Table 8- 8 is a transi tion table for the J-K flip- flop. All possible uutput transitiOns arc listed by showing the Q out put of the flip-flop going from present stale..>; to next states. QN is the present slale of the flip-flop tbefore a clock pulse) and QN+ I is the next stilte (after a clock pulse). For each outpliliransilion. the} and K inpu ts that will cause the transit ion 10 occllr arc listed. An X indicates a ""don', care" (the input can he c1ther a I or a 0). TABLE 8 - 8
OUTPUT TRANSiTIONS
ON
J
K
0
0
X
0
X
ON • I
0
--->
0
---> ---> --->
fLIP-flOP INPUTS
.
X
X
0
Q~' ~""'(ll!ol.
Q". ,: nc~1 slale X: ··t\on·1care'"
To desiBIl Ihe counter. the transition table is applied to each of the flip-flops in the counter. haSL'd on the next-stale table (Table 8- 7). For example. for the present Slale 000. Qo goes from a presclll stale of 0 to a next state of I. To make this happen, i o must be a I and YOli don't care what Ko is (i o = I. Ko = X). as you Can see in the transition table (Table 8-8). Next. Q I is 0 in the presem stale and remains a 0 in Ihe next slate. For this transition. i l := 0 and KI := X. Finally. Q! is 0 in thc present stale and re mains a 0 in the nex t state. Thercforc. i ! = 0 and K~ = X. Thi s an:.lysis is rcPCilled for each present stale in Table 8-7.
Step 4: Kamaugh Maps Knrnaugh maps can be used to delcnninc (hc logic required for the J and K inputs of e'
Transition table for aJ-K f1jp-flop.
450
•
COUNTERS
, Q~ Q I
The \'aluC'S of J " ~nd Kn ret] uired 10 pmdu~e lhe Ir.msilion are placed on each map in lhe pr..,;clll-!>l.ate <;ell.
,
0
,
00
0'
01
"
" X
,
0 X
00
'0
1be \'" Iues of J o ,,00 Ku req uired 10 prodoce lhe lransilion arc pl",:cd on "ach map in the
, Q~Q I
,
10
/'
presenl-st;Jle cell.
Output Tran~lionl
QN
I
Q "''+I
0 ____ 0
0_ I ____ II'
,- ,
J
Qz
K
~
, ,
0
X X
X X
Flip-11op Ifallsi li{)(l tJble
Ql
Qo
,, ",, 0 ,,
0
U
U
0 0
II
Qg
II
•
0 0
~nl ~Ia!e 101. Qo a Inmsilion frum I '00
For ' he mak~.,;
to.he next sl;Uc.
0
U
0
Q1
,, , , ,, , , 0 0,
0 U
0 0
L
U
Q1
For llie present sta:c UJU, Q o mak.:s a [ran~i[;on rrom 0 to I to lhe next s("le.
Next State
PrCICnt St.lte
Flip-Flop Inputs
0
U
0
0
•
NeKHlal" table FIGURE 8 - 29
Ex
11le compleled Kama ugh maps for all lhrcc nip-flops in thccOI lnl er arc shown in Figure 8-30. T he cells arc g rouped as indicated lind the correspond ing Boolean c,.;pressions for each group arc derived. FIGURE 8-30
Kamaugh map. for preoent-statc J and K in puu.
0
,
, <1"
0
OU
0
0
00
0
,
"
"'
x
'" "
(l IQ" -
, X
X
'0
X
X
, Q"
0
,
Q,Q
" '0
,
Q,
x
0'
0
x
x
X
0
u
"
u
,
X
Q .{J"
,
X
0
X
, Q,
u
,
X
I~
X
0
0
X
,
0
,
u,
X
U
x
x
"'0
X
0' u
" ,
0
",u
- '
_
10
X
0
, X
00
10'
0
,
X
0
, Q, OU
,e x 0'
(J IV"
,
, Q,
Q,Q
X
,
-
Q ,{J,
Q,QI
DESIGN OF SYNCHRONOUS COUNTERS
Step 5: logic Expressions for Flip-Flop Inputs From the Kam:llIgh maps o f Figure 8-30 you obtain the following expressions for the i and K inputs of each flip-flop: i o = Q2Ql
+ Q2Ql
= Q2 E}} Q;
Ko = Q2Ql
+ Q2Ql
=
i
l
=
Q2 EB Q\
QzQo
Kl = QlQO
i 2 = QIQO K2 = QIQO
Step 6: Counter Implementation The final slep is 10 implement Ihecombinutionallogic from the expressions for the l and K inputs and conncct thc fli p-flops 10 form tm: completc 3-bit Gr.ty code countcr as shown in Figure 8-3 1.
FFO ~1I
>- I>c
IT '>
J,
K,
m
FI' I
Q"
rlJ-
J,
pc Q"
~I
}-
Q,
Q,
K,
-fJ-
J,
c
-LJ-
K,
i-'" -
~
Q.K
FIGURE ' - 31 Thlre-bit Gray code counter. Open file F08- J 1 to verify operation.
A summary of stcps used in the design of this countcr follows. In geneml, thesc steps can he appl ied to any sequential circuit. I. Specify the counter sequence and draw a state diagram.
2. Derive a next-statc table from the statc diagrmn. 3. Develop a transition tahle showi ng the fl ip-flop inputs required fo r each Iransilion. The transition table is always the same for a givcn type of flip-flop. 4. Transfcr t.hc 1 mill K states from the transil'ion tahle to Karnaugh maps. Tl lere is a Kal11augh map for each input of each fli p-flop. 5. Group thc Kamaugh map cells each fl ip-flop input.
10
generate and derive the logic expression for
6. Implement thc expressions with combinational logic. and combinc with thc n ipnops to create the counter. This procedure is now applied to {he design o r other synchronous counters in Examples 8- 5 and 8--6.
•
451
452
•
COUNTE RS
i
EXAMPLE 8-5 Design a counter with the ilTCguJar bina')' count sequence shown in the state diagram of Figure 8--32. Use J- K nip-flops. FIGUR E 11-32
& ~
, "' ~ "' ./ "'-\;J . Solution
\
Stcl) 1: The state diagram is as shown. Although there arc only fOUf states, a 3-bit counter is required to implement this sequence because the maximum binary count is seven. Since Ihe required ~equence docs nol indude all the possible bi nary states, the invalid states (0, 3, 4 , and 6) ean be treated as "don't cares" in Ihe dcsign. However, if the counter should erroneously get into an invalid state, you must make sure thm it goes baek to a valid state.
Step 2:
The next-stale tahle is developed fmm thc state diagmm and is givcn in Table 8--9.
TABLE 11 - 9
Next-state table.
PRESENT STATE Q~
Q\
o
o
o
,
NEXT STATE
Qo
Q2
Q1
o
Qo
o
o
o
o o Step 3:
0
The transition table for the J-K fl ip-flop is repeated in lable 8- 10.
TABLE 11 - 10
Tramition table for aJ- K flip-flop.
OUTPUT TRANSITIONS FLIP-FLOP INPUTS QN QN • 1 ) K
o
u
o o
"
X
X X
Step 4:
x o
The J and K inputs ,Ire plolted on the prcsem-st
DESIGN O F SYNCHRONOUS COUNTERS
• FIGURE
1 - ]]
, Q,
0
I
00
X
X
X
01
I
X
X
X
X
X
10
X
I
" 10
X
X
,
, <10
0
I
, 0,
0
,
X
X
OIl
X
X
00
X
I
01
X
X
01
I
X
01
X
X
"
X
I
X
I
0
II
X
X
"
X
X
"
X
0
, <10
0
I
, <10
0
I
~I
X
0
00
X
I
01
I
X
01
X
"
X
X
10
X
X
"
, Q.
II
00
'0
Step 5:
- v,
III
.
~ I
Q,Q
10
•
-
I
-
V.
453
Group the Is, taking advantage of
12 =
K 2 = QI
Step 6: 111e implcmemation of the coumer is shown in r"igun:: 8- 34 . .... FIGURE I
34
L
o HIGH
J
J.
I
J,
e
"
Q,
Q,
Q
HIGIi
e K
,
J
J,
e K
, P--
Q,
e LK
An analysis shows tbat if thc counter, by acciden t, gets into one ofthc invalid states (0.3, 4,6), il will always return to a valid statc according to the following sequenccs: 0 - >3 -10 4 ·· 7.and6 - >I.
Related Problem
Verify tbc ana lysis thai provcs thc counler will always rctum (eventually) to a valid statc fro m an invalid state.
454
•
COUNTERS
Develop a synchronous 3-bit up/down counter with a Gray code sequence. The counter shou ld count up when an UP/ DOWN control input is rand CO UIll down when the control input is O. Solution
Slep 1: The state diagram is shown in Figure 8- 35. The I or 0 beside each arrow indicates the state of the UP/ DOWN contml input, Y. FIGURE 8- 35
State diagRlm for a J-bit up/down Gray code cOllnter.
'00
'"
SICI) 2:
The next-state table is derived from the state diagrmn and is shO\vn in Table 8- 11 . NOIice that for each present state there arc two possible next states. depending on the UP/ DOWN cumrol variable. t
TABLE 8-11
NocHbte table for J-bit up/down Gray code cou nter.
NEXT STATE Y '" 0 (DOWN)
-! ~
PRESENT STATE Qz
01
Qo
0
0
0
U
0
0
0
0,
O.
Qo
Q1 0
0
0
0
0
0
0
U
0
0
0
0
0
0
0
0
0 0
0 0
Q~
0 0
0
1 (UP)
Qz
0
0
0
0
0
0
I' - UP/ OOW N tQf)lro/ input
Step 3: The transition table for the J-K nip-flops j .~ repcmcd in Table 8-12.
DESIGN OF SYNCHRONOUS COUNTERS
TABLE &- 12
I
OUTPUT TRANSITIONS
Transition table fo r a J- K flip-flop.
ON
ON
o
o
J
K
o
x X
o
,
,
QY 00
01
00
I
0
01
0
"
10
x
1
X
o
The Kamaugh ma ps for the) and K inputs of the fli p-flops arc shown in Figure 8- 36. The UP/ DOWN control input. Y, is considered one of the stale variabl c.~ along wi th QIIo Q" and Q2' Using the next-state table. the information in the "Flip-Flop Inputs" column of Table 8- 12 is tra nsferred onto the maps as indicated for each presen t state of the couiller.
QY
,
~I
01
"I
00
,"
00
0,
"I
00
I
X
x /
1
0
x
X
0
I
X
X
I
0
X
"
10
0
0
00
0
0
I
0
00
0
I
0
0
01
X
X
X
X
01
x
x
x
X
X
X
X
X
X
X
X
"
0
0
0
I
" 10
,
-
10
X
.
J , rna P
J,llIa p
Q,Q, I
,
HI
,"
00
0.0 ,1
X
00
X
QY
, "
\ 111
X
X
X
00
X
X
"0
'" "
•
X
Q,Q" I
, '" '" " 00 X X X
4S S
FLIP-FLOP INPUTS
1
o
SLep 4:
•
~,
HI
10 I
01
X
X
X
X
01
0
0
0
I
01
X
X
I
0
~"
I
0
0
0
0
0
I
0
X
0
I
0
I
0
0
X
X
X
X
"
X
10
"10
X
X
I
0
IH
,
... FIGURE &- 36
J and K maps for Ta ble 8- ' I , The UP / DOWN control input, Y. Step 5:
i~ treated
011
a fourth variab le.
TIle Is are combined in the largest possible groupings, with "don' t cares" (Xs) used when: possible. TIle groups are faclOrcd. and the expressions fOf
{he J and K inpuLs an' as follows:
+ Q2Q 1Y + Q1Q1 Y + Q2Q,Y + Q2QOY Q,QoY + Q1QOY
+ Q1Q, Y + Q2Q,Y + Q2Q,Y Q2QOY + Q~Qo Y Q,QOY + Q,QOY
J o = QzQ,Y
Ko = Q2Q1Y
J 1 = Q2QOY
K, =
h
K2 =
=
45 6
•
COUNTERS
Step 6: The J and K equations arc implemented with combinatio nal logic. and the complete counter is shown in Figure R- 37.
Q, y
{J~
<', e,
0"
Q"
1{)
}-
}-
~
)-
Qu
I,
pc
~')-
K
"
~
}-
j
)-
0, I,
pC 1,)-
K
]
I,
)-
,
Q,
0.
pc j
)-
0, K,
cI K FIGURE 1 - 31
Three-bit upfdown G
Related Problem
Verify that the logic in Figure R-37 agn:cs with the ex pressions in Step 5.
CASCADED COUNTERS
I
SECTION 8 - 4 REVIEW
_
457
1. A flip-flop is presently in the RESET ~tate .Jnd must go to the SET state on the next dock pulse. What must} and K be? 2 . A flip-flop is presently in the SET state and must re main SET o n the next dock pulse. Wh.Jt mu~t} and K be?
3. A bin.Jry counter is in the O)OzO,OO= 1010 state. (a) \\/hat is its nextstate?
(b) What condition must exist on e.JCh flip-flop in put to e nsure that it goe~ to the proper next state on the dock pulse?
8- 5
CASCADED COUNTERS
Counters can be connected in cascade to achicvc higher-modulus operation. In essence, cascading means that the last-stage o utput of one COUllter drives the input of the next countcr. After complcling this section, you should be a hlc to _ Octennine the overall modulus of ca<;cadt.'d counters _ Analyze the timing diagram of a cascaded counlerconfiguralion _ Usc cascaded couillers as a fn.:qucncy d ivider - Use caSl:
An example of two counters connccted in cascade is shown in Figure 8- 3H for a 2-bit and a J -bil ripple co unter. llle timing diagram is shown in Figure 8- 39. Notice that the
FIGURE 1 - 31
J, rt .K
-
J,
e
W-
K,
J,
I>e
e
~
K,
Q,
J,
J,
e
W-
K,
Q,
W-
K,
e K,
Modu lu~_ 8
c()U nl cr
.flf
CLK
I I 12 13 14 15 16 17 18 19 110111112113114 11 511u!!71181191 20121122123124 1251261271 281 2913013 1132 I
I
1
I
I
I
I
,
I
I
I
I
I
I
,
I
I
I
I
I
I
I
I
I
I
,
I
I
I
I
1
I
Q,
,
L----!r
J---------iL
Q, _ _ _ _ _ _
Two (AlKMI&l counte rs (a ll ) and K inputs are HIGH).
Q,
Q,
Modu tus- 4ooumer
f-- (14
... FIGURE 1 -1 9
Timing d iagram for the (Al lClded counter configur.>tion of Figure 8-38.
458
•
CO UNT ERS
The O\Ieri!lJl moduluJ of Qlscaded counters is equi!ll to the product of the individui!ll moduli.
, i5 0 64-bit counter. It II o~ th
II
64-
il clocked at a
MHz. it will take go throvgh oil sbtes ond reach it!; termillill In contrail a 32-bit full-
I
::::~::~ will Cxh.lVlt oil of in opproxirT\iltely 4)
clocked ot 100 MHz. difference i5 astounding.
final output of the mooulus-S coumer, (2." occurs once for (:very 32 input clock pulses. TIle overall modulus of lhe cao;caded counters is 32; that is, they act as a dividL'-by-32 coumer. When operating synchronous counters in a cw:;caded confi guration, it is necessary to usc the counl enable and the tcrm inal count functions to achieve higheH llooulus opemlion. On some devices the count enable is labeled simply CrEN (or some oliler designation such as G), and temlinal cou m (TC) is analogolls to ripple clock out put (RCo) on somc Ie Cou Ill Cn;.. Figure 8-40 shows two decade cuunters connected in cascade. TIle terminal count (TC) output of counter I is connected to the count enable (CrEW) input of counter 2. Cou nte r 2 is inhi bited by the LOW on its CTEN input unt il counte r I rcaches its last. or term ina l, state and ils lerminal count output goes HIGH. Thi s HIGH now enables countcr 2, so lhal when Ihe fi rst clock pu lse aner counter I reaches its term inal count (CLKIO). countc r 2 goes from its ini ljal stale 10 ils second Slate. Upon complet ion 0 1" the e mire second cycle of counter I (when counter I reaches lerrn inal count the second time), counter 2 is again enabled and advances to its nex l state. This sequence conti nues. Since the.<;e arc decade countcrs. counl.cr I musl go lIlrough ten complete cycles before eoun ler 2 completes its fi rst cycle. In uther words, for every ten cycles of counter I, counter 2 goes through one cycle. Thus, counter 2 will compicte one cycle after one hundred clock pulses. Tile overall modu lus of these two cascaded counters is 10 x 10 = 100.
HI GH COUn!cr !
COllnlcr 2
crEN
elK
f--------'
-- C
f in
TC
elEN
TC
e rR Dl V 10
c
L-----'Qr'-=Qr'-="'r-:Q:,r'-'
FIGURE 8-40
A modulul- l 00 counter uling two cascoded decade counters.
When viewed as a frequency divider, the circuit of Figure 8-40 divides Ihe input clock freq ucncy by 100. Cascaded counl.crs are often uSt.'tl to divide a high-frequency clock signa1 to obtain highly occunlte pulse frequencies. Cascaded counter configurations used fOr such purposes are sometimes called COUlltdOWII chains. For example. suppose Ihat you have a basic clock freq uency of I MHz and you wish to obtain 100 kHz, 10 kHz, and I kH z; a series of cascaded decade counters can be uS(,'d. If Ihe I M Hz signal is divided by 10. the outpul is 100 kHz. Then if Ihe lex) kHz signal is divided by 10, the output is 10 kHz. Another division by 10 produces the I kHz freljuency. The general impicmentation of Ihis countdown chain is shown in Figure 8-4 1.
FIGURE 1 - 41
JU );H,
It)(1hi ll
HIG H
I ); 111
Three CJSCaded dec.o.de cou nters forming a divide-by- l OOO frequency d ivider with intennediate divide-by-
Cl'EN
10 ond dM"de-by- l 00 outputs.
TC
en..,.
erR DlV 10 I M ill
C
TC
CJ"£N
CTR DI V 10
I>C
C rR DIV 10
,
>C
TC
CASCADED COUNTERS
•
459
Dclennine Ihe overall modulus of Ihe I\','O c'l~{k,(] counler configumlions in Figure 8-42.
rH r-I ' ' ' '1 _I H r-I H CfR DlV!!
em. DlV !2
CfRDlV 16
ern Dl V 10
e rRDI V 4
CTR DIV7
o..'P"'
(a)
'oP"'
em. DIV 5
(b)
r-~'~'
... FIGUR£ 8 - 4Z
Solution
In Figure 8--42(a).thc overall modulus for the 3-cOunler configuration is
8x 12x 16 = 1536 In Figure g--42(b). the ove" lli mod ul us lor the 4-counter configurnlion is IOx4x7x5 = 1400
How many ca~aded decade counters are f<-'
Related Problem
[()(),( XX)?
I
EXAMPLE 8-8
Use 74F I62 decade counters 10 obtain a 10 kH z waveform from a I MHz clock. Show the logic diagram.
Solution
To obtain 10 kHz from a I MHz d ock re
SR~~~========t;=t;=~=b;===========~
P£-
3)
(I) , --
4)
S)
6)
--"'-"'"-"-'''-'''''-,
CfR DIV 10
(9)
(1) +V(:c -~tC';'-l C£P
(' )
ern DI V 10
(9)
TC" (IS)
cn
(1)
" TC
CEP
(IS)
IOltlz
o:r
c
C
CL K ------------f-~~Cf~--------~ I MIll
FIGUR£ 8 - 43
A divide-by- 100 counter ming two 74F1 62 decade countefl.
Related Problem
Delemline the freq uency of the waveform at the 011 the right) in Figure 8--43.
Olle
GJ o utput of the second counter (the
460
•
COUNTERS
Cascaded Counters with Truncated Sequences The prccL-ding discussion ha<; shown how to achieve an overall modulus (dividc-by-factor) thm is (he pnxluc( of the individual modul i of all the cascaded counters. This can be considered full-nuxlllius cascading. Often an application requi res an ovcrall modulus that i ~ Icss than that achieved by full modulus cascading. 11ml is, a trunc
2 16 = 65 ,536 LO/; I) (' I" ~
I
IIIGI-I
EN.,. C
RCO erR DlV 16
Em
I
U U
RCO
Em
C CTR DI V 1(,
C
RCO C fRDl V16
ENT C
RCO e r R DlV 16
OuTput
e LK FIGURE ' - 44
A dM"de-by-40,OOO count~r uling 74HC161 4-bit binary oounten. Note th ... t e ... ch of the par... Uel ddt" inputs iI. lhown in bill
Lei's ass ume Ihm a cel1ain application req uires a dividc-by-40 ,OOO counter (modulus 4O,0tXl). Thedirrerencc betwee n 65,536 and 40,000 is 25,536, which is Ihe number of slates that must be deleretf f ro m the full -modulus SL'qucnce. The technique u ~d in thc circuit of Figure R--44 is 10 presctlhc cascadr.-d counter to 25.536 (63CO in hexadecimal) each lime it recycles, so thai it will count from 25.536 up to 65.535 on each fu ll L)'cJe. There fore. each full cycle of thc countcr consists of 40,000 slates. Notice in Figure R-44 Ihat Ihe RCa output of the right-most counter is invcl1L'iI and applied to thc LOA D inpul o f each 4-bit counter. f.ach ti me Ihe count reaches ils lenninal value of65,535, which is Illlllllllllllll ~, NCO gocs HIGH and causes the numbcr on lhe parallel data inputs (63CO If.) to be synchronously loaded into the counter with the clock pulse. Thus, there is one RCa pulsc from thc right-most 4-bit countcr ror e\'cry 40.000 d ock pulses. With Ihis tcchnique any moduluSC
I
SECTION 8 5 REVIEW
1. How many deCc"lde counten "re necessary to implement a divide-by-l000 (modulus- l OOO) counter? A divide-by- l O.OOO? 2. ShOW" with general block diagrams how to achieve each or the fol/owing. using a flipflop, a decade counter, and a 4-bit binary counter, or any combination of these: (a) Divide-by-20 counter
(b) Divide-by-J2 counter
(c) Divide- by-' 60 counter
(d) Divide-by-320 counter
COUNTER DECODING
8-6
COUNTER DECODING
In mallY il ppl ic m i on ~. it is Ilt:CCSSaty Ihal some or all of the counter slates be decoded . The decoding of a cOOnler invol ,,~ using dccOOcrs 01'" log ic gate!> to dctcnn inc when lhe counlL'I' is in II CCrluin binary ..tate in ils S{:qucncc. For inslancc. the Icm linal count function previously discu:.sed is a single decoded slate (the last stale) in the counter seq uence. Arter completi ng this S(.'Clion. you should be able to
• Implcmcllll hc dt:ctxling IOllie for any given slale in a ctlunlcr ~'(j ucncc _ Explai n why glitches occur in counter decoding logic . Usc the method o f strobing 10 climi nlllC
l.k-'C odi llg glitches
Suppose that you wish to decode binary Sia le 6 (1 10) of a 3-bil binmy counier. When Q~) = O. a III GH 'Ippcars on the output of the lkcodi nJ,! gale. indica!ing Ihm the coomer is aI slale 6. TII;S can be donc as shown in Figure R-45. Th is is culled activt!-I f/GII l/t!c(){lillg. Replacing the AND gate with a NA ND gate provides uclive-LOW
Q2 = I. Q, = I. and
d(.'~:od i n!! .
II IGIt
~
(I"
J,
J,
C
'---
K,
Q,
, -,
)-.-
C
~
L
K,
~
J, C
~
'--- K,
o'!-
rI. K
I LSA
I
I M~IJ
f i GU RE '-45
DKoding of ~t.lte 6 ( 11 0). OJkn file f08-45 to verify opetation.
I
EXAMPLE 8-'
Implement the decoding of bina!)' Slate 2 and binary slate 7 of a 3-bil synchrono us counter. Show Ihe entin! counter liming diagr.uH and the output waveforms o f thc decoding gales. Binary 2 = Q2QIQOand bina!), 7 = QJQIQO'
•
461
462
•
COUNTERS
... FIGURE 8 - 46
IUGH
A J-bit counter with active-
FA!
HIGH decoding of count 2 and count 7. Open file F08-46 to
I1F I LS6
J,
J,
vt!rify operation.
I
Q,
I'F2
J
~
J,
Q"
c K,
Q"
C
>C
,
K,
K
MSB
-
Q,
-
Q.
~
eLK
, 7
, Q,
J
Q, Q,
n...·..:ukd UUl ptJl '
Solutkm
Related Problem
{:
,
L ,L L ,,
•
,,,
L
Sce Figure 8-46. The 3-bit coumer was originally d iscussed in Section 8- 2 (Figurc 8- 14). Show the logic for decoding state 5 in the 3-bit COlllllcr.
Decoding Glitches A glitch ii a n unwan ted spike of
voltage
TIle prohlcm of glitches produced by the decoding proces.~ wa" d i scus.~ed in Chapter 6. As yOll hm'e learned, the propagation delays duc to the ripple cffect in asynchronous counters create transitional slates in which the counter Olliputs arc changing aI slightly different limes. TIlcse transitional stales produce undesired voltage spikes o f shalt dumlion (glitches) on the DUtpulS of a decoder connected to the counter. The g li/ch problem can also occur 10 some degree with synchronous counters because [he propagation delays from the dock to the Q output" of each nip-Ilop in a counter can vary slightly. Figure 8-47 shows a basic asynchronous BCD decwJe eounter connecled 10 a BCD-todL'Cimal dL'COder. To sec what happens in Ihis case, let's look at a timing diagram in which the propagmion delays arc taken into account, as shown in Figure R-48. NOIil:c thatlhesc delays cause false Slates of short duration. l11e value of the false binaJ)' slate al each CI;!-
COUNTER DECODIN G
•
463
... FIGURE 1 - 47
em DlV 10
BCDIDEC 0
,
A ba1ic decade (BCD) counter and
doc,x",,_
2
3
Q, 2
4
4
5
8 eLK
"
7
8
C
EN
9
FIGURE 8 - 41
eLK
O utputs with gltc;he! from the deroder in Figure 8-47. G litch widthl are ex;,gger,;,ted for
Q,
iUustraHon and ~re UJually only OJ few
-
--11
ncmoseumdli wide.
o
2 3 o..' o.xIcr (JU l pU!~
4
U
:l
I II
I,
l
I, J
I,
III
,J
'I
----------~~--~:,tr--~:7:-~:
, -----------------, LJr-------i't'------i't n n' --6 7
8
--------------------"
r--11r-----i17:--
L--J
u
U
"
"' I
"II ,,
- - - - - - - ,LJij--
9
leal Imnsilion is indicated on the diagram . ·lllC resulting glitches can be seen on the decoder out puts. One way 10 eliminate the glitches is to enable the decoded outputs at a time aflcr the glitches have had time 10 disappear. This method is know n as strobil/I: and can be accomplished in the case of nn active-H IG H clock by using the LOW level o ft hc clock 10 enable the decoder, a~ shown in Figure 8-49. The resulting improved timing diagram is shown in Figure 8-50.
464
_
COUNTERS
fiGURE 8 49
CTR Dl V 10
BCDIDEC
The balK: decode counter and decoder with itrobing to eliminate
0
glitdld.
Q" Q, Q, Q,
2 3 4
,
2 4
,
b
, 7
EN
C
9
CLKlSTROBE FIGURE 8 50
Strobed decoder outpull for the circuit of Figu re 8- 49.
U 2 3
Decoder {lulpI.U _
4
~ ,6
7
U
8
U-
9
I
SECTION 8-6 REVIEW
8-7
,_ What traraitional states are pooible when a 4- bit asynchronous binary counter chan~ from (a) count 2 to count 3
(b) count 3 to count 4
(c) count 1010 to count 11 10
(d) count 15 to count 0
COUNTER APPLICATIONS The digital counter is a useful and versatile device that is found in many application!>. Inlhis sectiOIl, somc represcntati\'c countL" applications arc prcsemcd. After completing this section. you should be able [0 - Describe how counters are used in a basic digi tal dock syste m _ Explain how a divide-by-60 counter is implemented
COUNTER APPLICATIONS
A Digital Clock A common cxample of a counter aplliication is in ti mekee pinB systems. Figure X- 5 1 is a simplified logic diagram o f a dig ital clock tlUlt dis plays seconds, minutes, and hours. Firs t. a 60 Hz sinusoidal ac voltage is converted 10 a 60 Hz pul se waveform and divided dow n to a 1 Hz pu lse waveform by a divide-by-60 counter formed by a divide-by- W counter foll owcd by a dividc-by-6 cou nter. BOIh the seconds and millllle.~ counts are also produced by divide-by-60 count.c rs. the delails of which are shown in Figure 8- 52. Tht:.o;e counters count from 0 to 59 and Ihen recycle to 0; synchmnous decade counlers are used ill Ihis panicular implementation. Notice that Ihe di vide- by-6 pon io n is fo n ned with a decade counter wilh a IlUncatl.'
Di\'K1e· by-60
6011",,,
60 HI
'l1\l\I\, --
Wowshaping circui,
JU1IUl
C
Q
r--
~
EN
Seconds wilmer (divide-by-W)
MillUies oou fller (divide-by-W)
CrR DI V 10
mI-
C
,",
erR DIV6
I>C
Houn; cOu nCer
FF
CTR DI V 10
C<~
CTR D1V6 EN
r-
c<~
CTR DIV 10 EN r -
CTR DIV 6
c rR D1 V 10
EN
ENr-
c<~
c<~
C
~I I II BCl)!7-$eg
n CM-$eg
,, C-, (0- 9)
(0- 1)
•
•
BCDl7 -.oq
BCDl7-seg
,-=,
/I
:J (0 9)
(0-5)
'------------r-----------',
'-----------_.,-----------'
lhlU",
Mmlll'-'10
RCDI7-scg
•
•
I
=, (0- 5)
BCDI7-seg
/I
LI
(0-9)
'------------r-----------'
FIGUR£ 8 - 51
Simplified logic diagram for a 12-hour d igitat clock. logic detaill uling ~ic devic~ are shown in Figurel 8-52 and 8-53.
The hours counter is implemented with a decade counter and a fl ip-flop as shown in Figure 8- 53. Consider IIml initially bOlh Ihe decadc counlcr and the flip-flop are RESET. and lbe decode- I 2 gale and decodc-9 gate outputs are HIGH. The decade counter a(lvances throuBh all of its staleS from zero 10 nint:, amI on lhe clock pulse that recyclcs it from ni ne baek to zero, the flip- flop goes 10 the SET stale (l = I , K = 0). This illumi nates a I on the lens-o f-hours display. The tOlul count is now tcn (the decade countcr is in Ihe zem stale and thc nip-flop is SET). Next, Ihc total count advances to elcven and then to twelvc. In stale 12 the Q2 output of Ihe decade counicr is HIGH , the /lip-Ilop is stilt SET, and thus Ihe dccode- 12 gate outp ut is
•
465
466
•
COUNTERS
HIGH
eLK
P I
SR
stiL
e rR DIV 10
CEP CET C
~
SR
CTR DI V 6
CEP
crr
TC = ':J
C
1
To ne)!:1 Dcc
to
COlln\er
)..
TC=:'i
,
TuFN ABlE
S
ufne~1
{'"R
FIGURE 8-52
l Ogic diagram of typical dMde--by-60 counter ~;ng 74FI61 tyflChronoul decade counten . Note that the outpull are in binary orde!" (the right-mmt bit is t he ~B).
FIGURE 8 - 53
logic diagram for hours counter aocl decoden. Note that on the counter inpub imd outpull, the right-most bit is the 15B.
000 I'E
J
Q
C rRDIV 10 74F I62
eLK
G, 8
4
8 ,
::!
BCDI7-seg
I3CDI7~seg
74LS47
g/t' u c h "
2
74LS47
g /
f.'d c b(l
"re, unilw,f hUIII').
~ -~ T(lhm.. "r IKItIn.
di.. pIJ}
tli'pl~}
LOW. This ac tivate.... the PE input or lhe decaoeCQlInler. Oil the next clock pulse, the decade counter is pre..~et 10 state I by the data inpuls. and the nip-flop is RESET (J = 0, K "" I). As you can see, this logic always causes the coullIer 10 recycle from twelve back to one rather Ihan back to zero.
Automobile Parking Control T his counterexample illustrates the use of an up/down counter to solve an everyday problem. The problem is to devise a means of monitoring aVHilabJe spaL"eS in ,I one-hundredspace parking garage and provide for
COUNTER APPLICATIONS
•
467
circuit thllt uses the counter output 10 tum the FULL sign on or off liS required and lower or raise the gate har at the entrance. A general block diagram o f this system is shown in Figure 8-54. FIGURE ' - 54 Entr.mc.:
sensor v lI/Ofr
UI' CTR DI V 100
l ermi nal count
Function.)1 block diagram for parking gar.lgc control.
Interface
DOWN
A logic diagram o f the up/down counter is shown in Figure 8-55. IL consists of lwo cascaded 74HCl90 up/down decllde counters. The opemtion is described in the following paragra phs.
1l
From
-
S
~
1l
From ('K i t
-
=
R
-
DIU Crf:N
>c
ern. Dl V
10 74HCI90 ReO
L
P-c
DIU CT£N
>C
CTR DI V 10 74HClI)()
Q
f--
MAX/A n N
"" interface ) IU GH OlC ti\
IOwel"'!!
J FIGURE 8-55
logic diagram for mod ..dul-IOO up/down counter for au tomobile parking control.
The counter is initially preset to 0 using the parallel data inputs, which me not shown. Each automobile entering the garage breaks a light beam, activating a sensor that produces an e~ctri ca l pulse. This positive pulse ...elS the S-R lmch o n its leading edge. The LOW Oil the Q output of the latch puts the counter in the UP mode. Also, the .~en sor pulse goes through the NOR gate and clocks the counter on the LOW-to-IIIGII U-dnsition of its trailing edge. Each lime an automobile enters the garuge, the counter is advanced by one (incremented). When theone-hundredth aUlomobileenters.thecol1nte r goes to its last stale (1 00uJ. The MAXIMIN output goes HIG H and activates the interface cirellit (no detai l). which lights the FULL sign and lowers the gate bar to prevent further entry. When an automobile exit<>. an optoclectronic sensOl" producer; a positive pulse, which resets the S-R latch and puts the counter in the DOWN mode. The trailing edge of the clock decreas~ the count by olle (decremented). I rthe gamge is full and an automobile leaves, the MAXIMIN output of the counter goes LOW, luming off the FULL sign and raising the gate.
Parallel-to-Serial Data Conversion (Multiplexing) A simplified example of data trons mission using multiplexing and demulti plex ing techniques was introJuced in Cllllpter6. Esseillially. the par.tl lel data bits on the multiplexer inputs are convened to serial da ta bits on the single transmission line. A group or bits appearing simultllneously on para1!el li ne.~ is clllled IJClrallei daw. A group o f bits appearing on a single line in a lime sequence is called serial darn. Paralle l-to-serial conversion is normally accomplished by the use o f a counter to provide a binary sequence for the data-select inpUl ~ of a data selector/mult iplexer. as illustrated in Figure 8-56. The Q outputs of the mooulus-8 counter are connected to the data-select inpuIs of an 8-bit multiplexer.
Incrementing a counter increases its count by o ne.
Decrementing a counter decreases its count by one.
468
•
COUNTERS
FIGURE 8 - 56
MUX
CTR DIV8
Q,
O}u",
Q,
Q, e LK
Sele<:t
2
C
Serial
0
,
..1:11" nUl
2
,3
I~Jnl l kl
,
in
6 7
Figure 8-57 is a timing diagr.ml il1 u ~ trnli ng Ille operation of In is circuit. The firsl byle (eight-bit group) of parallel data is applied to the multiplexer inpuls. As the coUnier goes through a binary sequence from zero 10 seven, each bil, beginn ing wiln Dr:;. is sequenlially selected and passed Inrougll tile muhiplexer 10 the olllplllline. After eight clock pulses the
o
FIGURE 8 - 57
23<15670
2-'4567
eLK
Example o f para llcl-to-serial (;onvcn.ion timing for t he circuit in
Figure 8-56.
0" 1>'ltu )ek-": I
Q,
Q, D, D, D, Computers <:ontain ' "
;",~;;;,
counter that can be progr.wnmed for varioos (reqvencieI and tone durations, thlK producing ~ml.l5ic. ~ select iI p
I
~:~"~; to produu: an audio
dlJration of a tone <:
IlKCd ;,."~tio"' "''"''' ba$lc: to produce melodies by a
<:OI.Intcr is
controlling the freq...ency And
Id...ration of tones.
D, D-J!a
m
:: ! w : 1 _~1JJ I :1 i 1JJ : I i !·+-: ~ , , :
I
I
I
:
I
:
I
I
I
I I
I
I
,,
,,
"
I
I
I I
I
I
I
I
D,
I
I
:,
o o
o o
,, ,, ,, ,, ,, , ,,--,, o----,-- 1- ' - ·-'--; , , ,, I
I
D,
I I
I
I
I
I
I
,
D, D,
1 I
,,
I
I
~~~~--~~-7~"-1
I
I
o
:
l OGIC SYMBO LS WI TH DEP END EN C Y N OTAT IO N
data bYle has been convened to a serial formal and sent out on the Ir'dnsmissio n line. When the counter recycles back to O. the next byte is applied 10 the data inputs and is sequentially convened to serial form as the counter cycles through its eight stales. This process continues repeated ly as each parallel byte is converted 10 a st:rial byte.
1. Explain the purpme of each NAND gate in figure 8-53. 2. Identify the two recycle conditiom for the ho urs counter in figure 8-51, and explain the reason for each.
8- 8
LOGIC SYMBOLS WITH DEPENDENCY NOTATION
Up to this point, the logic symbols with dependem.:y nolation specified in ANSI/lEEE Standard 9 [- 1984 have been intruduced on a limited basis. In m:my cases. the new symbols do not deviate ~reall y from the tmditional symbols. A significant departure fmm what we are accustomed to does occur. hm'ever. for some devices. including counters and other more complex devices. Although we wi ll continue 10 use primarily the more traditional and familiar symbols throughout this book, a brief coverage of logic symbols with dependency notation is provided. A specific IC cQUnler is used as an example. After completing this section. you should be able to • interpret logic symbols that include dependency notation _ Identify the common block ant.! the individual elements of a counter symbol _ Inlerprel the qualifying symbol • Discuss conlrol dependency • Discuss mode dependency - Discuss AND dependency
Dependency notalion is fundamen lal lo Ihe ANSIII EEE standard. Depellde ncy notation is used in conj unclion with Ihe logic symbols to specify the relationshi ps of inputs and outpUIS so Ihat the logical operation of a given device can be determined entirely from its lo£ic symbol without a prior knowledge o f the details of its internal stnlcture and without a derailed logic diagram fOJ" refere nce. Th is covemge of a specific logic symbol with dependency notation is intended to aid in the interpretation of other such symbols that you may encounler in the futu re. Thc 74HC I63 4-bit synchronous binary countcr is uS«! fOl" illustrat ion. Porcomparison. Fi!!ure 8-58 shows a trad itional block symbol and the ANSIII.EEE symbol with dependency notation. Basic descriptions of the symbol and the depende ncy notation rollow. Common COIIuol Block The upper block wilh notched comers ill Figure 8-58(b) has in· Pl1lS and an outpullhat are considered common to D I, D2• and D J and outputs Qo- 01. Q}. and 0 3. Qualifyr."ng Symbol The labe] ·'CfR DIV 16·· in Figure 8--58(b) idenlifies the device as a ooul1ter (CfR) with sixteen states (DIV 16).
As shown in Fig.ure 8-58(b). the lcuer C denotes conlrol dependency. Comrol inputs usually enable or disable Ihe data inputs (D. J, K. S, and R) o f a stora~e element. The C inpUl is usually the cloc k inpUl. Tn this case the dig.it 5 fo llowing C (C512.3.4 + ) ind icates that the inputs labeled with a 5 prefi x are dependent on the clock Control. Dependency (C)
•
46'}
470
•
COUNTERS
V-:
Common
coolrol
CfRDI V 16
DII /) 1 IJ~
CUI
",
LOAn EItT
(LX WAD INT ENI'
CLK
ENP
( I)
(9)
CLK
( 10)
erR DlV 16
(7)
block
( I)
5CT ;O
(9)
(I~ (7 )
(2)
MI
3CT ,.- 15
M2
G3 G4 ~C5n,J.4+
(15) NCO
(3 )
D,
(2)
(4)
C
D, (J~
n,
0" Q, Q! Q, (a) Traclilional block symbol
(5) (6)
!. 5 D
r-
( 15)
RCO
( 14)
[ I)
(13) (21
[4]
( 12) ( II )
IK[
(b) ANSI/ IEEE Slu . 9 1- 19K4 logIC symbol FIGURE
a
51
The HHC163 4-bit synchronou l counter.
(synchronous with the clock). For example, SeT = 0 on Ihe cui. input indicates thai lhe clear function is dependenl on Ihe clock; thai is, il is a synchronous clear. When the CI.R inpm is LOW (0). the counter is resello zero (CT = 0) on the trigge ri ng edge o f the clock pulse. Also, the 5 D label at the input of storage element [I I indicates Ihm the daw storage i ~ dependent on (synchronous with) lhe clock. All labels in the II ] siorageelement appl y to the 12J, 141. and fS] elements below it si nce they arc not labeled differently.
Mode Dependency (M) As shown in Figure 8-SS(b), the letter M denotes mode depende ncy. This label is used to indicate how the functions of \'arious inpuls or out puts depend on the mode in which the device is o(X'Tating. In this case the device has two modes of oper
AND Dependenc.y (G)
As shown in Figure 8- SI:S(b), the leiter C denotes AND dependency. indicating that an input designated with C followed by a d igit is ANDed with any other input or OUIPUI having the same digil as a prefix in its label. In this pan icular example. the G3 at the £NT input
1. In dependency notation, wflat do the letters C, M, and G stand for?
2. By wflat letter is data storage denoted?
TROUBLESHOOTING
8-9
TROUBLESHOOTING
The trou ble$hooting o f counters can be simple or Qu ite invo lved. depending on the type o f counter and the Iype of fault. This section will give you some insight into how 10 uppruach the truubleshU(l(ing of sequential circuits. After completing Ihis seclion. you should be able to • Detect a faulty counter a Isolate faults in maximum- moo ulus cascaded counters • Isolate fau lls in cuscaded cOllnters wjlh truncated sequences _ Determine faulls in counters implemented wilh individual Ilip-nops
Counters For a counter with a straightforward sequence that is not controlled by external logic, abou t the only thing 10 chttk (Olher thiln Vcc and gl'Ound) is the possibility of open or shorted illputs or outputs. An Ie counter almost never alters ils sequeoce of ~ Iale~ because of an internal fault , so you need only check for pulse activity on the Q outpUtS to detect the existence of an open or a short. The absence of pulse activity on one of the Q outputs indicates an imemal open or a shon on the line, which may be intemal o r external to the Ie. Absence of pulse activity o n all the Q outputs indicates thai the dock input is fau lty or the clear input i.~ stuck in its active state. To check the clear input, apply a constanl active level whi le the counter is clocked. You w ill observe a LOW 011 each of lhe Q outputs if it is fUllCtioning properl y. A synchm nous parallel load feature on a counter can be checked by activating the parallellolll.l input and exert:ising each state as follows: Apply LOWs to the paml1el data inputs. pulse the clock input once, and check for LOWs on all the Q outputs. Next, apply HIGHs to all the parallel d
Cascaded Counters with Maximum Modulus A failure in one o f the coumers in a chai n of cascaded counters call aITect all the counters that fo llow it. Fo r example. if a count enable input opens, it effec ti vely aels as a HIGH (for 'ITL), and the counter is always enabled. This type o f fa ilure in one of the counters will cause that counter to ru n
Cascaded Counters with Truncated Sequences The count seque nce of a cascaded coun ter with
•
471
472
•
COUNTERS
1U0 ~ H I
1
TO
HIGH{ - CTEN
CffiDi V 10
[ f> c
10
[ f> c
I l i lt
1
TC
CT£fII
~ lI t
J·e
(TE.N
CfR DI Y 10
erR DI Y 10
Il>c
I MHI (01) NormOlI oper.ltion
!
I()O ~Hz
HIG H{ -
TC
CTEN
10 ~HI
1O0 l H.(
r r OI'I;-"II("Ct'''''I I IIGl h
C11:::N
e r R DlV 10
TC
1
[I>C
TC
cn.""N
e rR Dl V 10
CTR DI Y JO
[I>C
I I>C
I MHI (b) COUllt EnOlblc
KTEN) input of seomd cllunter open FIGURE I - 59
rumple of .. f.. ilure tMt .,ffects following counters in a caK
the sequence will begin with E3CO'b (58.30410). This change... the modulus of the counter from 40.000 to 65,536 - 58,304 = 7232. To check th is ctJunter, apply u known clock frequency, for example I MHz, and measure lhe outpul frequency at Ihe final terminal count output. Ifl he counter is oper
!. ~ "'""
f. modulus
~pcc iflc
In this case, the
1 M Hz 40,000
~ -- = 25 H z
fail ure desc ri bed in the precedi ng paragraph will cause Ihe output
rrequency to be
, ) 00' -
/;.
I M Hz
mod ul us
7232
138.3 1·lz
OPIoN W4D
c,.
Uu
~
II [PC I M i ll
D) D~ O,DO
D \ DI D, Do
CTEN
'11 i i'
"I iH
1111 TC
e rR DI Y Ifi
Least signirlCanf
r-- CTEN
r
pc
ern DI Y
~ 1;
J !t
1/,
DJ D2 DJ DI} TC
~
CTEN
e r R DI Y 16
1
C
i'i l' 6 ,.
DJ O! D J DfJ IT'
~
erEN
TC
erR DI V 16
I>C
r!>-
M05f signific:tnl
138.-' HI FIGURE ' - 60
oomple of a f.. il ure in a cascaded counter with .. truncat ed seq uence.
TRO U BLESHOOTING
I
•
473
EXAMPLE 8-10 Frequency measure menlS are made on the truncated counter in f-i gure 8--6 1 as indicated. Determine if the counter is working properl y. and if not. isolate the fa ult.
~
'IIH
1111
DJ D 2 D I Do
crEN
H IG II -
pc
r
CTR DIV 16
-
r
erR I
CTR OIV 16
C
CTR2
'I (11'
11 11
"l"C
erEN
","
DJ D 2 D I Do
D ) D2D I Do
1C
LOAD
, -'" ~
CI~
0",
r-
i
PC
DJ D 2 Dr DIJ
TC -
CT£N
CTR DI V 16
i
erR3
TC
CFEN
rc
CTR OIV 1(;
r-[:)o-
C rR4
TC '
FIGURE 8 - 61
Solution
Check 10 see if the frequency measured at TC 4 working properl y.
i.~
correct. If it is. the counter is
truncated modulus = full modulus - preset count =;
16 4 -
82COI ~
= 65,536 - 33,472 = 32.064 The correcl frequency at TC 4 is MHz , = 1032,064 "= 3 11 88Hz . .
J4
Uh oh! There is a problem. ·11"1(' mearmred frequency of 637.76 Hz does not agree with the correct calculated frequency of 311.88 Hz. To find the f,mlty counter, detemli ne the actual tru ncated modul us as fo llows:
!.n 10 MHz modulus = - = = 15680 f eu 637.76 Hz • Because the tnmcatoo modulus should be 32.064. most likely the counter is being preset the wrong COUIll when it ll."t-)'clcs. The actual preset count is detcnnined as fo llows:
10
trollcated moou lus - fu ll modulus - preset count preset count = = = =
fu ll modulus - truncated mod ulus 65.536 - 15.680 49.856 C2CO I6
This shows that the counter is bei ng preset to C2CO l 6 instead of 82COl6 each time it recycles. Counters J, 2, and 3 are being preset properl y but counter 4 is nol. SinceC I6 = I ICN:>..!. Ihe IJ~ inpul to counter 4 is HIG H when it should be l OW. lhis is mosl like ly caused by an ope n inp ut Check for an external open caused by a bad solder connection. a broken conductor, or a belli pin ol1lhe Ie. If none can be found. rephlce the IC and the counter should work properly.
Related Problem
Determ ine what the output frequency
474
•
COUNTERS
Counters Implemented with Individual Flip-Flops Counters implemented with individual fl ip-nop and 2ate ICs are sometimes more difficult to troubleshoot because there aI-C many more inputs and outpulS wilh external connections than there are in an IC counter. The sequence of a counter can be altered by a single open or short on an input or output. as Example 8-1 1 ill ustrates.
Suppose thai you observe the output waveforms that are indicated for the counter in I-Igurc 8-62. Determinc if there is a problem wilh the counter. FIGURE
. ~ 62
elK
HIGH
f FO
FFI Q"
J"
J,
I>c
I>c
K,
K,
lOP-
h Q,
c" '
-
J,
c K,
eLK
Solution
Relnted Problem
I
SECTION 8 - 9 REVIEW
The Q2 waveform is incorrecl. The correct waveform is shown as a red dashed line. You can see thal lhe Q1 waveform looh exactly like the Ql waveform, so whatever is causing FFI 10 toggle appears to also be controlling FF2. Checking the J and K inputs to FF2. you lind a waveform thai looks like Clo. 111is result indicates that Qu is somehow getting through the AND gate. The only way this can happen is if the QI input to the AND gate is always HIGH. However. you have ~ n that QI has a conect waveform. This observation leads to the conclusion that the lower input to Ihe AND gate must be internally open and acting as a HIGH. Replace the AND gate and relest the c ircuit. Describe the Q1 output of the counter in Figure 8--62 if the QI output of FF I is open.
1. What failures can cause the counter in figure 8- 59 to have no pulse activity on any of the TC outpuh? 2. What happens if the inverter in Figure 8- 61 develops an open output?
Trouhleshooting problems that arc keyed to the CD-ROM llrt' available in the Muhisim Trouble.iliooling Pmctice seclion of the end-of-chapter problems.
DIGITAL SYSTEM APPLICATION
•
4 75
To o b\erve the time relationship between l"\.VO digital signals with a dual-trace 010110 scope, the proper way to bigger the .scope is with the slower of the l"\.VO signals. The reason for this is that the slower signal has fewer possible trigger points than th e faster signal and there wi ll be n o ambiguity for starting the sweep. Vertical mode triggerin g uses a composite of both channeh and should never be uled for determining absolute time informa tion . Since d ock Signals are usua lly the fastest signal in a digita l ¥tem, they should not be used for triggering.
The tramc light oontrol l}'Stem that was started in Chapter 6 and continued in Chapter 7 n completed in this chaprer. In Chapter 6. the oombinationallogic wa. devt! loped. In Chapter 7, the timing circ uits were
5equentiallogjc Requirements The IC
of the traffic lighu baH.'d on inputs from the timing circuits and the vehicle .ensor. The scqucntial logic will produce a 2-bit Gray code sequence f~ the four .tates of the \}'Stem that are indicated in Figure 8- 64.
developed. In \:his chapter, the sequential logic is developed and all the blocks arc connected to produce the complete traffic control system. The over
Block Diagram The sequential logic consists of a 2-bit Gray code counter and alSociated input logic, as shown in figure 8- 65.
Traffic light cootrollogic
Tr~ ffi<:
,
Combhwtiomd logic Sl'
AIR
Vehic le
MY
S" S,
se nsor ;n pt, l
MG SR
SY
1 1 1 Shon limer
W".
SG
Clock
-
limer Long tri gger
Tim in~
Shoo tri!(ler
ci"uits
-
1
o
Completed In Chnpler 6
0
Completed in Chnpler7
FIGURE 8-63 Tr.lffrc ligh t control syst em block diagram.
o
li!!"1 " ml
imerface unit
Completed in thi\ chapter
476
•
COUNTERS
Side
0 0 0 0 0 0
M~in
Main
Side
0 0 0 0 0 0
Side
0 0 0 0 0 0
Second ~r~re
Side
-
0 0 0 0 0 0
Third sl:!Te
r-ourrh
~l~le
t FIGURE '-64
Sequence of traffic light stiltes. FIGURE 8 - 6 5
Block diilgfilm of the ~quentiil l logic. lllpul logic
elK
•
l -bil Gm)
__ ----'r'-------' code counter
s" T"~l"l" S,
uecndcr
T~ Short Un~r (4 ~I Tl . LUll!! !rille' (::!.'i ,I I ,. \ichide ...cn'OC for rhe ,;0.: -.t1'l.'\:1
FIGURE 8 - 66
Sbte didgrilm for the tr.lffic light control ¥tcm.
.,
Fil'lil '11I1C
'\13in: I;reen
Side:: rat
r,
FourIh ~1"le
&cond <;late
10
01 Main: ydlow
Main: red Side: yenow
1j
t \~
Side: red
Third ... me
"
Main: red Sidc:grecn
"
DIG ITAL SYSTEM APP LI C ATION
The ,ounter produce" ~quenc:<: of four dates. Transitions from one state to the next "re determined by the 4 s timer, the ZS s timer, and the vehicle scnWl input. The dock for th e counter is the 10 kHz signal produc:cd by thc OKillator in the timing ciu:uits. State DiagrM'l Thc state diagr"m fOt" the traffic light control o/Item Wils introduced in Chapter 6 and is shown again in Figure
8-66. Ba~ on this state di"gram the ~ qucntial logic: operation k described as foll~.
Fint state:
side street light is red. The system ICm
provide the D inputs to the f1ip-flopl and the oountu is clocked by the '0 kttt clock from the oscillator. The irput logic: ~s frve
\>Alen the short timer goes off (1"s).
inputvariablcs: 0 0. 0" TLo T.... ard '1,. The D flip-flop traruition table is !hewn in Table 8-13. From the !tate diagr-am, a next-state table can be developed as 410'\.\0T1 in Tablc 8-14. The input conditions fOf T" T.... and V, for C<>Ch prcsent-state/next-state combination are li,ted in the table. From Ta ble 8-1] "ndT"blc 8- 14. thc logic conditions required for each r1ip-ftop to go to the I statc can be determined. For example, Ou goes from 0 to 1 wnen the present jtatc is 00 and the input condition il T(V,. a. indicated on the K:Cond rCNJ of Table 8- 1]. Do mmtbe" 1 to make 0 0 go to a 1 or to remain a 1
Third state: The Gray code for thilltate is 11. The main street light is rcd and the side \trcet light il grecn. The system remaim in this st"te whcn the long timer is on and the re is a ~hide on the side street. This il cxprened "I Tl 11,. The l)lttcm goes to the next state when the long timer g<>ei off or when there is no ~hjde on the side il:tcct. This is cxprCl~ as Tl + v,. Fourth itate: The Gray code for this iLlte is 10. The main stred light is rcd and the side street light is yellow. The 1)'Stem rema ins in thk state for 4 s when the short timer is on (TJ and goes back to the first stAtc whcn the short timer goes off ( 1's).
on the next clock pulse. For Do to be a " a logic expression can be written from r "ble 8-14:
Sequential Logic Impkmentatiot'l The diagram in Figure 8-67, ~ that two D flip-flops are u~ to implement the Grol)' counter. Outputs from the input logic
Do = OlJoTl V, + O,OuT, + Q, OoT~ + O,OoTlV, =
OIOuTtV, + Q,Oo + O,OoTlv,
FIGURE 8-67
Sequential logic d~gram.
--
II
s,.,
Inp!.lllogic
D"
Q,
I>c
L
D,
>c
TABLE 8-13
D r1ip-flop transition table . OUTPUT TRANSITIONS
o o
ON
+,
o
FLIP-FLOP INPUT
0
o
I
o
o
-'0 \lal~
\', deloder
10 I.. lIn :lud.
QN
477
and the side §!reet light is red. The ¥tem remains in this state for 4 s when the short timer is on (TJ and goes to the next state
The Gray code for this state is
00. The rT\,lin \treet light is green and the
•
Q,
478
•
COUNTERS
You can u~ a Karnaugh map to reduce the Do expression fu rther to
TABLE 8 - 14
Next-stilte tilble for the scquentiililogic tnlnsitions.
I
PRESENT STATE NEXT STATE Ql Qo I Q1 Qo
Also, from Table 8-14, ttlc expression for DI can be developed. VI = 01QoTs .... Ql00TLY,
.... QlOoTL ·1 QIQOV, + OIOoTs = OIQoT~
+ OIQo(TLV, +
Tl )
+ OIOOV, + OIQoT\ = OIOoTs + OIOO( V,
+ T"d
+ OIQOY, + 0100TS = OIOoTs ·1 OIOO(V,
+ Tl + V, )
INPUT CONDITIONS
-
FF INPUTS DI Do
0
0
0
0
T, • V.
0
0
0
0
0
I
Tt V,
0
I
0
I
0
I
T,
0
I
0
I
I
I
T,
I
I
I
I
I
I
I
I
TI. + V.
I
0
-
'Ii.
-
v.
-
I
I
I
0
I
0
I
0
T,
I
0
I
0
0
0
Ts
0
0
i · OIOoTs
= 0100TS+ 0 100 --I- 0 10 0Ts
0, --,- - --1
You can usc a Karnaugh map to reduce the 0 1 expression further to
Doand Dl are implemented M
~own
in
Figure 8- 68. Combining the input logic with the l-bit counter, the complete
sequential logic d iagram is shown in Figure 8-69.
T.,
- 1------,.,
D,
FIGURE 8-68
Input logic for tl'lc l-bit G1"iIY code counter. FIGURE 1 - 69
TI'lc 1Cquentiilllogic.
I T,
...!'-,
I
-[)
V,
l
1
-3
-
"" >e
Q,
Gruy
T,
lod..
.J'-
L
""'"
J
0 , Q,
l-
e
s,
SUMMARY
The Complete Traffic Ught Conbol SYJtem
47 9
5YJtem Au.ignment
The Interface OrcuitJ Interface circuib are llCCClsa ry became the logic canno t drive the lights directly due to the curre nt and voltage requirements, There are ,everal pollible w"YJ to provide an interface but two pOllible dCligm are pro vided in Appendix B.
Now that Ilo1:: have aU three blockl (combinational logic, timing circuits, and lequenl:i
•
• Adivity 1 UiC a Kamaugh map to confirm that the ,implified cxpreSiion fo r Dc il correct. • Activity 2 Usc a Kamaugh map to confirm that the ,implifled c)(prcSiio n for D, i, correct.
Tmftic light cuntrol logic
Tr~ ffic
li glll and interface unit
Comhillational logk Seclllcntia llogic
I
MR
Vehicle senw r input
S,
1.1 1'
S,
MG SR SY
1 1 1 Shoo lime r
SG
Clock
"'"'
t imer
I
Lung trigger Shurt trigger
limi ng circuits
f-
!
1 FIGURE 8-70
Block diagram o( the complete traffic light control Syltem.
•
Asynchronous and synchronous counters differ only in the way in which they are clocked. as shown in Figure 8-7 1 Synchronous counters can run at fasler clock rates than asynchronous CQUll t en;.
FIGURE ' - 71
HIG H
Compa riw n of alynchronoul and synrltronous counter!.
~
fllG I·t
J
e LK
C ~
K
l
-
HIG H
-
J C
~
Asyncht"OlllJUl'
K
Q
f--
J
Q
c
e LK '--- K
-
J
p. c K
SynchrOllous
C- Q
480
•
COUNTERS
•
Connectio n diagrnms for the Ie counters introduced in thi s chaptcr arc shown in Figure 8-12.
•
The max imum modulus of a counter i ~ the maximum number of posgble states and is a function of the- number of stages (!lip-Ilops). TI1US, Maximum mooulu s = 2 w where" is the number of siages in the COUntcr. TIle modu lus of a coumer is the (lellwl num ber o f slates in ils ~eqllencc and can be equllltoor less th an the maxim um moo ulus.
•
Q.
Q,
Q,
,c
Q,
"
C
c
CTR Dl V to
C
Rcn <4.
,
Q,
Q,
D,
o Q. Q,
QJ C/:,T
Q,
CTR DlV 10 D,
cduct of Ihe modu li of tI,c ind ividual
f),
c
0 , eEl'
Q,
Q,
V,
D,
QJ (NT"
D,
D,
D.
D, WI'
741·1C16 1 4-bit syochronous bin"ry coume r with II.'>YlIChrunous clear
Q, EN!" D,
CTR Dl V 16 UJIlf) D"
Q,
CTR DIV 16 U M
a~
"
74 F 162 synehwnous BCD decade coumer wi th lIS)·'lChronoos clear
74LS934 -bi l llSynchronous binary Ci)untcr
ClJ(
i~
11K: oveli1 tt Ill<.ldutu.<. of C11.<.CilUro countcr... counters.
Q,
D , FNf'
erR Dl V LO Q"
(; DJWUI' Q,
Q,
74HC 19() ~yllChronous
74HCl63 4-bit syllChronou~ binary countCf with S)'nctJrOlluus clear
up/down dec ade coumer IG is Coon, Enable .,
FIGUR E 1 - 72
Note that the labels (nameJ of input! and outputs) are consident with teJ
KEY TERMS
Key tcl"l'rn and other bold tcrrm in the chapter are defined in the cnd-of-book glossary. A.'.~·ochroollu.';
Not occurring 111 the same time.
Ca...cade To con nect "cnd-to-end'" as w hcn !;Cvcrnl cou ntcrs are connected fmm the terminal count outpu t of one counter 10 the enable input of the nex t counter. Del"ade ChardClerizeO by ten states or values.
l\lodulus l "e number of unique states throug h whic h a COU nter will
~'-'q uence.
Recycle To undergo transition (as in a counterl from the fina l or terminal );tate back to the initial state. S tate diagnlln A g raphic depiction o f a sequence of staIb or \'al ues. Siale machin(- A logic system eJ\hibi ti ug a sequence of statCS condi tioned by in tcmallogic :lnd cxlernal inputs; tiny sequential circui t exhibiting Il specitit!d sequcnce of stales. S.mchronolls Occurring:lt the same time. Terminal (."oll nl The final slate in
iI
counler's sequence.
PRO BLEMS
Ans~n
•
481
ilre ilt the end of the
I. Asynchronous cou nters are known as (a) ri pple counters
(b) m ultiple clock counters
(e) decade cou nters
(d) modulus coullIers
2. An a~ynchronous cou nter differs from a Sy nchHlrlOus counter in (a) the num ber of st
(b) the method of clocking (e) the Iype o f ni p- n ~ uSc
3. The modu lus of a cou nter is (a) the number of fli p-flops (b) Ihe
(d) the max imum possible num ber of states
4. A 3-bil binary cou nter has a max imum modulus of (a) 3
(d 8
(b) 6
(d) 16
S. A 4--bit binary cou nter has a maximum modulus of (a) 16
(b) 32
(e)
8
(d) 4
6. A modul us- 12 cou nler mUSI h.w e (a) 12 fli p-flops
(b) 3 flip-flops
(e) 4 flip-flops
(d) sy nchronous clocki ng
7. Wh ich 0f1t! of the fol lowing is an example of a (a) Modulus 8
(h) Modulus 14
(d Mod ulus 16
(d) Modu lus 32
eount~
wilh a lru ncated modul us?
8. A 4-hil ripple cou nter consisls of Oi p- Ilops th
(b) 24
n.~
(e) 48 IlS
(d) 3(i ns
9. A BCD counter is an example of (a) a full -modulus counter
(b) a decade eoulll cr
(e)
(d ) answers (b) and (c)
10. Whi ch of the following is an invalid state in (a) 1100
(b) 0010
oll1
X42 1 BCD counter"
(d) I(X)()
(e) 0 101
11. Three cascaded moo ulus- l0 cou nters Imve an overal l modulus of (a) 30
(b) 100
~C)
1000
( tl)
10,000
12. A 10 MHz d uc\.. frcq uem:y is applied to OJ cascaded counler consisti ng of ~ modul us-5 cou nter. a mool1lus-8 coonter. and two modul us- I0 counters. The lowes t ou tpu t frequency possible is
(a) 10kHz
(b) 2.5 kH7.
(e) 5 kHz
(d) 25kHz
13. A 4--bit bi nary up/down l"OUtlier is . 11 the binary state of zero. -OlC next state in the DOWN mode is (a) 0001
(b) 1I I I
(e) 1000
(d) 1110
14_ The terminal count of a mod ulus- 13 binary eoumer is (a) f.(I()()
PROBLEMS SECTION 8-1
(b) 11 11
(c)
1101
h]) 1100
AnswerJ to odd- num bered problems ilrc ilt the cnd of the book.
Asynchronous Counter Operation I. For the ripp le cou nt er shown in Figure ~ 73, show the complete tim ing diagra m for cighl cloc k Pliiscs, showing the clock, Qo. and QI WaVCfOnllS.
482
•
COUNTERS
FIGUR E 8 - 11
HIGH
~
-
1, C
eLK
~
Qo
C
J
Ko
r- Q,
1,
K,
2. For the ripple coumer in Figure 8-74, show Ihe complert: liming dilt£nlm for sixleen clock pulses. Show Ihe clock, Qu. Qh and Q2 wavt:form s. FIGURE 8 - 14
HIGH
f-
- Qo
lo
c
eLK
K,
~
-
1, C
J
L
Q,
C
J
K,
f--
1,
,
K
3. In the cou nter of Problt:m 2, assume th at cach fl ip-flop has a propagUlion deby from the Irig~ering edge of the clock to a ehallge in the Q ou tput of 8 ns. Dctcnnine tI:e worst-ca"c (l on ge.~I) delay time flOm a clock pulse to Ihe arrival of the counter in a given Slate. Specify thc state or states for wh ich th is worst·case delay oc"Curs. 4. Show how 10 connect a 74LS93 4-bil async hronous cou nter for cach of the following moduli: (a)
SECTION 8-2
9
(d) 14
(c) 13
(b) I I
(e) 15
Synchronous Counter Operation 5. If the cou ntcr of Problem 3 were synch ronous rat her Ihan asynchronous, whl t wou ld be tht: longest delay timc? 6. Show the complete timing diagr,un for the 5-slage synchronous bi nary cou nter in Figure 8-75. Veri fy that the wllvcfonns of the Q outputs represent the pro per binary numtx:r Ilftt:r each clock pulse.
Jt--}
IIIGl1
1,
>C K"
~
J
JQ,
}
J } ~ Q,
J,
1,
1,
pC
pC
pc
pC
K,
K,
K,
K,
J,
eLK
FtGURE 1-15
7. By analYl;ing the J and K in pUlS 10 ellch fl ip-flop prior to t:ach clock pulse. prove thaI the decade coun ter in Figure 8-76 progresses through a BCD scqucn(."C. Explain how Ihcsc conditi ons in cach case CllllSC thc counter to go to the next proper slate.
PROBLEMS
1
HIGH
QI
'I
J" C
K,
'}
J
J,
}
Q,
J,
483
l '>
f-o,
,I ,
Q~
pc
>c
>c
K,
K,
K
,
m
1'1'1
FrQ
]
•
Q,
P-
A'3
CI K FIGURE 8-76
8. The waveforms in Figure 8-77 arc applied to the <.:ount enahle, clear, anti clock inputs as indi<.:atcil Show Ihe counter Oll tput waveforms in proper re lation to these inpu ts. TIle clear input is asynchronous. FIGURE 8-71
L
Cf"£N' _ _ _--'
C(fJ,' -
CLK
CTR Dl V 16
CI K
u
C
CI..R
9. A BCD oCt:adc <.:ou nt~r is shown in Figure 8- 78. The wavcfonns arc applied 10 lhe cloc k and clear inputs as ind i<.:atcd. Dctemline Ille wavcfonns for eaeh of the cuunlcr OI.IIPUIS (Qo, Q h Q2' and QJJ. T he clear is sy nchronous. and the (."Ou nter is initiall y in the binary 1llC.XJ state. FIGURE 8 - 78
e r R DIV 10
c
e LK CLR
10. The wavefomls in Figure 8-79 arc applic
f--lL--J1-JL-Jl Il,Jl- , , : ------~-+----------CLR -1~--------~--~~~ ,, eNI' -----------<--+----iLJ~------~~ ,, ----------, ENT LJ ,,
eLK
I
LOAD -----------~r--------------------------1 I. The w!lvcfonns in Figure 8-79 are applicd to a 741'162 ,,:oullicr. DctCflllirc the Q outpu ts and the rc. The inputs arc Ou = I, 0 1 = 0. Oz -'= 0, and 1)3 = I.
48 4
•
COUNTERS
SECTION 8 - 3
Up/ Down Synchronous Counters 12. Show a complctc timing di agram for 11 3-biLup/down counter t1wl gOt-'S through the following sequcnce. Ind icate when the counter is in the UP mode and whcn it is in the DOWN mode. Assume positivc edgc·triggeri ng. ~ I ,2.1L I ,2,14.5,~S,~3,2 . 1 , O
13. Develop the Q output w1lVefOn lls for a 741-1CI90 up/dow n counter with the input waveforms shown in Figure 8-80. A bin1lry 0 i~ on the ool1l inputs. Stal1 with a cou nt of CXXJO. FIGURE 1 - 10
e LK
, I
-
c rt"N
L t __
DIU
I I
I
I
I
I
I
I
,--cI'r ____ _:'I ----+_ _ _
r---i
I
'-+----------J----t'- -;i'------LI'----- +
- - - ----iU f - - - - - --
WAD
SECTION 8-4
I I
--+___i'- --'--'
-----1
--iL Jf--- -
Design of Synchronous Counters 14. Dclcnlline the sequcnec of the coul11er in Figure 8-8 1.
FIGURE 8 - 81
r\ ~
Q"
D,
""C
Q,
r;;,
D,
I>c
e
eLK
15. Detcrmi ne the sequcnce of the counter in Figure 8-82. Begin with thc counter clcarcrl.
BlGIl
b
J"
J,
Ii,
Q"
D
c
e
K,
K"
J,
0,
0
J,
c
e K,
L
fo,
K,
eLK FIGURE 8 - 82
16.
~igll
a counter 10 producc the following St:q ucncc. Usc J-K n ip-nops.
00. 10. 0 1. I I. 00, . . . 17. Design a counter 10 produce the fo llowing binary SC!jucnce. Use J-K ni p-flops. 1,4,3.5,7, 6,2, I,. 18. Design a counter 10 produce the fo llowing binary sequcnce. Use J-K nip-flop~. 0,9, 1, 8,2,7,3, 6,4,5,0, . . .
PROBLEMS
•
485
19. Dt!sign 1I binary <."()unler with the sequence shown in Ihe Slille diagram of FiguI'C 8-83. FI GURE 8-83
Up
II
3
DlI\\'n
,
9
SECTION 8-5
Cascaded Counters 20. For each o f Ihe cascaded counter configurations in Figure 8- 84, detennine the frequency of the wavefonn at eae h point indicated by a cireled ntlmbcr, and de tennine the overdll modulus.
FIGURE 8 - 14
J kHI.
----I DlV 4 ~ DtV 8 ~..92...
(,)
= CD ~~-I
lOOk l~z -~-~~ .
DIVl
(i) r-
( b)
.----, CD
2 I MI-I Z -l o IV 3 M
DI V6
I (i) _ = ~~~
~~
(d
r:--, (i) r=::-:-1 (j)
39.4 kHz
Dl V4
DIV6
®
(i)
~
Cd)
21. Expand the counter in Figun.: 8-4 1 to creale a dividc- by- IO,(J(X) counter and a divide-byIOO,OOOeounter.
22. Wi th general block diagrams, show how to obwin the following frcqueneic.~ from a 10 MHz clock by USi llg single nip-nops. modu lus-5 countc.-!;. and decade counters:
SECTION 8-6
(a) 5 rvl J-I1.
(b) 2.5 MHz
(C) 2 MHz
(d) I
(f) 250kl-lz
(g) 62.5kHz
(h) 40kHz
(i)
M H~.
10kHz
(e) 500 kH z
Gl
I kH z
Counter Decoding 23. Given a BCD decade counter with only the Q outputs ava ilable, show whal decodi ng logic is requin.'(] 10 dccoc.lc each of Ille following stiite~ and how il should be connocted 10 the counter. A WG n output indication is required for each decoded state. 1l1C MSB is 10 the left.
(a) 0001
(b) 00 1J
(e) OIQ!
(d) 011 r
(e) 1000
24. For the 4- bi' binary counter connected 10 IlIC decoder in Figure 8-85, detcnllioc each of IllC decoder outpu t waveforms in relitlion [0 [he clock pulses. 25. If tile counter in Figtlrc 8-85 is asynchronous, delcmline where the Jcuxling g litches occur on the rn:.'COder output wa\"cfonns.
486
•
COUNTERS
FIGURE 1-15
BIN/DEC
o
CTRO IV 16
2 3
, 4
Q,
6 7
8 9
10 11 12
eLK 2.
3 4
j
6
7 II
c
') 10 I I 121314 Ij 16
13 14
"
26. MOllify Ihe ci rcuit in Figure 8-85 10 e li minate decoding glitche.~.
27. AnalYl..e the counter in Figure 8-45 for the occurrence of glitches on the decode ga te outpul. If g li tche~
occur, suggesl a way
10
clil ninate them.
28. Analyze Ihe Cllll nter in Figure &-46 for the nccur!'Cm.'C nf gli tc hes nn the ou tpuls of the ~oding gate!;. If gli tch..:s OCCt.Jr. make a design change tllat will e!i minale Ihem.
SECTION 8-7
Counter Applications 29. As.<;ume thatthc di gita l clock of Figure 8--5 1 is initially resct lo 12 o'clock. Determine the binary Slate of each counlcr after si,;ty-two 60 Hz pu l sc~ have occllll"cd .
30. What is the Olltput frequency of e<1cll I:ounter in Ihe digital clock circuil o f Figu re 8--5 1? 31 . For t he automobile parking control system in Fij,!ufc 8--54, a pattern of enmlnCC lind e,;it scnsor pulses durin g a givcn 24-hour period arc shown in Figure 8-86. If thele were 53 cars already in the garage aI Ihe beginning of the period, whal is the stat e of the cou nter at the end of Ihe 24 hnun;? FIGURE I-B6
Entrance I~ UUe-"UCJ'-JUJJWL...'L...JL_"JWWLJLJL-'WLJLJL"e'L...JLJLJUL..._"U'J'-JU'uuue-,,_,
,,
lOCBS()f 1-
Exit : __...JUL...JLJL...JlJL____...JL...JL...J'U'Ul____JUUlJLlUUl__-" __lU'ULJLJLJLJLc I
~n'or
o
24 hrs
32. The binary Tlum ber for decimnl 57 appears on the parnlJel da ta inputs of the parallel-to-seri al con,-en er in Figure 8-56 (Do is tiT(' LS8). 'Ibe coun ter ini tiall y contai n~ at! zeros and a 10 kHz clock is app lied. Devclop the timing diagntm showi ng the clock, the counleroutpuls. <111(1 th e serial data output.
SECTION 8-9
Troubleshooting 33. For the enUiller in Figure 8- 1. sllQw the timing d iagrrun for the Qo and Q 1 w;wcforms for each of the following faults (Ms wne Qo and QI are initially LOW): (a) clock input
10 FFO
shorted to ground
(b) Q" outpu t open (c) clock input 10 FF ! open (d) J input to FRJ ope n (e) K input 10 FF ! shoncd 10 ground
PROB LEM S
•
4B7
34. Solve Problem 33 for tht: counter in Fig ure 8-- 1 I. 35. isolate the fau h in the counter in Figure 8- 3 by analyzing the wavcfonns in Figure 8--87. 36. From the waveform di agrdm in Figure 8-88. detenll ine the most likel y filllit in the cou nl er o f Figure ~- 14 .
eLK
e LK
eo
o
o
QI
0
o ~
.L-J
+-__-'____ ____'-__-r____+-___
____
~
eo
L
e, FIGURE' 11
FtGURE ' - 11
37. Solve Problem 36 if the Q, ou tput ha~ the waveform observed in Figure 8-89. Outputs Qo
eLK
JIlYlJ3U
4
o o
Q,
38. You :Ipply a 5 MH"I; elock to Ihe cascaded counler in Figure 8-44 an d measure a frequeucy of 76.2939 Hz at the last ReD output. Is this corrccl. and lf nOI. whal is the most likely pnJblem? 39. Devclop a lable for lise in testi ng the counler in Figure 8-44 that will show the frequency aI the fina l ReD outpu l for all po!;si blc open fai lures of the parallel data inpuL<; (0 0) D I '~' and OJ) taken one at a time. Usc 10 MH7. a~ the Icst frcquCJlcy for the clock. 40. The le n ~-of-hour.l 7-scgment display in the digital clock system of Figure 8-51 continuously di~ plays a I. All the other di gits worl:. properly. What could be the proble m'! 41- What would be the visual indicminn of an open Q r oulput in the tens portion of the minu tes counler in Figure 8-5 1? Also sec Figure 8- 52. 42. One day (pcrh..1ps a Monday) com plaints begin nooding in from patrons of a parking garage that uses the conlrol syslem depicted in Figures 8-54 and 8- 55. The patrons say that they enter the garage bcx:al.lsc Ihe gate is up and the FULL sign is o ff bu t thai, once in, Ihey can find no em pty ~p.
Dip l System Application 43. [mplemcnl thc inpu t logie in the scquelll.ial ci rcuit ponion of thc lroffie lighl con trol ~ys t e m usi ng only NAND gates. 44. Replatt the D fli p- nups in the 2-bil Gmy code state counter in Figure 8-67 with J-K nip- nops. 45. Spedfy how you wou ld e hange the time interval for th e grecn light from 25 s to 60 s.
SpeciaJ Design Problenu 46. Design a llIodulus-1 00 cou nter by us ing 74 F162 decade COUllter.'i. 47. Modify lhe design of the counier in Figurc 8-44 to achieve a modu lus of 30,00. 48. Rcpcllt Problem 47 for II modu lus of 50,00. 49. Modify the di gital clock in Figures 8- 5 1. 8-52, and 8- 53 so Ihat it can be presel to any desired time. SO. Design an alann ci rcuit for the di gi tal clock thai can deteel a prcdclemlincd time (hours and millu tes only) and jJroouce a s;gnalto acti vate an audio al:lrm.
488
•
COUNTERS
51. Mod ify the design of the circuit in Figure 8-55 for a lOOO-space parking garage and a 3000space parki ng gara!,'C. 52. ImplelTlellt the parallel-to-serial data convc r~i on logic ill Figure 8-56 with speci fi c fi xed· function devices. 53. In Problem 15 you found thai the counter locks up and alternates betwccn two states. It turns OuI that thi ~ ope ration is the resu lt of a design naw. Redesign the counter SO that when il goes inlo the second of lhe loc k-up stales. il will recycle III the all-Os stale on the ncxt clock pulse.
54_ Modify the block diagram of the tm ffi c light conlrol system in Figure 8-63 to renect the addition of a IS s left turn signal on the main street immediately preceding the green light. Multisim Troublruhooting Practice 55. Opc n file F08-55 and tcsllhc4-bi! asynchronous counte r to ddeJm ine ifl hert: is a fn ul!. If there is a faul!. identify it if possible. 56. Open fi le P08-56 and test the 3-bi! synchronous cou ntcr to deternUnc if there is a fau lt. If there is a fau lt. identify it if pos~ ible. 57. Open file F08-57 and tcst the BCD counter todelcnn ine if there is a fault. [f there is a faull , identify it if possible.
58. Open file F08-58 and teSt the 74163 4-bit binary counter 10 dClermine if there is a faulL If Ihere is a faull. iden tify il ifpossible. 59. Open fil e P08-59 and test the 74 190 Up/Down decade counter 10 detcnni nc if there is a fnulL If there is a fault. ide nt ify il if possible.
SECTION REVIEWS SECTION 8-1
Asynchronous Counter Operation I. Asynchronous mcan~ that cnch flip-nop IIfler the fi rst ont! is enabled by the UJ tpu t of the preceding nip-n op.
2. A modu lus- 14 coullter has fourleen Slates requiri ng four nil,..nops. SECTION 8 - 2
Synchronous Counter Operation 1_ A ll flip-nops in a synchronous eou nler arc clocked sirnulll1tlcously.
2_ The cou nter can be preset (i nitiali7.cd) to lilly gi\'cn slate. 3. Counter is enabled when ENP and £ NTare oolh H IGH: ReO goes HIGH whe n fin al Slate in sequence is reached.
SECTION 8 - 3
Up/ Down Synchronous Counters I. '!lIe COU[ller goes to 1001
2. UP: 1111 : OOWN: 0000; th e next state is I I I I.
SECTION 8 - 4
Design of Synchronous Counters I . J -= I , K = X ("don'l care") 2. J = X ("don't care"), K = 0 3. (al The ncxl stale is 1011 .
(b) QJ (MS B): no-<:hange or SET; Q1: no-c1wnge or RESET; QI: no change or SET; Qo (LSD): SET or toggle SECTION 8 - 5
Cascaded Counters I. TIlrcc decade counters produce 7 10CXl: 4 decade coonlcrs proo ulX + 1O.0CXl.
2. (a) 720: nip-nop an d DIV 10 (c) + 160: DIY 16 and DI Y 10
(b) + 32: Ili p- nopand DIY 16 (d) 7320: D IV 16 and DIV 10 lind flip-nop
ANSWERS
SECTION 8 - 6
•
489
Counter Decoding I. (aJ 1\0 transitional states because there is a single bit change (b) ()()((). 0001.00 10. 0101. 0 11 0.01 11 (c) No transitional states because there is a single bit change (d) 0001.00 10. 00 11. 0100.010 1. 01 10. 0 111 . 1000. [00 1. [010. 10 11 . 1100. 1101 . 1110
SECTION 8-7
CounterApplications I. Gate G I resets nip-flop on first clock pulSt: after cou nt 12. Gate G~ coulller to 000 I.
den)(l~
I:ount 12 10 preM!!
2. The hour:; decade countt:r advances Ihrough each ~Iale from "l.ero 10 nine, and as it rn:yc\cs flOm nine bock 10 l£ ro. lilt: flip-flop is t~lcd 10 the Sbil!Jate. This produces a ten ( 10) on the display. When the hoon; decade counter is in state 12. the dtlcodc NAND gate C"olUSt% the countcr 10 recyc le 10 ~e 1 OIt Ihe next dock pulse.1be flip-flop rcst:ts. This resu lts in a one (01) on lhe display.
SECTION 8 - 8
Logic Symbols with Dependency Rotation I. C: conlrol. IJsuall y d ock: M: mode: G: AN D
2. D indicates dala slornge.
SECTION 8-9
Troubleshooting I. No ptJlses on TC outputs: CI1:N of first counter shortcd to ground or 10 a LOW; clock inpu l of first counter open; d ock line shOr1ed to ground or 10 a LOW; TC outpul of fi rst counter shorted 10 ground or to a LOW. 2. Wi th inverter output open. the counter dues 1101 recycle at the preset l:uo nt but acts liS a fullmodu lus counter.
RELATED PROBLEMS FOR EXAMPLES 8-1 S<>e Figure 8---90.
FIGURE 3 - 90
a~
~~ ~ffi! ' i~ jIIT I ii ! i' ii 8-2 Connect Qn to the NAl'JD tlate as a third inplII (Q2 and Q ) are twu of the inputs). COllllet:t the line to the eLI? input of FFO a~ welJ a~ FF2 and FF1.
eLi?
8-3 Set: Figure 8-9 1.
8-4 Sec Figure 8--92.
CLKA e LK B
c
~ RUm
c
74U;93
UI'lOOWN C>~
,,<,,,",,;{:::::::r:
o,~~~
Q,
-<.
"' j Q,
o fiGURE 8 - 91
I I I I ~ llllllllllll :: ::: 11111 L..L.i , , I I , , I , I I , , I , , , I , I , I I I , , I I I I I 15 1 141 13 1 12 I tj I 14 I 15 I 0 I , I 0 I 15 I 14 I 15 I 0 I
FIGURE 8 - 92
490
•
COUNTE RS
TABLE 8-15
PRESENT INVALID STATE
J-K INPUTS
QJ
Q,
Qo
h
Kz
o o
o
o
o
o
o
o o
o
J,
K,
NEXT STATE
Jo
Q2
I
Ko
Q,
Qo
o
o
o
o
o
vaUd sta te
o
o
vali d state
()
S-S Sec T:tblc 8-- 15. 8-(i
Appl ication of Boolean algebra to the logic in Figure 8--37 shovn; that the output o f eHeh
OR g:tle agrees with the ex pression in SICp 5. 8-7 Fh'c decadc touutcrs arc req uired. lOS = ]OO,Q(() 8-S J(!iI = I MHzll( IO)(2) 1 = 50 kHz
S-9 Sec Figurc 8- 93. 8-10 8ACO l6 wou ld be loaded. 164
I.e> =
- 8ACO l6 = 65,536 - 32,520 = 30.0 16 10 MH7/30.0 16 = 333.2 Hz
8-11 Sec Figure 8- 94.
OJ<
n..n..n..nI1..Il...f1SL
1 ~ ' >-L-t " QG .J1---l1~ I LLJ I LLJ I LLJ I LLJ
Q, o
I I , , I I I I I I , I I 1 11 1 I I I I I I I ! I I ' I ! I I I I
Q> ~
FIGURE 8 - 91 FIGUR E 8 - 94
SELF-TEST I. (n)
2. (b)
3. (b)
4. (c)
5. (a)
6. (e)
9. (d)
10. (a)
11. (c)
12. (b)
13. (b)
14. (d)
7 . (b )
8. (e)
SHIFT CHAPTER OUTLINE
CHAPTER OBJECTIVES
9-1
Basic Shift Register Functions
Identify the bailC(onm of data ITIO'.Iement in shift rcgistcil
9- 2
Serial In/Serial Out Shift Registers
9-3
Serial In/Parallel Out Shift Registers
Explain how seri,,1in/senill out,. seri,,' in/parallel out, par
9- 4
Paralle l In/Serial Out Shift Registers
9- 5
Parallel In/Parallel Out Shift Registers
9-6
Bidirectional Shift Registers
9- 7
Shift Register Counters
9- 8
Shift Register Applications
•
Construct oil ring counter from a shift rCgKter
9- 9
Logic Symbols with Oependency Notation
•
Use a mift register as a ti~e ray device
9- 10
Troubleshooting
I::I:D
•
Digital System Application
Use a Ihift register to implement a \t:rial-to-parallel data converter
•
DeKribe how a bidire€;tional m ift register operata
"
Detelmine the sequence of a Johrnon coun te r
Set up a ring counler to produce a specified sequence
Implement oil b..uie shift~rcgister-cootrolled kcybooiIrd encoder InterpretANSlflEEE Stilndoilrd 91-1984 ,hift reg;.tcr symbols with dependency ootiltion
Usc shift legilters in a \)'Item applica.tion
KEY TERMS Regi~ter
lOoild
Stage
Bidirectional
INTRODUCTION
Shift registers are a type of 1e
Shift FIXED-FUNCTION lOGIC DEVICES
•••
74XX164
74XX165
74XX194
74XX195
74XX174
DIGITAL SYSTEM APPLICATION PREVIEW
The Digital System AppJicab·on illustrates the concepts from this chapter. A security entry system for controlling the alarms in a building is introduced. The !)'Stem uses two types of shift registers as well as other types of devices covered in previous chapten. The system also indudes a memory that will be the focus of the digital system application in Chapter 10.
Study aids for this chapter are available at http://www.prenhoilll.comifloyd
493
494
-
9- 1
SH IFT REG ISTERS
BASIC SHIFT REGISTER FUNCTIONS Shirl rcgistcrs consisl of mntngcmenls of nip-flops and are important in applicat ions involving thc storage and transfer of tlata in a d igital system. A register. unlike a countcr. has no specifieJ sequence of slales, except in certain very specialized applications. A register, in general, is used solely for storing and shifting dma ( Is •.IIld Os) entered into it from an external source and typically possesses no characteristic internal sequence of states. After completing this seCTion, you should be able to • Explain how a nip-flop stores a data bit - Define the storage c~lpacity of a shift register - Descri be the shirt capability of a register
A regisler is 11 digital circuit with two basic fu nct ions: data storage and data movement. The storage capability of a register makes it an important type of me mory device. Figure 9- 1 illustrates the concept of storing a I or a U in a D nip-Ilop. A I is applied to
A rewster can consist of one or more flip-flops u~d to store and shift dab.
,, eLK ..JL-
--jv
-
Q
o, -
JI When a I ison D.
--j>c
Q be",,,mcs a I al Ihe
,
----lv
CLK ...fL- - > C
lri~ l:"ri ng e
Whe n a 0 is on IJ,
Q b<.'<:OI1lIS :l 0 a t the lri~ gerinl!edl!c or eLK or remains a 0 if alread),
in Ire RESET SI
FIGUR E 9- 1
The flip-flop 3! a Itorage elemen t.
0..(;, in
@ ~,,~, (a) Serial io/shif! rightlserial Ullt
(bl Serial in/shift leftl..eri:tl OUI
D31:l
""";" ~ \.
I
DalauUI Ill) Senar inlparaJlel ou t
(c ) 1",m,lIcl io/scrial .)l1I
in
w
~ OataoU!
Ie ) l':l mllcl in/par
(0 Rnla1 e rig hl
(g) Rot;.,[c 1;:(1
FIGURE 9 - 2 Basic dab movement in shift regi.tcn. ( Four bits a re UJed flX ifjultration, The bits move in direction of the a rroM.)
the
SERIAL IN/S ERI AL O UT SHIFT REGISTERS •
495
thc data input as shown, and a clock pulse is applied that stores the I by settinf( t.hc nipnop. When the 1 on the input is removed. the flip-flop remains in the SET state, thereby storing the 1. 1\ similar procedure applies to the "torage o f a 0 by resetting the fli p-flop. as also illustrated in Figure 9-1. The storage c:aptlcity of a register j" Ihe total number of bits (I s and Os) of digital dala it can retain. E..lC;h stage (nip-flop) in a shift rcgi!'ter represents one bit of stomge capacity; therefore, the number of stagcs in a register dete rmines ils .~ toragc capacity. The sllift capabi lity of a registcr permits the movement of data from "tage to stage within the rcgister or into or out of the rcgi"tcr upon applicat ion of clock pulses. Figure 9-2 ill ustrates the types of data movcment in shift registers. The block represents any arbitral)' 4-bit register. and the arrows indicatc the direction of data movement.
1. Generally, what is the d iffere nce between a counter and a Ihift register? AmwelSare at the end of the
2. What two p n'nd paf functions are perfo rmed by a shift registe r?
ch;)prer.
SERIAL IN/SERIAL OUT SHIFT REGISTERS
9 -2
The serial in/serial OUI shifl reg i~ te r acce pLS data serially-that is, one bit at a time on a single line. It produces thc stored information on its output also in serial form. Aftc.r complcting this section, you should be able to • Explain how data bits arc serially e ntered into a shift register . Describe how data bilS arc shi fted through the registcr • Explain how data bi ts are serially take n OUI of a shin regis ter . Develop and analyze ti ming diagrams for serial in/serial out registers
Let's firsllook
S.:ri;,1 ILlta
-
mput
FFI
~D ~D ~D ,- pc C- pc C- pc C- pC D
f-'!'-
S".n..J dJt3 '.Up'"
~ "-:n;11 ,1:lhl nU'pm
register in a computer.
,
For Odmple, • register may be I Plio. to .a.n Mithmetic o r other operation. One way that registers in a computer are dcared il ~ng w(tware to subtract the
e LK FIGURE 9 -]
Seriat in/serial out ~ift regnler.
course, will alw¥ be
Figure 9-4 ill us trates entry of the four bi ts 1010 into the register, beginning with the , zero. For exa~e, a cCimputt'l" right-must bit. Thc register is initially clear. lllC 0 is put onto the data input line. making instruction that performs thil D "'" 0 for FFO. When the firs t clock pulse is applied, FFO is resel, th us sloring the O. ~perdti~n", SUB Al.AL With th;} Next the second bit , which is a I, is applied to thcdata input , making D = I for FFO and mstroctiCln, the registe r named Al D = 0 for FF I because the D input o f FF I is connected to thc Qo output. Whcn the second is cleared.
I I
496
•
SH IFT REGISTERS
FH)
"",, -
.....!L D
D
inpu t
C
m
1'1"2
I'fl l
r--!!.-
.....!L
D
c
I>c
D
r-Jl- Q,
\>C Ih'~Sl !tr
ini li nlJ)
C LEA R
-
D
C-
>C
.....!L C-
D
I>C
r-2C-
D
.....!L
>C
D
_0_<1,
I>C A tlcrCL K I
a.KI
J"L -
D
c-'-
I>C
D
I>C
f-'-C-
D
I>C
f-o--C-
D
f---.!!- Q,
pC A llel" CLK2
Cl X!
.JL
3n1 ,j;lla hil == n
-
D
r-2-
I>c
D
t-l-
I>c
D
r-"-
I>C
D
f---L Q,
I>C Ariel" CLK)
CLK)
Jl..
41 h tlam bi1 == I
-
D
I>c
t-'-
D
I>c
r-!'-
D
I>C
1---"---
D
I>C
f--l'--- Q, Art.,. C LK~. lhe 4,bit Jbcr i, cumpletd)
"" Slor,'tl in
~gblcr,
nK~ Jl.. FIGURE 9 4
Four bib (1010) being c ntcrc{hcriilily into the rcgiltcr.
For leria] data, one bit at a b'rne is transferred,
clock pulse occurs, the I on the data input is shifted into FFO. causing FFO to set; and the a Ihat was in FFa is shifted into FF], The third bit, a a. is now put onto the data-input line, and a clock pulse is applied. "Ille a is entered into FFa. [he I stored in FFa is shifted into FF I, and [he a stored in FF I is shifted into FF2. The last bit, a I, is now applied to the data input. and a clock pulse is :I~licd , This time the J isenlered into FFO, thea slored in f}l) i .~ .~ hifted into FFI , the I stored in FFJ is shifted inlo H"2, and Ihe a stored in Fl-L is shifted into FF3. This completes the serial entry oft hc four bits into the shift register, where they can be stored for any le ngth o f time as long as the nip- flops have de power,
SER IAL INfSERIAL OUT SHIfT REGISTERS
FFI
FFO
o-
0
-'-
>C
~
D
.
FF2
pC
D
-'-
r-J!Q,
0
C- pC
I>c
After elK... r~!!i~lcr ,-unt"l ns WID.
eLK
o-
D
--L
>C
f--'- D
D
pC
.....!'--
pC
2nd OOtu bl! f--:!Q,
D
pC After el.KS
o-
D
--L
~
D
>C
D
-
I>c
C
3n1 ,lata bit ~ Q,
D C
At(~r
Cl K6
CLKf> ..JL
o-C-
D
--L
~
D
>C
C
D
--L
_lIh tlal3 bi1 r--!Q,
D
C
I>c
A!kr elK7
elK7 ..JL
o-
v C- >C
--L
D
C- pC
f--L D - I>c
--L
D
C- pc
f-.!'.-Q, After eLKl!. rc"\tcr i~ n.E AR
el.K!!
JL
FIGURE 9 -5
Four bib (101 0) being «eriaJly ~I'li(ted out of the register and replaced by all zerm.
If you want to get Ihe data Olll of the regis ter. fh e bits mUSI be s hifted OUi seria lly and taken o ff the QJ output, as Figure 9- 5 ill ustrates. After CLK4 in the data~entry operatioll just described, the righi-most bil, 0, appears on the Q~ OUlpUi . W hen cloc'k pu lse e LKS is applied. the second bit appears on the Q) output. Clock pulse CLK6 shifts the Ihird bil lo the output. and CLK7 shifts the fourth bit 10 the out put. Whi le the original fo ur bi ls are being shi fted out, more bits call be shifted in. All zeros are shown being shifted in.
•
497
498
•
SH IFT REG ISTERS
i
EXAMPLE 9-1 Show Ihe states o f the 5-bit register in Figure 9-6(a) for lhe specifi ed data input and clock waveforms. Assume that the registe r is initially cleared (all Os). FIGURE 9 - 6
1'1"0
Opcn filc F09-06 to vcrify Data
operation.
input
-
FF2
FF'
Q,
Q.
-
D
I--
> C
I--
D
i>c
V
P.c
FF4
-
Q, D
-
Q,
-
D
P.C
Q,
[ M ..
Olltput
c
eLK eLK
Dom input
,
",,,
0
0
,,,
(. )
Q.
J
f-- - o
Q,
Q,
[}~I a
'---- 0
bits stored
after five
clock pu lses
Q,
Q, (b)
Solution
Related Problem -
The fi rs t data bit (I ) is entered into the register on the first clock pulsc and then shifted from left to right as the remaining bits are entered ,md shifted. The regisTer conta ins Q.;Q3Q2QtQO = 11010 after five clock pulses. See Figure 9-6(b). Show the states of the re
A tradilional logic block symbol for an 8-bit serial in/serial Qut shift register is shown ill Figure 9-7. 'I1le "SRG 8" designation indicales a shift register (SRG) with all 8-bit capacity. FIGURE 9-7
LogiC Iyml>ol for an 8-bit lerial inJ~rial out Ihift rcgillcr.
0::: =+~_c__S_RG__'_--,~ ;:
SERIA L INfPARALLEL OUT SHIFT REGISTERS
I
SECTION 9-2 REVIEW
_
4'1'1
1. Develop the logic diaglClm for the shift registe r in Figure 9-3, ulingJ-K f1ip-f1ofX to repl
2. How many dock pulses are required to enrer a byte of data sen'ally into an 8-bit shift registe r?
9-3
SERIAllN/PARAllEl OUT SHIFT REGISTERS
Data bits are ente red seria lly (ri p-ht- most bit first) into this type o f register in the same marmer a.~ discussed in Section 9- 2. The d iffere nce is the way in which the da ta bits a re ta ken out of the registe r; in the p;:\ralle l output register. the o utput o f each s tage is avai lahle . Once the dat.a are stored , ~ach bit a ppeal'S on its respective Olltput li ne, and all bits are available si multaneous ly. ralher Iha n on a bit-by- bit basis as with the serial output. After comple ti ng this sectio n. you sho uld be able to _ Explain how data bits a re ta ken out of a shift register in pamllei - Compare serial output 10 parallel output - Discuss the 74 HCI64 8-bil shift register - Develop and analyze timing diag ra ms for serial in/paralle l o ut registers
Figure 9- 8 shows a 4-bit seria l in/parallel out sh ift register and its logic block sy mbol.
Om;! inpur
-
D >C
~D
~D
~D
I>c
I>c
>C
IliI rJ input C'LK
SRG 4
D C
e LK Q (a)
Ib)
fiGURE 9 - 8
A serial in/pa rallel out shift rcgider.
I
EXAMPLE 9 - 2 S how the states of the 4-bit reg iste r (SRG 4) for the data input ~ nd clock wavefonns in Figure 9- 9(a). 'n le register initially contain!> all Is.
Solution Related Problem
The registe r contains 0 110 after fo ur clock pu lses. See Fig ure 9-9( h).
a
If the data input remains after the fOUl1h clock pu lse. what is the state "f the registe r after mree additional clock pulses?
500
•
SHIFT REGISTERS
- fiGURE 9 - 9
Oara in
eLK
(~)
--"------l
0
SRG 4
0
,
c
,, Q, 1
"'u Q, Q. Q,
Q,
Q, Q,
(b)
THE 74HC164 8-BIT SERIAllN/PARAllEl OllT SHIFT REGISTER The 74HC I64 is an example of an IC shift regisler having seriill in/paral lel oul opemlion. The logic diagram is shown IU Figurc 9- IO(a), and a Iypicallogic block symbol is shown in pari (b). NOtice that this device has two galed serial inputs, A and B. and a clear ( CLR ) input that is active-LOW. The pamJiel oulpulS are Qu through Q7'
( 9)
C/" C, K
'" (I) I'- y
{; (D
"
4>
"
"
N
"
"
" poe
po e
I> e
>e
I> c
I> c
>e
s
s
s
s
s
s
( 3)
(4 )
Q,
(5)
Q,
( (»
Q.
Q,
M Lo{! ic diagr.lI11 (I )
SRG !!
A
B
ctR
eLK
(2)
(9) (8)
C
(bJ Logic symhol fiGURE 9 - 10
The 74HC l 64 S-bit Jeri", infpa,.,-, Ud oo t snift regiltCt'.
(1 0 )
Q,
R
I>c s
(II' Q,
{ t 2J
Q,
(13)
Q-
PARALLEL IN/SERI AL OUT SH IFT REGISTERS
•
A sample timing d iagram for Ihe 7411C 164 is shown in Fi!lure 9- 11 . Notice that Ihe serial input data on input A are shifted into and throu!lh the register after input B goes I-UGH.
fiGURE 9 - 11
Sample timi .... g diagram (or a 7<1HCI6
I
SECTION 9 -3
REVIEW
1. The bit ~uern::e 1101 is U!rially entered (right-most bit first) into a 4-bit parallel out shift register that is initially dear. What are the Q outputs after two dock pulses? 2. How can a seria l in/paralle l out register be used as a register?
9-4
PARAllEllN/SERIAl OUT SHIFT REGISTERS
For a register wi th parallel data inputs. the bits are entered simultaneously into their respective stages 0 11 parallel lines ralher than on a bit-by-bit basis 0 11 one line as with serial data inputs. The serial output is the same as de~ ribed in Section 9- 2, once the data are complelely stored in the register.
~eria l
in/serial out
501
502
•
SHIFT REGISTERS
A rter completing this section, you should be able to - Ex plain how data bits arc entered into a shifl regisler in parallel - Compare serial input 10 paral lel inpu t - Discuss the 74 HC165 8-bit pamllel-load shift register - Develop and analY7.e timing diagrams for paralle l in/serial out regislers
Figure 9- 12 illustrates:l 4-bil parallel in/serial out shift reg ister and a typical logic symbol. Notice that there are fou r data-input li nes. Do. D" O 2, and O~ , and a SIJIFf/ LOAlJ input, which a llows fouT bits of data to load in parallel into the register. When SHirl / LOAD is LOW. gates G, through G4 are enabled, allowing each data bi t 10 be applied to Ihe D input of its respective flip-flop. When a dock pul se i ~ applied, the ni p-flops wilh D = I wi ll sel and those with D = 0 will reset, thereby storing all fOUf bi ts simultaneously.
For palClUel dOlta, multiple bits are trOlnsferred Olt one time.
0,
f)1l
\111FT/WID
D,
f),
-~>-t~~-----rt------rt-------, r'- ~ G~
G,
c,
G1
G,
V ~'---O--,
D
>c
Q"
Q,
>c
FH)
o
o
I>c
I>c
FB
FF2
FFI
el.K
(a) Logic diagram
Dam in
,
D, D,
D,
,
D,
I I I I
~I/IFTILOM)
OK
=tc
SRG4
~
&ri,,1
d,,, 00'
(bl Logic symbol
FIGURE 9 - 12
A 'I-bit parallel in/serial out $hjft r.:gilter. Open fil e F09-12 to verify oper.o tion.
When SHIrr/ WAD is HIGH. gates G, th rough G4 ilre disabled find gates G~ th rough G7 are enabled . allowing the data bits to ~ hift right from one stage tuthe next. The OR gates
PARAllEL IN/SERIAL OUT SHI FT REGISTERS
•
allow e ither the normal shifting operation or the paralle l data-entry operation, depend ing on which AND gates are enabled by the level on the SI-IIFT/ WAD iupUl. Notice that Pro has a sing le AND to disable the parallel input., D(T It doe..;; not req uire an AND/OR arrangemelll because mere is no serial data in.
I
EXAMPLE 9-3
Show the data-output waveform for a 4-bil register with the pardllel input data and the clock and SHln, LOAD waveforms given in Figure 9- 13ta). Refer to pigure 9- 12(a) for the logic diagram.
SllIfTIIUAn
Ct.K
CLK
c.)
LC -_ _---'
, ,, , 1
Cb)
, ,,,
SfIIFrfU )AD ~r+:--~--~--~r---r---
1
1
1
'_-,--;-,_+__
0 ~
r
L __ J _ __ _
"-
t.."'-...
oaL:!.
bot
FIGURE 9 - 13
Solution
RelaUuJ Problem
On clock pulse I, the parallel data (DoV, D2D3 = 10 10) are loaded into the register, making QJ a O. On clock pulse 2 Ihe I from Q2 is .~h i ft ed 0 1110 Q); on clock pul ~ 3 the ois shifted onto Q); o n clock pulse 4 the last dala bit ( I) is ~ hifted onto Q.,; and on clock pulse 5, all data bils have been shifted oul, and ouly Is remain in the register (a<;suming the D input remains a I). See I-l gure 9- 13(b). Show the data-output waveform fo r the clock anti SHIFT/ LOAD inputs shown in Figure 9- 13(a) if the parallel data are IJr:P ,D2D3 = 0 10 1.
THE 74HC165 8-BIT PARAllEL lOAD SHIFT REGISTER The 74 1-IC 165 is an example o fmll C shift register that has a parallel in/serial out operation (il can also be operdted as serial in/serial out). Figure 9- 14(a) shows Ihe intemal logic d iagram for rhis device, and ~rt (b) ~ hows a Iypical logic block symbol. A LOW all the SHU-I , LOAD input (SH/ LD) ellables all rhe NAND gates for paralle l loadi ng. When an input dala bil is a I, the nip-flop is asynchsonousJy sel by a lOW oul of the upper gate.
50)
504
•
SHIFT REG ISTERS
When 1In inpul data bit is a O. the f1ip-nop is asy nchronously reset by a LOW out of the lower gate. Additionally, data can he e ntered st!rially 011 the SER inpul. Al so, .he clock can be inhibited anytime with a l-IIGH on the eLK INN input. The serial data outputs or the re.giSler are Q7 and its complement Q7' Th is implememation is different from the synchrolJou s method of paralle l loadi ng previously discussed, demonslr.lling Ihal Ihere are usuall y severdJ ways to accom plish the same func tion.
.
,
I';\rulld input'
(12)
( II )
s
D.
D,
D,
f)n
s
s
s
D.
D, (J)
(1 4)
(13)
, (5)
(0)
s
s
s
D,
D.
("
S
191 Olli pur Q
Sf"R
{l0)
C
C
C
C
C
C
C
R
"H
DH
"H
DH
DH
DH
C (7)
D
0
H
~1put
Q
(2 )
CLK ~ eLK INII
la) Lot;ic diagram
sfllfjj .\"/:'H CLKINH eLK
(I)
,-'-=====-'-"-"-'==, (9)
(10)
SRG8
(IS)
-"oc~~ c ____________________~(" (2 )
Q,
(b) Logic sym bol FIGURE 9-14
The 74HC 165 8-bit pard liei load Ihift regilter.
Figllre 9- 15 is a lirninll diagram showinll an example of lhe operation ofa 74HC I65 shift regi&ler.
PARALLEL IN/PARAllEL OUT SHIFT REG ISTERS
eLK eLK /Nil
st.""/? 0 SIIILO
(LOW)
I-J
( ~ ~--~-----------------, 01 l tl , oJ ~---'----------------, oJ :0 , , 4 0 ~: ----------------, , Os
I tl
I
,
,o
I
I
Q,
ij,
1_lnhihil
"
- 1-.- ----- serial ,hlrl
•
J..Hl d FIGURE 9 - 15
S;3mplc timing di;3gr;3m for;3 ]4HC165 ihift register.
I
SECTION 9-4
REVIEW
1. Expl3in the function of the SHIFT/ LOAD input
2. Is the parallel load operation in a 74HC165 shift register synchronous or asynd"lronous? What doe this mean?
9-5
PARALLElIN/PARALLEl OUT SHIFT REGISTERS
Parallel entry of data was de.~ribed in Section 9-4. and parallel output of data has also been d iscussed previously. The parallel in/parallel OUI register employs bOlh methods. Immed iately fo llowing Ihe simultaneous entry of llil data bits.lhe bils llppear on the parallel outputs. After compleling th is section. yOU should be able 10 • DiSt:uss Ihe 74HCl95 4-bit pllralle l-access shift register . Develop aud analyze liming diagrams for parallel in/parallel out regislt:rs
•
505
506
•
SHIFT REGISTERS
Figure 9- 1() shows 11 parallel in/parallel out register. P:1r.[lIcI 001,[ Inpuh
c---------------~.~-C---------H OI
f) 1
f) ,
__, f) ,
D
D
D
D
pc
pc
>c
P.C
e LK
,Q, FIGURE 9 - 16
A parallel in/paralle l out regifter.
THE 74HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTER The 74HC I95 can be us(:d for parallel in/pamllc.J out operatio n. Becausc il also has aserial inp ut. it can be used for serial in/serial OUI and serial inlpamllcl oul opcmlions. It can be uscd for pamJlel in/serial out opcmtion by using QJ as Ihe OUlput A typical logic block symbol is shown in Figllre 9- 17. FIGURE 9 - 11
D"
D,
D,
The 74HC1,}S 4-bit pa", Jlelacces shift regilte!'".
D,
(7)
Serial { J inputs K SIfILI)
CLR
eLK
'"
SRG4
(3J
'"'I) ( 10)
c
Whell thc SHIFTIWAD input (SUI IJJ) is LOW. the data on fhe parallel inputs are enterc.:d sy nch ronou~ l y on Ihe positi ve Imnsition of the clock. When SHi Ll) i~I ·IIGH. ston..'
BIDIRECTIONAL SHIFT REGISTERS
_
507
e LK
CLH ~ J
----i:~--.l~.i--,L-------t_-t_-------
SfHW
~==~~======~~~~======
&,',' {
mput,
K
" [
--+____________
D2 _ _.;.._ _ _ _
D,
Q, P'.lf:l llci l lUIPU"
____~____________~I
LI+-___________
D: --t -----t--------------;::i=:;--t------------
I':I/"..!~I~ Ik l mpu l ~
_~
~
--i------t====~------------t=====t------------
Q, Q, Q,
,--- 1
, :---
- - - - Sen ,11 ,llIn
- -- - -_
('kar FIGURE 9 - 1 8
s.,mple timing diagram for a 74HCI95 shift register.
1. In Figure 9- 16, Do = 1, 0 1 = 0, O2 = 0, and OJ = I. After three dock pulses, what are the dab outpun? 2, For a 74HCT95, SH/ W = I,j = T, and K = 1. What is
9 -6
BIDIRECTIONAL SHIfT REGISTERS
A bidirectionaJ shift rcgisler is one in which Ihe clula can be shifll.:cl eilher left or righl. It can be implemcnted by using galing logic that enables Ihe transfer of a data bil from one singe to the nC:<.t stage to the righl or to the left. depending on the level of a control linc. Afler completing this section. you should be able to - Ex plain the opcratioll of a bidirectional shift register - Discuss the 74HCl94 4-bit bid irectional universal shift register - Develop and analyze timing d iagrams for bidirectional shift registers
1\ 4-bir bidirectional shift regisler is shown in Figure 9- 19. A HIGH on the RIGHT/ LEFf control inpul aJlowsdata bils inside Ihe rcgister to be shifted to the right, and a LOW enables dma bits inside the ret;isler to be shifled to Ihe left. An exa mination of Ihe ~aling logic w ill make the operation apparenl. When the RIGHT/ LEFT control input is HIGH , gates G, through GJ are enabled, and the stale of the Q output of each nip-fl op is
0 0 after one dock pulse?
508
•
SH[FT REG[ STERS
passed through [0 the D illput of the follOlrillg nip-nop. When a clock pu lse occurs, [hc data bits arc shifted olle pl ace to the right. When the RIGHT/ LEFT control input is LOW, gates G.~ th rough GM are cnabled, and the Q OUtput of each nip-flop is passed th rough to the U input of the precet/ing flip-flop. When a clock pulse occurs. the data bits arc then shifted one place 10 the lefl.
RIGHTIIJ.FT
If[)
S.:riaJ tlat~
~" ("
in
G,
j)e;;Q"
G6
,
J
G
he;;-
I>c
>c
'--
-
Q,
G,
G,
G
I\. '
h-;;-
h
(I.
D
~
c
c
-
CLK FIGURE 9 - 19
Four-bit bidirectional Ihift regilter. Open fil e F09- 19 to verify the operation.
I
EXAMPLE 9-4
Dctenni ne the state of\ he shift regis ter of Figure 9- 19 after each clock pulse for the given RIGHT/ LEFT cOlllrul input waveform in Figure 9- 20(a). Assume Ihm Qo = I, QI = I. Ql = O. and QJ = 1 and that the serial data-input line i~ LOW.
,... FIGURE 9 - 20
crigho
RIGHTI /£f"T
(al
eLK
(righO
(left)
,
,
,,,
,,, ,
, , ,,, ,, 10 :0 ,, :n ,, t-;-
,,,
On ll~~O_--}-~ O _fi~O'---j Q,
,,
Q,
Lj, ,
(b,
Solution Related Problem
Q,
,
,,
,,, , ,
,,,
l1...!LJII u
(Idl)
0
10
0
II
0
0
II
,, ,, r.-l
"
0
II
0
"
0
Sec Figure 9- 20(b). Invert the RIGHT/ LEFT waveform, and determine the stale of [he shift reBister in Figure 9-19 after each clock pulse.
BIDIRECTIONAL SHIFT REGISTERS
•
THE 74HC194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER The 74 HCI94 is an example of a universal bidinx:tional shift register in integrated circuit form. A unh'crsaJ shift regisfer has both serial and parallel input am1 OOlput capability. A logic block symbol is shown in Figu re 9-2 1, and a sample timing diagram is showll in Figure 9-22.
0"
f) ,
0,
J),
(6 )
( 1)
CLR
FIGURE 9 _ 21
The 74HC194 4-bit bidirectional universa l lhift register.
SRG4
(9)
5" 5,
(10) (2)
SRSER
(7)
SI.SER
110
CI. K
C (12)
Q"
,,",1,( { SRSER dala inpub
SI. SER 00
P.w.J lld
DI
data
inpub [
D2
Q-
Q,
~--+---i--,rTll -r-TT---H--t--;=~t-;==t=~1LJI _ -+_+_ -j__I-_ +_ -j_ _ I-_ +I--j--'
511 , , I
,:
,
,
--:'c=:t'=o-'--<--~--'--<--~,~,-+_--+--'--~-+i_---------_t--
-JJn-,_-+---+,--,,_- +-- -+:.;l-~--;--;--+--+~----------c--
D)
QQ
Q,
!
I
:
:
,
,
,
I
I
I
I
'
: :
, I
I
, I
I
!1 :
~~~r--i:--t---il+:-+---+--l---,i---,I
Q, -
L
I : nJ'l' " . ; f---+----+:[C--+-+----i----1I l~ ' ======~I,
,
•
Q3 -
I
: I
,
- 1'--t-:_~= ::~_j ,I I :' Shit! ri~ht •: Clc
FIGURE 9 - 22
Sample timing diagr
.t ::::'
:------ Shifllctl -~'.'---- I"" i l'il ----- . : C lear
50'i
5 10
_
SHIFT REG ISTERS
Parallcl looding, which is .~y nchronous with a positive transition or lhe clock, is accomplished by applying the four bils of data to the parallel input... and a HIGH to the Su and SI inputs. Shifl right is accomplished synchrotlously with the positive edge of the clock when So is HIG H and SI is LOW. Serial data in Ihis mode arc e nteTl!d at the shift -right serial input (SR SER) . When So is LOW and Sl is HIGH, data bits shin left synchro nously with the clock, and new data are entef(..'
I
SECTION 9-6 REVIEW
9- 7
1. Assume that the 4-bit bidirectional shift register in Figure 9-1 9 has the fo llowing contents: 0 0 = I. O l = 1,01 = 0, and OJ = O. There is a 1 on the serial datainput line. rf RIGHT/ LEFT is HIGH for th ree dock pulses and lOW for two more dock pulses, what arc the contents after the fifth dock pulse?
SHIFT REGISTER COUNTERS A shift register counter is ba'iically a shift register with the serial output connected back to the serial input to produce special sequences. These devices arc often classified as counters because they exhibit a spccifi(!d sequence of stales. Two of the roost common types of shift register counters. the Johnson counler and the ling counter, afC in(rodtLe(..xI in this section. After completing Ihi s section , you should be able tn - Discuss how a shift register counter differs from a basic shift register - Explain the operation of a Johnson counter - Spt!cify a Johnson s(..'
The Johnson Counter I.n a Johnson counter the complement of the output of the last nip-flop is connected back 10 the D input of the fi rs t flip -flop (it can be implemented with other tyJX."S of nip-flops as wel l). This fe(..'(\back arrangemenl produces a characteristic St.'
SHIfT REG ISTER COUNTERS
•
5 11
TABU 9 - 1
Four-bitJohmon !«juence.
o
o
o o
o
o
o
o o o
o
2 3 4
o o o
5
6 7
o
o
o TABLE 9-2
Five--bitJohmon lequence.
0
0
0
0
0
n
0
0
0
0
0
0
0
0
0
2 3
0
4 5 6
U
7
0
0
8
0
0
0
9
0
0
0
FFO
"C
22.. D
>c
FIGURE 9 - 23
m
FFI
J?:.... f)
0
rc
A '3
Four-bit .. nd 5-bitJohnlon counteo.
~D
rc Q.
rI K (a) l'our-bit Johnson counter
D
>c
FF2
FF I
FRJ
~D
>c
ClK (b) Five-bit JohnSOn l"OO nter
~D
I>c
m J£ D
I>c
~D
""
I>c
,
512
•
SHIFT REGISTERS
Diagrams of Ihe liming operations of the 4-bit and 5-bit counters
9-24 and 9-25, rt..'Spt..'Clivcly. FIGURE 9 - 24
Timing sequence for" 4-bit JohnlOn counter.
Q' ~~t± -----.J__-' Q, _ _ _ _
L
~ ------------' FIGURE 9 - 25
,
CLK
Timing sequence for" S-bitJohmon counter.
-=j-=- =-=~=~;=t=;
Q' --'J_-_-tf--_ tt-t
Q, -
-jT
-i
Q, - - - - - - - - - - - ' Q, - - - - - - - - - - - - - - - '
- - - ' I - - - - - - -- ---1L
Q., _ _ _ _ _
The Ring Counter The ring counter uti lizes one nip-flop for each state in its sequence. It has the advantage thil t decodillg gates arc noT requiretl. In toc case of a IO-bit ring counter. there is a unique OUTpuT for each decimal digit. A logic diagrnm for a IO-bit ring COllnter is shown in Figure 9- 26. The sequence for Ihis ring counter is given in Table 9- 3. Init ially,
PRE
Q. D
C
D
I>c
<,
Q.
D
c
"
D
C
ru
D
P.c
Q
r
(,'.
D
D
Q
D
Q
D
Q.
D
c
c
I>c
c
c
r
r
1
1
Y
eLK
FIGURE 9 26
A 10-bit ring countel'". Open file F09-26 to verify operotion.
SHIFT REGISTER CO UNTERS
•
TABLE 9 - 3
Ten-bit ring counter ~uence . 0
0
11 2
0
0
3
0
0
0
11
11
0
0
0
0
0
11
0
11
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
4
11
0
0
0
5
0
0
Ii
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
Ii
0
0
0
0
0
0
0
0
7
0
0
0
0
0
0
0
1
8
0
0
0
0
0
0
0
0
9
0
0
0
0
0
0
0
0
0 0
represenlS a three, and so on. You shOllld verify for yourself Ihatthe I is a lways retained in the counter and simply shifted "around the ring," advancing one stage for each clock pulse. Modifk-'d sequences can be achieved by having morc than a single I in the coun ter, as illustrated in Example 9- 5.
i
EXAMPLE 9 5 If a to-bit ring counter similar to Figure 9-26 ha... the initial state IOIDOOO.lOO. determine the waveform for each of the Q outpu ts.
Solution
See Figure 9-27.
FIGURE 9 - 21
Q, - - - - - - - '
~ ------------'
Q, - ----------------------'
,
S-L-J---iL
Q. _ _ _ _ _ _ _
Related Pr-oblem
If a I O-bit ring counter has an initial state 01 0 I 00 I J 11, delennine the waveform for each Q o utput.
S13
514
•
SHIFT REGISTERS
II
1. How many sti'ltcs are there in an 8-bitJohnson counter Jequcnce?
_ _ _ _2_, Write the sequence of sbtes for it 3-bitJohmon counter starting with ooo.~
9-8
SHIFT REGISTER APPLICATIONS Shift registers are found in many types of applications, a few of which arc prClicntcd in this st.."Ction. Aftcrcomplcling this sect ion, you should be able 10 • Usc a .~hi ft register 10 generate a lime delay . Implement a specified ring counter sequence ll5ing a 741·IC 195 shirt register . Discuss how shift registers are used for serial-to-parallel conversion of data • Define UART • Explain the operation of a keybo
Time Delay
The general-purpc»e regillcrs
the Pentium
accumulator (fAX) II
used mainly {Of temporary Itor.. ge of ooti'! ilnd imtruction oper.1nds. The bale regiJter (fBX) il used to ' dore iI value tempora rily. The count regiJter (Ea) is mainly used to dete rmine the numbef" of repetitions in ceruin loop, string. ~ifl or roUte operiltiom. The data regiJter (EOX), is normally moo for the temporary storage ofdilb.
I
I
The serial in/serial out shift register can be u ~t:t.llo provide a ti me delay from input to output that is a function of both the number of stages (II) in the register and the clock frequency. When a datu pulse is applic.:d to the serial inplll as shown in Figure 9- 28 (A and 8 connected together), it enters the fi rst stage on the triggering edge of the dock pulse. It is then shifted from stage to stage on each successive clock pulse unlil it
"'";" ~LK -f.I
'KG'
C
IMH~~L
~ "'''O"'
-,fJ"--
_______________
e LK
,
o..la in ---r-tL----- - - - - - - - - - -- -l,, , --0..180ul
--t):=================~~~================::j~ :'
FIGURE 9-21
The Ihift regilter ill.ao time-deby device.
t"
I-lp'
.:
SHIFT REGISTER APPLICATIONS
•
Determine the amount of time delay between the serial input and each Dutput in Figure Y- 29. Show a liming diagralTl lo illustrate. FIGURE 9-29
Dal~ in
- -,.'A'-j---SSRRGG:,i;;.---l 8
Q" Q, (h Q,
Q~ Q~
Q" Q7
• [ M a shi fts from Qo row~rd Q7.
Solution
The clock period is 2 p...<;. Thus, the lime delay can be increased or dt..'Creascd in 2 p's incremenls fro m a minimum of 2 p.S 10 a max imu m of J 6 p.s. as illuslraled in Figure 9- 30.
CLK
Om.," Q,
Dma OUlpuh
J-i"==_______________ -+----111
Q,
, L-_ _ ______________________ 11
Q,
:,
Q,
I
r-l , "-------------------------r-: ,
-~-_+--1ic_-_+i--1'
Q,
Q, Q, Q,
L I .- - - - - - - - - - - - -
I'
:I
: :I
I
I
,
.----,
!
IL_______
I I
I I
I I
I I
r---l
!
I
I
!
I
!
r-l'==:----------:I \ I' - - - - - - - - I
!
I
I
FIGURE 9 - 30
Tim ing diagram .hewing time del¥
Related Problem
for the regi.ter in Figure 9- 29.
Determine the dock frequency requi red to obtai n a time delay of 24 p.S to the Q7 output in j.."'igure 9-29.
L.
51 5
516
•
SHIFT REGISTERS
A RING COUNTER USING THE 74HC195 SHIFT REGISTER If thl:: output is connected back 10 the serial input, a shi ft register can be used as a ring coul1ler. Figure 9- 3 1 jllu.~trdles this
HIGH
74HC I95 connected '"" ,ins counter. (2 ) J
SRG4
(3) 11
SHIU)
(9)
0)
CUI eLK 110)
C
m.) Q"
Q,
Q>
Q>
Initially. a bit pattern of I000 (or any other panern) can be synchronouslt.£.reset into the COllnter by applying Ihe bit pattern 10 the parallel data inputs, l:Jking the SfJj W input LOW,
SI/lW _ _--.J
il-fl-fLll
,
Q"
Q,
I
,
"
Q,
r
"
~~---;"--;'--In
_---'11,
-------'~
"
,
II!---:----o,
i
~r----t,
-----'IIL____I L
Q, _ _ _ _ FIGURE 9 - 32
Timing diagram .howing two complete cycles of the ring counter in Figure 9-31 when it il initia lly preset to 1000.
Serial-to-Parallel Data Converter Serial data transmission from one digital system to another is commonly used 10 reduce the number of wi res inlhe [ rdll.~lllission line. For example, eight bils can be.scm serially over one wire, but it take.~ e ight wires to send the samc dlila in paralic/. A com puler or microprocessor-based system commonly requ ires incoming data to be in p:wnlJcJ formal, thus the requirement for serial-to-parallcJ conversion. II. simplified serial-to-parallel data (.'onverter. in whkh two types of shifl registers are used, is shown in Figure 9~33.
SHIFT REGISTER APPLICATIONS
SRG 8
/J
CLK GEN
Conlrol ni p-Ilop
H1GH -
Q
J
"""-
EN
Data-input register
e LK
C
C,
C
r-
Q,
Q.
Q, Q, Q, Q, Q,
K
-
CI.R
CLK
SRG8
I~
CTR DIV8
~
-
Dma-<.MJlptJ l
((:giSI<:r
C
C ~
c Q One -shot
-'-
IIIIIIII
I~) I),
,
1 rc' CLK
FIGURE 9 - 33
Simplified logic diauam of a serial-to-poril lie l COflVertef".
To illustrale Ihe opcralion or this scrial -IO-parallel convener. the serial data format shown in Figure 9--34 is used. It consists of eleven bils. The firsl bil (stan: bit) is always o and always begins with a HIGH-to-LOW lransilioll. The nexi eighl bi ts (D7 through Do' are the data bits (one of the bits can be parity). and the last two bits (StOP bits ) are always I s. When no dllta are be ing sent. there is II continuou s I on the serial data line.
FIGURE 9 - 34
1lle HIGH-la-LOW transition of the start bit sets the control nip-nop, which enables the clock generator. After a fi xed delay time, the clock generator begins producing a pulse wa\'eform. which is applictlto the data-input register and to the divide-by-8 counter. The crock has a rrcler. This Sll mc transition also triggcrs the oneshot. which produces a short-durat ion pulse to clear the countcr and reset the control flip-fl op and thus disable the clock generator. The system is now ready for the next group of cleven bits. and it waits for the next HIGH-to-LOW transition at thc beginn ing of the start bit.
f) ,
.
I), " ,
I)~ I).. 1)1
1,;w"lIdll;II'H'Ul
,
•
517
518
•
SHIFT REG ISTERS
Serial
SlOp
d,,(.a in
Conrrol
1li~l1op Q
---.l)---~-t---j-----j--j--t--t-:f-L____
CLK _ _ _- '
Q,
r
r
I
I
r
===
r
~t:= {)
-----~ , i--L-j--t'-i' , --Il i W Q , r II
Q,
O;' la
Inpul rC~ls r t" r
Q,
bil~
:
' l, :, ----~~~~il~~I~ {) === _ _I
Q,
-----hi' ---L-J~____
Q, _ _ _ _ _ _ _ _ _ _ _ _ _ _~~,-_+ i -(~)-
,
,
Q'_===========================~~I1 ___I~,~{)~===
Q, -
Tc· eLK
CUI
--===============~~;=== U
'"
{)
0,
{)
0,
DmJ uurpul
D,
",,~j~ler
0,
D, ________________________
~~ {) '-
Load dnl;., out
___
r~iSI~r
FIGURE 9 35
Timing diagram ilJultrating the operation of the lenal-to-pa.rallel cbta. convertff in Figure
9~33.
By reversing the process j ust stated. parnllel-to-scrial data conversion can be accomplished. However. since Ihe selial dala format mllst be produced. additional requi rements Blust be taken into considerdtion.
Universal Asynchronous Receiver Transmitter (UART) As mentioned. computers and microprocessor-based systems often send and receive data in a parallel format. Frequently, these systems mu~t communicate with extema! devices thai send and/or reccive serial data. An illlcrtacing device used to an:omplish these conversions is the UART (Universal Asynchronous Receiver Tnm~m iue r). Figure 9-36 ill ustrates the UART in a general microprocessor-bastxl system application.
SH IFT REGISTER APPLICATIONS
FIGURE 9 - ]6
/ Mklll-
•
UART inrerfOKe.
.• ,
P""=
Serilll tlal:l
E~lcnlal
Scrill l dl,l:l
In
sy,te m
•
device
(prinle~. u:>m muni<:al iom syMcm. elc .)
A UA RT includes a scrial-to-parallcl dala convener such as we havc discussed and a pal1lllcl-lo-sen al convencr. as shown in Figurc 9-37 , Thc dala bus is basically a sct of pal'alle l conduClOrs along which dala move between the UART and the m i c roproces.~or sys t e m . Buffers interface Ihe datn registers wilh the data bus, .. FIGURE 9 - 31
&.jc UART block diagram.
Buffcn.
T r.l lNniller ..l''' 3 rcgisl~r
('1...1( -
Tr:m~mincr ~hift rcgiSl~r
I
Serial Ualn .ltll
ReceivCl' wIre I"Cg ister
CI K -J
Receiver shifl ~i"ler
I Serial oJala in
The UART receivc100 dala in sclial formal, convcns the data to pamllel format, and places thcm on thc data bus. Thc UART :.tlso acccpts parallel data from thc data bus, cUIlVcrls the data to serial fo rmal, and tmnsmits them 10 an external device.
Keyboard Encoder The keyboard encooer is a !lood example of the applkatiOil of a shift register used as a ri ng counter in cunjunction wilh olher dcvices. Recallihal a simplificd compUicr keybuard enwder without dala stor'
•
519
520
•
SHIFT REGISTERS
Powcr On LOAD SHILD +Vcc Ringcoumer
Do DI TD~ IJJ
IJ.
J
CLK (5k H ~.)
'-----
i
K
T
c
L;
SRG4 74HC I95
K
r=
Q , Q, QT Q,
T
J)~
0J!?il
J
c
SRG4 74HC I95 +V
Q" Q, Q" Q
,.
,. I"I" I"I" I,.I,. !,.,Z" ",. !"!" !"!" I"I" I"I" I"I,. I",'"" "!" I" I" It I" " It' ~ It' I" I,., , /'
z"
'
!~
t'
z" ,. I" I,. I" I" I" z'
t-<
> Clock inhibIt .n.. I
2
,
3 4 5 6 7 ROWeocodcr 74HC I47 I 2 4
I
2
3 4 5 6 7 COLUM N encode r 7411CI47 I 2 4
?! I I ~
C
fl!-
Lr Q
~
Q
e Dt, DI
f)2 f),
f)4
,
I
Sw itch closur" I
f)~
Key cOOc register 74 HC174 C
Q" Q,
,
One-shots
Q, Q, , '. 0 RO"'.
Q'I Q'I ,
FIGURE 9 - 38
Simplified keyix>ard encoding circvit,
al a 5 kH z !"dte. The o(LOW) is scquentially applied to each ROW line. while al l other ROW lines arc I-UGH. All the ROW lines are connected to the ROW encoder inputs. so the 3-bit output orthe ROW encoder at any lime is the binary representlllion of the ROW line that is LOW. When there is a keyclosufC. one COLUMN line is connected 10 one ROW line. When fhe ROW line is taken LOW by (he ring counter, that particul .. rCOLUMN line is also pul led LOW. The COLUMN encoder produces a bin,try output corfCsponding to the COLUMN in which the key is closed. The 3-bi! ROW code plus the 3-bil COLUMN code uniquely identifies the key that is closed. This 6-bit code is appl ied to the inputs orthe key code regislCr. When a key is closed. the two one-sholS produce a delayed dock pulse to paral/el-Ioad the
lOGIC SYMBOLS WITH DEPEND EN CY NOTATI ON
•
521
6-bit cOtle into the key code It!gister. This delay allows the contact bounce to die out . Also. the fi r..;t une-shot output inhibits the ring counter to prevent iI from scanning while the data are r.ci ng loaded into the key code register. The 6-bit code in the key code register is now applied 10 a ROM (read-on ly memory) to be convelted to an appropriate alphanumeric cooe that ide ntifies the keybo;mJ character. RO Ms are studied in C hapter 10.
I
SECTION 9-8
1. In the keyboa rd e ncoder, how many times per M!cond does the ring counte r K<) n the keyboa rd?
REVIEW
2. What is the 6- bit ROW/COLUMN code (key code) for the top row and the leftmost column in the keyboard e ncoder?
3. What iJ the
pu rpo~
of t he diodes in the keyboard encoder? What is the purpose of
the resistors?
9-9
lOGIC SYMBOLS WITH DEPENDENCY NOTATION
Two examples of ANSJlIEEE Standard 9 1- 1984 symools with dependency notation for shift registers are presented. Two specific Ie shift registers are u ~ as examples. Aft er completing this section. you shou ld be able to • Understilild and interpret the logic symbols with dependency nOla tion for the 74 HC 164 and the 74HC 194 shift registers
The logic symbol for a 74HC I64 8-bit parallel output .serial shift register is shown in Figure 9- 39. The oommon control inputs are shown on the notched block. T he clear (CLR ) input is indicated by an R (for RESET) inside the block. Since [here is no dcp:!ndem.), prefi x to link R with the clock (C I), the clear fu nction is asynchro nous. The right arrow symbol af· ter C I indicates data n ow from Qu to Q7. 1nc A and B inputs are ANDcd , as indil:ated by the embedded AN D symbol. to provide the synchronous dma input. ID, 10 Ihe fi ~t slilge (Qo). Note the dependency of D on C, as indicated by the I suffi x on C and the I prefi x on D. CUI ~ R
eLK
'" , I)
Ii
(2) ~
FIGURIE
SRG 8
' - 39
logic .ymbol for the 74HCl 64. CII -
'r
I
&
(3)
ID
Q, (4 ) (5 ) (6 )
( 10)
(I t> (l 2) ( 13)
Q,
Q, Q, Q,
Q,
Q. Q,
Figure 9-40 is the 101lic symlxll for the 74 HC I94 4-bit bid ireclional un iversaJ shill regiSler. Sianing at t he top left side of the eontrol hlock, nolC that the CLR input is active-LOW and is asynchronous (no prefi x link with C). Inputs So and SI are mode inputs Ihat deler-
522
•
5HIFT REGISTERS
mine Ihe shift-right. shift-Iefl, and l'amlle1lulUl nuxlcs of operation. a!O indicaled by the ~ dependency designation following the M. ll1d reprcrenls the binary states of 0, I. 2. and 3 on Ihe SII and SI inputs. When one of these d igils is used as a prefix for anolher input, a dependency is establi):hcd. The 1-+f2f- symbol on the clod.. inpu t indicates the following: 1-+ indicates thai a right shirt (QII toward Q;o) occurs when Ihe mode inputs arc in the binary 2 Siaic (So:: 0, SI :: I ). TIle shift-right serial input (SR SER) is both mode-dependenl and clock-dependent, as indicaled by 1, 40. The pardllei input.~ (01Jo D !, O~, and 3 ) arc aU mode-dependent (prefix 3 indicates parallel load mode) and cJock-depcndenl. as indicaled by 3, 40 . The shift-left serial input tSL SER) is both mode-dependent and clock-dependent. a~ indicated by 2, 4D. The four modes for Ihe 74HC I94 Me sutluTIarized as follows:
°
Do nOlhing : Shift righl: Shift left: Pamllcl load:
So :: 0_ S!
(mode 0) I ,a~ in
So = I, S! = 0
(mode
Su = 0, S! ::
tlnCKle 2, as in 2, 40)
So =
(mode 3, as in 3. 40)
I, S! :: I
FIGURE 9 - 40
logic l}'llbol for ti'Ml 74HC194.
= 0
,I) OR
,.
s, eLK
,OJ ( ]O)
( Il )
SRG4
R
0 1
}
C4
121
,3J
",
,4,
D.
'51
D,
D,
'0' (7)
,\L SLII
I
SECTION 9 - 9 REVIEW
M~
L P.1_ n. _
'I SH '>1:11
1,4D)
t. ....O
I U S) Q"
3.40 3. 4J) 3.4D
3.40
( 14) (13 )
(I:?)
2.4D
1. In figure 9-40, are there any inputs that are dependent on the mode inputs being in the 0 state? 2 . Ii the paraUe llO
9 - 10
TROUBlE5HOOTlNG A Iraditionalmethod o f troubleshooting sequential logic and other more complex systems uses a procedu re of--exercising"lhc circuilunder test wilh a known input wavefOlm (.~t i mulusl antl lhcn observing Ihe output for the conl!ct bit pattern. After completing this section, you should be able to • Explain the procedure of "exercisin!( as a Iroubleshool ing tcchniq ue _ Discuss exercising of a serial-to-pamllcl converter
Q, Q.
TROUBLESHOOTING
The serial-IQ-p.lmllel d1l1 a converter in Figure 9-33 is used W i ll u ~trate Ihe "cxercising" procedure. The main objective in exercising the cireuil is to force all cle ments (l1ip-flops and gates) into all of the ir states to be certain that nothing is stuck in a gh "en state as a TCsult of a fau ll. TIle in put te ~t pattern, in this CUSC, must be designed to force each nip-flop in the registers into both states, to clock the counter th rough all o f its eight states. and to take the control flip-fl op, the clock generator. the one-shot, and the AND gate through (hei r paces. The inplll test pattern that accomplishes this objective for the serial-to-pardllel data conveneris ba'\Cd on the serial data format in Figure 9- 34. It consists of the patte m 10 1010 10 in one serial group of data bits followed by 010 10 10 1 in the next group. 3.<; shown in Figure 9--4 1. These patterns are genemlcd on a repetitive basi" by a special test-pattern genemtor. The basic tcst setup i:-, shown in Figure 9-42. fiGURE 9 - 41
LJ :'=i:1:n:1:u:I : 0 : I : n : ~§l1ii : n : I :n:I :n:I : 0 : 1:§l§l 1
1:7; 1
1
1
1
1
1
1
1
1
.ii3 IV: Iii3 1
1
1
1
1
1
1
1
I
~mpre
t el t
patt~rn.
' ::;:; IV'i .
Circuit under Test Scnal T~-p
generalO£ HIGH
,
Q
.n.n. EN
'--c
SRG8
0
e LK GEN
Da[;I-inptJl resisler
e lK
C r-~~~
Q, Q, Q2 Q,
K
'"
Q, Q,
CU< CUI
WAD r-'----'--~S~RG~'---'-'----'--,
erR DI V 8
TC
c c Q
FIGURE 9 - 42
Basic t.,.t ..,tup for the
u~riaJ-to-p"'rand
data converter of Figure 9-33.
After both patterns have been run through the c ircuit under tes!. alllhc flip- Ilops in thc data-input register and in Ihe d3t.a-OUlplil TC£ister have resided in both SET and RESET simes. thc COlllller has gone through itll !';cqucnce (once ror each bit pattern), and allthc other devices have oc'Cn exercised.
Dara-uulpul register
•
SlJ
524
•
SH IFT REGISTERS
To check for proper operation. each of the parallel data o utputs is observed for ,m alternating patte rn of Is and Os as the input test patterns arc repetitively shiftetJ into the datainput register and then loaded into the data-out put register. The proper liming d iagnlll1 is shown in Figure 9- 43. T he outputs can Ix! absented in pairs wilh a dual-Irace osci lloscope, or all e ight outputs can be obSCnted simultaneously wilh a logic amllyzer configured fo r timing analysis. FIGURE 9-4]
Proper outpub for tht! circuit un~r teit in Figure 9--42. The input te~t pattern ;l lhown.
Inpu t I.C$I paUern
L-
,-n L-n
"'mlllcl WI" uutflUt
o,J D., l DsJ D6l v, J
,-
-
L-n
,-n L-n
,-n
If one or more outputS of the data-output register are in(;QlTect, then you must back up the outputs ofl he data-input register. If these outputs are correct, then the problem is associated with Ihe data-output register. Check the inputs to the data-output register directly on the pins or the IC for an open input linc. Check that power and ground arc correct (look for Ihe absence of noise on the ground line). Verit)' that the load line is a solid LOW and Ihat there are clock pulses on the clock input of the COITCCt ampl itude. Make sure that the connection to the logic analy ....cr did not shortlwo output lines together. If a ll of these checks palo!> i n.~ pcct ion, then it is likely that the out put register is de fective. If the data-input register outputs arc also incorrect, the fault could be associated with the input reg ister itself or with any oflhc olher logic, and audil ional invcstigmiun is neces..'ii.ll)' to isolate Ihe problem. 10
ANDS
When measuring d igital signals with an oscilloscope, you should a lways use dccoupling. rathe r than ac coupling. The reaiOn that ac coupling il no t best fo r vlcwing d igital lignals is that the oV level of the signal will appear at the average level of the signal. not at true gro und or 0 V level. It il much ealier to find a ~fJOilting" ground o r incorrect logic level with de coupling. If you suspect an open ground in a digital circuit, increase the sensitivity of the scope to the maximum po!olible. A good ground will never appear to have noise unde r thil conditio n, but an o pen w.1i likely lhow iOme noise, v..f1ich appears as a random fluctuatio n in the 0 V level.
ON
i nCTlON REVIEW
9 - 10
1. What il the pur pose of providing a telt in put to a seque ntia l logic circuit?
2. Generally, when an o utput wavefo rm is found to be incorrect, what is the next step to be take n?
Troubleshooting proble ms that arc keyetJ to the C D-ROM arc available in the Mul tisim Troubleshooting Practice set:tion of the end-of-chlJplCr problems.
DIG ITAL SYSTEM APPLICATION
Securily code 'Oit;c r
IJJITlW I
; 0[I]~~ IJJ CD W I
tResel t-
lighll>IId
sen.'«)I"/al orrn interfac....
1111
1- 0
ISO"~ II
'lb:lrll1~-d
Clnel: B
C-
5Z5
AnI/Oil'
Clocl: A
I
-
•
MCioory logic
lI-Am" DiSOlml
~
FIGURE 9 - 44 In this system appli~tion, a relatively simple ~ Basic block diagr.-.m of the security I~tem. IYItcm is developed to control tho! 'leCUrity of a room ~ building. The s~tem un be programmed with a 4--<1igit sewrity code by entering the four digits, one at a time, from Serority Code logic a keypad. in the diJann rT'KXIe. Once the Thc security code Jogic controls the ~urity code has been entered and stored, arming. d i",rming. progl'iJmming. and the system is switched to the arm mode. To .,ntlY. The b.l.sic logic diagram is shown in diloarm the i)'stem. you mUlt enter the Figur., 9-45. Wo.,n the syrtem i~ firlt conect 4-digit code on the keypad. armed by placing the Arm/Disarm switch in the Arm position. sh ift regiJter C contains 0001 0000 10 that there is a lOW A Nlsic block diagram is sho",," in Figure on ArmOuI which activi!t.,. the ~ystem 9-44. The system logic consisu of the ~mors, the alarm circuits, and the ARMED security code logic and the memory logiC. indicator. AlIO, a reset pulJe is generated In this chapter. thc focus is on the code by OSE (or the memory ",ddr.,.1 countef'. entry lOgiC. The memO<)' logic will be developed in C~pter 10, and the two Entry To deactivate the ')"tcm 10 that logic .ectiom will be combined to (Of"m you can enter thc s.ecured area, you mu,t the complete system logic. enter the correct: 4-digit code that TIlt! scevre Arm/Di",rm switch pl~ matches the code stored in the memory. the security IYItem in either amI mode or The first digit of th., secu rity code ;s en-
,
diJarol mode. Programming is accomplidlCd by first putting the system into the diJarm
mode
"'-d.
tered from tile I<.cyp.old. The decima l- toBCD .,ncoder producel the BCD code rcpresenting the digit that wal pte1Sed on the kCYJ)"d. One-shot A (OSA) is triggered through gate G 1 producing a pulit! that docks to.,
the comparatOf" and putting shift regider C into the Sltift (SH) mode. The trailing edge of the GSA output pu lse triggers OSB which. in tum, triggen OSC on the trailing edge of its output pu lse. The output of OSC prO\oides Clock 8 to the memory address wunter and docks Ihift register C to shift the 000 10000 to the right so that the regi;ter now conbins 00001 000. Since there iSltiJi a 0 (lOW) on the wriaJ outpu t Am;Out, the system remains armed. \.\Ih.,n the 'IC'COnd coned code digit i, entered on the keypad, the contents of shift rcgistcrC are shifted to 00000100, and the syrtt!ITI remains armed. When the third axle digit is entered on the keypad, tflt! contents of shift rcg~tcr C are shifted to 00000010. \l.rht,n the fourth and last code digit ~ enteroo, the contents of shift register
C arc mifted to 00000001. Now, the 1 (HIGH) on the serial output AtmOut diloilrms tnc system and pc:rmits entry. /{ an incorrect code digit ~ entered at any time, the comparatcr output goc'I lOW. prodUCing a lOW on the SH!iJ5 and trigg.,red OSF to send a feset pulse to the memory addrcn counter. Shift regilter C is now in the Parallel Wad mode. OSC then docks the register and loads the prewired code 00010000 into the register. At this point, you must sbrt OYer and rcenter the entire fou r code digib.
526
•
SHIfT RE G ISTERS
,, 1-"'1111
~)puU
4 S
Occim:.l-to-
,
c"""""
,,
}
BCD
7
BCD~'~
Iume
9
I
Gt
1C
U
C 1C
1C
Q f-
Q
e,
> OSA
Shiftl cgistcr A
Q
I
>
W- U OSD
Comparator
USC
'----
j (10
(fo
memory)
}A
Gil
ao:",,:~~ ~"()I lntcrl
L-
I>c
A= lJ
Shift register B
f-
1C
Q
II
OSO
:-
\ ",011>,,,,,,,,
1C
~"II",I
L-c
Q
I>
1C
Q
}s
W
OSF
OSE
V G4
,
-fin
OJ
Rnt'
(Tn OOdre~
•
Ct>'Ul1cr )
SHiLD
HIGH( l)
LOW 101
II
0OO 10 UOO
,.,
Serml
C
Shift n:llister C
'\1'",0,,/
Tl,I so: n>oor and ala...l and lImv,.'ll lipll
interface
FIGURE '-45 Basic: logic: diagram of the ~rlty code logic.
Provownming To program a 4. digit code into the S)"tem, the Arm/[),$arm switdl is placed in the dOOfm pCllition. This biggen O<>C-1-hot OSD which ~nch a reet pu lle through GJ to the memory addrcJJ counter and reset! it to 00, the fint ad-dra" in the mcffiOf'y. The Store """;I.ch is placed in the Slore po
the A = B output of the comparat or viii gate G4 and enable the output of 0S8 vi.l G2 to prcMdc a dock to the memory during the programming of a code into themcmory. No:t, the fint digit of the desired ICO.Jnty code ;. ef1tered from the ""--,.pad. OSA is triggered through gate G' a. a result
of the key d osure and, in turn. triggen OSB ..Alich producf$ dock A to store the code in the memory. 058 triggen OSC producing dock B for the memory addfell counter and iKlvandng it to the second addrell (01). The second digit of the code is entered from the keypad, and the wquence dew:ribcd fOf the fint digit is
KEY TERMS
repea ted. After the fourth and last code digit is Cfltered, the memory oontains tht! 4-digit security code. If an iOCOfrcct d igit il 3CCident,,11y entered, you "JUlt finish entCfing four digiti or rC4)(:ti-ate the STORE twitch to (.'m u (e that the memory counter contains the fim address "gain. Once the programming is done, t he 'ystem is twitched to ormed mode.
•
• Activity 4
System Assignment
527
Describe the purpo\e of the
comparator. • Activity 1 Dc1cribe the purpole of Shift regilter A. • Activity 2 Descrioc the pUfpo!e of Shift regiltcr B. • Activity 3 DC\Cribe the purpose of Shift register C.
• Optional Ac.tivity Using 74XX logic les ilond the other componcnb, implement the M:Curity code logic in Figu re 'J-45. Miloke iloll)' chilng~ necCiSilory to accommcxbtc the dcvic.CI being used. Debug ilond telt the logic ilond dClCribe a ny design fliloWS (if any) th-.t you find.
T he b(lsic types of data movement in shirt registers arc iIlustratcd in Figure 9-46.
fR!~
0"",," ~fI} "',"m"
"''" , ,' --{ f f f ] -
(a) Serial
(b) Selinl i(\/~hi rl
i n/~hili.
•
righlherial out
OM" '"
left/serial ou!
in
9 ""'°'" Ie) .....lr.IUcl
iJl/scri,~
Data in ~
W
" "' -wH
/ ,
~
I
Ouln OU I
OiU:1 001
(dl Serial in/parlll1cl out
Ie) Pnrn ll cl ullpM:lUel out
(t) Rotate ri);hl
( s)
Rot ute left
FIGURE 9 46
KEY TERMS
•
S hi ft rcg isler countcrs arc shi ft registers with feedback that c)( hibit ~pecial seq uences.. Examples are Ihe John!;()n counlcr (lnd the ring cou nter.
•
·Ille Joh nso n counter has 211 Sl(lt CS in itS SC
•
T ile ri ng coullI cr has /I Slales in its Se(luencc.
Key terrm "nd other bold terms in the ch-.p ter ilore defined in the e nd-of-book rJOSSi!ory. Uid i rt.'Clional l· l a\' i n~
IWO directi ons. In a bidirCC lio nui ~ hin register. the stored
I.uua l:iUl be shifted
tig ht or Je fl. Loud To cnt er d.1ta in to a sh ift regislcr. Register One o r more fli p- nops uscd to store (lnd shift dma. S hiH To move bimlry data rrom ~t agc to stagc within a shift rcgi ~l eror ot her stornge device or to move bin1\ry dma i1)to o r OUI of the device.
S tugt' One storage c lement in (l regis te.r.
528
•
SHIFT REGISTERS
Aillwers
~hin rcgi ~[er consists
(b) a nip. flop
(al a Iml:h ~rially
L To
of (el
11
(d) fou r bi[s of s[o rage
byte of S[ord2e
shifl a bytc of dll HI into a shift register. there must be
(a) one dock pulse
(b) o ne lood pu lse
(e) eight doc k pulscs
ld) o nc dO(;k pulsc fo r each I in the data
3. To parullcl lO
(b) onc clock pulse fo r each I in the data
(e) eight doc l.. pulses
(d) o ne clock pulse fo r eoch 0 in the data
4. lllC grou p of bits 10 110 10 1 is .<;Cllal1 y shined (ri g ht-most bi t fi r.;t) into an 8-bit pamlle l output shi ft 1'C!,';ster wi th lin in itial stat e of 1 1100 I00. Afte r twO cloc k pulses, the register contai ns
(a, 0101 111 0
(b) 10 11010 1
(c) 0 111100 1
(d) 0010 11 01
S. With il 100 kH z dock freq uency. eight bits can be seria ll y entered into a shift register in (n) 80 P.s
(b) 8 p..s
(e)
80 ms
(d) 10 p.s
6. With II I MHz clock fn.'(llIet1l:Y. cig hl bilS can Ix: pamllcl e lllercd illlo il shift register (u) in 8 p.S
(b)
(c) in I p.s
7. A
in thc propagil tion de lay time of eight flip-flops
(d ) in the pro!XIgati on del ay titllC of one flip. flop
nMld u l u~- I O
Jo hns(Jn I,:Olln tcr TCq ui res
(a) ten nip-flops
( b) lOur nip- flops
(c) live flip-flop!;
(d) twelve flip-l1ops
8. A modulu~- I O ring eoomer req uire~ a min imum of (a) len ni p-flops
(b) fi ve nip-flops
(c) fo ur fl ip-flops
(d) IWclve flip-flops
9. When [In R· bi t serial in/seri al out shift rcgister is used for a 24 /-IS time de lay. the clock frequcncy must be
Ca) 4 1.67
kH~
(bl 333 kH z
(d) 8 MHz
(el 125 kHI
10. The pUfJ'L'!II;: of the ri n!! CQu nter in the keyboard e no.:oding d n:u it of f-lsul'e 9- 3f; (3)
to SC(IUcnti;llly :lppl y 1\ HIG H
[0
i~
eoc h row I'of detcction o f key c100llre
(b) to provide trigger pulses for the key code register (c) to SC(llI enti:lll y a ppl y il LOW to c;lc h
row for detection o f key c100llre
(d) to seque nti;!lI y reverse bias Ihe diodl.'S in cac h row
PROBLEMS SECTION 9-1
Amwers to odd-numbered problem! are at th e end of the book.
Basic Shift Register Functions I. Why are shift registers t:onsidered b.1sil,: memory dcvices7 2. What is the ~lOrage capacity of a register [hal Ciln retain two by tes o f data">
SECTION 9-2
Serial In/Serial Out Shift Registers 3. For [he d;lta input lI nd dock in Fig ure 9-47. de tem linc the SIII[CS nf c(Il' h fli p-flop in the shift rcg:isler of Fig ure 9-3 ilnd show the Q wa\·efon ns. AS~U I1IC thallhe reg ister contains all Is initia ll y.
FIGURE 9-47
eLK
,
,
' , , Serbl d~t" in put n ' _-.J__iJ- -'-- --'-l~--'----'-----''l_L_l_
PROBLEMS
•
52'1
4. Solve Problem 3 for the wuveforms in Figure 9--48. FIGURE 9-41
e LK Serial dm" input
5. W hat is the Slale of the reg ister in Figu re 9-49 after each clod pulse if it Sl
10100 111 1000 ~I
Scriillllillilin = t : 0
e LK - - -
SRG 12
C '-"-- - - --
~
Serial d ala 01.. 1
. -'
e LK Serial dmil in FIGURE 9 - 49
6.
For the serial in/serial OUI shift registCf. delermille the dma-oUlpul waveform for the datil-input nnd dock wavefOlms in Figure 9- 50. Assume th at [he regisler is initially cleared.
Scri,] """ i"
CLK
--jD L --+<_--=c___________...I1 SCri~l lL~U!m;1 SRG 10
e LK Seri:!! ,bt" in FIGURE 9-50
7. Solve Problem 6 for th e w
e LK Seri"t data in fiGURE 9 - 51
R. A lead ing-edge d ocl,.cd ~c ri ul in/serial nu t shili regi ster has a duta-output waveform as shown in Figure 9- 52. Wh
most) is the LSO'! FIGURE 9 - 52
()JI~ 0111
eLK :··----8;lIal)' lIumbcr--- - _' :
530
•
SHIFT REGISTERS
SECTION 9 - 3
Serial In/Parallel Out Shift Registers 9. Shuw" o.; umplete liming diagram ~howing the pamllel outputs for the shift rq;ij;ter in Figure 9- 8. Usc the w3vcfonns in Fig ure 9-50 with the reg ister initially clear. 10. Solve Problem 9 for the input w"vefonl1s ill Figure 9-5 1.
II. Devclop thc Qu through Ql ou tputj; for a 74HC I fi.4 shifl regbler wilh the input shO\\'n in Figure 9- 53.
FIGURE 9 - 53
-fLfLfLfL~ • • I I '
elK
A..,..... . I . · .IL..!....J /I
ctll
SECTION '}-4
wave fol1n~
,,
..u
•
I
r
I
I
I
I
I
I
I
I
I
I I
I I
I I
i I I
I I
l...LJ
I
!
Parallel In/Serial Out Shift Registers 12. "llie shin register in Figure 9- 54(a) has SHIFT/ UJAD :md e LK inputs as shown in p;:Ln (b). The serial data input (S£R) is a O. The ~ral1 ct d"ta inputs arc I)" = I. I) , = O. D~ = I. and D ) = 0 as shown. Develop the dala -Qutput w.lVe foml in relatiOfl to the inpUls.
o SIIIF1"fLOA f)
SRG4
0",,,
SEN
elK
elK
--t~e,--_____
J
FIGURE 9 - 54
SfffF11LOilD
~,
,,
J......jr---"--'---'L.l....Jr--'-----'-- -
'"
13. T1 le waveforms in Figure 9-55 are applied 1111 O. Dete rmine the Ql wavefonn.
elK SfHLD
SER CLKINH
,,
\0
a 74HC I65 shili
regi~h:r.
The parallel inputs are
,, ,, ,, ,, , , ~~G-D~0-r~~G-h4T
I
~_~_~_~_~_~_~_'"--"-lL~_~_~_~_:L__
FIGURE 9 - 55
14. Solve Problem IJ if lhc p;:l!"allcl inputs arc al ii . 15. SoJ\'e Problem 13 iflhe SEN input IS inverted.
PROB LEMS
FIGURE 9 - 56
eLK J
,,
K
531
,,, L...I
, , ,r--.-, ,, J
-,
--!-J
SII11JJ
•
,--<--"
CUi
I
I
,
L
I)"
D, D, D, SECTION 9 - 5
Parallel In/ Parallel Out Shift Registers 16. [)cterm ine ull the Q outpu t wavcfonns for a 74HC I95 4-bit shift register when the in puts are a~ ~hown in Figure 9-56. 17. Solve Prob lem 16 irthe SH;LV illPUI is in\'CI1cd alKl lhe rq~ is lcr is initiall y de" f. 18. Usc two 74HC 195 shili
SECTION 9-6
reg i ~ terl'i
to form
Bidirectional Shift Registers 19. For the 8-bit bidirectional reg ister in Figure 9-57. detennine the stme o f the regisler after each dock pulse for the RiGHT/ LEFT <.:ol"llrol waveform given. A HIGU on this inpu t elJablcs a shift to the righl.llnd a LOW enables a shitl to th e left. Assume that the register is initiall y slOring the decimal nurnbc:r seventy-six in bi twry. with the righI-most posit.ion being thc LSB. There is a LOW 0 11 the data- input line.
DOM =:JD
'KG'
L
-'I-
R1CHTI~:; ===+ L_c______
e LK i)al.a{)U1
R/GHTIILFT
..!J, '---'--'L-.l_iJ
FIGURE 9 - 51
20. Solve Problem 19 for the w,wefollns in I' igurc 9-58. FIGURE 9 - 5 8
eLK RIGHT/UFT
, ,
---c___--.Jl1l___J----
21. Usc two 71\He I'M 4-bil bidirectiona l shift register; register. Show the con nCX:l ion~.
to e,.c~ tc
an S-bit bi di~li o n(ll shift
22. Determine the QOll tputs of 11 74HC I94 with the inputs shOWn in Figure 9-59. D!. :JIMI D \ are all H IGH .
Inpul~
Do. D J,
532
•
SHIFT REGISTERS
SECTION 9-7
Shift Register Counters 23. How many nip-nops arc retjui rcd to implement eaeh of the followi ng in a Johnson COlllllcr configur;lIion: (ll) modul u~·6
(b) mod ulus· IO
(c) lllodulus· 14
(d) modulus- 16
24. Oww the logic diagnun for a modulus· IS Johnson coulller. Show Ihe liming diagr.ull and write lhe sel.juence in tabular form.
25. For Ihe ri ng l."Ounler in Figure 9-60, show the wuvefoml~ for ~.dch nip-flop outPUt wilh respect to thl.· clock. Assume that FA) is initi;Jlly SET :.111(/ th.,t the rest arc RESET. Show at least ten clock pulses.
, - -
~O
Q -
r-O
F o >c
pc
pc
>c
'-;;;;J
'-m
--;;;;-
e lK
Q.
r-
FF3
~ f)
0
>c
0,
>c
'F<
pc
-'- 0
pc
Ff~
1'1'5
Q. ~ O r-
0'
E:. v "-
-'-0
pc
>c FF9
Ff8
FF1
FIGURE 9 _ 60
26. The wu\"Cfonll p;.lItem in FiE-ure 9-61 is rcquin.:(/, /kvise a ri llg counter. and indicate how it cun be preset [0 produce this waveform (HI il~ Q" output. AI eLK 161hc pattern begins tn rcpe
e lK
,, I ,'7 ,' 3 ',4 ',5 ," ,," ,", ,," ,,'W ,I t l',12',,1311,, 4 ,,115 Q,
SECTION 9 - 8
:0: : :
0
()
()
0' 0 : 0 : 0
()
Shift Register Applications 27. Usc 74HCI95 4_bi\ shift registers to implement II 16-bit ring count er. Show the conne:.:tion~.
28. What is the purpose of lhe power-on LOAD input in Figure 9- 38? 29. Whill happens when IWO keys
SECTION 9 - 10
Troubleshooting 30.
CLK
Oma in
B~lsed Oil Ihe W",t ve fOmls ill Figure 9-62(a). determine Ihe most likely problem wilh the register in pan {bl of lhe ligu~ .
,
Tl ~,__==:-----:C--'
L
Q"J,, Q,
,-
Oma ;!
,'
V
P.C
Q,J
Q, - - - - ,
CLK
(b, FIGURE 9- ' 2
~
Q,
Q,
Q"
D
P.C
>-0
P.C
Q,
>-- 0
>C
PROB LEMS
•
S33
3 1. Refcrto the p;.!rtIl1cl in/scri al out shift reg i~ ter in Figure 9- 12. The register is in the state where QoQIQ2Q] = 100 1. and Dr:!JIJ)2DJ = 10 10 is loaded in. W hentheSIfIFT/1..0AD input is taken I IiGll the data show n in Figure 9-63 arc shifted out. Is this operation correct? If not, wlmt i.~ the most likely problcm?
FIGURE 9 - 63
eLK
-f1--f1--f1-fL I: W
32. You have found that the bidirectional registcr in Figure 9- 19 will shift datu right bl.llnot left. What is the most likcl)' fau lt"! 33. For the keyboard encoder in Figure 9-38. list the pussible fnulls for each of Ihe fo llOwing sym ptoms: (a) The stnte of Ihc key code register docs not cllllnge for lilly key closure. (b) 'Ibe staleofthc key code regisler docs nOI change whe n any key in the third mw A proper code occurs for all othcr key closures. (c) The state of the key code rcg istcr docs nOt change when any key in closed. A proper code OCCurs for all other key closures.
t h~
i.~
closed.
fi rst oolumn is
(d) When any key in the second oolumn is closed. the left three bits of thc key c"de (QOQIQ:J are correel. but the ri ght thrt.'C bits arc all Is. 34. Develop a test procedure for exercising lhe keyboard enl.-OOer in FIgure 'J..38. Specify the pnxedure on a stcp-by-sICp ba~ i s. indicating the OlltP111 code from the key code ,,--gister that should be ob!;crved at each step in the teM. 35. Whal sym ptoms are ob!;erved fo r the following failures in the scrial-to- paru llel ooll\'ener ill Figure 9- 33: (a) AN D gate output stllek in HIGH state (b) clock generntm' llIItput stuc k il] LOW
~Me
(c) third stage of da ta- input register Muck in SET stale (d) telminal count output of OOulltel" stuck in IUGH stille
Digital System Application 36. Wh
37. Assume the ent ry code is 1939. I)c term ine the state!'; of shi rt It.·gisler A and shift rcgistcr C aflcr the second oorrcct digit has been en tered. 38. Assume thc enl ry code is 7646 and tne digits 7645 are emered. Determi ne the states of shift regi.~l er A and shift register C aft er each or the digi ts is en tered.
Special Design Problems 39. Specify the devices that can be used to implement the scri al. to-p.1mllel d:tla converter in Figu re 9-33 . Develop thc comp lcte logic diugram. showing any modHications nccessary 10 accommodate the speci fic devices usC
534
•
SHIFT REGISTERS
Multisim Troubleshooting Practice 45. Open lilt: P09-45 lind test the 4-bi t ~h ifl reg ister todeterminc iflhere is fau ll if pos~ib l e.
faull. Idenli fy Ihe
3
46. Open file P09-46lllld tCSI thc 74164 8-bit seri.. , in/para llcl QUI slMt registcr to delennine if lhere is a fau lt. Iflhcrc is 1I fau ll. iden lify il if po~ib'e.
47. Opcn fiJc P0947 and tc~t the 741 65 8-bil parn llel load shift regisler lode/erminc if then:: is 11 faull. If there is a fllu ll. identify it if po.-.s ible.
48.. Open li le 1"09-48 and tL....1 the 74 195 4-bit paraJlclllCl:f..'!>s shirt reg iMe r 10 dctcnninc if thcre is a fau ll. If there is a fault. identify it if possible.
49. Ope n filc f'O')-49 ;U1d tc:;,l thc Io-bit ri ng C{)tllllertO uetennine if there
i~
a fault . If there is a
fau lt. identify it ifpossibJc.
SECTION REVIEWS SECTION 9-1
Basic Shift Register Functions I. A eoullter hilS a specified Sc<]ucncc of sta tes. but a shift regiMer does nOl. 2. Stomge and dala lTlovcmcotllre [wo funct ions of a shift reg i.q er.
SECTION 9 - 2
Serial'n/Senal Out Shift Registers I. FFO: d~ta inpu l to J II• dill a input to K11 : FFI: Q" to J " toJ., . Q~ 10 K,
<10
to K1; FF2: QI to j~. <11 to K !; FF3: Q2
2. Eight clod pul!>t.:s
SECTION 9-3
Serialln/ Parallel Out Shjft Regi.rtet's I . Ol OOafter 2c1od:pulscs
2. Take the serial o ulpul from the rig ht -lTlost flip- flop for serial o ul ClpCl1ltion.
SECTION 9-4
Parallelln/Serial Out Shjft Registers 1. Whcn SHlFfj U JAD is HIGH. the data are shill ed Ilgh l o ne bil per clock pulse. Whcn SHIFf/ LOA/) is LOW. [he I..!n la on Ihe parallel inptus are 10;].lcl..! imo Ihe le~btcr.
2. 'Ine pamlleJ load operation is
SECTION 9 - 5
ll~y nchronou s.
so it is not tlepenlle nt on the d ock.
Parallelln/Parallel Out Shift Registers I. The lima outputs arc 1001 .
2. Qn = I after one cloc k pulse
SECTION 9-6
Bidirectional Shift Registers I. I I I I aftcr the fi flh d ock pulse
SECTION 9 - 7
Shift Register Counten I. S ixtt\:n Slales arc in all S-bi! Juhnson l"Ul lllier seq uence.
2. For a 3-bi t Johnson counter: 000. 100. 110. I 11. 0 I I. 00 1. (XX)
SECTION 9-8
Shift Register Applications I . 625 scans/second
2.
Q~(MhQl(llQO = UI 1UI I
3. The diodes provide llilidirectiollal paths for pulling the ROWs LOW alld prevcnling H IGHs on [he ROW li nes from bei ng connecled to the switch matrix. TIle rcs i.~tor.i pull the COLUMK li ncs HIGH.
SECTION 9 - 9
Logic Symbols with Dependency Notation I. J\'o inputs arc dcpendcllt
Of)
the mode inputs bei ng in the 0 sta te.
2. Yes. the parodle] load is sy nchron ous Wilh the d od as indicated by the 4D label.
ANSWERS
SECTION 9-10
•
535
Troubleshooting I. A leli t input is used 10 SC(lu(:nce the circuillhroug/J all of its stiles.
2. Check the input to thaI ponion of the circuit. If the signal on that input is correct. the fault is isolated to the circuitry octween the good input and the bad o utput.
RELATED PROBLEMS FOR EXAMPLES 9-1 Sl'C Figure 9-64. FIGURE 9 - 64
9-2 The state of the register after three additional clock pulses is £lOC)!),
9-3 Sl'C Figure 9-65. FIGURE 9 - 65
9-4 Sec Fi gure 9-(ii FIGURE 9 - 66 IIIGI rt/LI,n eLK
:JiLn:::h:J:;:};::JiLn~
0. Q,
•0
' II
• (J
Q, Q.
Ii
' CI
' "
JT"! U
•
n
, '" .",'" ." '"
'" '"
!o
:0
9-5 Sec Figure ':J--(j7 .
FIGURE 9 - 61
, Q, =" 'T ", Q, =" , Q, ,-
·, ,,
'" ,
", '" " ,, ·,
[TL --l'l- --l'l- -f'1-
CL' Q,
",
-",
Q, u ' u Q,
", ,.,,
Q, " Q. " Q.
9--6
·
f=
,,
,,
, ,'
:'
, , , , '", .,
, ,'
",
, ~ , f'l() ·t,. -l'l, , '" ,' •, " '" ,' ' ", ,' '
.. .
~ '" lu
,,
n
,
, , '"
"
' ,' . , ~: ,, 1
tl
1
II
I
U
~ t
."
'"
~ fiL
-,-"=
'"
.", ,, ,, .,
113JIS = 333 kHz
SELF-TEST 1. (b)
9 . (b)
2. (e)
10.
(e)
3. (a)
4. (e)
S. (a)
6. (d)
7. (e)
8. (a)
CHAPTER OUTLINE
CHAPTER OBJECTIVES
10- 1 10-2 10-3 10-4 10-5 10- 6 10-7 10- 8 10- 9
Magnetic and Optical Storage
•
Oiscull the characteristlo of a flaY, memory
Troubleshooting
•
[II]
Digital System Application
Describe the expansion of ROMs and RAMs to increase v.ord length and "-
Basia of Semiconductor Memory
•
Random-Accen Memories (RAMs) Read-Only Memories (ROMs)
Define the basic memory characteristics Explain what a R.AM
•
Programmable ROMs (PROMs and EPROMs) Flash Memories
n. and how it "-
Explain the difference bet..veen stalk RAMi (SR.AMs) and dynamic RAMI (DRAMs) Explain whata ROM i'I and how itworlu
Memory Expansion DelOibe the variOlX typel of PROMs
Special Types of Memories
DiKun special twes of memories such.1o~ FIFO i'lnd UFO Describe the b,lIic orgilniz.ation o( magnetic did:.1 and magnetic '-'P'" DeKribe the basic operation of I'TI<'lgneto--optiOJI diw.1ond optiOJI disks
Describe b.'!osic methods (or memory testing Develop flowcharts (or memory testing Apply.1o memory device in a <)'Item appliOJuon
KEY TERMS
Byte
5RAM
Word
B",
Cell
DRAM
Add ress
PROM
up.1ocity
EPROM
Write
Flash memory
Read
FIFO
RAM
UFO
ROM
Ha rd disk
INTRODUCTION
Chapter 9 covered ~hift registers, which are a type of stori'lge device; in fact. a shift register is essentially a small-sCdle memory. The memory devices covered in this chapter are generally used for longer-te rm stor.1oge of l.1orger .1omounU of data than registers can provide. Computers and other types of systems require the permanent o r semipermanent storage of large amounts of binary data. Microprocessor-based systeml rely on storage devices and memories for their operation because of the necessity for storing pt'ogr.1oms and for retaining data during pt'ocessing. In computer terminology, memory usually refers to RAM and ROM and $torage refers to hard di~k, fl oppy disk, and CD-ROM. In this chapte r semiconductor memo ries and magnetic and optiCdI storage media are covered.
•••
DIGITAL SYSTEM APPLICATION PREVIEW
The digital ¥tem appliCdtion at the end of the chapte r completes the security system (rom Ch.1opte r 9. The focus in this chapter is the memory logic portion of the iystem, which stores the entry code. Once the memory logic is developed, it is interfaced with the security code logic from Chapter 9 to form the complete system.
v.iITm":O;"''''-oN wEI:\JnC,'C - - - - - - - - - http://W\.\IW.prenhall.com/floyd
537
538
_
10- 1
MEMORY AND STORAGE
BASICS OF SEMICONDUCTOR MEMORY Memory is the portion of a system for storing binary dala in large quantities. Semiconductor memories consist of arrays of elemen t.~ thai are generally either latches or capacitors. After complcting this chapter, you should be able to _ Explain how a memory stores binary data _ Discuss lhe basic organization of a memory - DeM:ribe Ihe wri te opemtion - Describe the read opel1ltion • Describe Ihe addressing opemlion _ Explain what RAMs and ROMs are
Units of Binary Data; Bits, Bytes, Nibbleli, and Wordli
•
•
The general definition of word i~ .3 oomplete unit of information comisting of
A"I-. a mle, memories store data in units lhal have from one to eighl bil.~ . 'Ille smallest uni t of binary duta,
The Basic Semiconductor Memory Array Each storage element in a memory can retain cithcr a I or a 0 and is called a cell. Memories are ml.lde up of arrays of cells,
I
I
2 3
, 4
I
,1
": 1
::m
,1
"
: 1
I 2 3 4 5 6 7 S (a )
S x Snrmy
" 16
I 2 34 (b) 16 x 4army
6
"
: 1
"
: 1
,1
, 1
.::~ 63
Ie) M X I array
FIGURE 10 _ 1
A 64-cell memory array organized in three different ways.
The 64-cell umlY can be organj..-..ed in seveml w
BASICS OF SEMICONDUCTOR MEMORY
Memory Address and Capacity The location of a unit of dal<) in a memOlY army is called its addrcss. ForexlImple, in Figure 10-2(a), the address of a bit in the 2-dimensional army is spec ified by tile row and column as shown. In Figure 10-2(bl, the address of a byte is specified only by the row. So, as you can see, the address depends on how the memory is or<~anizcd into units o f data . Personal computers have random~aceess memories organized in bytes. This means that the smallest group of bits thm can be addn::ssed is eight. 1 FIGURIE 10-2
Examples of memory add,e" in a array.
l-dimen~o n
6
, 7
I 2 3 -1 56 7 8 (a) ll1c ,KJdrcss of the blue bit is row 5. column 4.
(b l ll1c acklr~ of1h.. bl ue byte is mw 3.
In Figure 10-3. the address of a byte in the three-dimensional amlY is specified by the row and column, a'i shown. In this case. the smallest group of bits that can be accessed is eight.
Example of memory add ress in a 3-dimen~onal arr",y.
lHJW 1 2345678
The address of 1he blue byte is row 5, culumn 8.
The cupacity of II memory is the lot al number o f data units Ihal Cl.ITI be stored. For example, in Ihe bit-organizcd memory army in Figure 10-2(a). the capacity is 64 bits. In the byte-organized memory army in Figure 10-2(b), the capacity is 8 bytes, which is also 64bits. In Figure 10. . ·3. Ihe capacity is 64 bytes. Computer memories typically have 256 ME (M B is megabYle) or more of internal memory.
Basic Memory Operations Since a me mory stores binary data. dala must be put into the memory and data mu<;t be copied from the memOl), when needed. The wrile operation pUIS data into a !
•
539
540
•
MEMORY ANO STORAGE
memory or out of the memory). In this case of byte-organized memories. thc data bus has at least cighl lilles so that all ci!;hl bils in a selected address are lransferred ill parallel. For a write or a re.'ld opemtion. an addre~~ is selecled by placing a binary cooe reprc..:;enli ng the desired address 011 a set of lines called the address blls. The addrcs.~ ccrle is decoded internally. and Ihe appropriate address is selected. In Ihe ease of the 3-dirnensional memory army in Figure 10-4(b) there are two decoders, one for Ihe rows and one for the columns. T he num ber of lines in the add ress bus depends on the capac ity of the memory. For example, a IS-bit address code can select 32,768 locations (2' 5) in the me mory, a l6-bit addrus code can seleci 65.536 locations (2 lh) in the memory. and so on . In personal compulers a 32-bit address bus can select 4,294.967.296 locations (2.IJ). expressed as 40.
FIGURE 10-4 Atkin:"" decoder
Block diagram of a 2-dimem iOfia l m emory and a 3-dimensiona l memory showing addreu bus, address d ecooer(s), bidirectiol'l
Addrr~~ bu~
MelDory amJ)
Dala bus
a nd read/write ;npub.
1 I
(a I 2·dirTl<'ll~ i{lllaL
Re-.ul
\\'rile
H<'ad
Wri le
me mory arr,!}
j
I
R~
oddress
,,,,,,,,",, Address bus
MenlO!) array
11--------111 Cnl umn
addre.,,~
(\(:code,
( b) )·dimern;ionaJ memory array
Th e Write Operation
A simplified write operation is illustrated in Figure 10- 5. To store
a byte of data in thc memo!),. a code held in tht! address n::gisler is plitcetl on Ihe add re.s.~ bus, Once the add re.~s code is on the bus, the address decoder decodes the addrc!;S and selects the specified location in the memory. The memo!}' Ihell gels a write command. and the data byte held in Ihe data regislcr is placed on the data bus and stored in the selected mcm01)' addre ss. thus completing the write openltion. When a new dala byte is wriuen illlo a memory addres.~, the current dato byte stored at that address is ovenvriuen (replaced with a new data byle).
BASI CS OF SEM ICOND U C TOR MEMORY
Address register
D-Jla register
1011 I
:..L:..LI=0-cl,-, I I
LI:.. 1 Ll:U:.LI,, " LI(c'.LI
0
(i)
,! --.,1 --0
2 Addrcs.~
- - i ;;
bus
J
4 -- 0 ~ I
,-
1
7
0
•
541
FIGURE 10- 5
1Il\J~l.r.Ition of the write operatio n .
1 •i
:£
•
0
0
u 0
u u
0
U
0
0
0
0
j
0
0'
1 00
0 2'
0
0
0
0 Data bus
0
0
Q
J..!.-L..J,.
10
Write
(i)
o(9
Address
~'t>dc
1111 is placed on the address bus and address 5 is ~ Ieo.:led.
Dala byte is placet.! on lhe data bus. Write command c;u,,;cs the dala byte 10 be ~tored in addre.,~ 5. replaciug previous d3ta.
The ReDd Operation A simplified read opemlion is ill ustmted in Figure 10--6. Again, a code held in the addres~ register is placed on the address bus. Once the addre~s cooe is on the bus, the address decoder dccode~ the address and selects the speci fi ed location in the memory. The memory then gets a read command, and 11 "copy" of the data byte that is stored in the selected me mory address is placed on thc data bus and loaded into the dat,l register. thuscompieti ng the read opemlion. When adata byte i ~ res, it also remains stored at that address. Thi~ is called l1ont!e.umctive relit!.
Addrc5S regiMe!
1)"1,,
101 1' 1
fl
Address o.\ccodcl'
0
(i)
r l
----,.0 2 --I
Altdress bus
0 0
---< ,
0
j
0
~
0
0
0 ,0
0
0
U
0
0
0
4 ----10
0
0 '0
,
0
0' 0
0
0
,
=r:
7 -- 0
0
0 0
0 I
0
0 ReUlI
(i)
Alldrcss CQde 011
@
Read COmmOlllll is applitll_
o
i~
0 0 0 0
Bytc-organi7.cd nX!mory ami)'
0
placed on the aIIdreS!i rug and addreS!; 3 is selecled.
H Ie I:onlents of adIlress 3 is placed on Ihe data bus and shiflc
regi~1cr,
register
Data bus
fiGURE 10- 6 lIIultr.lb·on of th~ read oper.3tion.
542
_
MEMORY A ND STORAGE
RAMs and ROMs TIle two major categOlies of semicond uctor memories arc the RAM :lIld the ROM. RAM (mndom-a(."(:ess memory) is a type o f memory in which all addresses arc accessible in an equal amount of time and can be selected in any order for a read or write operation. All RAMs have both read and write capability. Because RAMs lose stored data when the power is turned off. they are ,·olatile memories. ROM (read-only me mory) is a Iype of memo ry in which data are stored pennanently or sernipennanently. Data can be reHd from a ROM , but there is no wrile opemtion as in the RAM. The ROM, like the RAM, is a I1Indom-access memory bUl the term RAM traditionally mellns a I1Indom-access read/II'r ite memol),. Sevenll types o f RAMs a nd ROM s will be covered in this chapter. Because ROMs re tain slared daw even if power is turned off, Ihey are nonvollJlilc me morie.." .
I
SECTION 10-1 REVIEW Aruwers are at chapter.
th~
end of the
1. Whilt is the SffiilUest unit of cL:Jta that I2n be stored in il memory? 2. Whilt is the bit Cilpild ty of il memory th
l
5. How is a given unit of dabl located in a memory? 6. Decnbe the diffe rence between a RAM and a ROM.
10-2
RANDOM-ACCESS MEMORIES (RAM.) RAMs are read/write memorie.." in which data can be written into or read from any seleclCd addre ss in any seque nce. When a data unit is wri nen into a g iven address in the RAM, the data unit previously stored at that address is replaced by the new data unit. When a data unit is relld from a g iven address in the RAM, Ihe dma unit remain:" stored and is not enlsed by the read o pe mtion. This nondestructive read operatio n can be viewed as copying the content of an
The RAM Family The two categOl"ies of RAM are the .~/(l/jc RA M (SRAM) and the dYI/(/fuic RAM (DRAM ). SIalic RAMs gene rally use latthes as storage elements and can therefore store data indefinitely lI.~ IOIW m; (Ie p ower is applied. Dynamic RAMs use capacitors a~ storage elemenlS :lIld cannot ret:Jin data very long without the capacitors bei ng recharged by a process called refreshing. Both SRAMs and DR AMs will lose stored data when de power is removed and , therefore. are classified as volatile memories. Data can be relld much faster from SRAMs than from DRAMs. However, DRAMs can store much more daw than SRAMs for a given physical size and cost because the
RANDOM - ACCESS MEMORIES (RAMJ)
DRAM cell is much simpler, and more cel ls cun be cmmmed into a g iven chip areu than in the S RAM. The basic types of SRAM are the (I,\'Yllchrrmous SRAM uoo th esYllc/i roIlOl/S SRAM with a burst Featu re. The basic type:- of DRAM arc the F(I.H Page Mo(le DRAM (FPM DRAM). the£rtcllde(/ DlIla 0 111 DRAM (EOO DRAM). the IJ/f/:{/ EDD DRAM (BEDO DRAM ), and the SYIlc/IIVJlOIIS DRAM (SDRAM). These are shown in Fi~ure 10- 7.
Rm)llufllA~'ttS.~
MeiflOf}'
(RAM )
Stmi,' RAM (S RAM)
AS)'f1dm)rl()U~
SRAM (ASRAMI
Dyllamic RAM fORAt-'1)
Srl1Chrol1(lll~
FO~I
PlIl!c MOO<
SRAM with bun.! reature
(SS S RAM )
DRAM (FPM DRAf'.U
Extcodcd
Bu~t
Data Out
EOODRAM /BEDO DRAM)
DRAM IEOOI)RAM )
FIGURE: 10- 7
The RAM (amity.
Static RAM, (SRAM,) Memory Cell All Sialic RAMs arc chamclerizcd by latch memory cc ll ~. As long as de power is ap plied to a static llIelllO"Y ce ll, il can relain a I or 0 slate indefinitely. If power is removed, the stored data bit is lost. Figure 10- 8 shows a basic SRAM latch memory ce ll . The cell is selected by an act i,'e level on the Select line Hnd a data bit (I or O) is wriuen into the cell by placin!; it on the Dat
A typic315RAM latch memory cell.
D:ua ill
J.).lIa oot
&sic Static Memory Cell AlTOr The memory cells in a SRA M arc orgHnized in rows and columns, as iUustrated in Figure 10-9 for the case of an 1/ x 4 array. All the cells in a row share (he smne Row Select line. Each set of Data in and Dma outl ines go to each cell in a given column and are connected to a .o;ingle data line that serves HS both an input and output (Data VO) tllrough the data input and daw output buffers.
Syochronoos DR AM (SDRAM )
•
543
544
•
MEMORY AND STORAGE
FIGURE 10-9
Ru\\ SeIL"-1 II
----t----~---1---,
Rn,," Sd~,,-, I
- -+- -t----1f--f--..,.- j-j-1-++,
HOI' s.-k,,1 :!
--t-~f--I--I--~-t-t-1-++,
,, ,
"
tnf~~~ DaHl lnputJOUlpul
Buffl!l1< and COOlrnl
0:'13 1/0 MilO
Dala IfO
I);,la [10
1)..1,. I/O
Bil I
Bil :'.
B•• ,
To write a d.1lll unil, in this case a nibble, inlo 11 given row of cells in the memory arrdy, [he Row Seioci line is laken to iL" active state and four data bils are placed on Ihe Data 1/0 lines. The Write line is then laken 10 its act ive state, which causes each data billo be stored in a seloclcd cell in Ihe a.,sociated column. To read a data unit, the Read line is L1ken 10 il!. active stale, which caw-e~ the four dala bit~ sloreJ in the ~lected row 10 appear on the Dn... 110 lines.
Basic Asynchronous SRAM Organization An asynchronous SRAM is one in which the operation is not synchronized with a system clock. To illustnue the general organization ot" a SRAM, a 32k x 8 hil mcmory is used. A logic symbol for this memory is shown in Figure 10-10. FIGURE 10- 10
RAM 32k><8
logiC diagrilm for iln ;uynctUO/1OUS
32k x 8SRAM.
" ,~ , --
A, A, A,
A,
,I,
-\ddr.·" IIII
V V V V
flO" 110 1
I. - -
V
J/O~
V
IfO,
1,-
V V
110" IK>_
J 4,'.
l A.
0 it l2.161
A" A"
,11 1
A"
cs
rO!!pso..&;n IWRITEI
II f.
IRF"AI)I
()t.
1000lVT U.AIlILI
110 ,
110,
llala Inll"" UJ alKI C'ItlIJ'U" 10)
RANDOM-ACCESS M EMO RIES (RA Ms )
•
In the READ mode. the eight data bits th;:lt are stored in a selected address :lppcaron the data outp ut lines. In the WR ITE mode. the e ight data bits that are applh::d to the data input lines arc stored ul u scleclcO address. The data input and datH output lines (1100 throug h 1107 ) share the same lines. Duri ng REA D. they act as output lincs (00 th rough OJ) and during WRITE they act as input lines (/u through 17)'
Tristate Outputs and Buses Tristatc buners in a mcmory allow Ihe data lines to act as eithe r input or outpul li ncs and connect the mClllory to the data bus in acomputer. These buffers have th ree output states: HIG H ( I). LOW (0). and HIGH-Z (open). Tristate outputs are indicated on logic symbols by a sllmll invcI1ed tria ngle ('\7). WI shown in Figure 10... 10, lind are used for compati bility with bus SIru.clurcs such as those found in micl'Oproces.<;or-bascd systems. Physically. a bus is a set of conducti ve paths that serve to interconnect two or more fu nctional components of a system or severnl divc rse systems. Electrically. a bus is a collcction of specifi ed voltage levels and/or CUtTen! levels and signals that allow the various devices connected to the bus to com municate and work properly togethe r. For example. a microproccssor is connected to me mories and input/ou tput devices by certain bu s structures. A n address bus a llows the microprocessor to addre....s the memories. and the daw bus provides for tra nsfer of datil between the microprocessor. the memo ries, and the input/outp ut devices such as monitors, printers, keyboards. and modems. 1lle cont rol bus allows the microprocessor to control dala transfers and timing fo r the vario us components.
Memory Array SRAM chips can be organi£..cd in single bits. nibbles (4 biIS), bytes (8 bils). or mult iple bytes ( 16. 24. 32 biLS. etc.). Figure 10- 11 shows the orga nization of a typical 32k x 8 SRAM. llle memory cel l array is
Mcmnry llrrny 1\()df\'S.'
linc'
R~
,lc<:oclcr
Eight input buffc,~ ........ llpu I\kmoryllmly
256 rows x 128 cotum ns x 8 bit>.
"0,
256 ro\\5 x 128cotulllllSx 8 bits
.. -_. ----_. -_ .. -_ .. Input
Cotullln VO
dat a cootrol
Cul umn dexodcr
_.Outl'tJl data
Eight output buffets (a) Mcmory IIIT'J)' conligurnlion FIGURE 10 - 1'
!Mjic org''lni2.'ltion of iln illynchronous J2 k x 8 SRAM.
(bl Memury hlncl; cliagmm
54 5
546
•
MEMORY AND STORAGE
10 select o ne of the 256 rows. Sevcn of thc fiflecll decoder to select one of the 128 8-bit columns.
addre.~"~ lin e.~
are dceodet.l by fhe t:olumn
Read In the REAO mode, the write enablc input, WE, is !-IIGH and the uUlput enable. GE, is LOW. 'lllc input tnstate bu ffers are disabled by gate Cit and the column output tristate buffers are enabled by gate C~. Therefore, the eight data bilS from the selected address are routed throutlh the column 110 to the data lines (lIOu though 110 7 ), which are acting ,l<; data output lines. Write In thc WRITE mode, WE is LOW and OE is HIGH. The input buffers are enabled by gate G1, and the output buffers are di sabled by gate G2 • Therefore. the eight input data bits on the data lines are routed through the input dma control and the column 11010 the select(.l.l addn..:ss and stored. Read and Write Cydru Figure 10--12 shows typical timing diagrams for a memory read cycle and II write cycle. For thc read cycle shown in part (lI). a valid ,Iddress code is lIPplied to the address lines for a spel:ifi ed ti me interval l:al!t:d the rem! cycle lillll-'. 'Re. Next., the c hip select (CS ) and the uutpu t enablc (OE) inputs go LOW. One time interval after the OE input goes LOW, a valid data byte from the se lecled address a ppears on the data lines. This lime inlelVlIl is called the outpur I-'l111bff! access rime, 'Gf}' Two olhcr acccss times for the read l:ycle are the lIl11frns aCCI-'s.\" tillll-'. tAcr measured from the beginning of a valid address to the appenrallce o f valid data on the dma lines and the chip e/lab/I-' lIC' un lime. I r:Qo measured from the HIGH-to-LOW tnmsition of CS to the appearance of valid data on the dina lines. During each read cycle. one unit of data. a byte in this ca~e. is read fro m the memory. FIGURE 10- 12
B
CS (Chip sclea) O£ ( Qulp'.11 enable)
o (O;ua oul) (a) Read ~'}'CIc
(WE t-IIGIII
\~ _ _ _ __
CS (Chip select) t
:
WE (Write t.'11able)
-
'r - - - 1,'
I
\
t----'~ l,--+I ~--------' , ~-IIW----l-lhll}'-..I
_ _ _ _ _ _ _ _ _ _-,~
I (Olda in) __ _ _ _ _ _ _ _ _ _ _~A
,,
(0) Wn le cycle ( WE LOW)
f
-L
v .. h (/
~ ,'
~
,,
RANDOM-ACC ESS MEMORIES (RAMs)
•
547
For the write cycle shown in Figure I 0-12(b), a valid address code is applied to the adlines f0r a spec ified time interval called the wrile ..:ycle lime, 1",0 Next, the chi p sclecl (CS ) and Ihe wrilC enable ( WE ) inputs go LOW. T he rt,.q' uired time interval from the begi nning of a valid address un til the WE inpul goes LOW is calk'tl the olltJress setup time, ' .s(M' The lime that the WE inpul must be LOW is the write pulse width. The time thaI the input WE must remain LOW aflL'r valid data are appLk.'d to the data inputs is designated tw~ the ti me that the valid input data must remain on the d..,la lines after the WE input goes HIGH is the llata holtllime, Ih(/J)' During eac h write cycle. one unil of data is wrinen inlo the memory, drcs.~
Basic Synchronous SRAM with Burst Feature Unlike the asynchronous SRAM, a synchronous SRAM is synchronized with the system clock. Fo r example. in a computer system, the synchronous SRAM operates with the same clock signal that operates the microprocessor so Iha! the microprocessor and memory arc synchronized for faster operalion . The fundamental com:ept of the synchronous feature of a SRAM can be shown with Figure 10- 13, which is a sirnplifit.'tI block diag ram of a 32k x 8 memory for purposes of illuslTmion. The synchronous SRAM is similar to the asynchronous SRAM in tcrms of the mcmory ilrray, ,lddrcss dt:coUcr, and rcad/wlitc und cnable inputs. Thc basic din'crence is that the synchrono us SRAM uses clocked f(,.'gistcrs to synchroo izc all inputs with thc sysICm clock. '111e add ress. the read/write input, the chip enable. and the input daHl are all latcht.'CI into thei r respective registers on an active clock pulse l.'<.ige. Once this information is latched. the memory operation is in sync with the clock.
,,;,
Burst <;:()nlru l
BurSI logic
X
--'---
t:::;=
A" A, '-
e LK A Q- A I4
Atldress
(e~ lcmal ~ ddress)
rcsi~tcr
"
IS
Memory I\mly
Address decoder
13
32k x8
Duta OlItpul rql i\tcr i, in
the pipelioco
==
s~llCh mnou~
SRAt-.l.
, Write "'gister
r> Da ta
Data inpul register
Output
Ell"ble
b llfl'en;
reBisler
1
OE
8
I!Oo-lI~
(1).";l tlO)
.)Ulpul
I
I/O comrul
>
•/
register
J)HtH
L-
8
FI G URE 10 - 13
A b.':!lic block di
There b 110 D,ur. 001/'1.11
8
8"
rcgi,terin~
tlo""-I hrou~h s}'rll:hrllnoo~
SRA M.
548
•
MEMORY AND STORAGE
For the purposc of simplification, a nOl
The m.ldn;:.o;s bits An Ihrough A I~ arc latc hed illio the Address regislcr on the posilive (:dge of a clock pulse. On the same d ock pulse. the state o f the write e nable (WE) line and chip select (C5) arc latchL-d into the Write rt:
The Burst Footure A'I> s hown in FiBun: 10- 13. synchronous SRAMs nonnally havc
Addre51 bunt logic. BUN ~'tllltrol
OK
l:Iinuf)'
]
~'Oun •..,r
Q,
Q"
JJ
JJ
I
I"
AI
--------
1.<""-.,, onk.T bit, uf '·M ... rn.:lt
~
To ~g in the burst ~que ncc, Ihe coullter is in its ()() .~tllt e and the two lO\Vest-ordcr address bits arc applied 10 the inputs o f the XOR gates. Assum ing that Au and AI arc bolh 0, the imernal addf(.'Ss se
Cache Memory One of the nltUlIr a ppl ications ofSRAMs is in cache memories in computers. Cache memory is a relati vely small, high-speed memory that slOf(.'S the most recently used instmctions or data from the larger but slower main Int.·mory. Cache memory can also lL<;e dynatnic RAM (DRAM),
RANDOM -ACCEH MEMORIES (RAMs)
•
549
whic h is covered next. Typically. S RAM is sc.'Vem! times faster than DRAM. Ovemll, a cache memory gets stored information to the mic.TOproccssor much fastc.'· lhan if only high-cap<'lCity DRAM is used. Cache memory is basically a cost-effective method of improving system performance without hm'ing to reson to the cxpL'nse of making all of the memory fast<'T. The concepl of cache memory is based on the idea that computer programs t.end to get instructions o r datu from one area of main memory before moving to anothcr area. Basically, the c.tChe controllcr "guesS<.'S" which ar<'"a of the slow dynamic memory the CPU (centml-procl:ssing unit) will nC<.'tlnext a nd moves it to the cache me mory so thm it is r<'''OIdy when nc<.'tIc.'d. If thc cache controlle r guesses ri g hi, the data arc immediately avail
Cadle AllQlogy There arc many analogies that can be uS{:d to describe a cache memOlY, but comparing it to a home refrig<.'fl.ltor is pe rhaps the most effective. A home refrigerator can be thought of as a "cache" for c<.,1ai l1 fo
Clock (elK)
Stock diagram showing I I and L2 cache memories in a computer system.
!)ala htJ .. A
Mi<:ropl"Otts-'iOr
,
bu.
Main memury
COC"'" cOlilfOtkr
L2t'>lche (SRAM)
(DRAM)
LI cm:he (inlema!)
Dynamic RAM (DRAM) Memory Cells D)'mlluic memory cells .'itore a data bi t in .1 small capaci to r rather than in 11 latc h. The advantage of this type o f cell is that it i.'i very simple, thus a llowing very large memo!)' amlys to be conslruct<.'tI on a chip at a [OW<'T cost p<.T bit. The dis."Idvantage is Ihm the stomgc capacitor cannot hold its charge over an extended period of ti me and will lose the stored data bil unless its charge is refreshed periodically. To refresh requires additi0l1
550
•
MEMORY AND STORAGE
FIGURE 10- 16
Column
(till
line)
A M05 DRAM ce ll. R~,
Cohllnn
,, ,
Column Re fr!:sh hun"cr
Rdn::.'h R~
Refresh butl~r
LOW
Rd rcsh
HIGH
R~
Output btl rrcrl Sense amplilier D~rr
RIW DtN
Lu\~
bu lfer
EIIG I I
Or.;
n~
Outptlt burre,"! Sellse ~."nplilicr Do~
R/W
fllG11
HIGH
LOW
,, ,
0"
LOW
LO,
LOW
, ,, Bit line
Bit line 111) Writi,,!;
~
1M Writi ng u 0 into the mclllOl")' ccll
I into the mel1Klly l~ 1l
Column
C"luUl:1 Rcfre>h buffer
Rcfr~~h
buffer
Ref,e..;!'
Ru\>,
LOW
Refresh
IIIGH
R,~
HIGH lI1GIt
St'nse amplifier D ot>T
RM
IIIG~I
Rti"V
t llGII fJ,N
Bil li ne (e) R~ading a I from the ",cmory l·ell
==a •
HIG H
!-1IGH
,,,
ON
'T
Dolfr !IIGH
!lIGf!
Dt~
-
Output hl1 ffer! Sense nJnpl ifie r
OUl pul huffer!
,, , Bill ine
(d ) Refrc~hing 1I stored I FIGURE 10 17
BaW"c operation of a DRAM cell.
line. The IransiSlor acls as a d oscd switch connecting Ihe capacilor 10 the bit line. This COI1tlL-clion allows Ihe capacitor 10 charge to a positive vo hage. a<; shown in Figure 1O- 17(a). When a 0 is to be slored. a LOW is applk-d 10 the DIN line. Irlhe cap."1Ci tor is storing a O. it remains lInchargL-d. or if it is storing a I. it disc harges as indicated in Figure JQ.... 17(b). When the ruw line is take n back LOW, the tmnsiMor turns off and disconnects the clp.'lcilor from the bit li ne. thus "trappi ng·' the charge ( I or 0) on the capacitor.
RANDO M-ACCESS MEM O RIES (RAM s)
To read from the cell , the R/IV ( Read/ Write) line is HIGH, cnabling the output buffer and disabling the input buffer. When the row line is taken HIGH, the transistor turns on and connects (ile capacitor to the bil li ne and thus to the output bufler (sense am plifier), so the data bil appcarson thedata-outputl ine (Dour). T his process is illustratcd in Figure 1O... 17(c). For rcfrl:sh ing the memory cell. U)C R/ IV linc is HIGH, t.he row linc is I-I IGH, and the refresh linc is HIGH. The tmnsistorlUms on, connecting thecapacilor to the bit line. Thc output buffe r is enabled, and the stored data bit is applied 10 the input of the refresh buffer. which is cmlbk'C.i by Ihe H IGI·I on the refresh input. This produces a voltage onlhe bit linc correspond ing to the stored bit. thus replenishing the capacitor. This is illustmte(\ in Figure 10-- 17(d).
Basic DRAM Organization The major ap plicmiol1 of DRAMs is in the main memory of computers. The difference bctwt.'Cn DRAMs and S RAMs is the typc of memory cell . As you have seen, the DRAM memory cell consists of one tra nsistor and a capacitor and is much simpler than the SRAM cell. nl; s allows much gremer densitit..... in DRAMs and resul ts in greater bit eapaci t;(.'S for a given chip area, although much slower access l.ime. Again. because charge stOR "(! in a capacitor will leak on~ the DRAM cell requi res a frequcnt refresh operation to preserve the stored data bi!. This requirement result.. in more comple)!. circ uitry than in a S RAM. Several features common to most DRAMs arc now discussed using a generic 1M x I bit DRAM as an example. DRAMs usc a technique called (ll[llress multipl exing to red uce the number of add ress lines. Figurc 10-- 18 shows the block diagram ofa I ,048,576-bil ( I Mbit)
Addre$f Multiplexing
R"fresh con trol 1100
IR"fresh <:utmt"r
ti ming
j rrrr0,,, r., 1== rt=; r~ 1--
"'" A&I",·
tinc'
,,," , ,,,
R= Imch
M"mt"Y 1!rrll)' R~
1024 rows X
t024
CiJllIInn.~
,=
f::
,
,---J =
CAS IWi
FIGURE 10 ... 18
Simplified block d iagrilm of .. 1M x 1 DRAM .
, llddn.'SS Imeh
tnput/Ou tput buffer.;
,,,oJ
'"
do:cod"r
Sense. llmplificrs
"'"
I
lc !
=
•
551
552
•
MEMORY AND STORAGE
DRAM wi lh a 1M x I orgauizalion. We will focus on Ihe blue block~ 10 illustrate addre~s multiplexing. The green blocks repn.:senllhc refre sh IO!,ic. 'nle ten addrt.'Ss lines arc time multiplexetl at the beginning of a memory cycle by the row address sck-c1 (RAS ) and the column nddress scicci (CAS) into {wo separate IO-bit address fields. First , Ihe IO-bit row address is latched into Ihe row address lmch. Next, Ihe 10bil column address is latched inlo the column address lalch . The row address and the column OIddrcss are decoded 10 seicci one orthe I ,()48,57fi add re.';se.~ (2:!O = I ,04R,57(') in Ihe memory array. The basic timing rOl' Ihe address muHiplc:(ing operation is show n in Figure 10-- 19. FIGURE 10- 19
B.uic timing for addreSl multiplexing.
Addrocscs
liAS CAS
:--:y.,==-~==::;-R_rn_'_"'_'"_·_"_-;.:X~==c:,:,:":",:":,,,=,"=,,==~x::=~==
-7
/ -----, F1 =-----
uddn:" j, laldll."tl ,,~n RASi, LOW. R~l\\
\ , _--.-----'/
I
(""nlumll add'e'~ j, 1:lIdlCll whm (""..Isis LOW.
Read and W,ite CydeJ At the beginni ng of each read or write memory cycle, HAS OInd CAS go aclive (LOW) to muhi plcx Ihe row OInd column addr<.--sses into the lalches and decoders. r'(H' a rCOId cycle. Ihe R/ W input is HIG H. For a write cycle, Ihe R/ W inpul is LOW. This is illustrnlCd in I--1guI"C 10-20.
,,,
FIGUR E 10- 20
Normal re;w and write cycle timing. Addr~
--:y.,
rc~d
R'f :lddre,~ X
'\
RAS
I
, ,
. 1
,)cI"
Column :lddn-....,
\
/
~
7
RJW
D~
<
Va lid d:lw
cyel"
..
, , Addres...-..:s
--:y.,
RII S CAS
RJW DIN
(b) W, ;\t:.:ydc
>,
,,
I wn lcc}dc
R'f, nrJdrC'o' X
'\
i
~
/
CAS
(, ) Read
X
Column :K1dre..,
X i,
~
/ \
/
r
\ \aJi
<
>---
RANDOM-ACCESS MEMORIES {RAMs}
•
Fmt Page Mode In the nonnal read or write cycle described previous ly. the row address for a particular memory location is first louded by an ac tive-LOW RAS and then the column address for th ut location is lomk'd by a n active-LOW CAS. The next location is sekcted by another RAS followt.'d by a CAS. and so on. A "page" is a section of memory ::wailable at a single row address and consists of all the columns in a row. Fast page mode allows fast sl1ccessive re,ld or write opernlions at each colum n address in a se\cclt.'d row. A row address is firstload<:d by RAS going LOW and remaining LOW while CAS is togglt.'d betwt.'t.'fI HIGH and LOW. A single row address is sck-'Cted and remains sclocl<:
__~r
RAS
CAS
R/lV
\ / \ / \
rm~
== - ==~:;:::7: : ;:\'- ~-=-~::;7=;\=-=--=-~::;7=;C~---" R""
Add resses
address
}-_-{
Column 3
Column I
'-_"' '''C ~_''_J
7~
_____ --<,
_C'__ ""__'m ___ " ~)---_ ado ....."';,. .
------------~~~------~~r----------<~ ----· ~ ~
~
~
FIGUR E 10_ 21 Fa~t
polge mode timing for a read oper<100n.
Refrrull Cycles As you know, DRAMs arc based on capaciJor c harge storage for each bit in the memory arruy. Th is c harge dL'grn 1024 rows. As an example, for an 8 illS refresh period. each row must be refreshed every 8 msl l024 = 7.8 J1S when distributed refn.'sh is used. _ The two types of rcfresh operations a rc RAS-(mly ,.efre.~h and CAS belo/'{' RAS refresh. RAS-only refresh eunsists of a RAS l ransi tion to Ihe LOW (act ive) s tule. which lutches
~
553
554
•
MEMORY AND STORAGE
thc addrcss of the row 10 be refreshcd whilc CAS rem
Type, of DRAM, Now that you h
FPM DRAM
EDO DRAM T he Extended Data Output D RAM, sometimes called hyper page /lux/e DRAM, is simi lar to the FPM DRAM. The key d ifference is thai the CAS ~ i gn a l in the EDO
DRAM does not (tisable thc outpul data when il goes 10 its nonasscrt{.'d st" te because the valid data from the current a(lclress C,1n be held unl il CAS is assert{.'(! "gain . This means thaI the next column "duress C
8£00 DRAM TIle Burst Extended Dala Output DRAM is an EDO DRAM with aJdress burst capability. R<..'Call from the discussion ofthc synchronous burst S I~AM thatlhc addrc.......... burst fcatUl"C allows up to four addresses to be intcrnally gencrat{.'(! from a single external address, which sav<""5 some access time. l11is same concept applics to the REDO DRAM. Faster DRAMs are nccdcd to keep up wilh the ever-i ncreas ing spe<..><1 of microprocessors. Thc Synchronous DRAM is one wny to accomplish this. Like the synchronous static RAM dil'Cusscd earl ier, the openltion of the SDRAM is synchronized with tbe sys· tem clock, which also rUlls the microprocessor in a computer system, The same b
READ-ONLY MEMORIES (ROMs)
I
SECTION 10- 2 REVIEW
1. U1t two types ofSRAM.
2. Wh.Jt i1 a c.)che? 3. Explain how SRAMs and DRAM1 differ. 4. Describe the
ref~h
operation in a DRAM.
5. u st four types of DRAM.
10-3
READ-ONLY MEMORIES (ROM.)
A ROM contains pcn nancnlly or scmipcrmancntly stored data, which can be read from the memory but either cannot be chan£cd at all or callnot be changed wilhollt specializcd equipmcllt. A ROM stores data that arc used repeated ly in system application!>. such as tables. conversions. or programmed instruc tions for system initialization and operation. ROMs rt.1ain stort.'tI data when the power is ofr and arc therefore nom'o lmi le memories. After completing this scction, you should be able to • Li st the IYIX!s or I~OM s • Describe a basic nmsk ROM stomgc cell . Explain how data arc rt.'tId rrom a ROM . Discus-s internal organization of a typical ROM . OiS(;uss some ROM applications
The ROM Family Figure 10-22 shows how semiconduclor ROMs arc categorizcd.1lle mask ROM is the type in which thc data arc permanently stort.'(\ in the memory du ring the manufneluring process. The PROM, or prO
The ROM family.
Read-Only M,""", (ROM)
Ma
Progr.Jmmabte ROM (PROM )
Er.l:;;lbJe PROM (E1'ROJ\H
UI1I<1 I';o!ct EPROM (UVEPROM)
EI<'Clric-.JUy Era'
The Mask ROM T he mask ROM is usually referred to simply as a ROM. It is permanently programmt.'tI during the manufacturing process to provide widely used ~tandard functions, such as popular conversions, or to pmvidc user-speci fied functions. Oncc the memOI)' is programmed, it
•
555
556
•
MEMORY AND STORAGE
cannot oc changed , Most Ie ROMs util ize the prese nce or absence of a transistor connectio n at a rowfeolumn junction to re prescm 11 I or a O. Figure 10-23 shows MOS ROM cells. The presence of a connection from a row line to the gate of a transistor represcnts a I at that location because when the row line is taken HIGH, aJll ransistors with a gate connection to that row line tum on and connect I he I-IIGI-I ( I ) to the associated column lines. A t rowfcolumn j unctions where there arc no gi.t!e connections, the column lines remain LOW (0) when the row is addressed. FI GURE lC - 13
Col umn
Cu!tl mn
ROM celli.
Row
R,,,,
--- - -t-- :;;-+-
--------:-c,---+~ +Vou
J ,J S,onni! 3 I
A Simple ROM To ill ustrate the ROM concept, Figure 10-24 shows 11 small , simplified ROM array. The blue squares represent stored Is, lind the gray sq uare:. re present stored Os. The bll.~ i c read operation is as fo llows: When :J binary :Jddress code is applied to the address input Jines,
Addro;s
tk:c,,
'Addrc,~
{
mpul tm\!\
2 --
,
Row :!
4--
8-14
Row t4
15
Row t5
o
,
6
1
,------------- - ----, FIGURE 10- 24
A represenbltion of a 16 x 8-bit ROM array.
READ-ONLY M EMOR IES (ROM J)
•
the corrcsponding row line goes HIG H. This HIGH is connected to the column lines through the tmnsistors at each junction (cell) where a I is stored. AI each cell where a 0 is stored, the colum n line stays LOW because of the terminating resistor. The colum n lines form the d ata outp ut The e ight data bits stored in the selectt.-d row appear on the output lincs. As you can see, the example ROM in Figure 10- 24 is organ ized into 16 addresscs, each of which stores 8 data bils. Thus, il is a lfi X 8 ( I h-by-8) ROM, and ils tOla l capacity is 12R bils or 16 bylcs. ROMs can be uscd as look-up tables (LUTs) for code cOllvcrsions and logic func lion gcncration.
I
EXAMPLE 10-1
Show a b
Review Chapter 2 for the Gmy code. Table 10- 1 is developed for lise in programming IheROM. TABLE 10- 1
0
0
0 0
0
0
0
0
0
0
0 0
1
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
U
0
0
U
0 0
0
0
1
0
0
0
The resulting 16 x 4 ROM
557
558
•
MEMORY AND STORAGE
to FIGURE 10_Z5
Reprelent ation of a ROM programmed <:II <:I binary-to-Gray code converter.
Address """",,
2
3 4
s B<> B i llaf)' t'tlllo: applkd 10
add.n:!>S IIlput hll~~ {
'
n, - - ,
6 7
B. - - ,
B, - - 8
8
9 10
" 12 13 14
IS
Grol} w,k ou tput
Related Problem·
Using Figure 10-25. determi ne the Gmy codc output when a binary code of lOll
j<;
- Answers arc at the end of the ,hapter.
Internal ROM Organization Most lC ROMs have a more complex imental organizatiOllthiUl (hal in the basic simplified example JUSt prescnted. To iIIustrale how an IC ROM is sfruChtrcd. let's usc a 1024-bil device with a 256 x 4 organization. The logic .~Y ll1 bol is shOwn in Figure 10-26. Whcn any one of 256 binary codes (cight bits) is applied to the address lines, tour data bils appear 011 the outputs if the chip cnable i n pu~ afC LOW. (256 addresses requi re eight address lines,)
READ -O NLY MEMOR IES (ROMi)
ROM 256x4
A 256 x 4 ROM logic symbol. The Al~1 deignawr mC
0
A"
i1ddrcss code relec::b i1ddreue 0
,1, - -
through 255.
,1, - Addl1"S.\
V
,
,1, - -
II1plll
linc~
•
Am
A.
,1, - -
O,,} lJoitu
V
01
V
O~
V
0 ,
fIIl!PUt
li ne ..
I,.
7
A,
,
&
" E,
EN
A lthough the 256 x 4 organization of this device implies that there are 256 rows and 4 columns in the memory array, this is not actually thecasc.llle memory cell ilffity is actually
Row
"',ro<>" -
" FIGURE 10-Z7
f= 1-,---
A I 024-bit ROM with
,,, ,
add ....':;~ {
,
32 x 32 Mcmvry army
32
row
,, ,, ,
linL'lO
A, A
Colum n tlccotlcr.;
(f"Our l-of-8dcoodcn;) and 110 circu;ts
I>
A,
Chi ll {," enable 1.1
256 x 4
32 x 3Z
i1rTay.
I-'Column
iI
organiZiltion hased on iI
r-
r-
r-
0,
0,
0,
C-
"", 00"
P"'
'"
0"
The ROM in Figure 10 - 27 works as follows: Five of lhe eight addre:;s lines (Ao through A4) are decoded by the row decoder (oflen called the Ydecoder) to select one orthe 32 rows. nuee of the eight address lines (A s th rough A7) arc decoded by the column decoct four of the 32 coluillns. Actually. the column decoder consists of fou r l-of-8 decoders (data selcctors), as shown in Figure 10-27. The result of this structure is that when 1.111 8-bil address code (Ao through~7 ) is uE,plicd. a 4-bil data word appears on the data outputs when the chip enable lines (Eo and E I ) arc
559
560
•
MEMORY AND STORAGE
LOW to enable Ihe output buffers. This type of intcrnal organization (architecture) is Iypical of Ie ROMs of variou!; capacit ic!;. ROM;' u.ed in a pe. ~"", computet to Itore the BIOS (Sdsic Input/Output System). ThC\e are progt"arrn that arc uied topeofoom fundament;ll For example, programs stored in the ROM control cerbin video monitol functions. provide for di.k formatting. Kan the ke)OOard for input!, and control certain printer functioOi.
ROM Access Time A lypical timing diagram that illustmtes ROM acees!; li me j!; shown in Figure 10-28. The access time, I", of a ROM is the tilllc from the application of a valid ;:K1dress code on the illpUl lincs unt.il the <1ppcamncc of valid output data. Acccss lime Can also be measured from the activation of the chi p cnable (£) input to the occurrencc of valid output data when a valid address is already Oft the inpul lincs. FIGURE 10 - 28
ROM ac:cess time (t~) from address change to data output with chip enabte a Iready active.
ChiP~n:.hl<' :-\L
I
SECTION 10-3 REVIEW
_ _ _ _ _ _ _ _ _ _ _ __
1. What il the bit ltorage capacity of a ROM with a 5 ' 2 x 8 organization? 2. list the types of read-only memories. 3. How many addreu bits are required fOf" a 2048-bit memory organized as a 256 X 8 memory?
10- 4
PROGRAMMABLE ROMs (PROMs AND EPROMs) PROMs arc basically the same as mask ROMs. once they have been progrnm rned. As you h:l\'c Icarned, ROMs are a type of progrnmmablc logic dcvicc. The difference is lhat PROMs come from the manufaclUrer unprogmmmed and are CUSlom progrnmmed in the field to meet thc user's m:cds. Anercomplcting this seetion, you should be able to • Distinguish between a ma..k ROM and a PROM . Describe a ba~ic PROM memory cell . Di scuss EPROMs including UV EPROMs and EEPROMs • AnalYlc an EPROM programming cycle
PROMs A PROM uses some type of fusing process to store bits, in which a memory link is bUrlu.'d open or len intact to represent;:1 0 or a I. The fusing process is irreversible; a liCe a PROM is programmed. it t:annot be changed.
PROGRAMMABLE ROM, (PROM, AND EPROM,)
•
56 1
Figure 10-29 illustrmes a MOS PROM array with fusible links. The fu sible links arc manufactured into the PROM between the source of each cell's tmnsistor and its column line. In the programming process. a sufficit'nt curre nt is injected through the fusib le link 10 bum it opcn to create a stored O. The link is Icn intact for a stored I. FIGURE 10- 29
r
Three basic fu se technologies used in PROMs arc metal links, sil il.:on links. and IJ/I junctions. A bricf dcscription of each o f thcsc follows.
t. Melallinks are made o f a material such as nichrome. Each bit in the memory rnr.ly is l"Cprcscnted by a f\Cpa ralC link. During progmmmiog, the link is either "blown" opcn or left intact Thi s is done basically by first addressing a given cell and then forcing a sufficient ,lmoulll of current through the link to cause it to open. 2. SilicHn links are formed by nUITQW, notched strips of polycryslalJine silicon . Pro;;ralllJlling of these fuscs relJuires melting o f the link:; by passing a suffic ient amount of currcnllhrough them. This amount of Cllrrent causes a high lemperature al the fuse location thai oxidizes Ihe silicon and forms an illslIialion around the now-ope n link. 3. Shoned jUlll.:tion, or ilvalilnche-indul.:cd migration, tcchnology consists basically of two 1)/1 junctions arranged back-ta-back. During progmmming, one of the d iode junctions is avalanched, and thc rcsulting voltage and heat causc aluminum ions [0 migrate and shan Ihe jUllction. The rcmainingjunctioll is then used as a fo!wardbiased diode to represem a data bi t.
EPROM, An EPROM is an era!;able PROM. Unlike an ordinary PROM. an EPROM can be reprogmmmcd if all cxisting progmm in the mcmory arr.l)' is cr.l..;;cd first. An EPROM uses an NMOSFET array with an isolatcd-gate struclUre . Thc isolated tr.ln!;istor gate has no electrical conncctions and can store an electrical charge for indclinitc pe_ riods of time. The data biLS in this type of array an: represclllcd by the prescnce or abscuce of a stored gate charge. Erasurc of a data bit is a process thai removcs Ihe g:ltc charge.
M05 PROM ;uray with hllible lioks. (All drilim ilre commooly coonected to Voo .)
562
•
MEMORY AND STORAGE
Two basic types o f er.t.'iablc PROMs arc the ultraviolet erasable PROM (UV EPROM) and the electrically erasable PROM (EEPROM). You can recognizc thc UV EPROM device by the trnnsparcnt quat1z lid on the package. as shown in Figure 10-30. Thc iwlmcd gatc in the t' ET of an ultraviolet EPROM is "floilting" withi n all ox ide insulating material. The programming process causcs elcctrons to be rcmoved from thc flOi.lt illg gate. Erasure i .~ dOlle by exposmc of the memory array chip to high-intensity ultraviolet mdiation through the quartz wi ndow on top of the package. The positive charge storcd on the gate is ncutralized aftcr several minutes to an ho ur of exposure time. UV EPROMJ
FIGURE 10- ]0
Uttraviolet efMab'e PROM package.
A typical UV £PROM is reprcsclltl:d ill rigure 10-31 by a logic diagram. Its opcmtioll is represcnt ativc or that of other typical UV EPROMs of vru'ious sizes. As the logic sy mbol shows. this device bas 2048 addresses (2 11 = 2(48). each with cight bits. Not ice that the eight outputs arc tristate (V). FIGURE 10 - ]1
EPROM 2(48)( II
The logic symbol for a 2048 x 8 IN EPROM. 0
V
",
V V V
A~
V V V
- --
V
10 Cf:tPGM
L
&
EN
OE
To read from the mcmory, thc output CIli.1b1c input (OE) must be LOW and the powerdow nlprogmm (CE/ PCM ) input LOW. To eTi.lse the stored data, the device is exposed to high-intcnsity ullraviolct light through the transparent lid. A typical UV lamp will Crdse the data in about 20 to 25 mi nutes. As in most UV EPROMs after erasure, all bits arc Is. Normal i.Ullbicnt light con t ai n.~ thc correct wavelength of UV light for craslI"C ovcr a period o f time. Therefore. the transparent lid on the package must be kept covcred. To pmgri.lm the device, a high dc voltage is applied to V I'!' and OE is I-IIGH. The eight data bils to be progmmmt:d into a given address are applied to the outputs (00 through 7 ) ,
°
FLASH MEMORI ES
•
563
and the address is selected on inputs Au through A n,. Next, a HIGH level pulse is applied 10 the CEj PGM input. The ad dre.~ ses Gin be progmmmed in an y order. A limingdiag....lffi for the programm ing is shown in Figure 10-32. These signals are normally produced by an EPROM progmmmcr. FIGURE 10- 1Z
Tim ing d iagra m for a 2 048 )( 8 UV
,1
"
1
OE.
1__ " 'h_ ~
---.../ i'"
1
,----'"r'-- '1
,' 1
CE.IPGM
EPROM programm ing cycle. with critical letup times (t,l a nd hold
Y:
:
: - ',"II'f" ---'
1 1 : 1
1 1 . 1 1 1 1 1 1 / ",l> 1 1 ' 1-
) i,,
' - - '.\0'\'_1 1
I :
~
times (tJ indiC
1
:-'h"" ~ ~-----
'\(::W)~ : 1 1
I
1 I
1
1 1
, 1 1 1
:
--~
,, ,:r----c °tr°1_____ V DC"C"C"-'---~X , _ ~ be JlIT'!!.rnmnlCtl ill . J
c
_
_
_ _- '
EEPROMs An clt.'Ctrically em.<:able PROM can be both erased and programmed with electrical pulses. Since it can be both electrically written into ill1d electrically emsed, the EEPRO M can be r'lpidly progmmmed and erased in-circui l for reprog ramming. Two ty pes of EEPROMs arc the noaling-galc MOS and the metal nitridc-ox idc silicon (MNOS). T he applic
1. How do PROM} differ from
ROM~?
2. After erasure, all bits are ( 1 ~. Os) in
10-5
FLASH MEMORIES
The ideal memory hm; high storage capacilY. nonvolalility, in-system read and wri te capability. compara ti vely fas t opcrmion. and cost effectiveness. The tr.lditional memo!}, technologies such as ROM, PROM. EPROM , EEPROM. SRAM. ,md DRAM ind ividually exhibit one or more ofthc.'>c chamcteriMics. but none of these technologies has all of the m except the flash memo!}'. After completi ng thi s section, you should be able to • Discuss the basic chamcteristics of a flas h memu!}, • Descri be the basic opcrmioll of a fl ash memo!}' cell • Compare fl ash memories with other types of memories
564
•
MEMORY AN D STORAGE
Flash memories arc high-densilY read/write memories (high-dcnsity tra nslates inlO large bit stomge capacity) that are nonvolatile, which means that data can be slored im1cfinitely withoul power. They an; someti mes lls(:d in place o f noppy or small-capacity hard disk drives in portable computers. High-<.lensilY means Ihat it large number of cel ls can be packed into agivcn surface area on achip; thaI is. Ihe higher the density. the more bits that can be stored on agiven size chip. This high density is achieved in flash memories wilh a storage CClllhat consists of a single noating-gate MOS tmnsistor. A data bil is stored as charge or the absence of charge o n thc !loating gate depending if a 0 Of a I is stored .
Flash Memory Cell A si ng le-tmnsistor cell in a tla<;h memory is re presented in Figure 10-33. The stacked gme MOS transistor consists of a conlrol gate and it floating gale in llddition to Ihe dmin mtd source. The floati ng gale stores electrons (charge) as a resu ll of a sufficient voltage applied to thc control gale. A 0 is stored when Ihere i.~ more chargE and a I is Slored when Ilzere is less or no charge. The amOlllll of charge prcscnl on Ihe Iloating gate determines if the trAnsistor will tum on and conduct current from the drain 10 lhe source whe n a control voltage is applied duri ng a rc,:ld operation. FIGURE 10- 13
l; hMI ,"~
l;.Ilc
The lto""ge c:e/I in a (lalh memory.
'"'" "'I~
Drain
Cnnlml \
I
MOS Imn~i~tor
symbl)l
Source
Many declrons :: more ch:lf~c = Moret! O.
-+
~
F'ew cle<:lmns::
k'!ls charge:: '\IO«.·d t.
Basic Flash Memory Operation There arc Ihrt.'C major opemtions in a flash memory: the pro!V(lllJIlliIlK opcralion, the re(I{1 opermioll, and the erme opcmtion. Inill.(llly, al l cells '1f'C al the I stme Ix:callse charge was removed from eaeh cel l in a previous erase operation. The programmi ng opcml ioll adds electrons (ch;:lrge) to Ihe fl oating gale of those cells thilt are to store a O. No charge is added to th use cells that arc to store a I. Application of a sufficienl positive voltage 10 the control gate with respect 10 the source during programming attracts clectrons to the !loati ng gate, as indicalt.'d in Figure 10 - 34. Oncc progmmmcd, a cell call retain the charge for up to 100 years without any external power. Programming
Read DUling a read operation. it positive voltagc is applied to the control gate. The amount of charge present on Ihe floating gale of a cell delermi nes whether or not the voltage applied 10 the control gate wi llltlTII 011 the transistor. If il I is stored. the control gate vol tage is sufficient to tum the tran ~islor 011. If a 0 is stored, Ihe transistor will 1101 \lim Oil because the control gate voltage is not sufficient to overcomc the negative charge stored in the Ilooting gate. Think of the charge on the Ilooti ng gme as a vult0.\2C source that opposes Ihe VOltage applied to the control t;ale du ring a read oper-liion. So the noating gate charge associaled with a stored 0 prevents the comroJ gate voltage from reaching the turn-on
FLASH MEMORIES
•
565
FIGURE 10 - ]4
Simplified ili ud:l<'ltion of storing ~ 0 OT;3 1 in ;3 ff;3Jl1 ce ll during the progr;3mmin g oper~tion .
ee e e IlV
To SIOI"C a O. a sufTicicm positive vollage is applied 10 the ClJlllrul gate with ~pecl to I~ soum: [0 ao:Jd char,;c [0 rhe floating gale during
To ston: a I. no charge is adtktl and the cd l is left in the era.o;ed colldi.ioll.
rrogramming.
threshold, whcrcm. the small or zero charge a'\sociall.'(\ with a stored I allows the cont rol gate volta2c to exceed the tllrn-on Ihrcshold. When the transistor lurns on, there h. current from the dl",Jin 10 the source of Ihe cciliransistor. The presence of this curre nt is sensed to indicate a I, and the absence of this cum:nt is scnsed to indicate a O. This basic idea is il1uslr.llcd in Figure 10-35 . FIGURE 10- ]5
The
",-'"'11 I
Hoalllll! !! ill,'
nv
Il\
When 3 0 i~ read. ,h.. Ir.ln~;~ror rt:n",i n~ "rr bo!call'.C the charge on the flootin,g gale pre"Cllls
[he read
"ol~gc
from excced ing The tum-Oil
th,'cshold.
When 3 1 is read !hl' lrnnsiswr turns on bccau.'iC the abscnC\' of charge on the noruing gale al lows the .ead ,·ollage 10 e»cecd Ihe Illm·QIl threshold.
Erase During an cmse operation. charge is removed from all the memory cells. A sufficient positive voltage is applied to the tr.msistor source with respect to the! cOnlrol gate. This is opposite in polarity 10 Ihat used in progmmming. This voltage attmcls electrons from lhe floating gittc and depleles it of chargc. a... illusll'
ov
-1
re~d
an array.
Simplified illustration of removing charge from;3 cell du ring el<'lse.
88
e e e
+IH!->'~L
To crmc a ce ll . a stlfTiClem p<)Sili--c ,"oltage is applied lethe source wilh n...~1 10 tbc COrltro/ gale 10 rclllO'-e cl"laq;c from lhe fleming gale during lhe erose flpero lion_
oper.loon of ~ f);3.h cell in
566
•
MEMORY AND STORAGE
Basic Flash Memory Array A ~ implifie
+V
+V
A.:ti,·" lootl - -- --- - - - - - -- - - ----- --- - --- ---
D:'I~ "UI U
D:'M nUl
m
COnlpa l1>lor
Rc:fcrt n.:c:
Hilhn"(}
BilJinc:m
~ RUII ",,[.,.,:1 ()
---------- - - ~
:
----------- ~
:
----- - ------- ~
:
~
0-+-1
C"IUIl. n -.ck"l;1 Q
C"]Ulllll -.cllXllII
FIGURE 10-37
Basic flash memory arr.ly.
The memury stick is a stol"
Comparison of Flash Memories with Other Memories Let's compare flash memories with other types of memories with which you are already fami liar.
fl AS H MEMOR IES
VJ. ROM, EPROM, and EEPROM Read-only memories arc high-density. nonvolatile devices. However. once programmed the contents of a ROM ean never be altered. Also. the initial programming is a time-cnnsuming and costly proce~s. Ahhough the EPROM is a high-density, nonvolatile memory. it can be erased only by removing it from the system and using ultraviolet light. [t can be reprogrammed o nly with specialized equipment . The EEPROM has a more complex cell structure than either the ROM or EPROM and so the density is not as high. although it can be reprogrammed without being removed from the system. Because of its lower density. the t:ostlbit is higher than ROMs or EPROMs. A flas h memory can be reprogrammed ea~ i1 y in the system because it is essentially a READ/WRITE device. The de nsity of a fl ash memory compares with the ROM and EPROM because both have single transistor cel ls. A fl ash rncmory (l ike a ROM, EPROM . or EEPROM) is nonvolatile. which allows data to be stored indefi nitely with power off.
Flash
As you have learned. static random-access memories are volali le READ/WR ITE devices. A SRAM requi res conslant pOwer 10 retain the slored data. In many applications. a battery backup is used to prevent dma loss if the main power source is turned off. However, since battery fai lure is always a possihi lity, indefinite retention of the stored data in a SRAM cannot be guaranteed. Because the memory cell in a SRAM is basically a flip-flop consisti ng of several transistors, the density is relatively low. A flash memory is also a READIWR ITE memory. but unli ke the SRAM it is nonvolatile. Also, a flash memory has a much higher den~ ity than a SRAM . Flash vs. SRAM
Rmh vs. DRAM Dynamic random-Ilcccs.'l memories are volatile high-density READ/ WRITE devices. DRAMs require not only consfanl power to retain data but also that the slOred uata must be refreshed frequently. In many applications. backup storage such as hard disk must be used with a DRAM. Flash memories exhibit higher densities than DRAM ~ becau ~e a flash memory cell con.'l ists of one tran.'l islQr and does not need refreshing, whereas 11 DRAM cell is one transislOr plus acapaci lor Ihat h a~ 10 be rcfrc.~hed. Typicall y, a fl ash memory consumes much less power than all equivalent DRAM and can be used as a hard disk replacement in many application!>. Table 10-2 provides a summary of the comparison of the memory tcchno log i c.~ .
TABLE 10- 2
Compariwn of type< of memories.
NONVOLATILE
HIGH· DENSITY
ONETRANSISTOR CEll
IN-SYSTEM WRITABlllTY
Flash
y"
y",
Yes
Yes
SRAM
No No
No
No
Yes
DR AM
Yes
Ye~
Yo.
y" Yc.<;
No
No No y",
MEMORY TYPE
RO M
Yes
EPROM
y"
Yes Yes
EEPROM
Yes
No
•
567
568
•
M EMORY AND STORAGE
I
SECTION 10- 5 REVIEW
1. What typ6 of memories are nonvolatile?
2. What is a major advantage of a flash me mory over a SAAM or DRAM?
3.
10-6
li~t
the three modes of operation of a
fla~h
memory.
MEMORY EXPANSION Available memory ean oc expanded to increase the word length (numocr o f bits in each addresSJ or the word capacity (number of different aJdrc~scs) or both. Memory expansion is accomplished by adding an ap propriate number of lllelllOlY chips to the address. data, and contml buses. SlMMs, DLMMs, and RIM Ms, which arc types of memory ex p.'lnsio n modules, arc intnxl uccd. After completi ng this S(.>Ction, you should be able to • Defi ne wurd~/e"g th e.\7Jllllsinn • Show how to expand the word le ngth of a memory • Define word·ClIpacity expa/lsion • Show how to expand the word capacity of a memory
Word-length Expansion To increase the word length of a memory, the number o f bits in the dala bus must be increased . For cxample. an 8-bit word Icngth can be achievcd by using two mcmories, each with 4-bit words as illustrated in Figure 10-3R(a). As you can f'CC in pal1 (b), the Iii-hit address bus is commonly connected to both mcmories so that the combi nation memory still has the same number of addresses (2"' = 65,536) a... each individualmelilolY. The 4-bi t data buses from the two memori es arecombincd to form an 8-bil data bus. Now when an address is se lected, eight bits arc produced on the data bus -four from cach memory. Example 12- 2 shows the details o f 65.536 x 4 to bS.53() x 8 expansion.
65.536 x 8 Address 1(, bi t$
00'
ROM
Add re!
('s,536 x 4 4 bit s
[}dla
bus
COinroL b.,
A
ROM 6.~,536
x4 4
Conlrol
"'"
bi l~
Dat~'
OM I
D
4 t its
Coolrot
"'" 16 bits
L6 biN
16biu, DOM 2 4bi13
""'
(a) T wo M"pi1r~ Le 6..~ .536 x 4 ROMs
8 bits
(b) One 65536 x 8 ROM from
t \.\'O
65,536 x 4
ROM~
FIGURE 10- 38
Expamion o(two 65,536 x 4 ROMs into a 65,536 x 8 ROM to iJlustrate word-length expansion.
MEMORY EXPANS tON
I
•
EXAMPLE 10-2
Expand the 65,536 x 4 ROM (64k x 4) in Figure 10-39 to fo ml a 64k x 8 ROM . Note that "64k" is the accepled shonhand for 65.536. Why not "65k"? Mayoc it'!; because 64 is al!;o a power-of-two. ,
FIGURE 10- 19
,'"
A 64k x 4 RO M.
ROM
Mk x 4
,
A ~_'lJ'
Add~,~
_O "}
-
01
_ o~
Dnl3
nUlp4.l1
0 ,
A"
Solution
MEN
10) if
Olip { t mlbk
"
Two 64k x 4 ROMs are connected n!; ~ hown in Figure 10-40. Not icc thaI a specific address is acccssed in ROM I and ROM 2 at the same time. The four bits from a selected address in ROM I and the four bits fro m the corre:;;ponding address in ROM 2 go o ut in parallel t~form an R-bit word on the data bu!;. A I ~o notice thai a LOW on the chi p enable line, £, which forms a simple control bus, enables bolh memories . A"
ROM 1
~
A
~
'
f>.'-!Il'
-
-< >-<
=
&
lJ
On
0,
EN
0,
ROM 2
0;
I)~I ..
o~
bu_
0,
0;, 0,
A
Cuntrol
tu,
E
>-<
&
'
~'"'
-
r
fi
FIGURE 10- 40
Related Problem
I
Describe how you would expand a 64k x I ROM to a 64k x 8 ROM .
EXAMPLE 10-3
Usc the memorie!; in Example [0-2 to form a 64k x 16 ROM. Solution
In this case you need a memory that Siores 65,536 16-bil words. Four 64k x 4 ROMs are rcquircd to do thc job, a<; shown in Figure 10-4 1.
569
570
•
MEMORY AND STORAGE
~" :
16 bits
A" 16 bils
ROM 1 Mk)(4
16bilS
ROM 2 64kx4
."
Control
M,
EN
ROM'
~
MEN
16 bits
64")(4
4 bili;
4 bils
~
16 bits
ROM 4 64k >< 4
,
4 bils
~
~ " l EN
bil~
"l'
EN
tcnabl",
16 bi ts
(}'na ",,-,
FI GURE 10- 4 1
ReliJted Problem
How many 64k x 1 ROMs would be required to im plement the memory shown in Figure 10-4 1?
A ROM has only data outputs, but a RAM has both data inputs and data outpuL<;. For wI,rd-length expallsion in a RAM (SRAM or DRAM), the daw inputs and data outputs form the data bu~. Because the saine lines are used for data input and data output, tristate buffers arc required. Most RAMs provide intemallristatecircuitry.FiI;urc 10-42 illustrates RAM expansion to increase the data word length. FIGURE 10- 42
RAM }III x 211
lUustration o f word- length expamion with two 2'" x n RAM, fo rming a 2'" x 2n RAM.
m bits
RAM I /II
bill.
RAM 2
III bils
i" , "
2"')("
V
V
Data
Data
in/ou t
" bits
infoul
"
bit~
Comrol
""
, EXAMPLE 1 0-4 Use I M Solution
Relnted Problem
x 4 SRAMs to create a iM
x 8 SRAM.
Two I M x 4 SRAMs arc connected as shown in the simplified block diagram of Figure 1()....43. Use I M x R SRAMs to create a 1M x 16 SRAM.
MEMORY EXPANS I ON
r~"" OO~
C' : ;
A"
-
':, O}SRAM I 19
"
'-<
,,",
tftJl!.' H
'-< V Data V 110 V V
comn'l{
O}SRAM2
A -'~
A -'~ tJlolClU
V Data \1
-
110 V V
r---
r--
"", E
Data ,,",
~
fiGURE 10- 43
Word-Capacity Expansion Whe n memo ries are expanded to inc rease thc word capacity, the number oj Olltlreues is increaself. To achieve this increasc. the number of address bits must be incrca"cd. a" illustrated in Fig ure 1()..44, (where two 1M x R RAMs are cxpanded [0 form a 2M x 8 memory). Each indi viduaimcillory ha~ 20 addrcs... biL" to selec t its I ,(}4R,576 addrc."SCs. as shown in pm1 (a). 'The expanded memory has 2,097.152 addresscs and therefore requires 2 1 address HOM -'M x II
\dtJ~:
20 bif!;
RAM IM )( II
RAM 1 tM )(1I
20 bi ~
EN 8
bil~
Cunlwl
COlllf,,1
""
"" 20 bils
II bils
RAM
2Ubils
IM x8
8 bits
(a)
II bilS
I ndi vitlu~1 mcmoric~
each ... Io re 1.()..I1I.576
lI_bi. words
FIGURE t 0 - .4
illustratio n o f YofOrd--capacity expa ruioo .
L(>o-<
RAr.·I~
IM )( 8 EN
II
bi l~
Ibl Memuries expanded to form a 2M )( 8 RAM rt.'Guiring a
21-bit ad<1ress bus
•
571
572
•
MEMORY AND STORAGE
bil'i, as shown in pan (b). The t wen ty-fir~t address bit is used to enable the uppropriate memory chip. The data bus for the expanded memory remai ns eight bilS wide. Details of this expansion arc illustmled in Example 10-5.
i
EXAMPLE 10-5 U~C
Solution
A
5 12k )( 4 RAMs 10 implement a 1M )( 4 memory.
The expanded addressing is achieved by connecti ng thc chip enable (Eo ) input 10 the twcntieth address bit (A I9), as shown in Figure 10--45. Input EI is used as an enablc input common to bOlh memories. When the Iwenl.ieth address bit (AI 9) is LOW, RAM I is selected (RAM 2 is disabled), and thc ninetcen lowcr-order address bits (Au-A IS) access each of the addrcsses in RAM I. When the twentieth address bit (A 19) is HIGH, RAM 2 is enabled by a LOW on the in\'eller output (RAM I is disabled), and the nineteen lowcr-order addrcs." bits (Au-A IH) access each oflhe RAM 2 addresses.
"
:
RAM 1
,,
,
,
v
A-524.W "- "V f---
vr-
A A
"
E
", flEN
"
E
/)110 D/IO"} 1
0110,
DIIO~
RAM 2
, ,,
A
4-b,[ daTa ' -
~:z.uJj8
U)4iU15
VrvI---v v
f'Comrol
V
bus
"" "l EN /-;1
FIGURE 10- 45
Related Proble m
What arc the ranges of addresses in
I~AM
1 and in RAM 2 in Figure 10-45?
Memory Modules RAMs are commonly supplied as single in-line memory modules (SIMMs) or as dual inlinc memory modules (DI!\.·IMs). S IMMs and D1MMs are small circuit board.~ on which memory chips (Ies) are mounted with the i npul~ and outputs connected to an edge connector on the bottom of the board. DIMMs arc generally faster, but thcy can only be installed in machines that
MEMORY EXPANSION
o
"WW,WN" ,
•••• _
-
•
"
....'..'1"...' .."",11 · ..,,;,\,,'......"~
-- .-... .......
.. .. ..
..
•
L
•
S73
FIGURE 10- 46
30-pin clnd 72-ptn SIMMI.
~
Dl MMs look similar fO SIMMs bul provide an increase in memory density w ilh only a relatively dight increase in physical size. T hc key difference is that OIMMs distribute the input and output pin!i on !xllh side!i of the PC !xlard. whereas SIMM!i usc only onc !iide. Common DlM M configurations arc 72-pin, 1000pin, 144-pill, and 168-pin thai m:cummudalc bOlh 32-bit and 64-bit dala paths. Generall y, DI MM capacities range fro m 4 M I3 to 5 12 MB. SIM M!i and DIMM!i plug intu socket!i on a system board such as those ill ustrated in Figure 10-47 where several ~kel s arc generally available for memory expansion. The sockets fo r SIMMs and DIMMs, of course, are differe nt and not interchangeable. Another slandanl memm)' module, simil ar to the DIMM but with a higher !ipccd bus, is the RI M M (ntmbus in-line memory module). Also, many laptop computer.; use a variation of lhc Dl MM called the SODlMM, which is smaller in size. hac; 144 pins. and has up \0 a 256 MB capacity. FtGURE 10- 47
A StMMfOIMM is inlerted into a
o
ANDS • N
-
lOCket o n .11 l)'Item bo.Jrd.
Memory components are extremely 'Iemitive to static electricity. Use the following pre(.autiom when handling memory chipl or mod ul~ such a5 SIMM.I and DIMMs: Befo re handling. discharge your body'5 static charge by touching a grounded surface or wear a grounding wrist strap containing a high-va lue resistor if available. A convenient. reliable ground is the ac outlet ground. Do not remove components from their antiltatic b,;,gs until you are ready to install them. Do not lay part! on the antistatic bags because only the inside is antistatic. When handling SIMMs or DIMMs, hold by the edges or the metal mounting bracket Do not touch components on the boards or the edge connector pins. Never slide any part over any type of surface. Avoid plastic, vinyl, styrofoam, and nylon in the \.VOrk area . When installing SIMMs or DIMMs, follow thee 'Itepi: 1. line up the notches on the SIMM or DIMM board with the notches in the memory socket 2. Push firm ly on the module until it is recurely seated in the socket 3. Generally, the latches on both sides of the socket will snap into place when the module is completely inserted. These latche.l also releare the modu le , so it can be removed from the socket.
574
•
MEMO RY AND STORAGE
SECTION 10 6
1. How many 16k x 1 RAMs are required to achieve a memory with a word capacity of 16k and a word length of eight bits?
\ REVIEW
2. To expand th e 16k x 8 memory in question 1 to a 32k x 8 organizaticn, how many more 16k x 1 RAMs are required? 3. What does SIMM stand for?
4. What does DIMM stand for? 5. What does the term RIMM stand for?
10- 7
SPECIAL TYPES OF MEMORIES In this section, the first in- first out (FLFO) memory, the la~t in- first out (LIFO) memory, the memory slack. and the charge-cottplctl device memory arc covered . After completing this section, you should be able to • Describc a FIFO memory _ Describe a LIFO memory _ Discuss memory slacks
• Explain how to usc a port io n of RAM as a memory stack . Describe a ba<;ic CCD memory
First In-First Out (FIFO) Memories This type of memory is fomled by an ilrmngcment of shift registers. Thc telm FIFO re fers to the basic operation o f this type of mcmory, in which the fi rst data bit written into the memory is thc rust to be read out. One important difference between a convent io n al .~ hift register and a FIFO re<.;i~ t cr is ilIU ~lratcd in Figure 10-48. In a conventional reg i ~ter. a data bit move~ through thc register only as new data bitS are entered: in a FIFO register, a data bit immediately goes through the register to the right-most bit location that is empty.
Conventronal shift regilter Inpo'
o u
1 X 1 X I X 0
0
I
X
x
X
X
0
X
X
0
X
FIFO shrft reg'lter
Input
1 00tpo,
--
-
I-
0
I-
0 0
--
0
I
0
0
0
I Output
---
X ", unknown daTa bils.
-
]n II conventional shift register. dat a SIlly 10 lhe lef. unli l" forccd" through b) additional rulta.
tn " FIFO .' hill re<,;iSlef, dona 'f:lll"' through (go right).
::: elllpty poiI iliolls.
FIGURE 10- 4'
Comparison of conventional and fiFO register ope.-ation.
Figure 10-49 is a block diagram of a firO serial memory, This particular memory ha.. foor serial 64-bil <.lata registers and a 64-bit control register (marker register). When data arc entered by a shift-in pulse. thcy move automatically undcr control orlhe marker register to the cll1pty location cJosestto the output. Data cannot advance into occupied positions. However, when a data bit is shifted out by a shift-oul pulse, the data bits remai ning in the
SPECIAL TYPES OF MEMOR IES
•
fIGURE '0 -'"
MclTJUl) affil) ,to....... data IU)nj,
/ ' (H ~-hit
Block diagram of a typical FIFO lefia J memory.
(H-hlt shi ft reg iSlcr
(}.ilil
in~tI {
= -
'< I ,: I,
{H- bi' shirl Input bulTL'Tl>
rcgi~lI: r
Out~'t
bufler
(M-bit shift ret;iSl.cr
Cl1ntrol lir>e, Inpul n:ady tin ,
Shirt in (S/)
-
,/ Inpul cuntml
IOCic
'-
/ ' Comrol li ncs
MaTher regi ster and
~ontrol~
o<} = = 0, O~
Datu nutptH
0,
M -bil shi ft register
~1 O,aput cont rol
logic
-
Output ready tOR) Sh,ft uut (SO)
registers automatically move 10 the next posilion toward the o utput 111 an a<;ynchronous AFO. data are shifted out independent of data entry. with the usc of two separate clocks.
FIFO Applications One imponam application area for the FI FO register is the case in which two systems o f differing data rales mllst communicate. Data can be e mered imo a FIFO register at one rate and taken out at another mle. Figure 10-50 illustrates how a FIFO register might be used in these situations. f IGURE to - S o (OIl lrn..llu]ar telemetry dllta t::ln be ,tored a nd retransm ittoo a' a conslmU ..... te.
_re_g_i~_'~_---,I_ Hip.ht:r·llltc d:u..
Lo ,llcr ...Jtc Jat .. - lL_ _"_FO _"
(b) I>,\tll input lit 1\ slnw kcyhoord rate call be stored and thell Imnsferred :'1 a higher rale lor processi rl!!:.
fiFO register
~_ Hul).( dna
(c) Oara inPUI aI a COIl
fi FO ft'gistcr
575
~ COlN~nHme ru.l:l
Cd ) Dlita in bursts can be 'fOfCd lind ft'fOrmalfCd ime 3 Constan t-mte output.
last In-First Out (UFO) Memories The LIFO (last in- fi rst out) me mory is found in applications involving microprocessors and other computing systems. It llilows data 10 be stored and then recalled in reverse order: that is. the Illst data byte to be stored is the first data byte ]() be retrieved. Register Stacks A LI FO memory is commo nly referred to a.~ a push-down ~taek . In some systems. it is implemented with a group of registers as shown in Figure 10-5 1. A slack can consist of any number ofregislers, butlhe register at the top is ca lled the IOP-Ofj'ICfCk.
Examples of th e AFO rcgiltcr in d.. ta-rate buffering applicationl.
576
•
MEM ORY AN D STO RAGE
FIGURE 10-51
·· .. .. .. · ...
I!!!!!!!
I I I I I I I I
I lI!hn~islcr
To ill ustrate the pri nciple, a byte of data is loaded in parallel Ol1to the top o f the stack. Each successh'e byte pushes the previous one down into the next regislCr. This process is illustr.lted in rigure 10-52. Notice that the new data byte is always loaded into the top register and the previously slored bytes are pushed deeper into the stack. TIle name pllsh-dow/! stack comes from Ihis characteristic. FIGURE 10- 52
FirM d:IU' h}1 ~ p.~"""'d omu ~1'Kk
I 0 0
Simplified iUulbation of pulning data
I
0 0
I
Second d:l'" hylt" pusht.'d onlo , tad.. J I I I 0 0 0 0
I
jjjj jjj
onto the Itack.
1 0
o
1 0
o
jj jj
1 1
n,ird (lata bylC pushed 01110 M'O<;1..
n
I
0
I
0
I
()
I
I
j
1 1 1 1 0
o
0 0
010 1 0
1 0
I
o
I
I
1 1 1 0
o
0 0
1
o
o
1 1
0 010
I
1 0
0
I
!II!!!!!
!!!!!Il!
11 11 1 1 1 1 1
I I 'I I I I 1.1 I
Il!llll!
1 111111 1 1
Data bytes arc retrieved in the reverse order. The last byte entered is always althe top of the stack, so when it is pulled from the stack. the other bytes pop up into the nex t hi gher lucations. 11lis process is illustrated in Figure 10-53. FIGURE to-53
Simplified ill ustration of pu lling data from the It'Kk .
I nili ~lI ) ~Ioring
J tlm 3 byte...
n il' la" b)l<' in i ~ " I lup-(.OI~ "tad...
o
I 0
I
0
I
t t o 1
0 I 0 1
1 I
I
I
1 0
o
1 0 0
0
J
I
t
t t
o
1
1 1 1 1 0
o
0
I U 0 I 00 1 I
t t t
0 0
After th in.! b) 1<' is pu lled rrom ' Iad (, Ihe 'L..."OI ..... h) l<' thJI W:l' s!on."d JX'P' up 1(1 Ihe lop ·of st:ld:.
I
I
I
0 0 0 0
t t
t t o
0 0
A fk .. \!'"C{lnd h) le is pulled
frum ~t:..:\... II ... !irsl b~c that lI"a, stOl"ed POP'> up 10 th(' top-ur· ,md :. 100 IOU , I
t
t t t
1 0 010 0 1 1
1 I 1
. . . .. . I I I I I I II 11111111 1
iii Iii j I IIIIIIU I
t
iii iii
I
i
111111111
RAM Stach Another approach 10 UFO memory used in microprocessor-based systems is the allocation of a section of RAM as the Slack rather th~n the usc of a dedicated set of registel"li. As you have seen, for a register Slack the data moves up or down from one locution
SPECIAL TVPES OF M EMORIES
to the nexL ln a RAM stack. the datHiL<;elfdoes not move but the top-of-stack moves under control of a register called the stack pointer. Consider a random-access memory that is byte organized- that is, one in which eHch address contains eight bits-a~ itl ustmted in Fi,gure 10-54. Th~ binmy address OOOOOOOQ(X)()() 11 11. forexamplc. can be written as OOOF in hexadecimal. A 16-bit .address can have a m inimllm hexadecimal val ue of 0000((, and a maximllm value of FFFF I6 • With I hi ~ notatio n. a64 kB memory army cftn be rcprese nted as shown in Figure 10-54. The lowest memory address is CXlOO (6 and the highest memory address is FFFF I6 · 16 -l>lt add ...." Ihex:lo(\('cima l)
""" U~ I
FIGURE 10- 54
Reprelentation of a M kB memO<)' with the 16-bit addreue expressed in hcxad ecim
"~2
um
""" = "'" 11007 FFPJ FFFA
fJ-rll
F1-l'C IFrD fFFF
Now. consider a section of RAM SCI aside for use as a slack. A special separale register. the stack pointer. contains Ihe addres!'> oflhl: top or lhe stack. as ill ustrated in Figure 10-55. A 4-digit hexadL'!:imal representation is used for the birl.1ry addresses. In the fi gure. lhc addresses are c hosen for purposes of il1 ustralioll.
StmdJ section
nfRAM
Stact; pointer
I FFF.f
~ 0 0 0 0 0 0 0 0 TOJH,f· ,t.Ld.
(,,) 'n.,. , ~Illd;. pointer i~ ini linll y m FFEE ~forc the data won! 00010010001 10100 ( 1234) is pushl-d on lo the
1+ 1.:('
o 0 I 0 1 0 0 000 I 0 0 I 0 (] () 0 () () 0 0 0
T"p'
fb) The ~(ack poinler i~ (kt,TClflffitcd I>y two and the dma ""lTd 1J(01(X)100Cll IOIIX) IS pl ru.;et! jn rhe lWO Icctllions
prinr to (he nrigimrl "'-Hek pui nt er location.
FIGUR.E 10 - 55
lIJultr.ltion of the PU5H opet""OOn for <1 RAM d ac.k,
Now ler's !;cc how dar<1 arc pushed onto the .~ t ac k , TIle slack poinler is initially at address FFEE,6. which is the top of the stack as shown in Figure 10-55(a). The slack poinler is Ihen decremented (decreased) by two 10 FFEC I6 , This mo ves Ihe lOp of the Slack (0 a lower memury add ress. as shown in Figure 10-55(b). Notice that thc top of the slack is not slnllonary ,is in the fixed regisler stack bur moves down ward (to lower addresses) in the RAM a<; d<1ta words are stored. Figure 10-55(b) shows thai two bytes (one data wOIll)
•
577
578
•
M EMO RY AND ST ORAGE
arc then pushed onto the stack. After the data word is stored. the top of the stack is at FFEC I 6 • Figure 10-56 illustrates the POPoJX,":ration for the RAM stack.1lle last data word stored in the stack is read fi rst. The stack pointer that is <1t FFEC is incremented ( i nc l'Ca~cd) by two to tlddress FFEE'h and a POP operation is performed as shown in part tb). Kecp in mind that RAMs are nondestructive when read, so the dllta word sti ll renmins in the memory after a PO P opcr.!tion. A dnta word is destroyt:d on ly when tl new word is wri tten over it.
00 1 Stacl.:
POilllLT
FF~ L
(aJ '!lie SlhCk poJinlcr is III FFEC I)d(lI'i: the dma word is CopiL'(/ (p"ppcd) fmm Ihc ~tacl.: .
o
I 0 0 0 0 0 0 0 0 0 0 0 0 0 ()
o
Top~ f-~tod.
puinll.T is incrcmCI11L'(! by IW(l and the: las! word Slort.'d is co(lil.'d (popp<-x1 ) fmm lite stack.
(h) T he si d dat ~
FIGURE 10-56
lJIultration of the pop operation for the RAM stack.
A RAM slack can be of any depth. depending on the number of continuous memory adassigned for thai purlXlSc.
dresse~
ceo Memories T he eel) (charge-coupled device) memory stores dam as charges on capacitors . Un like the DRAM, howe"er, the storage cell docs not include a lransiSlor. High dens ity is the main advantage o f CCOs. 'Ille CCO memolY consists of long rows o r semiconduCtOr capac itors, caJJed cfulI/ne/s. Omtl are entered into a channel sctially by depositing a small charge for a 0 and a large charge ror a I on the capncitors. These charge packets are then shifted along the channel by clock signals as more data are entered. As with the DRAM. the charges must be refrcshed periodically. T his process is done by shifting the charge packets serially th rou::;h a refresh circuit. Figure 10-5i shows the basic concept of a CCO channel. Because data are shifted seriaJly through the d annels, the CCD memO!), hns a relatively long access lime. CCO am lys are used in some modern camera~ 10 C['Plurc video inwges in the form or liglll-induced charge. FIGURE 10-57
A CCD (charge-coupled devi<:e) channel.
Ch
_
IJlO\eIllCnl - - -
,_ ", _ _______ _ _LL.L.t~~~~~
-'---'---'-_':"_':"!>r --'---'---'---'-Su hslmlc
I
SECTION 10 7 REVIEW
1. What is a FIFO memory? 2. What is a UFO memory? 3. Explain the PUSH operation in a memory stack. 4. Explain the POP operation in a memory .ltack. S. What does the term CCD Jtand for7
MAGNETIC AND OPTICAL STORAGE
10-8
MAGNETIC AND OPTICAL STORAGE
In this section, the basics of mug netic disks. magnetic tape. magnelo-optical disks. and optical disks lire infroduccd. These stonlge media arc vcry importam. particularly in computer applications. where they are used for mnss nonvolatile storage of dala and programs. After completing
thi.~
section, you shou ld be able 10
• Descri be a magnetic hard disk . Describe a floppy disk . Discuss removable hard disks . Explai n the principle of magneto-optical disks . Di ...cuss the CD~ ROM. CD·R, and CD·RW disks • Describe the WORM • Discuss the DVD· ROM
Magnetic Storage Magt1etic Hard Disks Computers use hard disks as the illlernal ma5S slOmge media. Hard disk.<; nre rigid "plttners" Illttde o r aluminum alloy or a mixture of glass and ccramic cov~ ered with a magnelic coating. Hard disk drives mai nly come in two diameter sizes. 5.25 in . and 3.5 in. although 2.5 in. and 1.75 in. are also avai lable. /\ hard disk drivc is hcnnctically seakd to keep the disks dust ~free . Typically. two or more planers are stacked on top of each Olhcr on a common shaft o r spindle that turns the assembly at 1>Cvernl tho usand rpm. A sep..'tration between euch disk al· lows for a magnetic read/write head thai is mounted on the end of an actuator arm. a<; shown in Figure 10-58. 'n lere is a read/write head for both sides or each d isk since data arc recorded on both sides of the disk surface. '1l1e drive actuator ann synchronizes all the read/write heads to keep thcm in perfect alignment as they "f1y" across the disk surface with a sep.'tration of only
A hard dilk drive.
Bruic Read/Wn'te Head Pri'lcipies The hard drive is a r:mdom· access dcvice because it can fCtri eve siored dala anywhere on the disk in any order. A simplified diaBram of the magnetic surface read/writc operation is shown in Figure 10-59. The directio n or po l ar~ ization of the magnetic domains on the disk surrace is controlled by the direction of the magnctic fl ux li nes (magnetic fi e ld) produced by the write head according to the direction of a current pulse in thc winding. ll1is maBnetic tlux magnetizcs a small spot on the disk surface in the direction of the mag netic fi eld. A magneli;r.ed spot of one polarity represents a binary I. and one of the opposi te polarity represents a binary O. Once a -"pot on the disk surrace is magnetizcd, it rcmains until written over with rm opposite magnetic fi eld.
•
579
580
•
M EMO RY AN D STOR AGE
FIGURE 10- 59
Vuh:.lg.: puI~
Simplified read/write head oper<)tion.
A
Write
T, ..... k
/'
Dilt il i1re Itored on iI h
hard drive (Iome time! referred ill hard drive BIOS). The device I d,"""od t he comput er'l track amof i1cceu mel i1nd two I:~:~~~~~:~ The {int tab le Cil l1ed i<
the fAT (file Al location Tilble). The fAT !hOWl' IIA'l
When the magnetic surface passes a read head, the magnetized spots prodllce magnetic fi elds in the read head, which induce voltage pulses ill the winding. The polarity o r these pubes depends on thc directio n of the magnctized spot and indlc,lles wh(.1hcr the stored bit is a I or a O. The read ,md writc hcads are usually com bined in a single unit. A hanl disk is organized or fonna ued inlo tmcks and seclors, as shown in Figure 10-60(n). Each track is divided into a number of sectors, and each track and "ector has a physical ndd res.~ thnt is used by the operating system to locnte a particu lnr dnta record. Hard disks typically have fmm a few hundred to thousands of tmcks. As you can see in the fi gure, there is a constant number of tracks/sector, with outer ~ct o rs usi ng more surface area than the inner sectors. Thc arnmgemem of tracks and sectors on a disk is known as the format. A hanl disk stack is illustrated in Figure 1O--6O(b). Hard disk drives differ in Ihe number of plallers in a Slack, butlhere is always a minimum of I WO. All ofthc same corresponding lracks on each platter are collectively known as a cylinder, ac; indicated. Hard Disk Fvrmat
C(,m"'puI1(J;ng.lr~d.. , tht~.
m:>l..canlil1l.Jcl
\ Title/.;
o
/I
Tmd 3 TrJd.:!
o
I
TrJCk I
--==:-...·,:Ior--(aj
(bJ
FIGURE 10-60
Hilrd di,k organiza tion i1nd formatting.
MAGNETIC AND O PTI CAL STORAGE
•
581
Hard DiJk Performance Sc\'cral b."\sic paramcters determine the performance of a given hard disk drive. A seek o~ralion is thc movcmcnt of thc rcad/write he'ld to the desired track. T hc seek time is the average time for this o~ralion to be performed. Typically, hard disk drives havc an averagc seck time of severnl milliseconds, dc~ndillg on the particular drive. TI1C latcncy pcriod is the time it takes for the desired sector to spin under the head oncc the head is positioned ovcr the desired track. A worsl case is whcn thc dcsired sector is just past the hcad !XJsition and spi nning away from it. The sector must rotate almost a full revolution back to the head position. Al'emge Ifllency period assumes that thc disk must make half of a revolution. Obviously, the latency period depends on the constant rot,ltional speed of the disk. Disk rOiation speeds 'Ire different for differcm disk drives but typically arc 3600 rpm, 4500 rpm, 5400 rpm, and 7200 rpm. Some disk drivcs rotatc al 10,033 rpm and havc an avemge latency period of less th
fiGURE 10- 61
....indu",
Sprinf· l"u•.kd door "-
The 3.5 inch floppy disk (diskette).
....>
/~
I)j~1;
M<'I:ll huh
Wril<'-I'flllcellah /
ZipTM The Zip drive is one type of removable magnetic storage device that has replaced the limi ted-capacily noppy. Likc thc floppy disk, the Zip disk cartridge is a nexible disk housed in a rigid case aboUl thc same size as that oflhe Ooppy disk but th icker. The lypical Zi p dlive is much faster than the floppy drive because it has a 3000 rpm spin rate compared to the flop py's 300 rpm. The Zip drive has a storage capacity of up to 250 MS, over 173 times more than the 1.44 MS noppy.
laz1M Another type of remov::lbJe magnetic storagc dcvice is the Jaz dli ve, which is simil ar to a hard disk drive except that two platters are housed in a removable cartridge protccted by n dust-proof shutter. The .Jaz cartridges arc available with stomge capacities o f l or 2G R. Removable Hard Disk In addilionlO thc !XJpu lar Zip and j'1Z removablc drives, a remov,lble hard disk drive with capacitics o f from 80 GB to 250 GB is available. Keep in mind
582
•
M EMORY A N O STORAGE
that the technology is changing so rnpidly that there most li kely will be fu rt her advanceIllCnts at the time yOll ilre reading this.
Magnetic Tape Tape is used for backup data from mass storage devices and typically is slower than disks because data on tape is accessed seria lly rathe r than randomly. There arc several types that are available, including QIC, OAT, 8 nun, and OLT. QIC is an abbreviation for quarte r-inch cartridge and looks muc h like audio tape cassettes with two ree ls ins ide. Various Q IC standards have from 36 to 72 tracks tha t can store from 80 M B to 1.2 GB. More rL'"Cent innovations under the Travan standa rd have lengthened the tape and increased its width allowing storage cilpacities up t04 GB. Q IC tapc drives use read/write heads that have a single write head with a read head on each side. Thi!> allows the tape dri ve to verify datajusl wrillen when the tape is nmning in either direction. In lhe record mode, Ihe tape movcs past the read/wTite hends at approximately 100 inches/second, as indicated in FigUl"C 10-62.
Wrile head
(m(1\ in!;
PI'" hcad)
FIGURE 10 62
Q ICtilpe.
DA1~ which is an abbreviation for digital audio tar~.":' uses a tedmique called helical scan recording. OATs offer stor.lge capacities ranging up to 12 GB but is more expensive than
QIC. A third type o f tapc format. the 8 mm tape, was o ri gi na lly dcsig ned for the vidco indwary but has been adopted by the computer industry as a rel iable way to sto re large amoun ts o f compule r daHl. 8 mm is simi lar 10 OAT but offcrs sto rage capacitics up to 25 G B. DLT is an abbrcviation fordigila l linear tape. DCI' is a half-inch wide tape. which is 60% wider tha n 8 mm and, o f course, tw ice as wide as standard Q IC. BasicalJ)'. OLT differs in the way the tape-drivc mechanism \\fOrks 10 minim izc lape wear compared 10 other systems. OLT offers the highest storage capacity o f all the tape formats with capacities r
10 35 GB.
Magneto-Optical Storage As the name implies, magneto-optical (MO) storage dcvices use a combination of magne tic and optical (lase r) tcchnologics. A Ilmgnehl-Ol)tical disk is fomlalled into Irac ks and sectors similar to magnetic disks. The tx...sie d ifference between a purely magnetic disk and an "" 10 disk is that the magnet ic coaling used on the MO disk requi res heat to alter the magnctic polari7..alion. l1lCrefore, thc MO is extremely stable at am bient temperatu re. making da ta unc hangeable. To write a data bil, n high-power laser beam is focused on a tiny s pot on the disk, and the temperat ure of Ih ~ t tiny s pot is raised above i\ temperature levcl called the Curie point (about 20(tc). Once hcated, the magnetic particles at thaI spot can easily have thei r di-
MAGN ETIC AND O PTICAL STORAGE
•
rection (polarization) changed by a magnetic fi eld generated by the write head. Infonnalion is read from the disk wi th a less-powerful laser than used for writing, making use of the Kerr effect where the polari ty of the reflected laser light is altered depending on the orientation of the magnetic panicles. Spots of o ne polarity represent Os and spots of the opposite polarity represent Is. Snsic MO operation is shown in Figure 10-63, which represents a smal l cross-sectional area of a disk.
1;:::=} ,,.,.
Magnetic
Disk mUllion
Lcm' High-power h~lJt,alU
Substrnte
'" 11""\".' Maglll'lic malerial
~E"'''"~"",
Spot is ilcated b)' 11lSC1" "nd magnctilcd by elcctrtJlmgnl'lic ficld.
Write C UITe m
(h) Wrilin!:!: A high-power ' [l.
magnetic particles to align wilh the cloctmrnagnelic field .
....
~
High-pcJ\HT " I...crhcllm
-·~TITITTI~~~r.P~~
! , ! , \ , I "
t .,
(c ) Reading: A l
)
~Tl t l
' il l I , III' II II IH
(d) Erruiing; 11.,., elcctromagnetic focld is r!:", .-,;cd:1$ the high· pomet !aser 0Cam hems the spot. c:tu~i ng 11.., rn.'l8ncuc partic)c,; to be re..;t,>rOO to the original pollifity.
fiGUR E 10-63 Basic princip le of ~ magneto-optical d isk.
Optical Storage CD- ROM The basic Compact Disk- Read-Only Memory is a 120 111m di,lme ler disk wirh a sandwich of three Co.1lings: a polycarbonate plastic o\) the bottom. a thin aluminum shcet for reflcctivilY. and a lop coaling of lacquer for prou:ction. The C»·ROM disk is fo rnwlled in a single spiral track with sequenti al 2 kB se.;tors and has a capacity of 680 MS . Data arc prerecorded at the factory in the fonn of minute indentations called pits and [he flat area .~ urrol!nding the pits called lam/s. The pits are stamped into Ihe plastic layer and cannot be erased.
583
584
•
MEMORY ANO STORAGE
A CD player read:.; dam from the spiral track with a low-power infntreJ laser, as illustrated in Figure 10--64. The data are in the fonn o f pits .\Ild lands as shown. Laser light reflec ted from a pit is 1800 out-of-phase with the light reflected from the lands. As the disk rotates, the naITOW lase r beam strikes the series of pits and lands of varying lengths, and a photodiode detects the difference in the reflected light. The result is a series of I s and Os corresponding to the configuration of pits and l an d~ along the track. FI GURE t o - 64 ~ic 01
operation of reading d
Co.-ROM.
\'
~I '
Pit --'
r
,.-
\;'
Ll.
"'''''
Di sk
t..eIlS
Lens
/{
r- .... ...,i"""'"
Pri~m
Pholr,da:tric ttll
I
.1L"\Ser
WORM Write Once/Read Many (WORM) is a Iype of oplical storage Ihat can be wrillen onto one time after which the data C<1I1110t be erased but can be read many times. To write data, a low-power laser is used to bum microscopic pits on the disk surface. I s and Os are represented by the burned and non burned areas.
CD- R This is essentially a type o f WORM. The difference is that the CD-Recordable allows mu ltiple write sessions to differen t areas o f the disk. The CO-R d isk has a spiral track like Ihe CD-ROM, but instead of medmnically pressing indentations on the disk to represent data, the CD-R uses a laser to burn microscopic spots into l1n organic dye surf
TRO UBLE SHOOTING
Originally DVD was an abbrevialion for Digit al Video Disk but eventually came to represent Digiw{ \'ersl/Iile Disk. Like the CD-ROM, DVO-ROM data are prestored on the disk. However. the pit size is snwller than for the CD-ROM. a llowing more data to be stored o n a track. The m
i SECTION 10-8 REVIEW
1. list the major types of magnetic storage.
2 . What i~ the storage cap.1lcity of fl o ppy disks? 3 . Ge nerally, how is a magnetic disk o rl}"lnized? 4. How.3re data \.VI"itten on and read from a magneto-optical disk? 5. list the types of o ptical storage.
10-9
TROUBLESHOOTING
Because memories can contai n Inrge numbers of storage cells. test ing each cell can be a lengthy and rrustrati ng process. Fortunately. memory testi ng is usually an automated process perfol1l1ed with a pro1!l1Immnble test instrument or with the aid or soft ware for in-system testing. Most microprocessor-based syslems provide lllltomatic memory testing as part of the ir system .~tJflwa re. Aftercompleting this section. you should be able to • Discuss the checksum melhod of testing ROMs . Discuss the checkerboard pattem method of testing RAMs
ROM Testing Since ROMs cOlllain known data, they can be chccked for the correctness or the stored data by reading each data word rrom the memory and comparing it with a data word that is known to be correct. One way of doing this is illustraled in Figure 10-65. This process
o ROM
-
Reference
ROl\t '0M
r
EN
Enable Address
ROM
uIJtI.:r
I
'N
EN
Ref.l)am
031:1
ROM IC'It-....
FIGURE 10 - 65 Block di"'gr"'m (or
eontent1 eheck o( '" ROM.
•
585
586
•
MEMORY AND STORAGE
reljuircs a reference ROM that contains the same data as the ROM to be tested. A s!X!cial test instrument is prob'rdmmed to read each address in both ROMs simultaneously and to compare the contents. A nowchart in Figure 10-66 ill ustrates the ba.-;ic sequence .
Selecl fin;t addrcSlS
- "", 0. Relld data byte ~--------I from address II of ROM & Ref. ROM.
Com pare lima bytt:s.
Do daln bytes agree?
Na:t address
addrcs~
Inll icate fali it.
Last
.,
addre~.
11=11+1
. " is the
No
number.
FIGURE 10- 66
Flowchart for a complete c:ontenb check of il ROM.
Checksum Method Although lhe previo us method checks each ROM address for correct dala, il has Ihe di sad vantage of requiring a reference ROM for each differe nt ROM to be tested. Also, a failure in the reference ROM can produce a fau lt indication. In the checksum melhod a number, the sum of the conte nts of all the ROM addresses. is stored in a designated ROM address when the ROM is programmed. To test the ROM , Iheconlellll; of aU the addresses except the checksum are added, and the result is compared with the chetksum stored in the ROM. If there is a difference, there is defi nitely a faull. If the checksums agree, the ROM is most likely good. However, there is a fCmote possibility that actually an XOR sum o f eftch column. T he flowchan in Figure 10-68 illustrates the basic checksum test.
TROUBLESHOOTING
U 0 I I 0 I 0 0 0
0 I
Simplified illustration of a
0
0
checksum ltored at a ooignated
0 0 0
u u
( 0 I 0 0 0 0 0 0 U 0 I I 0 U (I
I 0
"
587
FIGURE 10- 67
RO~I
Data
•
"
IO
po'ogrammed ROM with the address.
FI GURE 10-611
,
ScI " ",0 Sel Sli m = 0
Relit! IIdd resS'L
XOR
e,,," chedsum &It!ress.
C(lm[>llfl'
Ch•.'Ck.sllm Wi lh final XOR sum uf t!ala.
cCl!l1 tent~
ofaddre"'i " with pn.-" 'ious sum. Update the slim.
Ne~t
oot!rcss ".,,' + 1
Flowch<»i<: checksum test
Indicate Faull.
smr
The checksum test can be implemented wilh a special test instrument, or it can be incorporated as a test routine in the built- in (system) software or microprocessor-bnsed sys· tems. In lhllt case, the ROM lest routine is automatically run on system start-up.
RAM Testing To test a RAM for its ability to store both ~ and I.~ in each cell, fi rs t Os are written into 1111 the cells in each address and then read out and checked. Next, Is ure v>'rinen into aU the cells in each adclre.<;s Ilnd then read out and checked. TIlis basic test will detect a cell that is stuck in either a 1 state or a 0 state. Some memory fau lts cannot be detected with the 1l1l-0s- IlII - ls tesl. r"Or example, if two adjacent memory cells are shoned, Ihey will always be in the same stille, bolh Os or both Is. Also. the all-0s-all-l s lest is ineffective if there Ilre internal noise problems such thaI the contents of one or more Ilddresses are altered by a chnnge in Ihe contents of another address. The Checkerboard Patten'! Test One way 10 more fully lest a RAM is by using a checkerbourd pllttcm of Is and Ck, as illuslrated in Figure 10-69. Notice that ull adjacent cells have opposite bits. This paUem checks for a ShOll between two adjllccllt cells; if there is a ShOll, bolh cells will be in the same slate. After the RAM is checked with Ille paUem in Figure 10-69(a). the pattern is reversed, as shown in pari (b). TIlis TCversal checks the ability of all cells to store both 1s and Os.
58' •
MEMORY AND STORAG E
FIGURE 10- 69
The RAM checl<.erb0.3rd ted pattern.
1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0
1 0
0 0 1 0 1 0 0 0 1 1 0 1 0
0
0
0
0
0
1
1 0
0
0
1
1 0 1 0 0 1 0 1
0
0 1 0 0 0 1 0 1 l' 1 0 1 0 1 0 0 0 0
0
0
0 1 1 0 1 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0
0
1 0
0
0 0
1 0 1
0
1 1
0
,,\
1 0
0 0
1
1 0
1 0
1
1 0 1 0 0 1 0 1
0
0 0
0
1 0
1 0
0
1 0 1 1 0 1 0
0 0
0 1 0
1b1
A further test is 10 alternate the pallcrn one address at a time and check allihe other addresses fOf the proper pallcm. 1l1is lest will cl'ltch a problem in which the contents of an address are dynamically altered whe n the contents of another address change. A basic procedure for the checkerboard tcst is illuslHlfCd by the flowc hart in Figure 10-70. 111e procedure can be implememed wi th the system software in microproccssor-
S t OU $et n : ()
checkerboard pUllcrn at aU adtIres~s.
RCVLTIie th e
palll!fn in nlldres> II .
C heck all add~s.
Cill'c k
No
Indicate fault . No
A ll OK?
y~
Reverse
the l)auem at
all addn..~s.
Yt'S
N(!1;!
Cb.'.:k ull
address " = 11+1
addresses.
No
La\!
address?
Yes
All OK?
No
Indic,l1 e faull.
Yes FIGURE 10- 10
flowchart for b.uic RAM c heckerboard relt.
(
S1DP
)
Indicate fau lt.
DIGITA L SYSTEM APPLICATION
•
589
based systems so that e ither the tests are auto matic when the system is powered up or they can be initiated rrom the keyboard.
I
SECTION 10- 9 REVIEW
1. Describe the checksum method of ROM testing. 2. Why Gln the checksum method not be applied to AAM testing? 3. list the three basic faulb that the checkerboard pattern test can detect in a RM1.
General Operation
The block di"grJm of the comple te .ecurity ')'Stem is ~own in Figure 10- 71. The memory logic stores" 4-digit security code in BCD form>lt In the dUi1rm mode, four digits are entered into the memory from the keyp
In thi~ JppJication, the memory logic for the security sy;tem that WilS introduced in Ch
Secu rity code logic
-
mCD ~ i= II! CD CD I
CD
s,~
II
Clock B
1111
, AIW,
I)I.'iaOTI
~
-
Reset
Memory logic
.........
FIGURE 10-71
Block di
The Memory Cell The memory requires sixteen cell. to .tore the four BCD digib of the security code. One pcx.ible design £ex
1mrOlll
Clock A
1JJ0CD ,
rood ope«ltiom. A block diagl"
--
To unncd lighl 3nd ,;c'I..<.Orfalarm interface
590
•
MEMORY AND STORAGE
BCD,~ {
from le}PJu ~nc"der
-
2-bil counter
Clocl..A -
BCI) ~ode
e LK
M"mory add ress
""""" .'II",.".
\\1
r-
rr-
} A~= 0- 3
1-
in
'BCO{ ""'" 00'
~
-
--
ilCh
R.-od/Wri",
CkdD
16-bi l lllClllOI)' (4 x 41
FIGURE 10 - 72 Block diagrOlm of the memory logic::.
AJd.'5t>{
Oil in OUO:I..
RIll
G' } - - J
G3
Bil .."l
e
G2 r '-.I
Q
K
f
FIGURE 10-73 Memory cell logic.
of the flip-flop appeil" on the output ofG3 (Bitovt).
memory addre...es using the AddSeI lines.
Yhe Memory Address Decoder
The Memory Array
The memory Olddren decoder logic is
The memory t.....s sixteen cells M mOM! in Figure 10-75. When one of the toW! in the memory is selected by the address decoder and the read/wrik' input is ISYW, the 4-bit
shown in Figure 10- 74. A 2- bit bin;)ry u~quence
is Olpprie d to the select inpub
(So. 5,) to select eOlch of the four
BCD input code is clocked into the four selected cells. The inpub to the addr~s decoder Olre sequenced through each of four 5I:at~ (00, 01, 10, ;)nd 11) to sequentiilily \.e lect e.iICh row in
the memory.
Figure 10-76 iIIUSUOltes the programming of the memory OlS the security code 4739 is sequEOti.ll1y entered.
DIGITAL SYSTEM APPLICATION
•
FIGURE 10 - 14
The memory add resl decoder.
A,
s, --~-------------t
__~
"
CDcrxle {
frol n "e)pad
em;oOcr
--
AddS,./ Bil in Bi! 00'
AddSeI Bilin Biroo!
f--
Clock
C"" -
,
I'fiii
A(/dSeI Bil in Hir lXI,
AddS~1
Bit in BiloU!
IuMSeI El11;n Eli lout
AddSeI Hil in Bi( ool
I-
I-
I-
<..'\ock
C""
MdSeI Hit in Hil l)\11
IIddSeI Bil in Bilool
Clock
Clock lilW
CIocl<
AddSeI Bit in Bhool
MdSeI El il ;n Bilollt
I-
Clod< 1M'
-
R/l'
RIll'
f--
Qoc.
Rril'
Rlili
s,
f--
I'fiii
I 1M'
I~
V
f--
Add&1 Hil in Bil 001
III'"
C""
v
Md&1 Bit in Biro'" Clod
AddSeI Hi( in Bit ou l
A,MS'" - t1ir;n BilOOI
00"'"
RM
RIll'
Memory
""'= ",-
At/dSeI Bilin Hit 001
aoc. Rlili
-
Ii('(lil/Wri/£'
--
Cloc.
I'fiii
--
,-
Clod
"'"
Ad(/Sd Bit in Elitout
Ckrl RI"
Clock
'I FIGURE 10-15
Memory arr..y and
addres~
decoder.
L}
591
592
•
MEMORY AND STORAGE
I I I
I
0
8-
Il-
f
~
11
o}
8-
0
~
o ~
Lr--'-l
1
~ 11
h
I}
8Lr--'-l
OlI
~
Lr--'-l
8I l-
,.---'-,
~
0
" (3) Enter digit 4
fbl Emer digit 7
I I
I 0 11 I
8- M M-
8- Gl- 8- Mo
~
I
0
I
IJ
0
r-0 Lr--'-l I
I
~
oj y Q 0
~
I
'-r-'
I
(c) Enter dig it 3
~
I l-
,.---'-, I
I
11
I
I'-r-'
I
0
I
e
Jlllf-
0
(d ) EntL'T <.Iigit 9
FIGURE 10- U
Illustration of entering a security code (4139) into the memory.
The Complete Memory L.ogk A keypad encoder is necellary fo r converting a key stroke to a BCD code, and a Z~b it counter ;1 used t o produce the sequence for lelecting th e me mory
through its .equence by e
System AUignrnent Explain ~t the keyp
• Ar.tivity 1 The Complete Security Syttem Now th
logic from Ch
• Activity 1 Explain whilt the l -bit counter doe in the memory. • Optional Activity Comtruct the complete security entry system uling ibndard 74XX devices
DIGITAL SYSTEM APPLICATION
IJCDcOOc { from kCYP'td I'llc,,u,r
n-b-
I
~
j
I
~
Clock A
-
~
v
v
~I
T
~I
T
·'.. !S",rI'M'i1<:h,
I-
'I
r T
T
r r
ht ;-L
Y W- Y h n h
2-bi\ counler
e LK
•
l:Q ~
T
Ck>.:kB
'(
'(
L
~} """ C D " ...1
FIGURE 10-71
The complete memory logic.
Security code logie r~--lo
- --
I
-- 2
Fmm "c)'pacl
-
"
3
C
4 5
o
6 7 8
-- 9 , --
A
-, Ann/Djsann
FIGURE 10-78
The security code logic (from Chapter II'.
AnnOul Tri!;ger Rca!l
} From "0"'"
593
594
•
MEMORY AND STORAGE
0
M~mor)'
-
2
Fl'I>lll l.c)JXld
lock
I 2
I
, ]
]
,
,
6
6
4
DltlaOutO
7
7
8 9
DlltllOutJ DmaOu t2
8 9
[}dta().n3
,-Cludin
-
Trigger Sm", Reset Clock in
Securily lVlle logic
0 I 2
A
3
C D
I--
B
, 4
6 7 R
An"Out
ArmO"t T rigger
9 ArmlDisarm
'='Il
FIGURE 10 79
The complete security S)'lte m.
•
Types of semiconductor memOlics:
KAM R,tl1oolll-
AI",
A=~
R~n11l
Memucy
SRAM
a,-.;c"
DRAM
EPROM Erasable
St~ t k
Dyrutmie
Prt:l!!nllnma bie ROM
ROt-·l
FLASH
R FO
Re3d-
Read/wri te &
Serilll
Only
R.1ndom
M em ory
acces.~
EEPROM Electrically Erasable PROM
LIFO
CCD
Serial
St:Tilt!
flCCCSS
access
SUMMARY
• Types of SRAMs (Stalic RAMs) and OR Afo.'ls (Dynam ic RAMs):
SIu\\cr than SRAf-I,
l-ol'IL'f than DRAM ~rnalk'f npa:lly th;.n DR,\M,
l..a'l'tr LOIJ1"ICil > SRA:"I
OIlen Ir-.nI a..~ ~'IO:he
memor)_
I'hp-fk>p ,Ulr4;C ~'Cl h
UmnSRA)1. l;~ 8.' main
SRAM NO! S) nCluonizcd wit h sYSlcm dock
cd l~.
Mw.l bt
~fre.Jk-d.
ll'II:ll1OI).
SynchronOOli SRAM Wilh burst f Cllt llrt:
Asynchronou~
COlplk;itor'il~
DR AM
SDRAM
A ' M DRAM F IIloI
Page M (Ide
Synchronoo s
A~yl\Chrllnous
SyochronizL'Il \\ ith system clock. BU ~1 .wd m;sing
EDO DRA M F..xtcnc.k;d D,,111
O!.nplil Asynchronous
BElX) DR AM Bun;!. EOO
As}ochron(lus
•
RemovnbJc JlIZ disk
Hurd d isk
•
t.-1.aglltlt>OpIical
Types of mag netic ~tOffige:
Floppy d isk
Rcmo,'~bl c
Zipdisl.
QIC (Towan)
OAT
8mm
OLT
Types of optical (lase r) stOffigt::
CJ).ROM
CD-R
CD·I{W
WORM
DVD-ROM
Diu Croo.~ bc'"L....·n
\U;'l",e'ic uplkill
~"lfJ
Pn:n:c"nJcd ;), l'ICIt ...,
R<"t"on:JIlhJ"
Rc""tah lc
Wnt .. onl'" read
Digital \('Th.(l ilic
nmn>
•
595
596
•
MEM ORY AND STORAGE
KEY TERMS
Key terms and other bold terms in the <:hapte\" are defined in the end-of-book glossary. Ad drx.'SS The locat ion ofa given storage cell or group of l-el ls in
il
mcmory.
IIlls A set of interconnections that interface one or more devices based 00 il sland.1rdizcd spcd ficalion. Byte A group of cight hits.
Capacity The total number of dilla units (bils. nibb les. bytes. words) thilt a memory ca n ~ t ore. Cell A sing le Mor.lge eleme nt in a memory.
DRAM Dynamic random-access memory: a type of semiconductor memory thm uses cap'lciwrs as the swrage clemen ts and is a volatile. read/write memory. EI'ROJ\.I Erasable progr-.Imm:lblc read-onl y memory : a type of semicond uctor memory device th<1l typically uses ultr.l\'iolet light to er.lsc data. FIFO Fi rst in-fi rst out memo ry. F'lm;h mem0l1' A nom'Olatile read/wri te random-access selllkondu ctor memory in wh ich data are
storoo as charge on the nouting gmc n f a certain type of FIT.
liard di<;k A magnetic storage device: typically, a slack of two o r more ri gid disks enclosed in a sealed housing. UFO
LiL~1
in- first out me mory; a memory stac k.
PROM Programmable read-only memory; a type of scmiconduClor memory.
HAl\! Rnndom-access memory; a volatile read/write se micoodul1or memory. Rt'".!d 1be process of retrieving data from a memory. ROI\-1 Read-only memory; a nonvolatile mndom-accCl,s scmiconductor memory.
snAM Static nmdnm·acccss me mnfY; a type of \'fllatile read/write semil"Omluctor memo)) '. Woro A l"Omplete unit of binary data.
Write The proce~s of storing data in a lnell1ol)'.
I. The bit cilpacity o f a memory that has 1024 aJdres:\es lllld can store g bits at each address is (a) 1024
(b) 8 192
(I:)
8
(d) 4096
2. A 32-bit d,lta word l"Oosists of nib ble~
(aJ 2 bytes
(h) 4
(c) 4 bytes
(d) 3 bytes and I nibble
3. Dma are stored in a mndom-access memory (RA M ) du r in~ the
(a) read opermion
(11) enable operation
(e) write operot ion
Cd)
addT\:s~ing{)per.ttion
4. Dala thaI are stored at a given address in a random-acccss memory (RAM) is losl when (11) power goes off
(11) the data are read h om the iuJdress
(e) new data are wrilten at the address (d) answers (a) and (cl
5. AROMisa (a, llotWolali le memory
(11) volatile memory
(c) read/wri te memory
(d) byte-org-.!nizcd memory
6. A memory with 256 "ddresscs has (a) 256 address lines
(hI 6 address lines
(c) I addJTI;s li ne
(d) g address lines
PROB LEMS
•
597
7. A byle-organized melllOlY has (ll ) I dala OUlpu! line
(b) 4 dala oulpulli nes
(e) 8 data olllpullines
(d) 16 (I ala olllplll ii nes
8. The slomgeeell in a SRAM (a) a nip-nop
« ) .\ fuse
i_~
(b) a eapacilOr
,d,
a magnetic domain
9. A DRAM musl be (8) replaced period ically
(b) I'efrcshed pel'iodica tt y
(e) always enabled
(d) progmmmcd before each use
10. A nash memory is (b) a read -only memory
(a) vollllile
(e)
11
read/wri te memory
(d) nonvo lalile
(e) Ilnswers (a) and (c)
(0
an~wers
(c) and Cd)
I t. ' -lard disk, no ppy disk. Zip di sk, and Jaz disk are all (ll) rnagnelo-oplical slnmge device~ (b) scmiconductor ~tor.!ge
device~
(e) magnetic storage devices (d) optical slornge devices
12. Optielll storage devices employ
PROBLEMS SECTION 10- 1
(a' ult rnviolcl light
(b) elcctrOlnagnetie fields
(e) optical (:ouplcrs
Cd) lascrs
AnWICI1 to odd-numbered problems are at the end of th e book.
B.,sicI of Semiconductor Memory I. Identify the ROM and the RAyt in Figure 10-1\0.
FIGURE 10 - 80
A"
,I, ,I,
".1 A~
A,
64><4
JA~
0" 0,
A" A, A, - A,
0,
A~
0,
A, - -
64><4
JA&
1100 110\ 1I0l 110,
E E
NlW (. j
(b)
2. Explain why RAM s and ROMs are bulh rnnd\Jm-access memories.
3. Explai n the pll rpo!>CS of the addre-;s bus and the dala bus. 4. Wha t memory address (0 through 256) is represented by each orthe lo/lowing hexadecimal numbers:
598
•
MEMORY AND STORAGE
SECTION 10-2
Random-Access MemorieJ (RAMs) 5. 1\ slOltlC memory ;nTay wi th four rows similar to the one in Figure IQ-.9 is iniliOllly storing all Os. What is its conlent afler Ihc fo llowing m ndit ions? I\ssumc a I selccts a row. Row 0 == I . OOltOl in (Bil 0) :: I Row I :: O. 001101 in (Bill ):: I Row 2 = t . Datain(Bit2) = I Row 3 :: O. D31a in (Bit 3) = 0 6. Draw a b.1sic logic d i a~nun for U5 12 X 8"bi t slatic RI\M. showing a ll the inputs iIIld outputs. 7. I\ssumi ng thul OI64k x 8 SRI\M has a structure similar 10 Ihat of the SRAM in Figu re 10- 11. determi ne the number of rows OIfId 8-bit columns in ils memory cell OIrrny. 8. Redmw the block diag(t
SECTION 10-3
Read-Only Memories (ROMs) II. r"()r the ROM army in Figure 10-8 1. detenni nc the outputs for all possible input combinutiO(lS, and su mmOlll ze them in tabu lar f0l111 (Blue cell is a I. gray cell is a 0).
FIGURE 10- 81
1,, - -
1, - --
0 ,
0,
0,
0"
12. Determine the lruth table for Ihe ROM in Figure 10-82. FIGURE 10- 82
Address
""""", o 2
1,, --I --1, ---
3 4
, 6
7
u,
0,
0,
u"
PROBLEMS
•
599
13. Using a p!"Ol.'Cdllfe similar to thm in Example 10-1, de.~ign a ROM for conllCn;ion of si ngledigit BCD to excc.~~-3 code.
14. What is Ihe 10lal bil capacity of a ROM that has 14 address lines and 8 dataoutpUls?
SECTION 10-4
Programmable ROMs (PROMs and EPROMs) 15. Assuming that the PROM matri x in Figure 10-83 is programmed by blowi ng a fu se link to create a 0, indicate the links 10 be blown 10 program an Xl look-u p table, where X is a number from 0 through 7.
X{-l2 - -----1 '
FIGURE 10-83
16. Determine the addre~scs that are programmed and thc contents of each ad
SECTION 10- 6
Memory bpansion 17. Use 16k x 4 DR AMs 10 build a 64k x 8 DR AM. Show the logic diagrJm. 18. Using Ii block diagram, show how Mk x I dynamic 256k x 4 RAM.
R AM~
can be expanded 10 bui ld a
19. What is the word le nglh and thc word capacily of the menlO!)' of Problem 17? Problem 18?
SECTION 10- 7
Special Types of Memories 20. Complele lhe timing di agram in Figu re 10-85 by showing the ou tput wa\·ef0n11S that arc ini tiall y all LOW for a FIFO selial menlOry like thaI shown in Figure 10-49.
600
•
MEMORY AND STORAGE
,
Ao ,
Al ,l A~
,I
A I J
A, A, A, A, , ,
I
:
A. I
,
,
I
I
,
~:, A Ul
, :
I
:-----J
:-
,
,:
A I2 :-
A,, :;: All OE ~
:
,---,:
I
1-------1
I---
~: ~~~~l~~l-~~E;'~~
CI,:tPCM I
VW -"r' ---+--~~--+---4---~---+--~----T---t---~--0, 0, 0,
0, 0,
,,
0,
r---
0, FIGURE 10-84
FIGURE 10-85
Shift in
Shiff out _ _' -- '
21. Consider ~ 4096 x 8 RAM in which the last 64 addre~ses are used as a LIfO stack. If the fi rM address in the RAM i~ !XXl16' de~ i gna te the 64 addresses used for the stac k. 22. In the melllOry of Problelll 2 1. sixteen bytcs are pushed in to the stad..:. AI what address is thc fin;1 bytc in located? At what address is thc last byte ill located?
PROBLEMS
SECTION 10- 8
•
60 1
Magnetic and Optical Storage 23. Describe Ihe general formal of a hard disk.
24. Explain seck lime and lalcncy period in a hard disk drive. 25. Why d~ magnet ic lape require 11 much longer access lime than does a disk" 26. Explain Ihe dilTereoces ill a magncto-optical disk. aCD-ROM . and a WO RM .
SECTION 10- 9
Troubleshooting 27. Delenlline if the eOlllcllls of the ROM ill Figure l 0-8fi are cOOCCI. FIGURE 10- 86
ROM
101 I I I I I 10 I 10 1 I 10 1 I 0 I I 10 I
I I 1 00 00001 Checksum 0 I I 0 0
28. A
11~ X 8 ROM is implemented as ~hown ill Figure 10-87. The decoder decodes the two most signifi cant address hilS to e llllble the ROM s one lit a time. depending on Itc add ress selected.
(a) Express the lowest address and the highest uudICss of each ROM as hexauccimal Ilumbers . (b) Assume that a single chec ksum is used for thc entire memory and it is Sioretl all he highest addres~. Devclop a Ilowchart for testing the complete me mory systcm. (c) Assume that caeh ROM has a checksum stored aI its highest addrcs.~. Modify thc n()1.l.'chart developed in part Ib) to accommodate this challgc. (d) What is the disadvantage of using a single checksum for the entire memory [
7·bit .,.Jtln." O I u~ A6
A.
,,~
lli1~
r~MO
~
A.
'"
--=
} ROM I
A~
A.
'"
c..=::
} ROM 2
Ati
-
1"'rM3 Ai1;
2 linc-l04 line
"""""0 -
I
EN
r
2
r
EN
r<
EN
.~.
r<
EN
H-bit data
EN
bu~
3
FIGURE 10- 87
29. Suppose that a checksum test is !lin on the memory in Figure 10--87 and each individual ROM has a cilet.'ksum at ils highest aduress. Wha t Ie or ICs will you replace for each of the following error mesSllges Ihat appear on the system's video mon itor'! (a) ADDRESSES 4O-5F FAULTY (b) ADDRESSES .20-3F FAULTY
(c) ADDRESSES 00-7F FAULTY
602
•
MEMORY AND STORAGE
Digital System AppliCOlltio n
-
30. Develop a ti m ing diagram for the basic mcmory logic in Figure 10-72 to illustr.:ue the e llt!)' of the uigits 432 1 into the SRAM. Include all the inputs and outputs o f each device,
3J. When progrmllming the securi ty syste lli. whm two code u ig its have bec n e nte red?
i~
the Slate of the COullter in Figure 10-77 llfter
32. What is the purpose of the memory logic? 33. Discuss the ad\"alllages :mu the d isadvamages o f u,~i ng a PROM ex terna l to the CPLD instead of the memory on the CPLD c hi p in the me nlory logic.
Special Design Problems 34. Modify the design o f the memory logic o f the securit y en try sy~te m to accommodate a 5-digit e mry code.
35. Make the appropriate mod ificOItions to the secu rity code logic o f the securi ty e mry S-digit en lry code. Rc fer to lhe system a ppl icatio n in C hOlpte r 9.
sy.~km
for a
SECTION REVIEWS SECTION 10- 1
Basics of Semiconductor Memory I. Bit is the s1l!OI liest unit of dOlIa.
2.
2~6
bytes is 2048 biLS.
3. A write operation Slores data in memory. 4. A reOld
~rati on
lakes a copy o f data from memory.
5. A tlllit of data is located by its address. 6. A RAM is vo latile a nu hOls reud/write cOIpability. A ROM is non\"OIOItile OInd
hOl.~
on ly read
capability.
SECTION 10- 2
Random-Aceen Memories (RAMs) I. Asynchronous and synchronous with bursT fe'1Ture
2. A smOl I1 f
3. S RAMs have latch stoTl:1ge cclls lhaT
CaIl retain data indcfinitely wh ile power is appliell DR AMs have capac itive stor1l£c ce lls that must he pcriodicOl l1 y rcfrc~hed.
4. Thc re fresh oper.!tio n pre\'c nTs dOlla from being JO!it bcCOlUse of c~iti\"e dischl1rge. A stored bit i~ ",s tored pe ri odica ll y by rech arging The c apaci tor 10 iTS nomina l level.
5. FPM, EDO, BEDO, Synchronous
SECTION 10- 3
Read-Onfy Memories (ROMs) I. 5 12 x 8 eq uals 4096 bi ts. 2.
M OI.~k
ROM. PROM. EPROM, UV EPROM . EE PROM
3. EighTbit.. of add rCl's OIre Te
SECTION 10-4
Progtammable ROMs (PROMs and EPROMs) I. PROMs are fi eld-progra mnmble: RO Ms are lint.
2. h are lefT a fter EPROM erasu re. 3. Read is the nonnOlI mcxle o f opcnnion for
SECTION 10- 5
Ii
PROM .
Flash Memories 1. Flash. ROM . EPROM. and EEPROM arc nonvo lati le. 2. Fl ush is non\"OIOIt ile; S RAM :Uld DRAM are vo la ti le. 3. Pmgramm ing. read, erast:
ANSWERS
SECTION 10 - 6
•
603
MernoryExpansion I. Eig ht RAMs 2. EiJl-ht RAMs
3. SIMM : Single in-line memory module 4. D IMM: Dual in-line memory modu le 5. R IMM : Rambus in-line memory modu le
SECTION 10- 1
Special Types of Memories I. In a FIFO memory theji"sl bit (or word) il/ is thcji"~" bit {or word)
om.
2. In iI LI FO memury the {lIsi bit (or word) ill is thefi':)'1 bit (or wocd) 0111. A stack is a LIFO .
3. The opemtio n or imtruclion Iha[ adds data
[0
the me mory slack
4. The oper-llion or instruction thil[ removes datil from Ihe memory stack
5.
SECTION 10- 8
ceo is a ehmge-coupled devicc.
Magnetic and Optical Storage I. M agnetic S[Ofilge: floppy disk. hard disk. tape. and magneto-optical d is k.
2. Floppy di sk stor.tge capacity: 1.44 MB 3. A ffi
~ani7.ed
in Ir.tcks a ru:l
~cct ors.
4. A magneto-optica l d is k use s a laSer beam :md an e!<:ctTO magncl . 5. O ptil.-al slomge: C D -ROM , CD-R , CD-RW. DVD-ROM . WORM
SECTION 10- 9
Troubleshooting I. The con tents of the ROM llre added and compared with II preslored c hecksum . 2. Checksum cmmet be used because the con tents of a RAM arc nOl fix ed.
3. ( I) a short belwccn lldjacem cells: (2) an inabili ty of I«>me cells to store both Is and Os: (3) dynamic ,lltering of the l'Ontents of one add ress w/len the conlents of anether address dlilngc.
RELATED PROBLEMS FOR EXAMPLES 10- 1 C., G~G,GO = 1110 10-2 Connect eight64k x 1 ROMs ;n par.tlle! to form a 64k x 8 ROM . 10-3 Sixteen64k x 1 ROM s 10-4 See Figure 10-88. FIGURE 10- 88
}Aoo.
}A"""" '
1/00
110,
I I
--;:::: r
II 10-5 ROM I: 0 to 524.287: ROM 2: 524,288 to 1,048.575
SELF-TEST 1. (b)
2. (c)
3. (c)
4. (d)
5. (a)
6. (d)
7. (CJ
8. (a)
9. (b)
10. (f)
J I. (e)
12. (d)
LOGI CHAPTER OBJECTIVES
CHAPTER OUTLINE
11 - 1 11-2
Programmable Logic: SPLDs and CPlDs
Di)(:Uji
Alter., CPlDs
explain their bolsic Itructure
the type!. of progr~mrnablc logic, SPlDs and CPlDs, .. nd
11-3
Xilinx CPLDs
11-4
Macrocells
11 - 5
Programmable Logic: FPGk
Deicnbe the <1rcnitecture of the Alte", MAX. 1000 family of
11 - 6
A1te~
cpw.
t 1- 7
Xilinx FPGAs
11 - 8
Progr3mmable logic Software
11 - 9
Boundary SCitn Logic
•
DeKnbe the balic architedure of two types of SPlO!., the PAl and the GAL
FPGAs
DeKnbe the ",rchitecture of the Altera MAX II CPlD
•
Explain the billie structure of a prog... rnmable logic alTay (PLA)
11 - 10 Troubleshooting
c::tI
Oigibl System Applic.. tion
-
D~ribe
the ~rchitectu re of the Xilinx CooIRunoer II family of
INTRODUCTION
CPLIX Di~uSl
the oper~t:ion of macroceUI
Diltinguim between CPUli ~nd FPGI\! Exp l~in the b.uic operation of ~ look-up table (LlIT)
Define intellectual property and platform FPGA Describe the
~r(hitecturc
of the Altera Stratix fPGA family
Dilcuss embedded functions Deicri/)e the architecture of the Xilinx Virtex FPGA Show ~ basic loftw~re deign flow for a
f~mily
programm~ble
device
&pl~in the design (low elemenb of design entry, function~1 simulation, synthesis, impfementation, timing simul~tion, ~nd downloading
Disa.Jss several methods of teting a programmable logic device, including boundary scan logic
KEY TERMS
PAL
Schematic entry
GAL
Text entry
Macrocell
Compiler
Registered
Downloilding
CPLD
Bed-of-nilils
LAB
Flying probe
lUT
Boundary Kan
f PGA
Primitive
ClB
Fitter tool
Intellectual property
Functional simulation
Design flow
Timing simuliltion
In this chilpter, the bilsie ilrchitecture (internal structure and organization) of SPlDs, CPLDs, and FPGAs is discuued. Several specific CPLDs are introduced, including the Altera N\AX 7000, N\AX II, and theXilin" Coo/Runner II . Ff'GAj that are introduced are the Altera Stratix and the Xilin" Virtex. A discunion of softwilre development tools coven the generic design flow for programming a de,.;ce, including design entry, functiona l simulation, synthesis, implementation, timing simulation, ilnd downloading. Also, there is a section on in-circuit troubleshooting of a circuit board once the programmable device is operating. Test methods include bed-of-nails, flying probe, and bounda/)' scan. •••
DIGITAL SYSTEM APPLICATION PREVIEW
The Digital System Appliciltioo iliustr.Jtes a generic design flow process for programming the logic for driving a 7segment display. The logic for each segment was developed in the Digital S~tem Application in Chapter 4 and VHDL programs were written for each one. You could enter the VHDl progr.J ms using.J text ent/)' softw.Jre tool. However, we will ill ustrate the design flow with a generic schermtic entry app roach .
-";';C;;'.
COMPAN I ON WEBS ITO . - - - - -- - --
Study a ids for t"is chapter are a\lailable at http://www.p renh.JJl.comlfloyd
Target device
605
606
•
11-1
PROGRAMMABLE lOGIC AND SOFTWARE
PROGRAMMABLE lOGIC SPlD, AND CPLD, Two maj or types of simple programmable logic devices (SPLDs} are the PAL and the GAL. PAL stands for programmable array logic. and GAL stands fo r generic array logic. Genemlly. a PAL is o ne-time programmable (OTP). and a GAL is a type of PA L that is reprogmmmable: however. because some reprogramma ble S PLDs are still called PAL~, the line between PALs and GAL~ is a lillie vague in common usage. The te rm GAL is II designation originally used by Lattice Semicond uc tor and later licensed to other manufacturers. The basic struct ure of both PALs and GALs is a programmable AND array and a fixed OR array. which is a basic sum-of-produc ts archi tecture. The complex programmable logic device (CPLD) is basically a si ngle device wi th mu ltiple SPLDs thai provides more capacity for larger logic des igns. Afte r completing this sectio n, you should be able to • Describe S PLD 0pcrJ.tion _ Show how a sum-of-products expressioll is implememt:d in a PAL or GAL . Explain s implilil'1.l PAUGAL logic diagrams _ Describe a b.1,Sic PAU GAL macrocc11 • Discuss the PA.LlfiVR and the GAL22V IO _ Describe a basic CPLD
SPLD, The PAL A PAL (programmable aIT'dy logic) consists of a programmable array of AN D gales that co nnccts to a fi xed army of OR gates. Gc nemll y, PAL~ a re implemented wilh fuse process technology lmd are, therefore. o ne-time progmmmable (OTP). 'nle PAL stnlc ture allow.. a ny ~ um - o f- producl s (SOP) logic ex prc~s i on with a defilll.-'1.i number of variables to be implemented. As yo u have learned , any combinatio nal logic functio n can be expressed in SOP form . A s imple PAL struc ture is shown in Fi:;ure 11- 1 for two input varia bles a nd one output: most PAL~ have many inputs a nd many outputs. As yo u learned in Chapte r 3, a programmable array is essentially a grid or matri x of conductors that fo rm rows and colu mns with a prog rammable link at each cross point. Each programmable link, which is a fu se in the case of a PAL. if> called a cell. Each row is conn(."Cted to the input of an AN D !!ate, and each column is connected to an input variable or its complement. By programmi ng the presence o r a bsence of a fuse c()nnectioll, a ny combination of input vari abl e_~ o r cumple ments can be ll ppl ied to a n AND gate to form any dcs ired product te rm . The AN D gates are connecled 10 a n OR gate, creating a sum-ofproducts (SOP) output. FIGURE 11-1
A
&sk ANDIOR Itruchsre of a PAL
r"
•
"
"
)'I
,
"
)-
x
PROGRAMMABLE LOGIC: SPLDs AND CPLDI
•
607
An example of a simple PAL is progrommed as shown in Figure 11- 2 so that the product term AB is produced by the top AND gate. AB is produced by the middle AND gale, and AB is produced by the bottom AND gale. As you can see. the fuses are left intact to conneclthe desired variables or their complements to the appropriate AND gate inpul.'>. The fu ses are opened where a variable or its complement is not used in a given product term. The final output from the OR gate is the SOP expression. Implementing a Sum- oF- Products ExpreHion
X = AB
+ A B + A 11
,\
FIGUR E t 1-2
/I
PAl imp rement~tion of a sum-ofproductl exprdsion.
)\ )
X = AR-+-AH-+-AH
)-
I'
5PLD, The GAL The GAL is essentially a PAL thai can be reprogrammed. It has the same type uf AND/OR organization that the PAL does. The basic difference is that a GAL uses a reo programmable process technology, such as EEPROM (E"CMOS), instead of fuses, as shown in Figure 11- 3.
"
/I
n
fiGURE 11 - 3
Simplified GAL ~ "ay.
lit
x
608
•
PROGRAMMABLE LOGIC AND SOFTWARE
Simplified Notation for PAl/GAL Diagrams Ac tual PAL and GAL devices have mallY AND and OR Bates in addition to other elelTll".l1I s and arecapllble ofhalldling many variables and their complemems. Moot PAL and GAL dia!! rams that you may see on a data sheet use simplilied nOlation, as .Ilustr.lted in Figure 11 -4, 10 keep the schcmatic from being 100 complicated .
.
Input lincs
Input l-oufler
,
A
H
,-1-:> I!
Fi~nl ~-.mn~""tjon
/
>
Stn:;lc line "ilh ~I:lloh kpr"""m, muhipk Af\O .gUI~
il\put~
,
line:;
lhi~l-..I>C.
2 illpuI»
y
2
PrudUCI
l in
\ AiJ
2
.J 2
I'u,,", hl"\\"11 ..... n~"" lmn)
Ino~·
\
AI!
Fu-.: 111\;1<;1
tClIflne<.:twn)
FIGURE t 1- 4
A portion of a programmed PAl/GAL
The input variables to a PAL or GAL are usually buffered to prevclltloading by a large number of AND gate inputs to which they arc connected. On the diagram, the triangle symbol repre!;el1ls a buffer that produces both the \~.l ri able and its compleocllt. TIle fixed connect ions of the input variables amI buffers are shown using standard dOlnolation. PALs and GAls have a large number of programmable interconnection lines. and each AND gale has multiple inputs. Typical PAL and GAL logic diagmrns Jcpresenl 1"1 multip1cinput AND gate with an AND gate symbol having a si ngle inpul line wilh a slash and a digit represcming the actu
i EXAMPLE 11 - 1 Show how a PA L is progr
Solution
+ ABC +
AB
+ AC
The pmgramrm:d arrdY is shown in Figure I 1- 5. lhc inlact fusi ble by small red Xs. The
I jnk~
are indicaled
PROGRAMMABLE lOGIC: SPLD$ AND CPLDs
,\
n
8
c
•
c
'" "
~
c 3
~ - '"C
3
3
3
I FIGURE I t
Related Problem·
.," )-£
S
Wrile the expression for the OUlpu! if the fusihlc links cOImccting inpul A 10 the top row and to the bottom row ill Figure 11- 5 are also opent.'d, · Answcrs arc althe end of the chaplcr.
PAL/GAL General Block Diagram A block diagmm of a PAL or GAL is shown in Figure 11 -6. Remember. the basic difference is that a GAL has a reprog ramma ble array and the PAL is one-lime progmmmable. The programmable AND array OUlpUiS go 10 fixed OR gales Ihal are cOllllccled to additiOlUlI ('o Ulput logic. An OR gale combined with ils associated oUlput logic is typically called a tnocrocell. The complexity of the macrocell depends on the particular device. and in GALs il is often repmg ranllnable.
Maaocells A ma crocdl genem lly consislS of o ne OR gale a nd some associated output logic. The macrocell s vary in complexity, dependi ng on the panicular type of PAL or GAL. A macroce ll can be config ured for combinational log ic . reg islered logic, or a combinalion o f both . Rl!gisll!rl!d logic means thai there is a fl ip-flop in the mac roce ll to provide for sequentia l logic fu nclions. The regislcrcd operation of macrocell s is covered in Section 11 -4. Figure 11 -7 illustrates tim.'e basic types of macrocells with combinational logic. Part (a) shows a simple rnacrocell wilh the OR gate ano an inveril..T with a tristate controllhat can make the illvel1er like an open circuil lo complelely disc0llllect the output. 1lte output of the tristate invt:.lt:r can be either LOW. H IG H, or disconnected. Pan (b) is a macrocelJ that can be either
6 09
610
•
PROGRAMMABLE LOGIC AND SOFTWARE
FIGURE 11 - 6
Mao:;rot.... lI,
General block d;
GAL
ORarrny
11 = - "
OR gate
Output
OR gale
Ompul logic
OR gate
OUlp ,1I logic
OR sale
OuIP)t
01
logic
I)
11 =
, ,,, ,, ,, ,
--
,, ,,, ,,, ••, ,
Pn~rJrn"mb[c
02
AND army
PAL: On.e-lime pmgrmnmabJc GA L: Reprogr.:lI11mablc
,, [,, = --
logK
0
0.1
0 ...
an input or an OUipUl. When the output is used as an input the tristate invener is disconnected, and the input goes to the butTer that is connected (0 thei\ND arTIly. Part (c) IS a macroceli rhal call be progmmmed to haveeithcr an active-HIGH or an active-LOW outpul, or it can be used as an input. One input to the exc\usiye-OR (XOR) gate can be progra nllned to be either HIGH
!'romAKD
Trhlall" c"l1lml
g~l~
FmtflANI)
>a-C)
>a~-CJ tnpullDulplJl (1101
Qmput
(b) Combinational inpm/'llJ!pu! {a...1i\'c-LOW)
(a ) Combinaliunal OU' po.'l ( ueth'e-LQW). An active-HIGH
output would be ~tK'wn wilhoo llhc gmcsymbol.
.urny
bubble on .he lriSla.,.,
Fn,m AND ===r-~,_s-\\"-"
"-
>C",---<~ Inpuu'OmpulllJOt
Progrrunmabl~
'"~ (c) Progro um",bl c poturity output FIGUR E 11 - 7
B'llk types of PAl/GAL macrocell! for combinational logic.
PR.OG R.AMMABLE lOG IC: SP l D$ AND C PlDJ
•
6 11
or LOW. When the programmable XOR input is HIGH. the OR gate output is invel1ed because 0 EB I = I and I e I = O. Similarly, wilen the programmable XOR input is LOW. the OR gate output is not inverted bcc
Specific SPLDs Generally. SPLD package configurations range from 20 pins to 28 pins. Two factors that you can use to he lp determine whether a cenain PAL or GAL is adequate for a given logic design arc thc number of inputs and outputs and the number of equivalem gates or density. Other paramete rs to consider are the maximum operatillg frequ ency. de lay limes. a nd dc supply voltage. Lattice, Actel, At mel, and Cypress are among several companies that produce SPLDs. Various SPLD manufacturers may have d ifferent ways of defining dellsit)'. so you have to use Ihe speci fi ed number of equivalent gates with this in mind. The 16V8 and the 22V IDare common types of PALs and GA I_". The device designation ind icates the number of inputs, thc number of outputs, and the type of output logic. For example. 16V8 means that the device ha<; sixteen inputs, eight outputs, and the outputs are variable (V). The teller Lor H means the output is aclive-LOW or active-HIGH. respectively. The block diagram for a PAL l6V8 and a typical SPLD package are shown in Figure 11-8.
fIGUR E t 1 - 8
7
II
M:noccll
01
Macroce ll
U0 1
7
IJ
7
Mac.occ ll 14
--=
1102
7 15
Macmce ll
1103
Mal'flJO.:cll
1""
MalTOCell
U05
MacJOCC II
1/06
Prngrammable
At\Oanay
" 17
"
7
7
7
[9
7 110
Ma~-roce11
logiC block di~g..,m of" PAL1 6V8 and typi",' SPLD package.
612
•
PROGRAMMABLE LOGIC A N D SOfTWARE
Each macrocell has e ight inputs from the AND gate army. so you can have up to ei!lht proouctlerms for each output. There are ten dedic-dIed inpuls(l), two dedicated OUlput~ (0), and six pins thaI can be used as cither inputs or outputs (VO). Each output is active-LOW. The PAL 16V8 has a density of approximately 300 equivalcnt gatcs. A block diagram for a GAL22V 10 and a typical SPLD package are shown in Figure 11 - 9. Thi s device has twelve dedicated inputs and ten pills that can be either inputs or outputs . The macrocells have inputs from the AN D atT
8
" I'
Macro..·cJ l
110 1
MaCJ{)..'C1i
1102
Macroccll
1103
Macmccll
001
"
Mam:x:cli
11O~
"
Macroccll
1/0<\
Macroccll
U07
Macroccll
U08
Macro."eH
"""
Macr~ JJ
J)()1fl
1O
'-'
" 14
"
EICMOS progr~mmable
17
AN D Mnly
"
14
I"
1111
I"
111
FIG URE 11 - 9
Bled; diagram of the GAUZVIO and typiCC'l I SPLD package.
" 10
"
PROGRAMMABLE LOGI C: SPLDs AND CPLD$
•
TheCPlD A C PLD (complex progmmmable logic device) consists basically ofmullipleSPLD arrays with programmable interconnections, as illustrated in Figure 11- 10. Although the way CPLDs are internally organi7..ed varies with the manufacturer, Figure 11- 10 rep resents a generic CPLD. We will refer to each SPLD army in a CPLD as a LA B (logic arro:lY block). Other designations are sometimes used . such as jUllclion block, logic block, Or g€ll€ric block. The programmable inlerconneClions arc generally called the PIA (progr.munable interconnect arro:ly) although some manufacturers. such a.. Xi linx. use the term A IM (advanced interconnect matrix) or a similar designati0n. The LABs and Ihe imerconnections between l ABs are programmed usi ng sart ware. A CPLD can be programmed for complex logic fu nctions ba~ed on Ihe SOP slruclure of Ihe individual LABs (actually S PLDs). Inputs can be connected 10 any of the LABs, and their outputs can be interco nnected to any other LABs via the PIA.
tlO
¢::::::>
Logicarrar b lock (LAB) SPLD
ItO
¢::::::>
Logic arr3)' block (LAB)
SPCD
I/O
¢::::::>
Logic array block (LAB) SPLD
I/O
¢:::::::>
Logic array bklck (LAB) SPLD
• .-.. .-..
.-.. .-.. .-.. .-.. P'A
.-..
~
FIGURE 11 - 10 Bilsic block diilgl
SPLD
Logicarrny block (LAB)
~ 'IO
SPLD
Logic army block (LAB)
SPCD
~ ""
Logic array block (LAB)
..-
CPlD.
~ 'IO
SPLD
Mosl prog rammable logic manuracturers make a series ofCPLDs that runge in density. process technology. power consumption, supply vohage. and speed . Manufacturers usually specify CPLD density in terms of macrocells Or logic array blocks. Densities can ro:Inge from tens of macrocells to over 21XXl mal:rucells in packages with up to several hundred pillS. As PLDs become more complex, maximum densities will increase. Most CPLDs are reprogrammable and use EEPROM or SRAM process lechnology for the programmable links. Power cOllsumplion can mnge from a few mi lli watts to a few hundred milliwaus. DC supply voltages are typically from 2.5 V to 5 V, depending on the specifi c device. Several manufac turers. (for example. Altera, Xili nx . Lattice. and Cypress) produce CPLDs. In this chapleT. we wi ll focus on Altem and Xi linx products becausc Ihey arc two of the maj or companies in the market. The other companies Mfer simil ar devices
iI
gene.;c
613
614
•
PROGRAMMABLE lOGIC AND SOFTWARE
and software, and you call easily make a transition to other products once you are familiar wit h one or two. As you wili lcarn, CPLDs and other programmable logic devices are really a combination of hard ware and soft ware.
SECTION 11-1 REVIEW AnlWefl are at the end of the chapter.
1. What does PAL sta nd for? 2. What does GAL stand for? 3. What is the difference bet\l.leen a PAL and a GAL?
4. B... si~lIy, wh ... t does ... rTliIuocell contain? 5. What i.i ... CPLD?
ll-Z
AlTERA CPLD. Altera produces several families ofCPLDs including the MAX II. the MAX 3000, and the MAX 7QC() family. In this section. the focus is mainly on the MAX 7000 to ilJu.~ trate the concepts of traditional CPLD architecture. keeping in mind that other series may vary somewhat in architecture and/or in parameters such as density. process tL-chnology, power consumption. supply voltage. and speed. After completing this section, you should be able to • Describe a typical MAX family CPLD • Discuss the basic architecture of the MAX 7000 and tbe MAX rr CPLDs • Explain how product terms are generated in CPLDs
MAX 7000 CPlD The architecture of a CPLD is the way in which the internal elements are organized and arranged. The architecture of the MAX 7000 fa mily is similar to the block diagram of a generic CPLD (shown in Figure 11 - 10). It has the classic PAJ.JGAL structure that produces SOP functions. The density ranges from 2 LABs to 16 LABs, depending on the particular device in the series. Remember, H LAB is roughly equivale nt to one SPLO, and package sizes vary from 44 pins to 208 pins. The MAX 7000 series of CPLDs uses the EEPROMbased process technology. In-system programmable (lSP) versions lise the JTAG standan.l interface. Figure Il ~ 11 shows a general block diagram of the Allera MAX 7000 series CPLD. Four LABs are shown. but there can be up to sixteen, depending on the particular device in the series. Each of the four LABs consi sl~ of sixteen macrocells, and multiple LABs are linked together via the PIA. which is a programmable global (goes to all LABs) bus stmcture to which the general-purpose inputs. the 1/0s. and the macrocells are connectC(\. The Ma crocell A simplified diagram of a MAX 7000 series macrocell is shown in Fig ure 11 ~ 1 2. The macrocell contains a small progr.1mmable AND array with five AND gates, an OR gale. a product-ten n selection matrix for connecting the AND gate outputs to the OR gate, and associated logic that can be programmed lo r input. combiTlationa llogic output. or registered output. l h is macrocell is covered in more detail in Section J 1-4. Although based on the same concept, this macrocell d iflers somewhat from the macrocell discussed in Section I I ~l in relation [0 SPLDs because il comains a portion of [he
ALTERA CP LD,
C..:rx:ml
pu~
mJLAIJ
I
110 control
"""" , ,,, ,
8- 16
, •,, ,,, ,,
!!
!
!!!!
Logic RfllIY bkxk (U\B A)
Logic nmr.y bIocl:: (LAB B)
I I
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,
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,,• ,, M:lCnlcd l 16
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I
8-16
~
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Logic army bloc!.;: (LAB C)
u l(!ic arflOY block (LAR ])
I I
I I
I
Macrocell l
f.1acroct1l2
,, ,, , ~'lacmcell
16
I I I
,
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l6
36
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16
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8-1.
I
MacrOCl:' II I
Macroccl12
, ,,, , Mac:mcell 16
•• ••
• ••
fiGURE 11 - 11
Basi<: block diagr;,m of the Aile ..... MAX 7000
~ries
CPLD.
progmmmable AND array and a product-term selection malrix. As shown in Figure 11 - 12, fi ve AND gates feed product terms from the PIA into the product-term selection matrix. The product term from the bottom AND gate can be fed back inverted inlo Ihe progr.lmmable aIT.lY a.; a shared expander for use by other mac roce ll ~. The par.llle l expander inputs allow lx>fTOwing o f unused product terms from other macrocells 10 expand an SOP expression. The producH crm selection matrix is an arrdY of progrdmmable connections thai is used 10 conncct selected OUlputS from the AND army and from the expander input.'; to the OR gale. A complemented product lerm that can be used to increa..e the number of prodUCI terms in an SOP expre !t~ ion is available from each macrocell in a LAB . Figure 11- 13 iIIuSlI'alCS how a shared cxpandcr lenn from another macrocell can be used to create additional product tcrms. In this cao;c, cach afthe five AND gate~ in 3. macrocell array is limited 10 four inputs and, the refore, can produce up to a 4-variable product term, as illustrated in part (a). Fil,'llre 11 - 13(b) shows the expansion to two product terms. SIuJ,ed fJ
I I
110 ~1rOI
PIA
C{>fllrol block
,, ,
615
nrpu'"
II 16110
•
I I
110 <-"'OIllmi
block
,, ,,, ,
,, ,,, ,, ,,
8-1'
I II
616
•
PROGRAMMABLE LOGIC AND SOFTWARE
, ,,
Parallel e~pandcn rrom ()Iher macrocclls
I
8= 8= -D----3(,
'"
hnc-' frum PIA
---
/1
, ,,, ,,
!
-,--"
Product-lam selcctioo
manu:
G-
Associated
logic
~
-
10 110
control block
1
-- --,,
s""""
expander
'.J
IS c1.pandcr prodUCI lerms from
( ~hcr
ma<:m.:e iJs FIGURE 11 - 12
Simplified djagrilm of a macroce ll in
iI
A_ ,-_____
FIGURE 11 - 13
now
B C
u.,mp le of iI Io., red el
terms.
MAX 7000 series CPLD.
AHO£ t-
"-J=AHCI:: +A HCF
) - AHCD F+F
(a) A 4-inpul AND arra), gale can produce o ne 4- ' 'llfiable product 1CTll1..
1--- EF
Producr term rrom aoo!ocr macrocell in same LAB
(b) AND gate is expanded 1<, produce ' wo producttcm,s.
Each MAX 7000 macrocell can produce up 10 five prcxluct terms generated from its AND array. If a macrocell needs more than five prcxluct terms for its SOP output, it can use an expander term from another macroc:ell. Suppose that a design requires an SOP expression thai contain.'i six prcxluci terms. Figure 11- 14 shows how a product tenn from another macrocell ca n be used to increase an SOP output. MacroceH 2. which is underutilized, generales a shared expander term ( E + F) thai connects to the fi fth AND gate in macrocell I to produce an SOP expression with six product terms. The red Xs and lines represent the connectioos produced in the hardware by the software compiler running the programmed design. Another way to increase the number of proouct terms for a macrocell is by using parallel expanders in which additional product tenns are ORed with the lemlS generated by a macrocell instead of being combined ini.he AND array, as in the shared expander. A g iven macroce ll can borrow unused producttenns from neighboring macrocells (up to fi ve product terms from lhree other macrocells for the MAX 7000). The basic concept is illustrated ill Figure 1/- / 5 where a simplified circuit that can produce two product temls borrows three additional product teons. Parallel EKpanden
ALTERA CPLDs
,,
•
~ l acrocclll
,
R k"
ABCD+ABCD+A HCD +AHCD+ ABCE+ ABCF ~
I
L-/
-
---
Product-tenn 5elcction
I
EAJlIIntIcr ..:rm~
mHtrix
,,,
Macroccl12
r----
~ ~
-~
;\HCD+AHCD+A
- -
EF
ProdUCI-lcnn
/l \
---
I
.sck:clioll mlmix
'-J
hxpml!Jer (emIl:. + F 10 Macroccll I
H
c
D
r
FIGURE 11 - 14
Simplified illustrAtion of uling it lhared ecpandet" tenn from itnother INcroce/1 to
jncreit~
an SOP
expt=ion.
AHCD + ABCD + EFGH
-
Parallcl expander lerms
FIGURE 11 - 15
Balic concept of the ~r.tllel ex~ndef.
AHCD + £FGII + AHCD .. AHCD + rFGH
Figure 11 - 16 shows how one macrocell can borrow parallel expander lemls from another macroccll to increase the SOP output. Macrocel! 2 uses three product terms from macroccll 1 to produce an eight-term SOP expression. The red Xs and lines represent the connections produced in the hardware by the software compiler running the programmed design.
617
618
•
PROGRAMMABLE LOGIC AND SOFTWARE
,, ,
Macrocell I
"~
g
AHCD. A/JCD +AHCIl P.~ra lld e~P
ProdUCl-lcnn sc\ccliOil fTllUrix
I
---
lcnn'
lna ....'I.llo Mao.:,n.; d l ~
Macrocell 2
.
.
,
,
s= D- b,I h
.
r---
·lHCD + ABCD + ,tHCD .,IHCD+AIJCD+ ARC/) + ,t/ICD + ABCD
ProdLICI-\crm
seLection
/1
i>" H
c
v
I
matrix
---
•
F
FIGURE 11 - 16
Simplified ill ustration of using p
The MAX 1/ CPLD The architecture of the MAX II CPLD differs dramaticall y from the MAX 7000 fami ly and is what AJtera calls a "post-macrocell" CPLD. As shown by the block diagram in Figure 11-17. this device contains logic array blocks (LABs) each with muh iple logic e lements (LEs). An LE is the basic logic des ign unit and is analogous 10 the macrocell . The programmable interconnecls are arranged in a row and column arrangemen t running between the LABs. and inpuUoutput clements (TOEs) are oriented around the perimeter. The architecture of this fami ly of CPLDs is similar to that o f FPGAs. which we discuss in Section 11- 5. In fac t. you could think of the MAX II as a low-density FPGA. A main difference between the MAX II CPLD and the classic SPLD-based CPLD is the way in which a logic function is developed. The MAX II uses look-up tables (LUl) instead of AND/OR arrays. An LVT is basically a type o f memory that can be programmed to produce SOP functiOns (discussed in more detail in Section 11- 5). These two approaches are contrasted in Figure 11 - 18. As mentioned, the MAX 1I CPLD has a row/column arrangement of interconnecl.~ inslead of lhe Channel-type inrerconoc'Cts found in most classic CPLDs. These Iwo approaches are contmsted in Figure 11-19 and can be understood by comparing Figure II_ II and Figure J 1- 17.
ALTERA CPlOJ
L-_'O_~__~I ~I__'O_~__~I ~I__'O_~__~ LAB
II II
Logic elel1'll:nt
10Es
Logic c lc mclll
II
, ,,
,, Logic elcmcnt
LAB
I
Logic element
10Es
I
Logic element
, ,,, ,
I
Logic element
I I I I
LAB
Logic elel1'll:nt
Logic c lcmelll
I II
,, ,,
, Logic elcmelll
I I I II
LAB
Logic element
Logic element
I
II
,, ,,,
Logic e lement
•
619
FIGURE l ' - l1
Simplified block diagram of the
MAX II CPLD.
LAB
I I I I
Logic element
Logic clement
I I
,, ,,,
I I
logic clcmentJ
I I I I
I II
LAB
Logic element
I
Logic element
I
,,, ,,
Logic element
I ... FIGURE 11 - 18
A" A,
A,
,, ,,
LIfT
I
MAX II CPLDI have lUT logic. O"llic
"
CPl~
"
SOl'
SOP
outpUt
outpUl
have AND/OR arra)'i.
ll ~ J
(a) LouI::-up t
(b) AN D/OR army logic
FIGURE 11 - 1 9
0000 0 00 0 000 0000 0 0 0 0000 0 000000 (ill) Rowlcolum n illterconllccll;
DO DO DO DO DO (b) ChanllCl-type imcroonncct
MAX II CPLDI hClVe row/column interconnects. O"Slic CPlOs have channel-type interconnects.
620
•
PROGRAMMABLE LOGIC AND SOFTWARE
Most CPLDs use a nonvolatile process technology for the programmable links. MAX n. however, uses a S RAM-based process technology that is ,'olatile-all programmed logic is lost when power is turned off. 11le memory embedded on the chip stores Ihe program data using nonvolatile memory technology and reconfigures thc CPLD on power up.
i
SECTION 11 - 2
REVIEW
1. What does LAB stand for7 2. Describe a LAB in the MAX 7000 CPill. 3. What is the purpme of a shared expander? 4. What is the purpose of a parallel expander? 5. How does the MAX II differ from the MAX 70007
11-3
XlliNX CPlD, Xilinx. like Altern, makes a series of C PLDs rnat range in density, process technology, power consumption. supply voltage. and speed. Xilinx produces several families of CPLDs including Cool Runner II, Cool Runner XPLA3. and the XC9500. The XC9500 is similar in architecture to the Altera MAX 7(X)() CPLD family and exhibits the classic PAUGAL structure. In this section, we will focus on only the CoolRunner lIto illustrate the concepts, keeping in mind that other series may vary somewhat in architecture, and/or in the parameters previous ly mentioned. T his fam ily ofCPLDs is in-system programmable and JTAG compliant. After completi ng this section, you should be able to • Describe a PLA and compare to a PAL • Discuss the architecture of the Cool Runner 11 CPLD • Describe a funct ional block
PlA (Programmable logic Array) As you have learned. the architecture of a CPLD is the way in which the internal elements arc organized and arranged . lbe architecture of the Xilinx CoolRunner fI family is based Of] a PLA (programmable logic array) structure rather than on a PAL (progmmmable array logic) structure. Figure 11 - 20 compares a simple PAL structure with a simple PLA slruc-
A A
8
8
A A
B
H
(a) PAL-type array
AB+AB L _ - AB+AB L "-- -(b) PLA-Iypc array
FIGURE 1 1 - 2 0
Comparison of a wlie PLA to 11 ~ie PAL
-
-
- AB+AH -
A8+"H
XllIN.x
CPLD~
ture. As you know, the PAL has a programmable AND array fo llowed by a fi xed OR array and produces an SOP expression, as shown by the example in Figure 11 - 20(a). The PLA has a progranunable AND array followed by a programmable OR array. a.~ shown by the example in Figure 11 - 20(b).
Cool Runner II The CoolRunne r II CPLD uses a PLA type structure. This device has multiple fun ction blocks (FB s) that are analogous to the LABs in the Altem MAX 7000 (Figure' 1- 11). Each function block contains sixteen macrocells, just as the LAB does. The function blocks are interconnected by an advanced interconnect matrix (AIM) that is analogous to the PIA in the MAX 7000. A basic architectural block diagram for the CooIRunncr II is shown in Figure 11 - 2 1. As you can see, from a basic block diagram point of view, Funcli{)n block (FBl
Functi{)n block (FB)
II"'0 I-
Macroccl1 I
Macrocelll
Macrocc112
,
40 PLA
M'lCroccll J
,,
,
Macrocc1l 2
40
~
I'LA
, I- -1
00
Macroccll 16
I-
Macrocell l
I-
Macrocc ll 2
I-
Macrocc ll 3
,, ,
I- -1
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I.
AIM 40
40
PI-"
!'LA
Macroccll 16
I
,
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16
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Macrocell J
I-
Macrocell 16
l-
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Mocmccll 3
I-
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l-
,, ,
, ,,
00
00
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I00
Macroccll 1
,-
Macroccll 2
I-
Macroccll 3
-
,,,
-1
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I
Macroccl1 I
40
Mncroccl l 2
40
PI-"
PI-"
Ma(:rocc Il 3
,,
III-
,
I.
I.
16
16
FIGUR E 11 - 21
Basic architectvral block diagram of the Xilinx CooIRvnner II CPLD.
Marnxell 16
l-
00
•
621
622
•
PROGRAMMABLE l OGIC AND SOFTWARE
there is not much d iffere nce between the Xili nx CPLD and the AHera CPLD; however, internally there arc diffe rences. 1l1e CoolRunner II serier. of CPLDs contains from 32 macrocells to 5 12 macrocelJs. Since there are sixteen macrocells per funct ion block, the number of function blocks range from 2 to 32. A greatly simpl ified d iagmm of a funclion block (FB) is shown in Figure 11 ~22. The programmable AND array has 56 AND gate..<;, and the progmmmable OR array has 16 OR gates. With the PLA slI1lcture. any product term can be connected to any OR gate to create 1m SOP output. With maximum utilization, each FB can produce 16 SOP outputs each with 56 product ten ns. This macroceJl is covered in delai l in Section 11-4.
-I-t---+--+---/--I ' --I-t----I-t-- __~ 3
--++-+1---7"--1 " frum AIM A!>."ocialoo logic rOl"cach mocroccJ)
FIGURE 11 - 22
Simplified di... gr... m of ... Coo/Runnel" II function block (FB) with.it PLA structure.
I
EXAMPLE 11
~2
Show the programmed connections in the simplified FB of Figure 11 ~22 to produce the following SOP function from macrocell 1: ABeD + ABeD + ABe D and the following SOP fu nction from macrocell 2: ABeD + ABeD + ABCD + ABCD.
Solution
Related Problem
The red Xs in Figure arrays.
11 ~23
indicale programmed connections in the AND and OR
How many SOP functions can be generated by the FB in Figure 1 1 ~23?
MACROCElLS
AIJCD AIJCD
~
='
ABCD A8CD ,\8CD ABeD ABCD
,,, Sum-term
Proc\ucHcrm ~,
I
"
8
C
f)
)~--:~- ~6
16 ruocroct'lI~
ABCD + ,l IJCD+A8CD+ABCD AileD +A8CD + AHCD
FIGURE 11 - 2]
I
SECTION 11 - 3
REVIEW
1. What is the main difference between the Alte ra and the Xilinx CPlOsl 2 . Describe a PLA
3. How does a PtA differ from a PALl 4. What doe fB stand for?
11-4
MACROCEllS
C PLD macrocell s were introduced in the previous sections fo r both A ltera and Xilinx devices. Recall that a macroceJl can be configured for combinationa l logi c or registered logic outputs and inputs by programming. The tenn registered refers to the use of nip-n ops. In this .~ec lion , you will learn about the typical macroceLl , including the combinatio nal and the registered modes of operation. A lthough macrocel1 architecture varies among different CPLDs, representati ve devices arc used for illusn atio n. After completi ng this section, you should be able fo - Describe the operation o f an Altera MAX 7000 CPLD macrocelJ _ Describe the operation or a Xilinx CoolRunner II CPLD macroccll
_
623
624
•
PROGRAMMABLE LOGIC A ND SOFTWARE
Logic diagrams often use the symbol shown in Figure 1 1 ~24 to represent a multiplexer. In th is case, the multiplexer has two data inputs and a select input that provides for programmable selection: the select input is usually not shown on a logic diagram.
'''" '''PO'' {::
=y-"",
Sclc<:t /0 select'
~~
I ","leels
FIGURE 11-24 Commonly used symbol for a
00'",
mu ltip lexer. It can have a ny number of inpoU .
D!)
The Altera MAX 7000 Macrocell Figure 1 1 ~25 show.~ the complete macrocell including the nip-flop (register). The XOR gate provides for complementing the SOP fu nction from the OR gate to produce a function in POS fonn. A I on the top input of the XOR gate complements the OR output, and a 0 lets the OR output pass uncomplemented (in SOP form). MUX I provides for selection of either the XOR output or an input from the Uo. MUX 2 can be progmmmed to sekct either the global clock or a clock signal based on a product {enn. MUX 3 can be programmed to select either a HIGH (Ved or a product-tenn enable for the flip-flop. MUX 4 can select the global clear or a product-tenn clear. MUX 5 is used to bypasS the fl ip-flop and connect the combinational logic output to the 110 or to connect the registered output 10 the 110. T he flip-flop can be programmed as a D, T (toggle), J-K, or S-R flip-flop.
Global Global
, ,,
I
Parallel expanders from ethel macrocd ls
de,.,.
dock
F~
MUX5
V
-
"""""'" "election
mauh
D"-
---J(i lioe, frmll PIA
r-,-,
I ,, ~ J) ,,, f--/ i-'--.
--- ,,
,
'''"'''
-'" V
-rJ-MUX l
P~E ~ orr
110 '1'0110
Q
~>c r- EN
MUX2
CLR
V
expander
Ij
MUX4
I ~ cxp;!!ILlcr prOOUCI 1'0.111. '"4her
lcnn~
FIGURE 11 _ 25 A m
The {A}mbinational Mode When a macrocell is progmmmed to produce an SOP combinational logic function, the logic elements in the data path are as shown in red in Figure 11 -26. As you can see, only One mux is used and the reg ister (nip-nop) is bypassed.
MACRQCELLS
P:mlliel expanden
,"~
Irom ~""
,""
~I"
"-
d-
MUX5
V 0
h......,. ....
di, O d- "'""'" ..... ->-
I
MUXI
-D'fI hiit"'> from PIA
- --,,
,
PRE Dff
l~
MU~
1-'--
----
625
CIOOoI GIoIxII
,, ,
..
•
v,21kx,
"-
Q
sD-
r EN CUI
"=d
Y
expander
I
MUX4
15 eApanUo:r prodUo.:1 ~ .."ffil'.lrom other ma.:rocell~
FIGURE 11 - 26
A macrocell configu..ed fOf ger>er.ltion of OJ" SOP logic function . Red indoatci dilu path.
The Registered Mode When a macrocell is programmed for the registered mode with the SOP comhinational logic output providing the data input to the register anti clocked by the g lobal clock, the e lements in the dala path are as shown in red in I~ igure 11 - 27. As you can see. rour muxes are used and the register (flip-flop) is active.
,, ,
Parallel cxparider..
GloN.l
C_,
d ear
ck"d.
fmm OIher
macrocclls From
MUXS
V
B= ............ i t> 8= D0
t:,
- . 1-'--
---.,,
...
---'fi lion
'1l!I1l ",,\
~
-{)
~.MUX I
I
-lr
M~j 1'n.
""""
..:=:D
MUX 3
I
MUX4
~,.,..,."
I j "'~fXIJ\ller" prOOucl leml' other
'1l!I1l
FIGURE 11 _ 27 A macroceU configured (or generation of"" regis tered logic function. Red indoaf:eJ data path.
";0£ C EN
CUI
Q •
..rU·
""
626
•
PROGRAMMABLE LOGI C AND SOFTWARE
The Xilinx Cool Runner II Macrocell The macrocell in the CoolRunner II CPLD was imroduced briefly in Section 11 - 3. Recall thai Ihis device uses a PLA architecture. where boIh the AND array and Ihe OR array are programmable. Figure 11 - 28 shows the complete logic for this macrocell. including the flip-flop (regisler). The OR gate has multiple inputs from the AND array as indicated by the slash through the inplll line. The XOR gate provides for complementing the SOP funclion from the OR gate 10 produce a funct ion in POS form. A I on the bottom input of Ihe XOR gate complemems the OR output and a 0 leIs the OR output pass uncomplemented (in SOP form). MUX I provides for- selection of SOP or POS logic outputs. MUX 2 provides for selection of either the XOR output or an input from the 110. MUX 3 and MUX 4 can be programmed 10 select one of lhe global d ocks (GCKO. GCK I, orGCK2) o r a clock signal based on a productterm (eTC or PTe). e TC is a shared lerm and PTC is a locally generated tenn. MUX 5 can be programmed 10 provide eilher polarily of the clock signal. The product term PTC is used to provide a clock enable 10 the flip-flop. MUX 6 can select one of four signals to set the flip-flop . These are PTA (locally generated product term), CTS (shared product lenn). GSR (global set/reset). and GND. which is nonnally selecled when no active SET is required. MUX 7 provides the same functions to dear or resellhe fli p-flop as MUX 6. MUX 8 is used to bypass the flip-flop and connect Ihe combinalional logic output to the I/O or to connect the registered outpullO the I/O. The flip-flop can be programmed as a D, T (toggle). or as a latch.
FeKbock LoAD.1
MUX6 PTA
CTS GSR DND
, ----------t-----ji-i--- -
~m
MU X 8 MUX2
s Ofr
rrc
ToUO Q
CE CK
MUX3 GCKO
Produci-lcrm
MU XS
R
GCKI
arr.. y
DCK2
1--- - 40 from AIM
MUXI Vcc (l)
GND {O )
MUX4
(TC
PTC
MUX 7 pTA
CTS GSR GND
FIGURE 11 - 28
A macroceJl in the Xilinx CoolRunllef" II CPLD.
The Combinational Mode When a macrocell is programmed to produce an SOP combinational logic function, [he logic elements in the data path are as shown in red in Figure 11 - 29. As you can see, only two muxes are used and Ihe register (fl ip-flop) is bypassed.
MACRO CEllS
•
627
I~bad
to
M UX 6
111M
PTA ITS
eSRGND
+-__
r-______________
+-~---- From
I/O MUX 8
MUX 2
PTC
eK MUXJ Pro:.1J(.1-term
arra),
R
J\1UX 5
GCKO GCK I GCK2 -
1 -- -- 40 from A IM
MUX .
MUX 4
MUX7
PTA CIS
GND (O) -
eSR
eND FIGURE 11 - 2'1
A rrncrocdl configured for generation of an SOP logic function . Red indicates dab ~th . The RegiJtered M ode When a macrocell is programmed for the registered mode with the SOP combinational logic output providing the data input to the register and docked by one of the global docks, the e lements in the data path are as shown in red in Figure 11- 30. As you can see, five muxes are used and the register (flip-nop) is active. Fecdboc~
IOA [M
MUX6
PTA ITS
GSR GND
.---------------------+-----e-+------- I/O Fmnl MUX8
MUX2
t---V
GCKO Product-term
M UXI
VccC1>--fj GND (Ol - - { )
PTC
pTA CIS
eSR
GND
FIGURE 11 30
A m.lcnxeU configured
for
I
~
M UX 4
ere
PTC -
MUX-'- {D MU.X5
GCK1 - · GCK2
ami)'
1 -- -- 40 from AIM
- - ---I M
generation of a regiltered logic function. Red indicates dab path.
MUX7
S
CE
CK R
oi-+---l.-J
- - To 110
628
•
PROGR AMMABLE LOGIC AND SOFTWARE
i SECTION 11 - 4
REVIEW
1. Explain the purprue of the XOR gate in the macrocelL 2. What are the two major modes of a macrocell7 3. What does the term retfttered refer to? 4.
Beside~ the OR gate, XOR gate, and flip-flop, v.mat other logic element i~ commonly used in a macroceU?
------11-5
PROGRAMMABLE LOGIC FPGA, As you have learned, the classic CPLD architecture consists of PAUGAL or PLA-type logic blocks with programmable interconnections. Basically, the FPGA (fieldprogrammable gate array) differs in architecture, docs not use PAlJPLA t~ anays, and has much greater densities than C PLDs. A typical FPGA has many times more equivalent gates than a typical CPLD. The logic-producing elements in FPGAs are generally much smaller than in CPLDs, and there are many more of them. Also, lhe programmable interconnections are generally organi'l..ed in a row and column arrangement in FPGAs. Aftcr complcting this section, you should be able to • Describe the basic structure of an FPGA • Compare an FPGA to a CPLD • Discuss LUTs • Discuss the SRAM-based 1-"PCA • DerIne the FPCiA core
The basic concept of an FPGA was introduced in Chapter I. TIle three basic elements in an FPGA are the configurable logic block (CLB), the interconnections, and the inputJ output (1/0) blocks, as ill ustrated in Figure 11 - 3 1. The configurable logic blocks (CLl3s) in nn FPGA are not as complex as the LABs or PBs in a crLD. but generally there are many more of them. When the CLBs are relatively simple, the FPGA architectu re is called fine grained. When the CLBs are larger and more complex, the architecture is called coarse grained. The 110 blocks around the petimcter of the stlUcture provide individually selectable inpUl, output, or bidirectional aecess to the outside world. Thc distributed matri)', of programmable interconnections provide for interco nnection of the CLBs and connection to inputs and outputs. Large FPGAs can have lens of thousands of CLBs in addition to memory and other resources. Most programmable logic manufacturers make a series of FPGAs that range in density, power consumption, supply voltagc, speed, and to some degree vary in architecture. FPGAs are reprogrammable and use SRAM or antifuse process technology for the programmable links. Densities can range from hundreds of logic modules to approximately 180,000 logic modules in packages with up to over 1,000 pins. DC supply voltages are typically 1.2 V to 2.5 V, depend ing on the specific device.
Configurable logic Blocks Typically, an FPGA logic block consisls of several smaller logic modules thai are [he basic building units, somewhat analogous to macrocells in a C PLD. Figure 11- 32 shows the fun~amental configurabJe logic blocks (ClBs) within the g lobal rowlcolumn programmable mlefconn~ts that are used to connect logic blocks. Each CLB is made up of mulliple smaJJer logIC modules and a local programmllble interconnectlhat is used to conneclloglc modules withi n the CLB.
PROGRAMMABLE LOGIC: FPGAs
•
Prugrammahll'
~
~
UO
I/O
110
bloc!;
bloc!;
bloc!;
CLB
----,...
CLB
O _B
---<:::l
JIO block
---<:::l
110 block
---<:::l
I/O
---<:::l
CLB
UO block
CLII
.10 block
CLII
CLB
I/O
CLB
I
I/O
bJock
bk.K:k CUl
---'----
.10 block CLB
~
I n\erconllecllnn~
CLB
CLB
UO bl oc k
block
FPGA
I/O
I/O
I/C
I/O
block
bJock
block
block
FIGURE 11 - 31
Billie structure of ~n FPGA. ClB k
configur~ble
logic block. FIGURE 11 _32
S.nk configul'i)b1e logic block. (CLS,) within the globa l row/co lumn progr~mmable
CIB
(LB
Logic module
I I
Logic mxJulc
Ip
Logic module:
logic module
I I
logi.,; module
I
log ic module
¢:::
interconnects.
'-"".
1=. in\eIl:OllOC(:\
inlcrcOflnt'l;\
Logie module
I
Logic modu le
/
Cit,lha! ",.lumn in1cn::OflIl'''; I
I
¢:::>
629
630
•
PROGRAMMABLE lOGIC AND SOFTWARE
Logic Modules A logic module in an FPGA logic block can be confi gured for combinational logic, registered logic, or a combination of both . A flip-flop is part of the associated logic and is used fo r registered logic. (Aip-flops were covered in Chapter 7.) A block diagram of a typical LUT-bascd logic module is shown in Figure J 1- 33. As you know, an LUT (look-up table) is a type of memory that is programmable and used to generate SOP combinational logic functions. The LUT essentially does the same job as the PAL or PLA docs .
FIGURE 11-33 501'00lpul
Basic block diagram of a logic module in an fPGA.
LUT
110
Logic module
Generally, the organization of an LUT consists of a number of memory cells equal to 11 is the number of input variables. For example, three inputs can select up to eight memory ce lls, so an LUT wilh three input variables can produce an SOP expression with up to eight producttenns . A pattern of Is and Os can be programmed into the LUT memory celi s, as illustrated in Figure 11-34 fo r a specified SOP fun ction . Each 1 means the associated product term appears in the SOP output. and each 0 means thatlhe associated product tenn does not appear in the SOP output. The resulting SOP output expreSS10n IS 2n , where
FIGURE 11 - 34
Scicctioli logie
The balic concept of an lUT programmed for a p<>rtkula r SOP
Memory cells
A2!11Ao
output.
A2!1 1Ao !l2!1 IAo
A" A, A,
112Alllo SOPOUIPUI
A2!1 1Ao A2AIAo A2AI!I() 112111110
WT
PROGRAMMABLE LOGI C: FPG As
I
•
631
EXAMPLE 11 - 3
Show a basic 3-variable LUT programmed to produce the following SOP function:
A01Ao -+- A2AIAo + A01Ao Solution
+ A2AIAo -+- A2AI Ao
A I is stored for each product lenn in the SOP expression , as shown in Figure 11 -35. FIGURE 11-35 Seleclion Iogk:
Memory cells
A2AI Ao A ~AIAo
AzAIAn
A. A, A,
AZA1A!) SOl' oulput
A2AI Ao A2AI Ao " 2AI Ao A2AI Ao
Related Problem
How many memory cells would be in an LUT with four input variables? What would be the maximum possible number of product terms in the SOP output?
SRAM-B.,ed fPGAs FPGAs are either nonvolatile because they are based on anti fuse technology or they are volatile because they are based on SRAM technology. The term volatile means that aU the data programmed into the confi gurable logic blocks are lost when power is tumed off. Therefore, SRAM -based FPGAs include either a nonvolatile configuration memory embedded on the chip to store the pmgram data and reconfigure the device each time power is turned back on or they use an external memory with data transfer controlled by a host processor. The concept of on-the-chip memory is iIIustmted in Figure 11 - 36(a). The concept of the host processor configurdtion is shown in part (b).
FPGA Cores FPGAs, a.~ we have discus....ed, are essentially like "blank slates" that the end uscr can program for any logic design. FPGAs are available that also contain hard-core logic. A hard core is a portion of logic in an FPC" that is put in by the manufacturer to provide a specific function
and that cannot be reprogrammed. For cxample, if a customer needs a small microprocessor as part of a system des ign, it can be programmed into the FPGA by the customer or it can be provided as hard core by the manufacturer. If the emoc-dded function has some programmable fealmes, it is knOWIl as a soft-core function. An advantage of the hard-core Hpproach is that
632
•
PROGRAMMABLE LOG IC AND SOFTWARE
FIGURE 11-36
DDDDDDDDDDDDDDDDDD~~/B
8a-ic concepts of vo latile FPGA configurations.
DDDDDD~nnODDDDDDDDq~
DDDDr - ~tJU . '"'1]00000000 DOOr ,omlCl ' 00000000 DOD ' = JDDDOI llJDDDDDD DOD!.. . .JODDDDDD o CR ;-:;.Ci:O.:;; 0 0 0 0 0 DC .".
(a) Volatile FPGA with on -the-chip non"olatile con figur.ltlOll memory
Programming data
_.1
r-::l L=:J
N()fJY()I ~ [i le
configUJ1llion memo!),
Volatile A'GA
(b) Volmite FPGA with on -boord memory and host proce:;so.-
the same design can be implemented lIsing much less of the available capacity of the FPGA than if the u<;er programmed it in the field, resulting in less space on the chip ("real estate") and less development ti me for the user_ Also. hard-core function s have been thoroughly tested. The disadvantage of the hard core is thai the specifications are fIXed during manufacturing and the customer must be able to use the harrl
l iard core: portion o f CLBs
programmed during manufaclUring for a specific fUIX.1iOll
DDDDDDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDDDDDD 00000000000000000000 0000000 0000000000 -...- ........ 0000000 ..... ...... ..... 0000000000 ......... .... DDDDDlJDDDD 0000000 DDDDDDDODD 0000000 0000000000 00000000000000000000 00000000000000000000 00000000000000000000
____
FIGURE 11-37
BMic idea o( a hard-core function embedded in an FPGA.
RCm:lining CLBs are progr.lmmcd by user.
AlTERA FPGAJ
•
Hard core designs are generally developed by and are the property of the FPGA manufacturer. Designs owned by the manufacturer are tenned intellectual prope rly (lP). A company usually lists the types of inte llectual property thai are avai lable on its website. Some intel lectual properties are a mix of hard core and soft core. A processor that has some flex ibi lity in the selection and adjustment of certain parameters by the user is an example. Those FPGAs containing either or both hard-core and soft-C()fC embedded processors and other functions are known as p hltronn FPGAs because they can be used to implement an entire system without the need for external support device...
I I is ECTlON
,
11 - '
REVIEW
1. How does an f PGA differ fro m a CPL07 doe~
I
2. What
I
3. Describe an LUT and discuss ib purpose.
C LB ltand for?
4. Whilt is the d ifference between a local interconnect and a global interconnect in an FPGA? 5. What is an FPGA core?
L 11 - 6
6. Define the t erm intellectual property in relation to an FPGA man ufacbJ rer.
---------------- ALTERA FPGA.
Altem produces sevcml families of FPGAs including the Stratix II. the Stmtix, Cyclonc, and the ACEX family. In this section. we will focus on oilly the Stratix "10 iJ!u...trate the concepts, keeping in mind that other devices in the family may differ basicalJy in certain aspects of their architecture, afi{Vor in the pammelers such as densitjes. speed. and power. After completing this section, you should be able to • Discuss the basic architecture of 11 typical Str'dtix n family FPGA • Explain how product terms are genef'dted in FPGAs • Discuss embedded functions
The Logk Array Block (LAB) The block diagram of a gcneric FPGA was shown in Figure 11 - 3 1; the architecture oflhe Stratix II fam ily and other Ahem families is similar. They h.we the classic LUT structure for the logic modules, called adaptive logic modules (A LMs) by Altera, that produce SOP functions. Altera also calls the conligul"1lble logic blocks, shown in the gencric device, logic array blocks (LABs). T he density ranges from almost 2000 LABs to over 22,000 LABs, depending on the panicuJar device in the fami ly; and each LAB has eight ALM s. Package sizes vary from 34 1 pins to 1,173 pins. Devices requiring dc supply voltages of 1.2 V, 1.5 V, and 2.5 V arc typically available. The Stmtix n fami ly ofFPGAs uscs the SRAM-b
633
634
•
PRO GRAM M AB LE LOGIC AN D SOFTWARE
FIGURE"
•
- 38
Simplified d ia.gr.3m o ( t he Su a.tix II
I
FPGA LAB ( logic a.~ b lock)
LAR
structure. AlMI a. re a.da.ptive logic modu la .
t
I
I
1
ALM t
AIJ..12
ALM 3
,, ""',' inlCrOOfll1e(:1 : ,
AIJ..U!
'T,
~~~
~
t LAB
I
rfrf-
AL1<11 ALM2
f-
ALM3}
,, Loc" inlerCOllnoct : ,
-
ALMII
T
I
•
I
t
rfGIuhat r..... imercolllleci
Global column
imCn:0I1nc..:1
The Adaptive logic Module (ALM) The ALM is the basic design unit in the Stratix II FPGA. Each ALM contains an LUT-based combinational logic section and associated logic that can be programmed for two combinational logic outputs or registered outputs. Also, the ALM has adder logic, flip-naps, and other logic that allows for the implementation of arithmetic, counter, and shift register fu nctions. A simplified diagram of a Stratix n ALM is shown in Figure 11- 39. Operating ModeJ of an ALM operation:
An ALM can be programmed for the following modes o f
Normal mode Exlended LUT mode Arithmetic mode Shared arithmelic mode Register chain in
FIGURE 11 - 39
Simplified d ia.gra.m o f a. Str.3tix " a.da.ptive logic modu le (ALM).
I
---
---
j
COlllblnUlmnal
ou tput Miller
UIT
'''
RcgiSlt:r logic
r--
Register logic
-
I
oomhin~lional
logic
I AdW logic
j ALI\'!
I Regi~lCJ"
chain OUI
RcgISlert.'
00'1'"
ALTERA FPGAs
•
6 35
In addition to these four mCKles. an ALM can be utilized as a register chain to create counters and shift registers. In this section, we will discuss the normal mode and the extended LUTmode. The 110rmal mode is used primari ly for gcnerating combinational logic fu nctions. An ALM can implement one or two combinational oUlput fu nctions with it.~ two LUTs. Example...; of fou r LUT confi gurations are ill ustrated in Figure 11-40. Two SOP functions, each with four variables or less, can be implemented in an ALM without sharing inputs. For example. you call have two 4-variable fu nctions, one 4-variable function and one 3-variable fu nction or two 3-variable functions. By sharing inputs, you can have any combination of a total of eight inputs up to a maximum of six inputs for each l UT. In the normal mooe, you are limited to 6-variable SOP fu nctions.
FIGURE 11 - 40
~~1 4~~'
~I
Examples of pouible l UT
configu ratio n! in an adaptive logic modu le (ALM ) in the normal mode.
6-inpul
u r I'
4-input
LUT
5-inptlt
5-input
un
LUT
b
c4-input
LUT
5-inpul
wr
The extellded LUT mode allows expansion to a 7-variable function, as illustrated in Figure 11-41. The multiplexer formed by the AND-OR circuit with a complemented input is part oflh e dedicated logic in an ALM.
FIGURE 11 - 41
Al.M
Expansion of iO n ALM to produce a
7-variable SOP function in the extended lUT mode.
5-inpu t
lOT 7 inpul ,ari:Jb/e~
1:
5-input LUT
I
--{>
I
:r--
SOP i IUlflUl
636
•
PROGRAMMABLE LOGIC AND SOFTWARE
I
EXAMPLE 11-4 An A LM in a Stmtix II FPGA is configured in the extended LUT mode, as shown in Figure 11-42. For the specific LUT outputs show n. de tennine the final SOP output.
FIGURE 11 - 42
X<.4. ,.-\ .,.-\ ~. l , + ,\
,
ALI''! S-inpul
I
LIfT
1:
S-inpul
LIfT
Solution
Rela ted Problem
4>
~ I
The SOP output expression is as follows:
Show an ALM configured in the normal mode to produce one SOP function with five product tenns from one LUT and three product terms from the o ther LUT.
Embedded Functions A general block diagram of the Strati x II FPGA is shown in Figure 11- 43. The FPGA contains embedded memory fu nctions as well as d igital signal processing (DSP) funct ions. DSP funct ions, such as digital filters, arc commonly used in many systems. As you can see in the block diagram, the embedded blocks arc arranged throug hout the FPGA interconnection matrix and input/output clements (lO Es) are placed around the l-"PGA perimeter.
I
SECTION 11 -6 REVIEW
1. What
i~
the
ba~ic
logiC d~ign unit in the Stratix II FPGA?
2. How many ALMs are there in a LAB? 3. What produces combi~tio~ r logic functions in an AW? 4. How many SOP functions can oneALM produce? 5. Name the two types of embedded functions in the Stratix II.
- --
XILINX FPGAs
Embedded ~mory
110 elements
blocks
~ ~ 6,, ~,
Embedded ~mory
block
FIGURE 11 _ 43
Sttatix II block diilgr;,m.
11-7
XlliNX FPGA,
Xi linx has Iwo major lines of FPGAs. the Spartan and the Virtex, and there arc different families within cach line. Examples arc the Spartan 3 and Spartan lIE, Vll1ex-4, Virtex n, Virlcx n Pro, and Virtex II Pro X. Xilinx designatcs the Vincx II, Virtex II Pro, and Vinex II Pro X as platform FPGAs because lhey have embedded functions, such as memories. processors, transceivers, and othcr hard and sofl IP cores. The PGA fam ilies d iffcr gcnerally in density and pcrfonnancc paramcters. Most of the Xilinx device~ have a traditional FPGA architecture; howcver, the Vinex II Pro X has what is called Application Specific Modular Block. ASMBU').! (pronounccd w;~;emble) architecture with over a bil lion transistors in a single devicc. Afler completing this section, you should be able to • DeSt;ribe a typical Virtex family FPGA • Discuss lhe basic Virtex architecture • Explain how productlenns arc generated by an FPGA • Describe the ASMBL architecture
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Configurable logic Bloclo The configurable logic area (called FPGA fabric) of most Xilin x FPGAs is divided into configurablc logic blocks (CLBs) with each CLB containing Illultiple ba<;ic logic units called logi c cells (LCs). Eilch logic cell is based on traditional 4-input LUT logic plus additional logic and a nip-nop. A 4-input LUT can produce from one product lenn to an SOP function with sixteen producllenns. Two identical logic cells arc called a slice. Figure 11-44 illustmtes the levels of configumblc logic from the logic cell to the CLB. Densities mnge from around 2000 to over 74.()(X) logic cells in a sing le Virtex device.
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SOP Cascade Chains A simplified slice (two logic cell s) with cascade chain logic is shown in Figure 11-45. There is a dedicated multiplexer (M UX) within the associated logic of each LC that can be used in Ihe cascade chain and a dedicatcd OR gate wi thin cach slicc . Figure 11-45(a} shows an cxample of how onc slice in a CLB can be configu red as an AND galc 10 producc an 8~ variable producttcrm. Two slices can be configured to produce an SOP function wilh IWO 8-v
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E}(AMPLE 11-5
Show how a l 6-inpUi AND gate can be implemcnted in a CLB . Solution
Related Problem
Two slices configured as shown in Figure 11-46 result in a 16-input AND gate. Show how the two slices in Figure ' 1-46 could be configured to produce the SOP fu nction,A,Alf\04 + AyI.:t1,Ao + 8 78,fJ,84 + B]B?!JIBo.
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Traditional FPGA Architecrure V5. ASM8l Architecture As you have learned, the traditional FPGA archilcclUrc appears as an array of logic blocks (eLB!> or LABs) surrounded by configurablc inputloulput cells. 111e amount of confi gumblc logic (CLBs) in an FPGA depends on lhe number of VO clements that can be phys-
ically placed around the perimeter. When IPcorcs such as D$P and embedded memory arc requ ired, the amount of confi gurablc logic must be sacrifi ced and at some point add itio nal
VOs may be required. As morC IP cores are added, Ihe physicaJ size of the FPGA must Ix: increased to maintain the necessary confi gurabJc logic and to increase the number of VOs. This general concept is illustrated in Figure 11 -47 . The more complex the logic on an FPGA, the more liDs are required. The dependent relationship between log ic and liDs will result in an increase in chip si:t..c and cost. Also , another problem with platfon n FPGAs is that when additional embedded IP core functions are required, a major redesign or partial redesign in chip layout may be TC{luired, which is a very costly process. The ASMBL Architecture Xilinx created a flexible approach to platfonn FPGAs in the Virtex II Pro X devices in order to overcome somc of the limitations of thc traditional architecture. 111C Application Specific Modular Block (ASMBL) architccture is a columnbased structure instead of the row/column struclUre. The lIDs arc interspersed throughout rathcr than positioned aro und the perimeter, so their number can be increased without increasing chip size. Each column is essentially a strip of logic thai can be replaced by another type of logic strip without redesigning the chip layout. Examples of the types of logic stfips are configurablc logic blocks (CLBs), 110 blocks (lOBs), memory, and hard and soft IP Ulres such as DSP and processor. Various numbers of each lype of logic strip can be mixed to meet specific application requirements. For example. in the simplest con fi guration. you could have a mix of CLB strips and JlO block strips, as illustrated in Figure 11-48(a). More or fewe r of either could be used depending on the rcquiremems. If you require more memory, one or more CLB strips could be replaced, as indicated in part (b). If your specific arcaor application is digital signal proceSSing. you could add DSP IP cores with a mix of mcmory. as shown in part (c). P-drt (d) shows the addition of processor cores.
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(b)Same si~e FPGA with embt'ddt.-d menlJr)' lind IPoores (DSP) resu lts in fewer UBs and is limited ty the perimeter 11Os.
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SECTION I I 7 REVIEW
1. What doe ClB in a Xilinx fPGA consist of?
2. What does iln lC consi~t of? 3. Decribe a slice in a Xi/imc FPGA.
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11 - 8
PROGRAMMABLE LOGIC SOfTWARE
I.n order to be uscful, programmablc logic mUSI havc both hardware and software componcms combincd into a functional un it. All manufacturers of SPLDs. CPL~ , and FPGAs providc software support for cach hardware devicc. ll'ICsc software packages are in a catcgory of soflW'.lrc known as computcr aided design (CAD). PLD proEramming was introduced in Chaptcr I and covered fu rther in Chapter 3. In this seclion, programmable logic software is presented in a gcncric way. Aftcr complClinl) this scction. you should be able 10 - Explain Ihe programming process in tcrms of design now - Describe thc design entry phase - Describe the functional simulation phasc _ Dcs(.Tibe the synthesis phase - Dcscribe thc irnplcmcmalion phase - Describe Ihe liming simulation phase _ Descri be Ihc down load phasc
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The progmmming process is generally referred La as dcsign flow. A basie design flow diagram for implementing a logic design in a pmgmmmablc dcvice is shown in Figure 11--49. Masl specific software packages incorpomlc Ihcse e[emCniS in one foml or another and proccss Ihem aUIOinatically. The device being programmed is usulllly referred to as the target device. FIGURE 11 - 4'
General design flow diagram for programming a SPlD, CPlD, or FPGA.
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You musl have four Ihi ngs lO gCI started programming a dcvicc; a computcr, dcvelopment software , a programmable logic devke (SPLD, CPLD, or FPGA), and a way to conneCl Ihe device 10 thc compulcr. Thcse essentials arc iJ1uslralcd in Figure 11 -50. Part (a)
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&lentiaj elements for progf,"lmming an SPlD, CPLD, o. FPGA.
PROGRAMMA BLE LOG IC SOFTWARE
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shows a computer that mct.1S the system requirements for the particular software you arc using. Pan (b) shows the software acquired either on a CO from the device manufacturer or downloaded frum the device manufac(Urer's website. Most manufacturers provide free software thai can be downloaded and used for a limited lime. Pan (c) shows a programmable logic device. Pan (d) illustrates two means of physically connecting the device to Ihe computer via cable by using either the programming rlxture into which Ihe device is inserted or the development board on which the device is mounted. After the software has been installed on your computer, you musl become fa mi liar with the particular softwHre tools before attempting to connect and program a device. This learning process will require oonsidembleeffort and lime.
DeSign Enby A<;sumc that you have a logic circuit design that you wish to implement in a programmable device. You can enter the design on your computer in either of two basic ways: schematic entl1' or text entry. In order to use tcxt entry, you must be familiar with an HOL such as VHDL, Vcr· ilog, ABEL. or AHOL. Most progmmmabJe logic manufacturers provide software packages that support VHOL and Verilog because they are standard HDLs. Some also support ABEL, AHDL, or other proprietary HDLs. Schematic entry basicai1y allows you to place symbols of logic gates and other logic functions frum a library on the screen and connect them as required by your design. A knowlege of an HOL is not required for scheIT1<.1.tic entry. Figure II - 51 illustrates these two types of entry generically for a simple AND-OR logic cirL"llil.
FIGURE 11 - S1 Examptc! of text a nd schematic entry Icrecns.
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Building a Logic Schematic When you enter a complete logic circuit on the screen. it is called a "flat" schematic. More complex logic circui ts may be hard to fi t onto Ihe screen. You can c nter a logic ci rcuit in segments, save each segment as a block ~ymbo l , and then connect the block symbols to form the complete circuit. This is called a hierarchical approach. As an example, let's assume thai you need a circuit that will produce the following SOP expression:
z = (A0~ ,Ao + Ay'\2A,Ao) + (A 3A2A,Ao + A)AzA,Ao + A y'\~ , Ao) Let's use the hiemrchical approach and create the logic for each of the two parenthetical terms in the above equation; red uce each logic circuit to a single graphic hlock symbol; and then. when both circuits arc compl ete, place them on the screen and connect their out pul" to an OR gate. This is illustrated in the five pans of Figure 11 - 52. The entire circuit cou ld be entered on the screen at one time, but the hiemrchical approach is useful when the logic circuit is larger and must be broken down into parts. In pan (e) of Figure II - 52. the logic could be reduced to anOlher block symbol and used in an even larger logic design; or il could be saved and reused in olherdesign.... as illustrated in Figure II -53. After a logic circuit ha<; been emered as a schematic, a program application called a compiler controls the various CAD lOols that process the schematic and produces an implementation for the larget device.
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Functional Simulation The purpose of the fW1clional simulation in the de..<;ign flow is to make sure that Ihe design you entered works :l<; it should, in terms of its logic operation, before synthesizing into a hardware design. Basically, after a logic circuit is compiled, it then can be simulated by applying input waveforms and checking the output for all possible input combi nations using a waveform edilOr. The wavefonn editor allows you to selcct the nodes (inputs and outpul<;J that you want to test. The selected input and output names appear on the Wave form Editor screen along with a sy mbol or other designation that identifies each as an inp ut or an output, :l<; shown in Figure II -54. Initial ly, al l four inputs default to O. and the crosshatch indicates the output is unknnwn. You can select Ihe time intervals for Ihe display. Next, you create each input ..... aveform by enteri ng a I or 0 for each lime interval (interval between dashed Jines in Figure II -55). This is usually accomplished by a point. dick. and select process with your mouse, depending on the s(X'Cific software. For this particular case. you would create the waveforms so that al l 16 po.~s ibl e combinations of 4 inputs are represented. Figure II - 55 shows Ihe input waveforms (AD, A I, A2, A3) as they have been specified .
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After you have specified the input wavcfonns. gcnerally a simulation control window opens, allowing you to set the start and end times for the simul
After the functional limu l3tion ;1 run, the outpu t waveform Inourd indic
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Synthesis Once the design ha .. been entered and functionally simulared to verify that its logic operation is correct, the compiler automatically goes through several phao;es 10 prepare the design 10 be downloaded 10 the target device. During the synthesis phase of the design fl ow, the design is o ptimized in terms of minimizing the number of gates. replacing logic elements with other logic e lell1ent.~ that can pelform the same function more efficiently, and eliminati ng any redundant logic. The final output from the synthesis phase is a nellist that describes the optimized versiOn of the logic circuit.
Netwt A "etlist is basically aconnectivity lisl that describes components and how they are cOnnected together. Generally, a netlis! contains rdercnces to descriptions of the components or elements used. Each time a component, such as a logic gate, is used in a nellis!. il is called an imfance. Each instance has adefinilion that lists the connec tions that can be made to that ki nd of comptJl1ent and some basic properties of that compone nt. These connection points are called ports or pins. Usually, each instance will have a unique name; for example, if you have t .....'O inslances of AND gate..". o ne might be "and l" and the other "and2." Be.."ides thei r names, they migh t Otherwise be identical. Nets are the "wircs"that connect things together in the circuil. Net-based netlists usually describe all the instances and their attributes, then describe each net, and specify which port they arc connected to 011 each instance. The AND-OR logic circuit thai you entered in the design pha"e, shown in Fig ure 11- 57(a), cou ld resull in the o ptimized circuit shown in J-Ig ure 11 - 57(b). In Ihis illustralion. the compiler removed the three OR gates and rep laced them with one 5- inpul OR gale. Also, two redundam inverters were removed.
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TI1C synthesis software generates a nctlist. To iJllL"tratc tl1cconcept of a generic nellis," Figure 11- 58(a) shows net a<;sigllments. instance assignme nts. and UO assignments in red. ' n le nellist shown in I-igure 11- 58(b) does not necc<;sarily resemble any specific nellist format or syntax. l fiis hypothctical nctlist s imply indicates thc typcof infonnation thai would be nece.WiI)' to describe a circuit. One fomlai used for netlists is EDIF (Electronic Design Interchange Format).
Implementation (Software) After the des ign ha:. been synthesized, the compiler impleme nts the desigll, which is basically a "mapping" of the des ign so that il will fit in the specific targel device based on its
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Synthesil produces a netlid fOf the optimized logic circuit.
arc hilecture and pin confi guratio ns. This process is called jiltillg or place Gild rolltillg. To accomplish the implementation phase of the design flow, the software must "know" about the specific device and have detai led pin infonnalion. Complele data on all porential target devices are gellerally stOred ill the software library.
Timing Simulation This part oflhe design flov.' occurs afler the implemelltation and before dowllioading to the target device. The timing simulatiOll verifies thal the circuit works at the design frequency and that there are no propagation delays or other timing problems that will affect the overall operation. Since a functional simulation has already been done. the circuit should work properly from a logic point of view. The development software uses information about the specific laJ-gel device. such as propagation delays of the gate~. to pt:rform a timing simulation of the desig n. Foc the functional simulation, the specification of the target device was not required; but for lhe liming simulation, the largel device must be chosen. 'Ille Wavefonn Editor can be used 10 view the resull of the liming simulation just as with the funclional simulation. a<; illustrated in Figure II- 59. If there are no problems with the timing, a., shown in part (a). the design is ready to download. However, suppose thai the timing simulation l"C'oeals a "glitch" due to propagation delay, as shown in Figure 11- 59(b). A glitCh is a very short duration spike in the wavefonn. In thisevem, you .....,ould need to carefully analyze the design for the C3lL<;e, then re-enter the modified design, and repeat the design flow process. Remember, you have not committed the design to hard",,'8.Ie at this paim.
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Device Programming (Downloading) Once the funct ional and timing simulations have verified that the design is working properly, you can initiate the dow nload sequence. A bilstITam is generated that represellls Ihe fina l design, and it is sent to the larget device to automatically contlgure il. Upon completion. the design is actually in hardware and can be tcsled in-circuil. Figure 11-60 shows the bm;ic concept of downloading.
A Real Estate Analogy One way to think of the implementation and down loading processes is to use a real eSlale development analogy. The developer starts with a trnct of land, surveys it, and divides it into lots (analogous to an unprogrammed device). A site plan of the developmenl with all the lots, buildings. roads, and uli lities is conceived and laid out (analogous 10 design entry). Next, il is necessary to verify Ihat the number of buildings and infra... truclure will fi t on the tract of land and meet all local codes. The site plan also shows the placement o f each build· ing and shows the routing of each street and :oidewalk (analogou:o to synthesis and imple. mentation). Not until thi:o mapping has occurred can the developer begin physically constructing the buildings. roads. and utilities (analogous to downloading). This real eSl8le analogy is illustrated in Figure I 1--6 I(a). The process for placing a logic design il1lo a programmable device is de picled in part (b), where Ihe mapping phase is analogous to the site plan and the downloading is analogous to placi ng physical structures on the site.
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FIGURE 11 - 60
Downloading a design to the target device.
Site plan must be completed before the: dc:veloprnc:nt is physically imp lemented. This is analo~loUS 10 the: implemen· tation phasc:of the design now lOr programmHble logic.
Physic:tJ $IfUClUres ~ placed only after the site plan ~riflCs if and how everything will i;, on the property. Th i~ i~ analogous to doo>nloading the design inlU tho: target Ocvioo.
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1. Ust the phaieS of the design flow for programmable logic. 2. list the essential elements for programming a CPLO o r fPGA . 3. What is the purpose of a netlist? 4. Which comes first in the design flow, the functiona l simulation or the timing limulation7
11-9
BOUNDARY SCAN lOGIC Boundary scan is used for both the testing and the programming of the intemal logic of a programmable device. The JTAG standard for boundary scan logic is specified by IEEE Std. 11 49. I. Most programmable logic devices are JTAG complianl. In this section. the basic architecture of a JTAG IEEE Std. 11 49. 1 device is introd uced and discussed in terms of the details of its boundary scan register and comrol logic structure. After completing this section, you should be able to • Describe the required el e me nl~ of a JTAG compliam device • List the mandatory JTAG inputs and outputs • State the purpose of the boundary scan register • State the purpose of the instruction register - Explain what the bypass register is fo r
IEEE Std. 1149.1 Reg;,te" AU program mable logic devices thaI are compliant with fEEE Std. 11 49. 1 require the elements shown in the simplified diagram in Figure 11 -62. These are the boundary scan register, the bypass register, the instruction register. and the TAP (test access pon) logic. A fift h register, the identification register, is optional and not shown in the fi gure. Boundary Scan (85) Register 'Ille interconnected BSCs (boundary scan cells) form the boundary scan register. T he serial input to the register is the TDI (test data in). and the serial out put is TDO (test data OUI). Dala from the internal logic and the input and output pins of the device can a lso be parallel shifted into the BS register. The BS register is used to test connections between PLDs and Ihc internal logic that has been progranlmcd into the device.
BytJO.H (BP) Register 'Ib is required data register (typically only one nip-flop) optimizes the shifling process by shortening the path between the TOI and the TOO in case the BS register or other data register is nOI used. Imtmetiol1 Register Thi s required register stores instructions for the execution of various boulldary scan operations. Identification {lD} Register An identification register is an optional data register that is not required by IEEE Std. 11 49.1. However, it is used in some boundary scan architectures to store a code that identifies the particular programmable device.
IEEE Std. 1149.1 Boundary Scan Instructions Several standard instructions are used to control the boundary scan logic. In addition these. other optional instructions are ava ilable. BYPASS
This instructiOn sw itch~ the BP register into the TDiffDO path.
EX/EST Th is instruction switches the BS register into the TDIfI'[)O path and allows ex ternal pin tests and interconneCtion tests between the Output of one programmable logic device and the input of another.
[0
BOUNDARY SCAN l OG IC
•
655
.... FIGUR E 11 - 62
Greatly simplified diagram of a JTAG
(IEEE Std. 11 49.1) comptiant programmable logic device (CPLD o r FPGA). The aSCs (boundary SGln eelh) form the bouod3ry sca n register. Only a small number of ascI are shewn for mUltratio n. [olemaJ program nl3ble
logic
In!it nJct.iQIl rq;i!;lcr
TDI
TMS
TCK
TRST
l1JO
INTESI This instruclion switches thc BS register into the TDlfTOO path and allows testing ofthe intcrnal programmed logic. SAMPLEIPREWAD This instruction is used to sample data at the device input pins and ap ply the dam to the internal logic. Also, it is used to apply data (pld oad) from the internal logic to the device OUiput pins.
IDCODE This inslruction switches the optional identification regisle .. into Ihc TDIfT1)() path so Ihc ID code can be shifted out to the TOO.
IEEE Std . 1149.1 Test Access Port (TAP) The Test Access Port (fAP) consislJ; of control logic. four mandatory illputs and outpulS, and one defin(.'
Mode Selecl (TMS)
The TMS swilches between the states of the TAP controller.
Tesl Clock (TCK) The TCK provides timing for the TAP controller which generates control signals for the data registers and the illstruction register.
656
•
PR.OGRAMMABLE LOGIC AND SOFTWAR.E
A block diagram of the boundary scan logic is shown in Figure 11 -63. Eoth instructions and data are shifled in oll lhe TOlline. The TAP controller directs illstructions into the illstruction register or data into the appropriate data register. A decoded instruction from the in";tructioll decoder selects which data register is to be accessed via MUX I and also if an instruction or data are to be shifted out 011 the TDO line via MUX 2. Also. a decoded instruction provides for setting up the boundary scan register in o ne of five basic modes. The boundary scan cell and its modes of operation are descri bed next.
IIl.;(rm"tion n.gisler
MUX2
r--
rd
roo
I
I I n~l n.Jction
""""',
I
0"
TMS
TCK
-
-
I
l)ata/lnsl mction register 5eiect1incs
BSiIVlBt' n'g Lsler selccllmft'
TAP control logle UPDATEIR
r-
-
BS regir.rer "",.,lIel data 110 selcct
CLOCKIR SH IFTIR
UI-'DATEDR CLOCKDR S HIFT[)R
--
H Hound a~'
H
I
!
t'
ltll"tt - - --
scan (BS) re#sln
r-
----
Idcnt ifi~ion
(lO"! regiSll-r<'
11)1
l!.-
Data regiSI<:n' (· optional ) f iGURE 11-63
The Bounda,), Scan Cell (BK) The boundary scan register is made up of boundary scan cells. A block diagram of a basic ESC is shown in Figure 11 -64. As indicated, dam can be serially shifted in and OUI of the ESC. Also. data can be shilled into the sse from the internal programmable logic. from a device input pin. or from the previous SSc. Additionally, data can be shifted out of the BSC to the internal programmable logic. to a device output pin, o r to the next BSC. Thc architecture ofa generic bollooaty scan cell is shown in Figure I [-65. The cell consists of two identical logic circuits each containing two flip-flops and two multi plexers. Essentially. one circ uit allows data to be shifted from the internal programmable logic or to a device oulpul pin. The other circuil allows data to be shifted from a device input pin or to the internal prognllnmable logic. There arc fi ve modes in which the BSC can operate in terms of data flow. The first BSC mode allows data to flow seriaUy from the previous ESC to the next BSC. as illustrdled in
BOUNDARY SCAN LOG IC
•
FIGURE' ' - 64
Serilll delll oul lo neXI BSC
A balie bidirectional BSe
500
1 BS logic l nll."Tllal pr~ammablc
l(lgic
--=
1
Data ItO
IlS lugic
1
SDI
Serial data in rr(lm prev ious BSC
Serial data out to next BSC
SOO
I
0
L;;-D
,-1
-<
Q
-
1---
I
- rC
I>C
Captu re register B
Inlernal pm grammable logic
D
Q
Update
ICgi~cr
B
HSL:
0
L Oj
-~
D ~
I>C
Capture n:giSII:r A
SIIIFf CLOCK SOl Serial d>lw in rrom plt,v iou s BSC
0
Q
From TAP cootroller
r-- I> c
Q
110 pin
- L O[
Updatc register A
LJI'DATE
PDIIO I·rom decode <>f instnlClion register
-
FIGURE 11-65
Representative arcl1itecture of a typica l boundary se<>n cell.
Figure 11- 66. A I on the SHi t, input selects the SD I. The data on the SDI line are clocked into Capture register A on the positive edge of the CLOC K. The data are then clocked into Capture register B on the negative edge of the C LOC K and appear on tile SOO line. This is equ ivalent to serially shifting data through the boundary scan regisler.
657
658
•
PROGRAMMABLE lOGIC AND SOfTWARE
SIlO
I
ro-
LOD
r- '
Q
-< p.c
Cllpture register B
sse
r- ~
D ~
Q
I>c
Capture registCT A 1
SHI t-T
r-
Update register B
logic
LOi
I
,-- ~c
interna l programmable
Q -
D
.
D
Q
f - ~c
ro-
ItO pm
1
L DC
Update regisu:r A
Sl. CLOC K
L I'I)ATE
PDifO
SOl FIGURE t 1 - 66
Data pCl th for seria Uy JOhifting data from one BSC to the next. There il a I on the SHIFT input and a aOCK pu/ie iJO applied. The red lines indicate d ata flow.
The second BSe mOOe allows data to flow d irectly from the internal programmable logic to a device output pin. a.~ illuslrated in Figure 11-67. TheO o n the POliO (parallel data UO) control line select.s the data from the internal programmable logic. The I on the OE (output enable) li ne enables the outpul buffer. The third BSC mode allows data to flow d irectly frum a device input pin to the internal programmable logic. as illustrated in Figure 11-68. The 0 on the POliO (parallel data UO) control line selects the data from lhe input pin. The 0 on the OE (output enable) line disables the output buffer. The fourth USC mode allows dala to now from the SDI 10 the internal programmable logic. as ill ustrated in Figure 11-69. A I on Ihe SHIFT input selects the SOl. The data on the SDI line are clocked into Capture register A on the positive edge of the CLOCK. The data are then clocked into Capture register B on the negative edge of lhe CLOC K and appe.:1r on the SDO line. A pulse on the UPDATE line clocks the dala into Update regisler R. A I on the POUO line selects the output of Update register B and applies it 10 the intemal progmmmable logic. The data also appear on the SDO line. The fi fth sse mode a llows data 10 flow frollllhc SOl 10 a device output pin and 10 the SDO output, as illustrated in Figure 11- 70. A 1 on the S HiFf input selects the SOl. The data on t.he SO l line are clocked into Capture register A on the positive edge of the CLOCK. The data are then clocked into Capture register 13 on the negative edge of the CLOCK and appear on the SOO line. A pulse on the UPDATE li ne clocks the data into Update register A. With a 1 on OE. a I on the POliO line selecl~ the output of Update register A and applies it to the device output pin.
~ IXJ
I
0
L I(jD
,--- 1
,---
I}-
r- 1>c
C
Caplun: register B
Interna l
QI-
D
Q
Update reg isler B
programmable USC
10ll ie
0
Lfol
D
,~ +- p C Dlplurc
D
Q
+- 1>c
II 01;,
Upd~le rcgi~\cr
n:gisl~"r A
sHIrr CUX.'K
QI-~
IJO pin
A
"
PD IJO
L I'DATE
SDI
FIGURE 11-67
D
BSe
'U
SIXl
I
Lfol ,---~
D
r-
pc
c- p
Caplure register B
Internal
D
Q
Q
~ IJ
c
Update rcgi:;ler B
programmable IUiic
n Sf:
Lfol r-~
.
01 D
D
Q
+- p c Capture rrgislcr A
+- pc
--L] [/0 pin
Q I-~
"DE
Update tcgistcr A
0 SHirr CI.OCK
L PDATE
POlIO
SOl
FIGURE 11 - 68
Data p.ath (or I:r
659
SIX)
I
L IOJ C-
D
,j
-<
0
,
Q
pC
- .C-
Cl!plure register B
Internal programmable logic
/J
Q
--,
1--
pC
Update register B
BSC
u
L roD
c- ~
,
~
D
Q
pC
Q
'--
r- PC
Capture reg ister A
Upclmc regiMc r A
SL
SL
SHiff CLOCK
l
,
UOpin
L
"DC
,
POAn~
POlIO
SOl FIGURE 11-69
OiJta pilth for tTiJrnferring ebta from the SOl to the intem
soo
I
L IOJ
o
r ,J
-<
D
/J
Q
pC
Q
~
,
t-
c- p C
Capmrc register B
Imcrrol progn,m muhlc logic
ro-
,
Update reg i!olcr B
USC
0
L IOJ r~
,
D ~
Q
~-
pC
- pC /J
~
Capt ure rq:isler A
Update
JL
JL
SHU T CI _OC K
UPDATI:
Q
- D IIOpin
- -L
n.'Il i~tcr
, OE
A
, ""00
SD' FIGURE 11 - 70 OiJt~
660
path {or triJrnferring data from the SOl to a device output pin ~nd the 500. There il ~ 1 on the SHIFT line, iJ 1 OIl the POlIO line iJnd iJ , OIl the DE line. A pvlse is iJpplied to the CLOCK line followed by iJ pulse on the UPOATE line.
BOUNDARY SC A N lOG IC
•
Boundary Scan Testing of Multiple Devices Boundary 80m testing can be applied to printed circui t boards on which multi ple JTAG (IEEE Sid. 1149. J) devices are mounted 10 chet:k interconnections ao; well as intemal logic. T his concept is illustrated by tracing the path of data shown in red in Figure 11- 7 1.
2
-
~
3
--.. -0
[ ~- $-$-~'Y~~: ,
--.{}f~;}
l,. ,
i' {
g •• I •• ••
l: TUI rMS TCK
TOO
•
r
I
.. .=:J
~g
[[=::===:::JJ :•
I
t
-:J
T
••
t : - -=:!l
§~~~~T~~l T
••
T
~
{.
FIGURE 11-71
B. n ic concept of boundary scan testing of multip le devices and intclUlnnections. The test p
1lle bit is shifted into the IDI of device 1 and th rough the US register of dev ice I to a cell where the connection to be tested goes to device 2. The bit is shilied out to the device
output pin and through the interconnection to the input pin of device 2. The bit continues through the US register of device 2 10 an output pin and through thc illlerconneclion to thc input pin of device 3. It is then shifted through the BS register of device 3 to the TDO. If the hit co ming oul of the TOO i)' the same as the bit going into the TOI, the boundmy scan cells through whit'h it was shifted and the interconnectio ns from device I to device 2 and from device 2 10 device 3 are good.
i
SECTION 11-9 REVIEW
1.
U~t
the boundary ~can inputs and outputs required by IEEE Std.1149.1.
2. What II the TAP? 3. Name the mandatory regi~ters in boundary K
661
662
_
PROGRAMMABLE lOGI C AND SOFTWARE
11 - 10 TROUBLESHOOTING Two basic ways to test a device that has been programmed with a logic design are Il1lditional and au tomated. In the tmditional method, common laboratory test instruments can be used to check the operation. In the automated method, three Fundamental approaches can be used for testing: bed-of-nails. nying probe. and boundary scan. After completing this section, you should be able 10 _ Describe tmditional testing _ Dc!scribt! bed-of- nails and flying probe testing and discuss their limitations _ Discuss the HAG standard _ J:)e;cribt! the basic concept of boundary scan _ Explain the modes of boundary scan testing and briefly discuss
BSDL Aftcr you commit a logic design to hardware. you can test the device on a PC board. For relatively simple designs, you can check the device using standard labomtory test instruments such a,<,; the oscilloscope or logic analyzer, signal generdtor,
FIGURE 11 - 72
TriKlition.;,J testing using laboratory instrumenb.
Bed-of-Nails Testing The testi ng o f primed circuit boards at production levels must be done automatically. The bed-or-nails (BON) method was one of the firsl approaches 10 automated testing. ·n le concept is illustrated in Figure ' 1- 73 where the PC board is pl
TROUB LESHOOTI NG
•
663
fiGURE 11-13
Billie concept cf bed-of-n
method (or tesling a circuit board.
To ATE (aulOmmic tcst eq uipmen t)
•
~ •
the leSt pointS can be checked simultaneously with special automatcd test equipment. Basically, the purpose of automated production testing is to find any manufacturing fl aw!'>, such as open or shorted pi ns and wrong, missing, or misaligned components. This automated process does not primari ly test for function.'llity of the logic. It is assumed that eac-h componcnt had been tested for functionalily prior to installation on the circuit bo.,rd and thai the only f1l1ws should be those created during manufacturing. As integrated circuit devices became smaller and more complex, the trend to surfacemount tec,hnology increased, and c.ircui t boards changed from double-sided to mult ilayer. The increa~ed density and complexity o f circuit boards and devices. with large numbers of very closely spaced pins. resultcd in lim ited access to test points on thc board using lhebedof-nails approach.
Flying Probe Testing Another mcthod fo r testing printed c ircui t boards is called thc nying ,)robe method. A Iypical tlying probe and ils basic opemtion arc shown in Figure 11 - 74. A teSI probe is
(a) J ·axis 1TIt)\'cmcnt f iGURE 11 - 14
A
flying probe testing a circuit board.
(b) MOI'cmcnt from point to point
664
•
PROGRAMMABLE LOGIC AND SOFTWARE
positioned above a c ircuit board that is to be tested. The probe can be au tomatically moved in three axes~al ong the x-ax is, the y-ax is, and the z-axis of the board- to make contact with any specified test points. T he movement o f the probe i .~ controlled by software that uses the physical layou t of the board to determine the coordinates. Many n yin~ probe testers have mu ltiple probes for one board. The fly ing probe method or testing overcomes sume of the limitations of the bed-or-nai ls. First, the BON method requires a different fixture for each type of circuit board, but the flying probe method requ ires no fixture. Also, the fl ying probe can access more points on a board because the probe can be ITlOVed to any position and it can access the lOp of the board where the componcnts are. A drawback of the flying probe method is that it is s lower tha n the BON and so is generally limited to testing prototypes and s mall production q uantities.
Boundary Scan Testing Limited accefiS 10 test poi nts led to the concept of placing the test points within the integrated circuit devices themse l ve~. Mosl CPLD!; and FPGAs include boundary scan logic as part of their internal structure independent of the fu nctional ity of the logit'program med into the device. T hesc dcvices arc JTAG compliant. A circu it. known as a boundary scan cell , is placed between the prognlmmablc logic and each input and o utput pin of the device. as s hown in Figure 11 - 75. The cells are basically memory cells that store a I or a O. The cells connected 10 the programmable logic inpuls are called input cells, and those connCl;ted 10 the programmable logic outputs are called output cells. Boundary scan testing is based on the RAG standard (IEEE Std. 1149. 1). 'nle four lTAG illpUis and outputs- TOI (test data in), T DO (test data out), TCK (lest clock), alld TMS (test mode selCl;l)--are know n as the test access pons (TAP).
FIGUR£ 11 - 15
T IJO B,otl"d3r\ -.....ltl
Balic concept of boundary lean logic
~..:t h
in a programmable device. TOI _ -"
TCK "'~rnnInUlblc
h~Il'
TMS
Whcll boundary scan cells are used to test the inte rnal funct ionality of the devicc, the te.~t mode is called intes!. The ba'iic concept o r boundary scan using Intest i~ as ro]]ows: A software-driven pa ttern of I s and Os is shiCied in via thc TDI pin and is placed on the prog rammable logic inputs. As a resu lt of thcse applicu input bits, the logic wi ll produce output bit{),) in rcsponJ'e. The rcsulling output bites) is (a re) then s hifted out on the 11)() pin Illtest
TROUBLESHOOTING
•
665
FIGURE 11 - 16
'fDO
Example of a bit pottern in the boundary scan Intelt for the internal logic.
TOI
TMS
and checked for errors. An incorrect output, of course, indicales a fau lt in the programmed logic. UO cells, or boundary scan cells. Figu re 11- 76 shows a boundary scan Inlest pattern lOll for an AND-OR logiccircui l thal has been programmed into a device. Sixteen combinations offourTDI bits would test thecircui t in all possible states according 10 Ihe lisl in Table I I- I . lhe4-bit combinations are serially ~h i fted into the boundary scan cells. and Ihe corresponding output is shifted out on TOO for checking. lbis process is cuntrolled by boundary scan lest software.
TABLE 11 -1
TOI
TOO
oroo
Bounddry scan telt bit pattern (or t he programmed device in Figure
000 [
11 - 76.
00[0
0
0011 0[00 0101 0110 0 111
[000 [!Xl [
[
1010
0
1011
1100 1101
I I!O 11 11
666
•
PROGRAMMABLE l OGIC ANO SOFTWARE
When boundary scan cel ls arc uS/.:d to test the external connections to the de\'ice in add ition to some internal functionality. the test mode is called Extesi. The basic concept of boundary scan usi ng Extest is as foll ows: A software-driven pattern of Is and Os is applied to the input pins of the device and en tered into the input cells. As a result of th€'se applied input bits, the logic will produce output bit(s) in response. The resulti ng OUlput bit(s) is (arc) then taken from the output pin of the device and checked for errors. An incorrect outpul, of course. indicates a fau lt in the input or output pill connections or interconnections. an incoIT<.."Ct device, or improperly installed device. Obviously, some internal faults can a lso be detected in the Ex test mode. Forexample. fau lls in the boundary sca n cells, I/O cells or certai n faults ill the programmed logic will produce an incorrect outpu\. Figure 11 - 77 shows an exampl€' of a boundary scan Extest that lests the fo ur inputs and the output of the logic circuit.
Edelt
FIGURE 11-77
TDO
&
I"MS
If a fault is dell.."Cted in the Exlest mode. it can be either ex ternal (a bad pin connection) Of internal (a fau lty t"<)I1nectioll , boundary scan cell. or logic element) to the device. Therefore, in order 10 isolate an EXlest detected fau lt. an Intest should be run following the Extest. If both tests show a fau lt, then it is internal to the device. In the Extcst mode, it is necessary to probe contacts to the input and output pins of the device. These pins have to be available at a connector to the circu it board or on test pads so they can be checked by the automatic test equipment. Pin:. that are not brought through a JTAG board connector can be probed at a test pad Llsing the bcd-of-nails method and/or the fly ing probe method. These combined approaches are ill llslrated in Figure 11 - 78.
Boundary Scan Description Language (BSDL) This test software is part of the JTAG stand,lrd iEEE 11 49. 1 and uses VHDL to describe how the boundary :.can logic is implemented in a specific device and how ir opera!es. BSDL provides a standard dala forma! for desl.:ribing how IEEE 11 49. 1 is implemented in a JTAG-compJiant device. When you usc
TROUBLESHOOTING
H)in~
TOO
pruill.'
T DI
BON
J TMS f IGU R£ 11 - 78
A combination of boundary scan, bed-of-nails, and flying probe ~ting.
boundary scan test software lools that suppon BSDL. you can usually obtain BSDL from the device manufacturer. Each device that contains ded icated boundary scan logic is supponed by a BSDL file that describes that particu lar device. Certain things that are described in the BSDL IIIe are the device type and port descript ions that name the I/O pins and test access port (TAP) pins and denote their nature such a.<; input, Olltput, o r bidirectional. BSDL also provides a mapping of logical signals on to the physical pins and a deseriptjon of lhe boundary scan logic architecture contained in the device. A bit tesl pattern for testing the device can be defi nt.'d using BSDL.
J SECTlON 11 - 10 REVIEW
1. Describe the b'Hie concept of bed-of-nails board testing. 2 . What limits the bed-of-nails method? 3. How does the flying probe test method differ from BON7 4. Explain the basic concept of boundary sun. 5. What are the two modes ofboundary scan test? 6. Name four )TAG signals used with boundary scan. 7. Wh
•
667
66 8
•
PROGRAMMABLE LOG IC AND SOFTWARE
In this system application, the generic software d evelopment tools using the schematic entry procedure that you Ica rn ed in thi~ chapte r a rc applied to thc BCD-t o-7-scgmcnt dccoder logic tha t was developed in Cha ptcr 4. Only thc major st eps a rc shown herc in a gencric approach to iIIultratc the b.nic concept. Figu rc TT- 79shOWl the indMdua llogic cifC\lib for cach of the SCVCl1 scgmenb. Each legment logic circuit is c ntered as a sCp<'ratc file and then converted to block
symbol form, Aftcr all K:VCn segmen t logic files have becn cnt:ered, th!:y a rc combined in a single block that is tile fu ll dcrodcr. All of t he seven logic circuib could be cn tcred at onc time to create u.nat is known 211 a ·f1at~ schematic. However, we will use tile hicral(;hica l approach o f design c ntry to keep the amou nt of logic on the Graphic Editor ICI"CCll at one time more manageable. This approach is preferred whcn tile schematic is fairly complex an d ca n be broken do",."
c-
"
H
H
C
- "
A
A
Ib) Segment·1I logic
Ie) Segmenl-c logic
D------------------,
d
, (c) Sc<,;Ilx.·nH· logi<.:
(d) &-gITK"1I I-tllog lC
D - -- - - - - ,
D- - - - - - - - - , A
- - ---j
0----1 c-
- - -j-t--L--'
(f) Segmcnl:flogic
FIGuRE 11-79
The seven individ ual legment logic circu its..
A
-
-----j
H
~r-----~_/
f
c --t-,--j
(g) Segme nt-Ii logic
,
DIG ITAL SYSTEM APPLIC ATI ON
into leveral parts, Also, in situatiom wf1ere people arc working on circuit:! thilt will later be combined into a larger circuit or syst~m, th~ hi~r.>rcllic<>1 approacll is
found in most softwa re, luc h al Altera Qua rtus II and Xilinx ISE.
cslcntial. Each of t he seven logic circuit:! il en te red individually, converted to a block symbol, and ~ed, Wh~n all lev~n circuit:! h~ been entered, each block symbo l witl bc placed on th e grap hic en t ry Icreen. All the block symbols wi ll be t he n connected t o t he input:! and output:!. Keep in mind th at thil il a generic delcription but illus tra tes the concept of some of the majo r t ooh
After opening t he ~ftwa re, we will let up a p roject for the 7~legment logic and open t he GraphiC Editor screen . To place th e logic ga te i)'ffiboll on t he screen, click on the gate icon as indicated in Figure 11 -80. A Symbol lCfccn appea r! to allow you to IClect the gates t hat you want from the softwa re library. The logic gatel are called primitives and can bc selected from a lis t wf1en you go to th e Primitivcs headin g.
IC\IC~I
Design Entry of Segment-a Logic
D-
,~
li"il ,
LIbraries
Under [ ibr.1rle.. '
you ":In! IU plac.:
io thl." Grnphic &lilor ",:n:en. Cltck OK. Then I"occ a~ mall}
OIl",I~"'-"'~:I-'
reqll ",!d.
Cuminlit' lU selCl:t (,lithe gale, Ill'('(\(o,J ;Inll pl(K'e
tlll.'111 in th .. Gmpttk Editor.
Primitives
",<12 '003 '004
0<2 0",
0,,"" Cancel
fiGURE 11-80 IlIu~tration
669
For segment a, two instances of the 2in put AND ga te are selccted and placed on the screen al shown. Next, a 4- input OR gate il iClccted and onc imtance is placed on the screen. Finally, th e in...crte r (NOT) illeleded, and two imtanccs of it arc placed on t hc screen. Next, in thc Symbol window, select Pim from the library. Either an input pin o r an output pin un be lpecified, al illustrated in Figure 11 -81. ror this pa rticular circuit, four input pins and one outpu t pin havc been ~Iaced in the Graphic Editor ~rcen, ill shown in Figure 11 - 82.
Clid the G;lt~ iron tn open 11K' \ymbul ~leuivn "inti"",.
"1
•
of selection and pl
670
•
PROGRAMMAB LE LOGIC AND SOFTWARE
FIGURE 11-81
Selection of input ilnd output pins in the Symbol window.
hi!,hligh1 i nplll IIr IIUlplll. Clid. UK
U bra ries
In place i n Ihc
Grollh i..: Edi."...
D
Symbol
1'\':\1 ~kct Pin~ (Ill(!
;
P ins 'opu1 ,,"!pol
~
Continue 1O...:k."Ct all
lhe pll1~ ~ ~rtU plan' Ihcm in IOC
Name
e::>--
I
Gr:J.phic "'.1m......
.: (
OK
)
Cancel
Graphic Editor Sclt:d!he nanlC"'> rllr e,..;h pin.
Rle Edit View Project Assigrvnenls Processing Tools Window
"",
A ____ D e::>--
.0
L..., Ihe
L"Omlt.~lilln
1001 10 .:unn~~1 IIIl'
.:ir...'tJit t:\1Il1Jl('1I<'J1l ....
Be::>--
c =A C>--~~-----L~
D-
-c> SEGa
oro: COrtn<."t:u....n a lirro.: by dr",~!!ing from {II..... oonnct:hun poim In.he .1I1k.....
Ma~
aI
FIGURE T 1- 82
PliICerrn::nt of pin! ilnd milking circu it con nections in th e Grilphic Editor.
The complete rlemiltic for the scgrrn::n t-
Figure 1 I - 84. An indication will appear to show if the compilation is succasfuJ or not.
Compile the Oed,"
Functional Simulilltion
Aft.cr the design hils been entered, the n ext Itep is to compilc it. The compilcr is iI
Most software packages have at lcast two typel of s;mu liltion tools: function
software too l thilt rT\iInilgcJ t he daign!low
simulation and timing simulation. The
pllX:ClI. The fitter tool in the compiler 5Clcco. the optimum interconnection!, pin
functional simulation \'Cfifia functioOilI;ty of the logic circuit and
assignrrn::nts, ilnd logic cdl ilslignmcnts to
,hould be done alsoon a. the cirCl.J it has
~rcd time interva l and specifying the level a. a HIGH (1) or a lOW (0). Yoo ~
fit a design in the Jeleded
target device.
from intervill to intclVil' until the
entire waveform is complete. Thil il repeated for aU the other input w.werorml.;)\ indica ted in figure 11-85. When all the input W
been wcceslfuUy compiled. Create DIad;. Symbol
Gcneril lly, iI compilcr dia log box ilPpcars; ilnd when it is stilrted. it indicates t he
The first stcp in Ktting up th e simulation il to specify a sign
A lucceufullimulation meanl that thc logic
progr~
or output and allign
cirCI.Jit works
being made ill a bar graph and
percentage of completion, as shown in
iI
name. Ned. create
onc waveform ilt a time by selecting t he
iI
function
point of view; thilt is, the logic is cared
DIG ITAL SYSTEM APPLICATION
•
671
FIGURE 11-'3 Complete schcm
FIGUR E 11-84 Compller _-
Compikr dialog bOl<.
-.--. - .
-
_- ~G_£i l
62%J ( Stop )
I'in~ and "a\'eform flam"" nn: a,,~i!,1k:d 10 I1 lutch 1"" ~;ht'm~l ic.
To neale 3 wu\eform • ..:Iecl ea..:h lime imer\'a1 ami
~pecif)
IMl lime
__ B
a Oor I
i nl~,,.,,al.
inl~r\nl
UIl[' al a lim..:.
Yuu ~pcxi f) 1m: il1PlIl ";&'efOml~,
1001 produces Ihe 11K- W3H,funn. , imulaliol1 UUlp"l
--t~[=~~==~=~=~~~~~~=~::=:======~~~j
FIGURE 11 '5 Input wavdorrm and the fClulting output waveform (or Icgmcnt-GI logic.
The neJd: ltep il to oom.ert the logic
Design Entry for Segments b Through g
schematic into a block lymboI, al ilfurtrated
The lame general procedure that \Val Ule
ICgment-b logic, SCgrTlCn t-<" logic, and
in Figure 11-86, and I
to enter, limu/ate, and!a\IC a l a block
scgmCllt-d logic.
Ooce the b lock 1)1'1'1001 hal been ~, it
i)'Illbol the segment-GI logic il repeated (or
can be acccm:d for ule in the fina l reign.
each of the other IiI< ICgment logic
circuits. Figure T1-87 shows the screens for
fj~re 11-881hO\.\l5 the
screenl for
legmcn l-e logic, legmcnt-f1ogie, and
672
•
PROGRAMMABLE lOGIC ANO SOFTWARE
Place arn,l C{lnOCl:I
inpul and ('>t.lpul pir" the ~nc "":l~ a, }"U
St.-gmenl-8 Lugic
dill lOr lho:: ...:ho::m.UI~-.
Dc>--ID B
C
C
R
A
A
SEG
f----<=> SEG~
FIGURE 11-86
The scgmcnt-a logic Khcmatic converted to a block ¥JIbol.
, .. _.--' r'.- rc -r- - n r _-'.. "
'"
r
_0
"
,
~
'-
~
'"
Run run.:,ional simu lll';on.
_-----,
_._
,...... ,
---~-------~
c
,o
0
--
_.- I" r _.
•
---.. ~!:"
_0
_-----
o
,
r
Run fUrl\.-,iun,,1 ~il1\1.ll iil ion_
'" _._-. f----r
_.
-Ento.r sc~mcn1-d '«"hemat ic. FIGURE t 1-81
Screen! for iCgmcnt logic (b, c, and d).
~
-.
Oln\"Crt
SChe'H~!ic
".....
'"'"
1<) block .~y mb< .l and
------
-"'-
"
_0
......
'tt
",f'
--
., . . . .
Con,·cn sche llUl,ic 10 block s)'mbol and sallC.
-. -.
"
-'
Enler scgmcm -< schenudic.
,. . ...
----
-'-
·-tt
~
.
;::,;;:;,
"
'-
J .
~
,......
,o,
s;!\"t-_
..
c
~
-.
Run fUI1<:Ii<)ll;lJ s imula!i(IfJ.
~- -'" Convert l>Chcmal ic h> block
~ymbol
and s:,,·e_
DIGITAL SYSTEM APPLICATION
_--- --- -----
","",-.
...
'. ~ - '"-,..=,-.
_._.
.
--
..... •
,
_-----
0
," D
~
•
0
-", D
I
,
C()Jl,·cn schemmic 10 bloc k symbol aOO save.
_-- --
__----;c - --,...........
• '---I>-c
,-
Com ·en .;chernat ic 10 bl{)o:; k sy mbol a nd save.
.~r:
_..... -_.. '
.
. _.------, , -, -.--------------"
~ ;;-~-,-
,... •
-'
Ent(T segment -I: schematic.
I
.... ~--------.- .......r
.~---------,-
- - ;;;:-;- - - - - - - - - -
_w
- -- _,
r
Ru n funct ional simulation _
-
rt
i !,r
'
•
--
.....
-' - '
I
-_. ... _-------
_--_ -
-y, , ,;.
-_. _. ~~T~"" ~ -----,
......
673
L
_.-to
Ent(T scgmcnt.Jschcmatic.
,
c
Run functional simulatioo _
Enter so-gmc nt-e schcmal ic.
-_ ... _
'L
- '.-y
'.
~
-'
,--,
'.,
•
o
"
D
Run funct ional simulat ion.
,. . ."E[].c..... ""'*
I!
CQ",·cn schematic to block symbol lind sa' "C-
FIGURE 11-88
Screens for segment log;c (e, olctivity.
legment-g logic. The functionol l limuloltionl (or legmen~ e, f, olnd g olre left al oln activity. Final Block Diagram All of the block Iymboll for the segment logic h;we been SilVed olnd now can be re<:allo:d for UiC in the complete 7legmen t logiC. The symbol! ilre olcccucd u,ing the Symbol window,justils Wol' done for the selection of logic gates. Thc file they olrc stored in il opened and the lilt olppeoln, auho.."" in Figure 11 -89. The input olnd output pinl are added and olll of the block symbols arc connected to form th e complct.c segment logiC.
r, and g). The outpu t waveform~ in each ca)e ol re to be completed a) an
Timing Simulation After the complete cirC\.Jit has been entered in the Gr
glitches, ~u would go ~ck to the dcsign olnd try to CO
A Juccessfu l timing simulation meam tha t the logic circuit u.uks al expected in terml of both functionality and timing. The next Itep .1 to convert the multipleblock diagram into a lingle block ~bol, olS iII ultr.l ted in Figure 11-91, (or possible later use. Procramming the Target Device Alluming the timing simololtion indicatcs no problem!, the nC(trtep;' to progr
674
•
PROGRAMMABLE lOGIC AN D SOFTWARE
Clid lho: G,~
, )mhol ' ·1 \"i~
A S\ogmO!ut-a D
"],
C B
SEG:J
""
C B A
SEGb
A
[g
D C
"
C B
R A
A
'" D
D R A
C
C
SEGg
SEGr
B A
B
A
----------------
£!
Symbol
I
libraries ~k"llhc Ii i" "h~rc )c >U
!o3\"t:t1ItJ., I>I, ...!..,~ 01001, rc'€ tho: ~11 ~ nl ~l!;it:, Oid 0".
Cllnlin ..... \0 -.e lecl 0\11 I b~ blud ')llIbt,l, an mllllho:n jnICrt:lmn~""1 all 01 dlol: bloc!.. ",mbtll' 1{l11t.: inpuI' nllll ... "dl bhll:!.. hI ii' OlIlpul.
~
~
Segment file Segmenla Segmenlb Segmentc Segmentd Segmenle Segment! Segmentg
Sq:nwnl.a Lngic
-
-
D C
B
SEG"
-
A
~
COt< ,
Cancel
FIGURE 11 _ 89
Selection, placement.. <'Ind interconnection of the Icgmcnt logic in the Gri'lphic Editor.
DIGITAL SYSTEM APPLICATION
_ 0 x
Waveform Editor
Name: ~- A ~- B
,"'--'- C I~ D
SEGa I~
SEGb
-c;.. SEGc "'-'" SEGd ~ SEGe
! ....... SEGI
I-£' SEGg
.
.- .. , .
~
~
FIGURE 11 - 90
Ideal timing simulation for the complete 7-.cgmcnt logic in Figurt! 11-89. The segment w.wcforrnl for e, f, and g arc to be completed as an activity.
File Edit View Project Assignments Processing
Pia.:..· ~nlll:"" n~'t.' inpul at1O.l output pins I ~ "'Ink' ,,~> ," you (ji(j lor Ill(: ~I]t:m.. til:
"
0
'l.
D
D
~
Il
C
C
Il
A
A
[g
SEGa SEGh SEGc SroJ
SEGa SEGb SF...Gc SEGd
SEGc
SEee
SEGg
SEGr SEGg
: FIGURE 11-91
The complete BCD-to- 7-segmcnt decoder as a single block symbol.
•
675
676
•
PROGRAMMAB LE LOGIC AND SOFTWARE
FIGURE 11 - 92
I!'I
Device
Selection of the b rget device.
&1.....:[ the 00 ke family for tJ ~ t:tq;CI: Oe\ in'. _ Se IL'C1 [he 'J1C'Cl li..: tJ.."\KI.° in Ill<: dll....:n I;'mil)
Device Family
Specific Device
MAX II MAX3000A MAX 7000
EPM70328 EPM7064B EPM7128B EPM72568 EPM7512B
CYCLONE STRATIX STRATIX II STRATIX GX APEX II APEX 20K
FLEX 10K FLEx lK FlEX 600Q MERCURY
Download complete
(QD
, FIGURE 11
91
The ~gn hal been downloaded to the target device on a developme nt board.
the interface, ~uch as)TAG. Next, select the brget device from the Select [>e..,Ce
number of gates CoMl be programmed into a single PlD. Often the limitation is the
to, most software will automatically assign
window. as shown in FigLJre 11 -92. Keep in
number of inpull and outputs that are
the assignments.
mind that a very small percentage or the capacity of a tw~1 programmable devic::e will be UJed for a circuit the sire of ou r example. ThoUJandl of drcuib with a similar
them fo.you and make ~ilable a lilting of When the device selection is complete, the design is down loaded, ill indicated by the Download Complete me~ in Figvre 11-93.
SUMMARY
!n-Circuit Testing After the design hM been dO'%filoaded to the t .. rget device, hardware testing;' usually the next ltep. Prior to this, only software simulation httern generilltor to supply
the inputs ilII1d an osciIJOKOp<:: or a logic aOillJyzer for observing the outputs fTlilI)' be required. In the cale of the 7-regment deooder logic that has been downloaded to the t .. rget device, a simple test can be done using the resotJtcei
•
677
development board. ~ there features, al indicated in Figure 11-94. SYJtem Auignment
• Activity' Verify that the SEc... output waveform in Figure 11-85 il c~rect. • Activity 2 Verify that the output waveforms for segments b, c, and d in Figure 11 - 87 are correct.
• Activity 3 Determine the correct output Wilvefomu for segments e, f. ilInd g in Figure 11 - 88 and Figure 11 - 90.
S" II<:IIe • ..:"mlC\:I~'() 10 do....,.. k t! Inpul'.;,..._ _ _......
-
7-"-1!n...,m
di~rla~
n>n.nccfL'lllo
.Ie, iL1""
,~ --
nUlpul~
'LoooiI
FIGUR£ '1-94
Example of the target device mounted on oil development board being tested with on board ,witches "nd 7-regment displ"y.
•
A PAL is a one -li me pmg ram mablc (aT""P) S PLD cnn sisling of a programma ble amlY of AN D gates that connects to a fixed array o f OR gmcs.
•
T he PAL s tRIc tu re allows a ny sum-or-products (SOP) log ic expression with a de fined num ber o r vari ables to be imple mented.
•
The GAL is o:s~nti a lly a PAL that can be reprogrammL-d.
•
In a PAL or GAL.. a macn lCell ge nerall y consisls of one OR gate and some ~ssudated output logic.
•
The PALI6V8 is a com mo n type of prog rammable array log ic device.
•
The G AL22V l O is a com mon t}'pC of ge neric arr.1)' logic device.
678
•
PROGRAMMAB LE LOG IC AND .sOFTWARE
•
A CPLO is a complex programmable logic device Ihal L-on~ i~t s basically of mu Uiple SPLD :UT'dYS wi th prog ramlT4~ble interconnections.
•
Each SPLD array in a CPLO is calkd a logic array block (LAB).
•
The MAX 7000 is an Allera family ofCPLDs.
•
In the MAX 7000 CPLD fami ly. density mngcs from :! LABs to 16 LAB~. depending on the particular device in the series. and each LAB has six teen macrocells.
•
The Altera MAX II CPLD dIffers tlrammically fronl the MAX 7(0) liunity and is known :L~ "post-macrocell" CPLD.
•
The MAX 11 CPLD uses look-up lablc~ (LUn instead of AND/OR armys.
•
1lJe architecll1re of the Xilinx CoolR unner II CPLD family is b.~~d on a PLA stmctu re rathe r than on a PAL structu re.
•
'I" e CoolRun ner II fmnily contains C PLDs ra nging rrorn 32 nmcrOl.·d ls to 512 nmcrucells.
•
A macroce ll can be configurcd for ei ther of two modes: the reg istered mode.
•
An FPGA (fi c!d-progmmmable gate array) differ!> in archi tecture. docs not usc PAUPLA type arrays. and has mut'h grea ter den sities than typical C PLDs.
eombin~tional
11
mode or the
•
Most FPGAs use either anti fu se or SRAM-hascd process tcchno IO.H.
•
ElIch conligurable log ic block (CLS) in an FPGA is made up of multiple smaller log ic module~ and a local programmable interconnect th~t is used to connect logic m(xluies wi thin the CLB.
•
R'GAs are based on U Jr architecture.
•
LUT stands for look-up tab/(>, which is a ty pe of memory that is progranlmablc and used to ge nerate SOP colllbinationnilogie functions.
•
A hard core is a portion of logic embedded in an FPGA that is put in by the manufadurcr to
•
A soft-core is.1 portion of logic embedded in an FPGA that has some prognunmab1c features.
provide a specific funct ion and \\-hich cannot be rc prog rammed.
KEY TERMS
•
Designs owned by the manufacturer are tenned illtellec/ual pm/Jerty flP\.
•
Alterd pnxluces several fam ilies of I'l'GAs including the Strollix II . the S tratix , Cyclone. and the ACEX family.
•
X i lin~
•
The programm ing
•
The devi ce bei ng progmrmned is usuilily referred 10 as the target devi<.:e.
•
In software pacbges for programma ble log ic, the opcrntions arc controlled by an appl it'ation program called the compiler.
•
Du ri ng downloading. ~ bilStrcam is gcncnued that rt'prcsems the final desi gn, and it is sent to the target device to :1tltomaticilll y configu rc it.
•
The bcd-of-nails (BON) method was one of the first approaches to automated circuit board testing.
•
Anothcr method fOr test ing printed circuil boards is callcd the flying probe method.
•
A me thod of internHII)' teSiing 1I programmable device is called boundary scan. which is based on the JTAG standard (IEEE Std . 1149. 1).
•
The boundary scan logic in a CPLD consists of a boundary scml register. a bypass register. an instruction register. and a test access port (TAP).
has two major lines of FPGA!>. the SpHrtan and the Virtcx. and thert' are dilTerent fam ilies within each line. proces.~
is generall y referred to as design flow.
Key terms and other bold te rms in the chapter are defined in the end--or-book glouary. Ikd-nf-Im ils A me thod for the au tonlated testing of printed circuit boards in whic h the board is m(Junted on a lixture that resembles 11 bed (Jf nails that makes cnntact wi th test po ints. Rcmndary sc.:all A method 1'0.- internally te sling a PLD txt<;C(\ on the JTAG standard (IEEE Std. 1149.1). CLU Configurable logic block: a unit of logic in an FPGA \hat is made up of mu ltiple smaller logic modules and a local progmmmable interconnect that is used to connect logic modules within the CLB.
SElF-TEST
•
679
Compiler An application program in development software p.1ckngt:S thllt controls the opl'rdtion of the software. CPI.D A mrnplex programmable logic device that consist~ basically of mult iple SpLD arrays wilh program mable illtcrconncctions. Dcsign now The process or seq uence of operations carried out
[0
program a target device.
Dnwllioodillg The filial step in a des ign now in which the logic dcsign is imple mented in the tarl;et device. Fitter 1001 A com pile r software \()olthat selects the optimum intermnncctions. pin a~si gnme nt s. 1Ind logic cell assignments to fi t a design into the selected large t device. Flying probe A method for the automated testing of printcd circuit boards. in which a pmbc or probcs move from place to plate to contact test poinlS. FPGA Field progrOimmable gate arrdY: a prognul1mable logic device th;!t UlieS the LUT as the basic logic c lement and generally e mpl oys either antifuse O£ SRAM·b(lscd process technology. FUlictioual simulatioll A
softw~rc
process th(ltt ct>ts the logical or funct ional operation of a design.
GAl. A reprogmmnmble lypc of SPLD th1l1 is simi l'lr 10 il PA L cxcept that it uses a reprognllnrn.1blc process IL'C hnology. such as EEPROM (E2CMOS). instead of fu~es. Inlcllt.'Ctmd property (If', Designs owned by a manufOicturcr of prog ramm:ilile logic devices. I. AB Logic array block: an SPLD array in a CPLD.
l .UT
Look~l1p
mble; a type of mem ory thm can be progmmmed to prod ucc SOP functions.
Macroccll Pan of a PAL. GA L, or C pLD that ated outpul logic.
g~nerally
m nsists of one OR ga te and some associ-
PA l. A type of one-time programrru.lble SPLD thnl consists of a programmable army of AND ga tes that conntt\s 10 (I fixcd (lrT"dy of OR gates. Primith'e A ba.. k logic clement such as a gale or ni p-nop, inplJtlout pul pins, ground. and VeeRcgislen'(l A macrocell operational mode Ihm uses a nip-n op. Schematic clllr), A me thod of placing a logic d~ig ll inlo SOftwlll'e usi ng schematic s)'mlxlls. Ta'l:ct dcvice The pmgrnmmable logic device that is being progrum mcd. Text eu tr), A me thod of placing a logic guage CHDL).
de ~ign
into soft wa re usi ng a hardware desc ription Ian·
Timing s.imul.diull A soft wlt.re process Ihat USC'S inform
Answers are at the end of the
1. Two types of SPLDs are (a) CPLD and PAL
(b) PAL and f'PGA
(c) PAL and GAL
(d) GA L and SRAM
2. A
PAL cOII~jqS of a
(a) prog rammable AN D array and a plUJ!:T"dmmable OR array (b) programm Oible AN D army and a fixed OR It.rrd.y
(d fixed AND amlY and a progmmmablc OR array (d) fi xC
3. A macrocell consists of a (a) fi xed OR ga te and other assoc iated logic
(b) progmmmable OR army (lnd other associated logic (e) fh ed AND gale and OIher ~soc imcd logic (d) fixed AND/O R amy with 4. The 16V8 is a type of (3) CPLD
Cb) GAL
(e) PAL
Cd) FPGA
(I
nip-nop
680
•
PROG RAM M AB LE LOGIC A N O SOFT WARE
S. T he basic ANDIOR structu re of S PLDs and CPL Ds produces typ::s of Boolc.1Tl c1(pressions known as (it) POS
( b) SOP
(e) prod uct of complements
(d ) sum of com plements
6. T he term L4B stands for (II) logic AND block
(h ) logic array block
(e) last asse rtcd bit
(d) logic assem bly bloc!;:
7. The MAX 7000 is a
,.
(II) fam ily of C PLDs
(b) fam ily ofSPLDs
(e) fami ly of Fl'GAs
(d) type of SOflWOlfe
1be Cool Runner II is II th) fam il y ofS PL Ds
(II) fam ily of Cl'LDs
(c) fam ity of
FPGA.~
Id) type of softwarc
9. Two modes of mocroccll opermion :Ire (it) input and omput
(b) n.:gh lered and seq ucntial
(e) combinal ional and reg istered
(d) parallel and shared
10. When a macn.)Cell is configu red 10 produce an SOP funelion. it is in the (n) combinalional mode
(b ) p.1Ta llcl mode
(e) fegislcrcd mode
(d) shared mode
11. A typical macrocc ll consists of
(a) !;iltes. mult iplc1(c rs. and a flip-flop (c)
a G ray eode counter
(b) gatcs and it shift registc:'r (d) a fi xed logic amlY
12. Based o n the complexi ty of its configu rable log ic bl(x:!;:s (CL Bs). an FPGA Clm be clas~i fied as cither ht) vo llllile o r nonvolat ile (b) prog ra mmablc or reprugramlllabic (e) fine gr.li m:d or co..1rsC g rained
(d ) platform or embedded
13. Nonvolatile FPCiAs are gcocrally based o n (a ) fuse techno lo!:y (h i anl ifuse technology (c) EEPROM Icchnology
(d) S RAM le<: hnolo£),
14. A n FPGA with an em bedded Ingic function Ihm cannot be progra mmed is said to be (id) nonvolatile
(b) plulfoml
(e) hidrd cor-e
(d)
"Oft core
15. H:l rd core designs id~ general ly developed by and are the property o r the Il'GA manufactu rer. These de~i@ns are ca lled
I ().
(a) intc ll e<: tu .11 propen y
(b ) pmprietary logic
(e) custom deSig ns
(dl IEEE stlmdards
For text en try of a log ic design.
(a) logic symboll' mUl'l be used
(b) an HD L must be used
(e) only Boolclln algebra is used
(d) a special code mu~t
17. III a functional simulalion. the usc r must specify the (b) OlIlput wi1\"eform
(c) inpu t waveforms
(d) IiDL
II!. The I1na l OUlPIII of the syn thesis phase of a desig n (it) nellist
(bl bitslream
(e) lim ing simulation
(d ) dev ice pin numbers
now is the
be used
PROB LEMS
•
681
19. EDIF stand~ for (a) electronic device intcrchange format (b) e let-irieal design integrated fi )l:ture (e) elct:lrically dcstnlctivc input function (d) electronic dcsign interchange fOrm;l! 20. Thc boundary scan TAP stands for (a) Icst
ae!':es~
point
(b) Icst array port
(e) Icst acL'CSS port
(d) tenn inal aCL'CSS path
21. A Iypkal boundary scan cell oonlllins (a) fl ip- flops only
(b) ni l>-flops ;md multiplcxcr logic
(c) lawhcs and nip-flops
(d) hllt'hes and an cncoder
22. J\n automatcd printcd cin:uit board tcst mcthod that usc~ a fi xt ure wilh many liKed contOlcts to thc boMd tcsl point is called (H) traditional (c)
bcd-of- nail~
(b) fl ying probe (d) boundary SCOln
23. An automlllcd printed circuit board
le~t
(a) tmdilional
(b) flying probe
(e) IlCd_of_nails
(d) boundary
method tha t uscs a moving test point Lunlact is callcd
~an
24. Thl' JTAG standard has the following inputs and outputs (a) Intesl, C)l:tesi, TDI. TOO
(b) TDI , TOO, TCK. TMS
(c) ENT. e LK. SHE CLR
(d) TCK. TMS. TMO. TLF
25. Thc acronym BSDL stands for
PROBLEMS SECTION 11-1
(a) board standard digital logic
(b) boundary scan down load
(c) bistablc digi tal latch
(d) boundary scan description language
Amwers to odd-numbered problems are 'I t the end of the book,
Programmable Logic: SPLDs and CPLDs 1. ()ctcrmine th c Boolean OUIput cxprcs~ ion for thc simplc PAL array shown in Figure 11 - 95. The Xs represent lunnccled links.
FIGURIE 1' - '1S
A
-
n
n
c
r
} )-=
}
x
682
•
PROGRAMMABLE LOGIC AND SOFTWARE
2. Show how the PAL-type array in Figu re 11- 96 should be progmmmed to implcmc nt ea..:h of the fo llow ing SO P ell press ions. Usc
(a) Y = "BC ~ IiBC
(b) Y = IIBC FIGUR£ 11 - 96
-,
•
+ IIBC + ABC + IIBC +
c
IiBC
c
}
}=
x
3. Interpret each of the PAL device numbers.
(a) PALl6 L2
(h) PALl 2H6
4. Explain how a programmed pola rit y output in a PAL works. 5. Desc ribe how a C PLD d iffers frum an SPLD.
SECTION 11 - 2
Alte,., CPLDs 6. Refer to the MAX 7(XXJ block diagram in Figure I I - I I and d ete rmine the number of
(a) in puts from the PIA 10
11
LAB
(e) inputs flOm an I/O control bl(x:k to the PIA
(b) oUlputs rrom a LAB to the PI A
(d) outpu ts from a LAB to an VO control block
7. De term ine the product term for the AN D gate in a CPLD "n'~y sh"wn in Figure 11- 97(3). If the AND g:He is exp;mdcd. as show n in Figu re 11 - 97(bl. detenn ine the SOP ou tpul. FIGUR£ 11 - 97
___
,
1--
0£
~ --r-
c
}- x (b)
8. Determ ine the OIllpll t of lhe macnJl.:cll logic in Figu re 11-9A if ABED the parnll e l cll pandcr input. fiGUR E 11 - 9.
I'm..... llel expander input
+ ABeD is applied to
PROBLEMS
SECTION 11-3
•
683
Xl1inx CPLDs 9. [)ctennine the ou tput of the PLA in Figure 11- 99. The Xs represent connected links.
FIGURE 1 t-99
rlAHli
~X
10. Refer to [he CooIRunncr 11 CPLD bloc k diagmlll in rigurc 11 - 2 1 and detennme the number of (a) inputs from the AIM 10 an Fa
(b) outputs from an FB to the AIM
(c) inputs !Tom an 1/0 hlnek [0 the AIM (d) outpu ts from an 1"'13 to an 110 block
J I. DClermine [he output ex pressions for X, and X! from macrocdJs 1 and 2 in Figu re 11- 100.
,------,~
P=< ~
n
P=< P=<
0, , ,
Su rn 'l~rm
ProdLlct. term
,
I
8
(
IJ
Iy-~~':~-
16
,
X
FIGURE 11-100
684
•
PROGRAMMAB LE LOGIC AND SOFTWARE
FIGURE 11 - 10 1
SECTION 11 - 4
Macrocells 12, Dctenninc the dma ou tput for thc mult iplexer in Figure 11- 10 1 for each of the following I.:onditions: (.a) 1)0 = I,l)l = 0, Select =
°
(b) 1)0 = I,D I = O. Select = 1
13. Dete rmine how the macrocc ll in Figure I 1- 102 is configured (combi national or registcred) and Ihc dala bil lhat is on the ou tptl t (10 I/O) for each of Ihe following wnditions. The !lip-flop is a D type. Refer 10 Figure 11- 10 1 for MUX dnta input arran geme nt. (.a) XO R out pul = I . flip-flop Q ou tput .:. 1, from va input = I, M UX ! select = I, MUX 2 select = 0, MUX 3 select '"' 0, MU X 4 sclect = O. nnd MUX 5 )C lect = O. (b) XOR output = O. flip-flop QOUlptJt = 0. fro m If 0 input = I. MUX I select = I. MUX 2 select = 0, MUX 3 select = J, MUX 4 selecl = O. and MUX 5 sclcct = 1.
,, ,
(,I,,,",," d ..··
I'
I
Frum
MUXS
I
.= pJD ,
-,--"
""",,"~k.'C(ion
matri.o;
-D-
,,, ,,
--'--,
MUX I
..)
MU~
I'RE J)fr Q
--
I" I/O
C
EN
v2tkx]
-- -,, ,
~)
I/O
CLR
I JMUX4
-- --
<~
;(,1111'
Imm
1': \
•
I"''''t..
1'1 1.1
" Ir
FIGURE 11
102
cond i tion~ arc programmed: MUX I select I , MUX 2 select = 1. MUX 3 selects 01. MUX 4 select = O. MUX 5 selcct = I , MUX 6 ~e l cct s = J I, MUX 7 selects ~ I I, r-,'IUX 8 select = I . and the O R o utput = I . The fl ip-fl op is a D type and the MUX in puts
14. For the CPU) llHler(lcell in Figu rc 11- 103. the fo llowing
=
=
(.a) Is the Itmcmcell \:onfigurcd for combinational or rcgj~tcrcd logic?
(h) Whic h clock is app lied to [he nip-flop'! (c) Whlll is the data bi t on the D inptilto the flip-flop'! (d) What is the output ofMUX 8? 15. Repeal Problem 14 for MUX I select - O.
PROBLEMS
•
685
F...·t,tlt>:....·~
[oA IM f'TA
crs CSR ~
GND ___________ +-__+-+____
I-Tl~ll
IJO MUX8
MUX 2
L
-1-1\-____---l PTe
Off
s
Q
f--'- --L..-J
CE
CK MUX]
MUX5
GC KO GCKI GCK2
Produc\-Icrm amI)'
II
1 - - - - 40 fmmAIt-.
M UX I
\'ce (l)
MUX4
GI\D(O)
MUX7
f'TA
erc
ers CSR
PTC
GNO - -
fIGURE " - 103
SECTION 11-5
Programmable Logic: FPGAs 16. Generall y, what elements make up a configu rablc logic block (C LB ) in an FPG A'! What clements make up a logic module? 17. Determine the out put ex pression of the LUT for the intern al conditi ons shown in Figure 11 - 104.
18. Show how to reprogmm the LlIT in Figure 11 - 104 to prod ul.'e the following SOP output
ABC
t ABC
+ ABC
FIGURE ' I - 104
ScI<.'Ct;on logic
Memory c"l1 ~
o
2 ]
/I (
SI)I', ... n plil 4 S
6
7
1<. 1(0
686
•
PROGRAMMAB LE LOGIC AND SOFTWARE
SECTION 11-6
Altera FPGAs 19. Name the basic clements thllt make up an llJaptivc logic modu le (ALM) in the Stmtix II FPGA. 2ft List the modes of operation for an A LM.
21. Show an A LM configured in the norm!!l mode to produce onc4- \'ari ablc SOP funct ion mId one 2-lIl1riahle SOP function. 22. Determine the finll! SOP Out pul funct ion for Ihe ALM shown ill Figure 11- 105. FIGURE 11 - 105
,
,\~/I,A,A, +A~A ,AlA,
ALM 4-inpul
I
LUT
-SECTION 11-7
4-i npul
LUT
l-t>
j
l
Xilil\Jl FPGAJ 23. Usc olle or morc oft hc slices in l-igure 11 - 106 10 produce the SOP I"UI1Clioll:
FIGURE 11 - 106
LUT
wr Slice
24. A slice from a Vinex rPGA is shown in Figure I 1- 106. Show how one or more o f these slices can be configured 10 produce the SOP function:
Assume that the rei.! clements as well as the U 1Ts are rcconfigurablc. 25. [)clemline the number o f sl ices (Figure I 1- 1(6) required 10 gCllernte the cxp:l:ssion:
A.,Ati\..,A,y\y1.;oA I~ 26. Dclennine the numoc'T of slices required 10 genemle the expression: A7A (,A..,A.y1y1.0,AQ+ B7BJJ51J4BjB2B j/Jo + C7 C6C~C, C3Cl CJCU
PRO BLEM S
SECTION 11 - 8
•
687
Programmable Logic Software
27. Show the lugic diagram thm you wou ld enter in the Graph ic Editor for the circuit described by elleh of the V HDL progmms.
a. entity AND_OR is port (AO, A I, A2, A3: in bit ; X: out bit): end enlil y AN D_OR; architecture LogicFunction of AND_OR is
Ix:gin X <= (AO and A I) or (A2 and not A3): ('nd archilel1urc LogicFuncti on;
b. entity LogicCircui l
i~
port \A, B, C. D: in bit : X: out hit ); end enlity LogicCirc uit; architectuJ'C Function or Logi(;Circu it is
bt:gill X <= (A and B) or (C and D) and (A 311d 1101 13) a nd (not C and not 1)): end archit«:llIre Function; 28, Show Ihe logic ci rcuit lhllt you would en ter in the Gnlphic Ed itor for the following Boolean expression. Simp lify before enterin g, if possible. X =
ABCD + ABeD + AllCD + ABeD + IIlJeD + ABCD
29. TIIC in put wlIvefcrms for the logic cirwit dcs<:ribcd in Problem 28 arc as shown in tile WaVefOl1l1 &litorof Figure I I- I(fl . l)ctl, wure the output wavcfOrnl th;u is r.--oducui aflC!" runni ng a simulmion. FIGURE 11 - 107
Name:
e- A
0
B
0
C
0
£.,-
....,- D 0 -.::;. X
X
30. Repeat Problem 29 for the fo llOWing Boolean ex pression:
X =
SECTION 11 - 9
AIJeD + ABGD + AIJCD + ABeD + ABeD
Boundary Scan Logic 31. In a given bOLUldmy ~can cell. assume Ihat data now seriall y from the previous BCS to the next BSe. Describe what happens as thc datil pa.~s thfOLlgh the givcn DCS. 32. Describe th e condi tions and whm happells in a given BCS when data now di rec tly fmm the internal program mable logic to 1I device OUtput pin. 33. Describe Ihe (;()ndit ions and what happens in a given BCD wlICn iliI ta now from 1I device inpu t pin to the illtcrnal progmmmab le logic. 34. Descri be the data path for transferring dma from Ihe SOl 10 the imem al prOgra mma ble logic.
688
•
PROGRAMMABLE lOGIC AND SOFTWARE
SECTION 11-10
Troubleshooting 35. Develop a boundary ~can test bit pUllern to I Cst the logic that is programmed into the device shown in Figure I I- l OS for all possible input combinations.
FIGURE 11 - 108
TOO
TI)l
TCK
TMS
Digital System Application 36. If the logic for thesel'cn segments shown in Figure 11-79 life entcred in the Graphic Editor as a nat schematic. how many lind which clemcnts can be eliminated"! 37. A simulution for the 7-segment logic is show n in the Wavcfoml Ed itor in Figure 11- 109" Dctemline what the problem may be with Ihe sirn ulmcd cin:ui t. FIGURE 11 - 109
Name: __ A
...... SEGb ...... SEGc SEGel =.;
SEGe
...... SEGI "=-' SEGg
ANSWERS
•
689
SECTION REVIEWS SECTION 11 - 1
Programmable Logic: SPLDs a nd CPLDs I. PAL Progmmmabic Array Logic
2. GA L: Gcneric Array Logic 3. A GA L is reprogrnnunable. A PAL is one-time prognmllnablc. 4. Bas ically, a macrOCCll consists of ;m OR gate and
a.~s()c iatcd
output logic incl udi ng it ni r-flOIl.
5. CPLD: Com plex ProgrJ mmable Logic Devicc
SECTION 11-2
Allera CPLDs I. LA B: Logic Army Block
2. A LAB consists of 16 nmc rocclls in the MAX 7000 fam ily. 3. A sharcrl e)\ pa nder is used to increase the number of product tc nll~ from a macroccl l by AN Ding addi tilJl\al sum t<..'TlIlS (complementa l product terms) from other macrocel ls. 4. A pamllcl eXJXlndcr b used to im.:rcasc thc nu mber of product lCl1n~ from;1 lllilCroccil by O Ri ng unused product te nlls frolll other lllac roccl1s in a LAB. 5. TIIC MAX II is organiJ".cd in a row/co lumn architcclure and uses LUTs in ils macrocclls. ·111c MAX 70CXJ i~ ol"guniJ"..cd in a tmdilional column "rchitccturc and uses SOP logic in its macrocclls.
SECTION 11-3
Xilin" CPLDs I. AI1(.111 uses PAL architCC tu TC. Xilinx usc~ PLA architecture.
2. A PLA has a programmable AN D arrJY
fixed O R army.
4. FE: Function block
SECTION 11-4
Macrocells I. The XOR g
2. Combinational and reg istered 3.
Regi ~tered
refers 10 the ll'iC of a ni r- nop.
4. Multiplexer
SECTION 11 - 5
Program mable logic: FPGAs I. Generally. an A>G A is organiJ"(xl wit h a row/colulllll inlerconnttt structure WId uses LUTs rather lhan ANDIO R logic for generJting combination
2.
a~B:
COflfi gur.;ble Logic Block
3. LUT: Look- Up Tab le. A program ma ble type of memory that is used 10 store and gencflIle oo mbi nat ional logic funct ions. 4. A loc
FPG A manufacturer.
SECTION 11-6
Altera FPGAs 1. The LAB (Logic Array Block) is the
ba~ i c dc.,~ign
un it in the Strat ix II.
2. ·IYpicall y. there arc eighl ALMs in a LAB. 3. An LUT prod uces combinmional illgic functions in an ALM. 4. Two 5. Memory and DSP (di gital signal processing)
690
•
PROGRAMMABLE LOG IC AN D SOFTWARE
SECTION 11 - 7
Xilinx FPGAs t. A CLS consists of eight logic cells or four slices. 2. A LC (logic cell ) consjst~ of an LUT and associatcd logic.
3. A slice consists of two logic cel ls (LuJ. 4. A c!lscade chai n is two or more slices connected 10 expand an SOP expression. 5. ASM BL: Application Specifi c Modu lar Block
SECTION 11-8
Programmable Logic Software t. Design enlly. fU!lctional simulation, synthesis, im plementation. ti ming simulmio n, downloading 2. Com pUicr ru nning PLD dc\·e lopmenl soflwmc. a programming fi xture or " developmen t boord. and an in Wrface cable A nelliSI provides infoml
3.
4. TIIC fu nctional simulation comes before the timing simulation.
SECTION 11 - 9
Boundary Son Logic I. 11)1. TMS. TC K, T RST. TDO
2. TAP: 'Iest access port 3.
Boundary
SC;1ll
register, bypass register,
i n~truction rL,£i ~tt..'T,
and TAP
4. Tr.lnsfcr of data from SDI to Soo. transfcr of data from intcrnal pnJgr
SECTION 11-10
Troubleshooting I.
Bcd-of-naiJ~ tcs ting utili7£s a fix ture consisting of 11 fixed am,y of test probes (resembling !lails) o nl which a circuit brnmJ to be tcslcd is placed. F...
2. 11lt' bcd· of-nails (BON) mcthod is limi ted by the densit y of pmgramnlablc logic dellices. which makcs many contacl~ on a devicc inaccessiblc.
3. In a flying probe fixture. one o r morc probes moves from onc test POi !lt to anothcr 011 a PC board in a con trolled pattcrn.
4. Boundary scan enllblcs the intcmlll tcsting lind progr'JIl\l1l ins of 11 prognl1l11l1ablc logic dev ice and tcsting of intcrrOntlcctio ns betwccn two or more dev ices. It is based on the JTAG IEEE SId. 1149. I. BOl.1n dllry scan uses specifi c logic int ernal to the dt..'Vice for testing. S. Intcstll11d Ex tcs! 6. T D I. TOO, TC K, TMS
7. I3SDL: Boundary Scan Descri ption Lang uage
RELATED PROBLEMS FOR EXAMPLES 6-1 X = BC
+ ABC + Aii + C
6-4 Sec Figure 11- 110.
6-2 S ixtecn
6-5 See Figure 1 1- 111.
FIGURE 11-110
5-infll" L lIT
3-input LUT
6-3 S ixlren; six teen
ANSWERS
I
\~ \ <..I ~
+ I , I .A. I " A --,I".\ ,...I~
+A vl !. I,A"
+ H H, H, II~ + R1 H~ X I Xo
I, I,
Hoo II , H. II ,
•
U JT
LUT M UX
, I. I, I.
II , II,
LUT
H,. H,
I ,
Slict! t
LUT
1
I"
Stitt 2
Reli" li~li~
fiGURE 1'-'"
SELF-TEST 2. (b)
5. (b)
6. (b)
7. (a)
I. "j 10.
,,'
II. tb)
12. (e)
13. (b)
14. (b)
15. (a)
16. (a)
19. ,dj
20. (e)
21. (b)
22. (e)
23. (b)
24. (b)
25. (d)
3. (a)
4. Ie)
8.
(a)
17. Ie)
...••
(e) (a)
•
691
u
IN
N
C CHAPTER OB)ECTIVES
CHAPTER OUTLINE
12-1
The Beuie Computer
•
Name the b'lIic units of a (:omputer
12- 2
Microproceuors
•
No'lme the bdlic elements of a microproceso.or
12- 3 12- 4 12- 5 12-6 12- 7 12- 8
A Specific MicroproceuOI" Family
Explain the bollic operation of .lo Intel CPU
Computer Programming Explain the b.nk architecture of the Inte l microprocessor
Interrupts
Direct Memory Access (DMA) Intemallnterfacing
Standard BU.les
•
Explain the multiplexed bus operation of the Intel microprocessor DileU" the lOftware model of the Intel Pentium procenors
De«:ribe a simple ;membly language program
INTRODUCTION
Decribe the seven instructio n grou p1 for the Intel proc::essors Distinguish between assembly language and m,lI;hine language Compare polled I/O, interrupt-drivcn IfO, and mftware interrupts Describe the functions of PIC and PPI de0ccs Define and expl"in the iKlvantage of DMA Explain how function! are interfaced by the
u~
of bus systems
Define the basic characteristio and ", pplications of the PCI and ISA internal bus standards Define the b",sic ci1aracteristio and applications of the RS232C, IEEE 1394 (FireWire), USB, IEEE 488 (GPIB), and SCSI
external bus standards
This chapter provides a brief introduction to compute~, microproces.sors, and buse5. Naturally, a single chapter must be limited because one or more chapters could easily he devoted to each of the section topics. Keep in mind, however, that the purpose here is to f!Jve you a basic introduction. Thorough coverage of compute~ and microprocessors must wait until a later cou~e. Fo r furthe r informatio n on microprocessors, including dab sheets, go to the Intel website at W\V\V.intel.com. The Intel microprocenor fa milies are brieny discussed. The Intel 8086/8088 processor is used as a · mode l ~ to illustrate basic microprocessor concepts \.\lith recent enhancements up through the Pentium described in furthe r detail. The 808618088 was the first generation of the Intel 8OX86 family. Although the Pe ntium is more powerful and contains advanced fcatures, it is re lated in architecture and basic functions such as the register structu re.
KEY TERMS Poe'
Machine language
Program
Assembly language
CPU
High-level language
Interrupts
Tristate
Peripherals
Modem
Microprocesor
FireWire
Addren bus
U5B
Da~
GPIB
bus
Control bus
~
VISIT nn
COMPAN ION WEBSITE
Study aids fOf' this chapter are available at http://W\V\V.prenhall.comlfloyd
501
693
69'"
•
12 -1
INTRODU CTION TO COMPUTERS
THE BASIC COMPUTER Special-purpose computcrs conlrol various functions in automobiles or applianccs. control manufacturing processes in industry. prov ide games for entertainment, and arc used in navigation systems such as GPS (Global Positioning SyslCm), to name a few areas. Howcvcr, thc most familiar type of computer is the general-purpose computer that can be progrdmmed to do many difTeren t types of things. After completing this seelion. you should be able to • Describe the basic clements in a computer . Discuss what each part of a computer docs • Explain what a peripheral device is
All computers consist of basic functional blocks thai include a central prm.;essing //flit (CPU), memur) ; and il1plll/Olltl'ut port.\". These functional blocks are connected together with three internal buses. as shown in the block ditlgram of Figure 12- 1. The three buses arc the data bus, the address hilS. and the control blls. Input and output dcvices arc connected through the inpu(/output porls. A port is a physical interfaec on a computcr through which data are passcd to and from peripherals. FIGURE 12-1
s...ic computer block diagram.
MCnl~lor.tge:
RAM . ROM. ~·uchc. ham disk
Input/Oulplll
P"'"
CPU ( mkroprocCS>;
Control bus
and pioneer ~met', developed conside... ble a l\i)val
offlCef working with the HaMiro Mark I compu ter in the 194IOfking 00 the computer would reply that , theywere -debugging- the \}'Stem. The term
I II I
Instructions and data arc SlOrcd in memory in specific locations detemli ned by the p ro· list o f instructiOns designed tosolve a specific problcm. Each location has a unique address associated with it. Instructions are obtained by the CPU by placing an address 011 the address bus. Instructions are trdnsfelT(~d via the data bus as thcy arc requested by the CPU. T he CPU cxeeutes the instructions sequentially; fn.:q uclll ly. the instructions modify data stored in memory or obtained from an input dc\'lcc. Processed data may be stored back in memory or sent to an output device via the data tAts. Signals on the control bus arc £cnemted by the CPU to coordi nate all oflhcse operations. ~r8m . a
Central Processing Unit (CPU) T he ('flU is Ihc "brain" of the computer; it oversees everyth ing that the computcr docs. Thc CPU is a microproccssor with associated circuits that cOlltrol the running of the computer software proE rams. Basically, the CPU obtai ns (fetches) each program instruction from
memory and carries out (executes) Ihe instruction. After completing one instruction. the CPU movcs on to the next one and in most cases can operate on more than one instruction at the same time. This "fetch andexecutc" proccss is reperued until a ll of the instructions in a specific progmm have been exccUled. For ex-
THE BASIC COMPUTER
ample, an appli(;a\ion program may require the sum of a series of numbers. The instru(;tions to add the numbers are stored in the form of binary codes that direct the CPU to fetch a series of numbers from memory. add them. and store the sum bal'k in memory.
Memories and Storage Several types of memories are used in a ty pical computer. The RAM (random-access memory) stores binary data and programs temporarily during processi ng. Data are numbers and other information, and programs are lists of instructions. Data can be wr ittcn into and read out of a RAM at any time. The RAM is volatile, meaning that the information is lost if power is turned off or fails. Therefore, any data or program that needs to be saved should be moved to nonvolatile memory (such as a CD or hard disk) before power is removed. The I?OM (read-only memory) stores a permanent system progmm called the BIOS (Basic Input/Output System) and certain locations of system programs in memory. The ROM is non\,olati le, which means it retains what is stored, C1.'en when the power is of!. As the name implies, the programs and data in ROM Cllllflot be altered. Sometimes it is referred to as "firmware" because it is permanent software for a gll'en system. The BIOS is the lowest level of the computer's operating system. II contains instructions that tell the CPU what to (10 whcn lXlwer is first applied : the fi rst instlllction executed is in the BIOS. It controls the computer's basic stal1-up functions that include a self-test and a disk self-loader to bring up the rest of the opcralinfl system. In addition, the BIOS stores locations of system pTOflrams that hundle certain requests from peripherals culled interrupts, which causc the ClilTent processing to be temporarily stopped. The welle mcmo ry is a small RAM that is uscd to store a limi ted amount of frequcntly used data that can be accesscd much fa.~j er than the main RAM. The cache stores "close at hand" information that will be used again instead of having to retricve it from farthe r away in the main memory. Most microprocessors havc internal cache memory ca lled level- I, o r simply LI. External cache mcmory is in a separate memory chip and is referred to as level-2, or L2. The /)arrl di.~k is thc major storage medium in a computer because it can store large amounts of data and is nonvolatile. The high·level operating systems as wcJI as appl.ications soft warc and data files arc all stored on the hard disk. Relllomble storage is pan of most computer systcms. Thc most common types of removable storage med ia are the CDs, flo ppy disks, and Zip disks (magnetic storage media). Floppy disks havc limited storage capability of about 1.4 MB (rnegab}1e). CDs are available as CD-ROMs (Compact Disk- Re."d-Only Memory) and as CD-RWs (Rcwritablc) and can store huge amounts of data (typically 650 MB). Zip drives typically storc 250 M8.
Input/Output Ports Gencrally, the computer sends data to a peripheral device through an output POlt and receives informatiolllhrough an input port. Ports can be configured in software to be either an input or OUtput port. 'Ine kcyboard, mouse, video monitor, printer, and other peripherals communicate to thc CPU through individual pons. Ports arc generally classified as either serial pons, with a si ngle data line, or pamllct ports. with lIlultiple data lines.
Buses Peripherals are connectcd to the computcr ports with standard interface buscs. A bus can he thoughl of as a highway for digital signals that consists of a $el of physical cunnect ions, as well as electrical specifications for the signals. Examples of serial buses arc FircWire and USB (Universal Serial Bus). The most common parallel bus is simply called the parallel bus, which connects to a pori commonly referred to as the printer POIt (although this pori can be used hy other periphemls.) Another example of a parallel bus, for connecting lab instrumenls to a computer, is called the Gencrdl PUfjXlse Jnterface Bus (OPIB).
•
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INTRODUCTION TO COMPUTERS
The three basic types of internal buses that interconnect the CPU with memory and storage and with input and output ports are the address bus. data bus. and control bus. These bu~~ are u.~ually lurllpe t.l il1 lu wlmt i!i called the 100.:tI/ hll.l". T ile
Computer Softwa re In addi tion to the hardware, another major aspect of a computer is the ~ftware. TIle software makes the hard ware perfonll. The two major categories of wftw~re used in computers are system software and appl ications software.
System Software The syste m sot"rware is called the operating system of a computer and allows the user to interface with the computer. TIle most common opetaling syslCms used in desktop and laptop computers arc Windows, MacOS. and UNIX . Many other operdting systems arc used in special-purpose computers and in mainframe computers. System soft ware perform s two basic functions. it managcsall the hardware and soft ware in a computer. For ellample, the operati ng system manages and allot~ space on the harcl disk. It also provicles a consistent interface between appliCl.ltions soft ware and hardware. This allows an npplications program 10 work on various computers that may differ in hardware details. The opernting system on your computer al lows you to hnve several r rograms running at the same time. This is called multitasking. For exnmple, you can be using the word processor while downloading something from the Internet and printing an e-mai l message. Applications Software You use applications software to accomplish a specific job or task. Table 12- 1 lists $Cverdl types of applications software.
TABLE 12 - 1
Appliutions wftware.
APPLICATION
FUNCTION
EXAMPLES
Word processing
Prepare text documents and lellcn.
Minosoft Word. WordPcrfect
Dr,lwing
Prepare technical dmwings and pictures
CorelDraw. Freehand. Il lustratc-/"
M~lIlipllll!le
E);ccl. LOlliS 123
Spre~ldshcet
numbers nod woro5<
in an array Desktop pllblishing
Prepare ncwslellcrs. nyers. books. and other printcd mlHcna l
Quark XPrcs.",
Photography
Manipulatc digital pict ures, add speci:1I cffects to pictures
Photoshop. Image Expen
Accounting
Tilx prcparation, bookkeeping
Quio.;kbooks. Turbotall.
Prcscn tatiOfis
Prepare slide shO\\-'S and IcehniCllI prescntations
Pagemakr
MYOB
databa~s
PowcrPcint. Harvllrd Graphin
Data milll1lgcment
Manipulate lalJ].c
Mu ltimedia
Digital video editi ng. produce mo"'ing images in presentations
Premier. Drcalllwea\"cr. After EflCcls
Fi lemaktr. Access
Speech recognitIon
Convcns speech to tCllt
Nawr.tllySpcaldng
Website prcpar.uion
Tools to crea te web pages and \veb/;ilcs on the Internet
FTOfltPagt;':. Acrobal
Circuit simulation
Create and test ek'Ctrooic CirclliL~
Multisim
THE BASIC COMPUTER
Sequem;e of Operatio II
•
697
When you lirst turn on your computer. this is what happens:
1. BIOS from ROM is loaded into RAM and a self-lest is pelformed to check all major componcnl~ and memory. Also, the BIOS provides information about stor.lge, boQt sequence. and the like. 2. The operating system (such as Windows) on the hard disk is loaded into RAM. 3. Application progmms (such as Microsoft Word) are stored on the hard disk. When you select one, it is loaded into RAM. Sometimes. only portions al'\;: loaded as 1lI.:eded. 4. Fi les required by the application are loaded from the hard disk into RAM. S. When il file is saved and the applicalion is closed, the file is wrinen back to the hard disk and both the applic
The Computer System The block diagram in Figure 12- 2 shows the main clemcnts in atypic
Peripherals
Basic block diagram of a typial Keyboard
Mouse Monitor
port,
CPU
D~ta
peripherals. The computer ibelf is
Printer
Input/Output
comp!Jtcr system including common
shown within the y
t.fc!IIoricslStor.tge: N:AM, ROM, cache, hard disk
bu5
Control bu5 Compo teI'
I
SECTION 12-1 REVIEW
1. What are the major elements or blocks in a computer?
An~nareat~endof~
2. What is the difference between RAM and ROM?
chapter.
3. What are peripherah? 4. What is the difference between computer hardware and computer software?
698
_
12-2
INTRODUCTION TO COMPUTERS
MICROPROCESSORS The microprocessor is a digital integrated circuit thid can be progmmllll.:u with a series of inslructions to perform various opemtions on data. A microprocessor is the CPU of a computer. It can do arithmetic and logic operations. move uata from one place to another, und make uccisions bascO on certain instructions. AflercompletinJ; this section. you
~hou ld
be able to
• Describe the basic elements of a microprocessor _ Discuss microprocessor buses _ Discu",s a microprocessor instruction sel
Basic Elements A microproce",sor consi).ts of several units, each designed for a specific job. The specific unil.s. their design ,md organi:w tion . lII"C t11 lh::d the an:hitt'Ctul"C (do not confuse thc lenn wi th thc VHDL clemeTll). The arc hitecture de termines the instruction Sl.1 and the process for executing those instructions. Four basic units thtll arc common to all microprocessors are the arithmetic logic un it (ALU). thc instmction dccooer, the register array. and the cont rol uni t. as shown in FiJ;ure 1.2- 3. fiGURE 12 - ] M;cropruo:.~
Arithmetic
logic uni t (ALU)
Register
Con trol
array
unit
Arithmeh'c Lo~c Unit The ALU is the key processi ng element of the microprocessor. It is directed by the control unit to pcrfom l arithmetic operations (addition, subtrac tion. multiplication. and uivisiOll) and logic opcmtions (NOT. AN D. O R. and exclusive-OR). as well as many other Iypes of operations. Data for the ALU are obtained from the register array.
Decoder The instruction dt'Cooer can bc considered as part of the ALl), although we are treating it as a separate function in this uisc ussion lx.'Calise the instructions and the dl..'Cooing of them are key to a microprocessor's operation. The microprocessor accomplishes a J;ivcll task as directeu by prOJ; rams thaI consist of lists of instructions stored in memory. T he instruction decoder takes each binary instruction in the order in which it appears in memory and decodes it. IflfiructiOiI
RegUter A"tly The register army is a collection of registers Ihat arc contained within the microprocessor. During the execution of a program, dllta ilnd me mory addresses me temporarily stored in registers that make up this array. The ALU can itCCCSS the registers very quickl y, making the progl1lffi run more efficiently. Some regis ters are clussl..-o as generalpurpose, meaning they can be used for any purpose dict
MICROPROCESSORS
ters have specifi c capabilities and functions and cannot bc used as ge llenl l -purpo~ registers. Still others arc l:alled program invisible registers. used only by the microprocessor and nOi available to the programmer. Control Unit The conlml uni! is "in charge" of the processing of inslmctions o nce they are decoded. It provides the timing and conlrol signals for getting daul into and out of the microprlXessor and for synchronizing the execution of instructions.
Microprocessor Buses The thn:e buses mentioned earlier are the connections for microprocessors 10 allow data. addrc ..ses. and i n.~truct i ons 10 be moved. i l e AddreJi 8UJ The uddn'S.'i bus is a "onc-way street" over which the microprocl.'SSor sends an address code to a memory or other extemal devicc. The size or width of the address bus is SIX!cified by the num ber of conductivc paths or bits. Early microprocessors had sixtccn address lines that could selecl 65.536 (2 Ib) unique locations in memory. TIle morc bits there are in lhe address, the l1igher tile number of memory locations that can be accessed. TIIC number of audrcss bils htls auvanccd to the point where the Penti um 4 has 36 address bits and can access over 68 G (68,000.000,000) memory locations.
The Data Bus The dahl bus is a ··two-way street"' on which data or instruction code... are tnlOsfcrred into the microprocessor or the resul t of
Microprocessor Programming All microprocessors work with an instruction sct that implements the basic operations. The Pentium, for example, ha.<; hundreds of variations of its instnlction set divided into seven basic groups. Data transtCr Arithmetic and logic Bit manipul at ion Loops and jumps Strinp Subroutines and interrupts Control Each instruction consist), of a group of bits ( Is and Os) that is decoded by Ihe microprocessor before bci n!! executed. These binary code instructions arc called T11<1chine language anu are all that the microprocessor recognizes. The fi rst computers were programmed by actually wri ting instructions in binary code, which was a tedious job anu pronc to crror. This primitive method of programming in binary code ha~ evolved to 11 higher r01111 where coded
•
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INTRO DUCTIO N TO COMPUTERS
instruclions are represemed by English-like words to foon what is known a.~ gml!le. Th is wi ll be discussed further in SCClion 12-4.
as ~embly
lan-
Technological Progress The fi rsl microprocessor. the Intel 4()()4. was introouced in 197 1. Basically, all it could do was add and subtl1lct only 4 bils at a time. In [974. Ihe Intel 8080 became the first microprocessor to be used as the CPU in a computer. The 8080 chip had 6.000 tmnsistors, an 8-bit d,lta bus, llitest microprocessor (it may not be at the time you are read ing this) has about 42,000,000 tran ~ i s tors on the chip and a 64-bit data bus. It runs at dock freque ncies of up to over 3 GHz and it can do approx imate ly 1,700 MIPS. The inSlftlClio n sets have also changed drastically. but the Pentium 4 can execute ,IllY instruction cocle that ra n on the 8086, the 1979 device that came after the 8080. 'file numbcroft ra nsislOl"S available has a lremendous impaci on the performance and the types of things that a microprocessor can do. For c;o;ample, the large num ber of transistors 0 11 a chip ha<; made a technolo!:!y called pipe/iI/ill'; possible. Basica lly, pipelining allows more than one i n.~trllct ion to be in the process of execUliOIl at one ti me. Also, modcm microprocesson; have multiple instruction decoder.;, each with its own pipe line. Thi .~ allows several streams o f instructiolls to be processed simultaneously.
1. What are the four
ba~ic
e lemenb in a microproceuo r?
2 . What are the three types of buses in a 3 . What function
doe~
microproces~or?
a microprocessor perform in" computer?
4 . What are the three basic operation! that a micloproceuor performs? 5 . What is pipelining?
12-3
A SPECIFIC MICROPROCESSOR FAMILY The origimllintel micropnx:t;:ssur family has undergone a Iremcndous Chlll1!lc over the years from the 808618088 to the Pentium fllmily, both in ~1X:ed and in comple;o;ity. However. the ba~i c reg i ~ ter sct and othcr features of the 808618088 have been rctained (and expanded) throughout the evolut ionary pnx:ess so lh:lt all of the IlCwerlnlel processors respond to the same instmctions (liS well as a number of new instructions) as the origin
A SPEC IFIC MICROPROCESSOR FAMI LY
Basic Operation A rnicroprocessor ex(:clItes a program by repeatedly cycling through the follO\ving three steps: I. Felch an instruction from memory and pl ace it in the CPU.
2. Dl:cocle the instruction; if other information is required by the instruction, retch the other infonnation. In the dccode step, the progr'''lTI counter is updated to poillt to the next instruction. 3. Ext.'Cule the instruction (do what the instmction says). Results are relUrncd to registers and memory du ring this step. The architccture of the 8086/8088 microprocessor providcd for two separate internal un its: the execution unit (EU), which executes instructions, and the bus intcrface unit (81 U), which intclfaces with the system buses and fetc hcs instltlClions. reads opcmnds. and writes resu lts. These units are shown in Figure 12-4.
80861808!! MicropTOCesI>or Execution unit
Bus imerface IInit
EV
.,V
• E>;eclllcs instructions
• FClcllCS instructions • Reads op!'mnds • W rilCS resu lts
-
FI G URE 12 - 4
The 8086/8088 has two separate internal unib, the EU and the BtU.
The BTU perform s all the bus opermions for the EU, such as data transfers from memory or 1/0. While the EU is executing instructions, the BIU " looks ahead·' and retches more instructions from memory. This action is called prerctching or pipelinil1g T he concept of prefetching is to al low the processor to ext.'CUle illstructions at the same tillle as the next insU"uction was being fe tched, eliminati ng idle time. The prefetched instructions afe slort:d in an internal high-speed memory calk'd the instrttction tjtl(..'UC (pronounced "Q"). The queue allows the BIU to kee p the EU supplied with instructions. The EU docs not have to wai t for the next instruction to be fetched from memory; but inslt.'ad it retrieves the next instruction directly from the queue in much less time. In the Pentium, this process is taken a step rUllher. Two complete execution units enable two instmclions to execute at the same lime provided they arc independent. Cellai n compi lers arc designed to lake advantage o f the two execution units by a process known as instruction pairing 10 remove de pendencies.
Basic 8086/8088 Architecture Figure 12- 5 is a block diagram of the mchiteclure (internal organization) or an 8088 microprocessor. Extenmlly, the 8088 had 20 address bits [hat could address J MI3 (1 ,048,576 bytes) of memory and used an 8-bit ililta bus. l.ntcrnally, the 8088 had a 16-bit data bus and 11 4-bytc queuc. The 8086 was identical except that it had an ex[emaI 16-bit data bus and a 6-bylc instruction queue.
•
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•
INTR.ODUCTION TO COMPUTER.S
EU
BIU A
bus t20 hi ts)
General regisK'l's
AH BH CH DH
AL BL CL DL
Dala hrn; (Il bits)
cs DS SS
SP BP DI
F1i
IP
SI
Inlema] CQlnnmoiC'ations reG i~t~rs
ALUd;m"j
Tt'mpor.,ry l,.:gisle~
l3 u~
control
"""
-,--'~"'~.-, bus
f-JnstrucllOIl '1uc ue
I ,, ,,
ALU
,,, ,,,
,,
1
Fla~~
1-f-
EU
cunlrol s)'~lCm
Q"''''''''"'
CEEEl
1FIGURE 12 - 5
The intcrnill org
The Bus Interface Unit (BIU) TIle major p;Jrts of the BTU arc the 4~by te inslruclion queue. the segment reg isters (CS. OS, SS , and ES), the instruction poimer (IP), aOO lhe ;Jddrcss summing block (r.). The 16-bit intcmal data buses and the Q bus inlerconncct the BIU and Ihe EU. ltulruction Queue The instruction queue increases the avcr..Ige Sp,,'(.'(1 with which a program is execulcd (called thc throughput) by stori ng up 10 four bytes (six in the 8086). As dCM:ribt!'lI earlier, th is technique allowed thc 8088 essentially til do two things, felCh and executc, at one timc. This feature has been expllnded in subscqucnl proce.~sors to include much larger and faster queues. Segmen t Re1!ftten Thc 808618088 processors had fou r segment registcrs (es. DS, SS , and ES) that were all 16-bit registers used in the pnx:cs.s of forming a 20-bit address. A segment is a M k8 hlock o f memory and l:l\n begin at any point in the I MB (J .048.576 bytes) of memory Slx'lCC, plUvidcd it begi ns Oil a l6--bytc bou ndary (evenly divisible by 16). In dCf>ig ning the 8086/8088
A SPEC IFI C MICROPROCESSOR FAMilY
•
703
pal advantage of the mcthod sclecled was 10 a llow codes to be easily rclocalabic. A rclocatab1c code can be moved anywhere within the memory space withoul changing the basic code. Each of Ihe four segnlCnlS idenlify the starting address of a 64 kB (65,536-byle) block re presenting a "w indow" inlhe entire I MB (20-bit) memory space. TIle starting address of a segme nt is represented by the 16-bit numlx:r in the segment register plus an implied 4 bits appended 10 the righlthat are always assumed to Ix: zero. In other words, the segment registers contain the mosl significant 16 bilo; that represent the physical SLarting add ress of Ihe segmcnt. 11te four segmenl reg isters (CS, OS, SS, and ES) can be changed by Ihe progr.lln 10 po int 10 olher 64 kB bloch if necessary. (For small codes, it is normally nOlnecessary 10 change Ihe segments.) T he four sl.1:menlS can be sepamte locations wi thin the memory space or can overlap. depending on Ihe size and requirements of the particular code. They can even be defined as the same 64 k B block. In the 808618088, currently addressable memory segments were Ihose defined by Ihe scgment address contained in the CS (code segment) register, the OS (data segmcnl) register, Ihe SS (stack ~gll1ent) register, and the ES (exira segment) register. In later processors, other segment registers were added. A!; mentioned, within each segment arc 64 kB of memory. To find a given memory location, a segment address is combi ned with an offset address. The segment address represenls the most sign ificant sixteen bits (four hex dig its) o f the physical address which represcnt the beginning address of a segment. The offsct address is sixteen additional bils that re present the dislance frolllih e start of the segment to the physical address within the segment. Figure 12-6 illustrates how the memory is divided into segments and shows examples of nOllovcri
add..:"
addw.,
FI+FF
FFFFF
~gmen ts
H:OOO
1'0000
memory. Each l.Cgment repreenb
E
64 kB.
DO
EX Ira .'>Cgrncnl
OXXIO
-BrOX)
The dUTa "cgmcm begin,
S<'gmenl 1Idd1l'.\.~ t)(X1O and orr\C1 ,ldd".."" 0CXlJ. ~I
,
AtXJIII
Noooveriappingand overlapping in the tint 1 MB of
DOOOU
OXXIO Slac k I>Cgmenr
""00
Data segmcnt
AOUOU
900no
""'" 70000 Cooc segment
8000U
• 1bc code wgrncrII begill$ ~ aT >cgulcnt ,\dtIJC,\.~ 68(10 nlld tlrr<;c! acldrcSll 0000.
FIGURE 12 _ 6
Plly.<';c'll
'i£llOO
, «-.x.,
EX ira .
50000
,13 segmc
7'10
->0000
sc men
, "xXX)
""'" Nonow rlappillg
(hw lapping
Instruction Poi"ter{lP) ond Address Summing Block 'Ille 16-bi t IP (instruclion pointer) poi nts to the offset of Ihe lIeXI instruClion to be cxecUled in memory. 'Ille IP always refcrCllec.<; the CS (code segment) regisler: thus. the physical address of the next instntctioll is formed by combining the cooe segmcnt and the instruction poi mer. The II> always contains
704
•
INTRODUCTION TO COMPUTERS
the offset address of the next instmction. and the CS register always contai ns the segment address. This address is shown in assembly language as CS:IP. To form the 20-bit physical address of the next in .~ trucljon. the to-bit offsct address in thc IP is added to the segment address contained in the CS regisler. which has been sh ifted four bils to the left , as ind icated in Figure 12- 7. As mentioned earlier, an assumed binary 0000 is the least significOlnt position. The llddi tion is then dune by the address summing block. FIGURE 12 - 1
CS rcgiMCf
rormiltion o f the 20-bit phy!.iCil[
16-bi! >.e OteU! b.t..., ... kln:·
ilcklral from the segmen t Iuose
'000 ____ I,
+
i!ddrC1oI ilnd the ofket ildd.en.
t p (tu'lru.:li"n p",nh:n
!
Figure 12- 8 illustrates the addressing of a location in memory by the segment: offset method. In this fif;ure, A{X)(Jlf. is in the segment registcr and AOBO,~ is in the IP. When the CS register is shifted and added to the Ip, we get AOOOO l6 + AOBO l 6 = AA0130 l h for the physical address. FIGURE 12 - '
r AFI~"
Ul ull:r.ltion of the segmented "ddre ..ing .,.,.,thod.
,
I IoHB
j'.":B", II AOOOI,,,
,
I
-\UWO,
I AI I • I I 0
Physicnl adllrcs'
Bas., addn'SS
~
0
+
I
A J OIO IOlo l
EXAMPLE 12 1
1lle hexadeci mal contents of the CS register lmd the IP are shown in Figure 12- 9. Determine the physical address in memory of the next instruction. FIGURE 12 - 9 A034 16
Solution
Ics
Shining fhe CS rnL're address left four bits (olle hex digit) effeclhdy places a 0 16 in the LSD po~ i tion. a~ shown in Figure 12- 10. The shifted base address and the offset address are added to produce the 20-bit physical address.
A SPECIFIC M ICROPROCESSOR FAMILY
FIGURE 12 - 10
I A0340 1 Ba.o;e address
I O FF 2 I
+
onSet address
332
[)ctcnn]ne the physical add ress if the CS register contains 6B4D ,6. *Answel's are allhe end III' the chapler.
J[ i.~ impol1ant to undcr.~ tand how the scgment:offse t method is used to fonn the physicnl address: however, in programming work, it isn't usually necessary fo r the programmer to spl:{'ify actual physical addresses. This j ob i~ done by the asse mbler program using labels supplied by the programmer. When a physical address is required, the programmer generally sp..-'Cifics it with the segment:offsetmcthod. Thus, the address for Example 12- 1 would be given as si mply A034:QH """2.
The Execution Unit (EU) The EU decodes instJUctions fetched by the 8 1U. generates appropriate control signals. and executes the instructions. The main parts of the EU are the arithmetic log ic ullit (A L U), the gcneml registcrs. and the nags.
The ALU This unit dcx:s a ll the arithmetic and logic operations, worki n£ with either 8-bil or 16-bit operands. The GetU!ral Registen This set of 16-bit regis ters is divided into two sets of four registers each, a.<; shown in Figure 12- 11. O ne set consists of the dClta regislers, and the other sct consists of the pointer and index registers. The pointer and index registers are generally used to keep o ffset addresses (as used here, a pointer refen; to a specific memory location). 1n the case of the stack pointer (S P) und thc base pointer (BP). the default reference to form a physical address is the SUlek segment (SS). The index pointers (Sl and DI) and the base register (BX) generally dcfaullto the data segment (DS) register (an exception is made fllr certain instructions to thi~ general ru le).
I .1 ..
".
AH BH
AL
CH OH
SP
.... The gene"'" reg;Iter let.
"
ACr.:lInllliall)r
BL CL
COlInl
DC
Dal a
Base indl'x
ISlal·~ ~illler
1------.:"=p' --------1"B~sc pollller 1-_____ 0:::-'_ __ _ _ -j Deslin.uioo index
,=,'-____---'ISour~e inde~
L _____
FIGURE 12 - 11
1
nr next in~1rOClinn
(shi fled lefl
Related Problem·
1"
Physical..udfCloS
•
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•
INTRODUCTI O N TO COM PUTERS
Each of the 16-bi t data registers (AX. BX, ex, OX) hm; two separately accessible !:I-bit sections. Depending on the program, they can be usetl either a<; a 16-bit register or a<; twO 8-bit registcrs. The low-order bytes of the data registers are desig nated as AI., BL, CL, and DL The high·order by te~ are designated a<; AH. RH, eH, and DH. T hese registers call be used in most arithmetic und logic opemtions in any manner spt..'Cified by the programmer for storing duta prior to and after processing. Also, some of these registers are used specificaUy by cCI1ain progrnm instructions. The pointer and index registers are the stilck pointer (SP), the base pointer (BP). the destination index (01), and the source index (SI). The.~e registers are used in variolls forms of memory uddrcs.~i ng under cuntrul u f the EU. The F1a81 The nag register contains nine independe nt status and cOlllrol bits (n:tgs), a<; shown in Figure 12- 12. A stalUs n ag is a one-bit indicmor lL<;etl tO refl&:t u certui n condition after an ari thmetic 01" logic opemtion by the ALU, such a~ a carry (CT), a 7..ero result (ZFJ. or the sign of a result (SF). umong others. 111e control flags are used to ulter processor operations in certain situations.
fiGURE 12 _ 12
The ~t.ltus i1nd control nil&".
Control
Slatus
na~
n~.,.
~
1'"'101'11' IOFISI'IZFIAFI PF ICFI
I I
C31l')
P:lrily
Aux .:all') 7....,w ~jgn
(}.erOcm InlClTUpt enable Dir~~I;on
Trdp
Software Model of the Pentium Family of Processors As Intel introduced newer micropnxessors, capabil ities and speed increased dramaticaJly. With the Pe m illm proces~or, the e:lfJj er p ipt' lin f> conCf>pt inlrorltll:I'(I in th e 8086/8088 was increased 10 two-integer pipe lines. The extl:'fIlul coprocesso r was incorporated within the microprocessor, and address and data buses were greatly expanded. Other improvemcnts (such as doc k speed, reduced instruction cloc k cycles, branc h prediction cupabi li ty. and an integml floating· point lInit) Illude the Pentium a significantly better processor than its predecessors. In udditio n to processor improve ments, many improvements to other parts of computers occurred (such as bus pro tocols and size, speed. memory Si7..e, and cost). Despite all of these changes. the designers of the newer processors maintained compati bility with eurliersoft ware; that is. the newest Pentium could still run the soft ware for any or the processors that preceded it. This was done by maintaining the basic soft ware model (register structure) of the original 808618088 m ic rop roce.~sor. The rt.'gistcrs described previously for the 808618088 microprocessor are a sulht!1 of the registers in the Pentium family of processors. Beg inning with the 80386 processur, the regiSler set was expanded to include 32-bit fl.'g isters. 111e 32-bit registers kcpt the original names bot an E (for Extended) was added a.~ a prefi x to the register namcs; th us, the 32-bit designation for the AX register is the EAX. In addi tion, IwO new segment registers were added. The extended registers are shown in Figure 12- 13. The gmy areus repre.~e nt the reg.isters only uvai luble on the 386 and ubow. In addition 10 the extended fl.'g isters, the addressuble space in memory was increased dramatica lly with the introductinn of newer proces.~ors . To keep the upward compatibilit y. Intel reservetl the fi rst 1 MB of memoI)! for codes running ill real moUe. Re:tI mode is any
COMPUTER PROGRAMMING
Name
12- bit names
AH AL BH B BL ell ex CL OH I X DL
EAX
Accumulator
"
EllX EO< EDX
51'
BI'
Ba.o.: poin":r
01
I)o.:stination index
EDl
Stack poinltr
Source index
SI
ESI
-I
12 bits
I'
Regilten for the Intel proc;euon from 8086/8088 through Pentium.
D~l a
ESP
t--- 16 bits --.t Ell' EAag~
I
Gmy ar~as are roc SOJ86i111d abo
'"
CS
Cod<
os
"'"
ES
SS fS GS
EXira
Stock
operation Ihal allows Ihe processor to only access the tirst I MB of memory to simulate the 808618088. Code wrinen for an earlier processor cIIn run in rCOlI mode on a newcr proccssor (althollgh the reverse is not str ictly lrue). Code written in real mode is generally coo1pHlible (with some exceptions) with n.ll of the Intel prnce",sors from the ROR6J8ORR lIpwOlrd .
I
SECTION 12-3 REVIEW
1. Name the general-purpose registers in the Intel microprocessor.
2. What is the purpose of the BIU?
3. Does the EU interfa<:e with the system buses? 4. What is the function of the imtructioo queue? 5. What is the advantage of the segment:offset method of forming addresses? 6. What is instruction pairing?
12-4
COMPUTER PROGRAMMING
Assembly langllage is a way 10 express machine IIlnguIlgc in Engl ish-like terms, so there is II one-tQ-()ne corresponclem;e. A~~e m bly language has limited applications and i .~ not port;lhle from one pnx..:essor to another, so most computer programs are written in highlevel languages such as C. C+ + . JAVA, BASIC, COBOL, and FORTRAN. High-level languages are por1able anJ therefore can be used in diffe rent computers . High-level languages must be convened to the machine language for a specific microprocessor by a process called compiling. After complet ing this scaion, you sholiid be able to • Describe some progmmming l:Ollcepts • Discuss the levels of prognunrning languages
707
FIGURE 12 - 1]
Count
EBI'
•
708
•
INTRODUCTION TO COM PUTERS
levels of Programming languages A hierarc hy diagram of computer programming languuges relative 10 the computer hardware is shown in Figure 12- 14. AI the lowest level is the computer hard ware (CPU, memory, di sk drive, input/o utput) . Next is the machine language that the hunlware understands because it is written with I s and Os (remember, a logic gate can recognize only a LOW (0) or a HIG H ( I ). At the level above machine language is assembly language where the Is and Os are represented by English-like words. Assembly languages are considered low-level because they are closely related 10 machine language a nd are mach ine dependent. which means a given usrembly hmguuge cun only be used o n a specific microprocesso r. FIGURE 12 - t4 H i~ rchy of programming languages relative to computer h.ardware.
f1i g h . I~ \'(oi
tanguage
• Closer 10 human 1~~lIIIgc • Portabk
,\ ss~llIbty l:mgmlge • English-li ke terms 1L'Pre.'>Cnling hi nary code:• Mnc hiOt: dependent
Machine langu~ • Uin.ll)' code Its and Osl
• Mxh ine d~p"ndcnt
CumptliU hanhnlre \the - mllchi ne",
-CPU • Memor,. (RA M. ROM l • Di~1; drives • InpurJOutput
At the level above a"sembly language is high-Ievellallguage, which is closer to human language and further from machine language. An udvmlluge of high-level language over assembly languugc is that it is portable, which means that a progmm cun ru n on a variety of computers. Also, high-level language is easier to read. write. und m
Assembly language To avoid having to write out long strings of Is
COMPU T ER PROGRAMMING
•
709
croprocessor on another type of microprocessor. For example. an a . sembi), language is often used in a subroutine (a small progrmn within a larger program) (hal can be called from a high-level language prOCJram. Assembly language is useful in subroutine applications bet:ause it usually runs fas ter and has none of the restrictions o f a highlevel language. Assembly language is also used in machine control, such as for industrial processes. Another area for assembly language is in video game programmi ng.
Conversion of a Program to Machine language All progmms written in either an assembly language or a high-level language must be converted illlo machine language in order for a particular computer to recognize the program instructions. AlSemblers An assemblermmslates and converts a progmm written in assembly language inlo machine code. as inc.licatec.l in Figure 12- 15. The tenn source program is often used to refer to a program written in either a"sembly or high-level language. The tenn objecl program refers to a machine language translation of a source progntm. FIGURE 12 - 15 A~bty
language Jlf08..l1n (Source program)
-
Machille lanj'!ullgt: p''OS''Ull
Assembly to machine convcnion u.iog.ao .a.semble<".
IObjecll'ffillmm)
Compilers A cumpiler is a progmm thai compiles or translates a prognlln written in a high-level language and converts it into machine code. a" shown in Figure 12- 16. The compiler examines the entire SOurce program and co ll ect.~ and reoT'Janizes the instructions. Every high-level language comes with a specific compi ler for a specific computer, maki ng the high-level language inc.lepenc.lent of the computer on which it is used. Some high-level languages are translated using what is called an interpreler that tralls l ate~ each line of program code to mllchine language.
FIGURE 12- 16
High-level languuge
progrom
(Source progrumJ
_
Compiler
Machine langull~e pft)i,1ram
(Objecl program)
All high-level langlt:lges. such as C, C + + , FORTRAN, and COBOL, wi ll run on any computer. A given high- level language is valid for any computer. but the compiler that goes with it is speci fi c to a particular type of CPU. Thi ... is illustmted in Figure 12- 17. where the same high-level lang uage program (written in C + + in this ca"e) is (."(Jnverted by di ffe rent machine-speci fi c compi lers. &le of an Assembly LAnguage Program For a simple assembly language program, let's say that we want the complLter to add a list of numbers from the men"MJry and place the
High-level to m.achine conversion with a compiler.
7 10
•
INTR.ODUCTI ON TO COMPUTERS
FIGURE 12 - 17
Ma(hine independen(e of ~ pmgr.:lm \\Ifitten in a high- level language.
j
j Compiler Computer I with CPU A
I Compit~r
Compiler Computer 2 wi th
Computer J with CPUC
CPL' B
!
! Computer I
Computer 2
Compukr J
Object program
ObjL'C t progmrn (lnJchine code)
ObjeL1 progrnrn (nwchitle code)
(machine code)
sum of the numbers back illlo the memory. A zero is used as the last number in the list to indicale the cnd of thc list of numbers. The Sleps required to accomplish thi!; task arc as follows: 1. Clear a rel;!iSler (in the microprocessor) for the total or sum of the numbers. 2. Point to the fifSl number in Ihe memory (RAM). 3. Check to see if the number is uro. If it is zero, a\1 the numbers have been added. 4. If the number is nOl l..ero. add Ihe number in Ihe memory to the lotal in the regisler. S. Point to Ihe next number in the memory. 6. Repeal steps 3, 4, and 5. A fiowchart is often used to diagmm the sequence of steps in a computer progmm. Figure 12- 18 shows the fiowchart for the program represented by the six steps [isled above. T he a...sembly language progmm implements the addilion problem shown in the fiowchart in Figure 12- 18. Two o f the registers in the microprocessor are named ax and bx. The comments preceded by it semicolon arc nOt J"eC()gnized by the microprocessor: they
°
; Rep l~ces
~he
conLents o( the a x register with zero .
;Ite<;ister a x will store the total o f the
ncx ~ :
~ddition .
may bX,SOH
; Places memory address hexadecimal 50 into the bx regis ter .
cnp wore ptr [bx] , O
, ConP
jz done
;If the number in the menory location is zero , jump to
add a x. [bx1
: Add the nwrber in the memory location poi.ntee to by the bx regis t er to ; the number in the a x register and place the sum into the ax register .
add bX,02
;2 i s added to the add r ess in t he bx register . Two addresses are ; required to store each nunber which is two bytes long .
jmp nex t
: Loop back t o
done , moy [bx l ,ax nop
~next"
~done ".
and repeat the process .
; Rep lace the zero l asl n~~r in the memory loca~ion pointed to by the ; bx regis t e r with rhe total in the ax register . ; No operation,
~ h is
indicates the end of the p r ogram .
COMPUTER PROGRAMM I NG
.. FIGURE 12-18
Aa.\IChart fOf' ildding a lilt of numbe~.
Initialize lotal 101.ero.
Poinl 10
firl'l
number.
Is number >-"yoe''---_---, : ;tem?
No Add number 10 Iota!.
PoinllO neX I
numb..'f.
Depending on the a<;sembler. most programs in as~ mb l y language will have a number of assembler direclives thaI are used by lhe assembler fo do a variety of ta~ks. These tasks include setting up segments. using the appropriate instnlction set. deseribing uatasizes. and perrorming many other "housekeeping" functions . To simplify theexplanatioll, only one din.:.:clive (required) was shown in the preceding program. The directive was word ptr, which is used to indicate the size of the uata poi med 10 by the BX register.
The Debug Assembler Wilh a few small change!!., you can run the preceding progmm, if you choose. by using a built-in assembler. present in DOS-based pes. You will be able 10 observe il execule slep by step. All DOS-based PCs have a progmm called Debl/g that inclucles a primitive as~ m bier. To usc Debug. go into DOS and type Dcbug at Ihe DOS prompl. «CD stands for "ciUTiage return." which means In press Ihe [ ENTER 1key.) You shou ld see a minus sign. which is the Debug prompt. Debug ha<; a number of commands 10 obsen'e or enter data or programs. The compJele list of Debug commands will be shown if you type ? at the Debug prompt. Before writ ing and executi ng an assembly program, you can enter some dala by ty ping the informmion shown in red:
- a 50 This tells Debug to start assembJin!l instructions at the current daw segment aI an offset of 501-1. Although these are data that are being entered. it is simpler to enter a 16-bil word this way. (Keep in mind lilat all data in Debug is entered in HEX .) Debug responds with a segment address, which will undoubtedly be different than thai shown (2008), but
•
711
71 2
•
INTRO DUCTIO N TO CO MPUTERS
it does n' t matter. The offset address (SOH) will be the same. Type the information shown in red (re member each means press the [ ENTER I key).
2008 : 00 50 2008 : 0052 2008 : 00 54 2 008 : 00 56 20D8 : 00 58
dw dw d....· dw dw
30 15 aO Dc 00
.cr>
The dw is an
-a 2008 ; 0100 2008 : 0103 2008 : 01 06 2008 : 0109 2008 : 0108 2008 : 0100 20D8 : 011 0 2 008 : 0112 2008 ; 01l4 2 008 : 0115
mav ax . n mov hX , 50 crp word [bx) , O <;.cr .. .C> i add ax , [bxl j, l06 rna\' [bxJ . ax <<::1'.,.
nap
To confirm that the program ha.. been entered correctly. yOll can type u 100 114 at the Debug prompt, and the code you typed wi ll be shown on the screen. (It will be shown in capitalleuers). Now type r after the Debug prompt. and a list of the l 6-bit registers and <.:011 ditlon of the nags will appear. Notice Ihal lhe IP shuuld have 100, the starting address o f the code. Underneath the list of registers, the first instruction (MOV AX, 00(0) will be shown. You t.:an t.:ause Debug to execUie this instruction with the t (trace) command. This will bring onto the screen the latest condition of all of the registers and show the next instruction (MOV BX, 0050). Executing this with a t command will show that the num ber 0050 h a~ been moved into the BX register. The steps up to this point an: shown in Figure 12- 19. Notice that the first data point is shown in the lower right. Continuing in this way. you can execute the entire code and observe the changes to the registers mi the microproce:.sor follows the instructions, as shown in Figure 12-20. This progmm hus a common progmmmi ng str ucture called a 1nol', A loop is a repetitive group of instruc tions that arc executed until some condition is met; in this case, the condition is fi nding a zero in the data. After the zero has been found, the last instruction will be executed and the sum will be stored (in this case, OOFI is the hex sum) in place o f the zero that indicated the last data point. You cun ob...erve this by pressing d 0050 OOSF (display between add rc.~ses0050 and oo5F) at the Debug prompt when you reach the la<;t instruction (NaP), as shown in Figure 12-20. T he result appears as the 9th and 10th bytes (the 5th word) on the line following the display instruct ion. Notice that the least significant part of the answer is shown first. When executed in "real time" by the microprocessor, this program actually use.~ only ubout I J1S to do this entire process. If you choose to repeat the process, you wi ll need to reload the zero at lOCation 0058 be<:ause it has been replat.-ed with the sum. (Recall thut the program uses the zero as a "last data poi nt" sensor.)
COMPUTER PROGRAMM ING
•
-u 100 114 2008:0 100 2008:0 103 2008:0106 2008:0109 2008:010B 2008:0100 2008:0110 2008:0112 2008:01 14
MOV MOV CMP JZ
B80000 B85000 833FOO 7407 0307 83C302 EBF4 8907 90
AGO AOD
JMP MOV NDP
IV:,OOOO BX,0050 WORD PTR ( BX ] , +OO 01 12 AX, ( BX\ BX,+02 0106 [BX ) ,AX
-r AX =OOOO BX=OOOO 05=200B E5=200B 2008:0100 B8000 -t
CX=OOOO OX=OOOO 5P=FFEE 55=2008 C5=2008 IP=0100 MOV AX,OOOO
BP=OOOO 51 =0000 01=0000 NV UP EI Pl ZR NA PE NC
AX=OOOO 8X=0000 05=2008 E5=200B 200B:Ol03 B85000 -t
CX=oooo OX=OOOO 5P=FFEE C5"'2008 IP"'0103 55=2008 MOV BX,0050
BP=OOOO 51=0000 01 =0000 NV UP EI Pl ZR NA PE NC
AX =OOOO 8X=0050 05=2008 E5=200B 2008:0106 B33FOO
CX=oooo OX=OOOO 5P=FFEE BP=OOOO 51 =0000 01 "'0000 55=2008 C5=200B IP=0106 NV UP EI Pl ZR NA PE NC 05:0050:0030 CMP ~\IORO PTR [BX],+OO
FIGURE 12 - 19
Step. in beginning to ~xecut~
th~
addition progrilm with Debug.
NV UP EI Pl NZ NA PO NC
05=2008 E5=2008 2008:0110 EBF4 -t
55=2008 C5"'2008 1P=0110 JMP 0106
AX =OOFI 8X=005B 05=2008 E5=2008 2008:0106 833FOO -t
CX=OOOO OX=OOOO 5P=FFEE BP=OOOO 51 "'0000 0 1::0000 55=2008 C5=200B IP=0106 NV UP EI Pl NZ NA PO NC CMP WORO PTR IBX] ,+00 05:0058=0000
AX=OOFI BX=0058 o5=200B E5=20oB 2008:0109 7407 -t
CX=OOOO OX=OOOO 5P=FFEE 55"'2008 C5=200B IP=0109 JZ 0 11 2
BP=OOOO 51=0000 01 =0000 NV UP EI Pl ZR NA PE NC
AX=OOFI BX=OOSB OS: 2onR Es=?nnS 2008:01 12 8907
CX=OOOO OX"'OOOO 5P=FFEE ss=?ons CS=200R TP=0112 MOV ( BX),AX
BP=OOOO 51 =0000 01 =0000 NV lIP ET PL 7R NA PE NC 05:005B=0000
-t AX=OOF I BX=OOSB CX=OOOO OX=OOOO 5P= FFEE BP=OOOO 51 =0000 01 =0000 05=2008 E5=2008 55=2008 C5=2008 IP=0 11 4 NV UP EI Pl ZR NA PE NC 2008:0114 90 NOP --d 0050 005f 200B:0050 30 00 15 00 AO 00 OC OO - Fl 00 00 00 00 20 20 20 0 . .......... . Sum
FIGURE 12 - 20
Lut portion of tracing the addition program, Th~ sum OOF! is.OOwn in blue ""th the low part (Ft) given first
713
71'1
•
INTRO DUCTION TO COMPUTERS
I
EXAMPLE 12-2 Wrile the instructio ns for an a ..sembl y language program that will find the largest unsig ned number in the dala and place il in the last positio n. Assume Ihe la~t dala point is s ignaled with a zero.
Solution
The fl owchm1 is shown in Fig ure 12- 2 1. FIGURE 12-2 1
Flowchart. The variable BIG reple\entl the lalgest ""Ivc.
tnilial izc mG to zero.
Point to firsl
nu mber.
Is number
> BIG ! Rcpl",.."e BIG with nu mber.
No
Point to
next num ber.
Last
n" mlll...,.?
>-"
·O~,·_ _ _,
No
The data is a~umed to be the same as before. The progmm listing (w ith comme nt.<.) is as foll ows: ~v
ax , 0000
~v
1»: , 0050
r epeat : emp [bx J , ax jbc check ~v a x , lbx] check : add bX, Q2 crop word p tr [bxl. Q jnz repeat moY [bx] , a x nap
initial value of BIG is i n the ax register point to a location in memory (SOH) where the data ~tarts is the data point larger than BIG? if the data point is smaller , go to ~chec k ~ otherwise , put new largest d~La point in ax point to the next number in memory (two byLes per wo r d) t e st for last data point con tinue i f t he data poin t is not a zero save BIG in memory no operation
The Debug listing ofthi.<. prog ram is shown in Fig ure 12- 22. Data a re ente red in [he same way a~ before Slim ing allocatio n 0050. In this case the same data are used, but you may ch~ new data if you prefer. It is imponant (hat a zero be e nteretl a~ the last data
COMP U TER PROG RAMM I NG
•
7 15
poinl because the program continues until it finds this point. The zero is replaced each time the prognun is run with the laf1!est data point. The program is entered by slarti ng the assembly at location 100 by entering the program after the a 100 command is issued. FIGURE 12 - 22
Ulting of Debug portion of progr~m.
-, 100 2008 : 0100 2008:0 103 2008:0 106 2008:0108 2008:0 10A 2008:010C 2008:010F 2008:0 11 2 2008:01 14 2008:0 11 6 2008:0117
00' ax,O
mo, bx,50 emp [bxJ ,ax j be l ac
".
mav [ bx ] add bX,2 emp word ptr l bx ] ,0 j nz 106 mo, [ bx] , ax
"OP
The program can be traced to watch the execut ion. one step at a time. Alternath'ely. you can enter g = 100 116 to "go" between address 100 and 11 6. Figure 12- 23 shows the data before and after execution. Note thai each data point is stored in IWO bytes (although the data is only one byte long) bec:lUse the datu was defined as words. Also, note that the low byte preceded the high byte in memory. After the program is run. the last data point (fomlerly zero) is seen to be equal to the largest value (AO in this example). This value is seen to be in both the AX register and in memof)'.
-a 100
2008:0 100 mov ax , O 2008:0 103 mov bX,50 2008:0106 cmp (bx ), ax 20D8 : 0108 jbe 10c 2008:010A mav ax, ( bxj 2008:010C add bx,2 2008:010F cmp word ptr [ bx] , 0 2008:01 12 jnz 106 2008:0114 mav [ bx ], ax 2008 : 01 16 nop 2008: 01 17 fuI of d3la sil;!lIw -d 50 5f ,----.., 2008:0050 30 00 1500 AD 00 DC 00 -00 00 00 00 00 20 20 20 -g"'" 1 00 tt 6 '-~-=----:--:--~----'
0 .. . ........ .
Dala before enculinl; p!"OI!r.lITI
ex=oooo OX=OOOO 5P=t fEE BP=OOOO 5 1=0000 01 =0000 t:lX=0058 05=2008 E5=2008 55=2008 C5=2008 IP=0116 NV UP EI PL ZR NA PE NC NOP 2008:0 11 6 90 -d 50 5f 30 00 15 00 AD 00 DC ~O - AD 00 00 00 00 20 20 20 0 ... . . ...... . 2008 :0050 AX =OOAO
'~-~~''--y---'
I
D:u~ I\I"C. ulIl,:hw1~d.
End uf duI3 now has
l:lJtcst dina point.
FIGURE 12-23
Data before ~nd after ~ run.
Related Problem
Explain how you could change Ihc fl owchart to find the smallest number in the list inslead of the largest.
716
•
INTRODUCTION TO COMPUTERS
Types of Insuuctions TIle progmll1s in this section only show a few of the huudreds o f variations of inSLfUctiulls available to programmers. To simplify learning the Intel instructio ll set. instructions are di"ided into seven categories. These categories are descri bed here. The most basic data transfer instruction MOV wus introduced in the example programs. The MOV instruction. for example. can be used in M!\"eml ways to copy a byte, a word ( 16 bits), or a double word (32 bits) between various sources and destinations such as registers. memory. and 110 ports. (A better mnemon ic for MOV might have been "COPY" becauI>e this is what the instruction actually does.) Other data transfer in.~tructions include IN (get data from a port). OUT (send da ta to a port), PUSH (copy data onto the slack. a separate area of memory), pop (copy d'lIa from the stack), and XCHG (exchange). Data Trarufer
An"thmetic There are a number of instruct ions and variations of these instructions for addil io n, subtraction. multiplication. and division. The ADD in.~truction wa" u...cd in both example programs. Other arithmetic instructions include INC (increlnelll). DEC (decrement). CM Il (compare), SU B (subtnlct), MUL (multiply), and DlV (divide). Varialions of these instructions allow for carry operations and for signed or unsigned arithmetic. These instructions allow for specificatio n of opemnds located in memory. registers, and VO pollS. Bit Manipulation This group of instructions includes those used for three classes of operations: logical (Booleun) operations. shifts. and rotations. The logical instructions are Nar, AND, OR. XOR, and TEST. An exam ple of a shift instruction is SAR (shift arithmetic right). An example of a rotate instruction is ROL (rotate left) . When bits are shifted out of an operand, they are lost: but when bits are rotaled out of an operand. they are looped back into the other end. These logical. shift. and rotate instructions can operate all bytes or words in registers or memory. Loops and Jumps These instructions are designed to alter the normal (onc after the other) sequence of instructions. Most of these instmctions test the processor's flags 10 determine which instruction should be processed next. In Example 12- 2. the instructiolls JBE and JNZ were used to alter the path. Other instructions in this group include JMI' (unconditional jump), JA Dump abovc), JO Dump overflow), LOOI' (decrement the CX register and repeat if not zero) and many others.
A string is a contiguous (one after the other) sequence of bytes or words. Strings are common in computer programs. A simple example is a sentence that the prugrammer wishes to display on the screen. There are fi \'e basic string instructions that are designed to copy, load. store, compare, or scan a string---cither as a byte at a time or a word at a time. Examples of string insulJctions are MOVSB tcopy a string. one byte at a time) and MOVSW (copy a slring, one word at a time).
Stn"ngs
Subroutine and Interrupts A subroutine is a mini program that can be used repeatedly but progntlllmed only once. r or example, if a programmer needs to cOllvert ASCU llumbers from a keyboard to a BCD format, a simple programmi ng structure is to make the req uired instructions a separate process and "call" the prOCeSS whenever necessary. Instructions in this group inc1 udeCALL (begi n the subroutine) and RET (return to Ihe mai n program). Processor Control This is a SIl1
COMPUTER PROGRAMMING
High-Level Programming Thc basic StcpS to take whcn you write a high-Icvel computcr progmm. rcgardlcI>s of the particu lar programming language that you usc. arc as follows:
1. Delennine and specify the problem Ihal is to be solved or task that is to be donc . 2. Create an algorithm: that is. develop a series of steps to accomp lish thc lask. 3. Express thc steps using a particu lar progmmming language and enter them onlhe software text editor. 4. Compilc (or asscmblc) and rull the program. I\. simple program will show an example of high-IC\d programming. 'Ibe following C + + program implcmclIlS the same addition problcm defincd by the flowchart ill r:igurc 12- 18 and imp1cme llled using assembly language.
im: 1:0l:al = 0;
//Initialize che LOLal LO O .
while ( ' number
OXOO)
IILoop while the value is not Cound . The
flasl:eriGk pre ceding the pointer identifier
Iinumber says that the contents of the limemory location pointed to
by
the
II identifier number are being evaluated .
total = total
+ "number ;
tlumbecl +;
IIAccumulative summation of total . IIIncrement pointer
1:0
next number in memor y.
This C + + program is cquivalcllt to the al>scmbly program that adds a series of numbers and produces a total valuc. i n tOLal = 0 ;
=v
0' .
while ['number! '" OXOO)
~v
b>< . SO"
next : total = total I· ' number ; number l + ;
0
=t> wo ... d pte [bx] , 0
jz done
....
odd ax,
Equ i\';lJent
odd
b,.
,b><, 02
jmp next C i I·
done :
~v
[bxl. ao
000
Assef:lbly
•
717
718
•
IN TRODU CTION TO COMPUTERS
I
SECTION 12- 4 REVIEW
1. Define program.
-,
2. What i} an op-code?
3. What i1 a wing?
1 2-5
INTERRUPTS In this sectiou, the establishment of communications hetween a peripheral and the CPU is presented. Three methods are discussed: polled 1/0 . interm pl-drivcn IlO. and sort ware imelTUpls. Ah er completing this section, you should be able 10 • Discuss the need lo r intenupts in a computer system . Describe the basic concept of a polled 110 • Describe the ba...ic concept of an inlelTUpt-driven I/O • Discuss a software interrupt
In microp rocessor·based syslems such as the personal computer. peripheral devices require periodic service from the CPU. The term service generally means sending da\
Polled I/O One method of sen.'icing the peripherals is called polling. III this method, the C PU must test each peripheral device in sequence at certai n intervals to see if it necds or is ready for servicing. !-igure 12- 24 illustrates the basic polled I/O method. The CPU .~equ e ntia lly selects each peripheral device via the multiplexerlo see ifit need... service by checking Ihe state of iL~ ready line. Cen ain peripherals may need service at irregular and unpredictable intervals, lhal is. more rrequently o n some occasions than on others. Nevertheless, the C PU must poll the device at the highest rate. For example. let's say thai a cen ain perip heml occasionally needs service every 1000 p'S but most of the time requires service only once eve!)' 100 IllS. As you can see, preciolls processing time is wasted if the CPU polls the device. as it must, at its max imum rate levery 1000 p.S) because most of the time the device will nOl need service when it is polled. Each time the CPU polls a device, it must stop the progrdm that it is cUlTcntly processing. go through the polling sequence, provide service if necded. and then return to the point where it left off in it'> current program. Another problem with the sequentially polled 110 approach is that if two or more devices need service at lhc same time. the first one polled will be serviced first; the other dcvices will have to wait although they may need servicing much more urgently than the first device polled. As you can see, polli ng is sui table on ly for devices that can be ser-
INTERRUPTS
CPU
•
719
Addre., bib
Dala bus
Conlrol
JJ
•
I
RAil'!
JJ
J ROM
JJ
JJ
JJ
110 pon I
1/0 pon
110 po'"
110 pu n
2
J
"
Peri phcral
Peripherdl
Periphc ral
Peripheral
I
2
J
"
READY
READY
READY
READY
Multiplexer Select
1 1
FIGURE 12-24
The basic polled I/O t:onfrgurat ion.
viced at regu lar and prediclable intervals and only in situations in which there are no priority considerat ions.
Interrupt-Ddven 1/0 This approach ovcrcomes the disadvantages of the polling melhod. In Ihe lutelnlpt-dri ven method, the CPU responds to a need for service o nly when service is rC(jucstL"£I by a peripheral device. Thus, Ihe C PU can concentrate on 1111111ing the current program without having to break away unnecessarily to sec if a device needs service. When Ule CPU receives an 110 interrupt signal, it temporarily stops its current program. acknowledges the intelTIlpl. and fetches a special program (service ro uline) from memory for the pm1icular device that h a~ issued the intemJpt. When the service routine is complete. the CPU returns to where il left off. A device called a progra mmable imerrupt controller (PIC) h;mdles the intelTIlpts on a priority basis. h accepts service request" from Ihe peripherals. If two or more devices request service al the same time, the one assigned the highest priority is serviccd fi rst. then the olle with the next highesl priority. and so on. After issuing an interrupt tlNTR ) signal to the CPU, the PIC provides the CPU with informationlhat "points" the CPU to the beginning memory address of the appropriate service routine. This process is calJed veclO";lIg. Figure 12- 25 shows a basic illlerru pt-dri vcnllO configurlltion.
Software Interrupts Another type of interru pt is called a software illtcn·upt. Soft ware inlerrupts are program instructio ns Ihal can invoke the same service routines described prev io u ~ l y. The differe nce
7Z0
•
INTRODUCTION TO COMPUTERS
CPU
Address bus
l~rA · 'NTR
~
JJ PIC
RAM
[nlcrrupl
ROM
JJ
JJ
JJ
J
,
110 pon 1
110 porI
I
Periphcml
Periphcml
I
2
I'eriphe ral l
I/O pon
JJ 1I0pon
"
Peripheral
"
r~quesll inc~
, I/Ifl' - -A - Interrupt acknowletlgc
- - - - - - - - - - - - - - - ----' FIGURE 12-25
A basic interrupt-driven I/O configuration.
is they are invoked fro m software witler Ihan from exlernal hardware . When invoketl, the interrupi service routine executes exactly as if a hardware interrupt had occurred. The firsl five interrupts are dcfined by Intel. Others are defined by the BIOS and by DOS to perform many orlhe I/O opcrJ.tions, such as reading and writi ng data to the di sk, writing data to the display. and reading data from the keybomd.
1. How does an interrupt-driven I/O differ from a polled I/O? 2. What is the main advantage of an interrupt-driven I/O? 3. What ii a ioftware interrupt?
12-6
DIRECT MEMORY ACCE55 (DMA) [n this short section. the technique of data transle r called direct memory access (DMA) is defined. A comparison of a CPU-handled transfer and a DMA transfer is presented. After completing thi s section, you should be able to • Define the term DMA • Compare a memory 110 data transfer handled by the CPU to a DMA transfer
DIRECT MEMORY ACCESS (DMA)
All (/0 data transfers discussed so far have passed through the CPU. For eKumple. when data are to be transferred from RAM to a peripheral device. the CPU reads the fi rst data byte from the memory and loads it into an internal register withi n the microprocessor. The n the C PU writes the data byte to the appropriate 110 porI. Thi s read/write operation is repeated fo r each byte in the group of data 10 be transferred. Figu re 12- 26 illustra tes this process.
CPU
RAM
'''' pon
FIGURE 12-26
A memory ItO
tr~mfer
handled by the CPU.
For large blocks of data, intemlCdiate SlOpS by the microprocessor consume a lot of time. Forthis reason. many systems use a tcchniquecalled DJ\.1A (direct memory acces.q to speed up data trdllsfers between RAM and certain peripheral devices. Basically, OMA bypasses the CPU for cel1ain types of d:lta transfe rs. thus eliminating the li me consumed by the normal fetch and execute cycles required for each read or write operation. For direct memory transfers. a device called the DMA controller takes control of the system bu ses and allows data 10 flow directly between RAM and the peripheral device, as indicated in Figure 12- 27. Transfen; between the disk drive and RAM are particularl y suited for DMA becau ~ of the large amounts of data involved and the serial nature of the trall~ fers. The DMA controller can handle data lran ~ fe rs several times faste r than the CPU.
CPU
...............................
••
•• •
FIGURE
12 ~ 27
••• •• ••
J1EJ1R
RAM
~,
1011 '
DMA
oon trollt:1
110 "",
•
721
722
•
INTRODUCTI ON TO COMPUTERS
I~ECTION
12 6
1. What d~ DMA stand for?
REVIEW
12-7
2. Discuss the advi!nt
INTERNAL INTERFACING As you have seen. all the components in a computer are interconnected by buses, which serve as communication paths. Physically, a bus if> a f>el of conductive paths that serves to interconnecllwo or more fu nctional componentS of a system or se\'eral divcrse systcms. Electrically, a bus is a collection of specified \'oltage le\'CIs an(Vor current levels and si2nais that allow the various devices connected to the bus to work properly together. After completing thi s section, you shou ld be able to •
D i ~u s:-.
rhe concept of a multiplexed bus • Explain the
rea~)J1
for tristate OUlplllS
Basic Multiplexed Buses In computers the microprocessor controls and communicates with the memories and the input/output (I/O) devices via the in/enrol blls .f/rue/IIIT!, as indicated in Figure 12-28. A bus is mu hiplexed so that (Uly o r the devices connected to it cun either send or receive data 10 or from one of the other devi(.-es. A sending device is often called a soura. and a receiving device is often called an acceptor. At any gil'en ti me, there is only one source active. For example. the RAM may be sending data \0 the input/output (VO ) interface under control of the microproc-essor.
M icroproces.wr
RAM
ROM
liD Interface
Bus
FIGURE 12 -28
The interconnection of microprocelSo r-based system component! by a bidirectional, m""tiplexed 001.
Bus Signals With synchronous bus control. the microprocessor usually ori2inates all cont rol alld timing signals. 'me other devices then synchronize their opemtiol1s to those control and timing signals. Wi th asynchronous bus control, the conlfol and timing signals are generated jointly by a source and an acceptnr. The process of jointly establishing communication is called handshaking. A simple example of a handshaking SC(juence is given in Figure 12- 29. An important control fUllction is called bus urhitration. Arbitration prevents two sources from trying to use the bus at the same time.
INTERNAL INTERFACING
•
FIGURE 12 - 29
CD Source
0
Pre!""" lu rn;, i\ c I{~ad}
10 l'ecci,'c
1).11 ~ rc~'l y
Daiaocn'P wtl
0
An example of a himdmaking seq uence.
A~ceptOf
0
Connecting Devices to a Bus Tristate buffers are normally used to inlcrface the outputs of a source device 10 a bus. Usually more than one source is connected to a bus, but only o ne can have access at any given time . AlI lhe other sources must be disconnected f.rom the bus to prevent bus contention. Tri state circuits are uscd 10 connect a source to a bus or di sconnect il from a bus, as illustrated in Figure 12- 30(a) for the case ofl w o sources. The select input is llS(''(\ to connect
fiGURE 12- 30
Tristate buffer interface t o a bUI. s~
Soo=
A
A
.. .
. -
,,.,
,
lines
Source
--
. _.
.
- --
/ .
--
S SeIe..;1
'oj
(bj
723
721
•
INTRODU CTION TO COMPUTERS
either source i\ or source B but not both at the ~me time to thc bus. When the select input is LOW, sourcc A is connected and source B is disconnected . When the select input is HIGH, souree 13 i~ connected and source A is dil>CoI1l1cded. A switch e(llI ivalcm of this action is shown in pmt (b) o f the fi gUre. When the enable input of a tri ~tale circuit is not active, the device is in a high-impedance (high-ZJ state and aCls like an open switch. ManydigilallCs provide internal (rislate buffers for the output lines. A tristate output is indica ted by a V' symbol as shown in Figure 12- 31. FIGURE 12-31
v
Method of indicating tristate outputs on an Ie device.
0"
v v
0,
V
0,
v v v
0, 0, 0. 0,
0,
v
Tristate Buffer Opemtion rigure 12-32(a) shows the logic symbol for a noninverting tristale buffer with an active-HIGH enable. Part (bJ oflhe fi gure shows one with an activeLOW enable. FIGURE 12 - 32
Input
Trilute buffer symbols.
Fnat>'c
---f'>5
o..nptn
(iI) Acti ve· HIGH ~nable
E:: : i?{bj
ACliv~·LOW
o.,p",
cr:ab!c
TIle basic opemtion or a tristate buffer can be understood in terms of switching action as illustntlcd in Figllre 12-13 . Whell the enable input is uctive, the gate operu(cs as a normal nonin\'erting circu it. That is. the output is HIGH when the input is HIGH and LOW when the input is LOW, as shuwn in paJ1S (a) and (b) respectively. The HIGH and LOW levels rcprcM;lll lwu ur tllC ~UJ lcs. Till: bun-cr upcr
H'GH i?- "'e"
LO~ i?- LOW
HIGH
HIGH
(,'
(b,
LOW or HI(; H
~ D',,-"On'lL'·lo:d
5
Ih ilo'h-ZI
LOW
,,'
FIGURE 12 - 33
Triltilte buffer operation.
Many microprocessors, memories. and other integrated circuit functi ons have tristate bufrers thai serve to interface wi th the buses. Such bulTers are nece.~sary when two or more devices arc connected to a common bus. To prevent the devices from interfering with each olher, the lris tate buffers are used to disconnect all devices except the ones that are communicating aI any give n ti me.
INTERNAL INTERFACING
Bus Contention Bus contention occurs when two or more devices try to o utput opposi tc logic levels on the same common bus line. The most common form of bus contention is when one device has not completely turned off before another device connected to the bus line is turned on. This generall y occurs in memory systems when switching from the READ mode to the WRITE mode or vice versa and is the result of a timing problem.
Multiplexed lIDs Some devices that send and recei\'(; data have combined input and output lines, called 110 ports, that must be mult iplexed o nlD the data bus. Bidircctionai tristate bu ffers interface this type of device with the bus, as illustrated in Figure 12- 34(a).
Bus
FtGURE t 2-34
Multiplexed I/O operatio n. I/O
1100
LOW Sclllllnj!
I/O I
Bu, linc
110
-
-II-UGH
1m Rn:eh·inl;
SNDIRCI'
",
,b,
Each VO [X)11 has a pair of tristate buffeTS. When the SNIJ/ RCV( Send/ Receive ) line is LOW, the uppe r tristatc buffer in each pair is enabled and the lower one d isabled. In this state, the device is acting as a l;ouree and sending data to the bus. When the SNIJ/ RCV line is HIGH, the lower tristale buffer in each pair is enabled so that the device is acting as an accepwr and receiving data from the bus. This operation is ili ustr.lted in Figure 12- 34(b). Some devices provide for multiplexed va opcr.lliOI1 with interi1 HI c ircuitlY.
12-7
1. \.Vhyare tristate buffers required to interface digital devices to a bU5? 2. What is the purpose of a bus system?
•
725
726
_
12 - 8
INTRODUCTI ON TO COMPUTERS
STANDARD BUSES A bus can be thought of as a "highway" for digi tal signals; it consists of a set of physical connectio ns (printed circuit traces or wires) over which the data and other infonnation are moved from one place to another. A bus also consists of a siandard SCt of s peci fi cations that desig nale the characteristics and I)')X:S of signals that can travel along its pathway. Inlcmal buSt:..,; interconnect the V'"drious components withi n a computer system: the processor, memory, dis k drive, controller. and interface cards. External or 110 buses provide for tm nsfer of digital signals between a computer and the "outside world" and interface the computer wilh peri pheral t.'
Internal Buses Internal buses in a computer carry addresses. data, and conlrol signals between the microprocessor, cache memory, SR!\M. DRAM, d isk drives. expansion sims. and other internal devices. Personal computers consist of th ret: types of illlernal buses: Ihe load bllS, the PCI bllS, llnd the 15,'11 hilS. Figure 12- 35 shows the b3.-;ic arran!1emcnt of a bus syslem. FIGURE 12-35
Simplified iII ultra tioo of the basic bUI I)'Stem in a typicat perloOnat computer.
M~in Illemory
Coprocessor
Cache
Local bus
PCI bu, controller
PCI
PCI de"ices
bu~
(card stOlS)
rSA bl.1!;
cuntrvllcr
ISA bu.,
ISAdevic<$ (card , lOIS )
STANOARD BUSES
Local Bu.!" This bus direcllyconnects Ihe microprocessor to the cache memury, Ihe main memory, the coprocessor. and tIle PCI bus Controller. The local bus is the only internal bus thai connects directly to the microprocessor. Generall y, this bus includes the data bus, the address bus. and Ihe control bus thai allows the microprocessor to communicate wi th Ihe other dcvices. The local bus can be considered as the primury bus in a computer systelll. For example, the Pentium local bus consists of the address bus containing 32 memory address I.ines, the data bus contai ning 64 dala lincs, and the comrol bus containing numerous controlli ncs. PC! (Peripheral Contro/lnterconnect) Bu.!" This bus is for interfac ing Ihe microprocessor with external devices via expansion SloL~ (connectors). The PCI bus was developed by Intel ; and since il was firs l introduced in 1993, it has become the standard personal compuler interface bus , replacing seveml carlier bus sl:.Indards. PCI is a 64-bil res, al though it is often implementt."I:l as a 32-bit bus in which the address and dala buses arc mult iplexed. It can operate at clock :spced~ of 33 MHz or 66 MHz. 111e PC! bus is isolatL"I:l from the local bus by a bus controller unit that acts
ISA (Indus try Standard Architecture) BUJ 111is expansion bus was developed by fBM for its AT personal computer and is the standard bus into which virtually all printed circuit cards macle before 1993 plug, The lSA is currently incorporated into most mooern personal computers, as a companion 10 the PCI bus, for purposes of backward compatibility. The ISA has either an 8-bil or a 16-bil data bus and can operate at 8.33 MHz, An expanded version called the EISA provided a 32-bit data bus, but it has largely been discontinued due to its slow speed and replaced with the PCI bu;.,.
Extemal Buses External deviccs arc coonected to a computer via an input!outpUi (UO) interface called a pori. There are two ba~ic types of computer ports, the serial pon and the (Xl/fillel pori, and most computcrs havc a parallel port and at least one serial port for connecting modems, printers. mice, and O1her peripheral devices. A serial por1 is uscd for serial data communication, where only I bit is transferrcd at a limc. Moocms and mice are examples of typic a! scrial dcvices. Also. serial portS arc somctimes used for interfacing test and measuremcnt equipment with a computer. A parallcl port is used for parallel data communication, where at least I byte (8 bits) is transferred at a time. There arc several bus standards currently in usc for bOlh serial and parallel pons. TIle most prom inent oncs arc dcscribed ncxt.
Serial 1/0 Interface Buses RS-ZJZC TIlis is one of Ihe oldest and most common standard.. for serial interface approved by the Electronic Industries Association (EIA). The RS-232C is alsu referrcd to as the EIA-232. Most modems (modulator/demodulator) conform to the ELA-232 standard, and mosl personal computers have an RS-232C port. The mouse, some display screens, and scrial prinfe~i n addition 10 moderns-are designed toconnccl to the RS~232C port. The RS232C is commonly used for interfacing data terminal equipment (DTf-:) with data
•
727
728
•
INTRODUCTIO N TO COMP UTERS
communications l.!tjuipment (DCE). For example, a computer is d 1.ssificd ao; OTI3
The RS-232C 2S-pin connector plug.
Figure 12- 37(a) lisls the signals and pill assignments for a 25-pi n RS-232C conncclor, and p
Up 10 63 deviccs can be connected 10 FireWi rc based on a daisy-chain arm ngell1enl. ·n le FireWire cable consisL<; of six wires. two twisled pair for data and IwO for power. Also, this sland
STANDARD BUSES
r,
PI N
,
'2
' 3.
,
~":" u.:,,,.. "" n,II Rl
,.
("k; :1I"
S'
h. '>CIki IC:~rs =,___
1)"~la ""I I~'.ki) I DS I~J
6.
~, '11.;11 J!1'I.urki
'7
,.
I}Jla <':lIT;"" ocl<'t:t (IX' D )
9 Ie>.tp;n 10 To-t ri"
I)TE
" " " " " "
L"I!" ;~,,ed
Scl:olll1or)
12
OCE
rr.ln~ml""(ln limin~
s.....,>rld!!1) R[) (5RI)) 11.<'-'1:;''':' tlming
,
l.ocnJloopb;K\.. Il LI
2
&....uJ.laJ)
19
2>
lilk! "gnal dcl<'Ct
~'C. ".d"r} '1"1) I~DJ
16
20
I~CVD
,S...·..:t)nr.lm) CTS (se TS)
RT~
ISRTS)
3
I);ru krlll",;!1 Il'ad) Il flR I
-
22 , 23
2<
"
R<.'nlrUk: 100r"":I.IR I .)
-
-
Rill!, lIUM:.tl'"
D••I;.....I e ",k,el
- - ------
'Irnn\l1l1l MV\iII
h nu~~
'Ie'>l mode lT1\1)
(a) Full RS-232C Vi-pin interface wil h 1)'(lic~1 personal computer configuration irK'~~1Cd by blu!: and three minimu m ~isn~ ls mllrked by lUI aSl!:ri~1. (p ins 2. 3. 7).
,
DTE
, , , 7
9 (b) 9-pin RS -2:12C
Oat:! ,'arner ,.ldeel (OCI) J
Rc:cc",cd data (RI)I ·[nu\)Inlll<.'u u..t~ ITI)I ~a
lernullal rellr.l) [DTR I SIPl.llI.!fOllUU
t)ala 'oCt rr..~I) Rell"CS!.
IDSR)
10 sclki
tRTSJ
Cle....- It) -.end leTS) ~inl!
inlcrfl~
FIGURE 12 - 37
The R5~l32C pin allignmentl and ';gO<\I. for both connectorver1ion~.
devices, any uf which c
Parallel 1/0 Interface Buses IEEE 488 This bus siandard has been around a long time and is
inuir:;lI.ur
OCE
•
729
730
•
INTRODUCTION TO COMPUTERS
Compu ter
Monitor USB ~'ablc
USB
•
T)peA
us.
oonllCClor (oomll,.'CIS to compuu:r)
pon.~
P
~t~ 0,,
,,
USB poru,
, ,,
="" " 'Gnd
,,
Spcllker
J
MICrophone USB porIs
,
,
,
(
1
I
L
USB ports
J
TypeB USB
Modem
conneclor (COl1ll('(;t~
to
peripher.!ls)
r Prinlcr
FIGURE 12-38
&;,mpJe of;, computer .ystem with USB interf3Cing.
setup, up to 14 controlled devices (test and mea.>;urcment instruments) can be connccted to (he system controller. When the system controller issues a command for a controlled device to pcrfonn a spccifil..'
STANDARD BUSES
Instrument
lnMrllment
[n~lrllnlCnt
In",,-rumem
A ConU\JlIc r
B
C
D
Tal~crfL;slcncr
Ta[~crIL'.'lcner
LiMcncT
'1~I"cT
(Compuler)
(DMM)
(Prinler)
(C()IJ nlCrj
Dala lx,s
[nl<'fla:\'
~kar
AlIenl;I'n Scn'i~e
1\.'"4
l~cl1lUt<·
FN
Interface mH11IIgemenl hllS
End or i\knlif) D.. tll,,,li.J r.;OIr~;\IJ~
:-<01
~\V
___
("rOma :-JRI D - -
d~ta ~.:ceptcU 1'1"1)"<:'--
FIGURE 12- 3 9
A typiGll lEEE 488 (GPIBJ connection.
The parallel data li nes are designated 0 1/01 throug h OU08 (data input/output). One byte of data is transfe rred on this bidirectional part of the bus. Eve!)' byte thai is transferred undergoes a hand~ hak i ng operation via the data transle r control. T he three acti ve-LOW handshak ing lines indicate if data are valid (OAV), if tl1c addressed instrume nt is not ready for data (N RFD ), or if the data are 110t accepted (NDAC). MOfC than one instrument can accept data at tI"lt! !'lame time, and the !'I loWCSI instrument sets the mte of transfer. Figure 12-40 shows the timing d iagram for the GPIB handshaking sequence, und Table 12-2 descri bes the handshaking s ignals. TIle fi ve s ignals o f the interface management bus cont rol the orderl y flow of data. The ATN (attenti on) line is monitored by all instrume nts on the bus. When ATN is active, the system controller selects the specific interface operation, designates the tal kers and the listeners, and prov ides spccitic addre~s i ng for the li stcners. Each G PII3 instrument has a
01101-011011 ==X~_~I'~"'="~b~",~'_~X~_....::'''''::..:d=.":.::;'''~''''-~>C DAV
"\OT\"Al ID
I
VALID
INarVt\UD I
\AUG
INOfVALiO
___ All ready _ _
NRrn __~~" :":-~n "UIlI! ready ~n,--,N~'C"o'c'C'"='"')__ Some n:ad~
fIGURE 12- 40
Timing diagram for the GPtB handlhaklng .equence.
Some'" rcad)"
•
731
732
•
INTROD U CTIO N TO COMP UTERS
TABLE 12-2
NAME
The GPIB handlhaking lignall.
DESCR.IPTION
Data Valid: After the wl kerdetectb a HIGH un the NRFD li ne. a LOW is placed on this line by the tal ker when the data on its UO arc sdllcd and valid.
NRFD
Not Ready ror Data: ~ listenef places a LOW on this line to indicate Ihat it is not ready for data. A HIGH indicates thm it i~ re.1dy. TIle NRFD line will not go HIGH until all addJt:.S.<;ed listeners are ready to illXept tcd: The listener pla\.'e!; a LOW on thiS line to indicate that it has nO( accepted data. When il accepts
TABLE 12-3
NAME
The GPIB manageme nt lines.
DESCR.IPTION
ATN
AlI l.'lIlion: Causes all_ he device~ on the bus to iOierpret data. command Of addrcs~ and activates the hand~hald ng (unction.
a~
IFe
In l t'rfat.~
SRQ
Sen-in- Rl'q ue;t: Alel1s the controller tlmt a device needs to communicate.
REN
Remole Ena ble: Enables devices to respond to remote program control.
EOI
End ur Identity: Indicates the
a cOOiroller
Clear: In itializes the bus.
la~t
byte of data to be lr.lII~ferred .
specific idcnt ifying address that is used by the system cont rolle r. Ta ble 12- 3 descri bes thc GPIB interface managemen t lines and thei r functions. The GPIB i$ limilCd to a maximum cable le ngth of 15 meters, and there can be no mOl\: th,lIl o ne instnllnenl per meie r with a maximum capacitive loading of 50 pF each. lhe cable length limitation can be overcome by the usc of bus extenders and modems. A bus cxtendcr provides for cablc-interfacing o f inslrumems Ihat are scparakd by a d istance greate r than allowed by the G PIB spt."CiflCations or for com municating over greater dista nces via modem-interfacc..-d telephone lines. TI1C use ofblL~ exte nder.;; and/or modems is illlL';tratoo in Figure 12-4 1.
De,·icc
,
\)c\'icc
I
(controller)
""'
GPIB
Motlcnl
cxtender I.o"~
cable lno modenl ! ~
Telephonc li nes
(bu.~
extcnder + mode m!
Device
" Mokm
"",
e~ tendcr
G I'lU
FIGURE 12 - 41
A bm extender and modem can be Uled (Of interfacing remote GPIB o/StemJ..
STANOARO BUSES
SCSI (Small ComPfJWr System InterfoGe) Pnmounced $Cltz:;:y. this is a widely used standard for intert"
SCSI-l This ver.;ion is the same as SCSI- I, but u.
This uses a wider connector than SCS I-2 Io support 16-bit dala Ird nSfers.
Fast SCSI 10 MB/s.
This provides for 8-bit data transfer but suppons data transfer rales o f
Faw Wille SCSI
This version transfers 8 bits of dala at 20 Ml3/s.
Ultra SCSI SCSI-3
This version allows 16-bit data transfer al 20 MBts.
This version has 16 dala lines and ru ns al 40 Ml3/s.
Ultra SCSJ-l
This version transfers 8 bits al 40 MB/s.
Wide Ultra SCSI-2
This version provides for 16-bile dat
80 M Ots. TIle signal descriptions for a SCSI 25-pin connector arc given in Table 12- 4, and the pin configuration is shown in Figure 12-42. TABLE 12 _ 4
SCSI ligna II. PIN NUMB ER
SIGNAL N AME REQ!
SIGNAL DESCRIPTION R C
PIN NUMBER
SIGNAL NAME
SIGNAL DESCRIPTION
14
GND
Sigllal ground
C/DI
CommandlD:na
I.
2
MSG!
Messag~
3
liD!
InputJOutpul
GND
Signal grou nd
4
RST!
SCSI bus rcsel
17
P> I'NI
Atlenlio n
5
ACKl
Acknow ledge
i8
GND
Signal g round
IS
6
BSY!
Busy
19
S EU
Select
7
G ND
S ignal ground
20
OBPI
Data parity
8
DBO!
Dlltabil O
21
OB I!
On!a bit I
22
OB2I
O'Jta bit 2
9
GND
Signal~und
10
DB3!
Data bil 3
23
DB4I
Data bit 4
II
OB51
O'
24
GND
Signal ground
25
TPW R
Term inator power
12
OB6I
D:nabil 6
13
OB71
I)-Jla bil 7
FIGURE 12 - 42
13 t2 I I to 9 8 7 6 .5 4 3 2 I
i)
\ 0000000000000 ,\000000000000); 25 2423 222 1 20 19 II! n ib 1514
SCSI 25-pin connector.
•
733
734
•
INTRO DUCT IO N TO COMPUTERS
I
SECTION 12 - 8
1
1. Name the two major bus categories in terms of the way data are wnsferred.
REVIEW
2. Clauify each of the following buses as serial o r parallel:
(.) SCSI
(b) RS-232C
(e) USB
(d ) GPIB
3. Explain the basic diffe rence between a serial bus and a parallel bus . 4. How many devices can be connected to the USB? 5. Is t he FireWire a faster bus than the USB in terms of data transfer?
•
Basic units of a colllptJltr arc sho\\m in Fi1.'llre 12--43. FIGURE 12 - 43
Input poo
Output
CPI '
PO"
Memory
•
1lle th ree bllsic computer buses are the a(/(lrf!sJ bus. (I(lW blf~·.
•
Typ ical peri pheral do.:v ices include the keyboard, ex ternal disk •md scanner.
dri\'e.~.
mouse, print er, modem .
• 11)C number of addre....~ li nes iocl'e ased from 20 for the 80R61ROSS to 32 for the Pentiu m fami ly. T he dma bus was originnlly 16 bi ts for the 8086 and is 64 bi ts for the Pe nt ium fllmi ly. •
Genenll registers are a subset of those in all of the Inlel processors. They include Accu mulator (AX. whic h includes AI-! and At) Base (EX, which incl ude.~ BI I and BL) Cou nt (CX. which incl udes CH and CLl Data (OX. which includes DH and O L) Stack pointer (SP) Base pointer (UP) Desti nation index CDIl Source index (S I) Beginni ng with the 80386 proce~sor.
Ihi~
basic- set
Wil~
expanded to the extended
regi~le r
set.
• 11)C basic segment registers are iI subsel of those in all of the Intel processors. The segment registers are Code segment (CS ) Datll ~gmen t (OS ) Extra segme nt (ES) Stack segme nt (5S) Begin ning with the 80386 processor. •
IWO
new St.'gment registers were added.
The flag registers arc 11 subse t of those in all of the Imel processors. l hey incl ude Tntp (TF) Direction ( OF) Intcm lpt enable ( II:') Overflow (OF)
KEY TERMS
•
735
Si,gn (S F)
Zero (ZF) Auxiliary carry (AF) Parity (PF)
Carry (Cn •
T he basic " Ian,g uage" of a computer is called machine rode in which instructions are given as a series of bi nary codes.
•
In assembly language, machine instructions arc replaced with a short i1lphabetic Engli5h mnemonic 111<11 has a one-Io-one correspondence 10 machi ne code. Assembly language alw uses direcli ves to a llow Ihe programmer to specify mher parameters thaI arc oollrnnslaled direclly inlo machine code.
•
Ports are iITl interface to exterrlill dev ices. They can be set up as in put. output. or a combinmio n of both. They can be accesSt!d as dedicated or as memory-mapped and can be serviced by polling. inlerrupHlri"cn. or ~OfiWilre.
•
Tll blc 12- 5 comp
TABLE 12-5
INTERNAL BUSES
EXTERNAL RUSES
I
--------------- I ------------------- ---------------------------PCI ISA i RS· 232C IEEE 1394 USB IEEE 488 ~CSI
Type
Paralle!
Par-J llcl
Dnl(l lines
32164
81 16
D(lta r(lle
33/66MHl
8.33 MHz
Serill!
Seri al
Serial
Parallel
8 20 kooud
400Mbis
1..5112 Mbls
I Mbls
Parallel 81 16
4 Mbls (I) IU Mbls (Fast)
20 Mbls (Ullm)
40 Mbls (3) 80 Mbls (UJt rawide 2)
63
NumlWI" of f/el.'ices
KEY TERMS
Key terms and other bold
term~
127
14
16
in the chapter are defined in the e nd-of-book glon ... ry.
Addrcs.'i blls 1\ nne-way group of conduclors fro m the micmpr"lx:e.,<;or 10 a memory, or other external device, on which the ilddress code is sem. Assembly langmlge A progr.llllming l iITlgua~,'e thal uscs English-like word'i
pro~rJm
instructions.
Data bus A bidirectionill sel of condudivc pilths on which data or instnlction codes are trnnsfcrred into
Thc IEEE- 1394 sll1 ndard seri al bus.
GPIll Gcoc'r.ll-purpose inlerf
736
•
INTRODUCTION TO COMPUTERS
Machine hmguagc Cornplller instructiOfls wrinen in bi nary code that arc understood by a computer. lhe IOWL'St lc-.'cl of progrumming language. l\'Ueroprocessor A largL~ sca le digiml irrlegrmcd circuil that e'ln be prog rammcrllO perfo rm arithmetic. logic, or other operations: the CPU of a compu ter.
Modem A modulator/dcmodulator for interfacing digital devices to analog tran~mission systems such a~
telephone lines.
Peripheral A device wch
a~
a primCf or moo.::m that provides communication with a computer.
Port A physical interface on a computer through which data are palSscd to or from a pcriphcr.ll. Pr01;:ram A list of instructiuns thai a computer follow s in onIer to llchicvc a spct;ificd resull.
SCSI Small computer systems interface: an external paralld bus l>Iandard. Trh1ate A type of OUlpul on logic circuits that exhibits three stalC:S: I-lIGI-I, LOW, ilnd high Z; used to interface Ihe ou tputs of a ~ourCe device to il bus.
usn Uni vcn.al serial bus; an extCT11il1 scri ill bu~ swndard.
Answers are at the end of the
J. A basic computer docs not include (a) an arilhmet ic logic unit
(b) a control unit
(e) pcri pheml units
(d) a memo), unit
2. A 20-bil address blls SlipponS (a) 100,000 memory addrcsses
(b) 1,048.576 memory addresses
(e) 2.097.152 memory addresses
(d) 20,000 memory
addrcs~o;:s
3. The number of bit~ on the dam bus in Ihe Penti um pr(')CC5l;Ors is (a) 16
(b) 24
32
(e)
(d) 64
4. A bus that is used 10 tran~fef ;nfonnalion both to and from the microprocessor is the
(a) address bus
(b) data bus
(c) both of the above
(d) none of the abovc
5. An example of a peripheral unil is (a) the add rc~~ rcg i~ter
(b) the MPU
(c) the video monitor
(dl the interface adapter
6. TwO types of memory tmnsfers handled by the CPU arc (a) direct and interrupt
(b) re.aLI and write
(e) bus,..ed and mult iplexed
(d) input and Olliput
7. In Ihe Intel fami ly, the max imum numbcrof 8-bitl/O device~ is (II) 64
(b) 1000
(d) I million
(c) 64,000
(e) unlimited
8. Polling is a method used for (a) determining the state of the microprocessor
(b) c.<.lablishi ng communication~ be tween the CPU and a pcriphenll (c) establishing a priori ty for communicatiun with scverJI peri phcr.. ls (d) di!tcnnining the next instruction
9. Of the following, which is a 8· bit register? (a) AH
(b) BX
(e) SS
(d) IP
10. Essentially. a mncmOflic is a(n) (al flowe han 11. DMA
~ tands
(b) opcnlOd
(CJ machine code
(d) instruction
for
(a) digital mieroproccs,wr addre;s
(b) direct memory
(e) clata multiplexed access
(d) dired memory addn."SSing
PROBLEMS
•
12. II computer progra m is a list of (a l memory
atIdrcsse~
that c.."(mtain da ta 10 be Ilscd in an opcmtion
(b) ilddrcsses tha t contain instructions to be Ilscd in an operation (c) i n~l ruet i ons arrange
13. A type of llSSCmbly langlmge that alters the course of the program is cilllcd a (a) loop
(b) j ump
(c) bulh of the above
(d) none of the above
14. II type of interrupt that is invoko.:tl from with in (a) suftware interrupt
(b) polled illlCrrupt
(e) di rect in terrupl
(d) UO intelTllpl
fI
pro!,lmm is called a
15. Most devices life interfaced 10 a bus with (a) IClem-pole OlItPlilS
(b) tristate buffers
(e) Imp tr3 nsistOl-s
(d) re.,i ~tors
16. The PCI bus cOnsislsof (b) 32 or 64 data lines
(a) 8 or 16 data lines
(e) 1 :reri al data line
17. The devices OJXl7lti ng on a GJ>IB arc called
(a) source lind load
(b) ta lkcr and listener
(e) tr
(d) donor and acceptor
18. The RS-23:!C is (a) a standard in terface for pamllcl da ta
(b) a siandard interface for serial d:lta
(e) an cn hanccmellt of the IEEE 488 interface
(d ) the same as SCSI
19. The FircWirt' bus is the ,,;
(b) USB
(d) RS-422
(e) RS423
IEEE 1394
(e)
20. The USB can support up to
PROBLEMS SECTION 12 - 1
(a) 63 devices
(b) 14deviccs
(e) 100 dcvicc..'S
(d) 127deviccs
Anw,eo to oc:Id-nvmbered pro blem! are at the end of the book.
The Basic Computer 1. Name the b;ISic clemenls of a com puter. 2. Name two categories of compu ter software. 3. Whal is a bus?
4. What is a port?
SECTION 12 - 2
Microprocessors 5. Name the oosic clements of :l microprocessor. 6. List th ree opcmtions thai
il microprocCli~vr
pcrfom15.
7. Lisl the three microl'roccssOl' buses.
8. What arc the seven
SECTION 12 - 3
ba~ ie
groups of the Penti um instnlction sct?
A Specific Microprocessor Family 9. What arc the thn:c basic steps a processor repeatedly cycles through? I n. What is meu m by"pipc li ning"? II . Name the siJl segment registers.
737
738
•
IN TRODUCTIO N TO COMPUTERS
12_ As.<;ume the code !;Cgme nt regi ~tCJ" co mains the hell number ORl5 a nd lhe instructio n poim Clreg ister col1lai ns the nWllber 0100. Whl!( is the ph ysical nddru;s of the nell l instruction to be cllecU!ed·? 13. Ellplain the diffe rence bet ween the AH, the AL, the A X, and tile EA X reg isters.
14. (a) Whm is a flag? (b) Whlllt ....,o purposes are nag~ used for? 15. E xplain the advantage of instruction pairi ng in the Pentium procc~sor.
SECTION 12-4
Computer Programming 16. Wh at is a n 3f;.<;cm blcr?
17. Dmwa nowchart for a program th at adds the num lx: r.s from une 10 10 ami "avcs the resull in a me mo ry locatio n na med TOTA L.
18. Dr.lw II nowchart ~how in~ how you could count the number of bytcs in a
~tri ng an d place the count in a loca tion in memm)' ca lled COUNT. Assume the stri ng st:ms at a locatio n named START and has a 20H (ASC II fnTa space) tu s i~ n al t he end. Yo u ~hould nut coun l the s[XIce Chm"3Cle r.
19. Explai n what hapfl\! ns w hen the insfn lCl ioli mov itx,[ bxl is CIlCC uteU.
20. Whllt is a compile r?
SECTION 12-5
Int enupts 21. Compa re pollL"1.I I/O to intelTU pt-d riven 110.
22. What is meant by the lenn "ecloring? 23. Whm is meant by a software interru pt?
SECTION 12-6
Direct Memory Access COMA) 24. Explain what happens ;n a DMA opcl1ll ion. 25. How is the C PU
SECTION 12- 7
u ~cd
in DM A?
Intern
-==_
_-'nL_ _ _
_ __ _ _----"iL
27. Dcte nnine fhe sig nal un the bus li ne in Fig ure 12-45 fo r the data-i n pu t a rxl e nable waveforms s hown. FIGURE 12 - 45
O~ta H
Enable H
------=-=[...:...:~~J
PROBLEMS
•
739
28. In Figure 12-46(a), dala from lhe 1""0 sources are being placed o n the Ihlla bus under control o f Ihe scl(X;t line. The select waveform is shown in Fig ure 12-46(b). Determine the dala -bus waveforms for the t1evice output codes indicaled.
Dc~ke
I
DcVK:C 2
D,
D,
Bus (II hncs)
(,)
s _ ----' (bJ
FIGURE 12 - 46
SECTION 12-8
Standard
Bus~
29, Explai n the b..1sic difference bel\.\leen a local bu... and the PCI bu~.
30. Define ··plu1.\-and-play:· 31. How docs Ihe PCI bus differ from lhe ISA bus'! 32. If a shorter RS-232C is used. can data
tx:: U"a nsmilled al a fasler rate?
33. OCE and DTE lIre part of whi ch bus specifiealion? Explain the acronym~, DCE and DTE. 34. List lhe wires in a LOSB cable. 35. Eighl CPIB-compatible instruments arc connected to the bus. Hov.· many more can be added without excccdi!lg the specifications? 36. Consider the GPIB interface betwl."en a talker and a lislencr as shown in Figure 12-47(a). From the handshaking liming diagr.lm in part (b), dClenni ne how many data byles arc oclllally trn nsferred to the listening device.
Talkcr
LiSTcner
DAV
OaT:! I,.!)
DAV
T=""{ ""
NRm
NRFI) NI)AC
JlL_---'n <-_-----'n L _ _ _ _---'nL _ _
NDAC _
(,)
(b)
FIGURE 12- 4 7
-----'1L.
---'n L_ __ _---.Jn<--_ _ _
740
•
IN TRODUCTION TO COMPUTERS
37. Dc!.Crilx the opemtion... dep icted in the aPIB timing diagram of Figure 12-48. Develop a Ixlsie bl vd, di ag mm of thc system ill\'oln.'1.l in Ihis Operation. 38. A talker scnds a dala byle 10 a listener in II GP II:l system_ Simu ILant.:ous ly. 11 DTE send~ a data byte to a DeE on 1m RS-232C iruerf,ICc. Which system will rt.'CCive the c~plete dala byte finit'! Wby? Dahl
Address
1);\1:1
Address
(DJIOJ-DIfOOl -{,_ _ _ '~_'_A_ _-,Q---y7tJ~
ATN
DAV
__OO_ 'B_ _---,
='~;;;;~=15=~:'~;;;;2=~~=~ I
I
-
I
I
i NRFD _ _ _ _ _ _--',m; 'L---c,e--' "no'L- -Ct' _ _ _ _ _----'
,
,
NMC __________L-~nLi-~nL________~~ FIGURE 12 - 4 8
SECTION REVIEWS SECTION '2- '
The B'!IJ:ic Computer 1. Basic elem
SECTION' 2-2
Microprocessors I. Elements of
fI
microprocessor are ALU. instruction decoder, register army, and cont rol unit.
2. M icroprocessor buses arc address. data, and control. 3. A microprocessor functions a.. the CPU. 4. Aritlllneticllogic opentlion~. moves dnta. and makes decisions.
5. Pipcli ni ng
SECTION 12-3
i~
the process of e:>;e<:uting more than one instruction at lhe sall:C limc .
A Specific Microprocessor Family I. The gener-dl-purpose registers are Accumu lator (AX: AI-I. A L) Base index. (BX: BH. BLI Count (CX: CI-I. 0 ") Data (DX: 01·1. DL)
Stac k pointcr {SP) Ba~ pointer (BP) DI..-stinfllion inde:>; (01) SoIII\:C index. lSI)
2. The BIU provides acWrt.'ssing and data interface. 3. No, the EU docs not intcrface with the
bu.'iC~.
4. nte instruction queue Slores prefctched inslruclions for thc EU to increase throughpu t. 5. Codes C:tll be easily relocated within memory. 6. Instn.lction Jl'Iiri ng is the process of combining independent inslruct ion~ so Ihat they can be e:>;ecu ted simulta neously b} the Iwo e:>;ccul ion u nil~ in the Pen tium.
SECTION 12 - 4
ComputerProgramming I. A program is a li~1 of com puter inslruction s arrJllged 10 ach ieve a specific rc~u ll
2. An
op-L"
is the code fur an illSlruclioll.
3. A siring is a w miguous ot.'
ANSWERS
SECTION 12- 5
•
741
InterTUpb I. For an intcrrupi-drivcn 110, the CPU prov idc~ service to a peripheral only whcn 1'Cl:lucstcd to do SO by the periphcral; for a polled 110, the CPU periodically checks a peripheral to see if it ncals serv icc.
2_ Intcrrupt-drivcn IIOs save CPU time. 3. A software intCfmpt is an
SECTION 12- 6
in ~tmction
that invokes an interrupt !;Crviu: routinc.
OirectMemoryAcceu (OMA) I. DMA is direct memory aCCL'SS. 2. A DMA transfer of data from memory 10 110 or vice versa savcs CPU lime. Din:ct memory access is often usc..'
SECTION 12- 7
Interna"nterfacing I. TristlllC buffcrs allow devices to be completely disconnected from the bus when not in use, thus preven ting intcrferencc with ol.hcr dcv ices.
2. A bus inlCrconnccts all thc devices in II sy!>Icm and makcs communication betwecn dcvices possible.
SECTION 12- 8
Standard Buses I, Scrial and parn Ucl data transfcr 2. (a) parallel
(b) serial
(c) serial
(d) para llel
3. Serial- onc bit III II time; l"llmllcl-8 or more bilS III II time. 4. J 27 USB dcvices S. FircWiJ"C is faster th:lT1lJSB.
RELATED PROBLEMS FOR EXAMPLES 12-1 6C4C2 1~ 12-2 Changc first block (inilialization block} to " BIG = Fl'FF'; this is the largest possible unsigned number. Change nrsl question to " Is numbcr < BIG?"
SELF-TEST 1. (0)
,.
2. (b)
3. (d)
4. (b)
5. (e,
6. (b)
7. (e)
8. (b)
(,)
10. (d)
II. (b)
12. (c)
13. (c)
14. (3)
15. (b)
16_ (b)
17.
(b)
18. (b)
19. (e)
20. (d)
CHAPTER OUTLINE
13-1
Digibl Signal Proceuing Badcs
13-2
Converting Analog Signals to Digital
13- 3
Analog-to-Drgibl Conversion Methods
13- 4
The Digital Signal ProceuOf' (DSP)
13-5
Digital-to-Analog Conversion Methods
CHAPTER OBJECTIVES
lid the essen Dill elements in il digitil l signill processing ~tem •
Explilin how ilnillog signills are converted to digitil l form
•
Di
•
D~cribe
the Ioilmpling proc~1
Sure the pt.lrpose of ilnillog-to-digitill corwenion Explilin how sevel"ill types of ADG operille E>cplilin the bilSic concepts of il digibl lignill proc~!Or (OSP) Describe the basic ilrchitecture of il DSP
Name lOme of the function! that a DSP perforllli State the purpo
KEY TERMS
Analog-to-digital converter (ADC)
DSP Digital-to-analog converter (DAC) Sampling Nyquist frequency Aliasing Quantinltion
DSP core
MIPS MFLOPS
MMAU Pipeline Fetch Decode &ecute
INTRODUCTION
Digital signal processing is a powerful technology that is widely used in many applications, such as automotive, consumer, gnphics/imaging. industrial, insb"umentation, medical, military, telecommuniCi!ltions, and voice/speech applications. Digital signal processing incorporates mathematics, software programming, and processing hardware to manipulate analog signals. For example, digital signal proceuing can be used to enhance images, compress data for efficient transmission and storage, recogni~e and genente speech, and clean up noisy or deteriorated audio. This chapter provides a brief look at digital signal processing. To completely cover the topic in the depth necessary to have a detailed understanding would take much more than a single chapter. Entire books are available on the subject a list of references is available at the end of the chapter. Much information, including data sheeb, on the TMS320 family ofDSPs is available at the Texas Instrumenb \.\febsite (www.ti.com). Inform
ADC0804
DIGITAL SIGNAL PROCESSORS
TMS320C62xx
TMS320C64xx
TMS320C67)O(
Study aids fOf this chapter are available at http://www.prenhall.com!floyd
743
744
_
13-1
INTRO DUCTIO N TO DIGITAL 51GNA L PRO CE5SlN G
DIGITAL SIGNAL PROCESSING BASICS Digital signal processing convcrl<; signals that naturally occur in analog form, such as sound. video. and information from sensors. to digi tal form and USl'S digilal techniques to enhance and modify analog signal Jata for variou" applications. Aft er completing this section. you should be able to - Defi neADC - Define DSP - Deline DAC - Omw a basic block diagram of a digital signal processing system
A digilal signal prOCe.o;sing system fi rst tmnslales a c011linuously varying analog signal i11l0 a series of discrete levels. This series of levels fo llows the variations of the analog signal and resembles a stairea.'>C, as illustmled for the ca.<;e of a sine w,\ve in Figure 13- 1. The process of changing the original analog signal to a "stairstep" approx imation is accomplished by a sample-and- ho ld circuit. FIGURE U - 1
Hold
An o rigin.1 l .10<1108 sign.1 l (sine WolVe) .1 nd ib ' sbintepw ~pprOKim.1tion.
Eocll hdtllc"e\ is <.~)'l\"ertcd tu a binal)'cotle b)' an ADC.
Next, Ihe " slairstep" approximation is (IUantized into binary codes Ihat represen t each discrete step on the "stairsteps" by a proces.o; called analog-Io-digilal (AID ) conversion. The circuil that pcrfonns AlD conversion is an analog·to-digilal comerter (AI)C ). Once the analog si£nal hm; been converted 10 a bi nary coded form. il is appl ied loa DSP (digilal signal processor). The OSP can perform various operations on the incoming dala, such as removing unwanted interference. inc reasing the amplitude of some signal frequencies and red ucing others, encoding the dara for secure tn.msm issiuns. and detecting and correcting errors in transmilted codes. OSPs make possible. among many OIher things. the cleanup of sound recordings, the removal of cchos from communications lines. the enhancement of images from c r ~ans for better medical diagnosis. and the scrambling of cellular phone conversations for privacy. After a DSP processes a signal, the signal can be converted back 10 a much improved \'en;ion of the origi nal analog .~ i gna l. This is accomplished by a digital-to-analog 0011\'crtcr (DAC)_ Figure 13- 2 shows a basic block diagmm of a typical digilal signal processi ng system. JO I IO 01 JU I 00011 11 100
10111)
Ol IOI
()(IOII Anll-afiaslllg lihcr
SHmpk' /ln!Ihold circui,
111 00
ADC
FIGURE 13 - 2
OS I'
DAC
~econ<;/t1IC'ion
fili I:]
1:.n1i'lIicc-d
-
analog ~i!!J1.:l1
CONVERTING ANALOG SIGNALS TO DIGITAL
DSPs arc actually a specialized type of microprocessor but arc different from generalpurpose microproccssors in a couple of significant ways. Typically. microprocessors are designed for gencral-purpose fu nctions and operate with large software packages. DSPs are used for special-purpose applications; they arc very fast number crunchers Ihal musl work in rt:cl:11 time by processing information as il happens using special ized algorithms (programs). The analog-to-digital converter (AOC) in a sysrem must take samples of Ihe incom ing analog data oft en enough to catch a ll the relevant fluclllat ions in the signal amplit ude, and Ihe DSP must keep pace with the sampling l
I
SECTION 13 - 1 REVIEW Arnwers are at U,e end of the chapter.
1. What doe$ DSP 5tand fa ..? 2. What
do~
ADC .ltand for?
3 . What doe DAC $tand for? 4. An analog .lignal i5 changed to a binary coded form by what circuit? 5. A binary coded signal is changed to analog form by what drcuit?
13-2
CONVERTING ANALOG SIGNALS TO DIGITAL
In order to process signals using digital techniques, the incoming anaJog signal must be converted into digital form. Aft er completing this section, you should be able to - Explain the basic process of converting an analog signal to digital - Describe the purpose of Ihe sample-and-hold function _ Define the Nyqui~t frequency _ Define the reason for a/ia,.,·illg and discuss how it is eliminated - Describe the purpose of an ADC
Sampling and Filtering The fi rst two blocks in the system diagram of Figure 13- 2 arc the anti-alia.,ing filter and the sample-and-hold circui l. The sample-and-hold fu nction docs twO opcmtions, the fi rst of which is sampling. SHmpling is the process of taking a sufficient number of d iscrete values at points on a waveforlll that will define the shape of waveform. The more samples you take, Lhc more accuratdy you call define a waveform . Sampling converts an analog Signal inla a series of impulses, each reprcsenting the amplitUde of the signal at a given insram in time. Figure \3- 3 illustrates the process of sampling. When an analog signal is 10 be sampled, there arc certain criteria that IIllist be met in order to accurately represent the original signal . All analog signals (except a pure sinc wave) contain a spcctlUm of componenl frequencies called IllIrmOIli(".\·. The harmonics of an anaJog signal are sine waves of different frequencies and amplitUdes. When the harmonics of a givcn periodic waveform are added, Lhc resu lt is the original signal. Before a Signal can be sampled, it must be passed through a low-pass filter (anti-aliasing filt er) to e liminate harmonic frequencies above a cel1ain value a .. detennincd by the Nyquist frequency. !he Sampling .Theorem Notice in Figure 13- 3 that there arc IWO input waveforms. One IS the allal ~g signal and the other is the sampling pulse wavcfoOll. Tlle sampling theorem states that, 111 order 10 represcnt an analog signal, the sampling frequency,J..~, musl bear
_
745
746
•
INTRO[)UCTION TO OIGITAl SIGNAL PROCESSING
FIGUR E 13- 3 IIIUltration o f the I
An"l~
-
II1plll
"!!",,I
~"~:::
,i~naJ
circuit
11 1 1 1 111 1 1 111
Samplctl 'c!,jlln of
input
Samp1int
I
I
leaSltwice the hig hest fre(J uency compone nt! o( nlaA ) of the an,llog s ignal. AnOlher way 10 say this is tha I the highest an,llog frequency I:
Equation 13-1
f """fk ?:. 2fo(mJtl) To intuitively understand the slImplinf( theorem, a simple "bouncing-ball" analogy may be helpful. Ahho ugh il is not a perfect representation of the sampli ng of e lectrical signals, it does serve 10 illustrate the basic idea. If a ball is photographed (sampled ) al one insta nt during a single bounce. as illustrated in Figure 13-4(a). you cannot tell anyt hing aboul lhe palh of the ball except that it i.
{H} O'le :smnp le ofa 0011 during a smgle bounc e
(bl Two samp ''-'''' of a ball during II sloll le oolln';e. Thi., is Ihe absolule minimum
required 10 lell anything abollt Its mowmcm. 00) gCllcrnlJy iro;ufficienl )0
tbcribe ils porth.
FIGURE 1] - 4 Bouncing 0011 an ... 'ogy o f ~mpling theory.
(c) l'\:lur S<\mples of a ball during a sillg le
OOuIlCC form a mugh picl ure ofthc pmh of lhe 0011.
CONV ERTIN G ANALO G SI GN A LS TO DI GITAL
•
747
begins to emerge. The more photo" (~amp l es) that you take, the more accurately you can determine the path of the ball <-lS it bounces. Th e Need for Filtering LoW-PllSS fi ltering is necessary to remove all frequency component" (ha11l1Onics) of the an<-llo£ signal that exceed the NY
Unfiltered anatog rrcqucllcy spc«ru nl
.. FIGURE 13 - 5
Sampling frequclICY
A b.uic
illustr.. tion of th e cond ition
O "'CrlHp causes
",Ii.."illg crror
A low-pass ami-aliasing filter must be used to limit the frequency spectrum of the analog signal for a gh'en sample frequency. To avoid an alias in~ error, the filter must at least eliminate all analog fre<]ue nc ies
FIGURE 13 - 6
FitK"fCd analog frequcncy s]ll'Clrum
Samplillg frequcncy ~poxl rum
+-------~----~~----~---f f ...np.. All Appliadion
An example of the application of sampling is in digital audio equipment
n lC sampling mtes used are 32 kHz, 44. 1 kHz, or 48 kHz (the number of samples per second). "n le 48 kHz rate is Ihc most common, but the 44. 1 kHz rate is used for
After low-pcctrJ o f t h e "",,log "m:! thc l
748
•
INTRODUCTION TO DIGITAL SIGNA L PROCESSING
llnd, therefore. req ui res a sampl ing ra te of at least 20 kHz. Hov,:ever. if only frequencies up 104 k H z (ideally requiring an 8 kHz minimum sampling rate) are reproduced, voice is vcry understandable. On the other hand. if a sound signal I!' not sampled at a high enough r.lle, the effcc t o f aliHsing will become noticeable with background noi~ and distortion.
Holding the Sampled Value The holdi ngupcratiun is part of the sample-and-ho ld block .~ hown in Figure 13- 2. After fil-
teri ng and sampling. the lOiimpled level must be held conslant unti l the next sample occurs. This is neces.o;ary for the ADC 10 have time to process the sampled value. This sample-and hold open-ltion resulls in a "stainaep" wavefom l that approximates Ihe
Smnpl<:t1 \cI'ojon of .nput ,.fllat
I
I
-
-
I ! ! ! I ! II ! II!!
Sample
I
J
l-
! told
Samp!c-und·oold
S:unpk·:ml.l-tK,k/ appro\.imauon of ill[KI1 Sf)!I1,'(
FIGURE 13 - 1
Jl/ uIU;)tion of iI sample-'lJ1d-hold operation.
Analog-to-Digibl Conversion Analog-Io·digita l conversion is Ihe process of convcning Ihe output of Ihe sample-andhold c ircuit to a series of binary cooes thaI represen t the am plitude of the analog input at each o f the sample times. Thc .~amp le-and-ho l d process keeps the am plitude of the analog input signal con~tam between sample pulses; the refore, the analog· to-digital conve rsion can be done usi ng a constant va lue rather Ihan having the analog signa l change during a conversion interval. which is the time between sample pulses. Figure 13- 8 il-
-1
ADC
~
'-------'
,'",
,
~ \OIOO : OIOI: ·
l.JLl.Jl..rlL
,,
,,
) 1 10011 U 1 0 1
.. JlJlJll.
FIGURE t 3 - B
B,nic function of ,10
j,
CONVERTING ANALOG SIGNA LS TO DIGITAL
•
749
lustrates the basic fu nction of an analog-ta-digital (ADe) converter. The sample interva ls are ind icated by dashed lines. The process of converting an llnalog value to a code is called quuntization. During the quantization process, the ADC convert." each sampled value of the analog signal to a binary cc:x1e. The more bits Ihat :Ire used to represent a sampled value, Ihe more accurate is the representat ion. To illustrate, let's qlUlIltize a reproduclion of the analog waveform into four levels (0-3). As shown in Figure 13-9, two bits are required. NOle thai each
Qutlnfuation
.... FIGURE 13 - 9
Quantll.ilnOn level (Code)
S
3 ( II )
(
2 ( 10)
1 (01 )
~, ,
,
, r--; ,, ,, ,,
0
(OOJ
2
,,, ,
'h,, ,,s-: ,, ,,
3 : 4
,, ,, ,, ,, 5
6
7
8
'H , ,
,
{ -,
,, ,, ,r , ,,,
,,, , ,,, ,r , ,,,
o rigin
, ,,,
light gr..y for reference.
,,, ,
,, -'
,
,
3
, ,,, ,,,
,,, , ,
Sample
inlervals
9 : 10 : I I : 12 : 13
... TABLE 13 - 1 SAMPLE INTERVAL
QUANTIZATION LEVEL
CODE
0
00
2 3
01
2
JO
4
OJ
5
OJ
6
OJ
7
OJ
8
2
10
9
3
10
3
"12
3
" "
J3
3
3
" "
"
Ir the resulting 2-bit digilill codes are used 10 reconstruetlhe origina l wavefonn. which is done by digital-to-analog converters (DAC), you would get the wavcronn shown in Figure 13- 10. As you can see, quile a bit of accuracy is lost using only two bits to re present the sampled values.
Two-bit qu;mtiZ
waveform in Figure 13- 9.
750
•
INTRODUCTION TO DIG ITAL SIGNAL PROCESSING
fIGURE 13-1 0
The recorntructed W>lvcform in Figure 1 3-~ ~Ing four qu.mtiziltion leveli (2 bib). The origin"l """log waveform is shown in light gray (or rdefence .
Biliary Vlllucs
//~\
,
,, ,,
/ I
0
,
,, ,,,
o
00
2
]
4
5
6
,, ,, ,, , , , , , ,
,, '- ,, .' ,, ,, ,, ,, , , ,
,, , ,,
,, ,,
, , , , ,,, ,,, ,,, ,,,
, , , , 7
8
9
,
10 I II
12
Sample intervals
I]
Now, lee s see how more bits will improve the accur
Sample->lnd-hold output w>l\'E"form with lixteen qU.lntization Ieveli. The o rigi"'" ;) n>l log waveform il shown in light gray for reference.
Quanl;,.III;UlI
Ic'·cI (Oxlc)
Jf(I!} ll .=-_::::::::::... ___ . ____ ______ _ 14 ( 1110)
if:::~ -1I- (TO i l)
I~:F~'R
______ • ___ •
_ _ _ _ _ _ _____ _ _ -1 __ ..1
__: . 1
__
-----.. -----------.. - ·-}- --:--i - t ~.- : : ----------------- -- ,--r--,-· ,-+-+ i., --t : ·- , -- 1 :: :: :: t :: ::::::: J :::: ~ :::
:::::::::::.::::::::::.::::::::- ..:: ::::: ::
- 8 (1006) ------------------
-
-7 (01 11)
: : : : 1:I : : :::tI : : .1::::_ jI _:: : l:::::::: I I I
: : 6(Q 1l
- 4(0100) ::::: ::: ::::t ::::~::::: :::: 1::::::: 1.. _ _ 1_ - f IOO l i)
_2(ooiQi
1(0001)
_
-- , --r - -.- - "- - r - - I j :::::::1.:::: : t : : j : : : : j : : : : 1:::-:
-1- --:-- ~ -- + - - ~ - -:- - i -- + -- ~ - --:-- ~ -- ~
1-_
- - \ - - -f
_~
_ ..
_ -'- _ ..1 __ .1. __ 1..
- I- - -f
..- __ 1- _ --1_
.1 _ ..1 _ _ .1. _ _ 1..
__ :
-f - - t - - I
--' _ _ ..1 __ .1. _
I
-_£'"'.'''''''''.L_ !-:-+ ' -,-i'-,-' f-:-+' -,-i'-,:-' f-:-+ ' -,-i'-,--"f-:-+ ' -:c:i'-::c'f.. S"mpl. 2 3 4 S Ii 7 g 9 10111 11 2 1131 in«:""-als I
I
I
I
TABLE 13-2
Four-bit qua ntiz>ltion (o r the w.weform in Figure 13- 11 .
SAMPLE INTERVAL
2 3
, 5
QUANTIZATION LEVEL
CODE
0
!XXX)
, 5
010 1
7
0 11 1
5
1000 0101
6
,
UIOO
7
6
0 110
8
10
1010
9
" 15
Ill O
'0
111I
II
15
11II
12
15
1111
13
14
11 10
ANAlOG-TO-DIGITAl CONVERSION METHODS
_
751
If the resuhing 4-bil dig ital codes are used 10 reconslructthe orig inal wllveform, you would get the wave form shown in Figure 13- 12. As you can see, the result is much more like the o ri gina l wave form than fo r the case of four qu antization levels in Figure 13- 10. Thi s shows that g reater accuracy is achieved with more quanti zation bits. Most integrated c ircuit AOCs use from 8 to 24 bits, and the sample-and-ho ld function is sometimes contained on the J\DC chip. Seve ral types of ADCs are introduced in the next sect ion. FIGURE 13 - 1 2
Bin;vy yalues
The rt:CQmtrl.lctoo w aveform in
Figure 13- 11 using lixteen quantilation level. (4 bib). The
----------------------/,~~~,.
l I lt 111 0 -- - - - - ---------..,ti _...l __ 1 J 101 - ------------------11100 - - ---- - - - - - - - - - - - .. -4-_ _- ...l " __ ~ .j. t t- 10t t __ ___ ____________ _ -_ _ _ -1 _.....
-+. : +-+--
o rig'fl,)1 ilnillog wOlVCform i! !hewn in
light gray for reference.
~
10 10
lOO !
-- -------------------------·-1 __________
1000
__ ....
OIl! 0 11 0 010 1
---!- -- I
0100
-- t-
0011 ~ 0010 ()(X) I 0000
-
~
REVIEW
t -- ~ -
1
:
--I-- f --f- --
r- --'-- " -- T-- r --
1.-..... - - + - - 1-- - -
---:--{-- t-+--
: r -"- - ' -- T -- r -- I - -1 -- + -- 1- --
- j.
I --t-- ~ - + - ~ -- + -- ~ --
- "l -- T -- r --I- - "l - -T --r- ""l- - "l-- T -- r -- -1 -- "' -- 1- - -1- -1 -- + -- 1- - -1-- -1 -- 1 - t- - J _
.L __ L _ -' __ J __ I 1 1 1 1 1
1 2
i SECTION 13 - 2
. -----1-- r -- ----- ... --~ -- +
1
- - 1-- -
J
4
5
6 17 1
1. What does
L 1
8
~mp ling
_1 ._ .J __ t __ L _. 1 1 1 I
9
10 1 1111 2 1 13 1 1 1
Samplc illlc rv ats
mean?
2. Why must you hold a sampled value? 3_ If the highelt frequency component in an analog signal is 20 kHz, wtlat is the minimum li'Imple frequency? 4. What does quantization mean? 5. What determines the accuracy of the quantization process?
13 -3
ANAlOG - TO - DIGITAL CONVERSION METHODS
As you have seen, 1I11lllog-to-digillll conversion is the process by which an analog quanti ty is converted to digital roml. It is nec~sary when measured quantities must be in digital foml for processing or for display or storage. Some common types of analogto-digitfl l converters (AOCs) flre now examined. Two important AOC parameters are resoilfl ioll , which is the number of bits, and tllll:mghp lI/. which i .~ the sampling rate an ADC can handle in ull i t~ of samples per r.econd (sps). Afier completing this sectio n. you should be able to • Expl ain basically what an ope rational lllnplificr is - Show how the op-amp can be uscd as an inverting amplifier or a comparator _ Explai n how a nash AOC IJ.IOrks • Discuss dual-slo(X': "Des - Describe the operation of a successive-approximation AOC - Describe a delta-sigma "DC . Discuss testing AOCs for a missing code. incorrect code and offset
J
752
•
IN TROD UCTIO N TO DIGITAL SIGNAL PROCESSIN G
A Quick look at an Operational Amplifier Before geu ing inlO analog-la-digital conven ers (ADCs), let's look briefly at an clement Ihat is common 10 most types of AOCs and digital-la-analog converters (DACs)_ Th is e lement is the operational amplifi er. or op-amp for short. 1"h is is an abbreviated coverage of theop-amp. An op-amp is a lincar amplifi er that has two inputs (inverting and noninverting) and one OUipUI. It has a very high voltage gain anti a very high input impedance, as well a <; a very low out put impedance. 1lIe op-amp symbol is shown in Figure 13- 13(a). When usetl as an inverting amplifier, the op-amp is configured as shown in p.."U1 (b). The feedback resiSTOr, RI • and the input resistor. Rj , control the voltage gain accon.ling to the fomlUla in Equation 13- 2, where V,,,,,1V,wis the closetl-loop voltage gain (closed loop refers to the feedback from out put TO input provided by RJ). The negative sign indicates irl\'ersion.
Equation 13- 2
V"", ~ =-Vin
R,.
In the inverting am plifier conliguration, the inverting input of the op-am p is approximately al ground potential (0 V) because feedback and the extremely high open-loop gain make the dilTe rential voltage between the two inputs extremely smull. Since the noninverting input is grounded, the inverting input is at approximately 0 V, which is called l'il111al RIVIIlld. When the op-amp is used as a comparalor, as shovm in Figure 13- 13(c), two voltages are applied to the inpUL.,. When these input voltages diller by a very small amoum, [he opamp is dri ven into one of its two saturated output states, e ither HIGH or LOW, dependi ng on which input voltage is greater.
hl\'Cn;,,!.! lllpu!
I
O tHPUl
~\
~ ~u"IIl'c",ng
(a)
RcprC'l.'nts !hc hi[!"
IIlpu!
Op-nmp symbol
inpm impedance ampliller
lnt~"TTIar
(h)
Or-amp liS
Hn i n\"Crtili g
wilh gnin of
R/ R,
(e)
Op-amp ru; a comparnior
FIGURE 13- 13
The operation»! »mp!ifier (op-amp,.
Flash (SimUltaneous) Analog- to- Digital Converter The flas h methoo utilizes comparators thaI compm-c reference voltages with the ami log input voltage. When the input voltage exceeds the reference vo hage for a given compamtor. a HIGH is generated. Figure 13- 14 shows a 3-bit converter that uses seven comparator circuits; a compamlor is not needed for the all-Os condition. 1\ 4-bit converter of this ' ypc require.., f'i fleen compnrators. In general, 2" - J comparators are req ui red for conversion to an n-bj, binary code. TIle number of bits used in an ADC is its n:solution. The laf£e number of comparators noces.';ary for a re.1LsonabJe-sized binary number is one of thc disadvantages of the nash AV e. liS chief advantage is that it provides a fast conversion lime beC
ANALOG-TO-OIGITAL CO NVERSION METHOOS
+VREf
•
753
Opo-urnp compa!llu .....
R
+/ 1/
Input frnm '
antl·ool
Priurit)
T
R
c,,,~..Jn
7
i
R
6 5 I J - - l)u'1 Pnr.llld 2 1 - D, ~ bi,);,!)
4
f
3
4 -
2
R
T i
R
R
-
I),
output
C- I
11'°
EN
i
Enahk pul .......
R
FIGURE 13 - 14
A 3-bit fl310 ADC.
The frequency of the enable pulses and the number of bits in the binllry codc determine the accuracy wi th which the sequence of binary codes represents the input of the ADC. There should be one enable pulse for each sampled level of the input signa!.
Determine the binary code output of [he 3-bit flash ADC in Figure [3- 14 for the input signal in Figure 13- 15 and the encoder enable pulses shown. For Ihis example, VRIOF = +8 V. '" FIGURE 13 - 15
s..mpling of vi)l u~ on a wJVeform for conversion to binary ccxle.
v
, 7
6 Analog 5 input 4 \'olla)..~ 3 2 I
1
n r
~j T " ' I
:0. +
'
I
L
J
4
, I
5
r, f-'lt--:
~~ t i '-!---i,' . •, '' -r+ :I: l , I T:
,
I
I
,, , i . , , y ,, , , 2
I
[rE.\ T: It
,'M ,l-r, + , , r+- ,, , I ~~ . , -J
r
il
I
6
I
,
1
8
9
10
II
-;:--r , . ~ r1
tt ,
i~ 12
754
•
INTRODUCTION TO DIGITAL SIGNAL PROCESSING
Solution
The resulting J igilnl output sequence is listed as follows and shown in the wHvefoml rJiH);fHl ll ur Figurt: 13- 16 in Idatiun \(1 ti lt: emlble pul"e., ; 100. 110. III. 110. 100.010.000.00 1. Oil. 101. 11 0. III 2
3
4
5
6
, ,
7
IJ
JO
12
Enable pulses
0,
,,
-t- -!
,,
I
I
I
I
~ ~~~~~+-~ i ~,~~-~ , , I I I I I I I I I I 1 100 I 110 1 11 1 I II O l lOU I nlO l CIIWl l tkl l 1(1 11 1 10 1 1 110 1 11 1
FIGURE 13 - 16 ~ Itjng digit3' outputs
Related Problem·
for ~mp'C-3nd-ho ld v.J'ues. Output D~ is the 15B of the 3-bit. bin ...!), code.
If the ellable pulse fre(IUency in Figu re 13- 15 well! hal ved. detenlline the binary numbers represented by lhe resulting digital Olllput sequence for 6 pulses. h any informat ion lost? - Answer.; arc at the end of the chapter.
Dual-Slope Analog-to- Digital Converter A dual-slope AOC is common in d igilal voltmeters and other types of measurement instrumellls. /I, ramp gencralOr (imegr.tlor) is used to producl: the dual-slope characteristic. /I, block diagram o f a dual-slope ADC is shown in Figure 13- 17. FIGUR£ 13- f7
AIl~log
e
inpul cVIo J
e LK
c
+
Countl"f
-=
h ~egralOl"
(ram p gc ncr:1I(1)
_
"
Comparmor
CU A K
Swilch ooilirol
Conlrol
L_~''''~i'~.
_J--iEN I»
,
()~ D j I)~ /) , D! D, Drl ~
/3 ,"",)
("Ir
Brn
OUlpul
ANALOG-TO -DI GITAl CONVERSION METHODS
•
Figure 13- 18 illustrates dual-s lope conver.;ion. Stru1 by a.~su mi ng thai the counte r is reset and Ihe output of the integrdtor is zero. Now assu me that a positive in put voltage is applied to the input through Ihe swilch (SW) ell. selected by the control logic. S ince the
•
I'
,
f
sw R
I
'~ -
.nv ;> 1n ~~Ir: '
I
~'
I iAeti ink.,....·a l
'"
~
,," '-'lI.Ir'·
,,",hI< '''I1.lf'~
CI(
IbY
H1GH
1
Sl_flI L J l..n
c Coun ts lip 10 1/ and thell resets
R
" j
Y" i,hl<
, t
-v ___ _
~
C(lnlro) logic
llllchcs
EN
, (a) FiltCd·inlcn'al. nc~ati\'C'l!oing mmp (while tile coonter cOI."llS up 10 II )
c
I
SI~
II , ~,
I '"
nvI')
~) HIr.H
cr 1
.fl..fl..fl
fl
c Coumer
R
rt..,..,t
" Sl. Contini logic
Lah;m's
EN I
I
I
I
I
I
I
I
(b) End o f tl xcd-intenll' when the L"Oll iH Cr sends II pulse to cuntRll lugic 10 .wilCh SW 1<) the - VR r-F inpu t
".
I
' II
I
V
R
11 101
ClK
'OY,f""'~
/ I> _:V""",~ .
\uri,tbk
1.. Il
_SU"l.......-.. C
I"n~
ramp
" j
Control 10~k
..
, \ Vh•.m l hc rnmp ' ope po:. ili" e- "'<>ill g r~1tl p while the CV\l 111crOOU1l1. upugulIl. rcacm-s n v . the eou,'ler slops. ;u1<1 (he coumcr oolplll is loaded imo lalche.,;.
Fi~e(hl
FIGURE 13 - 18
Illustration of dUOl I-dopc convcnion.
j
.
Count loatIcd hllo latches
Sl. (c)
Coun ts up unt il r.lmp equals zero
R
EN I
I
I
I
I
,
755
756
•
INTRODU CTI O N TO DIGITAL SIGNAL PROCESSING
inverting input of A I is aI vinual ground, and assuming that V.. ;s constant for a period of ti me, there will be constant currcnt through the input resistor R and therefore throug h the capacitor C. Capacitor C will charge linearly beCause the current is constant, and as a result, there will be a negative-going linear voltage ramp on the output of A I' as illustmtcd in Figure 13- 18(a). When the counler rcache.~ a specified count, il will be resel, and Ihe control logic will switch the negative reference voltage ( - VREF) to the input of A I' as shown in Figure 13- 18(b). At this po;m the capacitor is charged to a negative voltage (- V) proponional to the inpm analog VOltage. Now the cHp..citor dischal1;es linearly bec.. usc of the constan t current from the - VREI" a..; shown in Figure 13- IM(c). This linear discharge proouces a positi\'e-going ramp on the A I output. starting Ht - Vand having a consWnt slope that is independent of the charge voltage. As the capacitor discharges. the counter advances from its RESET Slate. The time il takes the capacitor to di~harge to zero depends on the initial voltage - V (proportiomll to VI,,) because the discharge mte (slope) is constant. When the integrator (A I) output voltage reaches zero. the eompamtor (A 2) switches to the LOW swte .md disables the clock to the counter. The binary count is latched. thus completing one conversion cycle. The binary count is proponiomll to Vi~ because the time it takes the capacitor to discharge depends o nly on - V. and the counter records this interval of time.
Successive-Approximation Analog-to-Digibl Converter One of the 1I10St widely used methods of analog-to-digital conversion is successiveap proximation. It has a much faster convcrsion ti me than the dual-slope conversion. but it is slower than the flash method. It also has a fixed conversion lime that is the same for any value ofthc analog input. Fi gure 13-19 shows a basic block diagram of a 4-bit "uccessive ap proximati on ADC. 11 consists of a OAC (DACs are covered in Section 13-5), a successive-approx imation register (SAR). and a comparator. The ba.~il.: operation is as fo llows : The input bits of thc DAC arc enabled (made equa l to a I ) one at a time. starting with Ihe most signi ficant bit (MSR). As each bit is enabled, the comparator produces an output that indicates whether the input signal voltage is greater or less than the output of the DAC. If the DAC output i:. grc
Di!!itat-to-lIllalog
1',..,
COIl\"cr\cr
WAC)
1
"'} Il,
Il~
+
I MS B,
rL.,) 1j 1
0 SAO Cl I( -
Su«ellive-Clpprox,mCltion ADC.
output
D,
ComparnlOl"
FIGURE 13- "
P;lr:,lld hm.ar'l
I>c
t---
Serial I>in~ (lUt put
ANALOG-TO-OIGITAL CONVERSION METHOOS
the nex t, and so on . After all the bits o f the DAC have been tried, the cunversion cycle is complete. In order to better understand the opcmtion of the successive-approximation AOC. let's take a specifie example of a 4-bit conversion. Figure 13--20 il lustrates the step-by-step conversion of 1:1 constant input voltage (5. 1 V in this case). Let's assume that the DAC has the foll owing output chamcteristic: V_, == 8 V for the 2.1 bit (MSB), V"", = 4 V fo r the 2~ bi!. V..., = 2 V for the 21 bit. llnd Vow = 1 V for Ihe 24) bit (LSB).
D'C
D'C 2' 0
+5. 1 V
2'
2' t' 0 0
+5.t v - ---IV
- ---,;v I
SL o---~4l-"-L"~
".
SAR
~p
(a) MSB lrial
.,v +5.1 V
- -,:v
u
"
~
SL o-----Lf.l~4l-QJ
+5. t V -
-Iv
SAR
K<:<'p
He"':l (c) 2 1 -billri~ 1
(d) U iB Inal (conversKm comptete)
FIGURE 13-20
IIIvltration of the Ivcce"ive-approximation convenjon procell.
Figure 13-20(a) shows the fi rst step in the conversion cycle with the MSB = I. The output of the DAC is H V. Since this i.~ greater than the input o f 5. 1 V. the output of the comparator is LOW, causing the MSB in the SAR to be reset 10 a O. Figure 13-20(b) shov..s the second step in the conversion cycle with the 22 bit cqualto a I. The output of the OAC is 4 V. Since this is less than the input of 5.1 V. the OUlpUt of the comparmor switches to a HIGH, causing this bit to be retained in the SAR. Figure 13- 20(c) shows the third step in the convcrs ion cycle with the 21 bit equal to a I. The output of the DAC is 6 V because the re is a 1 on the 22 bit input and on thc 21 bi t input; 4 V + 2 V = 6 V Since thi s is £rcatcr than the input or 5. 1 V.the output ofthc comparator switches to a WW, causi n£ lhis bit to be resct to a O. Figure 13- 20(d) shows the fourth and final step in thc convcrsion cycle with thc 2° bit equal to a I. Thc output of Ihe DAC is 5 V because there is a 1 on the 21 bit input and on the 'flbil inpul;4 V + I V = 5 V. The four bi ts have all been tried. thus completing the convcrsion cycle. At thi s point the binary code in thc re~is ler is 0 10 1, which is approximately the binary valuc of lhe inpu l o f 5. 1 V. Additional bits will produce an c"en more accurate result . Another conversion cyc1c now bcs ins, and Ihc ba...ic process is repclltcd. The SAR is cleared at thc be£ inning of each cycle.
•
757
758
•
INTRODUCTION TO DI G ITAL SIGNAL PROCESS ING
THE ADC0804 ANAlOG-TO-DIGITAl CONVERTER The ADC0804 is an example of a successive-approximation ADC. A block diagram is shown in Figure 13-2 1. Thi s device opcmtes from a + 5 V supply and has a resolution of eight bits with a conversion time o f 100 IJS. Also. it has an on-chip clock generalor. The data outputs are Irist1lle, so they can be interfaced with a microprocC!>sor bus system . .. FI GURE 13 - 21
The ADC0804
analog-to-digitlll
( 20)
co~rter.
cs RD lV.
CLK tN .... ~.,~ { lnpul
Vio. V",_
REFn
(Il
(5)
(2)
(1 9)
(3) (4)
(6) (7)
(0)
v V V
V V
V V
V
( III)
(17)
( 16) (15)
INTR
cue R (00.1t) 1)11
D, I~
(i"4") 1)3 D, (13) D, (1 2) D, ( II)
Digital tl;)la
output
n,
( 10)
ANLG DGTL GND GNP The basic opemtion o f the device is as follow s: T he ADC0804 contains the equivalent of a 256-resislOr DAC network. TIle successive-approximation [ogie sequences the nelwork to match the analog d ifferen lia[ inpul voltage (V,M - V,-,._) wilh an output from the resistive network. The MSB is tested fi rst. After eight comparisons (sixty-four clock periods), an 8-bil bintlry code is tmnsferrcd 10 output latches, and the interrupt (lNfR ) output goes LOW. The device can be opcmted in a free-running mode by connecting the INTR output to the write (WR) inpul tlnd holding the conversion !Otart (CS) Law. To ensure startup under all conditions, a LOW \vR input is requi red du ri ng the power-up cycle. Taking CS low anytime aftcr that will inteffiJpt the conversion process. Whcn the IVR input goes LOW, the internal suc~sive~rox i mation rcgister (SAR) and the 8-bit shin registcr arc reset. As [ong as both CS and \VR rcmain LOW. the ADC remains in a RESEr stale. Convcrsion stal1.<; one to cight clock periods aftcr CS or IVR makc.~ a LOW-Io-HIGH transition. When 11 LOW is at both Ihe CS and RD inputs, the tri .~tate output [ateh is enabled and the output cooe is applied to the Do- D 7 lines. When cithcr the CS or the RD input returns to a HIGH. the Du- D7 outputs are disabled.
Sigma-Delta Analog-to-Digital Converter Sigma-delta is a widely used method of analog-to-digita[ conversion, particu[arly in telecommunications using audio signals. TI1C method is based on delta modulation where .he differcnce between two successive samples (increase ordocreasc) is quantized: other AOC methods were based on the absolute value of tl samplc. De[la mooultllion is a I-bit quantiw lion method. The output of a del la modulator is a single-bit data siream where the relativc number of Is and Os indicatcs the level or mn plitude of the input signal. The nu mbcrof Is over a given number of clock I.:yde.~ eSTablishes Ihe signal amplitude during that interval. A max imum number of Is cOlTe.~ponds to the maximum positive input voltage. A number of I s equal to one-half lhe maximum cOlTesponds 10 an input voltage of zero. No Is (all Os) corresponds
ANAlOG -TO-DfGITAl CONVERS ION METHODS
•
759
to the maximum negati\'e inpuf voifage. This is illuslmled in a si mplified wily in Fi£urc 13- 22. For example. a~sume that 4096 Is occurdurin£ the interval when Ihe input signal b a positive maximum . Since zero is Ihe midpoint of Ihe dynamic r.ln£c of the input signa l. 2048 I s occur during Ihe interval when Ihe input signal is zero. There arc no I s d uring the interval when the input signal is II negative maximum. f'Or signal levels in between, Ihe number o f I s is proportional to the level. FIGURE 13 - 22
+MAX
A simplified
ilJu~tion
del~ analog-to--digi~ 1
o f ligmaconversion.
The Sigma-Delta ADC Functional Block Diagram The basic block diagram in Figure 13- 23 accomplishes the conversio n illuslrated in Figure 13- 22. The analog input signal and the analog signlll from Ihecon\'ened quantized bit stream from the DAC in the feedback loop are applied to the summation p:) point. The difference It!.) signal out o f the :E is integmtcd. and the I-bit ADC increases or decreases the number of Is depending on the difference signal. 111is action attempts to keep the quantized signal that is fed back cquill to the incoming analog signal. The I-bit quantizcr is essentially a cOl11p<1mtor followed by a latch.
.
FIGURE 13- 23
Summina
point Anlllq; input
+
r
- ;-'
sigll~1
•
Integrator
-
Quantized output is /I si ngl~ bit dm a stream.
I-bit quantizer
Partial functional block diagram of a ligrna-delta ADC.
DAC
To complete Ihe sigma-dcJ tll conversion process using one particu lar ap proach, the single bit data stream is converted to a series of binary codes, as shown in Figure 13- 24. The counter counts Ihe Is in the quantized data strcmn for successive intervals. The code in Ihe
Att~log
.LIlpul
signal
-
Summing poi nt
+
,
- ';.;
Integrator
r--I-bil
DAC
fiGURE 13 - 24
One type o f $;grna-deltil ADC.
I -bit qUillllizer
'--
II- bil L"tlllnlCf
Lmch
-
l3in"ry oode 11lItpul
760
•
INTRODUCTI ON TO DIGITAL SIGNAL PROCESSING
counter then represents the amplitude of the an
Testing Analog-to-Digital Converters One method for te.<;ting ADCs is shown in Figure 13- 25. A DAC is used as part of the test setup to convelt the AOC output back tu iUlalog form for compa ri ~n with the lest input. A te."t input in the form of a li near ramp is applied to the input of the ADC. The resulting binary output sequence is thcn "pplicd to the DAC tCSt unit and convcned to a stairstcp ramp. The input and OUtput ram ps arc compared for any deviation.
AJWtO),! mpUl Bmarv
r~mp
Ramp SOlJrce
'>--
ADC
DAC
~'.ld.!
~: ---'---,
,
FIGURE 13 - 25
A method ror t~ting ADCs.
Analog- to- Digital Conversion Errors Again, a 4-bit cOllvefl-ion is used to illustrate the principles. Let's assume that the test input is an ideal linear nllllp.
Mwing Code The stairstep OUlpUl in Figure 13- 26(a) indicate... that the binary code 100 1 docs not appear on the output of the AOC. Notice that the 1000 valuc stays for two intervals and then the output jumps to the 10 10 value.
, r: +'1 ,, i'iH t " "
" ,",
13 W
9 8 7 6
, i=! H , ,-I, ,
, , '-W , 4
1
o
,
r
.
-
+
.L ,
c
Fh:tL_j~ illt -
0
_
__
-
§ ~ !x 80 ~~ Q8 :s g = ~e
ce !l~ oc 5c ::: _ '::: _ = = =::
(b ) r ,,<~lfTCC' codc.'S
(groe ll )
FIGURE 13- Z6
Illustrations o f an
I ,
-'
----:.....-
_ _ 0<::<:::=> _______ _ O~~§S~ = §S~3~2~= (e)
Off.
ANALOG -TO-DIGITAL CONVERS ION METHODS
•
In a nash ADC, for cxample, a fa ilu rc of onc of thc op-amp comparators can causc a missing-codc error. Incorrect CodeJ The stairstcp output in Figure 13- 26(b) indicatcs that sevcral of thc bi1 nUT}" codc words coming out ofthc ADC arc incorrect. Analysis indicatcs that thc 2 _bit linc is stuck in thc LOW (0) statc in this particularcasc.
Offset conditions are shown in 1J- 26(c). In this situation thc AIX intcrprets the analog input voltagc a~ grcatcr than its actual value.
Offse t
I
EXAMPLE 13 - 2
A 4-bit nash ADC is shown in Figurc 13-27(a). It is tcsted with a setup like thc onc in Figure 13-25 . The rcsu lting reconstructed analog output is shown in Figure J3- 27(b). Identify the problem and the most probable fuu lt.
15
14
1--
2 4
8
15 14 13
,
H
12
'"",9 ,~
7
" 5
I
1
I
tT
",
I :
4
3 2
(,j
r
(bj
... FIGURE 13-21
Solution
Related P,oblsm
The binary code 00 1 r is missi ng from thc ADC OLltput, as indicated by the missing step. Most likely, the output of comparator 3 is stuck in its inactive state (LOW). Reconstruct the analog output in a lest setup like in Figure 13- 25 if the ADC in Figure 13-27(a) has comparator 8 stuck ill the HIGH output slatc.
761
762
•
INTRODUCTION TO DIGITAL SIGNAL PROCESS ING
I
SECTION 13-3 REVIEW
1. What is the fastest method of a narog-to-digital conversion? 2. Which analog-to-digitill conversion method produce! a!ingle-bitdata !tream? 3. Doe! the successive-approximation converter have a fixed conversion time?
4. Name two types of output errors in anADC.
13-4
THE DIGITAL SIGNAL PROCESSOR (DSP) Esscnlially, a digital si!,!nal processor (OSP) is a special type of microprocessor that processcs, data in reallimc. Its applications focus on thc processing of digital data that represcnts analog signals. A DSP, likc a microproccssor, has a ccntral processing unit (CPU) and mcmory units in addition to many interfacing functions. Evcry timc you use your cel llliar tcicphone. YOllarc using a OSI>, and this is only onc example of ils many applications. Aftcr complcting this chapter, you should be able 10 • Explain the basic concept<; of a DSP • List some of the applications of DSPs • Describe the basic functions of a OSP in a ccll phone . Discuss the T MS32OC6000 series DSP
The digital signal processor (OSP) is the heart of a digilal signal processing system. It takes ils input from an ADC and pnxluccs an output that goes to a OAC. as shown in Figure 13-28. As you have learned, the ADC changes an analog waveform intod
Dig.il aJ IIlPU\ fn" n I\OC
The D5P hcI.
ADC
DiJ,'nalmllllUl \"DAC
DSP
L
DAC
Anal()~
-
"utput
DSP Programming OSPs are typically programmed in either a~sembl y language or in C. Becau~e programs written in assembly language can usual ly execute faster and because speed is crilical in mOSt OS!' applications, i:Issembly hmguage is used mllch mure in OSPs than in general. purpose microprocessors. Also. OSP progmms arc usually much shorter than tmditional microprocessor programs because of their \'cry specialized applications wherc much redundancy is used. In general, thc instruction sets for DSPs tend to be smaller than for microprocessors.
DSP Applications The OSP, un like the general-pl1lJlose microprocessor. must typically process data in real that is, as it happens. Many applications in which DSPs are used Call11ot tolerate any no!i ~eablc dclllYS, requiring the OSP 10 be extremely fast. In addition to cell phones, digital Signal p.roces~ors (O.S~) are used in multimedia computers, video recorders, CD playcrs, ~ ard disk drives. digital r~dio modems. and OIher applicarions to improve !he signal quality. Also, DSPs are becomrng more common in television applications. ,illl(';
THE DIGITAL SI GNA L PROCESSOR (D SP)
An important application of DSPs is in signal compression and decompression. In CD systems. for example. the music on the CD is in a compressed foml so that it does n't use as much storage space. It must be decompressed in order to be reproduced. Also signal compression is used in cell phones to allow a greater number of calls to be handled .~ i l11Ultanc ously in a local cell . Somc other areas where it h a.~ had a major impact arc as follows. Telecommunicatioru The field of telecommunications invoh 'cs trd nsferring all types of information from one location toanOlher, including tciephonecon\·ersations. television sigImls, and digital chl"l. Among other funct ions, the DSP faci litates mUh ipJcxing many signals 0 1110 one transmission channel because infonnation in dif:!ital form is l'datively easy to mUltiplex and demultiplex. At the transmitti ng end of a telecommunications system, DSPs are used 10 compress digitized voice signals for conservation of b.1.ndwidth. Compression is the process of reducing the data nlte. Gener-dly, a voice signal is convened to digital fonll at 8()(X) samples per second (sps), based on a Nyquist fTC
•
763
Sound u .dJ; u,ed in computer! use ,m AOC to convert lOund from a microphone, audio CD player, or other
I
764
•
INTRODUCTION TO DIG ITAL SIGNAL PROCESSING
section o flhc body from many directions. The resulting signals arc converted 10 digital foml and stored. This stored information is used to produce calculated imagc~ that appear to be sl ices through the human body that show great detail and permit bettcr diagnosis. Instead of X- ray~, MRI uses magnetic fields in conjunction with mdio waves 10 probe inside the human body. MRJ produces image~, ju~t as cr, and provides excellent discrimination between different types of tissue a<; well as infOlTIlation such as blood now through Mcries. MRJ depends entirely OIl digital signal processing methods. In applications such as video telephones. digital te levi~ion, and other media thaI provide moving piclures, the DSP uses image compression to reduce the number of bi ts needed. making these systems w mmercially feasible. Filtering DSPs are commonly uscd to implement digita l fil ters for the purposes of sepamting signals th'll h.we been combined with othcr signals or with intcrfcrenceand noise and for rcstoring signals thai arc distorted. Although analog fillcrs arc quite adequate for some applications, the digital filter i ~ generally much superior in terms of the perfonnance that can be 'lehicved. One dmwback to digital filters is that the execute ti me required produces a delay from the lime the analog signal is applied until the time the oulpul appears. Analog filters present no delay problems because as soon as the input occurs, the response appears on the output. Analog filters arc also less expensive than digit'll filters. Regardless of this. the overall perfonmmce of the digital filter is far superior in many applications.
The DSP in a Cellular Telephone The digital cellular telephone is an example of how a DSPcan be used. Figure 13-29 shows a simplified block diagmm of a digital cel l phone. The voice t:odcc (codet: is the abbreviation for coder/decoder) conta i n~. among other functions. the ADC and DAC net:cssal)' to convert between the analog voice signal and a digital voice form'l!' Sigma-delta conversion is typically used in most cell phone applications. For tmnsmis...ion, the voice signal from the microphone is convcn ed to digilUl form by the ADC in the codet: and Ihen it goes to the DSP ror proct:~~i ng. Frum the DSP, the d igilal signal goes 10 the rf (radio frequency) scction where it is modulated and chunged to thc radio frequency for tmnsmission . An incoming rfsignal containing voice data is picked up by the antenna, demodulated, and changed to a digital signal. 11 is Ihe n applied to the DSP for processing. after which the digital signal goes to the eruee for conversion back to the original voice signal by the DAC. It is then amplified and applied to the speaker.
A""J~
Cod~
Microphoot
0-
Ampl ifier
-
Fitl;,r
-
AD('
RFsection ( mndulauOl1
Clr-
tloemodut:mon.
DS"
frequellC) L"On\"('r.;iol1,
Amplifier - -
Filler
-
rt"amptilicr)
DAC
Speake.·
1
I
Control
FIGURE 13 - 29 Simplified block diagram of a digital cellular phone.
THE DI GI TAL SIGNAL PROCESSOR (D SP )
•
In a cellular phone application, the OSP performs many func tions to improve and facilitate the reception and Imnsmission of a voice signal. Some of these DSP functions arc as follows:
Functions Performed by th e DSP
Speech compression. TIle rate urt he digital voice signal is reduced si2nificanlly for transmission in order to meet the bandwidth requirements.
Speech decompreS!iion.
The rate of the received digital voice signa l is returner.! its original rate in order to properly reproduce Ihe analog voice signal.
10
Protocol hmullillg. The cel l phone commun icates with Ihe nearest base in order 10 establish the location oflhe l.."C1l phone, allocales lime and frequency slots, and arranges handover 10 another base station as the phone moves into another cell. En Dr detectiOIl (llId correction During trilllsmission, elTor detection ,md correction codes are generatcJ and, during reception, detect and correct enoTs induced in the rf channel by noise or interference. Encryption Converts Ihe digital voice signal to a form for secure transmission and conve11s it back to original form during reception.
Basic DSP Architecture As mentioned before, a OSP is basically a speciali zed microprocessor optimized for speed in order to process data in real time. Many OSPs arc based on whal is known as the Har\leild architecture, which consists of a central processing uilil (CPU) and two memories, one for data and the other for the program, as shown by Ihe block diagram in Figure 13- 30. FIGURE 11-30
[}',ltll
memor),
Many DSPI Uie the Harvard architecl1Jre (two memories'.
CPU Tnsuuction bus
Specific DSPs-The TMS320C6000 Series OSPs arc manufactured by several companies including Texas InSlru mellls. Motorola. and Analog Deviccs. DSPs are available for both fixed-point and floating-poinT processi ng. Recall From Chapter 2 that these two methods differ in the way numbers arc stored and manipulated. All noating-point DSPs can also hand le numbers in fixoo-point format. Fixed-point OSPs arc less expensive than the floati ng-point versions and, generally, can opcraie faSler. T he deta ils of OSP architecture can vary significantly, even within the same fam ily. Let's look briefly at one particu lar DSP series as an example o f how a OSP is gcnemily organized . Examples of DSPs avai lllblc in the T MS32OC6000 series include the TMS32OC62xx, the TMS32OC64xx, and IheTMS32OC67x.x. which arc part ufTexas Instrument's TMS320 family of devices. A genel1ll block diagram for these devices is shown in pigure 13- 3 I. The OSPs have a cenlml processing unit (CPU), also known a~ the DSP core, thai conTains 64 general-purpose 32-bit registers in thc C64x.x and 31 general-purpose 32-bi( registers in the C62xx and Ihe C67xx. The C67xx can handle floating -point opemtions, whereas the C62xx and C64xx arc lixed-point devices. Eaeh OSP has eighT func tiunal units th:1I contai n IWO 16-bit multipliers and six. arithmetic logic units (ALUs). The perfOrmance of lhe three OSPs in the C6000 series in lerms
765
76 6
•
INTRO DUCTI O N TO DI GITAL SIGNAL P ROCESSING
Progrnm cache/progrnm memory (32-bit address, 256-bit d:.uaJ
CPU (DSP CIIJ'e) Prugr.ml fC1<:h Comml
Illstruction
rcg'~ 'crs
di ~lXm:h
Instruct iol'l de~"Ode
DMA EM IF
Data pmh A
Col'llml logic
Data pmh B
Test
.LI
.s!
.02 .M2 .S2 .L2
.M I .01
DHta (:ar he/dara memory en-bit addre., s. R-. 16-,32-. (-.4-bil dala)
Adt!iUOl'Ill]
periphcl"l,ls
FIGURE 1 ] - ] 1
Gener,,! block d;"gr
of MiPS (M ill ion hlsrJuction$ Per Second), MFLQPS (Mi llion Floaring-po int Operations Per Second), and M!\1ACS (Mill ion Multiply/Accumulates per Second ) is shown in Table 13-3.
TABLE 1 ]
]
TMS320C6000 series DSP dab procelling performance.
DSP
TYPE
APPLICATION
I
PROCESSING SPEED
MULTIPLY / ACCUMULATE SPEED
C62xx
FixeJ-poinl
Gcncrn l-pu rpose
12(1)..2400 MI PS
300--600 MMACS
C64u
Fixed-poim
Spedal-purposc
3200-4800 MIPS
16(X)"2400 M M ACS
C67xx
FIOOling-point
Genernl-purpose
600- 1000 MFLOPS
200-333 MMACS
Data Patlu in the CPU In the CPU, lhe progmm reich, instl1.lclion dispatc h, and instl1!Ction decode scc li o n.~ can provide eight 32-bit instruclions ro the fu nctional units during every clock cycle. T he CPU is splil into two dala paths, and in~t ru cr i on prvcessing occurs in both data paths A and B. Each data path colllains half of (he general-purpose registers ( 16 in the C62xx and C67xx or 32 in the C64xx) and four fUllctional uniL". 1llc cont rol rcgisler and logic arc used 10 config ure and controllhe various processor operations.
fun ctional UnitJ Eaeh dma pmh has four runclional units. 1llc M units (Iabeled .M I and .~2 in ~ig ure .13-3 r ) ar:c dedicated multipl iers. TIle L lin its (1;:lbclcd .Ll and .L2) perfolm anthmetlc, logIC, and InlSCe/J ancoliS opcmtions. 1llc S lInits (labeled .S I and .S2) perform
THE DIG ITAL SIGNAL PROCESSOR (DSP)
•
767
compare, I';hirt, and miscellancous arithmctic opcratiOl\I';. Thc 0 unit!; (labeled .01 and .02) perform load, storc, and m iscellaneous operations. A pipelinc allows multiple instruction s to be processed simultaneously. A pipelinc operation consists of th ree stages through which all instructions now: f elch, deCOlle, exeCl/le. Eight instructions at a time arc !irst fetched from thc program mc mory: they are then decoded. and fin ally they are cxccutcd. During retch, the eight instructions (called a packet) are taken from memory in four phases, as shown in Figure 13-32. Pipelille
Progmm (uk/ress gcnemle (PC). Pmgmm lll/dress sena (PS). Progmm lIcces.~
relll~\,
T he progmm addres.s is generated by the CPU.
The program address is scnt to the memory.
wait (PlY).
A memory read operation occurs.
PmKl"lIIIIfetch packet receive (PR).
The CPU receives the packet of ins tructions. FIGURE 1 ] - 12
Prngnlln
addl"Cl;. gCllCmlC
(PG)
-
Progr,m address send
Progr.l.m
Progrolm
fclch receivc
OCCCl;.S
ready
WIIil
operiltion.
packet
(PW)
(1'5)
The Iovr fetch phalCS of the pipeline
(PR)
Two phases make up the instructio n decodc stage of pipeline operation, as shown in Fig ure 13- 33. The instruction dispatch (DP) pha.."l! is where the instruction packets are split into execute packcb and .Issigned to the appro pria te ftlnction al unit.~. The instruction del."Ode (DC) phase is where the instructio ns are decoded. FtGURE 13 - 3]
The two deaxle philses of the pipeline oper.ltion.
Dispatch (DP)
TIle e~ecutc stage of the pipeline operation is where the instructions from the decode stage are carried OUI . The execute stage has a maximuITI of fi ve phases (E I through E5), as shown in Figure [3- 34. All instruc tions do not use all five phases. The number of phases used d uring e Kccution depe nds on the type of instruction. Pan o f the eKccution o f an instructio n requircs getting da ta from the data memory. FIGURE 13 - 34
OJ
The flYe execvtc pha'leS of pipeline -
E2
-
El
-
FA
-
r;..5
As you can sec in f'igure 13-3 1. thcrc arc two imemal memories, one for data and olle for program. The program memory is organized ill 256 bit pxkets (eight 32-bit ins(I"\I<.1:ions) and th<....-e are 64 kB of capaci ty. The data memory also has aeapadty of 64 kB and can be aecessed in 8-, 16-. 32-, or 64-bit WQfd lengths, dependi ng on the specific deviL"C in the series. Both intel11al memories .Ire a<."CCSSCd with a 32-bit address. 'The OMA (DireL1 Memory Access) is used to transfer data without going through the CPU. 1lte EMIF (ExtemaI Memory Interface) is used to suppon extemal mellwrics when required in an applicalion. Additional illler/ace is provided for scrial l/O pons and other extenml devices. Internal DSP Memory and 1,lterfacef
Timen There arc two general-purpose timers in the DSP thatean be used for timcd events, coullting, pulse geneflllion. CPU interrupts, and more.
operation.
768
•
INTRODUCTION TO DIG ITAL SIGNAL PROCESSING
Packaging These particula r processors are availabk in 352-pin ball grid arm y (BGA) pockages. as shown in Figure 13- 35, and are implememed with CMOS technolo£y. AI'
00 0000 0 00 0 0 00 0 000000000 00 0 00 0 0000 00 0 0 0000000 00 0000 0 0 0 0 0 00000 000 0 00 0 00 0 0 0 0 00 0 00 00000 0 00 000 00 00000 0000 000 0 0 000 0000 0000 0000 0000 0 000 000 0 0000 000 0 0 000 0 00 0 00 00 00 0 0 0000 00 00 0 0 00
" Ii
,,0 ~:
li B I\lI.
v
"'
v
u
T H
gg gg
~
L ..: i H G F
f. (>
C B A indic~lC$
i
pinA l (a ) Top view
)5J
9
2.68
(b)
L
gggg
0 00 0 0000 00 00 00 0 0 00 00 0 000 000 0 0000 0000 0 000 0000 0000 000 0 0000 0 00 0 0 0 00 0 0000000 00 00 00 000 0 0 0 0 0 0 0 00 0 0 0000000000 0 00 0 00 000 00 0 00 0 0 000000 00 00000000 00 0000 0 0 0 0 000 0 000 0000 0 000 0 0 0 00000 0
M
BoIIOIII
i1llj5
11l1!
I'
iJ
19
~i2.J~
i6Ialf)Z!:!-I1f>
view
j
i ~b QQ QU UU UUb06UbOUUUQUObUOU
(e) Side "iew
FIGURE 1 3 - 3 5
A 352-pin BGA pilckoge.
I
SECTION 13 - 4 REVIEW
1. What is meant by the Harvard architecture?
2. What is a DSP core? 3. Name two categories of 0511 according to the type of numbeo handled. 4. What are the two type1; of internal memory?
5. Define (a) MIPS
(b) MFLOPS
(c) MMACS.
6. Basically, what does pipelining accomplilh? 7. Name the three stages of pipeline operation. 8. What happens during the fetch phase?
13-5
DIGITAl- TO-ANAlOG CONVERSION METHODS Digital-to-analog conversion is an imponal1l part of the digital processing system. Once the digital data have been proce!isc d by the DSP. they
DIGITA l -TO- ANAlOG CONVERS ION M ETHO DS
•
769
Binary-Wcightcd- Input Digital- to-Analog Conve rter One method of digital-to-analog conversion uses a resistor net wo rk with resistance values Ihilt represent the bimll}' weights of the input bits of the d ig ital code. Figure 1 3~36 shows a 4-bit DAC o f thi s type. Each of the input resistors will either have c urrent or have no current, de pending on the input voltage level. 1f the input voltage is zero (binary 0). thec urrcnt is also zero. If the input voltage is HIGH (binary I). the amoun t of CUlTent depends on the input resistor value and is different for each input resistor, as indicated in the ligure.
I' I n= IlJl I'
11= -1R I'
I! : 211
V
I ,"" R
2'
I'
V
4R
2' V
\~ ...
8'
2.
'" I,
FIGURE 1 ] - ]6
= I, R,
~ I,
1: 0
2'
A 4-bit DAC with binary-weighted inpvb.
- 0 1"",
+
V
"
R
I,
I,
Since the re is pmct ically no CUlient into the op-amp inverting (- ) input, ull of the input c urrents sum together and go through Rf . Since the inverting input is at OV (virtual ground ). the drop ac ross /~ is equal to the output voltage, so V",,, = If Rf . 'l11e values of the input resistors are chosen to be inversely propOit ional to the binary weights of the cOITe!;ponding input bib . T he lowest-value resistor (N) curresponds to the highcst binary-weighted input (2-1 ) . T he other resistors are multiples o r R (that is. 2R, 4R, and 8R) and correspond to the binmy weights 2 2, 2 1, and 2°, respectively. The input curren ts arc ah o proportional to the binary weights. Thus, the output voltage is proportional to the sum of the binary weights because the sum of the inpl1t CUtTents is through RI . Disadllantages of thi s type of DAC arc thc numbe r of d ifferent resistor values and the fact that the voltage levels lIlust be exactly the same for all inpu ts. For example, an 8-bit converter rC(lui rcs cight resistors, rang ing rrom some value or R to 128R in binary-we ighted steps. T his ra nge o f resistors req ui res toleran(;es of one pari in 255 (less than 0.5% ) to accuratel y convert the input, maki ng th i .~ type of DAC very difficult to mass- produce.
Determine the out put or the DAC in Figure 13-37(a) if the wave forms representing a sequence of 4-bit numbers in Figure 13-37(b) are applied to the inputs. Input Do is the least signific ant bit (LSB). 200 kH
/)" o---"IVv-----,
0 1 23 456 789 10111 2 13 14 15
lOOkO D,
o-----'\Mr- -f
Do
--<> 1',.., +
J1SLJ1.JL n n n fl-
0 II I II I I I I H H I- I +5V I I : I : I 01 U I I : I I I : I ( ( I
.,v .,vo ,, :
0,
D, (0) FIGURE 11 _ 37
., V
0
II
I ((
,(
L
,L ', I
L
770
•
IN TROO U CTIO N TO DIG ITA L SIGNAL PROCESSIN G
Solution
First, J etermi nc the curren t fo r eoch of thc weightcd inputs. Sincc the im'clti ng (- ) input of the op-amp is at 0 V (virtual ground) and a binary I corresponds to + 5 V. the CUITCnt thro ugh any of lhe input resistor.; is 5 V divided by the resistance vailit'.
5V
10 = 200 kO = 0 .025 rnA
5V I I = 100 k O = 0 .05 mA
5V
I~ = 50 kO = 0 .1 lIlA
13 =
5V
-25 kn
= 0.2 rnA
Almost no currcnt goes into the inverting op-
= ( 10 kO)(- O.025 rnA) = - 0 .25 V
\',,,,,(1)1 )
= ( 10 kO ) (- 0.05 mAl = - 0 .5 V
1'"",{D2 )
= ( IO kO )(- O. 1 mA l = - ] V
V,,,,>(03)
= ( 10 kO )(- 0 .2 rn A) = - 2 V
From Figure 13-37(b}, Ihc fi rst binary input code is C by - 0.25 V, so lo r th i~ partiCUlar straight binary sequence on the inputs, the output is a staimep waveform going from 0 V to -3.75 V in - 0.25 V steps. This is shown in Figure 13- 38. FIGURE 1 ] - ] 8
Output of the MC ill Figure 13- 37.
u
~ =8 c ~ § :S:Sco
-0.25 - 0.50 -0.7.'1 - 1.00 - L25 - l..'iU
- 1.75 _2.00
- 2.25 - 2.50 - 2.75 - 3.00 - US - 3.50
I-
0
c
0
;;; § 8 <:>:= = <:> :::
-i-'
L:;:f+ .
,
L
t ~
- 3.75
,
,I
t+ -I
tl
'"
I~
t
c
~
Bin.1ry inplil
~ t ~~
-~ t
V"", (V \
Related Problem
Rcverse thc input wmrefo rm.~ to Ihe DAC in Fiourc 13-37 (D to D D 10 D D 10 . e J 0> 2 I" I~, Do to DJ ) and dctermme [he output .
DIGI TA L- TO-ANALOG CONVERS ION METHODS
The R/2R Ladder Digital-to-Analog Converter Another method of d igital-to-mmlog wnversioll is the RflR ludder, us shown in Figure 13- 39 fOf four bits. It overcomcs one of the problems in the binary-wcighted-input DAC in that it requi res only two resistor values. l"Pill\
n,
f) !
R, 2R
2R
•
,
FIGURE
R., 2R
R,
2' R,
R,
•
R
An
n, RJ = 2R
>+ --<> 1'
,~
Start by assumi ng that the D3 input is HIG H ( + 5 V) and the other.; ilre LOW (ground, OV). 'Iltiscondi tion represent" the binary nu mber 1000. A circuit ilnalysis will show that this reduces to the equivalent fonn shown in Figure 13-4O(a). Essentially no curre nt goes through the 2R equivalent resistance because the inverting input is at " inual ground. Thus, all of the current (/ = 5 Vf2R) through R7 also goes through RJ • and the output voltage is - 5 V. The orxrational iUnplifier h .>cps the in''Crting (- ) input ncar zero volts (=0 V) lx."'Calise ofncgative feedback. Therefore. all CUlTCnt goes through R, nllher than into the inverting input. Figure I3-4O(b) shows the equ ivalent circu it when the f)2 input is at +5 V and theothers arc at ground. This cond ition represents 0 100. lfwe the"eni"te* looki llg from Rg. we gel 2.5 V in series w ith R, as shown. This resu lts in acurrcntt hrough RJo f 1 = 2.5 Vf2R, which gives an output voltage of - 2.5 V. Kee p in m ind thai there is no curren t into the op-amp inverting input ,md that therc is no CUITCnt through the equivalent resistance to ground because it has 0 V across it, due to the virtual ground. Figure 13-40(e) s hows the equi valcnt circu it when the 0) input is at + 5 V and the others arc at ground. This condition represents 0010. Again theven izing looking from RH• yo u get 1.25 V in serics with R as shown. This resu lts in a current through Rl of 1 = 1.25 VI2R, which gives Ull output voltage of - 1.25 V. In pan (d) of Figure 13-40, the C
Performance Characteristics of Digital-to-Analog Converters The perfo rmance characteristics of a DAC include resolution, accuracy, lineari ty, monotonic ity, and settling lime, each of which is discussed in the follow ing list: Resol UTion. The resolution of a DAC is the reciprocal of the number of discrete steps
in the output. This, of course, is depe ndent on the nu mber of inpm bits. For eXiUI\ple, a 4-bit DAC hilS a resolution of one part in 24 - I (one part ill fi fteen). Expressed as a percentage, this is ( 1/ 15) 100 = 6.67%. The to tal nu mber of discrete s te ps C
13~39
R/2R tildder DAC.
•
77 1
772
•
INTRODUCTION TO DIGITAL SIGNA L PROCESSING
OV
liju;\"knlladU.:r r~","I;tIII..'C \ulh f) •. _
R[Q '" 2H
0 ,. and V" g"""Jd.,\J
+
.sv R,
Il,
R,
-.
2R
-
R. R
~ R,
+
liR
-l
-l
r,.....
=
'"
--IH,
-e~~V)2R -
2.!'i V
D" 0 0, " 0 tb) Equi" "em circuit for IJl "" O. IJ~ '" I . D. "" O. Do- 0
+5V RJ
1)1" I
,.R,
-., -' =l -l -l = R,
R.
R
R
R, 2R
HI:.Q
=2R
2R
1' rt1
+ 1.2:) V
R IR 0
+
1
+
v_ '" - IR,
R, 2R
-
/
(1.~~V) 2R _
n , '" 0
'h =- 0
0 ,,= 0
R,
2R
1.25 V
{e ) EquI'·bienl circu il for I) ) _ O. D , .. 0.1)1 :: I. Do = 0
+5V
I
/)" =- I
R,
R, 2R R,
2R
R,
R
'" -
O, t'o2.~
v
-n +J.J~V:\--' 2R
R,
R,
R
2R
_ ,
.R,
R
2R
R, OR
-l =l -l D, 0
R, RTH VTH o--/I.Nv-W\-~-<-1 + 0.625 V H
Hs
o~= n
OV
+
H U
R, 1R
-
1
/
+
-'-
1".... '"
•
0.; :0
,", Eqoiwlcnt circllit fOf OJ '" 0' /)1 '" O. 1)1 .. O. 1)0 : I FIGURE 13-40
Anaty.iJ of the RJ2R /adder Me.
IR,
(o.6!."iV) ~H .0 f12!'i \ ~R
-
DIGITAL-TO -A NALOG CONVERSION METHODS
Accuracy is derived from a comparisol1 of the ac1Ut significl.llII bit is 0 .39% of full scale . 11lc acelln\cy should be approximately ±G.2%. ACCll rrlc.:\:
Li"earity. A li near error is a deviation from the ideal straight-line output of a DAC. special case is an o ffset error. which is the alllOUIlI of output vollage when the input bits are all zeros. A
MOl/otonicity. A DAC is monolonic if it docs nottakc any reverse stcps whcn it is sequenced over its entire range of input bits. SettlinR tilJle. Settling lime is nonnally defined a<; the lime it takes a DAC to scHle
within ± 112 LSB of its fi mll value when a change occur:i in t.he input code.
I
EXAMPLE 13 - 4
Dctermine the resolution, exprcssed as a percentage. of the following: (a) an 8-bit DAC
Solution
(b) a 12-bit DAC
(a) For the 8-bit converter.
- -I - x 2~
- I
I 100 = X 100 = 0.392'* 255
(b) For the 12-bil conven er, I
::0''--:- X 100 = - - X 100 = 0.0244% 2 12
Related Problem
4095
Calculate the resolmion for a 16-bit DAC.
Testing Digital- to-Analog Converters The concept of DAC testing is illustrated in Figure 13-4 1. In lhis basic method, a sequcnce o r binary codes is applied to the inputs, ilnd the resulting output is observed. The binilry code sequence extends over the rull range of values from 0 to 2n - I in asccnding order, where /I is the number of bit~.
RUlan ~ode
~: - - - ' - -•• II
FIGURE 13 - 41
Billie test letup for iI Me.
DtlC
•
77 3
774
•
INTRODU CTION TO DIGITAL SIG N AL PROCESSING
The ideal output is a siraigh t-line stairstep
Oigital-to-Analog Conversion Errors Several digital-to-anlliog conversion errors to be checked for Crctesteps. Each graph in the figure includes an ide
Nonmonotonidty
Figure 13-42(b) illustratcs differential nonlinearity ill which the Slep amplitude is less 111<111 it s hould be for certHin input codes. This partic ular output could be caused by the 2J bit having an ins uffic ielll weight, perhaps because of it faulty input resistor. We COllld also sec steps with amplitudes greater Ihan nomml ir a particular binary weight were greater than it should be. Differential Nonlinearity
FIGURE 13 - 42
IIllJltrationl of ~raJ digital-toana log convenion errofl.
An"l,,!:
""
13 J2
"9 10
8 7 6
,, 3 2 1
o ~~LLLL~-LLL~~-L.
8§- ~= 80~ =§8e=80=:= Binary 8 8805000 __ =:=:==== inpUI (al
NOl1mo~onjc
(b) Diffcrenl;alllOfllincanly (green)
OI.llpUl (f,rcrn)
Analog
AnillOj!:
"" ~~"C'i"='~=tl=~~=t~+=
OUl pul
""
13 J2
13 J2
"9
10
"9
8 7 6
7
10
8
,,
6
i~:~~~~Ei~~Et~I~'
3
~ t <::ti:..r
o ~~~~~~LLL4 g~ =:;;8 c
== S g9=
S:
_~8ooooo;:::_~~==== (c) High Hnd ,()\V gail\~ (green)
i np!.11
1
°x=~_~oL_~c~_~oL_LL§~_~_LLLL-LL4 "'"'x;::::=:o o _ _
~~~~-c--
....
0
0
SO!:::~go::::=Binary _c ____ _ inpu[
;;:00 _ _ _ _ _ _ _ _
(d) OffSCI error (green)
DIGITAL-TO-ANALOG CONVERS ION METHODS
•
775
Low or High Gain Output enurs caused by low or high gain are illuslmted in Figure l3-42(c). In the case of low gain, all of the step amplitudes are less than ideal. In the case o f high gain, 811 of the StCp amplitudes are greater than ideal. This situation may be caused by a fau lty feedback resistor in the op-amp circuit. Offset Error An offset error is ilhL~tnltcd in Figure 13-42(d). Notice that when the binary input is ()()(X), the output voltage is nonzero and that this amount of offset is the same for all steps in the conversion. A faulty op-amp may be the culprit in this situation.
i
EXAMPLE 13-5
The DAC outpu t in Figure 13-43 is obseT'.'ed when a straight 4-bit bi liary seq uence is applied to the inputs. Identify the type of error. and suggest an approach to isolate the fault. FIGURE 1 ) - 4 )
Analog output
Solution
The DAC in this case is nonmol1otonic. Analysis of the output reveals Ihat the device is converting Ihc following sC
OOIO.OO ll.OOJO.OO I1. 01 10.0 111 .0110.01 11.1 01O, 10 11.1010, 10 " , 11 10. 1111. 11 10, 1111 Apparently. the 21 bit is stuck in the HIGH ( I) slate. To find the problem. first monitor the bit inpul pin to the device. If it is changing states, the fault is inlenmllO the DAC ,lI1d it should be replaced. If the external pin is 1101 changing states and is always HIGH, check for an extemal short to + V that may be causcd b}" a solder bridge somewhere on the circuit board. Related Problem
Delennine the OurpUI of a DAC when H stmighl 4-bil binary sequence is applied to the inputs and the 2° bit is stuck HIGH.
The Reconstruction filter 'me output o flhe DAC is a "stairstep" approximation of the original analog signal aftcr it has been processed by the DSP. lltC purpose of the low-pass reconstruction filler (sometimes called a post fi lter) is to smooth out the DAC output by eliminating the higher fre(Iucney content that results frolll .he fa~t tmnsilions oflhe "stairsteps," as roughly illustrated in Figure 13-44.
77 6
•
INTRODUCTION TO DI GITAL SI GNAL PROCESSING
Rccon.~t ruction
fil ter Olltput of tho: [):\('
Fin:!L
:In:J,,~
"Ulplll
FIGURE 13 - 44
The reconstruction fil ter ~oothl the output of the DAe.
I
SECTION 13-5
1. What ii the disadvantage of the DAC with binary weighted inpu b ?
REVIEW
2. What ii t he resolution of a 4-bit DAC? 3. How do you detect nonmonoto nic behavior in a DAC? 4. What effect does low gain have on a DAC outpu t?
KEY TERMS
•
Digilal signal processing is the di gital processing of ,malog signals. usually in real-time. for Ihe purpose of mod ifying or enhancing the signal in some way.
•
In genenJl, a digital Signa l processing system consists uf an anti -alia.~ing filter. il sample-andhold cireu it, an anolog-lo-digilal converter, 0 DSP (digi tal signal processor). a digital-te-analog converter. and a recons truction fil ter.
•
S:!mpling converts an ana log ~ignal into a series of impu he1>. each representing the signal amplitude at a ~h'e tl instant in time.
•
The sampling theorem slates that the sampling frequency sampled frequency (Nyquisl frequency).
mu.~1
be alleaS! twire the highest
•
Ana log-to-digital convcrsion changcs an ana log ~ ignal into a series of digita l codes.
•
Four types of analO!!-to-digitul r..'()IlVcrters (ADCs) arc successive-approximation. aod sigma-del ta.
•
A DSP is a speciali7.cd microprocessor optimi7.ed for speed in order to process data as it OC(:un; (reol-time).
•
Most DSPs are ba:\.Cd on Ihe l-lafvard architecture, wh ich means that there is a data memory and a program mell1ory.
•
A pipeli ne operation
•
Di,gital-Io-analog conversion changes a :\.Cries of digi tal codes Ihat represem an analog signal back into the ana log signal.
•
Two Iypes of digital-Ie-analog converters (DACs) are binary-weighled input and Rf1R ladder.
eonsist~
na~h
(simultaneous), dual-slope.
of fetch. decode. and cxcwtc stages.
Key temu and other bold term! in the chapter
[0 convert
an analog signal to dig-ilal form .
l>eroflc A stage of Ihe DSP pipeline operation in which instructions ilfe assigned 10 functional units
and lire decoded.
SELF~TEST
•
777
Oigitul-to-alUllog com"erter (DAC) A circuit used to convert the digi tal representation of an analog signa l back to the ana log signal. OSI) Digital signa] processor; a special type of microprocessor that processes data in real time. OSP core The central proces..~ i ng unit of a OSP. Ex«utc A stage of the DSP pipeline opernt ion in which the decoded instructions arc carried oui. l--etch A stage of th e DSP pipeline operation in which an instruction is obtai ned from the program memory. MFLOPS Million nooti ng-point operntions
jJL7
sccoml.
MIPS Million instructions pe r second .
.I\1i\·lACS Million multiply/occu mul;ltes per second. Nyquist fTt'fIUcncy The hi ghest signal freq uency that can be sampled at a specified Sllmpling frequency: a frequency equal to or l es..~ than half the sam pling frequency. Pil)Cli ~
Pan of the DSP arc hitecture that allows mul tiple instructions 10 be processed simu ltaneously.
Qmmti7.11lion The process whereby a binary code is assignullO eadl sampled \~J l ue during analogto-digital conversion_ SaillJlling The process of toking a sufficient number of discrete values ilt points on a waveform ttwt will dct ine the ~hape o f the wa\·eform.
Answerl il re ilt the end of the I. An AOC is an (a) al phanumeric data coder
(b) onolog-to-digitol convertcr
(e) analog device carTier
(d) anfllog-to-digilal com parator
2. ADACisa (:1) digilill-to-f1nalog computer
t b) digita l analysis L'U lculator
(e) data ,\Ccumulmion L"tJ!1\'el1er
(d) digital-to-ana log COlwerter
3. A dig ita l signa l processing system us ullll y opcrJlcS in (a) real time
(b) imaginary time
(c) comprcssed li me
(ell computer ti me
4. Sampling of an ana log signal prod uces (a) a series of impulses that are proportional to thc amplitude of thc signal
(b) a series of impulses th flt ore propol1ionfl[ to thc frequclll:y of the signal (e) digi tal codes that reprcSCtlt the analog signal amplitude
(
(b) grea ter than tw ice Ihe highest signal frequency
(cl less than hal f the lowest signa.l frequcncy (d) greater than the lowest signal frequency
6. A hold action occurs (a) before Cilch sam ple (c) after the analog-tO-
(b) during each sample (d) immediately aller a sample
7. ·n le quan til.!ltion proccs." (a) converts Ihe s.."l.m ple-and-hold OUtput to binilry code (b) COllverts
fI
sample im pulse 10 a lere!
(e) converts
fI
sequence of billllry eodes 10 a reconstructed analog signal
(d) ti lters 0111 unw'o!.nled frequencies before salnp]i ng lakes place
778
•
INTRODUCTION TO DIGITAL 51GNAl PROCE55ING
8. Generall y, an ana log sign.. 1ca n be reconstructed more :lCCurntely with (a) more quunti7.ation levels (b) fewe rquan ti zution le\'els
(e) a hi gher sa mpli ng frequency (d) a lower sampling frc-qllency
(e) either
an~ wer
(a) or (c)
9, A flash ADC uses ~C)
(b) op-amps
(II) counters
an intcgnllor
(d) flip· nops
(e) answers (a) and (el
10. A dUll[-slopc ADC uses (a) a cOllnter
(e) an integrntOf
(b) op-umps
(d)
"differentiator
(I') answers (a) and k )
II. The ou tput of a sigmu-delta ADC is (b) multiple-bit data (a) parallel binary codes (d) a diffe rence \'olillge
(e) single-bit daw
12. The tcnn (II)
HCln'llfl/lm: hitel'flll'('
a CPU
~nd
means
a main memory
(h) a CPU and two data memories
(e) a CPU. a progrn m memory, and a daw memory
(d) a CPU and two register files
13. The minimum numocr of !leneml-purposc regi~ters in the TMS32OC6000 series DSPs is (a) 32
(b) 64
(d 16
(d) 8
14, The two internal memories in the TMS32OC6ODO series each han: a capacity of (d) 32!..B Ie) 64 kB (b) 512 kB MB 15_ In the TMS32OC6OClO serie., pipeline opcmtion, the number of instroctions processed (II) I
simultaneously is (:1)
eight
(bl four
(e) two
(d) one
16. The stage of the pipeli ne opcmtion in which instl1lctiorl<; are retrieved from the memory is called (a) execute
Ib) accumu lOlte
(e) decode
(d) fetch
17. In a binary-weightoo DAG. the resistors on the inputs (al deterl11 ine the ampli tude of the 1:111alog signal (b) dcte rnline the we ights of the digital inputs te) limi t tlle power cI)llsu mption (rn prevent [ooding on the
.~O\\rcc
18. In an R/2R DAC, there are (a) fou r \'alues of resistors (b) one resistor \u lue (e) two re sistor values (dl a number of resislOr values equaJlo the nu mocr of inputs
PROBLEMS SECTION 13- 1
Answen to odd-numbered problerm arc at the end of the boo k.
Digital Signa' Procm:sing Basics I. Explain the purpose of anaJog-to-digi ta J cOlll'crli ion.
PROBLEMS
•
779
2. Fill in the appropriale functiona l names for the digiw l signal processing system block diagl1lm in Figure 13-45.
FIGURE 13-45
3. Explai n the purpose of digit:ll-to-analog con'·c~ion.
SECTION 13-2
Converting Analog Signals to Digital 4. The wavefonn shown in Figure 13-46 is appli cd to a sallipl ing circuit and is sampled .:very 3 ms. Show the ou tput of thc s:lmpling circu it. Ass ume a one-to-one \"oltagc coITe~pondence belwecn thc input and outpUI.
I'
i
15 14
" " , , 12
III 9 7 6
,--'
,
4 3 2
'--<-t:
o
123 4 5 Ii 7 8 9 10 Il t2 IJ t4 IS I617IR I!J 20 2 11223 2425
Ll t(m s)
FIGURE 13 - 46
S. Thc OlLtpot of the sampling circuit in Problem 4 is app lied to a hold circuil. Show the output of the hold circuit. 6. If the output of the hold Circllil in Problem 5 is quan ti 7.cd using twO bits. whal is Ihc re sult ing sequence of binary codes'?
7. Repeat Problem 6 us ing 4-bit quant iZation. S. (a) Reconstruclthe ana log ~ig '1
SECTION 13 - 3
Aoalog-to-Digibl Conversion Methods 10. The inp\lt \'olla,ge to a certain op·amp inverting amplilier is 10 mY. and the otllpul is ~ V. What i~ the closed-loop "oltage gain? II. '10 achi eve a d osed-loop volwge gain of 330 with an inverting amplifier. what va lue or feedoock resistor do you usc if R, := 1.0 kO?
780
•
INTRODUCTION TO DIGITAL SIGN AL PROCESSING
12. Determine the binary OUtput code of a 3-bil flash AOC for the analog input signal in Figure [3-47. FIGURE 13-41
o
10 20 30 40.'iO 60 70!!O 90 100110 1201JOI40 150 100 170 18Q 190
13. Repeal Prob lem 12 for the ana log waveform in Figure 13-4l:!.
FIGURE 13- 48
V
9
" 6 , 7
4 3 2 1
0
r-'.-+
' +_.
f~!
.-1
1V '
-+I I
t-+/Lhi ·-k 'tY -; I
h= ':
! ,
L..L....L....l_L..L....I._L..L_-'_ L..L...l.....JLL..L....I._L ..L..L_ _. / (psi 10 20 30 40 50 60 70 I!O 90 100 110 120 130 140 150 160 170 ISO I
14. For a cert ain 2-bil succes~ive-approx irnati on ADC, the max imum ladder wtput is + 8 V. If l\ conSlanl +6 V is applied 10 the ana log input. delennine Ihe sequence of binary states fo r the SA R.
15. Repeat Problem 14 for a 4-bit successi\'e-approx imalioo ADC_ L6_ An AOC produces the fol[owing saillence of binary numbers when an ana log signal is applied to i l~ input: ()()(Xl. 000 1. 00 10, 00 11, 0100. 010 1, 0 110, Dil l , 01 10, 0/0 1, 0100, 00 11, 0010, 0001. 0000.
(a) RcconSlruct thc input digitally. (b) If the AOC failed so thai the code 01 I I were missing. what would the reconstructed output look like?
SECTION 13-4
The Digibl Signal Processor (DSP) 17. A TMS32OC62xx DSP ha~ 32-bil ins tructions and is operating al 2000 MIPS. How many bytes per second is the DSP process ing? L8. If the clock rale of a TMS32OC64xx DS!' is 4(X) MHz, how ma ny instructions can it providt: to the CPU functional uni ts in one second·! 19. How man y noaling-poilll operations can a DSP do in one second if il is specified at 1000 MFLOPS? 20. List and descri be the fOllf phases of Ihe fetch operation in a TMS32OC6OO(} series DSr 21. Lisl and descrilx.- the two phases of the decode operation in a TMS32OC6000 series DSP.
SECTION 13 - 5
Digital-to-Analog Cooversion Methods 22. In the 4-bit DAC in Figure 13-36. lhe lowcst-weighted res islorha.<;;J v;Jlue uf 10 Hl. Wh;J( should the values of the other input resistors be"
PROB l fM5
•
78 1
23. DClc nlline the output o f the DAC in Figure 13-49(a) if the sequence of 4-bit numbe rs in parr (b) is applied to the inputs. The data in puts Ilave a low value of 0 Vand a high value o f + 5 v. FIGURE 13-49
2oo k!}
IO H }
loo kO
I
I--
/J,
SO ,", /J ,
25 kO
n, ('J
-
r
(bJ
24_ Repel,t Problem 23 for the inputs in Figure 13- 50.
FIGURE 13 - 5(1
Do---lnHnI--r-rir fl n r:; : H H : : t
I
I
I
I
I
I
II II I I
- r -r :
I
I
I
I
I
I
I
I
I
I
,
I
II I
DJ
I
l~ ,I I I' I
, 'm I
DJ
I
,
D,
I
I
I
I
I
I
I
I
I I I
I I I
I
I
I
'---i----fTTl-W ',
I/ - il -
l
I
I
I
:
:
II
I
I
-
I
:
25. Determine the resolution ex pressed as a percentage. for each of the following DAC~: ( b) 10-bit (c) IS-bit (a) 3-bil 26. Develop a circuit for generating an B-bit binary test sequence for the tes t Sl.'tup ill Figure 13-41 . 27. A 4-bil DAC has failed in sllch a ..... ay tha t lhc MSB is stuck in the U stme. Draw the analog (HJ tllut when a straight binaty sequence: is applied to the inputs. 28. A straight bina ry sequem:e is applied to a 4-bit DAG. and the output in Figure 13- 5 1 is observed. What is the problem?
FIGURE 13-51
Qulpt.lt
" 14 13 12
II W 9
, , 7
6
4
3 2
782
•
INTRODUCTION TO DIGITAL SIGNAL PROCESSING
SECTION REVIEWS SECTION 13 - 1
Digital Signal Processing Sasia I. DSP stands for digita l sig na l processor. 2. AIX swnds for
anal ~-to-digjtal
convcrter.
3. OAC stmlds for digiW I-to-a niJlog coo\'erter. 4. The AOC changes an analog signal to binmy coded foml. 5. The OAC changes a binary coded signal to analog fonn.
SECTION 13-2
Converting Analog Signals to Digital 1. Sampli ng is the proccs.." of converting an analog signal into a series of impulses. each represcnting the amplitude of the ana log signal. 2. A sampled \'alue is he ld to allow time to (Xl m'crt thc va lue to a binary code.
3. The minimum s3mpling frequcncy is40 klk 4. Qu;mti7.ation is the process of convcrting a Silmp!cd !c,·clto a binary code. 5. 111C number of bits determinc quanti zation accuracy.
SECTION 13-3
Analog-tv-Digital Conversion Methoch I. ' Ibc sim ultancous mash) mcthod is fastcst.
2. The signliJ-delta mcthod produces a single-bit data stream. 3. Yes, successive approximation has a fixed (Xln\"crsion timc. 4. Missing codc. incorrcct code. and offset are types of ADC ootpul crrooo.
SECTION 13-4
The Digital Signal Processor (DSP) l. Harva rd archi tecture means that there is a CPU ,lIld two mcmo ri cs, one ror data and one fo r programs.
2. 11IC OSP core is the CPU. 3. DS!"s can be li xcd-point or noaling-point. 4, Intcma l lTh:mory Iypes are dala and progrnm.
5. (a) MIPS-million instructi ons per s<;wnd (b) Mn~OPS-m i l1ion
!looting· poill! operations pcrsccood
(c) MMACS- million multiply/accumulates pe r second
6. Pi pelining provides for the process ing of multip!c instructions simultaneously. 7. The stages o f pipeli ne operation are fetch. decode, and exC(:ute.
8. During fClch. instructiuns
Digital-to-Analog Conversion Methods 1. In a binary. we ighted DAC. eac h resistor has a diITl:rent value. 2. (11(2· - I}) 100% = 6.67%
3. A step reversa l indicatcs nonillonolonie beh.avio r in a DAC. 4. Step amplitudes in a DAC are Icss than ideal with low gain.
RElATED PROBLEMS FOR EXAMPLES 13-1 100, I ll. 100. (XXI, 0 1" 110. Yl.~. informmion is los\. 13-2 Sec Figure 13-52. 13-3 Scc Figure 13-53. 13--1 (11(2 16 - 1) 100% = 0.00 153% 13--5 See Figure 13-54.
ANSWERS
"" r-'->-'
""
"w,
L
;:t
B-,
i:1 l<88 O
>'100, _ - '-8 !:5' _o_,
=
C
,, ,,,
-r-' -tt- --J -+-, '1
:3311 _1m
f--.+-
j~
5
'-I ..... 1 J ,
- 1.50 _ 1.75
,
~-
j:",'-,
.'- 2.25 00 -2.50 -_32.75 III
-I-
-:J~ 3.75
...'-
..
I
.:-'-+- -
'
8
, 5
, 3
-j
'
. o.-l. __ L . .l....l
FIGURE 1 ]-53
FIGURE t ] - 52
, ,,
W
orr--'-~~~~~~
8
783
"" "" "
,
0,
•
FIGURE 13 - 54
SELF·TEST I . (b)
2. (d )
3. (a)
4. (a)
5. (b)
6. (d)
7. (,)
8, (c)
9. (b)
10. (el
11. (e)
12. (e)
13 . (,)
14. (e)
15. (a)
1(,. (d)
17. (b)
18. (c)
References Dahnoun. N(lim. f)jgi/a/ Sigl/(// Processing Implemelltatioll Ul";/Ig II,e TMS320C6()(X) DSP
Pltlfjonn. RCllding, Mass.: Addison-Wesley Longman. 2(X)Q. Hayes, Monson. Schaum's Outline of /)igiw/ Sigllo/ f>rocessing NcwYork: l\k Graw-Hill. 1998. Kuo, Sen, ilnd Bob Lee. Neal-Time Digital Signfll l'rrx:essing: flll,}lellll!lIto lioll.~, Applicmiolls. ami Experilllem.,· ....i'h ,he 'IMS32OC55x. New York: John Wiley & Sons. 200 1. Lyons, Ric hard. Unders({mding Dig;I{l1 Sigll(ll Long man. 1996.
Pux:e.\·.~illg.
Reading, Mass.: Addi son-Wesley
Marvell. Craig, and Gi lli an Ewers. A Simple AppUXlcfl 10 Digilnl Sigllllf Pux:essillg. New York: John Wil ey & Sons. 1996.
Oppenheim. Alan. and Rona ld Schafe r. Digilal Sigllal Pux:essillg. Englewood Cliffs. N.J.: Prentil.'CHall. 1974. Orfanidis. Sophocles. fnt,.odllclioll to Sig/l al Processing. Uppe r Saddle River. N.J.: PrcnticeH all. 1996. Proakis, John , and Dimit ris Mano lakis. Digital Signol Processing : p,.inciples, Algorithms, alld Applications, 3d cd. Upper Saddle River, N.J.: Prentiec-Hall. 1996. Sicigl il z, Ken. Digilal Sigllal Pmces.fillg p,.imer: lVi/II Applications 10 DiRiwl A/ulio alld Computer Mllsic. Readi ng. l\'lass.: Addison-Wesley Long man. 1996. Williams, Doug las, and Vijay Madisct li. Digital Siglilif p,.ocessillg Hlilldbook. Boca Raton, A.: CRC Press. 1997.
C I CHAPTER OUTLINE
Before beginning this chapter, Section 3-8 should be covered.
14- 1 14- 2 14-3 14-4 14- 5 14- 6 14- 7
CHAPTER OBJECTIVES
•
Basic Operational Characteristics and Parametet's
Cllwlate the power dissipatio n of a device
CMOS Cirruits
Explain how propa~tion delay time affects the frequency of operatio n o r speed of a circuit
TIl Circuib Practical Considerations in the Use of TTL
Interpret the lpeed-power product al a measure of performance
Comparison of CMOS and TTL Performance Emittet'-Coupled logic (ECl) Circuib PMOS, NMOS, and E2CMOS
Determine the norse margin of a device from data sheet parameters
"
Use data mew to obtain information about a specific device Explain what the fan-out of a gate mean!
Describe how basic TIL and CMOS gate operate at the component level Reoognize the difference octwcen m totem-pole output! and TIL open-collector output! and undentand the limitatioru and Ules of each Connect circuit! in a "';rcd-AND configuration Describe the operation of tristate circuit!
Properly terminate unused gate input! Comfl<'re the performance of TIL and CMOS famirieJ Handle CMOS devices "..,lhout risk of damage due to c1cctl'o!tatic dilCharge State the advantages of EeL Describe the PMOS and NMOS circuit! DeKribe an E2CMOS cell
KEY TERMS
m
Current sinking
CMOS
Unit 10000d
Noise immunity
Pull-up resistor
Noise margin
Tristate
Power diuipation
Totem pole
Propagation delay time
Open-collector
Fan-out
ECl
Current sourcing
EZCMOS
INTRODUCTION
This chapter is intended to be used as a ~fJoating~ chapter. That ii, all or portions; of this chapter can be covered at ;)ny point throughout the book o r completely omitted, depending on the course objectives. Section 3-8 should be covered before beginning this chapter. In Chapter 3 (Section 3-8) you learned ;)bout basic integrated circuit logic gates. This chapter provides an introduction to the circuit technology used to implement those gates, as well as other types of IC devices. Two major IC technologies, CMOS and TTL, are covered and their operating parameten art: defined. Also, the operational characteristics of various fami lies within these circuit technologies are compared. Other circuit technologies are also introduced. It is important to keep in mind that the particular circuit technology used to implement a logic gate has no effect on the logic operation of the gate. In terrm of its truth table operation, a certain type of gate that is implemented with CMOS is the same as that type of gate implemented with TTL The only differences in the gates ilre t he electrical characteristics such al power dissipation, switching speed, and noise immunity.
t=
VUlT THE COMPANION WEBSITE
Study aids for this chapter are available at http://www.prenhall.com/floyd
"5
786
_
14- 1
INTEGRATED CIRCUIT TECHNOLO GIES
BASIC OPERATIONAL CHARACTERISTICS AND PARAMETERS Whc n you work with digital ICs. you should be fami liar not only with their logical operatio n but also with such operational propel1ics as voltage Icvels, noise immuni ty, power dissipation. fan-out. and propagation delay ti me. In this section. the practical aspects of thc.<:e properties are discussed. A ft cr complcting this section. you should be ablc to - Detelmine the power and ground connections _ Descri be the logic lcvc!.o; for CMOS and TTL _ D iscuss noise immunity . Determine the powe r dissipation of a logic circuit _ Definc thc prop.1.gation delay time of a log ic gate _ Discuss s pccd-rxlWcr product and ex plain its signifi cance - Discuss loading and fan-out of TIL and CMOS
DC Supply Voltage The nominal value of thc de s upply voltagc for TTL (transistor-tmnsistor logic) devices is +5 V. TIL is also designated T~ L. CMOS (complementary mctal-oxide semiconductor) devices arc available in diffcren t supply voltage categories: + 5 V. + 3.3 V. 2.5 V. and 1.2 V. A lthough omitted from logic diagrams for simpl icity. the dc suppl y voltiJge is connected to the Vcr pin of an Ie pllckage, and grou nd is connected to the GND pin. Both voltage and ground are distributed internally to aU elements w ithin the pllckuge, a." illustrated in Fi gure 14-1 for a 14- pin package. FIGURE 14- 1
Exilmple of Vcc ilnd ground connection ilnd distribution in il n IC pilckilge. Other pin connectiorn ilre omitted for simplicity.
GNO (a) Si ng le
::~IC
(h)
te dual in_line 1>..,,;l;age
CMOS logic levels Logic levels we re discussed briet1 y in C hapter I. There are four different logic-level specificmions: V!L' VII I' VOL. and VOH' For CMOS circuits, the ranges o f input voltages (V1d thai c
BASIC O PERATIONA L CHARACTER ISTIC S AND PARAM ETERS
\ '111
Oulplll
InpUI
,V
I OH { .U '
{
Logic I (HIG H)
J .5V
""
•
787
FIGURE 14-2
Logic I (HIGH) 1001m"n l
Input and o utput logic: levels for CMOS.
I III" .." ,
Unallowed
Un~ lIowed
"n"".."
{ ISV Logic 0 (LOW)
I'll
1
'"
OV
{n.33 V
Logic 0 \ LOW)
1 01 " ... "
0V
(a) +5 V C MOS
IU[>111
e
OUIPUI
v
':U V Logic I (HIGH)
\(*1
Logic 1 (HIG H)
\ 'OI~""'"
::! AV
2V
IIF'm,n
Una llowed
Unallowed
"'V I 'll
\ n """" I.AJGic O ( LOW )
{
I"
,
0'
rv
Logic 0 (L OW)
\ 'OI'n"'"
OV
(b) +3.3 V CMOS
TTL logic Levels The inpul and output logic levels for TfL are givcn in Figure 14--3. JUSI as for CMOS. therc arc fo ur d iffeI'Cnt lugic level spccifici.\lions: VIL • VIII' VOL. and \/0 11 ,
,
lupt,l \ ·II~' ... "
V
"
,
.. FIGURE 14-3
Ollipul
\ (M ~ '''''' ,
Logic I (HIGH)
Logic I (HIGH)
\ 0 111",""
2"
IlIl< n,;",
Unallowed
Unallowed
(JJlV
Logic 0 (LOW)
OV
Logic 0 (LOW) \ II ""'"'
I '01 , . .. "
V'lI ","",
Input and output logic levels for TTL
788
•
INTEGR ATED CIRCUIT TECHNOLOGIES
Noise Immunity Noi!\
If excessive noise CilUSC5 inpullO go below Vllt '''''"I. the £ale may - dunk'· lhalthcrc is a LOW un it, input and respono.lacronlingly.
Potenti" l rcspo"~ 10 e ~~cssive noise ~pi ke on input
(. )
If e~ecssi~c noiN! Cm.lSCS inpm to go ab
"11;" I"
region
t,/
P()(cm ia' respon se noi_'iC spik.e Qn inP'l1 lo exe~"'~ive
---:-;::;J\,----;;;v--Ii\----;,-"/ \1
\(J \" lI
Jl
(b)
FIGURE 1 4 - 4
IIh.lItration of t he effects of input
noi~
on g.lte Opefiltion.
Noise Margin A mcasure of a circui t's noise immunity is called the noise margin, which is ex pressed in volts. There arc two values of noise margin specified for a given logic circuit: the HIGHlevel noise margin (Vtm ) and rhe LOW-level noise mnf!!in (VI\1.) . These parametcrs are defined by the fo llowing equations: Equation 14-1 Equation 14-2
BASIC OPERATIONAL CHARACTERISTICS AND PARAMETERS
•
"a:;.
Sometimes you will sec the noi ~ margin expres!\ed as a percentage of From the Cl.Jualions, VNII is the difference between the lowest possible HIGH output from a driving gate (VOIk minl) and the lowest possible HIGH input that the load gate call tolerate (V1Hlm"'J). Noise margin, V",I,., is the difference between the maximum possible l.OW inpUi thm a gate can tolerate (V1l.(mad and the maximum possible LOW output of the driving gate (Vot~ mo, J . Noise margins arc ill uslllltcd in Figure 14-5 .
' 0..."''''1
I
l 1'. , ILl
4.4V - - :
III GIl HIGH
I
\!lIlon~~'
:
BV
~
I r-.L I
I'l"",," O..UV
:::[::::)T~'- - --,-)
15V
1.0W=87+' -=o111e vol. age Ofl lhis li ro: w ill ne\"er execcd 0.33 V unless nu isc or imploper opera. ion is intrcduccd.
1bc vol! 3i;c on . h;~ line w ill nC\ll.'f be I~"l<' .han 4.4 V unI L"l;.' r>Oi!;C Of"
improper OJ:l<.nllion is im roducoo. (3) HIGH_level noise mal1:!in
,' _ _ I 'Ill ".." : I :
(b) LOW-k \'cI noise margin
FIGURE 1 4 _ 5
lHusmtion of noise margin!. Values are for 5 V ClviOS, but the principle applfel to any logic family.
Determine the HIGH-level and l.OW-level noise margins for CMOS ami for TIL by using the infomlation in Figures 14-2 Hnd 14-3. Solution
For 5 V CMOS, VII I("';") =
3.5
V
Vn.(m.. ) =
[.5
V
VOH["Iin) = 4.4 V VOL(m;.,,) = 0.33 V
V,m =
V0I 1(mi~ )
FNL =
\f1 1.{1l'W.) -
- VIIl(m;n) = 4.4 V - 3.5 V = 0.9 V VOI.(II"'-' ) = 1.5 V - 0.33 V = 1.17 V
For TTL, V ll ll m;n)
= 2V
Vn_{""",) = 0.8 V
VOHrminl = 2.4 V VOL{n,,,-,) = 0.4 V V~!l V NI,.
= VOH [,",,,) - "m(min} = 2.4 V - 2 V = 0.4 V = V lI.(m" .. ) - Voqn_) = 0.8 V - 0.4 V = 0.4 V
A ITL gllte is immune to up to 0.4 V of noise for both the H IGH and LOW input states.
Related Problem·
B'L<;cd on the preceding noise margin calculafions. which family of devices, 5 V CMOS or TTL. should be used in a high-noise environment?
*Answers are at the end orthe chapter.
7 89
790
•
INTEGRATED CIRCUIT TECHNOLOG IES
Power Dissipation A logic gatc draws (;U1Tcnt from the de supply voltagc sourcc, as indicilted in Figure 14-6. When thc gatc is in the HIGH OUtput statc. an amounl of current dcsignatcd by fccil is drawn; and in thc LOW omput statc. a diOcrent amount of current. feeL. is drawn. FtGURE 14- 6
+'0.-
~
Currents from the de supply. Conveotion
LOw - Y HIGH
opposite. (,I
(bl
As ao cxample, if l ear is specified as 1.5 rnA when Vee isS V and if thc gale is in aSiatic (nonchanging} HIGH output statc. thc power dissipation (I'D) of thc gatc is PD
=:
VcdCCl r
::0
(5 V)( 1.5 mA) = 7.5 mW
Whcn a gale is pulsed. its output switches back and f0l1h betwcen HIGH and LOW, and the amount of supply current varies betwccn Iccll and IcC!.. 111C a\'cmge powcr dis~i pat ion depends on the duty eyclc and is usually specificd for a du ty cyclc of 50%. Whcn the dut y cyclc is 50%, thc output is HIGH half thc limc and LOW thc olhcr half. The .\\'erilgc supply CUlTcnt is therefore Equation 14-3
Icc =
Iccil
+ 2
fcct.
The avcra2e power dissipation is Equation 14- 4
I
EXAMPLE 14-Z A ccnain gatc draws 2 p.A when its output is HIGH and 3.6 p.A when ils oUIput is LOW. What is its avcragc power dissipation if \fcc is 5 V and the gate is operated on a 50% duty cycle?
Solution
ll1C averagc Icc is
lee =
fern
+ Ioct. 2
=
2.0 p.A
+ 3.6 p.A :2
= 2.8 p..A
Thc avcrage power dis~ipat ion is PI)
Related Problem
=::
Vcc/cc = (5 V){1.8
~A) =
14 p.W
A certain IC gatc has an ICOI = J.5 p.A and fceL = 2.8 p.A. Determine the average power dissipation for 50% duty cycle operat ion if Vee is 5 V.
Powerdissi p.1.liOIl in a TTLci rcuil is esscntially cons/;mt over its mngcof operati ng frequencIes. Pow~r d issipation in CMOS, howcver. is freq uency depende nt. It is extremely low under stahc (de) conditions and increases as the frequency increases. Thesc charac-
BASIC OPERATI ONAL CHARACTERISTICS AND PARAMETERS
teriSlics afe shown in Ihe genera l curves of Figure 14---7. FOf example, the power d issipation of a low-power Scholtky (LS ) TTL gate is a constant 2.2 mW. The power di ssipalio n of an HCMQS gate is 2.75 JIW under static conditions and 170 p.W al 100 kHz. FIGURE 14_7
TIl
Power-vernn-frequency curve ffiandCMOS.
fO(
O ~------ f
o
Propagation Delay Time When a signal pa~ses (pro pagates) through a logic c ircuit, it alwayl'i experiences a time delay, as ill ustrated in Fi gure 14---8. A change in the output level always occurs a short time, called the propagation delay lime. later than the change in the input level that caused it. Input
FIGURE 14- 8
Outpllt
ElNt~y -[
.,
~;
A b<.sic ill ustration o f propagation
delay time.
I1I GH ~ A~
menti oned in Chapter 3, there arc two propagation de lay logic gates:
t im e~
specified (or
TIle time between a Jesignatcd point on the input pulse and Ihe corresponding point on the output pulse when the output ;l'i Changing from HIGH to LOW.
t /'lll.:
trw:
The time between a designated point on the input pull'iC and the oorrel'iponding poilll 0 11 the output pulse when the output is changing from LOW to HIGH.
111esc propagation delay times are illustrated in Figure 14-9. with the 50% pointl'i on the pulse edges used as references.
FIGURE 14- 9
----r-\
H Olll pul I nput~
I nput
Oulput
Il
~
L ~,
HJ.1Tl ,, ,' L
~I
= HIGH
L : LOW
~ ,
I
I t
I I
t I
I
I
t
I
I-r-t II
t-r-: L..
I
I
II'IJI
'/'11/
Propagation de lay timeJ.
•
791
792
•
INTEGRATED CIRCUIT TECHNOLO GIES
The propagation delay time of a gate limits the freque ncy at which it can be operated. The greater the propagmion delay time, the lower the max imum frequency. 111OS, a highcrspeed cireuit is one that has a smaller propagation delay lime. For example. a gate wi th a delay of 3 ns is faster than one with a IO ns delay.
Speed-Power Product The speed-power product provides a basis for the compari son of logic circuits when both propagation delay time illld power dissipmion are important considerations in the selection of the type of log ic to be used in a certain application. The lower Ihe speed-power product, the beUer. The un it o f .~ peed- power product is the picojoule (pJ). f or exam ple, HCMOS has a speed-power product of 1. 2 pl at 100 kHz while LS TTL has a value of 22 pl .
Loading and Fan-Out When the output of a logic gale is connected to one or more inputs of other gates. a load on the driving gate is created, as shown in Figure 14-- 10. There is a limit 10 the number of load gate inputs Illal a given gate can dri ve. Th is limit is called the fan -out of the gate. FIGURE 14- 10 A
Loading iI gilte output with gilte
Ii --;_J
inputs.
Loading in CMOS differs fromthm in TIL because the type of transistors used in CMOS logic present a predominantl y capacitive load to the driving gate, as illustrated in Figure 14-- 11. In this case. the limitations arc the charging and discharging times associated with the output resistance of the
CMOS Loodillg
+,v
1.0W
HI GH
JD..1
tal Charging
Ill)
I)ischa~ing
FIGURE 14- 11
UPilOtive 1000ding of a CMOS gille.
. Whc n more loud ga ~e inpu ts arc added to the drivi ng gate outp ut, the total capac itance IIlcrcuscs because the mput capacitanccs effcctively appear in parallel. This increase in capaeitancc increases thc charging and discharging ti mes, thus re
BASIC OPERATION AL C HAR AC TERISTICS AND PARAMETERS
frequency at which the gate can be operated. Therefore, the fan-ou t of a CMOS gate depends on the freque ncy of operation. The fewer the load g;:lte inputs, the greater the maximum frequency.
ITL Loading A ITL driving gate sources current to a load gate input in the HIG H slate (In;) and sinks CUJTcnt from Ihe load galc in the LOW Stalc (IlL)' Current sourcing and current sinking are illusl.nltcd in si mplified form in Figure 14- 12, where the resistors represent the internal input and output resistance of the gate for the two conditions.
+5V
H1G I I -~-h~ HIGH
-~~1:;',"=,====~/,,~,=====,==~~~~ IIIGH
I"
LOW -f""i1""''i===~=='~ ~d..../ LOW
Driver
• Cood
(al Currenl .'iOufc ing
(bl Currenl sink ing
f iGURE 14-12
Bc.sic illustr.ltion of current sourcing and ament sinking in logic gate\.
As more load gates arc connected to the driving gate, the loading on the driving gale increases. The total source cLUTcnt incre1.~"es with each [mid gale input that is added, as illustrated in Figure 14- 13. As this curren t increa..c.<;, the internal vo[tagc drop of the driving gate incrca.~es , causing the output, Vou , to dCCfe;:UiC. If an excessive number of load gate inputS are connccted, V OII drops below VOH(n "n )' and the H IG H-level noi ~ margin is reduced, thus compromising the circuit operation. A[so. as the total source current incrca~s, the power dissipation of the dri ving gate increases. fiGURE 14- 13
+ jV
HIGH-state m Total \
.....,
'-
O;OUiTC
.
I
TIle fall -out is the maximum llumber of load gate input" that call be connected without adversely (jffecting the specified operntional characteristics of the gl.ltc. For example, 10wpower Schottky (LS) l TL has a fan-out of 20 unit loads. One input of the same logic family as the ([riving g..1.te is called a unit load. TIle total sink current also increases with eHch lond gate input that is added, tL<; shown ill Figure 14- 14. As this current increllscs, the internal voltage drop of the dri ving gate incrcases, causi ng VOl to increase. If an excessive number of loads arc added, VOL excecds V (H.iIt1lU). and the LOW-level noise margin is reduced. In TIL. the current-sinking capability (LOW output state) is the limiting factor in determining Ihe fan-ou t.
loading.
•
793
794
•
INTEGRATED CIRCUIT TECHN O LOGIES
FIGURE 14- 14
.5V
LOW,b ge m 10000ing.
t
l OW TrlIa l 'IO ~ f
fn~ I
.5V
III ,
.'V
1
-
' II ,~,
I ~ECTION
14-1
REVIEW
1. Define VIti- Vlv V()H. ..md VOl'
A niWerS
2.
chapter.
3. Ga te A has a gre ate r pro pagation delay time than gate B. Which gate can o pe rate at a higher frequency7
I~
it better to have a lowe r value of noi~e margin o r a higher value?
4. How does excessive loading affect the noise margin of a gate?
14-2
CMOS CIRCUITS Basic intelllal CMOS ci rcuit ry and its o peratio n arc discussed in this section. The abbreviation CMOS Stands for complementary metal-ox ide semiconductor. The term complemem ary refers 10 the usc of two types of transistors in the output c ire uil. An II-channel MOSFET (MOS ficJd-cfTcct transistor) and a p-channcl MOSFET are uscd . After completing this section. you should be able 10 • Idelllifya MOSFET by ils symbol - Discuss the switching action of a MOSFET - Describe the btl<;ic operation of a CMOS inverter circuit _ Descri hc the bas ic operation of CMOS NAND and NOR gates . Explain the operation of a CMOS gate with an open-drain output • Discuss the operalion of tristate CMOS gates _ List the precautions required when handling CMOS devi(;es
The MOSFET Metal-oxide semicondu(;tor fie ld-effect tra nsistors (l\·IOSFETs) are fhe active switching e lemellls in CMOS circuits. These devices differ grcarly in constrlJ(;tion and internal oper<.Ition from bipolar j unction l ransi.~t ors uSCi..l in TTL (;ircu its, but fhe switch ing action is baSically the ."
CMOS C IRCU ITS
+5V
+5V
Dr;,in (1) 1
J c"j::JI ~G)
-
s.,,,"-~
IS)
Solln:c IJ-Chanucl
II-chanoc l (3) MaSFET symhuls
ON
OFF
( h) ,,-channel swilch
ON (d p-ch~nr>d switch
OFF
FIGURE 14- 15
Basic l)'fTlboli and iwitching action of M05FETs.
switch betwccn the drain anti the source. This operation is illustrated in Figure 14- 15(b). Thep-channcl MOSFET opemtcs with opposite voltage polarities. as shown in part (c). Sometimes a si mplified MOSFET symbol as shown in Figure 14- 16 is used. FIGURE 14- 16
5implified M05FET iymbol.
CMOS Inve rte r Complementary MOS (CMOS) logic uses the MOSFET in complementary pairs as its ba<;ic element A complementary pair U!\eS both I!-Channel and n-channcl enhancement MOSFETs. as shown in the invcrlercin:uit in Figure 14- 17. .Voo G~leIG)
J
>-
Soo~'IS) Q, Drn,o( D)
t---- - - - Ou IPUI
Inf'l'l
DrmnlDl
:=t G:,ICIG I
G,
1 "0",,-"(5)
FIGURE 14_11
A CMOS inverte r circuit.
•
795
796
•
INTEGRATED CIRCUIT TECHNOLOGIES
Whe n a HIGH is applied to t.he input. as shown in f7igurc 14- 18(a). the I'-channcl MOSffiT Qf is off and the IH hanncl MOSFET Q~ is on. 'Illis condition connects the output to BrolLnd through the on rcsislance of Q2. rcs ulli ng in a LOW oulput. When a LOW is applied 10 Ihe input, as shown in Figure 14-- 18(b). Ql is 011 and Q~ is off. This condition connects the outpullo + VOl) (dc supply vohaBe) Ihrough the Oil resistance o f Ql. rcsuiti ng in a HIGH ou/put. FIGURE 14-18
Operation of a CMOS inverter.
+V1)f)
+1'00
d
d Q
Q
L O W 1' OR'
tIIGl-I - -
1-"'GI
LOW - -
Q,
Q,
l ON
(1I) Ht GH input . LOW
' ON
I
1~'
(b) LOW inpul. HIGH OUlput
OtJlptJt
CMOS NAND Gate Figure 14- 19 shows a CMOS NAND gate wilh two inputs. N(){1ce thc arrangement of the complementary pairs (n-t.: hanncl and I'-channcl MOSFETs).
FIGURE 14_ 19
A CMOS NAND g.;lte circuit.
+Voo
l'd ~,Qd
"-----+--J'~J~--- ""'P' '
"', "'" --------+-,1
I'
'" "'B -~J~r
L L H H
L H L II
S S C C
S C S C
C C S S
C S C S
H H H L
C ~ ",,1OIT loft) S '" SI<1tJ'ation (onl lI = HIGIl L = I.OW
The operation o f a CMOS NAND gate is as follows: When bolh inputs arc LOW. Q, and Q2 afe on, amI Q3 and Q.. are off. The output is pulled H IGH through Ihe on resistance of Qt and Q2 in parallel.
CMOS C IRCU ITS
When input/\ is LOW and input IJ is HIGH. Q I and Q~ arc on, and Q~ and Q3 arc o ff. Thc output is pulled HIGl-lthrough the low 011 rcsistancc of QI' Whcn input /\ is HIGH and inpullJ is LOW, Q , and Q.. arc off. and Q~ and Q3 arc on. The OUlpUl is pulled HIGH through the low 011 resistance of Q2' r inally, whcn both inputs are HIGH. Q, and Q2 are off. anll Q~ anll case. thc output is pullet! LOW through the 0 11 rcsislancc of Q) and ground.
Q~ arc 011 . Q4
III this in series 10
CMOS NOR Gate Figure 14- 20 shows;1 CMOS NOR gatc with two inputs. Noticc the arrangement of the complementary pairs. FIGURE 14 - 20
+1'00
-----~ d
Inpul A - ....
,""",8
A CMOS NOR gate circuit
Q,
~---~J
L L OulpUI
H
L H L
H
H
S S C C
S C S C
C C S S
C S C S
H L L L
C = cUlOlTloIl) S .., " '"mlion (on) H : I IIGH I... I.OW
The operation of a CMOS NOR gate is as follows: When both inpuls arc LOW. QI and Q2 arc on. and Q.l and Q4 arc off. As a rcsult, the output is pulled HIGH through the on rcsiSlance of QI and Q2 in series. When inpUlA is LOW and input B is HIGH, QI and Q.. are on, and Q! and Q~ ,Ire off. The outptll is pulled LOW through the low 011 res istance of Q4 to ground. When input/\ is HIGH and input IJ is LOW, QI and Q4 are off. and Q2 and QJ afC on. The OUlput is pulled LOW Ihroug h the 011 resistance of Q3 10 grounll. Whcn both inputs arc HIGH, QI and Q2 arc o ff. and Q3 and Q4 arc on. The outp ut is pulled LOW through the 011 resistancc of Q3 and Q.. in parallcl to ground.
Open- Drain Gates Thc (Crill opell-dmin means Ihat the dr"in terminal of the output tnmsistor is unconnccted anu must be coTlncctell externally (0 VOl ) through a 10'ld. An open-urain sate is the CMOS counterpart of an opcn-coIlcclor lTL ~a' e (discussed in Section 1-1--3). An open-drain outplll circuit is a single II-channel MOSA? r as shown in Figure 14-2 1(;1). An extern,,1 pull. up resistor must be usctl. 1l~ shown in part (b). to produce" HIGH output slatc. Also. open-llrain outputs can be conncclet! in a wired-AND confi gunltion. a concept thm is discus.~ cd in the next section in relalion to 'ITL
•
797
798
•
INTEGRATED CIRCUIT TECHNOLOGIES
fiGURE 14- 21
! R,.
Open-
Res! of CMOS circuil
Resl of CMOS circUlI
~ Oo.'IPUI
~
Cb l With pull · up rL."is,or
Ca) Unconnec,ed o utput
Tristate CMOS Gates Tti state OUlputs arc available in both CMOS and 11'L logic. "Ille trishltc output combines the advan tages of the lotem-pole and open-coJlcclOr cirCllil s. As you recall, the three outpllt ~ tm cs arc HIGH . LOW, and high-impcd.mce(high-Z). When selected for normal logiclevel operation, as dClerminet! by the stale of the clwble input, illriS/ate d rcuil upe rates in the same way as a regular gale. When a lrislale circuil is selccled for high-Z uperat ion. the output is effeclively disconnCClCd from lite rcsi oflhecircuil by the imernal eircuilry. Figure 14-22 iIlustralcs Ihe operm ion of a lri s1ale cireui!. llle invcrtet!lriangle ('Il) designales a lrislale output. FIGUR E 14- 2 2
(~'n'l
The three Itates of a trilyte circuit I n GH
-fYo--
I0\\ ----=-r ! cruoblc )
LOW
LOW
-fYo--
,-
/
HIGI !
LOW----=-r
' ~~ IHGH
(Ui",t>/c)
lcnahlcJ
(a) Enabled for norma l logic op::ntl ion
(b) High·Z ~t:nc
Tlte t.:irt:uitry in a trislate CMOS gate, ~ shown in Figure 14-23, allows each of ll ,c OUlput tra nsistors Q, and Q2 to be lumet! otT at .he same lime, thus disconnecting the outpul from [he rest of the circuit. f iGURE 14 - 21
A tri,tate CMOS inverter.
[ npUl
:=t---
Oulp... ,
When the enable inpUi is lOW. the device is cnabled for nommllollie opcrmion. When the cnahlc inpUi is HIGH. both Q, and Qz arc off and the circuil is in the high-Z slate.
Precautions for Handling CMOS As you havc learned. all CMOS devict:s arc s ubjcct 10 damagc rrom cleclrosta.ie discharge (ESD). TIlereforc, they must be handlet! with special care. Revicw lhc followingprccautions:
TTL CIRCUITS
I. A ll CMOS dC\'ices arc shipped in conductive foam to prevent electrostatic
charge buildup. When thcy arc rcmovcd from the foam. the pins should not be touched. 2. 111e devices should be placed with pins down on a groundcd surface, such as a metal plate, when removed from protective nWlerial. Do not pl:lce CMOS dcvices in polystyrene foam or plastic trays.
3. All tools, test equipment , and mClal workbenches should be ea!1h-groundcd . A person working "ith CMOS devices should, in certain environmen ts, h,we his or her wrist grounded with a length of cable and a large-value series resistor. The resistor prevents severe shock should the person come in contact with a volt age source.
4. Do nDl insert CMOS devices (01" any other ICs) into sockets or PC boards with the power on.
5. All unused inputs should be connccted 10 the supply voltage or ground as indicated in Figure 14-24. If left open, an input can acquire electrostatic cJl
+v
H~odriog
1r;:'
uou-.ed CMOS iopub.
J'~"~~,
6. Afler assembly on PC bo.·uds. protcction should be provided by storing or shipping boards with their connectors in conductive roam . The CMOS input ,md Olltpu t pins may also be protected with large-value resistors connccted 10 ground.
I
SECTION 14 Z REVIEW
1. What type of transistor is used in CMOS logic? 2. What is meant by the term complementary MOS? 3. Why mu~t CMOS deo.'iccs be handled with GJre?
14-3
TTL CIRCUITS
The intemal circuit operlliion of TTL logic gates with IDlem-pole outputs is covered in this section. Also, the operation of TTL gates with opcn-colicclOruutputs and thc operation of tristate gates
•
799
800
•
INTEGRATED CIRCUIT TECHNOLOGIES
The Bipolar Junction Transistor The bipolar j unction Lra nsistOf" (B.l1') is thc acti ve switching c1CI1'lCnl uscU in alllTL cir-
cuits. Figure 14-25 shows the symbol for UlI npn BJT wilh its three !elm inals; base, emitter, and collector. A BJT has two junctions, the basc-emiuer junct ion and the base-collector junction. FIGURE 14- 25
The symbol for a BJT.
Emitter (i ~)
Thc basic switching operat ion is as follows: When thc base is approximatcly 0.7 Y more positive lhan the elll itter and whell sufficient current is provided into the basc, the transistor turns on and goes illlo s
+Vu;
The ideallwitching action of the BIT. Conventional current direction il Ihewn. Electron flow notation i, oppo!ite. ,I
ON
:=
I"
l
(w) Saturatoo ION) transi~t()l' and ideal switch CQlJj~lItclll
+vcc
0\
=
OIF
1f
(b) OFf' transistor and idCIIJ sw itch equivalen.
TTL Inverter T he logic fu nction of an invener or any type of gatc is always the same, regardless of Ihe type of circuit technology that is used. Figure 14-27 shows a standard TIL circuit FI){' an invencr. In this figure QJ is the input coupling trn nsistor, and D. is thc input clamp diode. Transistor Q1 is called a pllllse splitter, ,md the combination of QJ Hnd Q4 forms the output circuit often referred to as a totem-pule arrangement. Wht:n the inpul is a HIGH. the bmic-emiucr junc!ion of Q. is rc\'crse biased, and the mlsc-collector junction is forward biil~. This condition pcmlits current th rough RI and the base-collector junction of QJ into the base of Q~, thus driving Q2 into saturation. As a result. Q3 is tunKXI on by Q2' and its collector voltage, which is the output. is ncar grou nd potent ial. We therefore have a LOW output for HIGH input. At the same time, the collector of Q~ is at a sufficiently low voltage levcl to keep Q4 off. When the input is LOW, the basc-emitter junction of QI is forward niascd. line] thc basecollector junction is re\'crsc biased. There is curre nt through RJ Hnd the ba...c-emilter junc-
,I
TTL CIRCUITS
•
FIGURE 14- 21
A d 3nd3rd m inverter circ:uiL
R,
R,
R,
F L6kn
4k0
l)O 0
>-Q ~ +
D,
~
rilpUI
V ~ Q,
OuIPUI
>-
~ Q,
D,
R, 1.0 Hl
tion of QI 10 the LOW inpul. A LOW plUvidcs 11 path 10 gro und fOf the curren t. lllerc is no it is off. The collector of Q2 is HIGH, thus lUrn ing Q4 011. A sat urated Q4 prO\'idcs 11 low-rcsiSlimcc path from Vee to the output; we Ihcrcforc havt: a HIGH all the output for a LOW on the inpul. AI the same lime, Ihccmillcr of Q2 is ill ground polcnlial, keeping Q3 otT. Diode Dr in thcTTL circuit pfC\'cnls ncgmivc spi kes ofvo [lHgc on the input From damaging Q•. Diode D~ ensures lhal Q.I will rum offwhcn Q! is on (HIG H input). Inlhis COIldit ion, rhe col1cclOr voltage of Q! is cqu,I I IO rhe basc-lo-cl11iller vullage, V Blo• of QJ plus the collcctor-to-emitler vohage. Va. of Q 2' Diode D 2 provides an addiliomll VBE equivalent drop in series with the basc-emiller junction of ~ 10 ensure its lurn-offwhen Q! is on. The operation of the lTL inverter for the two input states is ill ustrmcd in Figure 14-28. In the circu it in part (a), Ihe base of QJ is 2. 1 V .tOOve ground. so Q2 and Qj arc on. In the circuit in part (b). the ba'ie of QJ is aboul 0.7 V above grou nd- not cnough to IlIrn Q2 Hnd QJ o n. CUlTcnt info the oosc of Q2' ':;0
.5V
(-;::==---r--:-----, + 5 V .~
R,
RCI·CN." .-""
bin' HI GH
I
~
1'\' Ql
.V I "' V
l
_ 1I7V
t--..
'
or-;
V'" "
0.7 V
OR 0,
1
V A'
R.
O.7V
~
Q,
OV
~ OH
-=
-L
('J
V'"ON D,
" D,
R,
+---- --[1--. - - Q, ....- Or F
t-- l O\\ Q,
D,
L
R,
R,
(bJ
FIGURE 1 4 - 28 Oper;)tion of ;) m ;nvertef.
TTL NAND Gate A 2-input rrL NAN D gale is shown in Figure 14-29. BasicH lly. il is the same as thc inverter circuil except for the additional input emitler of QI' In lTL technology mu lti ple-em itter
HIG H
801
802
•
INTEGRATED CIRCUIT TECHN OLOGIES
FIGURE 14 - 2 9
+V{.T
A m NAND ~ te circuit.
H,
H,
R,
4 \;,11
U)kU
n" V ....Q,
J, Q,'\
Input A Illpul/J D,
I),
....Q,-
- - - Output ....Q,
o~
R,
I.OHl
ImnsislOrs afe used for Ihe input devices. These mu Uip1e-e miner pared 10 Ihe diode arra ngement, as shown in Figure 14-30.
can be com-
D
" D,
"
Ira n s i ~ l C1r.~
C
E~
"
D,
--~.---~--~--~- c 01
E
FIGURE 14- 30
Diode equivalent of a m
mul tipl~mitter
transistor.
Perhaps ),ou can undefsland the operalinn of this circuit beller b), v i ~ua li z i ng Q I in Fi gure 14- 29 replaced b), the diode arra ngt:mcnt in Figu re 14-30. A LOW on either inpul A Of input B forward-bi ase .. the respect ive diode and reverse-biases D J (QI basecollector j unct ion) . This aelion keeps Q1 off and res ults in a HIGH output in the same W'I ), as described for Ihe 'IT L invener. Of COUfse, a LOW on bot h inputs w ill do the same thing. A HIGH on both inputs rc"erse-bia..cs both inputdiodcs and forward-binscsDJ (QI bnsccollcctorj unction). This action turns QJ on and res ults in a LOW output in the S,Hlle w,ly as described for lhe TIL invel1er. You .~hould recognize th i .~ operation as Ihat of the NA ND function: The OUlp ut is LOW onl y if all inputs are HIGH.
Open-Collector Gates l1lCTTL galt"S described in the previous sect ions al l had the totem-pole OUlput circuit. Another tYIX' of output avai lable in TTL integra/cd circuits is the open-collector output. This is compamble to the open-dmin output of CMOS . A standa rd TTL in\'el1er wit h an opencollector is shown io Figure 14-3 1(a). The other Iypcs of gates are also avai lable with opcncollector outputs. Notice Ihat the output is the collector of Imnsislor Q~ wil h oOlh ing connected to it, hence the name open (-"o lleetor. In order to get the prope r HIGH lmd LOW logic levels out of the circuit, an external pull-up resistor \TIust be connected to Vcr from the collector of Q" as shown in Figure 14-3 I(b). When Q, is off. the out put is pulled up to Vrc Ihrough the external resistor. Whe n QJ is on, the output is connected 10 ncar-ground th rough the salUraled IransislOr.
TTL CIRCUITS
R, I.j'ij..n
4W I"JlUt
_~_
_
803
r-----1-------t----O +vcc
r-- --"t--------o+voc R,
•
R (c.>.lemal )
,lQ,
Inl'lII -
./ - 4 --
O,n""
/) ,
D,
(HI Opcn-cQllect"r inwncr circuit
(bl With eXlCmal pull -up
r~istor
fIGURE 14- 31
m
inverter with open-collector output.
FIGURE 14- 32
Open-collector symbol in
'Illc ANSI/IEEE slarKIard symbol Ilml designillcs an open-col1cctor output is s hown in Figure 14- 32 for an ill\'CIlcr and is the same for an open-drain output .
Tristate TTL Gates Figurc 14-33 shows Ihc basic cireuil for a TTL trisl;:lte inverter. When thc cn
+l 'cc
R,
,,""
~
R,
R,
"Q,
/),
~
R,
D,
Q,
I v:Q ,
f--
0u1rul
v:
"Q,
~R,
1 FIGURE' 4 - ll ~\ic
triltate
i~rter circuit.
FIGURE 14- 34
An equivalent circuit (0, the tri,tate output in the high-Z !tate.
804
•
INTEGRATED CIRCUIT TECHNOLOGI ES
Schottky TTl The basic or standard TTL NAND 2a1e cireuit was discl1 s~d earl ier. It is a currcnl-sinking type of logic that draws curren! from the load when in the lOW out pul 1)tate and sources negligible current to the load whell in the HIGH out put stalC. Most 'lTllogic used tooilY is somc foml o f Schottky 'ITL, which provides a fastcr switching time by incorporati ng Schottky diotles to prevcnt thc transistors from going into satur-.lt ion. thcreby decreasi ng the time for a transistor to tum on or off. Figure 14-35 shows a Schollky gate circuit. Not.ice the symbols for the Schon ky IransislOr imd Schottky diodes. Schotlky deviccs arc desigllilted by an S in their Pillt number, such as 74S00. Othcr types of Schottky " TL arc low-power Schonky dcsignaled by LS. advanced Schonky designated by AS, advanccO low-power Schottky designmcd by ALS, and filst designated by F.
r----t--------1~--O
R,
n,
2.8k O
9000
'\ -
lnpu l ll ~.-'rQ .' , Inpul H
- [
R,
- -\---+
_
3.5 kO
+vcc
+-__
Oulpul
r-,.Q, R,
soon
R.
,so 0
fiGURE 14- 35
Schottky TTL NAND gate.
1. An npn B}T is on when the wse is more negative than the emitter.
(T o r F)
2. In te rm~ of iwitching action, what do the on and off states of a BJT rEpresent? 3. What .are the hvo m.ajo r types of output circuits in TTL? 4. Expl.ain how tri~ta te logiC diffen from no rmal, two-st.ate logiC.
14-4
PRACTICAL CONSIDERATIONS IN THE USE OF TTL Ahholl1;h CMOS is the more predominant IC Icchnolo1;y in industry and commercial applications. TIL is still uscO. In edUGltional applications, T rL i~ usually preferred because il docs not have the handling rcstrictions Ihal CMOS docs due 10 ESD. Bcc.msc of thi!., scveral pr,lclical considerations in Ihe usc and :lpplication of TTL circuits will be covcred using standard lTL for illuslmlion.
PRACTICAL CONSIDERATIONS IN THE USE OF TTL
Afler completing this section, you should be able to
_ Dc~ ribc current !>jnking and currelll sourci ng - Use;m open-collcctor circuit for wired-AN D operat ion _ Dc.~cribc the effects of connccti ng two or more tote m-pole outputs _ Usc opcn-colla:lor gates to dri ve LEOs and lamrs - Explain wha. to du w ith unused TTL inputs
Current Sinking and Current Sourcing Thc concepts of clirrent sinking and current sourcing were introduced in Scction 14- 1. Now th,lI you arc familiar with Ihe lotcm-polc-output ci rcuit configuration used in -n1.. leI's look closer at the sinking ;tIld sourcing ac tion. Figure 14-36 shows a standard -ITL invcrter with ;) totem-pole output connected 10 Ihe input of anothcrTI'L invcrter. When the dri ving gate is in the HIG H outp ut stalc,the driver
+,v R,
R,
R,
R,
V-
o-P'
7
'''PUI
V-
...8'
'Il l'" .j.{)pA
YQ,
OFF
R.,
R,
A'
'h
Q,
Q,
+, V
D,
T
Q,
Q,
HIGH
Output
.-~Q,
OFF
f),
D,
R,
R,
(a) OlITCnI sourcing (Jil t laJUC is max imum)
--0 +5 V
R,
R,
+SV
R,
R,
~R,
.-
V-
...8'
1--84 OFF
7
Input
"'"
Q,
111 _:0 1.6mA
D,
Q,
V.
•.p, D,
Q,
LOW
D, OutpUI
Q,
V.
ON
....Q, R,
-~
(bJ Current sinking (IlL l'>!lue is maliimum)
CUffe nt linking and lourcing action;n TIL
T D,
R,
FIGURE 14- 36
ON
R,
--
_
805
806
•
INTEGRATED CIRCUIT TECHNOLOGIES
is sourcing currcni lO the load. as shown in Figure 14--36(a). The input to the load gate is like a fCverse-biased diode, so there is practically no currenl n:quired by the load. Actually, since the input is nonideal. there is a maximum of 40 pA from the tOlem-pole output of the dliver imo the load gale input. When the driving gale is in the LOW output state. the driver is sinking current from the load, a~ shown in Figure 14-36(b). This current is [.6 rnA maximum for standard TIL and is indicated on a data sheet with a negative value because it is 0 111 of the input.
When a lTL NAND gate drives fi ve ITL inputs. hem' much current docs the driver output source, and how Illuch docs it sink? (Refer to Figure 14-36.) Solution
Total source current (in HIGH output state): f IH ( ...... ) = 40 J.lA per input I T(_-c)
= (5 inputs)(40 J1.A/input ) = 5(40J.lA ) = 200 p.A
Total sink current (in LOW output state): 11L(mo.»
= -1 .6 rnA per input
IT{..nt ) = (5 inputs)(- 1.6 mAj inpul ) = 5(- 1.6 mAl = - 8.0 rnA Related Problem
I
Repeat the calculation... for an Ui TIL NAND gate. Refer to a data sheet all the Texa.s Instruments CD-ROM.
EXAMPLE 14-4 Refer to the data sheet on the Tcxa<; Instruments CD-ROM. and detennine Ihe fan -uul of the 7400 NAND gale. SoiutiDn
According 10 the data shcel. the current parameters are as follows:
40 J1.A
IIH(""", ) = lILt ..... )
= - 1.6mA
IOH{"",.) =
-400 J1.A
l OU""",) = 16mA
Fan-oul for the HIGH output state is calculated as fo llows: Current /c.!!!...",. is the m:Jximum current I.hat the g:Jtc can source to a load. Each load input requires an ' IHEm:,",. ) of 40 ILA. The HIG H-stale fan-out is
/ I
I
OH .. ) -(",- 400 J.lA - 10
I !II(""', )
40 J1.A
For the LOW output state. fan-out is calculated as fo llows: 10..1."",," ) is thc maximum CllITCnllhat the gate can sink. Each load input produce., an fl u"'.. 1of - 1.6 mAo The LOW-state fan-out is /000{nWl l 16 mA 1 ["",) = 1.6mA = 10 1 11
In this ca<;e both the HIGH-state fan-ou t and the LOW-state fan-out arc the same. Related Problem
Determine the fan-nut for a 74LSoo NAND gatc.
PRACT ICAL CONS IDERATIONS IN THE USE OF TTL
•
807
Using Open-Collector Gates for Wired-AND Operation The ouipUIS of opcn-collcclor gales etm be win..'1i together 10 form what is called a wiretlAND conligurmion. Figure 14-37 ill ustrates how fou r inverters arc connected to produce a 4-inpul negative-AND gale. A sing le external pull-up resistor. RIP is required in illl wircdAND cir(;ui t.~ . FIGURE 14- 37
+5 V
A wired-AND configuration of four inverter!.
R, A
H
X ", ABC!)
c--+-f n~
When one (or more) of the inverter inputs is HIGH- the ompul X is pulled LOW oceause an outpul transistor is on and aclS as a closed switch 10 ground. as ill ustrated in Figure 14-38(a). In this case only one inverter has a HIGH input, but this is sufficient to pull the output LOW through the saturated output transistor Ql as indic3led.
"y
+5Y
~
H,
HIGH
Open-collector wired negative-AND operation wfth i~rten_
R, LOW
ON Q,
Oft-
1.0\'1'
LOW
LO~
Lo\\
f---HIGH
LOW
Q.
(]I' more oulpul on. the OI.l!put i> LO W.
(:I.) When one
l mnsisto~
arc
(b) When all oulpUllf".U1Si~ loo; arc 011". the OUlput is I·UGH.
For the output X to be HIGH, all inverler inputs must oc LOW so that all the opencollector oulpU I transistors are ofr. ilS ind icaled in Figure 14- 38(b). When this condition ex ists. the output X is pulled HIGH throug h the pull-up resistOr. Thus, the output X is HIGH o nly when (II/ the inputs arc LOW. There fore. we have a negative-AN D funclion. as expressed in the fo llowi ng equation:
X = AB C D
FIGURE 14-38
BOB
•
INTEGR ATED CIRC UIT TECH NO LO GIES
I
EXAMPLE 14-5
Write the output expression for the wired-AN D confi guration of open-collcctOr AND gales in Figure 14- 39. FIGURE 14-39 + Va:
.. -
.,--"
8 - <_
/
r - .,--"
~~ =:;:::::::: t---o X
~ ==~
H - <_ /
Solution
T he Output expression is X = AHCDEFGH
T he wired-AND connL'(:lion of lhe four 2-input AN D gatl:$ creates an 8-input AND gate.
Related Problem
I
Determi ne the output expression if NAND gates arc uscd in Figure [4-39.
EXAMPLE 14 6
T hree open-collcctOr AND gates are connected in a wired-AN D configuITu ion as shown in Fig ure 14-40. Assume that the wired-AND circuit is dri ving four standiu"d TTL inputs ( - 1.6 mA each). (a) Wri te the logic ex pression for X.
(b) Determine the mi nimum value of HII if 101 .1.1"'1» for each gilte is 30 rn A ilnd is 0.4 v.
+,v
FIGURE 14- 40
A -
.,----.
8 -
'----'
~ =II)-1~---O X
"-
.,--"
F -
'----"
VOU mIlI<,
PRACTICAL CONS IDERATI ONS IN THE USE OF TTl
Solution
•
809
(a) X = ABCDEF
(b) 4( 1.6 mA) = 6.4 mA
I R • = /OI..(n",,) - 6.4 IllA = 30 IllA - 6.4 rn A = 23.6 mA Rp =
Related Problem
Vee - VOL(~l IJI~
=
5 V - 0.4 V 23.6mA
=
195 n
Show the wired-AND cireuit for a IO-input AND funct ion using 74LS09 quad 2-input AND gates.
Connection of Totem-Pole Outputs Totcm-pole outputs cannot be connected togedler because such a connection might produce excessive currcnt and result in damage to the devices. For example, in Figure 14-4 1, when Q J in device A and Q2 in device B arc both on. the out put of device A is effectively sho11ed 10 ground through Q2 of device B.
y
K
Tatem-pole autputs wired together.
Such a connection may caUie
of
0'
R~'
01 circuit
1
l Q,
~OFF
... FIGUR£ 14- 41
+5V
+5V
'
,,>-
cxcc!$ive current through 0 1 af device A and Ol af device Band lhould never be u!ed. Hcsl
0'
circuit
ON
B
A ~
~
Open-Collector Buffer/Drivers A ITL circuit with a totem-pole output is limitcd in the amount of currenl that il can sink in the LOW state (/01..("""') to 16 rnA for standard TfL and 8 rnA for LS lTL. In many special applications, a gate must drivc extcrnal devices. such as LEDs. lam ps. or relays, that may require more CUlTcnt than that. Because o f their higher voltage and current-handling capability. circu its with opencollector outputs arc ~cnera ll y used fordri v in ~ LEOs, lamps, or relays. However, tolempo le outputs can be used. as long as the output currcnt req uircd by the external device docs not exceed the amount that rhe TTL driver cun sink. With an open-col1cclorTIl gate, the collector o f the outpul transistor is connected to un LEI) or incandescent lamp, as illustmlcd in Figure 14-42. In part (a) the limitillg resistor, RI; is USed to keep the current below maximulll LED CUIl"CnI. Whcn the output of the !,"!ate is LOW, the outpuT transistor is .sinking current, and the LED is on. The LED is off when The output trilnsistor is o iTilnd the output is HIGH. A typical open-collector buffer gate can sink up 10 40 mA. In plU1 (b) of the figure, the lam p requires no limiting resistor because ~ he fii
8 10
•
INTEGRATED CIRCUIT TECHNOLOGIES
+,v
+,v
J
NO
t; U I T~ nL
HIG H IIIGIl -
..-_____
LOW
-L_/
LOW = D - - 1 OR-
l
X
HIG H
(a) Driving;ln LEI)
+20 V
+20 V
I
+20V
~
No
cun.... '"
~ =rv-l
HIGII -
-r-,
LOW -
HIGII -
-L_/
X -
"
HI GH
'----'
(b) Drivin1! a I""".cu rren! lamp
FIGURE 14- 42
Some ;application\ of open-collooor d river!.
I
EXAMPLE 14 7
Determine Ihe value of the limiling resistor, Ru in the open-collector circuit o f Figure 14--43 jf the LED current is to be 20 rnA. As~u m e a 1.5 V drop acro~s the LED when it i ~ forward bia<;ed and a LOW-~tate o utput voltage of 0. 1 Vat the output of the gate. FIGURE 14 - 41
Solution
VR, = 5 V - 1.5 V - 0. 1 V = 3.4 V R = I.
Rela ted Problem
Detemline the value of the
VRI.
I
= 3.4 V = 170 n 20 rn A
li mitin~ re~ist or.
Ru ifthc LED requi res 35 mAo
Unused TTL Inputs An unconnected input on a 1TLgateact ~ as a HIGH because an opcn i nputTd;uh ~ in arevcffiCbiased emiller junction on the inpul lra ns i.~tor. j ust as a HIGH level does. This effCCI is illustrated in Figu re 14-44. However, because of noise sensitivity, it is best not to leave unused TIL illput<; uneonnccled (open). TIx:re arc several allcmalive ways to handle unused inputs.
PRACTICAL CONS I DERATIONS IN THE USE OF TTl
+SV
-
HIGH
Co mparison of an opt!n
1---- -oJ---
m
and a HIGH-level input.
Rcn:~-biascd
diode is lik.c an open
Diode cquh:lknt cm illcr jUllI:lion wi th urll,:onnet:ted inptrt
Tied- Together Inputs The mOSI common method for handling unu~ed gate inputs is to connect them to a used input of the same gale . ror AND gates and NAND gmes, all liLxitogcther inpul<; cou nt as onc uni t load in thc LOW state ; but for OR gates and NOR gates, each inpllt tied 10 another input cOllnts as a separale unilload in the LOW state. In the HIGH state, each tied· together input cOun l.~ as a separate load for all types of TIL gates. In FigufC 1 ~5 (a) arc two examples of the connection of two unused inputs to a used inplit.
~:J
=;-:::J ?'-,,,-'--~ Tn" unu'-<:Illllptot, connected to .>lIC u...."d input This
~onllCClion ~11\l. 11."
I unit lood in LOW ~1 3!C 3 unil loads in HI GH ~Iale
~~~
>-
--;::§
"
T"o unu..ru in.,...t' <"
OIlC u~
input
~"Onnection ~·"O.m ts ~s;
3 unit load.' in LOW stntc 3 unit load.~ in HIG H StnlC
(a, TIcd-tOI1Clhc r illptlLS
+,
V
1.01..0
Unu....-Il (b) lopuis 10 Vee o r grotlnd
Ie)
I n puI~
811
.. FIGURE 14-44
+5 V
or
Tn. inpllttran\i~tor
•
Cnuxd input
Unm;ell input
HIGH
LOW
gnl~
10 u !ltlo;cll o utput
FIGURE 14- 45
Me thcxk fOr Nnd/ing unuS<:ld m inpuh.
The AND and NAND gatcs present only a sing le unit load no mallcr how many inputs arc tied togelher, whereas OR and NOR gates present a unit load for each liLxi-togcther inPUI. Thi ~ is because the NAN D gale uscs a mUltiple-emiller input transistor; so no mallcr how many inputs are LOW. the total LOW-statc currcnt is limitcd to a fi ~cd valuc. TIIC NOR gate uscs a separate transistor for eileh input; therefore, thc LOW-stilte currcn! is thc sum of the c urrcnts from allihe tied-together inputs.
Inputs to Vee or Ground Unu sed inputs of AND and NAND gales can be l.'Onneeted to Vee through a 1.0 ill resistor. lliis connection pulls the unused inputs 10 a HIGH level . Unused inputs of OR and NOR galcs can be connectcd 10 ground. These mcthods are illustrated in Figure 14-45(b).
Unu",,11
~:lIC
input
81 Z
•
INTEG RATE D C IRC UIT TECH NO LOGIES
Inputs to Unused Output A third method of terminati ng unused inputs may be appropriate in some cases when an unused galc or inve rtcr is avai lable. The unused g.ate output must be a COllstilnt H IGH for un used AND and NAND inputs and a constant LOW for unused OR and NOR inpu ts, as illustmtcd in Figure 14-45(c).
I
SECTION 14- 4 REVIEW
1. In whClt output ItClte does a TIL circuit sink current fro m a load? 2. Why does a TIL circuit source len current into.., TTL load than it sinks? 3 . Why can m circuits with totem-pole outputs not be co nnected together? 4. What type of TTL circuit must be used for a wired-AND configuration? 5. Why type ofm circuit would you use to drive a lamp? 6. An unconnected TIL input acts as a l OW.
14-5
(T or F)
COMPARISON OF CMOS AND TTl PERFORMANCE In this section. thc main operational ,lOd pt!rformmu;c characteristics of selccted CMOS serics arc compared with those of the major lTL scries and with BiCMOS. Afte r completing this section. you should be able to • Compare TIL (bipolar). SiMaS. and CMOS devices in terms o f prop.:'lg3tion delay, maximum clock frequency, power d issipation. and drive capability
In the past, the superior characteristic oflTL (bipolar) compared to CMOS wa.<; its rd · atively high speed and output current capability. Today, these advantages of TTL have diminished to the point where CMOS is often equal or superior in many arCll<; and has become the dominant IC teChnology, although TIL is still available and in usc, as you know. One fam ily of IC logic devices, SiCMOS. combines CMOS log ic with T TL output circuitry in an effort to combine the advantuges of both. Table 14-1 provides a comparison of the performance of scverallC logic families. TABLE 14- 1
CompariIDn of so:lt:cted performance parameten of Ievt
BIPOLAR (TTL) F ·
Bi("MOS
LS
.- A: l
ART
3.3
10
7
3.'
145
33
45
6
2.2
1.4
~C -
---- -- -._---------CMOS
-
LV
3.3 V LVC
3.7
9
4.3
3
IW
170
90
100
150
2_75
0.55
2.75
1.6
0.8
0.8
4
24
8
12
24
24
5V
A<
AHe
7
5
150
50
17
64
I
ALVC
S"",d G~le prop~galion
delay. /" {IL~J IT maxim um clock freq . (MHz)
Powe r DissiF"'til)n Per Gale Bipolar; 5O'.i: de (mW) CMOS; quiescent (j:lW) Output Drive la . lmA)
20
8
8
EMITTER-COUPLED LOG IC (Eel) CIRCU ITS
I!I!II!I!II!II-- --
--
1. Wh.Jt is a BiCMOS circuit7
Z. In general, what is the main advantage of CMOS over bipolar (TIL)?
14- 6
EMITTER - COUPLED LOGIC (ECL) CIRCUITS
Eminer-collpJcd logic. li ke r rl, is a bipolar technology. The typicul ECl circliit cons ists of a differen t amplifier inpUi ci rcuit, a bia<; circuit, and emitter-follower outputs. EeL is much faster than TTL because the transistors do not operate in saturation and is used in more specialized high-speed applications. After completing this seclion, you should be able to • Describe how EeL differs from TTL and CMOS . Explain the advantages and d isadvantages of EeL
An Eel, ORINOR gate is shown in FigufC 14--46(a).111e emitler-foJiower outputS provide the OR IOf!ie function and its NOR cOlllplemelll, a~ indicated by Figure 14-46(b). Dill creUliul
__-"C',=",,;p,:I~C'= ;"C ""='O '_ _ ,--
"mp!iticr ,("
,
,
Ilia' ci l\:uil
C"111p1 ~menlm)
l'U1r U1 , , ,c_':':I:'-_,
r---t-i:-i-i~-<: OR ~)\,tput
tt----t~-lr:..----c NOR tll ,IPUI (b)
i +___I ____+ _ + _-o
L + ....--I....__
VEE
(-5.2 V)
,A
"
c
,,) fiGURE 14 - 46
An fa OR/NOR gil te drru il
Because of the low output impedance of the cm iUcr-follower and the high input impedancc of thediftcrentiul amplifier input, high fan-out operation is possible. In this Iypcofcircuit. saturation i.r.: not possible. The lack of sHturation results in higher power consumption and li mited voltage swing (less than I V), bllt il permits high-frequency switching. The Vee pin is normally connected to ground, and the VI,E pi n is connected to -5 .2 V from the power supply for best operation. Notice that in Fif!ure l4-46(c) Ihe output varies from a LOW level of -1.75 V to a HIGH level of -O.~ V wilh respect to ground. In positivc logic a J is Ihe HIGH level (less negative), and i.I 0 is the lOW level (more negative).
- 1.4 V
,,)
- 1.2 V
tnpul ,·ohase
•
813
8 14
•
INTEGRATED CIRC UIT TECHNOLOG IES
Noise Margin As yuu have learned. the noise nwrgin o f agatc is thc mcaSure of il.~ immunity to undesired voltage fluc tuations (noise). Typical Eel circuits have noi se margins from about 0.2 V to 0.25 V. These arc le~s than for TrL and make Eel less sui table in hi2h-noiscenvironmenLs.
Comparison of ECL with TTL and CMOS Table 14-2 shows a comparison of key performance parameters for F, AHC, and EeL.
TABLE 14- 2
Comp<'l ri'lOn of ECL ieries performance porameh,n with F and AHC.
!
BIPOLAR (TTL) F
I
CMOS AHC
BIPOLAR (ECL)
3.7
0.22- 1
s"""
Ome propllglltion
dekly" l' ( ns)
3.3
FF mu ximu/ll
dock freq. (MRd
145
170
330-2800
Power Dissipation Pcr Outc Bipolar: S(N. de CMOS: quiescelll
- I SECTION 14 6 REVIEW
2.5jJ.W
1. What i~ the primary advantage of Eel over TIL? 2 . Name
14- 7
25 mW- 73 mW
8.9mW
I.\l.1o
disadva ntages of Eel compared with TIL
PMOS, NMOS , AND E'CMOS The PMOS and NMOS circuits arc used largely in LSI funct ions, such as long ~hift registers. large memories. and microprocessor prooucts. Such use is a result of the low power consumption and very small ehi p area required for MOS transistors. E2CMOS is u~ in reprogrammablc PLDs. After completing this section, you shou ld be able to • Deseribe a ba<;ic PMOS gate . Describe a basic NMOS gate . Describe a basic E~CMOS cell
PMOS One of the first high-density MOS circuil lcchnologies to be produced was PMOS. It utilizc.<; enhanccmcnt-mooep-chan nel MOS transistors ro form the basic gale buildin" blocks. Figure 14-47 shov.'s a ba<;ic PMOS gate lhat produces the NOR function in posj ti~e logic.
PMOS, NMOS, AND eCMOS
FIGURE 14- 47
Billie PMOS g"te.
"-------'I,g, InptlL'>
.----oJ 1
The opcmtion of the PMOS gate is as rollows: The supply voltage V(;(j is a negative voltage, and Vee is a positive voltage or ground (0 V). Transistor Q ) is permanentl y biased to create a constant dmin-tQ-source resistance. Its sole purpose is to r unction as a current-limiting resistor. If a HTGH (\fcd is appl ied to input A or B. then QI or Q~ is oll, and theoulput is pulled down 10 a voltage near \f0(;. which represcnl~ a LOW. When a LOW vollage (\10(;) is applied to both inpul A and input B, both QI and Q, are turned on. This cau~.~ the output to go to a HIG H level (ncar Vee). Sincea LOW output occurs when citheror both inputs arc HIGH. and a HIGH output occurs only when all inputs arc LOW, we have a NOR gate.
NMOS The NMOS devices were developed as processing techno logy improved. The ,,-channel MOS tra nsistor is uscd in NMOS c ircuits, as shown in Figure 14-48 ror a NAND gltle and a NOR galc.
FIGURE 14- 48
Two NMOS gat~
t -- -- - Ompul
,.."J:fr;,J9
Q
vCoG or Ground VUGor grou nd
(n) NAND
{!l)NOR
,
•
815
816
•
INTEGRATED CIRCU IT TECHNOLOGI ES
In Figure 14-48(a). QJ Olcts as
E' CMOS E 2CMOS (electrically crasable CMOS ) technology is based on a combination of CMOS anti NMOS technologics and is used in programmable devices such as PROMs and CPLDs. An E~CMOS cell is bui lt around a MOS transistor with a nouting gate that is externally charged Or discharged by a small programming current. A schematic of this type of cell is shown in Figure 14-49. FIGURE 14- 49 Bi! line
:.....----H_-§
\\,,,,1 C ' c...
Cell ~r""nd
- - -+--
When Ihe noating gate is charged toa positive potential by removing electrons. the sense: transistor is turned on, storing a binary .....ero. When the noat ing gale is eh3rged to a negative potcntial by placing ele(..1rons on it. the scnsc transistor is turned off. storing a binary I . The control gate controls the potential of the tloating gate. The pa<;s transistor isolates the sense transistor from the array dOling read and write operations that use the word and bit lines. ll1e cell is programmed by applying a programming pulse to either the control gate or the bit line of a cell that has been seJected by a voltagc on the word line. During tho.: programming eyelc.thc cell is first erased by applying a voltage to the control gate to make the naming gate negative. 'Inis leaves the sense transistor in the off state (storing a I). A write pu lse is applied to the bit line of a <:ell in which a 0 is to be stored. This will charge the lloat~ ing gate to a poillt where the sense transistor is on (storing a 0). T he bit stored in the cell is read by sensing presence or absence of a small cell current in the bit line. When a I is stored, there is no cell current becausc the sense transistor is o ff. When a 0 is stored. there is a small cell current because the scnse transistor is on. Once a bit is stored in a cell, it will remain indefinitely unless the ccll is erased or a new bit is written into the cd l.
I
SECTION 14 7 REVIEW
1. Wh
KE~
•
TE RMS
•
817
Pomm/ali: J4-J
V"'II = \'011/",",1 - VII«nIin1
High-level no ise margin
14-2
VNI. = Vn.''''''' 1 -
u )w-Ievel noise margin
IO_"'H
+
Vou""",)
leu
2
Avenlge de supply current Power d is.~i pali on
•
KEY TERMS
T()(em-poJc outputs o f"n 'L can not be conncctootugcther.
•
Open-coUcctor and open-drain out puts can be connl'Ctcd for wi red-AN D.
•
CMOS devices offer lower po'>ver dissipl1tion thim ;IIlY of the TIL seri es.
•
A rrL device is nOt as vu lnera ble 10 elcctrostalic di sc harge (ESD) as is a CMOS device.
•
Becflusc of ES D, CMOS devices must be ha ndl ed wilh greal care.
•
EeL is Ihe faslesllYPC of logic circuit.
•
E1CMOS is used in PRO Ms and olher I'Ll:>:..
Key terms and other bold terml in the chapter arc defined in the cnd-of-book glOSS
/t-
C urrent sinking The '1ction of a logic circuil in which it accepts cunen! inm ilS oUtput from C urrent sourcing The aclion of a logic ci rcui t in wh ich il send s cu rrent from
it ~
11
loud.
outpul to a load.
ECL Em iller-co uploo logic; a c1a~s of integratoo logic circuits th ai afe implemented wi lh nonsaluTllti ng bipolar j uncti on transistors. E J C1\IOS Electricall y erasable CMOS: Ihe IC technology used in prognmmmhie logic devices ( PLDs). Fanout "111e number of equiva lem gl1te in puts o f the sa me fumily series Ihat a logic gll te can drive. NoiSt) immunit y The abi li lY of a logic circuit to rejcct unw
A Iype of ou tpul for ;1 TI'L ci rcui t in whi ch thc collector of the ou tpu t trans istor is left internall y disconnectoo a nd is l1\'u ill1ble for CQ llIlection lO an externlll locd th ai requires relativel y high curren l or volt age. Pow~r dis.~ilmti0I1111e
prod UCl of the dc supply voltage and Ihe de su pply current in
cire uil . ProlJllgalion delay time "111e timc interval between Ihe occurrence of an inp.H tnUlsiti on and the OCCI1ITenCe of the corrcspondi llg ou tpu l lransition in a logic c ircuit. P ull-up n.'Sis lor A rc.~ i stor wit h onc e nd connected 10 th e de supply vo ltage poinl in a logic circuit HI GH when in the inlleti\"e st
u.~ed
10 keep u g ivcn
Tolem pole A type of output in l T L circu its. Tristute A type ofoul put in logic C.rrc uils thaI exhibits three states: HIG I·1. LOW, tlnd hi gh Z rrL Transistor-Irtmsislof logic: a type o f i111egmled c ircui l tlUl1 uses bipolar j unction tmns istors. Unil load A measure of fan-out. O ne gide in put represents a lInit load 10 a dli ving gale.
818
•
INTEG RATED CIRCUIT TECHNOLOG IES
Answers arc at the end of the I. When Ihe fn:
(b) increases
(e) docs nO.[ e h.mge
(d) dCcrellses exponentiall y
2. CMOS operatcs more n::Jinbly th un l TL in a hig h· noise environment hecausc of its (a) lower noise rna,!!in
(b) input capacitance
(c) hig her noise margin
(d)
smaller power d issipation
3. Proper handl ing of a CMOS device
j.~
nL>ccssary because of its
(b) high-noise immunity
(a) fragile construct io n (e) susce ptibi lity to
elcctrosliltic discharge
(d) low powc r dissipa tion
4. Which of the fo ll owing is nOl II TIL cirellit'! (a) 74FOO
(b) 74ASOO
(e) 74HCOO
(d) 74ALSOO
S. An open TIl.. NOR gatc input (II)
acts as 11 LOW
(bl
(e) shoold be grounded
(d) s ho uld be con nected to Vee th rough a resistor
(e) answer.> (b) and (e)
(0
H n swcr~
(a) and (e)
6. An LS ·IT L g mc can drive a maximum of (a) 20 uni t loads
(b) 10 unil loods
(e) 40 unillOllds
(d ) unlimilcd unil loods
7. If Iwo unused inputs of a LS TIL gale are connccted II) a n inpUi heing driven by mu){ her LS TIL gale, lhe lI)lal number of remain ing un it loods thai can be drh'cn by this gale is (a) scvcn
(h) eight
(c) SCVClltL"C1l
(d) Wllimitcd
8. T hc main advantage of ECl ovcr TIl or CMOS is (II)
ECl is less e xpensive
(e)
Eel... is !\\'ailablc in " greater
(b) ECl conslimes Il!ss powcr \~Jridy of circuil types
(d) EeL is fas lc r
9. ECl cannot be used in (a) high-noi se environme m s
(b) damp cnviron ments
(e) high· freque ncy applications
III, The ba.~ i(' mechanism for storing a datil bit in an E~CMOS cell is {II} cont rol ga!c
(c)
PROBLEMS SECTION 14- 1
floming gmc
(b)
flo.al illg drain
(d) (;1'11 curren!
Ans\.VCrs to odd-numbered prob lems arc al the end of the book.
Basic Operational CharacteriJticJ and Parameten I. A ccrtain logic g illc has a VOI ~,",nl = 2.2 V, and it is dri ving a galt" wi lh a Ihcse ga tcs compatiblc fo r HI GH -statc oper.ltion ? Wh y"
VIII'''"l
= "2.5 V. Are
2. A ccrtilin logicgatc has a VOIJ ...... I = 0.45 V. and it is driving a gale with il V1L\....l Art': Ihcse ga1I!S compatible for LOW-stalc 0pcTlltion:' Why '!
:=
0.75 V,
3, A 1TL galc has thc fo llowing uctu.al Vl) llilgc level \':lIue5: VIIII"""1 = 2.25 V, VII~""'I :: 0.65 V. Assuming il is bcillg drivcn by a g.ale with VOII!loin. = 2.4 V and VOI..l."". = 0.4 V, whal arc the H IGl l- lmd LOW-level noise: millgills? 4. Whm j~ thc maximum a mpliiUdI! of lIo ise spikes thm can be toleratcd on the inputs in both the I-II GH slale und Ilk LOW slale for Ihc galc in Proble m 3?
PROBLEMS
•
819
5. Voltagc spccifiefllions for threc types of logic gatcs are g ivcn in Table 14-1 Select the gate that you wou ld uSC' in a high-noise i ndu~trial environment. TABLE 14- }
2V
0.8\0
0.2 V
2.5V
O.6V
0.2 V
3.2V
0.8 \i
GaleA
2.4V
0.4 V
Gaten
3.5 V
Galee
4.2V
6. A ccrtain gale dmws fl de su ppl y CUITCnt fTOm a + 5 V ~ou rce 0[ 2 mA in the LOW stalc and 3_5 rnA in the HIGH stille. What i~ thc pO\l-'c r dissipHiion in the LOW ~tatc? Whill is thc powc r dissi plliion in thc HLGH Slide? J\~suming a 50% dUlY cycle, whm is the average power di s.~i p~l l ion'!
1. Each gate in the circuil uf Figure 14---50 has i1 (PIJI and i11P1IL of 4 ns. If a positivc-going pulsc is applicJ to the input as indicated. how long wi ll it uokc thc outpu t pu l ~ to appear? fiGURE 14 - 50 mGlt
IIlGH -L_ / Output
LOW
8. For aecn'lin gatc, I I'IJl = 3 Ill; :\l1d '/'IIL = 2 ns. What is thc a\'crngc
pr~!gwion
dclay timc'!
li ~ l s pammeten; for three types of gmc~. Basing your dec ision on thc specd·power product, which OIlC wou ld you select for besl performance?
9. Ti1ble 14--4
TABLE 14- 4
Gatc i1
1.2 ns
15mW
GatcB
I "' 5 ns
4""
8mW
Gatce
10 IlS
10 ns
0.5mW
10. Which ga te in Table 14-4 wou ld you select if you wantc
h ighe~t
II. A standard TIL gate has a fall-out of 10. Are any of the ga tes in Figure 14-5 1 ovcrloaded? If so, which ones? FIGURE 14 - 51
G,
G.
A,
G,
X,
G,
82 0
•
INTEGRATED CIRCU IT TECHNOLOGIES
12. Wh ich CMOS gatc Iletwork ill Figure 14-52 Cllll opcrn te at thc highest fn:qucllcy"!
A"
A"
X"
.4,
x"
X"
X,
X, X,
(,'
A,
X,
A,
X,
rei
(b)
fiGURE 14- 52
SECTION 14-2
CMOS Circuits 13. Delcnnine Ihe state ton or ofT) of cach MOSFET in Figure 14- 51
+,V
FIGURE 14 - 53
+,v
+,v
J HrC H J ~
J J r rcrJ "l LowJi-
,,'
(",
+5V
J rowJ "l
,<,
I, d )
14. TIle CMOS gllie nctworl: in figure 14-54 b incolllplctc. IndiC
Ompul
• unuS{'() inpUls 15. Devise u ci rcuit. using appropriate CMOS logi(; gHles and/or inverters, with which sign.1l s from four d iffcrent sources Colli be connttted 10 a common line ill different rimes wi thou t interfering wi th (;11I:h olh\..,..
SECTION 14- 3
TTl. Circuits 16. Detel111ine which BJTs in Figure 14-55 .Ire orf
FIGURE 14- 55
+,v
+5 V
(,)
o--lVV'v--
+,v
0.3 V
(b)
o--\M-l
+,v
ov
«,
+,v
+,v
(d)
PROBLEMS
•
821
17. Dcten nine the ou tput state of eac h TrL gate in Figure 14--56. FIGUR E 14-56
+5V
HIGH HIGH LOW
===D--
IUGH
IIiGH
LO\\
HIGH
Q
J
==:::IT)1-
I-IIGH HIGH HIGH
Ie)
Ib)
'"
(d)
18. TIle TIL gate IlCtwork in FIgure 14--57 is incompll!tt!. Ind icate Ihe changes Ihllt shoold be made. FIGUR E 14-51 . -Q-
/
Output
• • unused
SECTION 14- 4
inputs
Practical Considerationl in the Ule of ITt 19. Dctennine the output level of each TTL gate in Figure 14--58.
FIGURE 14- 58
OV~
""'" ------L/fb)
I
I
LOW~ Ie )
20. For each pall of Figure 14- 59, te ll whether each drivi ng gale is sourc ing or si nking currell! . Specify the malli mum eUrl"Cnt ou t of or into the outp ut of tht:: driving gate Of gales in each e'tsc. All gates are standard 1TL.
FIGURE 14_ 59
HIGH _ -=j~:;O-'--<1-;:~ G, HIGI ! - --<_/ G,
(,)
(b)
1.0\\ HIGH
(e,
21. Usc opclJ-eoJlector ilJ\'cncrs 10 implement Ihe fo llowing logic expre~sions:
(a) X =
:4nc
(b) X = ABCD
(e) X = ABCnEr
8ZZ
•
INTEGRATED CIRCU IT TECHNOLOGIES
22. Write the logic expression for each o f the cireuils in Figure 14-60. fiGURE 14- flO
+V
+1'
+V
A ~R'
",
"
II
H
Q
C
II
x
c - - ----l
/J E
Q
X
!=11>-
r
G
G
/J --~I
,.j
H
Q
Col
(bl
23. Determi ne the minim um vl1luc for the pull-up resiSlOr ill each c ircu it in Figure 14-60 if l Ot.n'l'w.) = 40 mA and VULun• ., = 0.25 V for eaeh gale. Assumc lllUl 10 standa rd 'n 'L un it loads arc being d riven from oUlput X and the supply volt age is 5 V. 24. A l:e rtain re lay req uires 60 lilA. Devise a way 10 lou",.. ) = 40 m A 10 drive Ihe re lay.
SECTION 14-5
U~
opcn-colieclOTNAND gates w it h
Comparison of CMOS and nL Performance 25. Sclt:t.:I lhe Ie fami ly wilh Ihe besl speed-power product in Table 14- 1.
26. Determ ine
from Table 14- 1 the logic fam il y that is most ap propriate f(ff each of thc following
rcqu in:menll>: (a)
s hm1 e~1
(b)
fa~ tcsi
propagation delay lime
flip- nop loggle Tale
(c) lowest powerdi;.sipalion
(d) best rom promiSc: ixtwec n speed and power for a logic gale 27. Determine tht: tolal prop
FIGURE 14-61 .1
II -''----+-
r
-L-.J
------l--L~
D ----=L~ (a)
74 FX X gale.~
(b) 74 HCXX gale,;
c x
(e) 74A HCXX ~ales
"
x,
x,
ANSWERS
•
813
28. One of the flip-t1ops in Figure 14-62 may have an errntic outJlllt. Wh ich one is it if any und why"?
SECTION 14 - 6
Emitte r-Coupled Logic (ECL) Orcuib 29. Wh 31 is the basic difference bet\\'<:.'en ECL d rcuiu)' and T IL ci rcuit ry"? 30. Select Ee L. HCMOS. u r the appropriatc TTL serie~ for each of the following requirements: (a)
hi~hesl
spet:tJ
(b) lowest power (c) best compromise bet"',:cn high speed and luw power (spee.J-puwcr prod uct)
SECTION REVIEWS SECTION 14-1
Basic Operational Characteristia and Parameten I. V1H : HIGH le"el input \ullage: V1L : LOW lcvel input \'o ltage : Voo: HI G H leyel ou tput vo ltage; VOL: LOW level oo tput voltage
2. A hi~he r val ue of noise margin i ~ bellcr. 3. Gatc B can opcrnte at a higher frequency. 4. E;I(ccSl;ivc looJ ing reduces the noise marg in of II gale,
SECTION 14-2
CMOS Orcuib 1. MOSFETs are ulSCd in CMOS logic. 2. A compl ementary otlfpu r circuil consists of an I,-dlannel and a p -channcl MOS FET. 3. Because electrostatic dischaQ;c can damage CMOS de\'iccs
SECTION 14-3
TTL Circuia I . False. Ihe 111m BJT is off.
2. The 0 11 state of a BJT is a closed swi tch; thc ojJsw.te is an open switch. 3. Totem-pole and opcll-col lcctor are types of'ITL ou tput s.
82 4
•
INTEGRAT ED C IRC UIT TEC HNOLOG IES
4_ Trislate logic pro ... ide.~:J high- impcxhull:e slate. in which II)!! OUiput is dh.conna:tcd from the rest of the circuil.
SECTION 14-4
Practical Considerations in the Use ofTTt L Sin}.; current occurs in l·, LOW outpU t state. Ics.~
2. Source currem is the HIGH ~(ilte .
than sin k cum:nt bcnl11SC 1'1 TIL IOild looks like il re\"erse-biui\Cd d iode in
3. The totem-pole transistors can not hand le the current when one outputlties to go HIG H and the other is LOW. 4. Wired-AN D must uo;e open-collct:tor.
S. Lamp dri\·cr must be open-colleclor. 6. False. •m uJl(;onllrtted TTL input gene ra lly acts as a HI GH.
SECTION 14- 5
Comparison of CMOS and TTl Performance L BiCMOS use~ bipolar tran~ i stors fo r i.lput and output circ uitry and CMOS in betwee n. 2.. CMOS
SECTION 14-6
h a.~
lower power dissiJXltion than bipol:lr.
Emitter-Coupled logic (Ea) Circum 1. EeL
i~
([lster than TTL.
2. ECl hilS more power al1 d less noise margin Ih:ln ·' TL.
SECTION 14- 7
PMOS, NMOS, and E2 CMOS 1. NMOS :1I1d PMOS:lfC high
('en ~i t y.
2_ The f100 tinggalc i~ Ii)!! mechanism for sloring charge in an E~MOS cell.
RELATED PROBLEMS FOR EXAMPLES 14-1 CMOS
14-2 IO.75JLW
14-3 111"""""1"" 5(20,.,1\) = 100,.,A / 1 ,,.......,
= 5( - 0.4 rnA) = - 2.0 rn/\
14-4 Fan-oul = 20 14-5 X = (AB)(CD)(EF)(Gf/) =
14-6 See Figu re 14--63.
(A + 8)(C + V )(£ + F)(C + H)
14-7 Rt . = 97 n
FIGURE 14-63
Two 14LSlJ<)s
H-
-LC-/
C-
r;:-"
/) -
-<-../
E-
'--:---'
F-
-L:./
G - "''''' 1/ 1- ,--" J ~'-/
SElF-TEST I. (b)
2. (cl
3. (c)
4. (cJ
6. (a)
7. (c)
8.
9.
(tJ)
(u)
S. (e}
w. (c)
A: Conversions DECIMAL 8CO(8421) OCTAL BINARY DECIMAL 8(0(8421) OCTAl BINARy l OECIMAL 8(0(8421) OCTAL BINARY
o
"'"
o
3
00 ' 0 00 11
,
4
0'00
4
5
010 '
5
OlIO
•
o
34
00110 100
42
tOCX1 lO
fill
011 011)00
104
](XXIIOO
35
001 10101
4]
1000 1.
105
1000 10 1
10
36
00 110 11 0
44
100100
'"
0 110 100 1
70
OI II OOOU
106
1000110
II
37
00 110111
45
10010 1
71
011 10001
107
ItXXl lll
""
38
00111 000
.J6
100110
72
0 11 10010
110
100ltXXl
WI
39
001 11 001
47
10011 1
73
01 1100 11
II I
100100 1
IIU
4U
U' OOUOOU
50
IUlOOO
74
OI IIUloo
112
IOOJU IO
'"
41
0 1000001
51
101001
113
10010 11 IOU II{MI
000 '
2
• ,
2
7
01 11
8
'000
'0
'00'
7
75
0 111 01 01
42
01000010
52
10 10 10
76
0 1110 110
114
II
' 000 HIO I
43
UIOlX.lJI I
53
10 10 11
77
OIIIU I II
115
)0011 01
44
01000100
54
10 11 00
78
0 1111000
116
100111 0
'0
000' 0000
12
10 10
II
00010001
12
000 100 10
" 14
1100
13
000 1001r
15
110 1
14
00010 100
15
000 10101
16
.
0 100010 1
j5
10 11 01
79
0 11 1100 1
11 7
100111 1
0 100011 0
56
10 11 10
OJ
' 0000000
120
10 10000
47
01000111
57
10 11 11
81
10 1000 1
"
trIO
48
01011l00ll
60
110000
82
'000000' I()(XX)OIO
12 1 122
10lUOlO
17
11]1
61
IUXX)!
8l
100000 11
123
10100 11
000 10 110
10
'IlOIlO
"
0100 1001
50
01010010
62
110010
84
10000100
124
10 10100
17
00010 111
21
63
11001 1
12'5
10 l OlUI
100' 0
52
OIQ IOO](l
64
110 100
"
IUlUJIU I
00011000
"
OIO IOOO J
18
86
I OCXIO 1If)
126
10101 10
19
000 11001
23
1001 1
53
010 10011
65
110101
87
101".f.(l) 1I
127
1010111
20
00' 00000
24
10100
54
010 10 100
(l6
I lO I lO
130
10 11000
00100001
10 10 1
55
0101010 1
67
1101 11
"
10001000
21
89
10001001
131
10 11001
22
OO J(lOO IO
01010 110
70
11 1000
QI\
IOOll'X)OO
132
101 10 10 10110 11
1011
'000'
45
l3
00 1000 11
" " 27
101 11
UtO Wl l 1
11
11 1001
133
OO H)() IOO
JO
11000
58
010 11000
72
111010
"
l00 IUlAJI
24
", "
92
10010010
134
10 11100
25
00 ]00101
31
11001
59
010 1100 1
73
111011
93
IOIlI (Xll l
135
10 ) 1101
2(,
00100110
32
[ lOtO
74
I I I 100
136
10 11110
33
110 11
61
01100001
75
111101
1(01010 )
137
10 111 J I
62
0 11 00010
76
J 11110
100101 10
14U
I 1UlWI
63
OIlOOOli
71
11 111 ]
100101 11
14 1
] I ()(X() I
0 11 00 100
100
J00!XXXl
'" " ., "
10010100
00]00111
'"
OJ JOUOOO
21
1001 1000
142
1100010
HJO l llt ll
I·n
11OUOI I
101 10
28
0010 1000
34
11100
29
0010100 1
35
1110 1
30
00110000
36
11110
"
UUllOuO I
37
11111
32
001]0010
4U
'oooou
"
001 100 , ]
41
'0000'
. '"
Ul loo lOl
10 1
ICXJOOOI
66
0 1100 11 0
102
1000010
OJ
0 11 00 11 1
103
1000011
96
W
825
826
•
APPENDIX A
,,
• ,, ,,,
Powers 0[1'11"0
0
• , "" ,,, '" ,• ,"" "" """ """ "" nfl '" , rm """ n ~
.~~
~12
I IJ24
8 ' I>~ 16 lSi 7611 6!1 SM. 131 012 }~
!62 HI
~ ~ ~ ~&&
l l>$!1
2
152 19-1 .l().I
2~
~ .Ill~ t.I)I!
16
33
m
2 16
~:..I ~.\2
61 108 1!64 134 217 12R
268 U S ~ ~ S36 1!1() 9 1 ~ I on 141 8201 2 141 4lll MI! 4 m %7 2'A'I 8 SIIY 9J..1 -W! 17 179 11("" 18-1 )4 l.W 1)11
."611
611 119 ~ 7b ~ 137 4}X 9H 412
,
11~ 1!17_ ~ ~') 755 BI3 888
1 099 S I ) fil7776 19') on :!''is 552 4 .19f!046S I I , ~ /I 796 093 {(!! :!OS 1759! II!6 IJ.I.I .JJ6 ~ I ~ 312 O&! !\l! 1U 3f>ll 1~ 171 6(.l 140 737 4I!8 JSS 32K :lil t 414 976 710 6S6 562 9-l'J '15.1 4! 1 Jl2 I !S £'}} _ 1\.12 6:!-1 so bKS 2-111 2 2."
,
"" " "'" "" " "" ••" """ .,"" ..," 26 ~
~
H
~
~
IIO!I 6 16
'"" "" "" " "'"
36 1193 488 In 41 9 100 212 73 1l!6 9 76 29-1 838 206 46.1 147 ~7J 9jl SlI9 ern; ·111 v:l~ 2\lS 141 'lQ'\ 17Y 3.~J U' !!56 195 KID :B8 705 6S 1 7 1 ~ 100 ~I 6:!(l 717 4 11 303 4~ no U 1 ·Il.! 8::>:! 606 !!.IS 4 m 366 4l(.! M 1,15 21J tFJ6
.'"
m
4 SOJ m 1m lW 49() 9 1107 1'19 !S-I no 992
18 o , ~ 3911 50') 481 ')I!.I 36 028 797 0111 \163 %II
,
72 057 SO» 037 9~7 936 141 Il~ ' !;II U7~ ~ss !111 !1!Il 230 376 15 1 11 1 74-1
S76 -t«I
152 2 .W1S ~ 611 9 223
7~!
303 421 4H8
'i.!1 ~ 606 lH6 iU3 009 213 /:oB f>116 018 427 31n I n UJ(, 1'-.... T7S
184-1(1 7.f.1 07) 7W
m
'"
~~ ,
916 "'52
\10.1
~
~ ~
W
" "'"
~
M M
""
B: Traffic Light Interface
+ 12 V
,=
R,
I~ic
1.0 kfl
digital
5 light
~
4N35
,
2
R,
-
22 1.:fi
Q,
R, 15kfl
TIP3055
The development baird with programmed
CPLD and an imerface brnll'd rooning model UlIfflC
-
lights in the lab. Courtesy of Dave Buchta.
FIGURE 8 - 1
Inteoface circuit used with model traffic tighb. One cin:uit drivel one light-
Project board +5 V source 4N3S
Project board ()llIput pi n
- -'VVv-{Oh 1.0 kJ1
CRYOOM D2W03F
Optocooplcr
'-----<=;I_'}--J2 v OC
[lC;;;~;W------'r---cd ~ }
3A 240 VAC
Solid-slate relay
110VAC
I Student holding a (\e\'CIopment board wilh the programmed CPlD funn illS real t",me li gh ts in the tub. The interface circu its arc in lhe- [octal box mounted ()11 the light support. Courtc,s y of Doug Jok.o;ch .
FIGURE B-2
Interface circuit used with act.ua! traffic lights_ One cin:uit d rivel one light.
827
Answers to Odd-Numbered Problems II . (a) 1010
Chapter 1
(d) 11 0000
1. Di!;ilal can be Inmsmiuc(\ and stored mOTe effidently lind re1iabl}'.
3. (II) 1101000 1 S. (II) 550 os
(b)
(gJ
(b) 600 os
(c) 2.7}lS
(d) JOV
~b)
15. UU lIddcr
(e) mu ltiplexer
(h) 1001001
(d)
(d) oompar.lIor
(c) 1000
Ie) IlIU
Ir,llooo (0 10110110
(b) 00 1
0010 1000
(e)
td) 11\11011
23. (al 0000 11 00
(hI 101 11100
25. fa) - 102
in either ;o.:hcrnatic (gnlphk) funn or i n (ex! fonn usill!;
(d) Download:
TIle pro<:css in whicll the design is
1n1l1srerrcd from software 10 hardware. 27. A collecliOl"l of cin;uits interconnected to perform a specified function
(b) I 100010[0 I lOOOOO l l()(J()(X)OO()O(
(hi 00011101
(e) 11 101011
(d) 100111110
(b J II ()()(X)(X)
31. la) 11 000 101
33. 10011 1001010 35.
(a)
oo lll lOO
(b) 0101 HXH (d) 0101 11001000 (e)
01 OOXX)] OOOOOOOO
(0 11111 0110001011 1
kt:y~d .
(g) 100010 1010011101 .J7. la) 35 (b) 146
Chapter 2
Ie) 243 (b) 100
(e) 100,000
39. (a) 6016
(b) 9000; 300; 50; 6
3. (a) 400; 70; I
41. (a) 10
Ie) 100.000: 20.000: 5000: 0: 0: 0 S. (a}3
12
7. (a) 51.75
(f) 367
(d) 8
(b}4
Ie} 7
(g) 11
(h) 15
(e) 9
(f) 235
(i) 408S
.n, (a) 00101 I
(e) 92.65625
(0 11 3.062'5
(e) IOllocmo
(h) 127.96875
bils
(I) 7 bits
(e) 7
(e) IBA'6
(b) IOJ r II
Ie) tX)10l10t"0 1
(lI) 120.625
(h) 8 bits
(h) 1792
(g) J 15
(g) 90.625 (d) 7 bils
1474
(d) 52
(d) 011 0 10001
(e) 6 bils
(g)
(d) 141
(e) 46
(c) 65.875
(b) 6 bils
Ie) 26
(b) IOB I6 (b) 23
(bl 42.25
(g) 8 bi l~
(e) - 64
(el rOt()(x)()IOIOO
25. 7 V
29. Enter ilnew value Of1lhe
I d) I ()(()()() 11 (b) + 11f1
29. (a) 00 11 0000
design i., simulated based 0 11 defined input waveforms.
(e) Compillllion: A program process that (1)OIro is the design now process and translates 11 design source code to object code fur tcstin g and downloading.
to 11\10
27. (a) 01000110 1 11 J 10000 10JOII0lUX.0000
an HDL. (hI Simulalion: The SlCp in a design flow where Inc entered
Ie) 0101
000 1010
(b) 11010101
(e) 01 10010 1
23. (H) Design cOlry: The step in 11 programmable logic design now where 11 description of Ihe circuil is entered
9. (a) 5 bils
(d lCXXl11
(e) 10101001
(e) 01 100100
21. ABEL. CUPL
11100
(b) 1000
21. (a) 0001 1101
19. DIP pins 1;0 throug h hules in a circuit board. SMT pin~ ll)nncct 10 s urf;t(;c pads.
1. (a) 1
(bl 100
19. (al 010
multiplier
17. 0101000C1
828
(e) 101000
(g) I (xxXX)]
(d) 11011 0
13. AND gate
(I)
(d) 100010
(I) 111 0 11
17. (a) 1001
11. 8 ps; I J1S
11000
«)
(d) 1101
9. 50%
(I) 1011101
{bl 10101
15. (a) 100
7. 250 Hz
(e)
(e) 111101 (h) 10 111 010
11 11101
13. (a) 111 1
(XXIlOlOl0
(b) 10001
(f) 100 110101 0 11
(g) 0010] 1010111 00 1 (It) 100101 I IOCXXXX)() (i) 0010Cl00CXX)] 000 JO II
(e) 67
ANSWERS TO ODD- N UMBERED PROBLEMS
45. (a) 00010000
(r.)
5. See Figure P- 3.
000100 "
(e) (0) 11000
(d) 00 10000 1
(e) 00100101
(f) 00 1101 10
(g) 01lX)0 100
(h) 010101 11
(i) OJ 101001
(j) 10011 000
(k) 000 100 100101
II) 000101010 110
47. (a) OOO IOlXXXl l00
(b) 000 100101000
t\ ~ I , I I • I ,
I
«) 000 1001 10010
l d) 000 10 I0 1(XX)() (0 00 I 0000 I 0000
(,I 00110 101100 1
(h) 0 10101000 111
(d 346
(d) 42 1
(e) 754
(£) 800
(g) 978
(h) 1683
(i) 9018
(j) 6667
,
I
I I
I
I
:i L
(b) 000 10010
000 101 11
Cd) 000 101 10
(e) 010 10010
(n
(g) 000 11001010 1
(h) OUO I(XlIOOl 10 1lX)I
FIGURE P - 4
000 10000 100 1
53. The Gra)' (:ore makes o nly one bit chan~e m a lime when going from one number in the sequence to the nex t. (11) 000 11
(b) J
(e) =
A ~~""--'L
Cd) /I
(e) >
(I)
H
B
59. 41:165 6C6C 6F 2E 2u4K 6F 77 20 6 1 72 65 20 79 6F75 3F
c
,II
I
I
,
x~
(b) OO(XXHOOI
I
I,
II
I
,
" bJd= " atf ,
(e) 111 111 110
::
::
::
::
L
FIGURE P - S
65. 00 1010001 110 1000 10
I
o--.J
61. (b) is incorrcd. 63. (a) 110 100 100
9. See Figure P- 5.
(e) lUUOl101 1 110
55. (11) 11 00
57. (a) CAN
(a)
I
I '
7. See Figure P-4.
(b) 237
51 . (a) 000 101 00
67.
, I
FIGURE P - l
(i) 000 HXXXXll 01 0001
«,
, I
nI :: I ::
(e) OOCH 100001 10
49. (a) 80
I
-L-L---."
(b) I !XXX)() 10 I
II. Sec Figure P-6.
Chapter 3
, JU\J1IUlJ1I\J1J
I. Sec Figure P- l.
B~ 111111 111111 1111
1111 11 1111 11
11 11 1 1
111 1 11 111 111
1111 11
1111 1111
III ,
V.. HIGH LOW
FIGURE P - 6 HIGH V_
LOW
13. SccFigure P-7. FIGURE P- I
3. Sec Figure P- 2.
FIGURE P - Z
t\
rTi'
rill
-.J "
LJ "
"
"
II
"
L
H~
x-tL1L
"
,, , ,,, ,
x ----~~r ' -----FIGURE P - 1
•
829
830
•
ANSWERS TO ODD_NUMBERED PROBLEMS
15. See Figure P-8.
39. Add lln inverter 10 the enable input line of the AND gate. 41. Sec Figure P- 12.
Igmtion ~wil" h
Timer
1" lw:<>d ligh'
comrot
FIGURE P - '
Tim...,. pr
17. Sec Figure P- 9. A
FIGURE P- 12
--.J
, 'I B-Lj , , C
I" '
o
:
]
43.
L!
x -,L__________--",--
inputs arc now :lcti\"e-LOW. Ch:lnge the OR gat es to NAND ga tes (negati\'e-OR) and add two inverters.
"[lie
45. G
47. Gate output open FIGURE P - 9
Chapter 4 19. XOR = AB + AB;OR = A + 8
1. X = A + B
21. See Figure P- IO.
+C+0
3. X= A+ B +C S.
~a)
AB = I when A = I , H = I
= I, B = O,C = I
(b) ABC = , whcn A
. ++++H1,,, ,'""
'"
x
,, , '" ",
'"
(e)
A+ B = Owl1t:nA=O, B = O
(d)
A+
B +
C=
0 when A = I. B -; 0, C = I
(e) A+ B + C = OwhenA = l . B = I. C = O (f) A+ 8 = O when A= I,B = O (g)
AB C= I whcnA = I, B = O,C = O
Cb) Comrnutath'c
7. (a) Comm utiltive FIGURE P - tO
(e) Distributi ve
9. (a) AH 23. Xl =
AB. X~ "
A B, X 1 = All
25. CMOS
n.
t l'lJ I
= 4.3 ns; IpHL = 10.5 ns
29. 20mW 31. TIle g
33. (a) defectivc output (stuck lOW or open) (b) Pin 4 inpu t or pin 6 output intcmlllly open.
35. "The SCllt belt input to the AN D gMe is open. 37. Sec Figure P- I I.
~e,
(b) A
A HC
(e)A + HC (g) II. (a) (b) (e)
+ B
(d)II+8 -+ C (f) II
(A + 8)(C + D)
(h)
+B+
C
+
AB + CD
(A + 8 + C)(E + F + G)(fi + I + J) (K + I + M) ABC + HeABc15EFG H (b) X = AH + C
13. (a) X = A BCD (e) X = AB
(d) X = (A +B)C
15. Sec Figure P- IJ. 17. (a) A
(b) AB
(d) A
(e) AC
19. (a) BD
+ BC
+ BE + OF
(e) 8 FIGURE P-ll
(e) C
(e) ABC
(b)
ABC + ABO
(d) AB
+ CD
0
ANSWERS TO ODD- NUMBERED PROBLEMS
: ~x
- x
, -'====L~
(dl X _ A f IIIC t 0(11
f
ell
FIGURE p-tl
21.
Ib) AC +
(a) AB + AC + BC
Be
(c) AB+AC
23.
29. (b) See Table 1'- 2.
TABLE P-Z
(bJ Domain: A. B, C Sltl ndard SOP: ABC + Aiic + A BC
«)
Domain: A, H, C Standard SOP: ABC + ABC + ABC
25.
«,
27.
,a)
(b) 111 + 10 1 +001
+
U
0
0
I
(A + IJ + C)(A + H + C )(A (A+n+C)(A + B + C )
B
+ C)
B
+
0
0
0
0
0 0
+ 8 + C)(A + B + C )(A + (A + lJ + C)(A + B + C)
29.
0
0
111 + 11 0+ 101 (A + IJ + C )(A + B + C)(A (A + Ii + C)
(b) (A
«)
0
0
C)
0
+ Ii + C)
0
,a, See T
31. laJ See Table P- 3. TABLE P_]
TABLE P-1
0
0
0
0
0
0
0
0 0
0
0
0
0
0 0
0
0
0
0
0
0
0
0 I
0
0
0 0
0
0
0
0 0
•
831
832
•
ANSWERS TO 000 · NUMBERED PROBLEMS
33. (b) Sec Table P-6.
31. (hl See Thbk: P-4. TABLE P - 4
TABLE P- 6
w
X
Y
Z
0
0
0
0
0
0
0
0
0
0
0
Q
0
0
0
0
0
0 0
I
0
0
0 0
0
0
0 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0 0
0
I
0 0
0
0
0
0 0 0 0
0 I
I
D
0 0
I
0
ABC
0
0 0
0
0 0
0
c
0
"00 ".
, C~ I'
00
lILO
til'
"
1111
'"
00
""
lUI
c
"00
0
''''
, \//(
00
"". ""
"
'or "Ie
00
ORC
' He
ANSWERS TO ODD- NUMBERED PROBLEMS
39. (.) No simplificmion
port (A. B. C. D. E. EO. H. I: in bit: X:
begin
+ BCD + ACD
X <= (A and Band C) or (0 aud E and F) or (0 and H a nd I):
+ CD
43. B + C
+ CD + BC + AD (A + Ii I- C + 15)(A + B
end architecture I..ogic;
45. A B CD 47.
(.,
55. LED. LEOs emit light. LeOs tlo not. I-
C + D)
(A+B +C+ D)
+ Z )(X + Y) (A + C + D)(A + H + C )(A ... 8 + D) (8 + C + O)(A + Ii + C + D)
(h, (IV + Z)(\V + X)(Y 49.
A HellE + ABCDE + AHCIJ£ ABDE + AHDE + liCDE + ABeD
51. X
=:
bit);
architecture Logic of AN D_OR is
+ BC
(d' AH
Ol1t
end enlil}' AND_O R;
41. (a) AB + AC (,) BCD + ACD
833
53. entity AND_OR i-;
(b) AC
(,) DF + £1-"
(b) A
•
+
57. Ont: less inverter and six fewer gUles_ 59. Add an inverter to the output of the OR gate in each of the segmt:nt logic circuits . 61. See Figure P-1 6. 63. In"eller out put open
65. b-scgment O R gate output ope n
FIGURE P- 16
, .'''.1;",.:111 b = (C -t fJ+ AXC-t 8+Aj
r I - /- '
, f
834
•
ANSWERS TO
OOD~NUM8EREO
PROBLEMS
S. (d)
5. (el
Chapter 5 I. See Figure P-17.
0
-, "c
• "
",,. ,",, ,
,
0
0
0
0
0
0 0
0
0
&
&
S. (I)
5. (el FIGURE P - 17
ABC 3.
(II)
X = ABH
(e) X
(b) X - AH
=A + fJ
(d) X = (A
8
+ 8)
+ 118
t_)
0
0
0
0
0 0
0
(0 X = (A + B) (B + C)
(.) X = ABC
5.
+
0
5. (b)
X
0
0
0
0
0 0
0
ABC
0 0
0
0
0
0
0
0
0
0
0
0
(a )
/)
FIGURE P - f8
0
+ B)
P- I K
x = IIR+iic
, ,, '~ {
\
.I.
0
0
7. X = AB + AO = (A t- 8 HA
•• St:e Figure
0
1
0
0 0
0
0 U
0
0
0
0
X
,
0
ANSWERS TO ODD- NUMBERED PROBLEMS
II. Scc Figure P- 19.
835
17. (a) X "" AC+AD + 8C+BD
A~ " C
(b) X = ACD + BCD
{cl X "" ABD+ ('D + £ \' - AIJ+C
FIGURE P - 19
(d)
X = A+ B + D
(e)
X = ABO + CD + E
{O X = A C + A D t- BC + HD +E C+£H
+ FC + PH
13. X = AB 15. (al No sim pl ifi~'at i oo
19. Set: Figure P-20.
(Il) No Simplification
21. Scc Figure P-2 1.
(cl X = A
23. See Figure P-22.
(d) X =
•
A+ B + C+
EF +
25. Sec Figure P-23 on page 836.
G
+ R: see Figure P- 24.
(e ) X = II.BC
27. X = II.
(0 X = 8CDE + ABErG + BCEFG
29. X = AB C: sec Figure P- 2S.
FIGURE P - ZO
, FIGURE P - Z1
,. FIGURE P - ZZ
'~" , ~'
I~ ~ \,
"
,. ~
(hI
x . ,W(;
, ,,---'
f
, --"f
,..
,"
tt;J X ~ "BI CfDE + Mi)
.. BCEI
n
!
,
836
•
ANSWERS TO ODD-NUMBERED PROBLEMS
'B»-,
FIGURE P-ll
'
; '"
'"
'"
,i , ,"r =:JI
'
"'" N
'"
,,r "to
1.1
"~
H~ X
c-GJ
LJ FIGURE P - Z4
FIGURE P-ZS
31. The output pulsc width is ~re
end elltity Cin:ui15_53f;
33. (e) entity Circuit 5_52c is
compo~nt
port (A. B. C: in bit ; X: oul bit): ellli entity Ci".: uit5_52c, architecture LogicFunction or Circuit5_S2e is begin X <= (I)ul A a nd Bl or B ortB alld 001 C) ur (1)01 A and 11111 C) IIr (B and mIt C) or nol C;
end arch itccture LogicFunclioll; (f) enlity
Cin:uiI5_52fi~
port (A, B. C: in bit : X : out bit); end elllil y Cin:uit5_52f: architecturc w gicFunclion of Cin:uit5_52f i~ hegin X <= (II. IIr B) alld (not B ur C);
cnd an:hitcclure LogicFuoction: 35. Number ~ates from top to bottom and left to rig ht G J, G2, G3, etc. Re label inputs IN I. IN:!. IN3. etc. and output OUT.
entity Circuit5_53f is port (lN I, IN2, IN3, IN4, IN5, IN6, IN7, INS: ill bit; OUT: out bit):
arch itecture LogicFuoction or Circuit5_53f is NAND_gale is
port (A. 13: ill bit; X: out bit);
end CtH:ll poncnt NAND_gale; sign.al G IOUT, G20UT, G30UT, G40UT, G50UT, G60UT: bit; begin GI ; NAN D_gme port tn.3p (A ; > IN I, B = > IN2, X = > GIOlJT); 02: NII.ND...,gate port lIIap (A = > IN3. B = > IN4. X = > G20UT); G3: NAN D_sate port tn.3p (A = > IN5. B = > IN6. X = > G30UT):
G4: NAND...,gate port map (A = > IN7. B = > INS, X = > CAOUT): GS : NAND...gme port
m~p
(A = > GIOlfl', B
~>
G20V'!: X = > G50Ul);
G6: NAND_SllIC pori map (A = > G30L:l : B = > G40lfT. X = > G60UT); G7: NAND...,galc port map ( A = > G50UT, B = > G60UT. X = > 0l1T): end architt.'Cturc lq!icFlInction;
ANSWERS TO OOO - NUMBEREO PROBLEMS
37.
-0<11;1
flow ilpprooch
•
837
• TABLE P-7
cnlily Fip_64 io; port (A. B. C. D. E; in hil; X: oul bill: cnd entity Fip_64:
INPUTS ABC
D
OUTPUT X
architecturc (}JtaFIow of FigS_64 is begin X < - ( A lind Ii lind C) or (0 and not E):
end arch it«tur\! [}.lIaFlow; - StruclUrlllappmllch elility FigS 64 is Pllrt (IN 1. IN2, IN3, IN4, INS: in hi t; OtT; out hit); end elltity FigS 64; :'In:hitet'lure StructLiTC ur rlg53>4 io; compunenl AND-£alc is pun ( A , Ii: in bil; X: jKlI bit): end compunent AND_grue: component OfLgale is PU" (A , Ii: in bit; X; ulIl bil):
end ctlf11ptHlCnl OR...,galc; componen t Inverter is
port (A: ill bit: X : out bil); end componellt
Inum~r:
sigllal G lOur, G20lIT. G30LT, INVOlIT: bit; begin
end l'omponcllt OR...,gate;
G I: AND....satc purt map (A "'> IN I. B = > IN2. X = > G IOtfT);
eompcNlcntl nvcncr io;
G2: AND_gate port map (A = > GIOIJ r , B = > IN3, X :: > C20UT );
end
INV: Inverter port mall (A "" > INS, X = > IN VOUI):
G3: AND Solie pun map (A = > IN4, B = > INVQliT , X = > G30UT);
G4: OR...gme PlJrt map fA = > G20lJT. Ii = > G30LiT. X = >OUT);
cnd architcctur\! Stru cture; 39, See Table P- 7.
41. 11lc AND gll tCS art' numbered top to bouom G I, G2, G3, ('.4 . TIlC OR gate is GS and Inc in\'crters are, lop 10 bottom. G6 and G7. Change AI ' A:, B I, B~ 10 IN I. IN2. I.N3. IN4 respectively. Ch:lI1ge X 10 OlIT. e ntity Circoit5_62 is
port CIN 1. IN2. IN3. IN4: in bit; Olll: out bil):
end ent ity CirellitS_6:!; Itrchltccture Lo<.:ic uf Cin:uitS_62 is oom pont:nt AND...£
!'Mlrl (A: in bil: X: Ullt bitl; ~mlPtJncn t
hwcncr,
.o;lgna l G I OU1~ G20UT, G30UT, G4QIIT, C.50lJJ'. G60lJl: G70l1T: hit ; begin Gl ; AND_gUle port map IA = > IN!. Ii = > rN2. X - > GIOlJT); G2: AND...,giIlC !'Mlrt map (A = > IN2. B = > G60UT. X --> G20Ul"): G3: AND...,gillc pcln map tA = > G60lJJ'. 8 = > G70lIT. X = >G30un:
04: AND...,gllle pori map (A = >G70LiT. B = > IN I. X = >G40U1); GS; OR....galc PClrt map IA - > Gl OUT, B = > G20l'T. C - > GJOlIT. D = > G40lJT, X = > OUl): (;6;
",,"ener port map (A = > IN3. X = > G60UT):
G7: In\'Cl1er port map (A = > IN4. X = > G70U1): cnd archil«:tll.-e Logrc:
43. X = Aile + DI . Sinc e X is the same as thc G) output. either GI or Gl has fai led. with its output sluck LOW.
end l'OmIJoollf'nl AND_galc;
45. Sec Figure P- 26 OIl page 838.
component OR... gale is
47, (a) Sec Figure P- 27.
purt (A. Ii. C, 0 ; in bit: X: uul bit);
(e) X = £
(b) X = £
838
•
ANSWERS TO ODD · NUMBERED PROBLEMS
Omm~l'.~e
I 14 II
I~
11
10
9
:pl
8
)4567
2
2)45
6
:P,"'
,
i
Hi""')"
'P
,
'-----_-----'I
x
_
7
FIGURE P-26
,
MSD
IJ
,"
I
,
~
.1
~
,
:
FIGURE P-27
-
IJ
I
49. Sec Figure P- 28. I ,, ~~
1;. 'C-"-_/ FIGURE P-31
I,
-
--
Chapter 6
FIGURE P - 2'
1. (3) A ID 8 = 0. 1: = J. {A @ B)Cin = O. AB = I. C.... = 1 (hJ A ID 8 = I. I: = O. (A Gl BlCin = 1. A8 = 0. C_ = I
51. See Figure P- 29.
(e) A m B = 1.1: = 1.(/\ m BlCin= O. AB = O. C.... = O
~::~ ~ -
3. (a) 1: = I.C".. = O: II
I,
(b) I = I.C"", = O; (el I: = O.C"", = I; ld) 1: = 5. 11100
J.e"", ""
1
7. 1:, '" 0110; l::! = 10 11 ; 1:J = 0 110; I:., = 000 1; I::s = 1000
9. 225 ns 11. A = B is HIG H when ~ = Hoand A, = 8 ,; see Figu re P- 32. 13. (a) A>H = I ; A = B = O; II < H = O (b) A <8 = I: A = 8 = 0;II>B = 0 (e) A = 8 = ] : AB = O
15. Sec Figure P- 33. FIGUR E P - 29
17. X = AY\;i,Aa + A;A;A'/\II + A ;A~, x. ~
53. X = lamp on. II = front door switch on. B = back (\{)()I' switch on. Sl-" e Fig\lre P- 3D.
A,
FIGURE P- 30
J---LJ---Ul ., ,, I. .' ,, ,,
Hn :, B
55. Sec Fig ure P--3 1. Invcrters (not shown) arc u.~ to convert each HIGH key closure 10 LOW. 57_ Pill Cof OR gmcopcn.
59. No f
A:
FIGURE P- 31
'
:
,
.r
,
,
:,
--t----i : ; f------ti L.......i...... j ,
,
I
I
,
I
: ~~ ~ ~ ! H ---L-J
AN~WER~
TO ODD-NUMBER ED
,MSII) ,MSlh
IM\I:!I
I' ~
11,111
.,
,,'
,1 \11,
~j>fp-, ,_<_~
ItS!))
'" 't~"~"~'=:;:~
IMSH)
il -~
!~,
. =i>?
.
,, ..
IMSIl )
I~
,,~"~-: -t>J r~ '" -t>Jr
,.,
•
PROBlEM~
ItSIl)
11.£1l,
,,)
. ,_~_.J
.LSI!>
ILSI! ,
,.,
'"
FIGURE P 33
19. Sec Figure P- 34.
25. (a) 1000CXXX()()Gr.iY ...... J l00000000bin
(b) 001 1001 100Gmy > 00 10001000 binary (e) 1 1110001 11 Gray - . IO IUOUO IOl binary (d) ((l(O)()(X(I I GIOlY ... 00IXXXXl001 binary
See Figu re P- 35.
', _~ ---''-.J " , " A, . ,1 I
.. -1 IUGII
, ,
I
'
'"
I
, , ,, U,
,
IIIGII
HIGH
I
, ,, U,
,L
UA FI GURE P-35
, , ,
27. Sec Figure P- 36.
~ ~~:-:l~~~ I , I I I I
"
: r--+--1r---j
FIGURE P-34 FIGURE P - 36
21 . Ay1:0,AIl = 101 1. inva lid HCD
23.
(u) 2 = 00 10 = 00IOl
(b) 8 - I(X)O = 10001 (c) 13 "" 000 100 1 1 = I
29. Sec FigtlfC P- 37 011 page 840. 31. Sec Figure 1'- 38. IOI ~
33.
(ll)
OK
(d) 26 = 00 100 1 10 = 1IO I0 z
(b) .segment 8 burned OU I: o ulptJt G open
(e) 33 = 00 11 00 11 = IOCOOl 2
(el Segment b outpu t stuc k. LOW
:
,,
839
840
•
ANSWERS TO OOO-NU MBERE O
PROBlEM~
r..
te) The OUlput of Ihe top adder is shoncd to ground: Same binary valucs above 15 will be short by Hi. The lirst BCD vaiue to indica te thi s will be (X)() I 1000. (dJ TIle £.1 ou tpu t of the bollom adder is ~hOr1cd to ground: Every other set of 16 va lues starti ng with 16 will be short 16. The fi rst !leD val ue 10 indiclue this will be 000 1 01 10.
, ,
"o[~~+,, ~i!:BBEEEEi§i ,, ffi=f:
"
I
I
t. Place a LOW 011 pin 7 (Ellable ). 2. Apply a HIGH 10 Do and a LOW to D , through D 1• 3. Go through t~ binary sequence 011 the select inputs alld ehec k Yand Y accordi ng to Ta ble P-K
U
D. D, [
37.
TABLE P - 8
D.
0,
u
u
o o o
o o
o o o
o o
FIGURE P- l7
o
u
o
o o
o
0
o EVEN 00" ,",
", :f--Tt : ~ :: : !-:-I : '--'--C ,,, ,' ,,
A)
u--u--u---u:
! f'"""TI : ~ :-u : ~ ; ;
A. !
"
,, ,! I ,' "
H--i
4. Repellithe binary seq uence of select inputs for each sct of Ollta inputs listed in Tuble P- 9. A HIG H Oil the Y ou tJlllt ~hould occu r only for the correspondin!! combi nlllions of select inpu t~ ~howl\. ~ with LOWs 011 ;111 the other inputs. For eaeh HIG H applied 10 a data input. SC
39. Apply a HIGH in tum to each Datu input , 1)0 through
1-1
t:::t:t:::;--:-!: I
41. Sec Figure P- 39.
'
r -- -- 116741.S04 - - -- MG
roO!) FIGURE P-38
L _ _ __ _ _ __ ."
, - -- - - - -\\
35. ( 3 ) l1lc A, input of the top adder is opcn: All binary va lucs correspond ing to a BCD number having a \~,tlue oro, I, 4, 5. 8. Of 9 will be ofT by 2. TIlis will first be seen for a
;><>---""
OCD \'ullie ofOQ(X) (XXX)'
(b) The carry ou t of Ihe lOp
"---- -----'" au.put logk
FIGURE P 39
A NSWERS TO OOO- NUMB ERED PRO BLEMS
•
8 41
TABLE P - 9
43.
L
H
L
L
L
L
L
L
0
0
L
L
H
L
L
L
L
L
0
0
L
L
L
H
L
L
L
L
0
0
L
L
L
L
H
L
L
L
0
0
L
L
L
L
L
H
L
L
0
0
L
L
L
L
L
L
H
L
0
L
L
L
L
L
L
L
H
0
r
=
ABCu, + ABC\. + ABCi• + ABCi•
C"", = ABC;.,
0
0 0
47. Sec Figure P-42.
49. See Figure P-43.
+ ABCIn + ABCln + AHe",
51 . LSBaddcrcarrYOli t opcn
Sec Figure P-40.
53. Pin 12 of upper 74 14Hopcll
45. See the block dingnllTI in FIgure P-4 1 on page 842_
fiGURE P - 4 0
0
" " 00
" ~ = No
"00
,
" , ,
•
,
0
,
" "
, ,
,
"
,
"
"I]IpliflClllioo
C_ "' HC... + AB+AC..
.-
c
/-.tux
- '" ", :}G~ 0 ,,
.r
'--
C
,-
fl -
,
74LS JSJ
}Gl 0
, ,•
]
,,• ,
Mill< EN
1
=:
-
74LSI51
I- C...
842
•
ANSWERS TO ODD-NUMBERED PROBLEMS
FIGURE P- 41
"CD
" 7·5C8
.-
r;;;;;-
"""
f-
»CD
....,-, "
,
FIGURE P-42
(10)
,I, 1_
(12) (13)
1_
(IS)
, --=::;:;:;-- '
D',., '" '" D' D'
=
1'»
/I"
", ...i!.!l. II.
(14)
H~
(I)
.'. " ,"
74liCSS
", ,. , ,.,'" , '"
:"} '
( 15)
7411O!.S
3
", A:
.. , ..
;}-
<>.
em eB)
''"" '"
..
'" "
FIGURE P-41
A",I!
,.,
o. ,
od
,~} '
III)
( 14)
'" "
."
II
<>J 3
-I
;I(»)
"'''' "'"
nil
IlCIj,-e-l..oW
( 12)
~~,
(Il)
0"
,
,~~
,
~
,3
'" '" ,, '" • '" , OJ
)
( IU)
OJ
(3)~
)0,
m
'"
(9)
~ l.->-
(8)
141,5 147
.t=
8)
Chapter 7 3. Sec Figure P-45.
J. See Figure P-44.
,~ I
I
I
,
; f-J i
r:--. r:--. rf-l i f-l i /-J
,
I
ii ---;--, I
rh I
'
I
I
Ii
: I
I
Q~ FIGURE P-44
' u'------------u,, Q
I
JlJf'~ I
I
--.H'--________---'IL
FIGURE P- 45
ANSWERS TO ODD-NUMBERED PROBLEMS
•
843
15. See Figure P- 5 1.
5. See Mllure P-46.
d .t.:
, , , ~ r--7' ,---.J ,: L-J ,,: L , I I
Q
FIGURE P-S1
FIGURE P - 46
17. Sec Figure P-52.
7. See Figure P-47.
" Q
FIGURE P-47
9. Sec Figure P-48.
Q
,, ,,
'I
, .J
FIGURE P - 4'
,, ,,
~f-== r----u-
FIGURE P-SZ
19. Dircel curren! and de supply ,·{)lillge 21. 14.9 MHz 23. ISO mA. 750mW 25. di vide- by-2: sec Figure P- 53.
II. See Figure P-4IJ.
FIGURE P - 53
"
27. 4.62 ps
Q
29. C 1 = I IIF, RI = 227 kn (usc 220 kn). Sec Figure P- 54.
FIGURE P - 49
13. See FigUic P- SO. 2:!0 Ul
II , DlSOl
,,,
THRESII
'" GND
C'I ~
FIGURE P-SO
FIGURE P - 54
QOlPF
844
•
ANSWERS TO ODD - NUMBERED PROBLEMS
c .•
Q'::=±::=:l:=:=j----j:=:=i::=:![
upper NANI)
"",,..
Lo,,"er NAND
"",..XI_;' _1-_j--i-----jiL-....Li
,,'
'" Q,
---.;-----i----+-----i----+-----ic ~--' 1'Ill kvel (Hle l n
Uppc
0.0"".
l ""wNI\,'1D
~"', =l-~ (~)
FIGURE P- 55
31. R( = IS hl. Rl = 9. 1 kQ.
43. Q output of U I open.
33. ·Illc wi re from pi n 6 10 pin 10 and thc grou nd wire are
45. SIT input of UI open.
fC"Crsc:d 00 lhe protObo.1rd .
47. K input of U2 open.
35. CLR shooed 10 ground . 37. Sec Figure P- 55. Delays nol shown.
Chapter 8
39. Sec Figu re P- 5(,.
I. Sec figUfC P- 5S.
4 s: C 1 = I lIE RI = 3.63 Mil (use 3.9 MQ) 25 s: C ( = 2.2 pF, R( = 10.3 Mil (use 10 Mil) 41. Sec Figure P- 57.
"
FIGURE P-511 RI;.Si>-r
DlSOI nIR I'SIl TRIG
'"
3. Worsl-Ol!;c de lay is 24 ns; il occun; when all ni p-flops changc stale from 011 to 100 or from II I 10 ()(X). co!'>".
5. 8 ns
T
7_ Initiall y. each fli p-nop is reset. 11.OIpF
AtCLK I:
= FIGURE P-56
l u = Ko = I
Thcrefore 0 0 goes 10 a I.
l ( = K( = 0
TIlcrcfore QI remains 11 O.
1l Il
FIGURE P-S1
,
,
,
K
&>. full
ANSWERS TO ODD-N U MBERED PROBLEMS
J 2 = K2 = 0 J)
= K) = 0
Therefore
Q~
remains
l!
•
845
O.
- J
'Ibcreforc Q3 remains a O.
SR
AtCLK2: 10 = Ko = I
Therefore Qo goes 10 a O.
1 , - Kj = I
There fore Q, goes to a I.
eEl'
crr
12 = K2 = 0
There fore Q2 ICmains II O.
h = KJ = 0
Therefore QJ remai ns a O.
I I
I I
I I
I
I I
I I
I I
I I
I I
I I
I
I I
I I I
I I I
I I
I I
I I
__ ~...;.'_;......;'-!-'~,-!-...:..j' I I I._...;~...;.-:-~'-:-;"'''';_ W' ' +, ' I I II I
I
I I
I I
I
"".
'
,
I
I
I I
I I
".~ ,
I
--'-'-iW' r+--i--i-,--',-
-+-~,-+-~,~,~+-~,-~, I
I I
W, ' -:--'f--!-'-!--i-CC-,,-"';'-!-"';,-r
t
I I
I
At eLK3:
,
10 = Ko =
Therefore Qo goes to a !.
Q,
1 , = K\ = 0
ThcrcforcQI remains a I .
0
Therefo re Q2 remai ns a O.
~ -7-+-+-~~~L,-+-+~--~~t-~~~-
0
Therefore Qj remains a O.
12 -
K2 -
h - KJ
""
~ _"-"-"-~'~~~ , -C-"-"-"C-"-"-"-~~_ " _ _ _ _-'HL-_ _ _ _ _ _ _ __
A l:Olllinuation oflhis procctlurc for the ,lCXI seven d ock pul !';Cs will show that the counter progresses through the BCD !1Cqucncc.
FIGURE P - 60
9. Sec Figure P- 59. II. Sec Figure P- 60. I
13. Sec Figure P-6I. IS. The scqUCIlCC is. 11 11.1 110, 1101 , 10 1O.0 101.Thc cou nter '"locks up" in the 1010 and 010 1 stales and a llcrmlles between them.
I
I
I
I
I
I I
I
CLR I
I
I
I I
,, I
e,
I
' I I
I
I
I
I
:
I
I
l"
I
I
I
I
I
I
I
I
II I I I
I I I
L!.J I I
I I
!! I I I I
I
I
--'
,
!II I I I I I I
FIGUR E P_61 t OW
-'--jL....L-'--'----'-17. Sec Figure P-62.
FIGUR E P - 5,)
19. Sec Figure P-63.
Q,
'0
Q.
" Q
, U'
FIGURE P- 61
, '"
Q.
Q,
i!.
Q.
", ,,
Q,
Q.
",
Q,
"
K.
,. ii,
P
",
Q,
"
p,
" 6,
", 1<,
"p,
I
I
I
I
I
I
I
I
I
II I I I I
--~Il~~~~~~~~1
.
,
fIGURE P-6Z
I
,
I
I
I
t ..l.-L...L..- .1 _
I
I I
, ,
Q,
Q,
1 I
I
,
GI ~ Q,
I
I
t-tl
."" , _-:_ L--L.. . . .1. . I i--L--L--I-----1---L-4-1-. ~-
u, JLrlJlJlJlJL
,
I
, I I' lin ___--}_ I_ .......,,
I
I
: :
,>,
",
p,
~
"
Q.
•,
Q,
P.
,
• ~
846
•
ANSWERS TO ODD-NUMBERED PROB LEMS
FIGURE P - 64
-
crw
I OO ~ H~
K
am
,-c
IOHu L7 EN
c r RDlV1 0
<''TR OI VIO
C
,c
L'TR I)IVIO
pc
C
I kHz
am
K
I loo H,_
CffiI)JV IO
pc
CL' I MtU
""~ Q'~ O'~
U
~
~
(!
(!
Q.
(! .
(I
IMS!:II
'~ISB I
(j . IMSIlI
,., FIGUR E P - 65
'"
21. Sec FiBure P-64 for dividc-by-IO.OOO. Add one more DIVIO cou nter to create a d ividc-by- IOO,OC().
'"'
k'
TABLE P-l0
23. Sec FiBufe P--65. 25. CLK2, OU tput 0; CLK4. OUlputs 2. (); CLK6, ()Ulpu t 4: elK8, OUIPUIS 6, 4. 0; ClK 10. OUlput !l: ClK I2. outputs 10.8: CLKI 4,outPUI 12;CLKI6.oulputS 14, 12, 8 27. A glitch oflhc AN D g;;teoutpu t occurs on Ihe III 10 ()(X) trn nsilion. El imi nate by ANDing CLK wit h cou nt er outputs (strobe) or usc G rlly code.
'"
STAGE
OPEN
LOADED COUNT
fOUT
0
63C I
250.006 Hz
63C2
250.0 12 Hz
63C4
250.025 Hz 250.050 H7
2
,
3
mCR
2Y. Hours tens: 0001
0
63DO
250. 100 Hz
Hours unil<;: 0010
2
I
63Fil
2S0.2ooHz
Minutes tens: ()()()()
,
2
63CO
250Hz
3
b3CU
250 Hz
3
0
63CO
250Hz
3
I
31. 64
3
2
"CO 67CO
256.568 Hz
33. (n) Qo and Q I will not change from the ir initia1 state.
263.49 1 Hz
MinUles
unil~ :
000 1
Seconds lens: ()O(X) Seconds
uniL~:
0010
2
250Hz
3
3
6BCO
(b) norma l opcrnlioo exce pt Qo float ing
4
0
73C0
278.520 Hz
(c) Qo w:t\'eform is normal: QI remains in inilial slalc.
4
63C0
250Hz
(d) nomlaloperalion
4
2
63CO
250Hz
(e) The cou nter willllot c hange from its initial stale.
4
3
133('0
1.38.1 kH7
35. The K input of FFI muSt be connected to ground nlthc r than 10 the J inpu t. Cht:ck for ;; wiring t..'lTOf . 37.
I
C20 input toANO gale open and aCling as a HJGH
39. See Table P- IO. 41. The dcrodc 6 gale interprcls count 4 as 1I 6 (0 110) and clears Ihe eou mer back fo O(acrually 0010 since QI is open). The apparent sequence of fhe lens portion of the cou nter is 00 10, 001 I. 00 10. 00 11. 0 110. 43. See Figure P-6
Q, Q•.
r
" r_ 0,
f iGURE P-66
",
ANSWERS TO ODD- NUMBERED PROBLEMS
•
"..
FIGURE P-67
oc,-t:::::::::::::::j:::::::::::::::jt:::::::::::::::t=__________________~'""~D:J 4'. S'-"i,: Figure P- fJlt
55. Q OU lptll of U 3 open
5 1. S'-"i,: Figure P-69.
57. Pin A of G3 open
53. Sec Figure P- 70 .
59. Pin 9 open
FIGURE P-68
~ II>
+t--c--"
M.
, MAXIM IN
r--r--<---/ ,J,.
Q,
FIGURE P - 69 FIGURE P - 7()
'. c Q,
'"
FfU
''''
"
c K,
""
"
c
Q, K,
m
c
'"
K,
""
Q,
_
Il
847
848
•
ANswERS TO OD~ - NUMBERED PROBLEMS
Chapter 9 I. Shift rcgiSlCfS store binary dma.
3. Sec Figure P- 7 1.
,.
Initiall y:
10100 11 t 1(0)
elKI :
0101001 111 00
CLK 2:
0010 1001 r 11 0
elK3:
00010100 1J 11
CLK4 :
000010100 111
eLKS:
1()((l()10 100 11
CLK6:
110000101001
e L K7:
111 0000 101 00
FIGURE p - 7t
e L KS:
0 111 00001010
CLK9:
00 111 0000 10 1
CLK I O:
000 1110000 10
e LKII :
10001 I lOOlOI
CL KI 2:
I I()()) I I 10000
7. Stt Figure P- 72.
9. See I-lBure P- 73. II. Sec R gtlre P- 74.
13- Sr..'C Figure P- 75.
IS. St:c Figure P- 76. 17. St:C Figure P- 71.
n .'
'-'~ ~L:~-i:~1---i-l
:---:--:~~
, ,' - j.:- r--+-~ ---f---1t
__
: -1:=tj=~ 1I -
--j.1--!--H--iL...J-LJ
Q, --:'- :' -
+'___
L
1 I ' " -:--:--;::1--+--f---+''--~1L...J-LJ1--7"--''t , , 1 '" -~--~--'~...i--t..____ j--J'_il ' L.H.....J---'-
FIGURE P-12
Data in
----~
""" _ _ _______..J
FIGURE P- 71
1234S6189101I12 U K Dalain
FIGURE P - 74
--f1-jLfl.[L t
I
CLK
, I
,
t
I
:
;
,
I
l.LJr~---
----r----t-H ...It-j 1---- -
o Q Q, _
___
Q, _ _ _---.JHL ' _ Q) I~" (/, rem"," LOW.
_
_
ANswERS TO ODD-N UMBERED PROBLEMS
FIGURE P- 75
,7
C'K Sf/lt.D
•
849
~ii]--Ji24i1-Ji'L
r
r
I
r
I
I
I
I
I
I
I
I
_l-- Lr r:- -i-- -i---ri---'---'---'---'-+:-+--+--+-I
, r+---+I-, SER -f- -i-- :-.l 4J ,: rl 4, _ ' _-1_-L_-L__'LcI"'--''lcJ,-cJ-1-1_-!_-1__ CLKI NH ~_~_-1
FIGURE P-76
UK
-rll-pLrLFy5L.f6LrL-fil--.FL--.V~ I
SfUW
I
I t
I
,
: , : I
I
I
I
t
I
I
I
I
I
I
I
1
I
I
I
I
I
I
I
I
I
t
I
1 : ii : ::: : : :
tl lt1 SeN --,--,---.-,. CLK IN H
I I I
I I I
I I I
l r~,:4' 1 t I'~ I I I" I I .,----r--' I -, I t I I I I I I I I I I I I I I I : I I I I I I
,
,, ______________--'h 'L__ I),. I' .......l.-J.... I ,.......J...... I I ,.......J.. J I I I LJ...J , l . l- - W I 1 I I I I I I I I I I I I ;::; I I I I I - 1.., 1 I I .--+-+... I I I t ' I L...r-----+---- I I I I I I I I I I I I I SI/JW - " I I I I I I ( I I r I ,- - ,
,
O.R
'...r:-!
,~
-1, ,, ,
""
SR ~I
"
SH~
.. t;R
/), II,
, O)~_ _.LLLl-.
'0)
SRG 4
0) (10)
'"
(I I)
~R q'lt.
74 HC J<)4
m
.. , SI R
c
o
SRG4
"mm
741TC I94
D.'
v, FIGURE P - 78
v,
'QI~ " Q,
, ,
, ,
Q,
'"
FIGURE P 77
1'.
,:
I :
Inil ially (76):
01001 100
ClKI :
10011000
CLK2:
01 00 1100
righl
CLK3:
00 100110
dgh l
ClK4:
000100 11
righl
Cl KS:
00 100 110
left
ClK6:
0100 1100
len
e lK7:
00 100 110
ri ghl
e lK8:
0 1001100
left
25. Sec Figure P- 79.
Cl K9: e lK IO:
00 100 110
right
27. Sec Figure P-ROnn page 850.
01001100
left
29. An incorrect code may be producL-d.
CLKI ):
10011000
left
31. D J inpu t open
lerr
21. Sec Figure P- 78.
23.
-i-i--+--+,---+-f--
...I"/1-~-i-,
----.J-1, ,: Q,---,' l Q. M
Q,
(H)
3
(b) 5
(e) 7
(d) 8
Q.
~f'-i_-tl-i_-+_: H !-,-i,i -+--
~ --------,1""""1 Q.,
Q. _ _ _ _ _ _-'HL~
~ -------~~ ... FIGURE P 79
33. (a) No clock 3 1 swilch closure bccauseof faulty NA ND tnegali\'c-OR) gate or one-shol; open clock (C) input
850
•
ANSWERS TO ODD- NUMBERED PROBLEMS
\/I/i]'j
~~"
, K
, '" G~
SRG4
"
74HC I9.S
~ ~
c
,'1!:!E
n,
SRG4
K
~,,"
14HC I ~
c I.! ~
,
, , tJ\:
I
SRG 4
K
74HCI ~
I
n
'""
c v ~
SRG4 74HC I ~
c
1! l.'..!B.
FtGURE P- 80
39. Comrol n ip-nop: 7476 Clock gencr,l.Ior. 555
to key code register: open SHI Ll) inpu t to key eode
reg ister (h' DiorJc in Ihin! row qx:n: Q! ou tpu t of ri ng eounlc r open
«, The NAN D (negatin:-OR) gate input
CQnncClOO 10
COIJnler: 74LSI 63
the
Dala inpu t rcgislcr: 74LSI64
fin;t column is open or shorted.
Dala outptJl rcgiSICI: 74L$ I99
(.,
41 . Sec Figure P- 8 1.
(b, Comenls of both registcrs do not Change.
«, Third stage Oll tput of data outpu t register rem
43. Sec Figure P- 82.
(d, Cloc k gcncruloc is dis.1bhxl after cach pulse by the fli pnop being con tinuously SET and then RESET.
47. Pin 14 ope n
(d' lbc """"2" inpu t to the column cncode r is open. 35. Co nlCn ts of dat:r OIllPlit regiSicr remain Cothlant.
One-shot: 74 121
45. CLK inpu t of U3 open 4'. Cl K input of U6 open
37. shift registcr A: 100 1 shift register C: 00000 100
FIGURE P - 81
ll
r
lUlU>
", ". " ". ". ",
-1r-- --,,-,.,.--,,-, SR G ~
SRG8
74LS 1'15
141 _~ 1 9'1
C
n' __ ____ ~
,
" "
C
",_____
~
FIGURE P- 12.
'"
,
Q
c
Q
K
" I'm......,.,
,,
,,
C
C
K
UK
.1'$,,,,,
".
SI:1"
K
~
,
<'
"
SIl/lJ)
C
SRG II
ANSWER.S TO ODD- NUMBERED PR.OB LEMS
851
21. 10wl'Sl address: fCO' b
Chapter 10 I. (11) ROM
highest address:
(b) RAM
3. Ad(lress blls provides for transfer of address cede to memory for accessi ng any memory locl1tiol1 in any order for 11 read or wri te opcrntion . Dow btl.\' provides for tm nsfer of data between the microprocessor and the memory or liD.
BhO
~
•
Bhl
Bit2
Bh 3
o o o
o o
o o o
o
o
o
R~O
o o o
R~ I
Row 2 R~3
FFFI ~
23. A hard disk is formatted into tracks and Sf:Clors. Each track is divided into a num ber of SCi:tOC1i with each sector of a track hl1ving a physical address. Hard disks typicl1 lly have from 11 flW hundred to a few thousand trdeks. 25. Magnetic tape: has a longer ac<.tSS time th an dis k because d.ua 111USt be aecessed ~quential1y rather than random ly. 27. Checksum content is in error. 29. (a) ROM 2
.'1.
(b) ROM I
(c) All ROMs
10
7. 512rowsxI288· bil(:olumns
33. PROfo.l will retain cede when power is olT. The code in PROM can not be readily chllflbW unless il is an EEPROM.
9. A SRAM stores bils in nip-Ilops indefinitely as lon~ as power is upplil:d. A DRAM stores bits ill cl1pijcitors thl1t must be refreshed pcriedically 10 retain the dmu.
35. To l1<.tommod:ne a 5-bit entry code. shift fC1! istt.1' C must he loaded with five Os illslead of four. The HIGH ( I) must be moved left one place on the parallel illf.uts.
J J. See Tab le P- II .
Chapter 11 TABLE P- l1
I. X = A IJC + A1JC + AfJC
3. INPUTS
A1
Ao
0)
o o
o
o
O2
0
16 in pu ts and IWO active- LOW ou tputs.
0
1
5. A CPU ) basically consists of multiple SPLD~ lhal can be
o
conncclL-d wi lh
o o
(h) PALl2H6 is a progrJmmable llfrJy logic device with 12 inpUl~ and 6
0
o
o
o o
o
13. Sec Figu re P- 83.
9.
13. la) Combin;]liollat: I
,
0
/
0
0., -
!
IJ, _
2
"· _
4 ~
ABeD (b) ABC(jj + E) = !lBeD + ABeE x = AB + liB XI = ABCD + ABCD + ABeD: Xl = AIlCD + AliCD + AIlCD + ABeD
7. (a)
11.
,, -
(:I) PA L I6L2 is a progrnmmable array logic device wit h
OUTPUTS
15. (a) Registered 17. SOP OUtplil '"
/
".
,,
(h) Rq;istcrcJ: U (c) 0
(b) GCK I
ABC + ABC +ABC + I1IJC +
(>."'POJI.
cuT
. '., ,
:1
"
~
.
1 1"npul
:1 '-'IT
FIGURE P-'l
15. Blown li nk:;: 1- 17, 19-23,25- 3 1, 34,37,38,40--47, 53.55, 58, 61 . 62, 63, 65.67, 69
ABC
LUT for combinational log ic. l1dder logic. and register logic
21. Sec Figure P- 84.
,• ,
, ,"
(d) 0
FIGURE P-B4
17. Usc eight 16k x 4 DRAMs wilh sixtcen addre~ lines. Two of the address lines are decoded 10 enable the selccted memory chips. r"Our data li nes go 10 eacb Chip.
23. Sec Figure P- 85 on pagt' 852.
19. II bilS, 64k wordJ;; 4 bi ts, 256k words
27. See Figure P-86.
25. One s lice
1
852
•
ANSWER.S TO ODD-NUMBERED PROBLEMS
FIGURE P -8 5
",A,,A,,\~A ,, I ~rI,,\,
1/11/,,1/, # fl, I/. II, 11"
,j..----;:=-l~ - -'\'--------- --;::l\c:I::>-- L 4" 1. 1,.1 ,A~rI"I, + 11
1I" IJ
MUX
wr
>.UT
,
R, R.
'.
R. _
"
Slic~
"
1
Sliet: 2
31. Shift inpu t = I, data all: applied LO S DI. go Ihrough Ihe MUX, and are clocked imoC
,.:; ~ . 1.,"
33. PDIIO = 0 and OE ... O. The dula arc applirtllO Ihe input pin a nd go throu gh the selected MUX to the internal programmable logic.
"
J
r
]
35. 0000 1100 101000 11110 11 0
" h
:,.»FIGURE P-86
29. Sec Figure 1'- 87,
FIGURE P-87
0000110010 10001 1110 11 UOOOI H)UIO IOOOl l llO l l
J )-
3
OO Xll lOOIOlOOO ll llO l 1
6
000 J\ II .o1 010001111 Oil
12 0000 ; [()O IO IOOO II IIOlI 9
iXXXlI 1001 0100011 11011
2
0000 1 1U()I Cl IOOO I II 10 11
S
(")(XI() I 1011 1111 000 I I
10
00001100 11)\1100 1 I J 101 1
I 10 1 I
4
OCXXl J HXl JtH(1 () I IIIOll
AN SWERS TO ODD- NUMB ERED PROB LEMS
8
(XX)() I 10010 1000 1 r 11011
I
OOCK>! 100 101 000 1111 01 1
3
OOOO il OO lOl ()1 1!JlI 11Ol i
7
0000 11 0010 1001.) 111 lO l l
IS
0000 11 00 101 (00 111 10 11
14
0000 11 00 101000 11110 11
13
0000 1 IOOlO lin H I I ]() I I
II
0000 1100 [0 1000 111 lOll
37. The D inptJI lo the logic is fau lt y or nOl connected.
Chapter 12 1. CPU, memory, I/O ports, buses 3. A bus is a SCI of co nnections and electrical spccilicati nnN for m{wing informatio n in
II
compll ter.
5. ALU. instruction decoder, register army, and con trol unit
7. Address bus. data bus, and control bus 9. Felch, decode, C)(ccutc
II. CS, 1)5, SS, ES. FS. GS 13. A H and A L arc 8- bit rcgislcrs
17. Sec !-I gure P- 88. I nilial i ~c
to
•
853
27. See Fi~urc P- 89.
Bus _ _ _---'
FIGURE P- 8'J
29. The loc
31. The PCI hus is a 33- or 6(1 MH7., 32- o r 66-bit e)( pansion bus. Thc ISA bus is an R.33 M H ~~ 8- o r 16-bit c)( pansion bus.
33. OCE stllnds fo r data com mun icatio ns I..'q uipment. such as
35. si)( 37. A cont roller i ~ sending data to two listeners. The fi rst two bytes or datll (3 F and 4 1) go the listener wilh llddres... OI.) \ A. The $l."Cond twO bYlcs go 10 thc listener with address 00 18 . The h
TOTAL
~cro
LiMenc .
COlllroi lcr
tal"".
llllcrfacc mD.MgCmc'" b"s
IsNUM
TraJl!,fcr btl<
> IO"! FIGURE P-90
Chapter 13 I ncrement NUM
FIGURE P- 8 8
I. An analog-to-digilal convc rter convert s an analog signal 10 a digiw i code. 3. A digital-to-analog convener changes a digi tal code tn thc corresponding llna log signal.
S. See Figu re P-9 t o n page 854. 19. Whcn thc instruction mOl' ax , [bx) is cJ(ccutoo. thc word in mcmory poi nted to by the bJ( registcr is copied to the a)( registcr. 21. Tn a pollcd 110. the C PU poHseac h device in tum to see jf it needs scn 'icc: in an interrupt.driven system. the pcriphcrn l dev ice signa ls lhe C PU when it requires S(:r vice.
7. 1000. 111 0. 1011 , 01 00.0001. 0 111 , 111 0. 10 11 ,0100. 9. See Figure P- 92.
11. 330 kQ
13. 000, 001. 100, 110, 10 1, 100,0 11.010,001,00 1, 011, 110. 111 , 11 1. 11 1, 111 . 111 , 111 , 111 , 100
23. A prog r.lm instruction that im'Okcs an inferrupt .'>Crvice routine.
IS. Scc l bble P- 12.
25. The C PU is bypassed in DMA.
17. 8(xx) MB/s
854
•
ANSWERS TO ODD- NUMBER ED PROBLEMS
FIGURE P - 91
,
I'
"", , ,
,
I .;
, +-;+ '--1-+i ' "
1 t .
,I I ii' Til I--i--! 1 '-l' , I
,-
-I-'
,
I
"• •
r-t;r--j +' +-+ t- i, 11 I " ,
,
t ,
,
:
,
j~T- -I-i -t-h- r-::: J±--i+ ,, , , L, .: :TT
'
1
~
I
-n- H', ,, , ,, •, , •, ~H~ :H-i-f-i ,T + , , ;-1- , --f! H+ , t,
,
,
'~
,
:
,
i
, -t- '-1- i-,-I
o
1 2 3 4
~
, '" ,,
FIGURE P- 92
'" t--!--' "'" 00 ''"" 0, ---1+ : '00 , 0" , 0" , IT , , 0100 ,, 00' 00' , ,1 1000
010
0 IX»
L
f--I-
,
,
-j
I ,-
~- I -
-
L
--
-1-
i-,
-t
J
-
Greater Ihan V",. reSl.1 MSB
23. See Figure P- 93.
0100
Less Ihlln V... keep Ihe I
25. (a) 14 .3%
0 110
Equal 10 V"" keep Ihl! lrinal sialc)
27. See Figure P-94.
Oulpm
- 1.00 _ 12 - 1.51 _1.7
~,
I-
- 2.2!
,
- f-
1
, It
FIGURE P- '9.1
,
_J
, ~- ---j
(c) O.CXX)3RIJi
(b) (L()I)R%
r-
e-: -
1
I"
1
,
--"0 ' --H~~' - 2.7,
-3.2 --B 0 - 3.7
-!,
Oulpon .mpl;llKlc
-~.OO
- 100
•
- _I
1000
, -"" ,, ,
,
,
,
--
,--
~
--j
,
f-+
1(",-, )
21. Inslruction dispaleh (DP): InSlruCiiOIl packcls OTC Spill imo execute packets and assig nl-xI to functiona l un il ~: Instructio n decode (IX): inslruclions are decoded.
COMMENT
0
,
I_ I-
19. 1.000,000.000
SAR
-"'" -"-10
_!-'.
,
,
,
TABLE P- 12
1 ,
:--.._ L I
q-f -
,
6 7 8 .. 10 II 12 I) 14 15 16 11 18 19 20 2 1 22 23 24;os
,
0000
I
I
:
1
~
~
,
,=t MSB
FIGURE P-94
"",,~at O
Ii
ANSWERS TO ODD-NUMBERED PROBLEMS
17. (a) HIGH
Chapter 14 I. No: VOl ~mi") < VllfI ....n•
3. 0.15 V in HIGH slate; 0.25 V in LOW Slale.
5. Galc C
7. 12 ns
9. Galc C
II. Yes. C-h
13. (al on (f) off
(b) off (d)
(el HIGH
".
15. Sec Figu re P- 95 for onc possible circu it 7411C l25 (Tri$l ''''')
(dl High-Z (b) LOW
la) LOW
(c) LOW
21. Sec Pigure P- 96.
23. (n)Rp = 198Q (b) Rp = 1980. (e)
01\
(b) Floming
Rp = 1980.
25. AlVC 17. (a) A.
/110
X: 9.') ns
C, Dlo X: 6.6ns
(1I) A loX" Xl. X.I : 14 ns
IJloX,:7 ns CloX2: 7 ns DloXJ ;7ns (cl A loX: 11.1 ns IJ loX: 11.1 ns
CtoX: 7.4 ns DIOX: 7.4
n~
29. ECl Oper.tICS with nonsaltJralcd BITs. FIGURE P - 9 5 FIGURE P-96
•
855
Glossa 8(,:t.-.: plor A receiving device on :l bus. nl...."1.!!iS ti me The time from the application of a \'alid memory 00dres..~ 10 the appearance of valid out put d:lla. adde nd In addi tion. the number thm is added to :lJ101her number called the augend. adder A logic cirruil used 10 add IWO bi nary numbers. add ress The loca tion of a given storage ce ll o r group of cells in a memory: : lernal dev ice. on whi ch the address code is ren\. adj accncy C1laracleristic of cells in a Knrnaugh map in which there is a sinllie-mriabic change from one cell 10 another l:ell llCX t 10 it on any of ils four s ides. a lillsing '/be effect created when a signal is sampled at less Ihtl(J 1\\ ice the ~ignal frequency. Al iasing creates unwanted frequeocies that interfere ..... ith the signal frequency.
a iphan ulller ic ConsiMing of numcrllis. 1cUcl"l', nnd other
assembly la ng ull.g(' A programming language thm uses English. like words a nd has a one·to-one corres pondencc to machinc language. associalin' la w In add iti on (ORingl and m ul tiplication (ANDing) of three or more variables. the o rder in which the variables are grouped makes no difference . asta ble Having no stable sla te. An astable ntul tivibrntor oscillates between two quasi -stab lc slates. asyndlronolL~
Having no fi xed timc re lationshi p; nm occ urri ng 1lI
the same time. nsynch l'On(X~<; counle r A type of coun te r in which each stllge is clocked from the o ulpu t of Ihe prttt:ding stage.
nugcnd In addit ion. t.he numhcr 10 wh ic h the addend is addCfJ.
base One of the three rcgion s in a bipolar j unct ion Ir.mSi~ lor.
base add n$.<; The beginning IIddress of a segment of Inefl'lQl)'. BCD Binary coded dcdmal; a d igi tal code in which each of the tk:cima l digi l'i. 0 through I). is representcd by a group of four bits.
chilrtl.;tcn>.
BEDO DKAM BUn>1 extended data output dynamic n mdom·
AI.U Arithme tic log ic uni t; thc key p~~si ng clemeOl ora microproccssor that pe rforms ari thme tic and logic oper.Jti ons.
:lCCCSS memory.
amplitu de In a pulse waveform, the he ight or max imu m ' '3lue of the pulse as measured from its low le vel.
IJ«I -or-na ils A me thod fo r the au to mated tes ti ng of printed cireui t boards in which the bo.l rd is mo unl cd on a fixt ure that rescmh les a bed of nails lrut makes COnl a<:! with lest points.
a nalog Being continOOllS or hav ing conl inuous va lues. as opposed to having a set of discrete V'oilues.
hid in.'(:lional Having two d irections. In a hid irectio nal shift regi1>ter, the s tored dllla can he lohifled right or lefL
an alog-tCH:ligital (AiD) con~'cn;io n analog !iignalto dig ital form.
hlnar}' Having two values or !ila tes: descri bes a number system thlll has a base of two and utili 7.es I and 0 as its digits.
' l1le
process of corwertillg an
ana log-tCH:ligita l com'c rlc r (Al)C) A device used to rom-en an nnalog signal to a sequencc of d ig it al codes.
mos Basic inputlOUIJHII ~yslcm ; a sel of p«Jgmms in ROM that interfaces the I/O devices in a computet' system.
A NI) A basic logic operation in which a t['lIC (HIGH ) output ()(,'CU I'S o nly whe n alt the input conditions are true (HI GH).
bipola r Havi ng two OPpCl8iIC c harge camen> wi lhin the tr..lllsis tOf struct ure.
A ND array An array of AND gates rons istin g of a matrix of progl".unmablc interconnections.
hisclhle Having two s table s tmes. Flip. nops and lalches lire bistable multivibratcm.
AND gatc A log ic gate that prodoces a HIGH OlItJll.U o nly whe n al l of tile inputs are H tGH. ANS I A mcricllO National Standard~ Ins titutc. n nlifusc A Iype of PL D nOIl\'o latilc programmablc li n k that can be le rt ~n o r can he shorted once as direcled by the program.
hit A binary dig.i l. which can be ei ther a. I o r O. bilst ream A serio> of biLS describing a final design thai is sent to the ta.r~'t l device du ri nS programming. bit l ime The in terval oftimc occupicd by a single bi t in a sequenCe of hits; the period of the cloc k.
arch ilcdun' TIle VHDL Iini l th at deSl:.:ribe.~ thc intcrnal openltion of a logic functio n; the int ernal functiona l arrangemen t of the eleme Ols that givc a dc vice i l~ pl.u1icu tar OflCI'ating chamctcristics.
R1U Bus interface unit; lhe portion of the CPU that interfaces wi th the system buses and k tc hes instructions. reads operands. and wri tes res ults.
a rrn) In a PLD, a m atrix formed by rows of prudUL1-term linCli a nd rolumns of input li ~ v. ilh a programmable cell at each j unclion. In VHDL. an amlY is an onlercd SCI o f ind ividual irems call ed ClelTlCllts with a single identifie r name.
for o r am plifil.:ation. A BJT has two j unctions. the basc('mi ne r junction and the b:L~
ASCU l\mc rican 5r..mdard Code fo r In formation Interchange: the Il101.1. wide ly usc:
assem bler A ptq!r..lm that converts Eni! lish-like mnemonics into machine code.
856
BJT Bipolar junction tmnsistor; a semiconductor device used
s\\'i t chin~
Boolean addition In Boolean algebra. the O R operdtion. Roolean albocbra 11te malhematics of logic circuil~. Bvulu lII CKp ra.'ilon A ll expression of \'ariablcs and opemtOl'S
used to express the operntion of a logic circui t. Booh:8n multiplicatio n In Boolean algebra, tilt: AN D opcmtion.
GLOSSARY
boundary scan A mcehod for imcm llJJy Inc H AG ~Ulndard (IEEE SId. 1149. 1). buffer A circui t that
prc\'cnl~
1~ling
a PLD 1xIs«l on
loading of an in pul or o utput.
bus A SCI of imcrconncctions Ihal imcrface one o r more dc\'ices ba..w on a ~tandnrd i 7.cd spccilic31ion.
bus arbitl'1ll.ion The process that pre\'ents
IWO
sources from usillg
•
857
C MOS Complementary metal oxide scmic01duclo r, a class of integrated logic circuits that is implemcnted with a type of fiel de lTecl transistor. code A set of bits armnl,>e
a bus al the SlIme ti me. bu~ conlenlion An ackersc condit ion thaI could occur if Iwo or more deviccs Iry to communicate at the same time on a bus.
"Wet A combilICd coder and dcccdc r. ..-olfcctor One of trIC Ihree. regions in a bipolar trans istor.
byle A group of eight bil., .
10
caclM! melllory A re l:u i\,ely small. high-speed memory Ihat stores Ihc IllO:>t reccnt ly use
commutlllh'c la\\' In additio n (DRing) and multipti cali nn (AN D· ing) of two variables. the o rde r in which Ihe l'aTiables arc O Red o r AN Ded makes no cJifte rence.
I:Optlcil), 'Ille 10lal nu m ber of data un ils (bilS, nibbles. byles, wonl~J Ihal a me mory ca n slore.
comparator II digilal circ uit Ih:t! CUlllPill'CS Ihe magn i!Udtls of tWIl q uarllities and produces an oulpul indicating the rc lalionsbip of the Quant ities.
c8rry The dig it ge ne r.J ted when the ceeds I .
~um
of two binary digilS ex-
ca IT)' gcu(,rIltion TI1C procc~~ of pruducing an out pul carry in full -adder Whcll boIh input bils arc Is.
iI
ealTY propagation 'I1IC process of rippling an input carry 10 become lhe OOlput curry in a full-adde r when eiliv; r or bolh of the input bits are I s and the input cnrry is a I. C8.'iCadc '10 COTlf'ICCI "end· to-eoo" as when SC'\~ral coulllers arc connecu:d from the terminal coum OUlpul of one coumer to the enable inpul of the IICXI counter. ta'iCading Connecting the OU IPUI of one de"ice 10 lhe in ptll of a simila r dev ice. ali owinJ,!. one device to drh'e lHlolhcr in order 10 expand the operational capabililY.
ern C harge·coupled de,,~ : a type of semiconductor memory that Slm~s
d:lta in the foml of d13rge rockels and is serially acccsscd.
CD·H CO-Recordable: an o ptical disk slor,lge dC\'ice on wh idl da!a can be siored o nce. CD·HOl\.'1 An upt ical disk stol'a gc dev ice o n w hich data arc presiored and can un ly be reud. C D· HW CD-Hewritable; an o ptical disk SlOr.Jge on wh ich data can be wrillen and overwritten many tjnles. cell An area o n a Kanmullh map Ihal fepresenls a unique combinat io n of variables in prodUCI rom.: a single storage elemelll in a memory: a fusc
combina tionn llOgic A c(Jmbination of logic gales intcrconnceled produce a s pecified Boolean func tion w ith no storage or memory capabili ty: sometimes caJJed rombilwlOrl(ll logic.
compiler An a pplicati on program in development son\.\~.JIC pock· ages thaI cumruls the desiJ,!.1I flow pnx:es:; and translates soun."C code into objccl code in a format tmt can be logicail ) lestcd o r downlooded 10 a targel devicc. CClmlllenM!nt 1bc in\'crse or opposile of a number; in Boolean alJ,!.ebt1J. the i rn.~rse funct io n, exprc!'.SCd w ith a bar o \'er lhe \·anable. The complement of a I is a O. and \·ice \'ersa. componenl A V II DL feature that can be used 10 predefine the logic function for mu ltiple use througbout a program or programs. contiguous Joined
t~'Cther.
control bus A sel of co nducth'e paths Ihat C
l'Olltroi ullit Thc portio n wilhin the microprocesso r thai pr01licles the ti ming and co m rol signals for gell ing data into and 01.11 o rthc microprocessor and for synchronizing the executio n of instrueli on~.
l:oul1l('r A digitul eircuil capable of counting electronic evenlS. such as ptJlses, by progressing through a SCQuenee of binary slates.
clmrncter A symbol, teller, or nUIIICml.
Crl .•D A comple... proJ,!.ramma lJlc lugic device Ihal cUlIsj~l~ ba.~ica ll y of mult ip le S PlD aTTIlys with programma ble inlcrconnect ; on~ .
circuil A n II ITnnge mem of eleclrical andlor e lectronic cumpu~ nems imerconnecled in slICh a wily as to perfonn a speCified (unclion.
CI'U Celll rni pruo.:essing unit: ttIC main part of a computer l'Cspnn~iblC' lor con trol and proccssing of data; the ctte of a DSP Ihal processes the jX'QJ,!.ram inSi ructi ons.
CLB Configurable logic blOck; a unit of lugil: in an B 'GA that is made up of multiple smaller logic modu les and a local programmable intcrronntcctl hat il> used 10 connect logic modules w ithin thea. u .
crO!iS-a'iSClllhlcr A progrnm that trnnslates an assembly language program for one type of microproct:~sor to an assembly langlJal,'C fo r anod lCTtype of microprocessor. curnml s inking 'I1te action of a circu it in w\':.ich it accepls cummt intn ils o utput from II load.
elenr A n asy nchronous input u".,d 10 reset a fl ip-flop (make the Q o ul ptlt 0 ): 10 place a reg isler orcounlcr in the Slate in which it contains all ll!;.
curn.'I1lllOurcing 'I1IC acli on of II circuit in whic h il sends CUtTCn! Ollt of its o utput aod into a load.
chx'k Thc ba~ic liminJ,!. siJ,!.nal in a digilal system: a periodic W3\'efurm in which tlIC inte rval bclwccn pulses equal s lhe ti me for onc bi t: lhe triggering inpu l of a nip-flop.
data Informmion in mlmeric. alphabclic. o r aher form.
I)AT Digitlll au dio IUpe: u Iypc of mll~ne lic 13pe forma\.
858
•
GLOSSARY
data bus A bidirec tional sct of condu ctive paths on whic h data o r instructio n codes are trans ferred into a microprocessor nr on wh ich the result o f an ope rati on is sent out from the microprocessor. data sclCC:ItlT A circuit that ~ leC1s data from seveml inputs one at u time in a sequence and places them on the output: al!>O called a mu hiplexel: data sheet A document thai ~pedfies par.::nneter va lues mid operating conditions fo r an integ rated cireuit or other device. DCE Data com munications equi pmenl. Ik'hug A codc withi n DOS that all ows variuus oper
To d«rease the binary state of a coulller by one.
delia modu lation A mcthod of analo!!-to-digi tal conversio n using a I-bi t quant ization process.
divisor In a division operation, tbe (IUantit)' that is di vided into the dividend. DI"T Digi tal linear tape; a type of magnetic tape format. DMA Dirccl memory al.: ..-cSs: a method to directly interface 3 peripheral dev ice to memory wi thout using the CPU fo r control. domain All of tnc variables in a Boolean expressio n. "Don't care" A co mbination of inpu t literals th3t cann ot occur and can be used as a I or a 0 o n a Kamaugh map for simplificll.lion. downloading A des ign nov" process in wh ich the log ic design is tr.l1l ~ferrcd from soft ware to hardware. drain One of thc term inals of a field-cffcct transisto r. DRAM Dynam ic r,mdom-al.: ..-ess memory: a type of se miconduclor memory that uses capaci tor.; as the storage c lements and is a vo lati le. read/writ e memory, DSI' Digital sign3i processor: a special type of micropruceSSCl( that processes data in real time. I)SP core The cen tral processing unit of a digital system processor,
UTE Data temli nal e<]uipment. duly q 'cle The ratio of pulse width to peliod ex pressed as a perce ntage.
desig n 110w TIIC process or !>C(juence of operati ons carried ou t 10 program a targel dev icc.
DVD-ROM Digital versat ile disk-ROM: also known a~ di!!ital \'ideo disk-ROM: a type of optical sturdge dev ice o n whieh data is prestored with a much hig her capacity than a C D-ROM.
D 11ip-t1()J) A type of bistable mu ili vibrmor in w hich the out put ass umes the st:,l1e of the D input OIl the trig!!ering edge of a clock pulse.
dynamic memory A type of semico nductor memory having capacitive sto r'dge (-ells that lose stored data o \'e r a period of lime and. thcreforc. must be refreshed.
demultiplexc r (demux) A circuit (digital dc\'icc) that swit.c hcs di gi tal data from one in put line tn sC\'eml OlItput li nes in a s pccified time sequence.
ECI. Emitter-coupled Jogic ; a c l a~s of integrdted logic circuiL~ tlUlt are implemcnted w ith no nsaturating bipolar junctio n tran sistors.
depcmJcncy notali()ll A notationa l system for logic symbols thai s pecifies input and outpu t rel ations hips. thu s full y defining a givcn function: .:111 inte2fll l pan of ANS I/ IEEE Std. 91- 1984. differellce The resu lt of a subtracti on. digit A symbol used 10 express a qU:'lIltity. digital Related to digi ts o r discretc quanti ties: hav ing a set of di screte va lues as o pposcd to C(lfltinu ous \'alues_ digital-to-analug (O/A) comersionllle process of convt:rting 3 seq uence of d igital codes to an analog form . digilal-to-analug eOIlVl'rter (l)AC) A device in which informalion in di gital fo nn is cOlwcned 10 analog fo rm. DI MM Dual in-li ne memory modulI'. diode A se miconducto r device tlmt conducts current in only one directi on. niP Dual in-line package; a type of IC pac kage whose leads must pass throu gh holes to the OlllCr ~ide of a PC board, distribuLive law The law that states that ORing sevcral variablcs and then AN Ding tllC resull wi th a single vari able is equivalCntto ANDing the sin.£le va riable wit h each of the sevel1ll variables und then O Ring the prooJUCL dilidl'nd In a division opcrntion. the quantity that is being divided.
EZCI\'IOS Elect rically erasable CMOS (FECMOS); the circuit tec hn ology used fo r the re progrmnmable cells in a PLD. ('(\gt.'-triggcred flip-nOI) A type of flip-no p in wh ich the data arc emered and appear on tnc o ut put on the same clock edge. r'1JfF Electronic o....-..i!!n i llterehal1~>e fonmu : a Slandan.l fonn oflX!tliSL
EDO DRAM Extended d3ta output dynam ic rando m-access mcmory. EEPROM Elcctricall y erasable prog ram mable read-only mem ory; a Iype of nonvolatil e PLD programmable link based o n elt:clric3I1y-crd.'lable programmablc read-o nl y memory cells and can be turned on o r 01T repeatedl y by pro!ln.tmmin g. emiltcr One of the th ree regio ns in a bipolar j unctio n tronsiMor. enable To activate o r put into an operational mode; an input on a logic circui t that enables its ope rati on. encoder A di!!ital cireu it (dev ice) t11at convcns information 10 a coded form. entily 1lle VHDL unitthlll desc ri bes the inputs and outputs of a logic fu nction. EPROM Erasable progmmmnbic read -only mcmory; A type of PLD no nvolatilc prog ramma ble link based on elcctrically programmable read-mtly memory ct:ll.~ and call be tu rned ei ther on or olT once w ith program ming.
GLOSSARY
error deta1: ion The proc-ess of detecting bit errors in a di gital code. EU F..xllCution uni t; the ponion of a CPU that executes instructions; it conlains Ihe ari lhme tic logic unil (ALU). the gene ral re~islers. ilnd the flags. e\'Cn parity The condition of l11wing an even numhc r of I s in evel)' grou p of bits. exclush'c-NOR (XNOR)gate A logic gate thai produces a LOW only when the two inpuls ,Ire al opposite levels. C):clu.~in.'-OR (XOR) A basic logic operation in which a HIGH occurs when the two inpu ts are at opposile levels.
exclusin .'-OR (XOR) I}'ltc A lo~ic gate thm produces a HIGH only when the two in puts lire ul opposite levels. execute A CPU proceNs in which an instructiun is carried oul: a Ntage o f the DSP pipeli ne operation in whil:h the decoded instmctions are carried oul. CXIKmcnt The paI1 of a floating-point nu mber Iha l represcnts the nu mber ofploces that the decima l point (or binary point) is to be moved. fall time The lime interval between the 90% point and the 10% poinl on thc ncgative-going edge of a pulse. fa n-oul The number of Ci:luiva lent gate inpu ts o f the same f:unily seri e.~ that a logic gatc can drive. fC('dhack The output voltage or a ponion of il lhat is connectcd hilck 10 the input of a cirelli!. FET Field-elTect transistoe. fetch A C PU process in whic h an instrllction is oblained from Ihe mcmory; a SlagI' of the DSP pipeline operation in which an instruction is oIlLained from the program memory. fifo First in- lirst OUI memory. FireWirc 'Ibe IEEE- 13tJ4 standard serial bus. nUer 1001 A compiler soft ware 1001 thaI selects the optim um intercon nections, pin assign ments. and logic cell ass ignmenls 10 fi t a design inio Ihc sclecled target dev ice.
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859
n'GA Field programmablc gate
flag A bit th at indicates the reslill of an ari th metic or logic opcr.llion or is used to alter an operation.
hard disk A mag nclic disk storage device; lypicalty, a slack of two or more rigid disks enclo<;ed in a scaled m using.
flash ADC A si multaneous analog- to-d igilal convener.
hardware The d R1..t itry and physical com pol1t! nls of a computer sySlem (lt~ opposed to the direclions caUed software).
fla~h m.:-nlOry A nonvob.tilc rcadlwritc random-acc(.~ scmiconductor memory in which dala is stored as charge on the noaling gale of a ceI1ain PET.
flip-flop A ba"ic stomge circuit ttUII can slore only one bil at a limc: a synchronous bislable device.
HDL Hardware descriptio n language; a language used for describing a logic de.<;ign using software. hcxildccimul Descri bes a number system with a base of 16. h igh-Ic"el language A type of COlliputer lanl,'llagc closcst 10 human language that is a level aoo\'e a'isembl y language.
floaling-J)()i n l nu mber A number representation baso..."<1 on scientific nolntion in which the numbe r consist"- of an exponenl and a mantissa.
h igh-Z The high-impedance stale of a tristate cireuil in which the oulput is elTectively disco nnected from the rest of the circuit.
flOIJPY disk A magnetic storage device; it nex iblc disk wilh a diameter of3.5 inches and a storage capx ity of 1.44 MB encased in a ri gid plastic ho using.
hold ti me The time intcrval required for the runt rol levels to remai n on the in pu ts to 11 nip-nop
flying llrob.:- A method for the au tomated Icsti ng of printed circuit OO:lrds. in which a probe or probes mm'e from place to place to contact tcst points.
HPm Hewlett-Packard interface bus; SaHlI' as GrlB (ge nera l-
furwllrd bias A voltage polarity cOlldition that al lows a scmkonduelOr fill junelion in 11 t ran.~istor or diode to conduct current.
purpose
inlerf~ cc
bus).
hysler csb A chanIcteristic of a thrcsho ld-u;ggercd cin.:n il. such as the Schmilt Irigger, whe re the device tums on
860
•
GLOSSARY
lEEE Ins titute of Electrical and Eleclf(mics En gineers, IF:EE 48K bus Same:1$ G PIB (general- purpose imerfoce blls): a sta ndard parallel blls IlSed widely for test and mea~urernem interfacing , lEEE 1394 A se rial bus for high-speed data transfer; also known as FireWire.
fL Intcgraled injection
logic: an IC technology_
Implementation The software process whe re the logic s tnlctllTeS described by the netli st are mapped into the structure of the target de\'icc. incn:ment To increase the binary
~ tate
of a cOll nter b)' one.
input'me Signal or line go ing into a circuit: a signal that controls ttw::: operation of a circuit. input/ou tpu t (110) A tcrmina l of a dc\·ice that can be uscd as either an inpIII or as an outpll t. in.~truction
One step in a computer progmm: a unit of infonnation thai tells the CPU what to do. inslrul1ion pairing The process of com bining cerlain independent instructions so tha t they can be executed simulumeously by two scpamle exec ution units.
JTAG Joint test actio n group; the IEEE Std. 11 49.1 standard interface for in-system progr.tmm in g. junction lllC boundary between an 11 n.:gion and al' region in a BJT. Karnaugh map An arrangement of cells re presenti ng the combinations of li tenlls in a Boolean expression and used for a systematic sill1 pJification of the expression. LAB Log ic army block; an SPLD array in a CT'I.D. latch A bistahle dig ital cill~ui t used for storing a bit. latent}' period T he time it lakes for the desired sector to spin under the head once the heud is positioned ove r the de.~ i red track of a ml.lJ?netic hard d isk .
LCCC Leadless ceramic chip carrier, an SMT package that LCD Liquid crystal display. leading edge TIle firstll",lIlsition of a pulse.
least sigJlilicant bit (T..SD) Geller.dl y. the right-most bi t in a binary whole nu mbe r or code.
LED Lighl-emill ing diode.
integer A whole numbe r.
LIFO Last in- fi rst ou t mcmory, memory stack.
int(..>grntcd cir'(:uit (Ie) A type or ci r~:uit in which all of the components arc intcgmted on a sing le chip of scmicondllctive material of \'cry small size.
listener An instnullent capable of receiving data on a GPIB (gener.lI-purposc interface bus).
in tclh.'Ctunl prOperly (IP) Designs owned by the manufacturer of progmmmable logic devices.
11.100 To ente r data into a shift
interfacing 1bc process of making IwO o r mOfC electronic devices or syste ms opemlionall y compatib le wi th each other so that they func tion pro perly together. inte rrupt A computer signal o r instruction that cause.~ the currem process to be te mpura ri ly s topped while a service routine is nm. ill\~n;ion -me conversion of a HIGH level to II LOW leve l or vlee versa; also calle
in\-ertcr A Nar circuit; vice versa.
a circuit that change~ a HI G I·lto a LOW
Of
ha~
metallic contacts molded into its body.
literal fI. va riable tJr the cunlpleme nt of a variable. rcg i ~ ter.
loatl blls An internal bus that connects the m icroprocessor to the cache memory. the main memory. the coprocessor. and the PCI hus control ler. loca l inten:onncct A set of lines that allows interconnections among the eight log ic eleme nt s in a logic amlY block w ithout using the row and t'()llInm interconnecl.'i. logic In digi tnl electronics. the decision-maki ng capabil ity of gate circui ts. in wh ic h a HIGH repre.~e IU S a lrue stateme nt and a lOW represent s a false one.
110 port Inpulloulput purl ; the interface between an internal bus and a peripllcral.
logi c array block (LAB) A grou p of macrocells tlUlt can be interconnected w ilh other LABs o r to other 1I0s using a programmable interconnect array; also called a function bloc!;.
II' Instructi on pointer: a ~pecial register within the CPU Ihat ho lds the olrSel address of the next instruction 10 be executed.
logk clement The ~mallesl section of logic in an A>G A that typically contains an LUT. a~soc iated logic. nnd a nip--nop.
ISA hus
I ndo~try
standard architeclu re bus: an intema l parallel
bus standard.
1ST' In-system pro~mming: a method for programming SP U)~ after they are installed on a prinTed cireu it board
luuk -a head carry A melhod of binnry add it ion where by carries from preceding adder stages arc amicip..1ted. thus eliminating carry propagation delays. LS I Large-scale integration: a level of fi xed-funeli on IC c,)mp lexity ill which there are from more than 100 to IO.OOOequivale nt gates perchip.
ja:t. ca rtrid ge A mag ncti c ~to rnge dev ice; ha rd d isks e ncased in a rigid pl astic cartridge with slorage C
LlIT Look -up tab le: a Iype of memory that can be programmed to
j-K fJil>-fl np A ty pe uf mp-nop that can olX'rate in the SET. RESE'[ no-chango:. lind t o~~le modes.
machine code TIle basic binary instructions undeTlltood by lhe processor,
johltsun rount~r A type of reg ister in wh ich a specilic prestored pattern o f I s and Os is s hilled through the stages. creating a unique sequCJ1ce of bit p;..lIcms.
mochinc language Computer instructions wri tten in binary code that are understood b)' a com puter; the 1000'est level of programmin g language.
produce SOP functions,
G LOSSARY
•
861
macf"O<."CIl An SOP logic umlY with (:ombi nati onal and registered out pu ts: pan ofa PAL or GAL that general ly consists of one OR gale and some as~i at ed oUlput logic. Mu lliple inlt:rconnccted mocrocells fonn a CPLD.
ncgalh'c-AND An equivalent NOR gate opem.ion in which the [-J1GH is the active input when all inputs are LOW.
magnctu-oJltieal disk A stontge deviee that uses t:iectroma}.!nctism and a laser beam 10 rClld and wri te data. magllitude The size or vfl lue of a quantity.
nellist A detailed listing of inform1t1 io n necessary to describe a circuit, such as t)pes of elemenl~. i npul~, and outputs, and al1 intt..'rcon noctions.
mantissa The magnitude of a fl oating-point number.
nibble A group oj" four bits.
memory array An alr.lY of memory cells arranged in mws and columns.
\"ii\'IOS An II-channc l llleial-oxide semiconductor.
!\In '-LOI"S Million noati ng-poil1 t opemtions per second. microprocessvr A large-scale digita l integrated circuit (]eviCt: that can be pmgrJ.mmed wit h a scri es of instructions to perform specified functions on data. minimil.alion -n le process th:1t resu lts in an SOP or POS Boolean ex pression that contains the fewest possible terms with the fewest possib le li terals per term. minuend The numbe r from which anot her nu mbe r is sublracted.
MJPS Million instructions per secnnd.
nl.>gati''t.' -OR An equi valent NAND gate operation in which the HIGH is the active input when one or more of tile ill puts are LOW.
node A common connection poi nt in u circuit in which a gate outpu t is connected to one or more gate iupaLS. noi~c immuni ty The ability of a circu il to rejcct un w:mled signals.
lIoise ma l-gin The difference between the max imum LOW output of a gate and the rmVlim um acccptable LOW input of an eq uivalent gate; a lSt), the dilference between the mini mu m UIGH outpu l of a gate and the Ininimum HIGH inpu t of an equivalent gate. nonHJlalile A tenn that describes 1\ memory tllat clln retain stored when the power is removed,
daUI
MMACS Million mu ltiply/accumu lates per SC(;ond,
NOR gate A logic gale in which the Out put is LOW when lm y or all of the input~ are HIGH.
mnemonic An English-like instruction that is convened by an usscmbler into a machine code for use by a processor.
NOT A basic logic opcmtiun that performs im'er.;ions.
modem A modu lator/demodulator for in1erfacing digital devices 10 analog tmnsmission systems such as telephone li nes. modulus The number of unique states thJ"tlu gh which a counter wi ll ~eq uence.
numcrk Relatcd to numbers. Nyquist fn.'tlucncy The highest sib'llal frequency that can be ~ml pled at a speCified sampling frelJuenc)': a frequency equal to or less th:tll hnlf the samplinf.! frequency,
monostable Having only one stable ~tJ te . A rnonost,lb le rn ultivibmlOr, commonly cal led a one-shot, produce_~ a single pulse in response to a triggeling input.
object program A machine language trJ.\lslat:on ofa high-level SlIun;c program.
mUliotonieity The characteristic of a DAC defined by the absence of any incorrect ~tcp rcvcr.;als: one type of digital-t(}-am1iog lineari ty.
odd parily The condition of having an odd nLmher of Is in e\'ery group of bits.
l\.·tOS Meta l--Q)\ide semiconductor;
(I
type of transistor technology.
MOSF'ET Metal-o>;ide semiconductor field--effectt ransistor, most signifiClint b it (MSm 'll1.e left-most bit i n a bi nary whole number or (."Q{le. MSI Medium-s(.'ale in tegnl.lio n; a level of fixed-funct ion Ie complexity in wh ich there:lre from 10 to 100 equivalen t gutes per chi p, OluUi)llcxcr (n1llx) A circuit (digital device) that switches digi t(1i da ta from sc\'eml input li nes onto a single output line in a specified time sc(Juence. mul til>licand 'llle number Ihat is being mu ltiplied by :mother /llnl1her. nmlliJllicr The number that multiplies the Illulti plicand. mult ivibrn tor A class of digital circuits in which the output is connected back to the input (an alT:l.ngeme nt called reedback) to produce eit her two stablc States, one stable state, or no st~lble stales. depending on the confi guration. NAND gale A logic circuit in which il LOW output occur.; only if all the inputs arc HIGH.
octal Describes a numbe r ~yste m with a base or eight.
offset address The distance in number of bytes of a physical ad dress from the base addnoN>. OLMC Outllullogic macrocell ; the pari of a GA L that C:1n be progmmmt.""
01"
862
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G LOSSARY
oscillato r An clcclronic cireuillhat is based on I ~ principle of rcllener.ltive feedback and produces a repetit ive 0l11Pllt waveform: a ~ ignal source.
prdelching Thc process of exccuting instmctio ns at the same ti mc as o ther instnlclions are "'fetched :" eliminating idle time; also Ca lled pipelining .
OTP One-lime programmable.
prL~t An asynchronous inputuscd to set a flip-flop (ma ke the Q output I).
output The signal or line cuming oUl of a cireuil. O\'crflow 'me condi l; on Ih at oceurs when the number of bils in a sum exceeds the nllmber of bils in each of the numbcn; added. I'AL Programmable array Ingi,: a type of one- progrommable S PlD that (,:Qnsi.~ts of u prognlmmublc array of AND gate.~ that connects 10 a fi xed array of OR gates. Ilarallciin di gita l syslems, dutu oc,urring simul taneous ly on severo l lines: lhe tmnsfer or pro(:e....sing of several bits simultancousl y. lln rity In relati on to binary 'odes. the oondition of eve nness or oodness of Ihe number of I s in :1 cooe group. Ilarity b it A bil al1ached to each group of infomlatiun bits to make the tolal number of Is odd o r e\'Cn for e..-ery group of bits. 1'<:1 bu... Pe ripheral 001111'01 inte rconnect bus: an inlemal para llel bus s tandard.
JlCriod (n TIle time required for 11 periodic waveform to repeat itselr. JlCriodic De.';(:I; bes a waveform that
rcpeal~
itself m a fixed inu:rvnl.
pcl'iph('ml A device or instrument that provides communication wi th " compo ter or provides :1lJ);i liary servit.--es vr I"unclions fur !he oomputer. physical
addn's.~
'Jbe actual location of a dma un it in memOl)'.
PIC Progmmabk interrupt COfltrollcr: handlcs the interrupts o n a priority basis. Jli peli nc As applied to memories, an implementation that allows a read or w rit t' operation to be ini tiated beforc the previous operalion is <.:omp1e Hxl: pan of lhe DSP arehileCfUre that al1()\.\ts l11u ltipie instruc ti ons 10 be processed simu ltaneously.
primiUv(' A oo~k logic clemenl such as a gale o r nip-nop, inpulloutput pins, ground. and V<''C. priority encodcr An encoder in which 0111y Ile highest va llie in· put digit is e ncoded and any other acti\'c input is ignored. p robe An at;t;e;sory used 10 t;Omlt;C\ a VOIt.1!!t to the input of an oscilloscope o r other instmment. product The resu lt of a multiplication. p m d ucl-of_s mns (POS) A fonn of Boolean expres~ion that is basically the ANDing of ORed terms. produ('ttcrm 'Ille Boolean product of Iwo or more li terab equ i\'alent to an AN D operation. 11rob'I"Um A list of Compuler instru,tions arranged to achi('\"e a speci fic result ; software.
programmable illt
cOlldut;tor~
)'ROM Programmable read-on ly Sl'micondllttor memory; an SPlD w ilh a fi xed AND array and progmmll"able O R array; uscd as a memory devke and no rmall y not as a logic circuit device. propagation delay 11111(' Thc time interval bet.... ccn !he occurrence of an inputtrnnsition and the oocurrence oflhe corresponding ou tput transit ion in a logic circuil. pM.1Jdo-opcratiun An inSinlC\ion to the asse.,bler las opposed to a processor). pull-up resistor A res istor w ith one end conncctt'd to the dc suppl y vo ltage used 10 keep a given ]Xlint in a circtlit HIG H whe n in tht: inocti\'e state.
PLA Programnmblc logk array: an SPLD with programmllblc AN D mId OR UIT'..ty s.
pulse A sudden ebange from one I('vel to ancthcr. lo ll owcd after a time. ca ll ed th e pul se width. by a s udden e haOJ;e back to the ori gi· nal leveL
pl nlform "-PGA An FPGt\ thut contains eilht'r or both bard oore and soft core cmbedded processors and othe r functions,
11Uise width (t...) 'Ille lime imerval belweeu l1.e SO<1- IXl intl> of the leading and lrailing edge.~ of the pu lse: the d~ration (If Ihc pulse.
PLCC Plasti c leaded chip carrier; an SMT package whose leads arc fUrned lip unde r its hoUy III a J-type shape.
OIC Quan er-inch ,usse tte: a type o f l11agneti~ tape.
PlD Prog rammabl e logic dcvi<.--e; an imegr.l1ed cireuillhm can be. programmed w ith any specified log ic tilllction.
(IUunth:lltion The process whereby a binary code is ass igned to each sa mpled \'a luc during analog-to-dig ita l wnvcrsion.
Pf\.'1OS A p-dlannel me tOl I-t)xide sem;t:ondUt:tur.
(IUeuC A high-speed memory that stOfCS instnletio ns or data.
pointer The contcnts of a reg ister (or registers) that oontain an ad dres..~.
)lOliing The process of checking a series of peripllt'ral dt'\'iccs to determ inc if any require service frum the C PU,
pori A
phY~;C:l1
pa.~,;ed 10
inte rlace on a oomputer through w hich data are
or fmm pel'i pherols.
posith'c logic llJc syslcm of rcpre..ent ing a bi nary I with a HIG H and a binary 0 wi th a l OW. powt'r dissipation The prod uct of the de supply voltill;le and the de suppl y current in an clcclron ic cireuit; the all1O\JIl t of po""er required by a cireuil.
quoticnt The resu lt of a divi sion. mel' A wndi tion in a logic nctwor).. in whil·h thc difference in propagatio n times through two or more sil!na_paths in Ihe network can produce an erroneous OUlpUi .
RAM Random· access co nductor memory.
I\lClllOf}' ;
a \'o latile reid/write semi·
read The proce.~s of !"Ctrieving dat il from a memOf)'. real mude Operati on of an Jnle l processor in ~ ma nne r to emula te the 8086's I M B of memory.
rcqck To undergo Ir..tnsition (as in a co unter., from the final or ten ninal state back 10 the initial state.
GLOSSA RY
refresh To rel1Cw tile oontent~ of Ddynam ic memory by nx:hHrging the capaci tor slOr-dge cells. regis ter II dig ital circui t capable o f storing :md shifting binary information; typicall y used as n tempor.uy s tOOlg
•
s hin 'Ib movc bi nary data from s tage 10 stage within a ~ ifl register or ()(hcr storage de\1CC o r to movc binary diltil into 01" oot of the device. sig nal A t)'JlC of V HDLobject thllt holds data signall mcing A troublc!;hooting tech nique in which waveforms arc obse rved in a step-by-ste p manner beginnilg at the input alld working t(}\\'tI.rd the oo tput or vice versa. At eoch poi nt the observed wa\'efonn is comparcd w ith the correct signal for that point.
rcloctltll ble M e II progmm tlutl can be moved anywhere with in the memory sp."\Ce wi thou t c hanging the basic code.
sig n hI! The left-most bit of 11 binary number (luit designate s whethe r the number is positive (0) o r negati\'e ( \ ).
rem ainder The mnou nt left o ver after
SII\'IM S in,!!le-in-line mcmory mod ule.
!I
division.
R ESET T he slate of a !lip-nop o r latch w hen the Ol1 tpl1t is 0: the acti on of prodl1ci ng a RES ET state. resolution The nu mbe r of hilS used in an II DC.
renT"SC hillS A \'o ltage 1)D IMity conditio n that pre\'e nts a pfl j unclion of D trnnsisto r o r d iode from conducting c um:nt. ring counle r A register in which II cel1 l1in pa ttern o f Is and Os is (;o ntinuously recirculated. riPllle cn rry A method uf hinilry addition in whic h the output carry from each :ldder becomes the input cany of the next higher-
order :lddt:r. ripple countc r A n
a.~)'nchronous
counter.
r~
time The time required for the pos itive·going edge of a pu lse to go from 10% of its full val ue to 90% ofilS full \·alue. ROM Read-only !;t!mi(:unductor mem •.ory. ill.;<.-cs:;e
seek time The tillle for the rc:ld/write beud in a hard drive to pos i-
863
Sl\'IT Su rfoce-mo ullt tl.'chnology; il n Ie pac kagc tec hnique in whic h thc packuges arc smllller tha n D IPs mtd:lre mounted on the printed slIrfliCC of the PC board. sol'!. core A po n ion oflollic in a n 1'1'011: similar to hard core except it has some programmilblt: fealures. softwa re Compute r programs: prog rams that in~1:ruct a compu ter wh:lt 10 do in order to cany Oll t a givcn sct of tasks. softwa re iI(lt'rrupl lln instrut:tion that in\'okes:ln intelTUpt service rout ine .
sole STTI:lll-outlinc integrated drcu it; an SMT pad;1Ib'C tl\.1I. resell\bIcs:l sm:l.ll DIP but has ilS leads bent out in a "gull-wing" sha.pe. liOIln:e A sending dcvi<.'e of a hus; one of the ~inals o f a fieldeffcct transistor. !\OUn:c p rogram A pt"Ogl1lm wrincn in e ither assembly le\'el lung uage.
or higi1-
lipcW-I)()\\·er Ilrod uCl A performance pamJl1d.er tha.t is the product of the propag:llion de\:1y time and the power d issil)lltion in a d ig ital ci rcuit. S I)I.D Simple program mab le logic dev ice; an amty of AND giltes :lnd OR ga tcs that can he prog rammed to ach ie\'e specified log ic func tions. Fu ur types are P RO M. Pt A. PA L and G ilL. SRAM Stati c r-dll{l o(lI-nccl.'SS me mo ry: a type of PLD volatile prog ramm abll.' link based on s tmic mndo m-xcess me mory cells attd can be turned o n o r otT re pea tedly with progmmming. S-R fli )l- nop A SET-RF.sET !lip-no p.
SSI SllJull-scale int egratiOn; a
level of fixed· function IC complexit y in which there arc up to I0 Cqui \~... lcnt gates per c hip.
tion iL-.elf over the des ired trock for a I~:ld opemtion.
SSOI' S hrink s mall-outline package.
segme nt A ()4 k block of melllOfy.
~1:age
SC(lue ntia l circuil A dig ital circuil whose logic states fo llow a specirled ti me S(.'(lucnce.
Mule diagnull A llrdphic depic1ion of a sequence of st;Ues cr \'allleS.
seria l H:lving one e le men t fo ll owing anotber. a.~ in II se rial tt1lnsfe r of hils~ occuning, as pulses. in SCl:Jllence m tller than si mu ltaneousl)". SET ' n lC slute o f a nip-flop cr la tch when the outpul is I; the action of producing a SI:.I state. set-up time T he ti me inte ..... al required for the cont rol levels to bt: o n the in pu ts to a d igilH l ('ircu it, suc h as a !lip-flo p. pri or 10 the triggeri ng edge of clock pulse.
Onc storage element (flip-nql) in a register.
slatc m achine A logic system exh ibit ing a sequence o f st:ltcs conditioned by illtemnllogic and exte rnal inputs; aIly sequen tia l circllit e}C hihiting a specified SCi:luence of states. s ta li c memo ry A vo lalile semiconducto r memory Ihat uses flipfl ops as the s torlllle cells and is capable or ret.~ning d."lt3 wi thout refreslling. s tomgc The capability of :1 dig it al device to retain bil~; the process of retainin,!! d igi tal da ta fo r later usc. string A contiguous !lequc nce of bytes ()r word s.
864
•
GLOSSARY
slrobing A process of using il poise 10 sample the oc(:unence of an c"e nt at a specified lime in re lation 10 Ihe eve n\.
troobleshouting The tcchnique of systematic31l)' identifyin8, isolaling, and corrccting a f3ul! in a cireuit Of s:r--Iem.
subro uti ne A M!riL'l; uf inMrucliulls Ih ill Ca" be "~.'c l "bled lu~e !ll'" and IIScu re pented ly by a progr:lJTl but prog r.lmmed only once.
II-uth labJe A table showing !he inp uts and corresp
subtral1er A logic circuil used 10 subtrncl two binary numben>.
TSSO J> nun shrin k small-outline pllCkage.
subt railCoo The nu mber that is being sutxrnClcd fmm Ihe minuend.
'I1' L Tra nsisto r-trans istor logic: a c1 3~S of imcgrnlcd logic circuit tha i uses bipolar j unctio n tra nsistors.
sum The result when
IWO
o r more nurnbers are added logelhcr.
Slim-of-llroducts (SOP) A fonn of Boolean expressiun that is basica ll y Ihe DRing of ANDcd ICrms. stirn term The Boolea n sum of two or more litends eq ui\'3!cnl 10 an OR operation. sym;ilronous Having il fixed time relatiunsh ip; occu rring at Ihe Silme tunc.
"'''SOP Thi n vcry small"out line pac kage. UlSI Ult ra large-sca le integratio n: a level of Ie complex ity in which Ihere are more than 100.000 equiv31ert gates pe r chip. unil luad A measure of fan-oul. One 8 31e input rc presems 3 unit load ((J the o utput of a gate wi thin the same Ie fami ly,
synchrono us Cllllllter A type o f coun ter in whi ch cach stage is clocked by the Silme pul)iC.
unil'('rsnl ga te Either 3 NAN D gate o r a NOR gate. The lem} IflliI·er.ml refers to the property of a 8ate that pennils any logic functi on to be implemen ted by thai gate or b? a com bi na ti on of
s~·lIthesis TIle
gates of that ki nd.
software process where the design is Iranslnted into
a netl is\.
unil'efSlll shift regis ter f\ rc!!i stcr thai input and output capabilit y.
ha.~
both seri al and parolld
talker An instnl ment capable uf transm itting data on a GPIB (generoJ-purpuse interface bus).
up/down counter A counter that can through a certain ...equence.
targel deli(-e A PLD muunted on a progmmm inp: fi xture or deve lopmelll board inlO which a SOftW3rc logic design is 10 be downloaded: Ihe prognlmmable logic Uevicc that is being program med.
usn Uni,"ers.'l l serial bus; an ex ternal scri:d hus standard. U" EPROI\I Ult mviolel erdSable
Pro8rc~s
in eilher dircction
progr.lInm~b le
ROM.
terminal L'O u nl ·rlle fi na l SI:l!e in a countcr's ~eq ucncc.
va riable sy mbol used to represent a logical quanti ty Ihat can ha ve a value o r I or (J, usuall y de signated by an ilt He letter.
tc):t ent ry A method of entering a logic design into sc nwflre u ~ ing 3 h3rdware descriptio n language (H DL).
"HOI. A standard hardwa re descri ption I:mpmgc: IEEE Std.
throughput The 3verogc spt.'Cd with which a program is cxecllled.
"LSI Very large -scale inlegra tlo n; a le"eI of Ie com plex it), in
timer A cin:uit that ca n be l~';C'd a.~ '" tJne-:.hOl o r a:s ",n oscillatOr. a cirellit that produces a fixed timc intcrval OUt put.
which there arc fru m mOfe than 10,000 to 100,000 equiva lent gates per chip.
liming d iagn!m A gr3ph of digi tal wavcfonns showin!! the proper time rel3tionship of two or more waveforms and how each waveform changes in rc lmio n to Ihe o thers.
Hllatile The chardCleriSlit: of a prcgra mmabl ~ logic device that loses progrommed data when power is tumcd off.
timing simulation A ~o flw:lre process thm \l...es infonnmion on propagation delays 3nd netli st data to tcst both the logical operotion and the worst-case timing of a design.
weight Tbe \'alue of a di8 it in a number based on its position in the number.
toggle The acti on of a flip-flo!, when it changes sta te on each clock pulse.
woro capacit y T he num be r of words th ai a nemory can store.
totem -pole A type of output in TrL circuits. trniling edge The second transiti on of a pul!;(:. transistor f\ semicondut:lor device cxhibiting CUlTent andlor vo ltage ga in. Whcn used as il swilchi ng de vice. it approx imates an open o r closed switch. trigge r A pul!;(: used to ini ti ate a changc in the state of a logic cireuit tristnte A Iype of OUlput in logic c i rcuil.~ that exhi bi ts three sImes: H IG H, LOW. and hig h-Z; also known a.~ 3-stale.
1076-1993.
won! A complete onit of bi nary data. woro IcngtJl Thc number of bits in a word. WORM Write unce-read IJUmy; a type of op:ical sto rage device. write The process of sIOIin8 d;J\a in a memory. U'r o sUI)prL"\..,ion -Ille process {Jf blnn king OM I lendi ng or Imili ng ,eros in a digital display. Z ip disk A Iype of magnetic storage; a nexible disk with a capacil )' of 100 MB houscd in a rigi d plastic cartridge about lhe size of a noWY.
Index ABEL (A dv;mced Boolean EJtpression LangLwge). 27. 148. 64S Acceptor, 722 Access ti me, 546, 560 Accumulator. 105 Adapti ve logic module (ALl\'I), 634 ADC (anaiog-lo-di git:lJ convener). 6,
28·29,744,75 1-760 dual slope. 754 n:L~h , 752 ~ igl11(j-dclla, 758 simu ltaneous, 752 suocessi\'c approximation, 756 AiD conversion. 6, 28, 74R-762 incorrect code, 76 1 missing code. 760 offset, 761
Addend,68 Adder, 15, 61 , 143,298-3 1\ half, 298, 354 rull, 299. 302, 354 look-ahc3d carry. 309-3 11 parallel, JO I-311 ripple carry, 308 Addcrexp.1nsion, ]05 Add ition. IS, 68, 78 Address, 57 1, 5% Add ress access lime. 546. 560 Addrcs.~ bus, 540, 699. 735
Addres.<; decoder, 54 1, 559 Addrc~~ multip lexing, 55\ Address register, 54 1, 547 Adjacency, 2 11, 226 AHDL (A hem Haillware Descri ption Language). 26. 148 A IM (udvanced interconnect matrix ), 621 Aliasing, 747, 776 Alphanu meric codes, 90. 103 ALU (ari th me tic logic unit ). 698, 70S, 765 Amplifi~r. 5, 752 Am plitude. 8, 28 Analog. 4, 40. 744 Analog oscilloscope, 29 Analog-to-digital convel1l,.T (AIX), 6, 28, 744,75 1-760 AN D army. 144. 168 AN D dependency. 470 AND gatc, 13,24,40, 11 7- 123. 152- 153, ]68, 185-186,299,3 16,606 AND-OR, 200, 246, 606 AND-OR-lnvel1,247 Anti-aliasing fil t(!f, 747 Ant ifuse tcchnoloH. 145. 168 Appliclllions software. 696 Arbit rary wa, 'efonn genemtor, 36 An;hi t(!ct ure, 25, 228, 61 4, 64 1, 765
Ari thmetic Logic Unit (ALU). 698. 705 ASCII. 90-94. IOJ ASMBL (appliclllion specific modular block), 641 Assembl er, 709 Assemb ler directive, 7 12 Assembly language, 708-709, 735 Assened state, 114 Associative laws, 186 Astable mul1 ivibrato r, 406, 4 13 Async hronous. 386.480 Async hronous cQun ter, 4280436 Asynchronous SR AM, 543. 544·547 A lleml:ltion, 29, 32 Audio. 5. 747 Augend,68 Automobi le parking control system, 466 Ball-g rid 'lrray package, 25, 768 Base, 50, 75, 800 Base addres~, 704 Baseline. 8 Baud rate, 728 BCD (binary c(Xk:d dec imal), 16, 84-87, 95, 103,320,324 addit ion, 85 counter, 432, 4<10, 443 decoder. 463 BEDO DRAM, 554 Bed-of-nai ls testing, 662, 678 Bias, 800 Biased exponent, 60 Bidirectional COUnlt::f, 444-447 Bidirectional shin registl,.T, 507-5 10 BiCMOS. 22, 15 1,8 12 Binary, 6, 40, 202, 204 aUcler, 15, 143. 301 -31m addit ion, 57, 127 cou nter, 429, 436-439 datil,1O decoder. 3 16 digit, 6 division, 59 fmetion,52 infomlalion, 9 mu it ip liclllion, 58 numbe r. 50-53 point. 52 subt raction, 57, 69 BIOS, 695 Bipolar j unction transisto r (BJ1), 22, 15 1,800 Bistable multivibrdtor, 372, 4 13 Bit, 6. 40. 50. 538 Bit mani pulation. 7 16 Bilstream, 27. 652
Bil time. 9 Boole. George, 12 Boolean al£ebm. 12. 116. 168. 182-209. 229 add ition. 127, 184 associulive law~, 186 commutati ve laws, 186 DeMorgan'~ I heorem~. 19 1- 194 distribu tive law. 186, 189 domain, 200 expressions, 116, 12 1, 127, 1)4, 139, 187, 195,~227,229,250,4~51,607
laws. 185- 194 multiplication,12 1 IRS ru les. 187- 190 simplification. 196-200 Booleun analysis, 194- 196 Borrow, 15, 58 Boundary scan, 654-661 ,664,678 Breadboard, 409 BSC (boundary scan cell). 656 BSDL (boundary scan description 1anl;Uitge), 666 Buffer, 545, 724 BUr.!I, 548 Bus, 540. 545, 596, 695. 726-734 address. 540, 699. 735 control. 545. 699. 735 duta. 539. 699. 735 E1A-232, 728 extcrnal. 727 FireWirc, 728, 735 General-purpose in:erface (G PlB), 729. 735 IEEE-488. 729 IEEE- 1394,728 internal,726 ISA,72fr727 local, 72fr727 mu l tiplt:~ed, 722 PO. 726-727 RS-232C, 727 RS-422.728 RS-423.728 US B, 728, 736 Bus arbitra tion, 722 Blls wn lenlion, 723. 725 Bns interface un it ( 8 1U). 701 -702 Bus signals, 722 Bypass register, 654 Byte, 65, 103,538,596 Cache memory. 548, 695 CaITY, 15, 56-57, 69-70, 88, 308 generation, 309 propagation, 309
865
866
•
IN DEX
CIlTry look-ahcnd adder. 309-311 Cascade. 306. 354, 457. 480 Cascade c hilin. 639 Cascaded CQllnter. 457-460. 47 J CC D tcharge-coupled dev ice), 578 CD player, S C D-R.584 C D -ROM , 583 CD-R\v' 584 C ell. 2 10. 538. 543. 564. 596. 606 Cell adjacency. 2 11. 226 Cell ular telephone. 764 Channel COll nt , 34 Checkerboard pallern. 587 Checksulll, 586 Chip. 19 C lear. 386. 4 13, 52 1 C loc k, 9. 40, 392. 4 13, 428. 448, 472, 4% C MOS. 7.22. 15 1.1 56. 168.39 1. 786. 794-799.8 17 Coarse-grained. 25. 628 Codec.764 Codes, 6, 15, 87- 10 1 Code com·c rtc r. 15. ]29-33 1 BCD-to-binary, 329 binary-to-Gray, 330 Grn y-to-binary, 33 1 Cul1ectur, 800 Combinational log ie. 246--278. 2%-347 Combi national mode, 624. 626 Commutati\'e laws. 186 ComJX)ct disk (CD). 5 C omparator, 14,3 11-3 15, 566 Compi ler. 27, 40. 646. 6 79. 700 Comple lncnI.60. 114, 116, 168. 184. 189. 19 1,234 Compone nt. VHDL. 267-268. 2112 C Olnponcnt instantiation, 2(f) C omputer. 692-735 C unfigurab le logic block (CL B), 628. 638,678 Comact bounce eli mination. 375 Olnt ro l bus, 545, 699, 735 Cont ro l dcpendency. 469 Comrol unit, 699 Com'ersion NO (anal ug-Io-di ~ it al). 6. 28. 748-762 BCD-to-binary. 329 I3CD-lo-decimal, 85 binary-tIHiec itmll, 52 binary-to-Gray. 88 binary -to-hexadecimal. 7(' binary-tQ-OCtal, 83 D/A (di,g il al -to-ilnalugl. 768-775 decima l-lo-BCD, 85 decimal-to-binary, 53-56 decimal-Io-hexadecimal. 78 dcciln,11-to-octal, 82 frac tional, 55 Gray-Io-binary, 88
hexadecimal-to-binary. 76 hexadecimal-to-dccimal, 77 ot.1al-lo-b inary, 113 OClill-to-decimal, 82 C+" language. 7 17 Count-down c hai n, 458 Counter. 18. 122.396,426-480 asynchronous. 428-436 binary. 429. 4]6-439 cascade(l 457-460. 47 1 decade, 432, 440 sync hronous. 436-457 uJidown.444447 C ounter decoding. 461 -464 Coupling. oscillO!>Copc. ] I C PlD (complex PLD). 23-24, 40. 146. 148, 613-623.679 C PU «(:-entml-proceSliing unit). 694, 735. 766 Cruss-aso;cmb lcr. 709 C RT (cathode-ray lUbe). 2!! ClJPL 148 C uri e point, 582 Current sinking. 793. K05 . KI7 C urrent sourcing. 79 3. 805, 8 17
D/A c()l1\·crsion. 768-775 accUTal),.773 di lTeremia l non linearity. 774 errors, 774 linearity, 773 monolonicity. 773 IlOnmonolOnicity, 774 offset e rror. 775 resolution. 77 1 sca ling time, 773 DAC (digital-to-anal og con\'c n er), 5. 744, 769-773 binary-weig hted-input.7m RflR ladder. 77 1 OAT (digital audio tapel. 582 Data. 10. 40.97 Data ocquisition, 35 Data bus, 539, 699. 735. Data communication equipment (DC E), 728 Data mte buffcring. 575 Data register. 54 1. 707 D..1I:1 SC IC(; tOf, 16. 33 1-]42 Data sheet. 157- 159, 806 Data storage. 494, 579 D..1ta terminal equipme nt ( I)T E), 727 Datil trans ter, 10, 7 16 Data troUlsmission system. 343 IX:: component , ] I DC su pply. 37, 15 1, 155,786 Debug assembler. 71 1 Decade cuull ter. 432, 440 Dedlna! numbe rs. 48-49. 5]-56 Decimal-to-bi nary c()ll\'ersion. 53-56
Decode r. 16. J 16--324. 354. 559 address. 54 1, 559 BC D-to-(kcimal. 32U. 462-463 BCD-to-7 segment. 322-324 bi nary. 3 16 colJnler.46 1464 4-linc-lo-I6-li nc , 317 4- line-to-IO-line.320 l-of- 16.3 17 l -of- 10.320 Della modul ation, 75t! DeMorgan's theorem.'\. 19 1- 194,257 Dcmult iple)lcr (DEMUX), 16, 340-342.354 Dependency notation. 4(f)470. 52 1·522 Design. 447 Design e ntry. 26. 148.645 Design !low, 26. 644. 679 De\'elopme m board. 26. 644 Develo pmcnt soft ware. 26. 643-654 D flip-flop. 382-3!!3, .j 13 Diffe rencc. 15.69 Digi tal, 4, 40 Dig ital d ock. 465 Digital codes. 4. 87- 101 Digital mliltimeter (DMM), 37 Digi tlr tape), 582 Domain. 200 "Do n'l care" (;oudi tion, 220, 234. 449 Double precision. 66 Download. 27.652.679 Drain. 794 DRAM (D)'namic Ra ndom Acces.~ Memory), 542. 549-555. 567. 596 FPM, 554 EOO.554 BEDO, 554 syochronous. 554 DS P (Digital Signal Processor), 762-768, 777 OS]> cure, 765. 777 DS P programming. 762 Dual gale symbols, 258, 26 1
I NDEX
Dual-slope ADC, 754 DUly cycle, 9, 407 DVD (digitll l versatilc disk). 585 Dynamic input indica tor, 378 Dynamic random-access memory (DRAM). 542. 549-555. 567. 596 ECL (emillcHouplcJ logic), 813, 8 17 Ec ho, 763 Edge-tri ggered flip-fiop, 378-393, 4 13 EDIF (Electronic Dc...ign Interchange Fonnat), 650 EOO DRAM. 554 E2CMOS.1 46,607, 8 16-8!7 EIA (Electronic Industries Association), 727 EPRO M, 145- 146, 168 EEPRO M 146. 168, 555, 563,5(,7, 6 13 EIA-232.728 842 1 code, 84 Eied ron ic ~w itch, 16 Electrostatic discharge (ESD). 22, 798 Embedded functions, 150, 632, 636.642 EmilieI'. 800 Enable. 122. 168.376 Encoder. 16. 324-328,354 decimal-to-BCD, 324 keyboard. 328 priority, 326. 355 Encryption, 765 Entity. 228 EPROM. 145. 168. 555. 56 1-563. 567. 5% Equality, 312 Erasc,565 Error corrcction, 95-10 1, 765 Error detection, 95-96, 343, 765 Even pari ty, 95. 342 Exclusive-NOR, 141. 152. 168. 249 Exclusive-OR, 139-14 1, 152-153, 168, 249,299,3 12, 6 10 Execution un il (EU), 70 1,705 Ex ponent, 66 Ex tended ASCII, 9'2-94 Extended precisioo. 66 Extes!, 654, 666 Falling edge, 7, I 15 Fall lime, 8 Fan oul, 156, 168,79'2,8 17 Fast page mode DRAM. 553 Feedback, 372, 5 10 Fetch/execute. 694, 70 1, 767, 777 Fiekl-cffcct transistor (f ET). 151,562 FIFO (first-in-firsl-out) memolY, 574,596 Filler. 737, 764 ami -alia.~ ing. 747 reconstructi{ln,775 fine-grained, 25, 628 FireWi re, 728, 735
Fitter 1001, 679 Fitl ing, 27, 65 1 555 timer, 403-409 Fixed-function logic, 19-22, 150-158 Flag. 706 Flash memory. 146.563·568,596 Flat schematic, 646 Flip-flop, 17. 378-397, 428,474,494,609 D. 382-383, 495 J-K, 383-386, 428 S-R,379-382 Flip-flop transition table, 449 Floating gale. 145.564.8 16 Floating level. 273 Floating-point number, 65-67, 103 Floppy disk, 18, 58 1 Flow ('han, 586-588, 710 R ow-through SRAM, 548 Flying probe tcsti ng. 663. 679 Fowler-Nordheim tunnd ing, 145 FPCA (tid o-programmable, ga te array), 23-24,4 1. 146. 148,628-642,679 FPGA core, 63 1 FPM DRAM, 554 Fractional number. 48. 55 FllXjuency, 5, 8, 28, 392 Frequency division, 394 Full-adder, 299, 302,354 Full-modulus c>1scading, 460 Functional simulation, 27, 648, 679 Function block (FB), 62 1 Function generator. 36 Fuse technology, 145, 168 Fusible link. 56 1 GA L (generic 11ll1ly logiC), 23, f:iJ7. 679 Gllte, 13,41 , 11 7,794 Gmed latch. 376--378 Gcneral-pul'JX'>SC interra(.'C (GPIB), 729, 135 General register, 705 Glitch, 345, 347, 354, 462, 65 1 Global bus, 614 Graphic enlry, 26, 148.645 Gr.J.ycode .16,87.448.475 Groundi ng, 166 Half-adder, 298, 354 Ham ming (.-OOe, 96-- 10 1, 103 Handling prct:au lions. C MOS. 22. 798 Handshaki ng. 722. 73 1 Han! core, 63 1 Hard disk, 18,579,5%, 695 Hardware d~iption language (I-IDL), 26, 148,228 Harmonics, 745 Hertz, 8 Hexadedmal addition, 78 Hexadecimal numbers, 35, 75-81 , 90, \03 I-Iexadccimal subtrac tion, 80
•
Hex inverter, 152 Hierarchical approach, 646 High-le\'el language, 708, 735 High-le\'cI program millg, 7 17 High-Z state. 724, 798 Hold,748 Hold ti me, 392, 4 13, 541 Horizontal cont rols, o!>Ci lloscope, 31 Host procc!OSOr. 63 1 Hyper page mode DRAM, 554 Hysteresis, 400 Identification register, 654 IEEE 488. 729. 135 IEEE 1394,728 IEEE Std . 754- 1985, t6 IEEE Std. 1076- 1993,228 IEEE Std. [ 149_1 . 149, 168. (;54, (,(,4 Image processing, 763 Implemenlfllion. 27. 650 Index rcgisters, 705 Inequality, 313 Inhibit, 122 Inpul, 13, 4 1 Input/out put ( 1/0 ) interru pt, 7 19 Inpu t/output ( I/O) port, 3 19, 695 Instance., 650 In~t rucl ion, 694, 716 Instruction decoder, 698 Instruction pairing. 701 Instruction pointer, 703 Instruction queue. 101-702 Instruction register, 654 I nst rume nL~, 27-37 In-system programmi ng (lSP), 21, 146, 148 In teger, 65 Integratedeirc uil. 19-22. 4 1.150-159, 784-8 17 ADC0804 AOC, 158 CoolRunncr 1I CPLD, 62 1,626 555 ti mer, 403-409 GAL22 V lO, 6 12 MAX 70Cl0 CPLD.6 14..{j17, 624 MAX If C PLD. 6 18-620 PALl6V8,6 11 Pent ium microprocessor, 706 74ABT,15 1 14AC, 15 1 74Acr. 15 1 74AHC, 151 74AHCT, 15 1 74ALB, l SI 74A LvC, 151 74AL$, 152 74AS, 152 74 BCT.151 74F, 152 74HC, 15 1 74 HCT, 151
867
868
•
INDEX
74 LV, 15 1 74 LVC, 15 1 74 LVT, I5 1 74 LS. 152 74S. 152 74121 n onretri ~crnblc one-~hot. 399 74 AHC74 dua l edge-triggered J-K flipflop, 388 74FI 62 synchronous BCD deeadc counter. 443 74 HCOO q uad 2-i npul NA f'D !;'atc. 159 741-1C85 +'bi l magnitudc (;ompnrator, 3 14 741-IC 1 12 dual J-K nip-flop. 389 74 HC [38 3-linc-to-8- li nc decodcr/dcmux . 344. 346-347 741K147 decima l- to- BCD priority e oc(Xicr. 326 74HC 154 4-line-to- l6-linc decoder. 318.34 1 741-IC 157 quad 2-illptlt dala selector/mu x. 333 74HC I6 1 4-bi! binary counter. 460 741-IC 163 4- bit synchronous binary countcr, 44 1 74 HC I64 IS-bit seri a l in/parallel ou t s hirl rcgister. 500, 52 1 74HC I65 IS-bit pamllell oad shift register. 503 741-1(' I'Xl up/down decade cou lHcr. 446 74HCI94 4-bi l bidirectional univcrsal shin registcr, 509 74HC I95 4-bit para ll cl-an:css shift register. 506. 5 16 74LSOO q uad 2- inpUi NAND galcs, 15K 741...S47 BCD-to-7 segment decoder/drivcr, 322. 336 74L" 75 quad D latch. 377 74 LS 93 4-bit synchlllflous binar), counter. 434 74 LS 122 relriggcrnble OIl1'--m , 400, 403 74 LS 139 dual 2 -line-to-4- li nc dc('wcr/dem ux. 336 74 LS 148 8-linc-to-3-linc c nrode r. 326 74 L" 151 8-bit daw .q:lcc tur/mult iplcxer. 334. 338-339.344 74 LS279 quad S -R latch, 375 74LS280 uddlc\'c n parity gencmtor/Checkcr, 343-344 74LS283 4- bit par-I llci binary adder.
304 74XXOO quad 2-inpu t NAl\'D B:i!es. IS) 74XX02 quad 2-inpu t NOR g al es. 153 74XX04 hex inverters. 153 74 XX08 quad 2-inpu! AND gates, 153 74XX I0 triple 3 -inpUi NA]\'D ga le.~. 15 3
74 X X II tripie 3-input AND gates. 153 74XX20 dual 4-inJ'l1l NAND giltes. 153 74XX 2 1 dual 4-inpllt AND ga tes, 153 74XX27 triple 3-input NOR gates. 153 74XX30 s ingle II -in put NAN D !(ilte. 153 74XX32 quad 2-input OR ga te. 153 74XX86 quad ellclusi\'c-O R gates. 153 TMS32OC6COO DSP. 765 Integrated circuit packages, 20. 24, 152 Intelkct ual property (IP). 633. 679 Intcrfadng .722-725 Inte rpreter. 709 Im errup!. 716, 7 18-720 , 735 Intcrrupt d rivcn 110 . 7 19 IllIcsl. 655, 664 [ n tlu.~iOfl detection. 128 Invalid c()(lc. 85. 220 In vcrsion. 114 In\·crtc r. 13.41. 60-6 1, 11 4- 11 7, 129. 16 8,795 ISA bus, 726-7TJ [SP On-System Programm ing ), 27, 146. 1411 Jack Kilby. 3113 Jaz.58 1 J-K ni p-n op. 383-386, 41 3 lohnson counter, 51 0-51 2 JTAG.27, 149, 168. 654.664 JUlnp.716 Juncti on. ROO Karnaugh map, 2 10-22!S. 234. 449 Kerr effect. 583 Keyboa rd eneooer. 5 19-521 LAB (logk bloc k array). 24-25. 6 13. 679 Lamp tcst, 323 Lands.5K3 Laser. 5 ,18,583-584 Latc h, 372-378, 4 13, 543 Late TIC)' period. 581 LCCC (Jc adles.~ cerami c ch ip carricr), 20-2 1 LCD (l iq uid crysta l d is play), 29 Leading ed!;'e. 7 LED tlig ht emi tt ing diode), 138 Le vel indicator. 11 4 LIFO (lOIst io----first out) memory. 575, 596 Liste ner. 730 Literal, I R4 Loading. 157,502,527. 7n-793 local bus, 726-727 Logic. 12- 19. 41 Log ic ana lyl.L'f. 33-35 logic /l rmy bloc k (l AB), 24. 633 Logic block. 25 Log ic functi on gencrnlor. 337 Log ic level. 6. 156, 786-787
Logic modu lc (LM), 0]0 Logic opernt ions, 12- 14 Logic probe. 36 Log ic pul.<;Cf. 36 Logic schcmatic. 646 Logic Signa l source. 35 Look-ahead em"!)' adder. 309-3 1 I. 354 Loop. 7 16 LSB (leasl signi fic ant bit). 52. 54, 60, 103, 302. 3 12, 428 LSD (least Sig nificant d igi t). 78 LS I (large scale integrat ion). 2 1 LUT (look-u p table), 557, 6 18, 630, 679 M3chi ne languagc. 708-709, 736 Maeroce" . 609. 6 14. 623-6 24. 626. 6 79 Magnetic storngc. 18.579-582 M3gnctic tape , 18.582 M:lgneto-optil'al dis k. 18.582 Magn itude. 14 Manti ssa. 65-66 Mask ROM . 555 Mea ly Siale machine. 447 Memory, 18. 150.448. 536-578. (;95 dynamk. 542. 549·555. 567. 5911 nash, 146. 563-568. 596 magnetic. 17- 18.579-582 rnndom -acccss. 18. 542-555,5%. 6',15 read -only. Ill, 555-563. 567, 596, 695 slOltic, 146. 168, 542-549. 567. 596, 628. 63 1 Memory addrcss. 539 MemO!)' army. 538, 545. 566 Me mory c apac it y. 539, 596 Memory depth, 34 l\'lcmory cxpans ion. 568-574 Memory modules, 572 MCnlO!)' te.~ting. 585 M FLO PS. 766, 777 Microphone. 5 Microprocc.<;,<;or, 150,698-707. 736 Minimiza tion, 2 12. 2 15-2 16. 22 1. 234 Mi nuend,69 M IPS. 76(" 777 MMACS. 766. 777 Mnemon ic. 35. 708 Mode dependcncy, 470 Modem 727, 736 Modu lus . 432, 458, 480 Monostahle mu)tivibralor. 398-404.4 13 Monotonicit )', 773 Moore stale machine , 447 MOSFEf, 22, 794 MOS mcmOl)', 56 1 MSB (mosl signi fi can t bi t), 52, 54. 88, 103. 3 12, 429 MS I (medium scalc illlegratio nJ. 2 1 MuJriplexed bus. 722 Multip[exed lIO, 725
INDE X
Multiplexer (mu;.; ), 16, 331 -340, 354, 467,639 Multiplicand. 70 Mu ltiplicati on. 15. 70 Multiplier, 15, 70 Multi\'ibrator, 372, 398-404, 406, 4 13 Music processing, 763 NAND gate, 129- 134, 152- 153, 168, 191 ,256, 258, 3 16, 372, 461, 796.80 1 NAN D/NAN D. 20 1 Negation indicator, 114 Negath'e-AND. 136-137. 10,11 , 261,282 Negath'e logic, 6 Negatke-OR. 131, 191.258. 282 Net li~1. 27. 650 Next-state table. 448 Nibble. 538 NMOS, 22, 56 1,815 Node, 273, 282 Noisc,4, 15 1 Noise itl\/11Ullity, 151 , 788.817 Noise margin, 788. 8 14. 8 17 Nondestruct ive read, 54 1 Non linearity, 8 No npcriodic,8 Nonvolatile mcmory, 542 NO R gatc, 134- 139, 152- 153, 168, 19 1. 257,26 1. 797 NOT-AN D, 129 NOT operation, 13, 4 1, 60 NOT-OR, 135 Numerical ex pan~ ion, 213 Nyquist frequency, 746, 777 Object eodc. 27 Object progmm. 7W Octal numbers, 82-84, 103 Ckld pa rity, 95, 342 Offsct address, 704 ! 's complement, 60, 62, 64 Onc-~hot, 398-404, 4 13 One-time-programmable (CITP), 145, 147,606 On-the-fl y programming, 27, 150 Op-code, 35, 708 Open co llector gate, 138, 802, 807, 8 17 Opcn drain ga te. 138, 797 Open input, 160, 273 Opcnoutput, 16 1-162,273 Operational amplifier (op-amp}, 752 Optical storage, 583-585 OR gatc. 13, 24, 41, 124- 128, 152-153, 168, 184. 186,607 Oscillator, 406 Oscilloscope, 27-33 Output, 13, 41 O\'erftow, 69 O\'ershool,7
Page mooc, 553 PAL (programmable array logic), 23, 606,679 Parallel adder. 30 1-3 11 Parallel data, 10. 4 1, 393. 467 P'.lmltcl expander, 616 Purnllcl-inlparatlcl out shift rcgiSlcr, 505-507 Par.lIlci-inlscrial oul shift register, 501-505 Parallel loud, 502 P'drallcl-Io-serial eon\'ersion, 467 Parity, 95, 97,103, 342, 354 Purity generator/checker, 342-345 Partial decoding, 432 Panial prod uct, 15,59, 71 PCI. 722, 726 Pentium. 706 Peri od, 8. 28. 408 Periodic, 8 Peripheral, 319, 697, 736 Phusc splitter, 800 Physical address, 704 PIA (progm mmablc interconnect array), 24.613 Pin numbering, 20 Pin~, input and output, 650 Pipeli ned SRIIM, 548 Pipclini ng, 700, 767, 827, 777 PilS.583 PLA (programmilb1c logiC arruy). 620, 626 Placc-and-rntlte, 27, 65 I Plalfonll FPGA, 633 PLCC (plastic-leaded chi p carrier), 20-2 1 PLD (programmable logic de"j(:e), 22-27, 143- 150,604-679 PtD pmflramming, 643-654 PMOS, 8 14 Polarit y indicator. 114 Polled 110, 7 18 Polling, 7 18 Pop opcrati on, 576, 578 Port, 228. 268.Q~0.694. 736 Port map, 269 Positive logk , 6 Power dissipation, 151 , 156,392,4 14, 790, 812,8 17 Power supply, 37 Powers-of-eight, 82 Powers-of-16.77 l'owCTli-of-[cJl, 48 Powers-o f-two, 50. 52 Prefetching, 701 Preset, 386, 4 14 Primitive, 679 PriorilY encoder, 326. 355 Probe, 29. 32, 35 Probe compcn~tion, 32 Product, 15. 70 Prod uct-of-~ums (PUS), 203-206, 22 1, 224 , 234
•
869
Prod uct term, 185,202,234,615-616 Program, 268, 736 Programmable arruy, 24, [44.606 Programmable array logk (PA L). 23. 606 Programmable interconnect urrny (P[A), 24, 613 Programillable interrull cont roller (PtC),7 19 Programmab le link, 144- 147,606 Programmable logic array (P LA), 620. 626 Programmab le logic. 22-27. 143- 150. 604-679 Programmable logic device (I'LD), 22-27, 143-150,604-679 Progmmml.'r , 147 Programming, 26. 147,266-272.564, (,qq. 707-7 18 PROM, 150,555.560-563,596 Pmpagation dc lay time, 15 1, 154, 168, 305, 308,390,4 14, 430,79 1, 81 2,8 17 Proposi tiOlHll statement, 12 Protocol hand ling, 765 Public udd rcss ~yslem. 5 Pull-up res istor, 328, 797, 817 Pulse, 7, 4 1, 115, 122, 263 Pulse train, 8 Pulse trans ition de\cctcr, 381 Pulse width, 8, 392 Push opcrntion, 576-577 QIC (quarter-inch cartridge), 582 QUantization, 749, 7n Queue, 701 QuOlient, 15, 73 Race, 4 10 Rada r, 763 RAM (random uu:css rnemOlY), 18,542555, 596, 695,721 RAM st;Kk, 576 Range o f signed numbers, (,5 Read,539.54 1,546. 564.596 Rea{Vwritc cycle. 546. 552 Read/wri te head, 579 Real mode, 706 Real number, 65 Real timc. 28. 745 Reconstruction fiit er, 775 Rcctangu lar outline symbol. 11 4. 11 7, 124, 129, 135,140,154, 246, 249 RL'Cycle, 429, 480 Refresh, 542, 553 Register, 17,494,527,554 Registcr array, 698 Reg istered logic, 609, 679 Registered mode. 625. 627 Register stock, 575 Retocalable code, 703 Remainder, 15,54
870
•
IN DEX
Rcmo\'able storage, 581,695 Repeated division-by-2 method. 54 Repealed mu ltipJicalion-by-2 method, 56 Reset, .H3. 386, 4 14 , 495 Resol ution. 752 RIMM, 573 Ri ng countcr. 5 12-5 16 Ringing. 7 Ripple blanking. 323 Ripple·carry addl..'f. 308. 355 Ripplc coomcr. 430. 457 Rise time , 8 Rising cdgc. 7, 115 ROM (read-only memory). 18. 555-563. 567 , 596,695 ROM access time, 560 RS-232C,727 RS-422,728 RS-423,728 Sample-and-hold, 744 Samplillg, 28. 745, 777 Sawtooth wa\'efonn. 29 St:hmilllriggcr. 400 Schematic entry, 26, 148, 645.679 Schottky, 152, 804 SCSI (small compuler syslcm imerface). 733. 736 SDRAM.554 Seat belt alaml. 123 Sedor.5lID Security ~y~tem. 525-527, 589-594 Seck time. 58 1 Segment. 702 Scgment register. 702 Semiconductor. 18. 538 Sequential timer. 402 Scrial dala, 10.4 1,467 Serial-infpanillel-{lut shi li register. 499-501 Serial-in/serial out shi n register. 495-499 Scrial ·to-pllr"lJeJ cOlwcrsion. 5 16. 523 Set. 371. 386, 4 14, 4'}';; Settling time, 773 Sct-up time. 39 1. 4 1ll tracing. 275. 282 Sign bit, 62 Signed binary numbers, 62-74 Sign-magnitude. 62-63 SIMM.572
Simulation funl..1iona l, 27, 648, 679 timing. 27, 65 1, 679 Simultaneous NO conversion, 752 Single-precision numbers. fi6 Singlc'gatc [ogk. 154 Slk-c, 638 SMT (surface ffiOUnt lcchno[ogy). 20 Sofl core, 63 1 Softw;lrc, 26, 27 1, M3-654, o'}6 Software illlCmJp(, 7 19 sOle (small outline IC) 20. 152- 153 Sound WllVC. 5 Sourcc. 722. 794 Source code, 27 Source program. 7(}1) SpcHker, 5 Spet.'Ch compn.'Ssion and decomprcssion. 765 Spa.'Ch generation and recogn ition, 763 Speed-power produ<.:t. 156. 792 SPLO (simple programmable log ic device). 23, 4 1. 606-6 12 Square wave, 32 SRAM (smtic RAM). [46, 168,542-549, 567. 596, 628. 631 S-R flip-flop. 379-382 SSI (small scale inlcgmtion). 21 S-R lalch. 372 SSOP. 20 Slack poi mer. 577, 705 Stage, 495, 527 State diagram. 448, 480 State machinc, 448. 480 Slatic memory, 146, 168, 542-549, 567, 5%, 628.631 Storage. 4. 17. 494.579 Storage t;lnk sy~tem. 278-28 1 Stray effects. 8 Strobing, 463 String, 7 16 Slru<.:tuml approach. VI-IOL. 266 !)ubroutinc, 1 1b Suhtrllctcr, [5 Suhtmction. 15. 57.69. 73 SUbtTll hend.69-70 Successive approximation, 756 Sum, 15,57, 68 Sum-of-product~ (SO P), 200-203, 2 12, 224. 234. 247, 606. 639. 646 Sum-or-weights me thod. 53. 5(, Sum tenTI. 184. 204. 234 Suppl y \'oltage. 37. 15 1, 155- [56. 786 Sulfacc mount tcchnology (SMT), 20 Switching speed. 154 Synehrooous. 9, 4 14. 436, 480 Synchronous burst SRAM. 543, 547-549 Synchronous coonlcr. 436-457 Sym:hronous DRAM, 554
Synthesis, 27. 650 System software. 696 Talker, 730 Tape. 18, 582 Targcl dcvit-c. 148. 168.644.679 Telecommunications. 763 Tcnnina[ COOn!. 442, 480 Test access pori (TAP). 655 TI..'S! in ~trumcnts, 27-37 Tc xt emry, 26, 148,645, 679 T flip-flop, 384 Th reshold, 403. 406 Throughput. 702 Tied-together inputs. 8 11 Ti me consmnl, 8, 398 Ti mcdclay, 5 14 Ti me division mu lti plcxing. 17 Timer, 403-409. 4 14, 767 TinK'S. 7 1 Timing dillgram, 10, -I I . [15. 120. 168. 428, 433,437, 440, -157, 5 18 Timing simulation, 27. 65 1. 679 Toggle. 384. 4 14 , 430 ToIcm-pole ou tput, 800, 809, R17 Track, 580 Tmffic lipht control syslCm. 348-353. 4 11 412. 475-479 Trailing edge. 7 Transition table, 449 TriSl,ler, 31 . 378. 398, 405 Trislate logic. 366. 545. 61 D. 723-724, 736. 798, 803. 817 Troubleshooting, 27, 4 1, 160- 166, 272278, 345-347, 4094 11 , 471-474, 522-524. 585-589, 662-667 Truncated sequencc. 432. 460, 47 I Trut h table. I 14, 118, 125, 130. 135, 142. 168, 195.206-208.220. 246. 249,25 1,298-299,303. 374. 379,384 TSSOP.20 "j·rL (trunslstor-lr.msistor IQl:ic). 22. 138, 151 - 152, 156,168, 787.799-8 12, 817 TVSOP.20 2'~ cOlllplernent. 60-61, 63-64, 72. 80 UART (universa l asynchronous receiver lransmiller), 518 ULSI (ult ra large scale integration), 22 Unilload, 157. 168, 793, 8 17 Univcrsal gale. 256-257. 282 Uni versal shifl regisler, 509 Unused input, 157, 8 10 Up/down counter. 444-447 US B (uni versa l serial bus). 728, 736 UV EPROM, 145, 555, 562 V(lrillble. 11 6, 184,234 Vectoring. 7 [9
INDEX
Veri lng. 26. 645 VHDL. 26. 228. 234. 266-272. 645 Virtual ground. 752 Vertical controls, oscilloscope, 31 VLSI (very laf<~e !>Calc integration), 2 1 Volatile memory, 27, 542 Volume. 5 Vot ing system, 306-308
Wave fonn , 7-8, 119, 125, 130, 135, 142, 263.275 Wan:form editor. 27. 272. 648 Weight. 48. 52. 64, 84, 329 Wired-AND, 807 Word, 538, 568. 57 1, 5% Word·capacity expansion. 57 1
•
8 71
Word-length ex pansion. 568 WORM (wri te once-read many) disk, 584 Write, 539-540.546.596 Zero suppression. 323
Zip, 581