`timescale 1ns / 1ps
TestBench_FirFilter
//Owner: Abdul Rehman //Contact:
[email protected] //Please mention reference if this code is used anywhere ////////Clock Generation Code///////////////////// `define clk_per 20 `define clk_cycle(x) #(`clk_per*x) module clock_gen(output reg clk); initial begin clk=0; forever #(`clk_per/2)clk=~clk; #(`clk_per/2)clk=~clk; end endmodule //////////Clock Generation Code Ends////////////// module TestBench_FirFilter; TestBench_FirFilter; // Inputs reg [7:0] xn; reg [3:0] fil_coff; reg set_coff; wire clk; reg rst_n; // Outputs wire [7:0] result; clock_gen c1(clk); // Instantiate the Unit Under Test (UUT) FIR_filter uut ( .result(result), .xn(xn), .fil_coff(fil_coff), .set_coff(set_coff), .clk(clk), .rst_n(rst_n) ); integer i=0; initial begin // Initialize Inputs xn = 0; fil_coff = 0; set_coff = 0; rst_n = 0; `clk_cycle(1); rst_n=1; set_coff=1; //fil_coff=4'b1011; fil_coff=1; `clk_cycle(1); //fil_coff=4'b1011; fil_coff=2; `clk_cycle(1); fil_coff=1; //fil_coff=4'b1101; `clk_cycle(1); fil_coff=2; //fil_coff=4'b1011; `clk_cycle(1); set_coff=0; repeat(15)begin xn=i; `clk_cycle(1); i=i+1; end // Wait 100 ns for global reset to finish $finish; Page 1
TestBench_FirFilter // Add stimulus here end endmodule
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