Tanner EDA simulation Detailed

CHAPTER – 3 SIMULATION TOOL The The tool tool used used for sim simulat ulatiion purp purpos osee for the the enti entire re rese resear arch ch work work is Tann Tanner er EDA EDA tool version 13.0. The features and functionality of this tool has been described below:

3.1 SIMULATION TOOL

The design cycle for the development of electronic circuits includes an important pre-fabrication verification ver ification phase. Because of the expense and time pressures associated with the fabrication step, accurate verification is crucial to efficient design. The role of EDA tool is to help design and verify a circuit’s operation by numerically solving the differential equations describing the circuit. These simulation results allow circuit designers to verify and fine-tune designs before submitting them for fabrication. Tanner EDA tool is a complete circuit design and analysis system that includes: 

Schematic Editor (S-Edit): Schematic editor is a powerful design capture and

analysis package that can generate generat e netlist directly usable in T-Spice simulations. 

T-Spice Circuit Simulator: T-Spice performs fast and accurate simulation of

analog and mixed analog/digital circuits. The simulator includes the latest and best device models available, as a s well as coupled co upled line models and support suppo rt for userdefined device models models via tables or C functions. T-Spice uses uses an extended version of the SPICE input language that is compatible with all industry standard SPICE simulation programs. All of SPICE’s device models are incorporated, as well as resistors, capacitors, inductors, mutual inductors, single and coupled transmission lines, current sources, voltage sources, controlled sources, and a full complement of the latest advanced semiconductor device models from Berkeley and Philips Labs.

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Waveform Editor (W-Edit): W-Edit displays T-Spice simulation output

waveforms as they are being generated during simulation. Visualizing the complex numerical data resulting from VLSI circuit simulation is critical to testing, understanding, and improving those circuits. W-Edit is a waveform viewer that provides ease of use, power, and speed in a flexible environment designed for graphical data presentation. 

Layout Editor (L-Edit): Tanner EDA tool includes L-Edit for layout editing,

Interactive DRC for real-time design rule checking during editing, Standard DRC for hierarchical DRC, Standard Extract for netlist extraction, Standard LVS for layout versus schematic, Node Highlighting for highlighting all geometry associated with a node and SPR for standard cell place & route. 3.2

T-SPICE [57]

To transform your ideas into designs, you must be able to simulate large circuits quickly and with a high degree of accuracy. That means you need a simulation tool that offers fast run times, integrates with your other design tools, and is compatible with industry standards. Tanner T-Spice Circuit Circuit Simulator puts you in in control of simulation jobs with an easy-to-use graphical interface and a faster, more intuitive intuitive design environment. With key features such as multi-threading support, device state plotting, real-time waveform viewing and analysis, and a command wizard for simpler SPICE syntax creation, T-Spice saves you time and money during the simulation phase of your design flow. T-Spice enables more accurate simulations by supporting the latest transistor model odels— s—iincl ncludi uding BSIM4 BSIM4 and and the the Penn Penn Stat Statee Phil Philiips (PSP (PSP)) model odel.. Give Given n that that T-Sp T-Spiice is compatible with a wide range of design solutions and runs on Windows and Linux platforms, it fits easily and cost effectively into into your current tool flow. T-Spice incorporates numerous innovations and improvements not found in other SPICE and SPICE-compatible simulators: 

Speed: T-Spice provides highly optimized code for evaluating device models,

formulating the systems of linear equations, and solving those systems. In addition to the standard direct model evaluation, T-Spice also provides the option of table-base transistor model evaluation, in which the results of device model

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Waveform Editor (W-Edit): W-Edit displays T-Spice simulation output

waveforms as they are being generated during simulation. Visualizing the complex numerical data resulting from VLSI circuit simulation is critical to testing, understanding, and improving those circuits. W-Edit is a waveform viewer that provides ease of use, power, and speed in a flexible environment designed for graphical data presentation. 

Layout Editor (L-Edit): Tanner EDA tool includes L-Edit for layout editing,

Interactive DRC for real-time design rule checking during editing, Standard DRC for hierarchical DRC, Standard Extract for netlist extraction, Standard LVS for layout versus schematic, Node Highlighting for highlighting all geometry associated with a node and SPR for standard cell place & route. 3.2

T-SPICE [57]

To transform your ideas into designs, you must be able to simulate large circuits quickly and with a high degree of accuracy. That means you need a simulation tool that offers fast run times, integrates with your other design tools, and is compatible with industry standards. Tanner T-Spice Circuit Circuit Simulator puts you in in control of simulation jobs with an easy-to-use graphical interface and a faster, more intuitive intuitive design environment. With key features such as multi-threading support, device state plotting, real-time waveform viewing and analysis, and a command wizard for simpler SPICE syntax creation, T-Spice saves you time and money during the simulation phase of your design flow. T-Spice enables more accurate simulations by supporting the latest transistor model odels— s—iincl ncludi uding BSIM4 BSIM4 and and the the Penn Penn Stat Statee Phil Philiips (PSP (PSP)) model odel.. Give Given n that that T-Sp T-Spiice is compatible with a wide range of design solutions and runs on Windows and Linux platforms, it fits easily and cost effectively into into your current tool flow. T-Spice incorporates numerous innovations and improvements not found in other SPICE and SPICE-compatible simulators: 

Speed: T-Spice provides highly optimized code for evaluating device models,

formulating the systems of linear equations, and solving those systems. In addition to the standard direct model evaluation, T-Spice also provides the option of table-base transistor model evaluation, in which the results of device model

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evaluations are stored in tables and reused. Because evaluation of device models can be computationally expensive, this technique can yield dramatic simulation speed increases. 

Convergence : T-Spice uses advanced mathematical methods to achieve superior

numerical stability. Large circuits and feedback circuits, impossible to analyze with other SPICE products, can be simulated in T-Spice. 

Accuracy: T-Spice uses very accurate numerical methods and charge

conservation to achieve superior simulation accuracy. 

Macro modeling: T-Spice simulates circuits containing “black box” macro

devices. A macro device can directly use experimental data as its device model. Macro devices can also represent complex devices, such as logic gates, for which only the overall transfer characteristics, are of interest. 

Input language extensions: The T-Spice input language is an enriched version of

the standard SPICE language. It contains many enhancements, including parameters, algebraic expressions, and a powerful bit and bus input wave specification syntax. 

External model interface: You can develop custom device models using C or

C++. 

Runtime waveform viewing: The W-Edit waveform viewer displays graphical

results during simulation. T-Spice analysis results for voltages, currents, charges, and power can be written to single or multiple files.

T-Spice also supports foundry extensions, including HSPICE foundry extensions to models. •

Supports PSP, BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, 11, 20, 30, 31, 40, PSP, RPI a-Si & Poly-Si Poly-Si TFT, VBIC, Modella, and MEXTRAM MEXTRAM models.

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Includes two stress effect models, from the Berkeley BSIM4 model and from TSMC processes processes,, in the BSIM3 BSIM3 model to provide more more accuracy in in smaller geometry processes.

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Supports gate and body resistance networks in RF modeling.

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Performs non-quasi-static (NQS) modeling.

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Supports comprehensive geometry-based parasitic models for multi-finger devices.

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Models partially depleted, fully depleted, and unified FD-PD SOI devices.

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Models self-heating and RF resistor networks.

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Performs table-based modeling for using measured device data to model a device.

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Includes enhanced diode and temperature equations to improve compatibility with many foundry model libraries.

Work in a faster, easier design environment

T-Spice helps integrate your design flow from schematic capture through simulation and waveform viewing. An easy-to-use point-and-click environment gives you complete control over the simulation process for greater efficiency and productivity. •

Enables easy creation of syntax-correct SPICE through a command wizard.

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Highlights SPICE Syntax through a text editor.

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Provides Fast, Accurate, and Precise options to enable optimal balance of accuracy and performance.

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Enables you to link from syntax errors to the SPICE deck by double clicking.

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Supports Verilog-A for analog behavioral modeling, allowing designers to prove system level designs before doing full device level design.

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Provides “.alter” command for easy what-if simulations with netlist changes.

Perform sophisticated analysis

T-Spice uses superior numerical techniques to achieve convergence for circuits that are often impossible to simulate with other SPICE programs. The types of circuit analysis it performs include: •

DC and AC analysis.

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Transient analysis with Gear or trapezoidal integration.

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Enhanced noise analysis.

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Monte Carlo analysis over unlimited variables and trials with device and lot variations.

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Virtual measurements with functions for timing, error, and statistical analysis including common measurements such as delay, rise time, frequency, period, pulse width, settling time, and slew rate.

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Parameter sweeping using linear, log, discrete value, or external file data sweeps.

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64-bit engine for increased capacity and higher performance.

With T-Spice, you can

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Optimize designs with variables and multiple constraints by applying a Levenberg-Marquardt non-linear optimizer.

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Perform Safe Operating Area (SOA) checks to create robust designs.

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Use bit and bus logic waveform inputs.

Benefit from flexible licensing

When you purchase a new design tool, licensing options can greatly affect your total cost of ownership. T-Spice is available in node-locked and networked configurations offering you the most flexible licensing possible. With a single solution, T-Spice will work whenever and wherever meeting the design needs of your main workgroup and remote workers. If you offshore design projects, T-Spice does not have geographic restriction on its licenses, thus, lowering your total cost of ownership.

3.3

SCHEMATIC EDITOR [58]

Schematic Editor (S-Edit) is an easy-to-use PC-based design environment for schematic capture. It gives you the power you need to handle your most complex full custom IC design capture. S-Edit is tightly integrated with Tanner EDA’s T-Spice simulation, L-Edit layout, and HiPer verification tools. S-Edit helps you meet the demands of today’s fast-paced market by optimizing your productivity and speeding your concepts to silicon. Its efficient design capture process integrates easily with third-party tools. S-Edit enables you to explore design choices and provides an easy-to-use view into the consequences of those choices. A faster design cycle gives you more flexibility in moving to an optimal solution—freeing up more time and resources for process corner validation. The results are less risk downstream, higher yield, and quicker time to market.

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Schematic capture for the most complex full custom IC design

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Bus support speeds the creation of mixed signal designs.

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Advanced array support enables easy creation and editing of memory, imaging, or circuits with repetitive blocks.

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Rubberband connectivity editing enables faster design modifications.

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S-Edit displays evaluated parameters in real time over the course of the design process. Parameters with formulas based on other circuit parameters can be displayed or evaluated.

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Auto symbol generation enables you to easily create symbols from schematics, and synchronize any changes.

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All actions are fully scriptable through the TCL/ Tk command language.

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Recordable scripts enable you to automate tasks or expand the tool for application-specific needs.

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Replay-able logs permit recovery if there is an unexpected network or hardware failure.

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S-Edit performs net highlighting and keeps the net highlighted as you move through the hierarchy.

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Cross probe from SPICE net lists and LVS to highlighting nets or devices.

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Schematic ERC enables you to check your design for common errors such as undriven nets, unconnected pins and multiple output pins connected together. The design checks are fully configurable, including custom validation scripts.

Tight integration with simulation

•

S-Edit is tightly integrated with simulation. You can drive the simulator from within the schematic capture environment, viewing o perating point results directly on the schematic and performing waveform cross-probing to view node voltages and device terminal currents or charges.

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S-Edit creates an efficient flow for the iterative loop of design, simulation, analysis, and tweaking of circuit parameters. The IC designer can focus on the design and not on data processing—thereby speeding up the design process.

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Easy interoperability with third party tools and legacy data

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S-Edit imports schematics via EDIF from third party tools, including Cadence®, Mentor, Laker and ViewDraw with automatic conversion of schematics and properties for seamless integration of legacy data.

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Net lists can be exported in flexible, user-configurable formats, including SPICE and CDL variants, EDIF, structural Verilog, and struct ural VHDL.

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Library support in S-Edit maximizes the reuse of IP developed in previous projects, or imported from third- party vendors.

Powerful and easy-to-use interface

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S-Edit brings to front-end design capture the ease-of-use and design productivity for which Tanner Tools are known.

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A fully user-programmable design environment allows you to remap hotkeys, create new toolbars, and customize the view to your preference—all in a streamlined GUI.

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The complete user interface is available in multiple languages. S-Edit currently supports English, Japanese, Simplified and Traditional Chinese.

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S-Edit provides Unicode support. All user data can be entered in international character sets.

Cost-effective

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S-Edit provides an ideal performance to-cost ratio, allowing you to maximize the number of designers on a project.

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Since S-Edit is Windows-based, designers can work on cost-effective workstations or laptops. This means you can take your work with you anywhere—even home—and continue working to meet time-to-market pressures.

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Available in two configurations—full schematic editor, and schematic viewer.

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Easy to manage

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Human-readable technology files and design databases are revision-control system-compatible.

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CAD managers can control distribution and access rights to the technology or design. The format allows revision control systems to manage revisions over the course of the design process.


When you purchase a new design tool, licensing options can greatly affect your total cost of ownership. S-Edit is available in node-locked and networked configurations offering you the most flexible licensing possible. With a single solution, S-Edit will work whenever and wherever meeting the design needs of your main workgroup and remote workers. If you offshore design projects, S-Edit does not have geographic restriction on its licenses, thus, lowering your total cost of ownership.

3.4

LAYOUT EDITOR [59]

In today’s analog design world, speed is more important than ever. To compete in a high-efficiency, high-productivity marketplace, you need a toolset that has proven its ability to accelerate the design cycles o f commercially successful projects. Tanner EDA’s Layout Editor (L-Edit) meets our needs by combining the fastest rendering available with powerful features that exceed the needs of the most demanding user. This leading analog/ mixed signal IC design tool for the PC platform enables you to get started with minimal training. You can draw and edit quickly, with fewer keystrokes and mouse clicks than other layout tools. Using powerful features such as interactive DRC, object snapping, and alignment, you can work more efficiently to save time and money. L-Edit increases productivity by enabling you to import Cadence Virtuoso technology and display files for quick setup. Save time by using foundry-provided files directly, allowing you to avoid having to set up technology information manually. Once you’ve begun using L-Edit, the CAD support burden for your physical design tools will be reduced, enabling you to focus on other mission critical tasks.

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Create layout with precision

L-Edit gives you greater precision by enabling you to perform complex Boolean and derived layer operations with polygons of arbitrary shape and curvature. Perform AND, OR, XOR, Subtract, Grow, and Shrink on groups of objects. You can display coordinate and distance values in any technology unit, and automatically add guard rings around any shape. Further increase your productivity by mapping multiple layout functions to a single keystroke. •

Perform complete hierarchical physical layout with all-angle and curved polygons on an unlimited number of layers.

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Use orthogonal, 45°, all-angle, and curved drawing modes.

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View your design with the fastest rendering on the market.

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Use a command line interface for run-time automation.

L-Edit schematic driven layout (SDL) provides capabilities that enable you to: •

Read in a netlist and automatically generate parameterized cells and instance them into your design.

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Display fly lines allowing you to place your blocks to minimize routing congestion.

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Mark existing geometry as part of a specific net allowing selection and rip-up of geometry by net.

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Perform engineering change orders (ECO) and highlight differences in the netlists.

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Use netlist files in T-Spice, HSPICE, Pspice, structural Verilog, or CDL formats.

L-Edit also supports parameterized cells called T-Cells With T-Cells, you can create versatile source cells that consist of user-defined input parameters and layoutgenerating code. T-Cells extend traditional geometry cells to include the flexibility and automation of L-Edit’s user-programmable interface (UP I). L-Comp, a set of high-level composition functions, provides a simple toolkit for creating T-Cell code.

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Use L-Comp to efficiently create, place, and align ce ll instances in a design.

Navigate efficiently

L-Edit provides a built-in Design Navigator that enables you to: •

Efficiently traverse design hierarchy with top-down and bottom-up hierarchical view, non-instanced cells view, or view cells sorted by their modified date.

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Drag and drop cells into layout from library files, other design files, or the current design database.

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View layout details down to any level of the hierarchy.

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Lock and unlock cells to protect the design from any changes.

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Easily replace instances of one cell with another cell, at the current level or throughout the design.

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Maximize IP reuse or partition your design for multiple designers with L-Edit’s multiple library support (Xref Cells).

Gain complete control over editing

L-Edit gives you the flexibility and control you need to master the editing process. You can dramatically streamline the process by editing the properties of multiple objects simultaneously. With L-Edit you can instantly push down the hierarchy to any object, making it easy to edit edges, corners, and arcs. You can quickly stretch or shrink multiple edges to make room for more layouts. •

Change the current drawing layer directly from the layout using the virtual layer palette.

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Perform unlimited undo and redo operations.

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Perform all-angle rotate, flip, merge, nibble, and slice operations.

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Speed drawing and editing by snapping the cursor to object vertices, edges, midpoints, center points, and instances.

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Perform one-click horizontal or vertical object alignment, equally space objects, or tile objects horizontally, vertically, or in a 2D arra y.

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Specify a reference point for editing operations such as object rotation, flip, move, or instance placement using the base point feature.

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Work in a versatile environment

Save time and money with L-Edit’s ease-of-use benefits: •

Delivers powerful features from an affordable, customizable, easy-to manage tool.

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Offers a short learning curve.

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Enables you to import and export GDS, DXF, and CIF file formats.

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Provides multi-language menus (English, Japanese, Simplified and Traditional Chinese, German, Italian, and Russian).

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Customize and filter the Layer Palette to show only layers used in the file, current cell, or cell and its hierarchy allowing you to finish your layout faster.

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Enables you to easily cut and paste layout into your documentation flow.

Generate layout for parameterized devices

L-Edit’s DevGen feature provides layout generators for most common devices. It is easy to configure for any process to help ensure DRC correct layout. Devices include Capacitor Generator, Inductor Generator, Resistor Generator, and MOSFET Generator. For specialized devices, use L-Edit’s automatic layout to T-Cell generator to quickly complete your T-Cell library.

Create UPI macros

L-Edit’s powerful user programmable interface (UPI) allows you to create macros that automate layout manipulations, geometric synthesis, batch verification, and advanced analysis. You can further increase your productivity by mapping multiple layout functions to a single keystroke. UPI macros are written in C/C++ language and can be executed with L-Edit’s built in interpreter or compiled as a DLL.

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Speed layout with standard cell place and route

L-Edit standard cell place and route (SPR) performs place and route, pad frame generation, and pad routing. To minimize total area, a built in placement and routing optimizer automatically reduces net length and the number o f vias. L-Edit SPR includes: •

Three-layer channel routing.

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Cell clustering options.

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Specification of critical nets.

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Global signal routing for clock nets.

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Back annotation with SDF.

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EDIF input.

Further streamline verification with Interactive DRC

L-Edit Interactive DRC displays violations in real time while you edit your layout, helping you create compact, error-free layouts the first time. Interactive DRC simultaneously checks for violations between objects in the same cell and down through the cell hierarchy.

Correct layout as you goes

L-Edit Node Highlighting offers node highlighting for connectivity visualization so you can quickly find and fix LVS problems. •

Point to an object in the layout, regardless of hierarchy, and display all the geometry connected to it based on a set of connectivity rules.

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Highlight discrepancies between the schematic netlist and the extracted netlist in the layout.

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View multiple nodes in different colors.

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Track down shorts and opens.

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Improve design productivity significantly during LVS.

Verify complex designs with DRC

L-Edit DRC is a high performance, all angle, hierarchical design rule checker. Setting up rules is configurable for any technology, with a graphical interface for easy

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setup. Hierarchical error output displays your errors at the level of the hierarchy where they occur, and the error navigator opens the cell and zooms automatically to the location of the error. Your productivity improves via speedy runt imes and quick location of errors. L-Edit DRC features include: •

Support for an unlimited number of width, spacing, surround, enclose, extension, overlap, not exist, and density rules.

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High performance all-angle Boolean and Select layer generation.

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Flag off grid vertices, self-intersecting polygons, all-angle edges, and polygons with more than a specific number of vertices.

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Full chip and local region DRC.

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Import of Calibre® DRC results for browsing in L-Edit.

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Seamless integration into the layout environment using the DRC Error Navigator.

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See the DRC status (pass/fail/needed) of each cell.

Integrated Verification Error Navigator allows you to: •

Navigate instantly down the hierarchy to locate errors.

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View errors grouped by rule or by cell.

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See rule distance and actual violation distance.

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View errors in the top cell or in the cell where the error occurred.

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Mark or remove errors that have been fixed.

Extract SPICE netlists

L-Edit Extract generates a SPICE netlist from L-Edit layout for LVS comparison or for post-layout simulation with T-Spice. It extracts active and passive devices and user-definable sub circuits, with support for orthogonal, 45°, all-angle, and curved layout. To aid in verification against the schematic, L-Edit enables you to zoom or click in the layout to display a specific node or element. For increased accuracy, you can extract parasitic node capacitances, including fringing effects. You can extract the most common device parameters, including: •

MOSFET width, length, source/drain area, and perimeter.

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Areas of diodes, BJTs, MESFETs, and JFETs.

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Capacitance and resistance.

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Sub circuit extraction for functional blocks with user parameters.

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Compare layout to schematic

L-Edit layout versus schematic (LVS) accurately and efficiently compares two SPICE netlists to determine whether they contain equivalent circuit descriptions. LVS can use topological information, parametric values, and geometric values to compare netlists according to your specifications. The program quickly traces element and node mismatches back to their origins, pinpointing irresolvable nodes and devices using fragmented class reporting. LVS offers a full range of pre-processing options to optimize netlists for comparison, including: •

Merging of parallel or series devices, where options can be set independently for different device types and for specific device models.

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Elimination of shorted and disconnected (open) devices.

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Elimination of parasitic resistors and capacitors that exceed user-supplied min/max thresholds.

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Removal of user-specified device models so that the nodes spanned by their terminals can be shorted or opened.

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Omission of user-selected device parameters from the compared netlists.

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Checking for soft-connections.

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Supporting asymmetrical MOSFETs with user-defined pin swapping.

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Matching device parameter values, which are crucial for analog design.

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Specifying pre- and post-iteration matches to speed the comparison process. LVS reads netlist files in T-Spice, HSPICE, Pspice, or CDL formats, with support

for all device types and key parameters. Input netlists do not need matching formats or hierarchy to be compared. LVS supports length and width parameters, with accompanying model definitions, in capacitor I and resistor I device statements. Zip through LVS with cross-probing from SPICE and LVS results to layout or schematic and with enhanced navigation of SPICE files.

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When you purchase a new design tool, licensing options can greatly affect your total cost of ownership. L-Edit is available in node-locked and networked configurations offering you the most flexible licensing possible. With a single solution, L-Edit will work whenever and wherever meeting the design needs of your main workgroup and remote workers. If you offshore design projects, L-Edit does not have geographic restriction on its licenses, thus, lowering your total cost of ownership. 3.5

WAVEFORM EDITOR: Waveform Viewing & Analysis

The Waveform Editor (W-Edit) waveform analysis tool is a comprehensive viewer for displaying, comparing, and analyzing simulation results. W-Edit provides an intuitive multiple-window, multiple-chart interface for easy viewing of waveforms and data in highly configurable formats. 

W-Edit is dynamically linked to T-Spice and S-Edit with a run-time update feature that displays simulation results as they are being generated and allows waveform cross-probing directly in the schematic editor for faster design cycles.



Focus on and optimize your design with W-Edit’s advanced features such as automatically calculating and displaying FFT results in a variety of formats, including dB or linear magnitude, wrapped or unwrapped phase, and real or imaginary parts.

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W-Edit allows creation of new traces based on mathematical expressions of other traces for advanced analysis and easy comparison with measured data.

The advantages of W-Edit include: 

Tight integration with T-Spice, Tanner EDA’s circuit-level simulator. W-Edit can chart data generated by T-Spice directly, without modification of the output data files. W-Edit charts data dynamically as it is produced during the simulation.

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Charts are automatically configured for the type of dat a being presented.

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A data set is treated by W-Edit as a unit called a trace. Multiple traces from different output files can be viewed simultaneously, in single or multiple windows. You can copy and move traces between charts and windows. You can perform trace arithmetic or spectral analysis on existing traces to create new ones.

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You can pan back and forth and zoom in and out of chart views, including specifying the exact x- y coordinate range W-Edit displays. You can measure positions and distances between points easily and precisely with the mouse.

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You can customize properties of axes, traces, grids, charts, text, and colors. Numerical data is input to W-Edit in the form of plain or binary text files. Header and comment information supplied by T-Spice is used for automatic chart configuration. Runtime update of results is made possible by linking W-Edit to a running simulation in T-Spice.

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W-Edit saves information on chart, trace, axis, and environment settings in files with the .wdb (W-Edit Database) extension. You can load a .wdb file in conjunction with a data file to automatically apply saved formats and environment settings. The .wdb file does not contain any trace data.

CHAPTER – 4 SIMULATION ENVIRONMENT

The pre-layout and post-layout simulations of the proposed and the existing designs have been performed using Tanner EDA Tool version 13.0. All the pre layout and post layout simulations are performed different technologies like 65nm, 45nm and 32nm process technologies [61] for low-power applications. The technology files of 32nm, 45nm and 65nm for low power process technology is given in Appendix-A.

4.1

Environment The designs working best in one technology may not be best in other technologies

thus, the proposed and conventional designs are tested in different technologies to prove their technology independence. In low power applications area, power consumption, and delay introduced by the device are the main technological aspects to prefer a design over the other conventional design. In order to prove that proposed design is consuming low power and have high performance, simulations are carried out for power consumption and delay at different input and supply voltages, operating frequencies and temperatures. The designs producing low power consumption and lower delay are proposed in this work for the designing of low power portable systems. A digital device is characterized by its inputs. The complete input stream is chosen such that it is covering all possible input combinations to prove the proper functioning of the circuits. The standard values of temperature, voltage and frequency are o

o

taken to be 25 C, 0.35V and 1 MHz respectively in 65nm technology and 25 C, 0.20V and 1 MHz respectively in 45nm technology. During simulation one value is varied keeping other two constant. The input and supply voltages are always kept below the

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threshold voltage of the nMOS or pMOS transistors, whichever is less, so that they operate always in sub-threshold region.

4.2

Simulation Commands Used for Coding The description of the simulation commands used during the research work is

presented below.

.dc Performs DC transfer analysis to study the voltage or current at one set of points in a circuit as a function of the voltage or current at another set of points. Can also be used for linear or logarithmic sweeps of DC voltage or current; for sweeps of parameters other than voltage and current source values; and for Monte Carlo analysis or optimization. 

Transfer analysis is done by sweeping the source variables over specified ranges, and recording the o utput.

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Up to three parameters can be spec ified per .dc command When two or more sources are specified, the last-named source

“controls” the sweeping process. 

The specified current or voltage sources must exist—that is, be defined by i or v device statements elsewhere in the input file

DC transfer analysis results can be reported with the “.print ” dc, “.probe ” dc, and “.macro /.eom” dc commands.

Syntax .dc swinfo [[sweep] swinfo [[sweep] swinfo]]

Examples .dc isrc 0 1e-6 0.1e-6


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Current source isrc is swept from 0 to 1 microampere in 0.1microampere steps. .dc vin 0 5 0.05 VCC 4 6 0.5 Names two voltage sources: vin, to be swept from 0 to 5 volts in 0.05-volt steps, and VCC, to be

swept from 4 to 6 volts in 0.5-volt steps. The second source “controls” the sweep: VCC is initially set to 4 volts, while vin is swept over its specified range. Then VCC is incremented to 4.5 volts, and vin is again swept over its range. This process is repeated until VCC reaches the upper limit of its specified range.

.end Signifies the end of the circuit description. 

Any text in the input file after the .end command is ignored.

The .end command is optional in T-Spice but is included for compatibility with generic SPICE. Syntax

.end [comment ]

.measure Used to compute and print electrical specifications of a circuit, such as delay between signals, rise and fall times, and minimum and maximum values of a signal. Also used for optimization in conjunction with the following commands:


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“.ac”



“.dc”



“.connect ”



“.step”



“.tran ”

For parameter sweeps, T-Spice generates a separate output section plotting measurement results versus swept parameter values. A data set can be used with the error measurement syntax of .measure to compute differences between simulation output curves and corresponding external data. Trigger/Target Measurements The trigger/target format of the .measure command is used to make independent variable (time, frequency, or swept parameter) difference measurements. The trigger and target specifications determine the beginning and end, respectively, of the measurement. The value of the measurement is the difference in the independent variable value between the trigger and the target. Common examples of trigger/target measurements include delay time, rise time, fall time, and bandwidth measurements. Syntax trig outvar val=val [td=td ] {cross=cross | rise=rise | fall= fall }

+ targ outvar val=val [td=td ] {cross= cross | rise= rise | fall= fall } or trig at=at_value targ outvar val=val [td=td ] {cross= cross | rise=rise

| fall= fall }


at_value

34

Specifies an explicit independent variable value

for the event. Outvar

Specifies an output signal on which the trigger or target measurement is performed. This can be any output plot item that is legal on a .print command for the appropriate analysis type. For .measure ac commands, .print noise plot items

are allowed. Outvar may be an output expression enclosed in single quotes. Val

Specifies the value of outvar at which the trigger or target counter for cross, rise, or fall is incremented.

Td

Specifies a time delay before the measurement is enabled and crossings, rises, and falls are counted. Default: 0.

Cross

Indicates which occurrence of the trigger or target crossing is to be used for the measurement. A crossing occurs when the trigger or target outvar takes on the value val . The special syntax cross=last indicates that the last crossing is to be

used. Rise

Indicates which occurrence of the trigger or target rise crossing is to be used for the measurement. A rise crossing occurs when the trigger or target outvar takes on the value val while increasing. The special syntax rise=last indicates that the last rise crossing is to be used.

Fall

Indicates which occurrence of the trigger or target fall crossing is to be used for the


35

measurement. A fall crossing occurs when the trigger or target outvar takes on the value val while decreasing. The special syntax fall=last indicates that the last fall crossing is to be used.

Note: For a particular trigger or target, only one of cross, rise, or fall

may be specified. Trigger/target measurement output reports the independent variable value difference between the trigger and the target, as well as the independent variable values at the trigger and target. The measurement result may be negative if the target independent variable value is less than the trigger independent variable value. Examples .measure tran delaytime trig v(1) val=2.5 fall=3 targ v(2) val=2.5 rise=3 measures the time delay from the third falling edge of signal v(1) to the third rising edge of signal v(2) . The measurement begins when v(1) falls through 2.5V for the third time, and ends when v(2) rises through 2.5V for the third time.

.measure tran risetime trig v(1) val=0.5 rise=1

targ v(1) val=4.5

rise=1 measures the first rise time of the vo ltage at node 1.

.model Specifies device model parameters to be used by one or more


36

devices. Syntax .model

modelname

type

[level= L][ parameter =value

[ parameter =value [...]]] modelname

Model name.

type

Device type (see below).

L

Model level, required for device models with

multiple levels. Parameter

The parameter list is predefined for each

standard device model.

Type is one of the following: c

Capacitor

cpl

Coupled transmission line.

Csw

Current-controlled switch element.

D

P-N diode.

Npn

NPN-type BJT.

Pnp

PNP-type BJT.

Njf

N-type JFET.

Pjf

P-type JFET.

Nmf

N-type MESFET.

Opt

Controls the optimization algorithm.

Pmf

P-type MESFET.

Nmos

N-type MOSFET.


37

P-type MOSFET.

Pmos

Two-terminal resistor (or three-terminal resistor

R

if a capacitance is specified). Voltage-controlled switch element.

Sw

Examples .model nmos nmos + Level=2 Ld=0.0u Tox=225.00E-10 + Nsub=1.066EV+16 Gamma=.639243

Vto=0.622490 Phi=0.31

Kp=6.326640E-05

Uo=1215.74

+

+

Uexp=4.612355E-2

Ucrit=1746677 Delta=0.0 + Vmax=177269 Xj=.9u Lambda=0.0 + Nfs=4.55168E+12 Neff=4.68830 Nss=3.00E+10 + Tpg=1.000 Rsh=60 Cgso=2.89E-10

+

Cgdo=2.89E-10

Cj=3.27E-04

Mj=1.067

+

Cjsw=1.74E-10 Mjsw=0.195 Specifies the parameters for an n-type MOSFET model called nmos.

.power Computes power dissipation in conjunction with transient analysis. 

If the “.tran ” command is missing from the input file, the .power command is ignored.



The average power consumption, the instantaneous maximum power, and the instantaneous minimum power (in watts) and the times of maximum and minimum power consumption (in seconds) are reported at the end of the transient simulation.



The instantaneous power P (t ) dissipated by a voltage source at

time t is the current through the source multiplied by the voltage drop across the source. The average power P for a time interval (t1,t2) is computed by using the trapezoidal rule approximation


38

to evaluate the integral 

Multiple .power commands can be used in a single simulation.

Power results can also be reported with the “.print ” tran command. Syntax .power source [ A [ Z ]]

Voltage

source

source

whose

power

consumption is to be computed. Time at which power recording begins. (Unit:

A

seconds. Default: simulation start time.) Z

Time at which power recording ends. (Unit: seconds. Default:

simulation end time.) Examples .power vtest 3e-7 Computes the power dissipated by voltage source vtest between the given time (0.3 microseconds) and the end of the simulation. It might produce the following sample output:

Power Results vtest from time 0 to 3e-007 Average power consumed -> 1.249948e-002 watts Max power 2.490143e-002 at time 9.76e-006 Min power 2.282279e-030 at time 1e-005


39

.print Reports simulation results. 

If an output filename is not specified, the output file specified in the Start Simulation dialog is used. (If

that file cannot be

opened, the results are written to the Simulation Window.) 

Multiple .print commands can be used to direct different types of output to separate files.



Transient analysis results are printed in columns, with time values in the first column.



AC and noise analysis results are printed in columns, with frequency values in the first co lumn.



DC transfer analysis results are printed in columns, with sweep values from the first source listed on the “.dc” command in the first column.



DC operating point analysis results are printed line by line, each argument to a line.



Expressions can be printed by themselves, with or without reference to physical quantities at specific nodes.



Nodes and devices within subcircuits can be accessed with hierarchical notation in the form xinstance.xinstance.node.



.print commands inside subcircuit definition blocks are

replicated for each instance. 

If no arguments are given, all node voltages and source currents are printed. If neither mode nor arguments are given, .print applies to all analysis types. If arguments are given, a mode


40

must also be specified. 

Wildcards may be entered as part of the .print command node names, devices names, terminal names, or terminal numbers. Wildcards are expanded to match any available elements which match the name specification.

Device State print statements are a means of obtaining very detailed information about devices and device internal states. Data such as the current, charge, capacitance, and voltage values can be listed, as well as certain model evaluation variable (threshold voltage, beta, et c.). Syntax .print [mode ] [“ filename”] [arguments ]

Analysis mode (see below).

mode Filename

Output filename. Must be enclosed by

double quotes. Arguments

Information to be printed (see below). Arguments

may

include

valid

expressions involving other arguments or global parameters. Arguments take one or more of a number of values, depending on mode. When no arguments are given, all node voltages and source currents are printed.

Mode is one of the following: tran Dc

Print results from transient analysis. Print results from DC transfer analysis


41

and DC operating point analysis. Print results from AC analysis.

Ac Noise

Print results from noise analysis.

Examples .print tran in out i1(r2) id(M2) Prints transient analysis results: the voltages at nodes in and out and the currents into terminal 1 of device r2 and the drain terminal of device M2.

.print v(n*) Prints the voltages for all nodes whose name begins with the letter ’n’.

. subckt Defines a hierarchical set of devices and nodes to be used repeatedly in a higher-level circuit. 

Subcircuits are replicated by means of the instance (x) statement.



When invocations of the following commands appear within subcircuit definitions and refer to nodes inside the subcircuit, the commands are executed for each instance of the node: “.acmodel ” , “.hdl”, “.macro /.eom”, “.nodeset”, “.noise”, “.print ”, and “.probe”, and “.tf ”.



Node and device names have local scope in subcircuits unless global node names (defined elsewhere with the “.global”


42

command are used. Subcircuit blocks cannot be nested: after one .subckt command, the “.ends” command must appear before another .subckt command can be

used. Syntax .subckt name node1 [node2 ...] [ parameter = X ...]

subcircuit .ends

Name of subcircuit.

name Node1 node2

Nodes

used

as

“external”

connections to the subcircuit. Parameter

Parameter(s),

with

default

value(s) assigned. X can be a number

or

an

expression.

Subcircuit parameters have local scope. Parameters can be written in any order in both definition and instances.

Parameter

values

specified in the definition are used as defaults when not specified in instances. Within the definition, parameter values are referenced (in

place

of

numbers)

by

enclosing their names in single quotes.

Alternatively,

the

“.param” command may be used

within the definition, with the


43

same results. Parameters created outside the definition with the “.param” command may be used

inside

the

definition,

but

an

assignment made with the .subckt command to an externally defined parameter always overrides its external value. Subcircuit

Subcircuit

definition

(may

be

multiple lines). Examples .subckt inv in out Vdd length=1.25u nwidth=2u pwidth=3u mt1 out in GND GND nmos l=’length’ w=’nwidth’ mt2 out in Vdd Vdd pmos l=’length’ w=’pwidth’ c2 out GND 800f .ends inv

This subcircuit could be instanced as follows: xinv1 a1 a2 Vdd inv nwidth=4u pwidth=6u

. temp Specifies the temperatures at which the circuit is to be simulated. 

Changing the temperature affects the behavior of diode, resistor, BJT, JFET, MESFET, and MOSFET models. It may also affect the behavior of user-defined external mo dels.

The .temp command has no effect on external tables, which should


44

be regenerated to reflect the new temperature. Syntax .temp temperature [temperature [temperature [...]]]

temperature

Temperature. (Unit: °C.

Default: 25.)

Using .TEMP and .STEP displays voltage vs. voltage plots with different temperatures displaying as different traces. Examples .DC vin 0 5 0.1 .TEMP 25 30 35 40 50 To plot voltage vs. temperature, use the following so that the first sweep variable in the DC analysis will become the X axis:

.DC temp 25 40 5 VIN 0 5 0.1

. tf Computes and reports the value of the small-signal DC transfer function between the specified output and input, and the corresponding input and output resistances, at the DC operating point. 

The .tf command automatically performs (but does not report the results from) a DC operating point calculation.



Results are reported under the heading SMALL-SIGNAL


45

TRANSFER FUNCTION (to the specified output file or in the

Simulation Window). The transfer function value corresponds to a voltage (V ⁄ V) or current (I ⁄ I) gain, a transconductance (I ⁄ V), or a transresistance (V ⁄ I). Syntax .tf arguments source

arguments

Any arguments appropriate for the “.print ” dc command.

Source

Voltage or current input source.

Examples .tf i(mb1,out1) ii1 Computes transfer function results between node out1 of device mb1 and current source i1.

. tran Performs large-signal time-domain (transient) analysis of the circuit to determine its response to initial conditions and time-dependent stimuli. 

The time step is adaptively varied throughout the simulation to ensure accuracy.

Results for nodes selected by the .print tran , .probe tran , and .measure tran commands will be output for every time step, unless

otherwise specified by the .options prtdel command. For additional information on these commands, see “.print ”, “.probe ”, “.macro


46

/.eom” and “.options”.

Syntax mode] S L [start= A] A] [UIC] [sweep sweep] sweep] .tran[/mode]

mode

Analysis

mode

(see

below).

This

parameter must immediately follow the keyword .tran and be preceded by a slash (/). Maximum time step allowed. By default,

S

the time step is dynamically adapted to resolve the output values. (Unit: seconds.) L

Total simulation time. (Unit: seconds.) Output start time. Execution of the .print

A

tran command will not start until this

time. (Unit: seconds. Default: 0.) UIC

Instructs

T-Spice

to

skip

the

DC

opera operati ting ng point point analy analysi siss for dete determ rmiining ning the time=0 circuit circuit state. Instead, Instead, only only the initial conditions specified using .ic commands are used to set the time=0 voltages.

Voltages which cannot be

determined using .ic commands are set to zero. Sweep

For a description of the syntax for

this field, see “.step”.

mode takes one of the following values:


47

Performs

op

calculation determine

a

DC

operating

before initial

point

simulation steady-state

to node

voltages. The commands “.nodeset ” or “.hdl” can be used to impose initial

conditions. Powerup

Performs a “powerup” simulation. All nodes are at the same potential at time zero, and the voltage sources are ramped gradually to their final values.

Preview

Steps through the input signals without simulating the circuit. Input waveforms will be reported as specified by the “.print ” tran command.

If mode is not specified, T-Spice first performs a DC operating point analy analysis sis,, withou withoutt printi printing ng the DC operati operating ng point point analy analysis sis results. results. Sweep indicates the beginning of the next nested sweep variable

specification. The sweep keyword can be omitted if the previous sweep is not of the list or poi type or if one of the keywords lin, dec, oct, list, poi, temp, param, source, or modparam follows immediately.

Using the sweep option with .tran or “.ac” causes that that analysi analysiss to be performed for all parameter values of the sweep. It is equivalent to “.step ”, except that it applies only to one analysis command, while .step applies to all analysis commands in the input file. If sweep is

specified on an analysis command and .step is present, the sweep sweep is nested inside the .step sweep. The sweep parameter may be used to specify a parametric sweep, Monte Carlo analysis, or optimization.


48

Examples .tran 0.5n 100n Defines a transient simulation lasting 100 nanoseconds, using time steps of at most 0.5 nanosecond. By default, a DC operating point calculation will first be performed to define a starting condition. .tran/preview 4n 4000n The input waveforms are reported for 4000 nanoseconds; the rest of the circuit is ignored. .tran 1ns 100ns Specifies a maximum time step of 1 nanosecond and a total simulation time of 100 nanoseconds. .tran/powerup 1ns 100 ns Specifies a powerup simulation with no operating o perating point computation. .tran 1ns 100 ns start=50ns Produces output starting at time 50 nanoseconds. .tran 1n 100n sweep temp list 0 27 100 150 -50 Performs five transient analysis runs, one for each temperature listed. The keyword keyword temp specif specifie iess the sweep sweep variable, variable, as defi define ned d in in “.step”. .tran 1n 400n sweep temp -50 150 50 This performs five transient transient analyses at temperatures temperatures -50, 0, 50, 100, and 150 degrees Celsius. .tran 1n 200n sweep temp list 0 25 75 150 This example performs four transient analysis runs at temperatures 0, 25, 75, and 150 degrees Celsius.


49

MOSFET(m) A transistor with four terminals: drain, gate, source, and bulk. (MOSFET stands for metal oxide semiconductor field effect transistor .) Syntax mname drain gate source bulk model [l= L] [w=W ] [ad= Ad ]

[pd= Pd ] [ as= As] [ps= Ps]

name

MOSFET name.

drain

Drain terminal.

Gate

Gate terminal.

Source

Source terminal.

Bulk Model

Bulk terminal. MOSFET model name. The model is declared elsewhere in the input file in the form: .model name nmos | pmos level=1 | 2 | 3 | 4 | 5 | 9|13|20|28|30|31|40|47

|

49

|52|100… [ parameters] L

Channel length. (Unit: meters. Default: set by the .options defl command.)

W

Channel width. (Unit: meters. Default: set by the .options


50

defw command.)

Drain

Ad

area.

(Unit:

square

meters) Drain

Pd

perimeter.

(Unit:

meters) Source area. (Unit: square

As

meters.) Source

Ps

perimeter.

(Unit:

meters) Examples m12 n1 n2 GND GND ndep l=10u w=5u ad=100p as=100p pd=40u ps=40u

Voltage Source (V) A two-terminal ideal voltage supp ly. Exponential, pulse, piecewise linear, frequency-modulated, sinusoidal, and customizable (vectorized) waveforms are available. Voltage sources whose waveform is described using an expression can be created using the e-element with an expression and the time() function. Syntax vname node1 node2 [[DC] V ] [AC M [ P ]] [ waveform]

name

Voltage source


51

name. Positive terminal

node1

Negative

node2

terminal. DC

V

level

between

and

node1

node2.

(Unit: volts. Default: 0.) Waveform

waveform

identifier

and parameters AC magnitude. (Unit:

M

volts.) AC

P

phase.

(Unit:

degrees. Default: 0.)

DC,

AC,

and

transient

values

can

be

specified

independently and in any order. Waveform is one of the following:

Exponential Waveform exp (Vi Vp [ Dr [Tr [ Df [Tf ]]]])

Vi

Initial voltage. (Unit:

volts.) Vp

volts.)

Peak

voltage.

(Unit:


Dr

52

Rise time delay. (Unit:

seconds. Default: 0.) Tr

Rise

time

constant.

(Unit: seconds. Default: 0.) Df

Fall time delay. (Unit:

seconds. Default: 0.) Tf

Fall

time

constant.

(Unit: seconds. Default: 0.)

Pulse Waveform pulse (Vi Vp [ D [Tr [Tf [ Pw [ Pp]]]]]) [ ROUND= RND]

Vi

Initial voltage. (Unit:

volts.) Vp

Peak

voltage.

(Unit:

Initial

delay.

(Unit:

Rise

time.

(Unit:

volts.) D

seconds. Default: 0.) Tr

seconds. Default: time step from .tran.) Tf

Fall

time.

(Unit:

seconds. Default: time step from .tran.) Pw

Pulse

width.

(Unit:

seconds. Default: stop time from .tran.)


53

Pulse

Pp

period.

(Unit:

seconds. Default: stop time from .tran.) RND

Rounding half-interval. A corner at time T is replaced by a smoothly differentiable polynomial

in

the

interval

(T –

RND,T + RND).

The

maximum RND is half the

distance

nearest

to

the

neighboring

corner. ( Default: 0—no rounding.)

Note that rise time is not necessarily a ’rise’ time, but is the time to go from the initial voltage to the pulse voltage, regardless of whether it’s smaller or larger.

Vectorized Waveform bit| bus ({ pattern} [on= A] [off= Z ] [delay= D] [pw= P ]

[rt= R] [ft= F ] [lt= L] [ht= H ]) [ROUND= RND]

pattern

An

expression

consisting of one or more string or string-


54

multiplier combinations. A

On voltage (Unit: volts.

Default: 0.001.) Z

Off

voltage

(Unit:

time.

(Unit:

volts. Default: 0.) D

Delay

seconds. Default: 0.) Pulse width: P = R +

P

A = F + T Z , where T A T

is the time during a pulse where the voltage Z is “on” (V = A) and T

is the time during a pulse where the voltage is “off” (V = Z ). (Unit: seconds. Default: 10 × 10– 9.) R

Rise

time.

(Unit:

Fall

time.

(Unit:

seconds. Default: 1 × 10–9.) F

seconds. Default: 1 × 10–9.) L

Z , Low time: L = F + T Z is the time where T

during a pulse where the voltage is “off” (V = Z ).

(Unit:

seconds.

Default: 10 × 10–9.)


55

High time: H = R + T A,

H

where T A is the time during a pulse where the voltage is “on” (V = A).

(Unit:

seconds.

Default: 10 × 10–9.) RND

Rounding half-interval. A corner at time T is

replaced by a smoothly differentiable polynomial in the RND, T + RND). The maximum RND is half the interval (T –

distance to the nearest neighboring corner. ( Default: 0—no rounding.) Examples v2 n2 GND bit ({01010 11011} on=5.0 off=0.0 pw=50n rt=10n ft=30n) v2 generates a bit input. Enclosed in braces { } are two

binary-valued five-bit patterns specifying the waveform. The two patterns alternate in time. The on voltage value is 5.0 volts; the off voltage value is zero. The pulse width (pw), 50 nanoseconds, is the time the wave is either (ramping up and) on, or (dropping down and) off. The rise time ( rt), 10 nanoseconds, is the time given for the wave to ramp from off to on; and the fall time ( ft), 30 nanoseconds, the time given for the wave to drop from on to off.

V3 n3 GND bit ({5(01010 5(1))} pw=10n on=5.0 o ff=0.0)

v3 generates a repeating bit input. Two distinct patterns

are given again, but now multiplier factors are included. The


56

wave consists of two alternating patterns: the first pattern contains five bits; the second is a single bit. The five-bit pattern is followed by five successive repetitions of the single-bit pattern, and this combination is repeated five times. The pulse width and on and off voltages are again specified, but the rise and fall times take default values.

CHAPTER – 5 INTERCONNECT REPEATER DESIGN All electronic system, at any level, is composed of functional blocks (transistors, gates, sub-circuits, IPs, cores, processors, boards etc) interconnected with each other, that is, capable of transmitting information from one part to another. This information is in the form of a voltage or a current value. Ideally, the communication between interconnected blocks should be instantaneous and distortion free. Under these conditions, the system is completely described by its building blocks and the way they are connected. However, this ideal picture cannot be achieved in practice. The reason is that physically, there is always a propagation time for transmitting the information from one point to another. If the signals change very slowly compared to this propagation time, the transmission may be considered instantaneous and the ideal picture is valid. If, on the other hand, the signals vary rapidly compared to the propagation time, several effects may be observed: 1. Signal Delay – This fact must be taken into account when designing the system to ensure that all the blocks receive the information at the expected time. 2. Reflection coming from the end of the interconnection and interfering with the signal sent. 3. Interference between nearby interconnections. All these non-ideal effects may influence the behavior of the system and they present limitation on performance of the system. 5.1 The problem with interconnections

The evolution of electronic technology, as dictated by Moore’s Law, is towards denser, more complex and faster systems. All three trends imply a larger interconnection effect, once considered only from the functional point of view. The physical parameters that characterize an interconnection are resistance, capacitance and inductance. The interconnection response to a certain voltage and current excitation can be

INTERCONNECT REPEATER DESIGN

58

derived from the relative values of those parameters. Roughly speaking, delay is mostly dependent on R and C (although L is also important for high frequency signals). On the other hand, crosstalk interference depends on mutual C and L between close lines. Let us analyze the influence of technology trends on parameters and their effect on signal integrity. 5.1.1 Increase in integration

As the number of devices per unit area increases, the density of interconnection also increases. This is creating reduced cross sectional dimension and greater number of vertical layers. The reduced cross sectional dimension leads to more tightly coupled interconnection leading to higher unwanted crosstalk and increase in R, thus, produces higher delay and signal distortion. 5.1.2 Increase in complexity

Increase in complexity implies an increase in the length of global interconnections along with the increase of conducting layers to interconnect high number of devices. 5.1.3 Signal frequency

As a result of technology advancement, higher frequency components are transmitted through interconnections. Higher frequency content means two things: firstly, circuit parameters L and C will have great influence on the line impedance and secondly, reflections of the signals are higher. The performance of electronic systems is more critically dependent on the effects introduced by interconnections. It is therefore, very important to have good models of the interconnection at the design phase to prevent design-manufacturing iterations and to reduce the time-to-market. Further, in this research we have used the RLGC model of interconnections. In fabrication of a chip power-delay product act as a figure of merit and intention is always to reduce it. The transistor count is increasing in a chip with the technology advancement, which in turn increases the complexity of interconnects, leading to increased length of interconnects. The long interconnections lead to prohibitively high propagation delays. Buffers are required to drive high capacitive loads in order to keep pace with the required speed and single buffer is not sufficient, hence number of buffers are required to be inserted at regular intervals of distance in the interconnect for the


59

proper detection and reconstruction of the signal, which are termed as repeaters (inverters). The optimum number of inverters required to be inserted in the mid for the design of active interconnection, driven by minimum size inverters is presented in Eq. 5.1 –

 �  

(5.1)

=

.

Where,

Ri = Total resistance of the interconnect line C i = Total capacitance of the interconnect line Rr = Output resistance of the inverter C r = Input capacitance of the inverter Thus the designing of the repeater plays a significant role in the design and

fabrication of the chip. 5.2 Design of the Repeater

The conventional repeater is used as a repeater circuit, after every fixed length of interconnect, to reproduce the original signal. In earlier Interconnect designs, conventional repeater was used.

3.50x10 3.00x10

-16

-16

2.50x10

PowerDelay Product

2.00x10

-16

-16

1.50x10 1.00x10

-16

-16

-17

5.00 x10

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

Substrate Voltage

(a)

(b)

Figure 5.1 (a) Schematic of inverter with pMOS bo dy at ground, (b) variation of powerdelay product with nMOS substrate voltage keeping pMOS body at ground.


60

Table I. Delay, power and power-delay product variation with nMOS body bias VBB VBB 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.37

Delay -7 5.41x10 -7 5.42x10 5.42x10-7 5.43x10-7 5.43x10-7 5.44x10-7 5.45x10-7 5.46x10-7 5.47x10-7

Power -10 2.76x10 -10 2.84x10 2.74x10-10 3.05x10-10 3.40x10-10 3.75x10-10 4.45x10-10 5.33x10-10 5.76x10-10

PDP -16 1.49x10 -16 1.54x10 1.49x10-16 1.66x10-16 2.04x10-16 2.04x10-16 2.42x10-16 2.91x10-16 3.15x10-16

The observation has to be carried out to find the suitable body biasing voltage for the nMOS in inverter circuit. Thus, the bulk of the pMOS is connected to the ground and bulk o f the nMOS is connected to the DC voltage supply and applied biasing voltage is varied to observe the effect on the average power consumption and delay of the inverter circuit. Since the input and supply voltage should be less than the threshold voltage, the supply and input voltages are fixed at 0.37V (according to 180nm technology) and frequency of the applied signal is taken 1 kHz. The schematic diagram of the buffer is demonstrated in figure 5.1(a). Figure 5.1(b) shows the variation of power-delay product with biasing voltage VBB of nMOS. The delay is found almost constant but the average power consumption is increasing with the increase of VBB. As the nMOS body biasing voltage is increased, the power-delay product also increases and it can be inferred from the table I in which the power-delay product for various nMOS body bias keeping the pMOS body at V DD is presented. Thus, choosing the repeater design having both nMOS and pMOS bodies at zero potential will give better power-delay product.


Figure 5.2 Conventional repeater circuit with interconnect.

Figure 5.3 LVSB repeater circuit with interconnect.

61


62

Figure 5.4 STGB bias repeater circuit with interconnect. Figure 5.2 shows the conventional repeater with interconnect and output load capacitor. In the conventional repeater, the substrate bias voltage is zero for both the nMOS and pMOS. Conventional body biasing schemes apply a constant body-to-source voltage to all devices, independent of V DD. As a result, they incur some area overhead for bias generators and body bias grid routing. The LVSB buffer with interconnect having capacitive load is shown in figure 5.3. In the LVSB bias buffer, substrate bias voltage for the nMOS and pMOS is set to V DD, thus the threshold voltage of the pMOS changes with applied voltage. As a result, all devices receive an amount of forward body bias equal to V DD. Area overhead for LVSB bias technique, is negligible, similar to NBB designs. LVSB bias buffer technique can be used dynamically where the body connections remain swapped during active mode and are reversed to the conventional NBB configuration during standby. The grounded body bias repeater with interconnect having capacitive load is presented in figure 5.4. In the STGB bias repeater substrate bias voltage for the nMOS is set to zero but for the pMOS it is not at zero value, thus the threshold voltage of the pMOS changes with applied voltage, while in case of the conventional repeate r threshold


63

voltage of pMOS and nMOS are not depending upon the change of the applied input voltage. Because of this change in threshold voltage of the repeater in STGB techniques, the frequency range of operation is increased, which produces a various advantages over the conventional and LVSB repeaters. 5.3 Simulation and Analysis

Repeater circuits are simulated by taking various lengths of interconnects in 180nm technology. During simulation, the input voltage and the power supply voltage V DD, both are kept below threshold voltage, V t, so that the device always operates in subthreshold region. Resistance ( Rint ), Capacitance (C int ) and inductance ( Lint ) are the parameters of the interconnect line, chosen according to the technology. The output or load capacitance is chosen to be 50fF. The formula used for calculating the parameters of interconnect [61] are as follows R

int



C int





. l

------------ [5.1]

W int .T

(  ox .l ).[(

W int H

)

 C 1 

C 2



C

3

 C 4 ]

------------ [5.2]

Where,

 W  C 1  2 . 24  int   H 

0 . 0275

  1  0 . 85  

S     0 . 62  H  

   

------------ [5.3]

C 2

  0 . 065 S   T   T   S  1 . 62 S  T     0 .32 log   0 .15 e  0 . 12 e   H  S   

C 3



T S

 T   1 . 31    H 

0 . 073

 S   1 . 38    H 

 2 . 22

------------ [5.4]

------------ [5.5]

and, W int   S   1 . 12  C 4  0 . 4 log  1  5 . 46  S   H  

 0 . 81

------------ [5.6]


L int



0 . 2 l  L s







2 . 0 M sg



L g 2 .0



64

M gg  2 .0

 

------------ [5.7]

Where,

  2 l  W g  T       0 .5  0 .22 L s  log   W g  T   l  

------------ [5.8]

 2l  d sg      M sg log  d sg  1 .0 l  

------------ [5.9]

M gg

L g



log

 2 l     d gg   1 . 0   

d gg l

 2l  W  T   0 .5  0.22 int  log  l  W int  T 

------------ [5.10]

------------ [5.11]

Where, Wg is the width of the ground shield, d sg is the distance between the center of the signal line and the ground shield, and dgg is the distance between the center of the two ground shield. l

=

Length of the interconnect



=

Resistivity

T

=

Thickness of interconnect

W int

=

Width of interconnect

H

=

Height of metal layer from the substrate

S

=

Spacing between the signal and ground line


Figure 5.5 Conventional repeater output for 10mm interconnect at 50 kHz.

Figure 5.6 LVSB bias buffer output for 10mm interconnects at 50 kHz.

65


66

Figure 5.7 STGB bias repeater output for 10mm interconnects at 50 kHz.

Table II. Delay in Conventional and STGB bias repeater at different frequencies for various interconnect lengths Delay (in µs) frequency Conventional Repeater

LVSB Bias Repeater

STGB Bias Repeater

(kHz)

10mm

5mm

1mm

10mm

5mm

1mm

10mm

5mm

1mm

0.5

1014

1008

1001

1002

1001

1000

1001

1001

1000

1

514.3

507.6

500.8

501.5

500.9

500.3

500.8

500.8

500.2

2

264.3

257.6

250.8

251.6

250.9

250.3

250.8

250.8

250.2

5

114.3

107.6

100.8

101.6

100.9

100.3

100.8

100.8

100.2

1

64.3

57.6

50.8

51.59

50.85

50.25

50.8

50.8

50.2

20

39.2

32.6

25.8

26.59

25.85

25.25

25.8

25.8

25.2

0

N/A

17.6

10.8

1.159

10.85

10.25

10.8

10.8

10.22

100

N/A

N/A

5.79

6.586

5.855

5.249

5.79

5.79

5.22

200

N/A

N/A

3.29

4.087

3.351

2.749

3.29

3.29

2.72


67

Figure 5.5, 5.6 and 5.7 shows the conventional, LVSB and STGB bias repeater output for 10mm interconnect at 50 kHz. From the figures, it can be well understood that the performance of LVSB and STGB bias repeater are better than that of the conventional repeater for medium frequency operation. Simulation results reveal that the STGB bias repeater even shows good performance in medium frequency range. Table II shows 50% delay produced in conventional, LVSB and STGB bias repeater circuits for various lengths of interconnect at various frequencies. Delay produced by the conventional repeater for 10mm interconnect at 50 kHz, 100 kHz and 200 kHz and for 5mm interconnects at 100 kHz and 200 kHz is not calculated as the conventional repeater output is below the 50% reference level. From the table it is clear that the delay produced by the STGB bias repeater is less than the conventional and LVSB repeater for 10mm interconnects. For 5mm and 1mm interconnect also the delay produced by the STGB bias repeater is less than that of conventional and LVSB repeater in the frequency range of 0.5 kHz to 200 kHz. It is also found that the delay is very less affected by the increase of the length of interconnect in STGB bias repeater. 1.4×10 1.2×10

Average

1.0×10 8.0×10

Power Dissipation

6.0×10 4.0×10 2.0×10

-

at 10mm -

at 5mm -

at 1mm -

-

0

0.5

1

2

5

10

Frequency (in kHz)

Figure 5.8 Average power consumption in STGB bias repeater for different lengths of interconnects at various frequencies.


68

Table III. Average power consumption, delay and power-delay product in Conventional and LVSB bias buffer for 10mm interconnect lengths (130nm technology) Conventional Buffe Frequency

Av. Power Consumption

LVSB Bias

PowerDelay Product

Delay


-

-

6.06×10

-

-

1.08×10

-

-

2.09×10

-

-

4.97×10

-

-

9.76×10

-

-

1.99×10

-

-

4.97×10

8.33×10 5.22×10

-

-

9.41×10

not found

1.22×10

0.5 kHz

5.69×10

1.00×10 5.70×10

1 kHz

1.05×10

5.03×10 5.28×10

2 kHz

2.06×10

2.53×10 5.21×10

5 kHz

4.98×10

1.03×10 5.14×10

10 kHz

9.84×10

5.33×10 5.25×10

20 kHz

1.99×10

2.83×10 5.64×10

50 kHz

4.82×10

1.33×10 6.43×10

100 kHz

6.27×10

200 kHz

7.04×10

not found

uffer

PowerDelay Product

Delay

-

1.00×10

-

6.07×10

-

5.02×10

-

2.52×10

-

1.02×10

-

5.15×10

-

2.65×10

-

1.15×10

-

6.50×10

-

3.99×10

-

-

5.39×10

-

5.26×10

-

5.04×10

-

5.03×10

-

5.28×10

-

5.72×10

-

5.11×10

-

4.89×10

-

-

-

-

-

-

-

-

Figure 5.8 shows the average power consumption in STGB bias buffer for different lengths of interconnects at various frequencies at 180nm technology. The average power consumption increases non-linearly but for 10mm interconnects; it increases rapidly with increasing frequency. This figure shows obvious results that the average power consumption increases with increasing the length of interconnect. Table III shows the performance comparison of conventional and LVSB bias buffer in 130nm technology. It can be inferred that the power-delay product of LVSB buffer is more up to frequencies 2 kHz, but becomes less for higher frequencies. The value of the output signal produced by the conventional buffer becomes less than the 50% voltage reference level for frequencies more than 200 kHz. Thus, the delay value cannot be calculated and the power-delay product unidentified.


69

5.4 LVSB Bias Repeater and Conventional Repeater

The Conventional buffer and LVSB bias buffer are simulated by taking various lengths of interconnect 180nm and 130nm technology [60] and V DD is kept below the threshold voltage to operate in sub-threshold region. Table IV. Interconnect parameters in 180nm and 1 30nm technology. 180nm technolo 130nm technolo L=10mm L=5mm L=1mmm L=10m L=5mm L=1mm 220 10 22 305.55 152.77 30.555 Resistance (Ohm) 19.37 9.685 1.937 19.63 9.82 1.963 Inductance (nH) 797.04 398.52 79.704 861.2 430.6 86. 2 Capacitance (fF)

The different parameters of the interconnect line is derived from the Eq . 5.1-5.3 as discussed earlier and presented in the table IV. It can be observed that the values of resistance, capacitance and inductance are increasing with the length of the interconnection and also with the technology [42]. Table V. Power-delay product in Conventional and LVSB bias buffer at different frequencies for 10mm interconnect lengths (180nm techno logy)

Frequency

Conventional Buffer

0.5 kHz

8.44×10

1 kHz

7.23×10

2 kHz

6.78×10

5 kHz

6.87×10

10 kHz

7.56×10

20 kHz

LVSB Bias Buffer

-

4.71×10

-

-

2.63×10

-

1.62×10

-

9.90×10

-

7.87×10

7.61×10

-

7.20×10

50 kHz

not found

7.13×10-

100 kHz

not found

7.72×10

200 kHz

not found

7.04×10-

-

-


70

Power-delay product of LVSB bias buffer is more t han the conventional buffer for frequencies less than 20 kHz, but improves for higher frequencies as depicted in table V. Since the delay values for frequencies more than 50 kHz were not calibrated by the simulation tool (as voltage reference levels are below 50%), therefore, the respective power-delay product is not even calculated. Table VI. Average power consumption, de lay and power-delay product in Conventional and LVSB bias buffer for 10mm interconnect lengths (130nm technology)

Conventional Buffer Frequency


0.5 kHz

5.69×10

1 kHz

LVSB Bias Buffer

Power-Delay Av. Power Product Consumption

Delay

-11

1.00×10

-3

5.70×10

1.05×10

-10

2 kHz

2.06×10-10

5 kHz

4.98×10

5.03×10

-4

2.53×10-4

10 kHz

9.84×10

20 kHz

1.99×10-09

50 kHz

4.82×10

100 kHz

6.27×10

200 kHz

7.04×10

-10

1.03×10

-10

5.33×10

-14

6.06×10

5.28×10

-14

5.21×10-14

-4

5.14×10

-5

5.25×10

2.83×10-5

-09

1.33×10

-09 -09

1.00×10

1.08×10

-10

2.09×10-10 4.97×10

-14

-5

6.43×10

8.33×10

-6

not found

Delay

-11

-14

5.64×10-14

PowerDelay Product -3

6.07×10

5.02×10

-4

5.39×10

2.52×10-4

5.26×10-14

-10

1.02×10

9.76×10

-10

1.99×10-09

-14

4.97×10

5.22×10

-14

9.41×10

not found

1.22×10

-14 -14

-4

5.04×10

5.15×10

-5

5.03×10

2.65×10-5

5.28×10-14

-09

1.15×10

-09

6.50×10

-08

3.99×10

-14 -14

-5

5.72×10

-14

-6

5.11×10

-6

4.89×10

-14 -14

Table VI shows the performance comparison of Conventional and LVSB bias buffer in 130nm technology. It is depicted that the power-delay product of LVSB buffer is higher up to frequency 2 kHz, but becomes less for higher frequencies. Even at 200 kHz and more than this frequency the value of the output signal produced by the conventional buffer becomes less than the 50% of the reference value, thus the delay value and hence the power-delay product cannot be calculated.


71

For low frequency operation conventional buffer is found to be still better in terms of average power consumption but in high frequency operation, performance of the LVSB bias buffer is better. It is also found that delay introduced by LVSB bias buffer is less at various frequencies. Thus in a nutshell LVSB bias buffer is a better choice in subthreshold region for low level high frequency signals and thus act as a good option for the designing of portable applications. So further we will compare the LVSB buffer with the proposed STGB buffer. 5.5 Proposed STGB Bias Repeater and Conventional Repeater

Table VII shows delay (between 50% of the input and output voltage levels) produced in conventional repeater and STGB bias repeater circuit for different lengths of interconnects at various frequencies. Delay produced by the conventional repeater for 10mm interconnect at 50 kHz, 100 kHz and 200 kHz and for 5mm interconnects at 100 kHz and 200 kHz is not calculated as the repeater output is below the 50% reference voltage level. The calculated data clearly indicate that the delay produced by the STGB bias repeater is less than the conventional repeater for 10mm interconnect. For 5mm and 1mm interconnect also the delay produced by the STGB bias repeater is less than that of conventional repeater in the frequency range of 0.5 – 200 kHz. It is also significant to mention that the delay is very less affected by the increase of the length of interconnect in STGB bias repeater. Table VII. Delay in Conventional and STGB bias repeaters at different frequencies for various interconnect lengths frequency (kHz) 0.5 1 2 5 1 20 50 100 200

Delay (in µs) Conventional Repeater STGB Bias Repeater 10mm 5mm 1mm 10mm 5mm 1mm 1014 1008 1002 1002 1001 1000 514.3 507.6 502.2 501.5 500.8 500.2 264.3 257.6 252.2 251.5 250.8 250.2 114.3 107.6 102.2 101.5 100.8 100.2 64.3 57.6 52.2 51.5 50.8 50.2 39.2 32.6 27.2 26.5 25.8 25.2 N/A 17.6 12.2 1.15 10.8 10.22 N/A N/A 7.2 6.47 5.79 5.22 N/A N/A 4.7 3.98 3.29 2.72


72

5.35×10-

Conventional Repeater

-

5.25×10 Delay (Seconds)

5.15×10-4

STGB Bias Repeater

5.05×104.95×10 4.85×100.34

0.35

0.36

0.37

Voltage

Figure 5.9 Delays in Conventional and STGB bias repeater at various vo ltages for 10mm interconnect at 1 kHz frequency. 5.20×10-4


-

5.15×10 5.10×10 Delay Seconds

STGB Bias Repeater

5.05×105.00×104.95×10-4 4.90×10-4 0.34

0.35

0.36

0.37

Voltage

Figure 5.10 Delays in Conventional and STGB bias repeater at various vo ltages for 5mm interconnect at 1 kHz frequency. Conventional Repeater

-

5.05×10 5.04×10

-

5.03×10

-

5.02×10

-

5.01×10

-

5.00×10

-

4.99×10

-

Delay (Seconds)

STGB Bias Repeater

4.98×100.34

0.35

0.36

0.37

Voltage

Figure 5.11 Delays in Conventional and STGB bias repeater at various vo ltages for 1mm interconnect at 1 kHz frequency.


73

Figures 5.9, 5.10 and 5.11 show the delays produced in the STGB bias and conventional repeater at various supply voltages for three different lengths of interconnects, viz., 10mm, 5mm, and 1mm. These figures indicate that the delay produced by the STGB bias repeater at various voltages and for various lengths of interconnects is less than that of the conventional repeater. Also the effect of the voltage variation is less in STGB bias repeater, thus, STGB bias repeater can be used at lower voltages in sub-threshold region, which in turn also decreases average power consumption. 8.00x10

-

7.00x10

Power-Delay Product

-

6.00x10

-

5.00x10

-

4.00 x10 3.00x10

-


-

2.00x10 1.00x10

-

STGB Bias Repeater

-

0

1

2

5

10

W/L Ratio

Figure 5.12 Power-delay products in Conventional and STGB bias repeater at various aspect ratios.

Figure 5.12 shows the variation of power-delay products with aspect ratio of conventional and STGB bias repeater. The aspect ratio of nMOS and pMOS are changed and the effect is analyzed on delay and power. The delay and power values as well as power-delay product can be reduced by increasing the aspect ratio. Moreover, powerdelay product of STGB bias repeater shows almost 21% improved performance than the conventional one. The effect of temperature is also analyzed on power, delay and power-delay product of conventional and STGB bias repeater. This analysis is necessary to find the temperature sustainability of the device. There is 20% improvement in the power-delay


74

product, if the STGB bias repeater is used in place of conventional repeater in interconnect design (table VIII and figure 5.13, ). Table VIII. Power and delay in Conventional and STGB bias repeater at various temperatures Temperature


STGB Bias Repeater

Power

Power

Delay

Delay

25

1.18x10

-

6.43x10

-

1.15x10

5.15x10

-

35

1.18x10-

6.36x10-

1.16x10

5.15x10-

45

1.19x10

55

1.20x10

65

1.21x10

-

6.30x10

-

1.17x10

5.15x10

-

6.24x10

-

1.18x10

5.16x10

-

6.19x10

-

1.20x10

5.16x10

-

6.15x10

-

1.21x10

5.16x10

1.22x10

-

8x10-14 7 x10

-14

6 x10-14 Power-Delay Product

5 x10-14


4 x10-14 3 x10-14

STGB Bias Repeater

2 x10-14 -14

1 x10

0

25

35

45

55

65

75

Temperature

Figure 5.13 Power-delay products in Conventional and STGB bias repeater at various temperatures 5.6 Proposed STGB Bias Repeater and LVSB Bias Repeater

The LVSB bias buffer and STGB bias buffer are simulated for various lengths of interconnects at 180nm to 90nm technology [60] keeping V DD below the threshold voltage. Resistance, capacitance and inductance parameters of the interconnect line chosen according to the technology.


75

Table IX. Delay in LVSB and STGB buffer at different frequencies for various interconnect lengths in 180nm technology Freq. (kHz) 0.5 1 2 5 1 20 50 100 200

Delay (in µs) LVSB Buffer 10mm 5mm 1mm 1001.6 1000.9 1000.2 501.47 500.85 500.25 251.59 250.85 250.25 101.59 100.85 100.25 51.586 50.853 50.248 26.586 25.854 25.248 11.586 10.853 10.248 6.5859 5.8546 5.2485 4.0865 3.3509 2.7485

STGB Buffer 10mm 5mm 1mm 1001.5 1000.8 1000.2 501.47 500.79 500.22 251.47 250.79 250.22 101.47 100.79 100.22 51.472 50.787 50.224 26.470 25.786 25.224 11.472 10.789 10.224 6.4665 5.7857 5.2239 3.9766 3.2893 2.7237

Table X. Average power consumption in LVSB and STGB buffer at different frequencies for various interconnect lengths in 180nm techno logy Freq. (kHz) 0.5 1

1 20 50 100 200

-

Average Power consumption (×10 atts) LVSB Buffe STGB Buffer 10mm 5mm 1mm 10mm 5mm 1mm 4.6991 4.4284 4.21 0.8803 0.607 0.389 5.2388 4.6983 4.27 1.4241 0.879 0.457 6.4245 5. 417 4.47 2.6198 1.528 0.656 9.7435 7.0391 4.92 5.9640 3.239 1.111 15.264 9. 664 5.67 1.1.537 6.102 1.868 27.099 16.311 7.64 23.486 16.31 3.864 61.524 34.576 12.9 58.282 31.12 9.220 117.26 63.506 20.7 114.50 59.91 17.09 172.40 122. 4 37.5 172.13 120.0 34.03

Table IX shows delay produced by LVSB bias buffer and STGB bias buffer circuit for various lengths of interconnect at various frequencies. It is clear that the delay produced in the STGB buffer is less than the LVSB buffer for all the three lengths of interconnects at all the frequencies. It is also found that the delay is very less affected by the increasing the length of interconnect. Table X shows that the average power consumption by LVSB bias buffer is always more than STGB bias buffer for various lengths of interconnect at all the frequencies. The difference in power consumption by LVSB bias buffer and STGB bias


76

buffer is not very significant, but it will produce remarkable difference in the design of the VLSI chip having billions of transistors along with the thou sands of repeaters. Table XI. Average power consumption in LVSB and STGB bias buffer in 90nm technology Frequency 0.5 kHz 1 kHz 2 kHz 5 kHz 10 Hz 20 Hz 50 Hz 100 kHz 200 kHz 500 kHz 1 MHz 2 MHz 5 MHz 10 MHz 20 MHz

LVSB Bias 5.696738×10 5.750666×10 6.404436×107.287622×109.007799×10 1.490244×10 2.908238×10 4.728535×10 9.046027×10 2.066558×10 4.309791×10 9.272656×108.349710×10 1.643776×10 1.163286×10

STGB Bias 3.568436×10 3.621490×10 4.276297×105.156865×106.880180×10 1.278228×10 2.699521×10 4.519926×10 8.826260×10 2.039797×10 4.185116×10 6.376219×103.156971×10 7.577094×10 5.230270×10

Table XII. Power-delay product in LVSB and STGB bias buffer in 90nm technology Frequency 0.5 kHz 1 kHz 2 kHz 5 kHz 10 Hz 20 Hz 50 Hz 100 kHz 200 kHz 500 Hz 1 MHz 2 MHz 5 MHz

LVSB Bias 5.70×10 2.88×10 1.60×10 7.29×10 4.50×10 3.73×10- 2.91×10- 2.37×10 2.27×10 2.09×10 2.20×10 2.41×10 7.70×10

STGB Bias 3.57×10 1.81×10 1.07×10 5.15×10 3.44×10 3.19×102.68×102.23×10 2.15×10 1.90×10 1.89×10 8.66×10 1.26×10

Table XI depicts the comparison of the average power consumed by both the buffers for 10mm interconnect using 90nm technology. In medium frequency range, the average power consumed by single LVSB bias buffer is higher than the average power


77

consumed by the STGB bias buffer. In a chip, the length of interconnect may be very long and may use several buffers. Therefore the power consumed by the number of buffer increases significantly, which degrades the overall performance of the chip. Delay produced by the STGB bias buffer is marginally less than LVSB bias buffer at 90nm technology. Analysis reveals that the power-delay product is less for STGB bias buffer at 90nm technology (table XII). 6.00×105.00×10-

LVSB Buffer 0

4.00×10-10 Power

3.00×102.00×10-

STGB Buffer 0

1.00×10-10 0 0.34 V

0.35 V

0.36 V

0.37 V

Voltage

Figure 5.14 Power consumed in LVSB and STGB buffer at various voltages for 10mm interconnects in 180nm technology. 5.04×10-

LVSB Buffer

.03×10Delay

5.02×10STGB Buffer -

5.01×10 5.00×10

0.34

0.35

0.36

0.37

Voltage

Figure 5.15 Delay introduced by LVSB and STGB buffer for various voltages for 10mm interconnects at 180nm technology Now the performance of the both buffer is analyzed by varying the voltages keeping input signal of frequency 1 kHz in 180nm technology and for 10mm interconnect. The average power consumed by the STGB bias buffer is still found less


78

than LVSB bias buffer and almost unaffected by the change in voltage, while the average power consumed co nsumed by the LVSB buffer increases with the t he increasing voltage vo ltage (figure 5.14). The delay produced by the STGB buffer is always less than the LVSB buffer and decreasing with the increase of the voltage for both the buffers (figure 5.15). Thus the power-delay product of STGB bias buffer is less than the LVSB bias buffer as the voltage increases. Table XIII. Power-delay product in LVSB and STGB bias bu ffer for various voltages at 130nm technology for 10mm interconnect. Voltage 0.30 V 0.31 V 0.32 V 0.33 V

LVSB Bias Buffer 4.52×10 4.80×10 5.09×10- 5.39×10-14 8.20×10

STGB Bias Buffer 4.48×10 4.76×10 5.04×105.34×10-14

LVSB Buffer

8.00×107.80×10ower Delay Product

7.60×10 14 7.40×10-14 7.20×10-14

STGB Buffer

7.00×10 25

35

45

55

65

75

Temperature (oC)

Figu Figure re 5.16 5.16 Power ower-d -del elay ay prod produc uctt in LVSB LVSB and and STGB STGB bias bias buff uffer for vari variou ouss vol voltage tagess at 90nm technology for 10mm interconnect. Power-delay product of STGB bias buffer is also found to be less than LVSB bias buffer at 130nm and 90nm technology, which shows that the performance of o f the t he STGB bias buffer is better than the LVSB bias buffer in sub-threshold region reg ion at 180nm to 90nm technologies (table XIII and figure 5.16).


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3.50×10-1

LVSB Buffer

3.00×102.50×10Power

2.00×10-1

Delay

1.50×10-1

Product

1.00×10-14 STGB Buffer

5.00×100 0.23 V

0.24 V

0.25 V

0.26 V

Voltages

Figure 5.17 Power-delay product in LVSB and S TGB bias buffer at various temperatures in 180nm Technology for 10mm interconnect.

Power Delay Product

5.00×10-15 4.50×104.00×10-1 3.50×103.00×10-15 2.50×10-15 2.00×10 1.50×10-1 1.00×10-15 5.00×10-1

LVSB Buffer

STGB Buffer

0 25

35

45

55

65

75

o

Temperatu Temperature re ( C)

Figure 5.18 Power-delay product in LVSB and S TGB bias buffer at various temperatures in 90nm 90nm Techn Technol ology ogy for 10mm 10mm inter intercon conne nect. ct. Now the performance of o f the STGB and a nd LVSB LVS B bias buffers has been investigated at various temperatures for 100 kHz input signal. The result reveals that the power-delay product of STGB bias buffer is less at 180 and 90nm technologies as compared to the LVSB bias buffer (figure 5.17 & 5.18). 5.18 ). Simulation results reveal that the performance of STGB bias buffer in subthreshold region is better than LVSB bias buffer in terms of power consumption, delay and power-delay product. The temperature sustainability sustainability of o f STGB bias buffer is better for


80

low voltage operation in medium frequency range. This makes STGB buffer a better choice in designing portable devices, which dissipates less power and produces less delay in the transportation of the signal. Thus in a nutshell STGB bias buffer is a better choice in sub-threshold region to be used as repeat er for global interconnects.

CHAPTER – 6 SET D FLIP-FLOP DESIGN The major class of logic circuits is sequential circuits, in which the output is determined by the present inputs as well as the previously applied input variables. In most cases, the regenerative behavior of sequential circuits is due to either a direct or an indirect feedback connection between the input and the output. Regenerative operation can also be interpreted as a simple memory function. With the widespread use of CMOS circuit techniques in digital integrated circuit design, a large selection of CMOS-based sequential circuits has also gained popularity and prominence, especially in VLSI design. One of the most complex, power consuming and indispensable components is the flip-flop (FF) among the various building blocks in digital designs. About 30%-70% of the total power in the system is dissipated due to clocking network, and the flip-flops. Two types of flip-flops are found in literature – Single Edge-Triggered (SET) and Double Edge-Triggered (DET). The simplest flip-flop design is single edge-triggered, sampling data on only one clock edge (either on rising or falling). The SET flip-flops are usually configured as Master-Slave (MS) configuration. Several single edge-triggered D flip-flop designs were proposed in the past to reduce either power or delay. Other type of flip-flop is double edge-triggered, which samples data on both clock edges. DET flipflops have lower energy requirement (~ 20%) than SET flip-flop. There are three main drawbacks of DET flip-flops: (1) Potential increase in the design complexity, (2) Performance degradation in terms of speed and/or power consumption, (3) Control of the clock duty cycle.

SET D-FLIP FLOP DESIGN

82

Double edge-triggered flip-flops suffer performance degradation, when compared to their single edge counterparts, due to more complex design and the fact that most of the complexity increase affects the signal propagation along the critical path. Flip-flops can be static and dynamic in nature. Dynamic FF produces faulty logic levels, when clock is removed, because of charge leakage from the output node capacitances. Static FF on the other hand maintains their output state even if clock is removed. The number of logic gate delays in a clock period is reducing by 25% per generation in high-performance IA-32 microprocessors, and is approaching a value of 10 or smaller beyond 0.13

μm

technology generation. As a result, latency of flip-flops or

latches is becoming a larger portion of the cycle time. In addition, the energy consumed by low-skew clock distribution networks is steadily increasing and becoming a larger fraction of the chip power. In order to achieve a design that is both, high performance while also being power-efficient, careful attention must be paid to the design of the flipflops. 6.1 SET D Flip-Flop

Conventional 16- transistor single edge-triggered D flip-flop operates either at rising edge or falling edge of the clock. For the correct operation of the flip-flop, the input value has to be maintained constant just before setup time (t setup) and just after hold time (t hold) the triggering edge of the clock. The circuit in the figure 6.1 shows a conventional 16-transistor SET D flip-flop [36]. In this figure, master and slave sections are demarcated by dashed vertical line. A pMOS transistor is used in the feedback path as it leads to a more compact layout than using a nMOS transistor. In high noise environment, pass transistors may be replaced with transmission gates.


83

Figure 6.1 Conventional SET D flip-flop The design of 10-transistor negative edge-triggered SET D flip-flop [25] is shown in figure 6.2. In this design, the feedback circuit of the master section is removed and in slave section, feedback loop consists of transmission gate. When clock level is ‘HIGH’, master latch is functional and the inverse of the data is stored to an intermediate node X. When the clock goes to ‘LOW’ logic level, the slave latch consisting of transistor TN2 and regenerative feedback loop L1 becomes functional and produces data at the output Q and QB. The SET D flip-flop maintains the logic level even if clock is permanently grounded (stopped), proves that it is static in nature.

Figure 6.2 10-transistor SET D flip-flop


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The aspect ratios of the transistors involved in the SET D flip-flop design are given in the Table XIV. In comparison to the conventional SET D flip-flop the tentransistor SET D flip-flop, is advantageous on account of reduced transistor count. TABLE XIV. Aspect ratios of 10-transistor SET D flip-flop Transistor

Aspect Ratio (W/L)

TN1

22 / 0.6

INV1 – nMOS

22 / 0.6

INV1 – pMOS

22 / 0.6

TN2

22 / 0.6

INV2 – nMOS

22 / 0.6

INV2 – pMOS

22 / 0.6

INV3 – nMOS

2 / 0.6

INV3 – pMOS

2 / 0.6

TG – nMOS

2 / 0.6

TG – pMOS

2 / 0.6

Now the main aim is to modify the 10-transistor design to reduce the overall area and power consumption such that the design becomes better applicable for the low power applications. To continue with this, the design is first modified by changing the substrate connections. Figure 6.3 shows Low Voltage Swapped Body (LVSB) [23] bias 10-tramsistor SET D flip-flop design. In this design, substrate of all pMOS transistors are connected to ground and substrate of all nMOS transistors are connected to the supply voltage (VDD). In this type of substrate connection, bulk voltage is less than the source voltage (VB < VS). As a result, all devices receive an amount of forward body bias equal to V DD. In swapped body bias connection the depletion width between source and bulk is less and diode between source and bulk is forward bias. The forward bias voltage between drain and bulk depends upon the drain voltage as bulk voltage is fixed. More the drain voltage, less will be the forward bias voltage, and therefore, less the depletion width between drain and bulk.


85

Figure 6.3 LVSB bias 10-transistor SET D flip-flop Figure 6.4 shows Sub Threshold Grounded Body (STGB) bias 10-tramsistor SET D flip-flop design [22]. In this design, substrates of all nMOS and pMOS transistors are connected to ground. This type of substrate connection reduces the complexity of the design. All the nMOS transistors are at no-body bias condition and all pMOS are at forward body bias condition. STGB design is less sensitive towards supply and ground noise as compared to LVSB design.

Figure 6.4 Sub-Threshold Grounded Body (STGB) bias 10-transistor SET D flip-flop


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Figure 6.5 NBB 10-transistor SET D flip-flop When source of the transistor is shorted with the bulk, then V SB becomes zero and the transistor becomes zero body bias (figure 6.5). The threshold voltage of such transistor becomes independent of the substrate bias effect. No-body bias (NBB) condition is also applied in the present design for fair comparison. 6.2 Simulation and Analysis

The 10-transistor and 16-transistor SET D flip-flop designs are tested in 65nm technology using tanner tools v13. Table XV gives the comparison result of the two designs. From the table, it is clear that the power and delay; and thus leading to powerdelay product of the 10-transistor design is better than the conventional 16-transistor design. Also the design superiority of 10-transistor over 16-transistor SET D flip-flop design has been proved earlier [25]. Thus, further the 10-transistor SET D flip-flop design will be considered. Table XV. Comparison of 16-transistor and 10-transistor SET D flip-flops S. no.

SET D flip-flop

Power

Delay

Power-delay product

1.

16-transistor

2.53e-8

5.23e-5

1.32e-13

2.

10-transistor

3.28e-9

5.13e-6

1.68e-15


87

During the simulation and calculation, the designs are tested in 65nm and 45nm technologies to prove their technology independence. First the data in 65nm is compared and then the data in 45nm is taken to show the design superiority of one over the others. Designs are compared by taking the temperature, frequency and supply voltage as parameters. 6.2.1 Comparison of LVSB and STGB Bias 10-Transistor SET D Flip-Flop

Circuits can be compared at various frequencies to check its compatibility with various applications. In each case, we can measure average power consumption and delay introduced by the circuit. The circuit having less power-delay product should be considered better. Design better in one technology may not perform well in other technology, so the design must be tested in at least two technologies to be universally acceptable. During the simulation and calculation, the designs are tested in 65nm and 45nm technologies to prove their technology independence. Earlier proposed design [25] with the reported aspect ratio and zero body biasing is compared with the LVSB and STGB designs with W/L ratio 2. From Table XVI and XVII, it is clear that STGB designs at W/L = 2 shows less power consumption than the earlier proposed design with the reported aspect ratio and no-body biasing. Table XVI. Comparison of SET D flip-flop designs in 65nm technology. Design

LVSB STGB Earlier Design [25] with no-body biasing

Power consumption (Watts) 1.238054e-08 1.179902e-08 1.044951e-07

Table XVII. Comparison of SET D flip-flop designs in 45nm technology. Design

LVSB STGB Earlier Design [25] with no-body biasing

Power consumption (Watts) 8.994676e-09 8.584484e-09 3.501623e-08


88

Power consumption by LVSB and STGB designs is 5 to 10 times less than the earlier reported design. Further, we will compare the LVSB and STGB designs to check their performance. The legends used in the figures further in this chapter are shown below.

LVSB STGB NBB Power in Watts PDP in Watts × sec.

1.2E-06

P

1.0E-06

O

8.0E-07

W

6.0E-07 E R

4.0E-07

2.0E-07

. 0

0.1

0.5

1

10

50

100

Frequency (MHz)

Figure 6.6 Power consumption at various frequencies in 65nm technology


89

6.0E-07

P O

5.0E-07

4.0E-07

W

3.0E-07 E R

2.0E-07

1.0E-07

0

0.1

0.5

10

1

50

100

Frequency (MHz)

Figure 6.7 Power consumption at various frequencies in 45nm technology. As shown in the figure 6.6 and 6.7, the power consumption by the STGB design is always less than the LVSB design at all the frequencies ranging from 0.1 MHz to 100 MHz in two different technologies. 100%

80% P D P

60%

40%

20%

0

0.1

0.5

1

10

50

100

Frequency (MHz)

Figure 6.8 Power-delay products at various frequencies in 65nm technology in percentage scale.


90

100%

80% P

60% D P

40%

20%

0

0.1

0.5

1

10

50

100

Frequency (MHz)

Figure 6.9 Power-delay products at various frequencies in 45nm technology in percentage scale. The power-delay product of STGB is drawn with respect to LVSB in figure 6.8 and 6.9. The power-delay product of the STGB design is on an average 10% less than the LVSB design in 65nm technology (figure 6.8). In 45nm technology, STGB design shows average improvement of 13% in power-delay product than the LVSB biased design (figure 6.9). 4.5E-08 4.0E-08 P O W E R

3.5E-08 3.0E-08 2.5E-08 2.0E-08 1.5E-08 1.0E-08 5.0E-09

0

W/L =1

W/L =2

Aspect ratios of transistors

Figure 6.10 Power consumption at various aspect ratios in 65nm technology


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3.5E-08 3.0E-08 P O

2.5E-08

W 2.0E-08 E

1.5E-08 1.0E-08 5.0E-09

0

W/L =1

W/L =2

Aspect ratios of transistors

Figure 6.11 Power consumption at various aspect ratios in 45nm technology Further the aspect ratios of the designs are reduced to see the effect on the output. Designs are tested taking power consumption as a measurement parameter at W/L = 1 and W/L = 2. The supply voltage is taken to be 0.3V, frequency of the signal 10 MHz at o

temperature of 25 C. Again it can be verified from the figure 6.10 and 6.11, that the power consumption in STGB SET D-FF is less than the LVSB SET D-FF at different aspect ratios of the transistors in the designs. The output of the STGB SET D-FF design for W/L = 1 and W/L = 2 keeping 0

supply voltage VDD at 0.3V, clock frequency at 10 MHz and temperature at 25 C is analyzed. Both designs show better output performance in terms of power consumption at less aspect ratio, but the output waveform is better in case of W/L = 2 as the rise time and fall time in the output waveform is 5% and 20% less respectively in comparison to the output at W/L = 1. Hence, more the aspect ratio less will be the rise and fall time. So the trade-off is required between area and performance according to the requirement in application. Till now, we compared the STGB and LVSB designs of SET D-FF and results show that the STGB design is better than LVSB design. So further we like to compare these two designs along with the NBB design of the SET D-FF for different parameters and conditions.


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6.2.2 Comparison of LVSB, STGB and NBB Designs of 10-Transistor SET D FlipFlop

All the three designs are compared in 65nm and 45nm with the temperature, supply voltage and frequency as parameters and average power consumption, delay and power-delay product are measured. The design, which shows less power consumption, delay and thus the power-delay product, will be proposed for the construction of low power applications. 1.0E-06 9.0E-07 P

8.0E-07

O

7.0E-07

W

6.0E-07 5.0E-07

E

4.0E-07 R

3.0E-07 2.0E-07 1.0E-07

0

25

35

45

55

65

75

o

Temperature ( C)

Figure 6.12 Power consumption with temperature at 65nm technology 6.0E-07 P O

5.0E-07

W

4.0E-07

E

3.0E-07

R

2.0E-07 1.0E-07

0 25

35

45

55

65

75

o

Temperature ( C)

Figure 6.13 Power consumption with temperature at 45nm technology


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3.00E-14 2.50E-14 P D P

2.00E-14 1.50E-14 1.00E-14 5.00E-15

0

25

35

45

55

75

65

o

Temperature ( C)

Figure 6.14 Power-delay products with temperature at 45nm technology 1.2E-6 1.0E-6

P O

8.0E-7

W

6.0E-7

E

4.0E-7

R

2.0E-7

. 0

0.1

0.5

10

1

100

50

Frequency (MHz)

Figure 6.15 Power consumption at various frequencies in 65nm technology 6.0E-07

P O

5.0E-07 4.0E-07

W E R

3.0E-07 2.0E-07 1.0E-07

0

0.1

0.5

1

10

50

100

Frequency (MHz)

Figure 6.16 Power consumption at various frequencies in 45nm technology


94

Figure 6.12 and 6.13 shows the power consumption comparison graph of the LVSB, STGB and NBB designs in 65nm and 45nm technology. It is clear that the No body bias design shows less power consumption than the contending LVSB and STGB designs at all the values of the temperature. Similar results can be interpreted for the power-delay product (PDP) from the figure 6.14. Thus at 65nm and 45nm technology, where channel lengths of the MOSFET are taken 70nm and 50nm respectively, the power consumption and PDP of the NBB design is less and hence the temperature sustainability of the NBB design is better. As shown in figures 6.15 and 6.16, the average power consumption by the NBB design is always less than the STGB and LVSB design at all the frequencies ranging from 0.1 MHz to 100 MHz in medium frequency range. The power-delay product of the STGB design is on an average 10% less than the LVSB design but the NBB design shows 63% improvement than the LVSB design and 53% than the STGB design in 65nm technology. In 45nm technology, STGB design shows 13% improvement and NBB design shows 61% reduction in power-delay product than the LVSB biased design. More simulation results are presented in Appendix – B. It is also verified in all the designs that the output is present even if clock signal is absent, so the designs are static in nature. The NBB design of static SET D flip-flop shows better performance in terms of power consumption and area among other designs discussed in this chapter. This design is tested in 65nm and 45nm technologies, thus it is also technology independent. Hence NBB design of negative edge-triggered static SET D-FF design is suitable for portable application, as it is more area and power efficient.

CHAPTER – 7 DOMINO LOGIC AND GATE DESIGN

Logic circuits, or gates, which perform Boolean operations on multiple input variables and determine the outputs as Boolean functions of the inputs, are the basic building blocks of all digital systems. Static logic circuits allow versatile implementation of logic functions based on static, or steady-state, behavior of simple nMOS or CMOS structures. A typical static logic gate generates its output corresponding to the applied input voltages after a certain time delay, and it can preserve its output level (or state) as long as the power supply is provided. This approach, however, may require a large number of transistors to implement a function, and may cause a considerable time delay. Compared to nMOS logic circuits, CMOS logic circuits, which are extensively used, require more number of gates to realize the same logic function. Thus in CMOS logic though the power consumption is less, but the area requirement is more. So, we need to select the logic circuit; which can realize the logic functions without losing the advantage of less power consumption with less number of transistors. In high-density, high-performance digital implementations, where reduction of circuit delay and silicon area is the major concern, dynamic logic circuits offer several significant advantages over static logic circuits. The operation of all dynamic logic gates depends on temporary (transient) storage of charge in parasitic node capacitances, instead of relying on steady-state circuit behavior. Dynamic logic circuits require periodic clock signals in order to control charge refreshing. Also, the use of common clock signals throughout the system enables us to synchronize the operations of various circuit blocks. As for the power consumption, which increases with the parasitic capacitances, the dynamic circuit implementation in a smaller area will, in many cases, consume less power than the static counterpart, despite its use of clock signals. The problem with the dynamic logic circuits is that it cannot be cascaded directly. This severe limitation seems

DOMINO LOGIC AND GATE DESIGN

96

to undermine all the other advantages of dynamic CMOS logic, such as low power consumption, large noise margins, and low transistor count. To achieve ultimate goal of reliable, high speed, compact circuits using least complicated clocking scheme, Domino CMOS logic is preferred. This logic circuit is same as dynamic CMOS logic circuits except one more inverter is added at the output, and thus the area efficiency is slightly decreased. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are lack of design automation, decreased tolerance to noise and increased power consumption. Dynamic CMOS circuits, featuring a high speed operation are used in high performance VLSI designs. Domino logic circuit techniques are extensively applied in high performance microprocessors due to the superior speed and area characteristics. Over the past decade, considerable research is devoted to the development of energy efficient VLSI circuit and systems for portable systems. In this chapter, domino AND gates with different substrate biasing techniques and conventional body bias inverter are designed and their performances are compared. Comparison of body bias methods using delay, power and PDP indicates that separately biasing the pre-charge and evaluation tree transistor bodies permits high-speed and energy-efficient ultra-low voltage domino circuits to be realized. Minimum energy in the sub-threshold region then depends not only on supply voltage but also on the substrate bias voltage. 7.1 Circuit Techniques

Dynamic domino logic circuits are widely used in modern VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic. This work discusses several domino circuits design techniques to reduce the power consumption of domino logic while simultaneously improving noise immunity. Domino logic gates are frequently employed in high performance circuits for high speed and area efficiency. As supply voltage is


97

reduced, delay increases, unless threshold voltage V t is also decreased. Substrate biasing provides an effective circuit-level technique for varying threshold voltage, as can be see n in the equation of threshold voltage below-

� = � +  ( | − 2∅ | −  |2∅ ) Where,

V to is

------------ (7.1)

the zero-bias threshold voltage, γ the body-effect coefficient, VSB

the source-to- bulk voltage,

ΦF

the quasi-Fermi potential. By changing the substrate

biasing voltage the threshold voltage of the circuit can be desirably changed. Minimum power consumption in sub-threshold region depends not only on supply voltage but also on the sub-threshold bias voltage. For different biasing schemes, the same zero body biased inverter is selected at the output as shown in figure 7.1.

Figure 7.1 Conventional body bias inverter In order to enhance the performance of the circuit, various body biasing techniques are used. The substrate of the MOS transistors is connected in six different ways. Six body biasing schemes for the evaluation networks are shown in figure 2. 1. The substrate of nMOS is connected to clock and the substrate of pMOS is connected to supply voltage VDD (SB1) (figure 7.2(a)). 2. The substrate of nMOS and pMOS is connected to clock (SB2) (figure 7.2(b)).


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3. The substrate of nMOS is connected to supply voltage VDD and the substrate of pMOS is connected to clock (SB3) (figure 7.2(c)). 4. The substrate of nMOS is connected to supply voltage VDD and the substrate of pMOS is connected to Ground (SB4) (figure 7.2(d)). 5. The substrate of nMOS and pMOS both connected to supply voltage VDD (SB5) (figure 7.2(e)). 6. The substrate of nMOS is connected to its source terminal and the substrate of pMOS is connected to clock (SB6) (figure 7.2(f)).


99

Figure 7.2 Different body biasing schemes (a) SB1, (b)SB2, (c)SB3, (d)SB4, (e)SB5, (f)SB6 7.2 Simulation and Implementation Results

The designs are simulated using 32nm, 45nm and 65nm technology. Designs are tested for different biasing conditions, where average power consumption and delay of the circuits at different supply voltages, operating frequencies, and temperatures are taken as parameters of comparison. 7.2.1 Simulation in 32nm technology

Figure 7.3 Power consumption at various voltages in 32nm technology


Figure 7.4 Delay at various voltages in 32nm technology

Figure 7.5 Power consumption versus frequency in 32nm technology

Figure 7.6 Power consumption versus temperature in 32nm technology

100


101

Figure 7.7 Delay versus temperature in 32nm technology

Figure 7.8 Power-delay product versus temperature in 32nm technology Supply voltage, frequency and temperature are the parameters. The standard value of temperature, input signal frequency, and supply voltage in 32nm technology are 25°C, 500 kHz and 0.22V respectively. Power consumption, delay are measured keeping one parameter variable with two other parameters constant, e.g., power consumption is calculated at various frequencies keeping the supply voltage at 0.22 V and temperature at 25°C. The power consumption depends upon the supply voltage. As the supply voltage increases, the power consumption also increases. It is clear from the figure 7.3, that the supply voltage is varied from 0.20 to 0.24 V such that the circuit operates in subthreshold region. The power consumption is measured in various body biased designs and found that the SB6 design shows the least power consumption. Delay also depends upon


102

the supply voltage. The SB6 biasing and SB4 biasing of the gate shows the comparable delay (figure 7.4) but overall power-delay product of the SB6 biased gate is least among all the biasing schemes. Power consumption is proportional to the frequency of the applied input signal. From the figure 7.5, the power consumption at various frequencies in SB6 biasing is minimum in low to medium frequency region up to 5 MHz, but more than SB2 biasing above 5 MHz frequency. Power consumption in the chip increases with the temperature, which in turn degrades the performance of the chip. Thus the performance of the design to be tested at various temperatures is also an important simulation step. The power consumption by the o

SB6 design is less up to 45 C (figure 7.6). Delay introduced by the SB6 design is always less at various temperatures among all the designs (figure 7.7). Hence the power-delay o

product is least but up to 45 C among all the designs (figure 7.8). 7.2.2 Simulation in 45nm technology

.

Figure 7.9 Power consumption at different voltages in 45nm technology


Figure 7.10 Power-delay Product at various voltages in 45nm technology

Figure 7.11 Power consumption at different frequencies in 45nm technology

Figure 7.12 Power-delay product versus frequency in 45nm technology

103


Figure 7.13 Power consumpt ion at different temperatures in 45nm technology

Figure 7.14 Delay at various temperatures in 45nm technology

104


105

Figure 7.15 Power-delay product versus temperature in 45nm technology

Figures 7.9 and 7.10 are showing power consumption, power-delay product at different voltages with frequency of input signal 500 kHz and temperature of 25°C. Proposed SB6 biasing, in which the substrate of nMOS is connected to its source terminal and the substrate of pMOS is connected to clock condition, shows minimum power consumption, delay and power-delay product. At different frequencies with supply voltage of 0.22V and temperature of 25°C, SB6 biasing condition again shows minimum value of power consumption, and PDP (figure 7.11 and 7.12). In 45nm technology for different temperatures with input signal frequency of 500 kHz and voltage of 0.22V (figure 7.13-7.15), SB6 biasing consumes less power, introduces less delay and thus less power-delay product.


7.2.3 Simulation in 65nm technology

Figure 7.16 Power consumption versus voltage in 65nm technology

Figure 7.17 Delay at different voltages in 65 nm technology

106


107

Figure 7.18 Power-delay product at different voltages in 65nm technology Similar results are obtained in 65nm technology confirming that the SB6 biasing is the best biasing for domino AND gate design. The power consumption by the gate is least at various supply voltages, when the SB6 biasing is used (figure 7.16). The SB1 biased gate shows sudden decrease in delay at supply voltage of 0.34 V but at other supply voltages, it is showing the higher delay (figure 7.17). SB5 biasing is showing least delay but overall power-delay product is less in the proposed SB6 biasing (figure 7.18). Though the power consumption with various biasing at various frequencies is almost equal (between 10 – 100 kHz) but as the frequency increases the power consumption by the gate with SB6 biasing comes out to be less than the other biasing schemes. Comparison of body bias methods using delay, power and PDP indicates that separately biasing the pre-charge and evaluation tree bulk of the MOS transistors permits high-speed and energy efficient ultra low voltage domino circuits to be realized. Simulation analysis reveal that the domino logic AND gate design using proposed SB6 biasing scheme, in which the substrate of nMOS transistors are connected to its source terminal and the substrate of pMOS transistor is connected to clock, is an energy efficient design and since the simulation is performed at three different technologies, it confirms that the proposed design is technology independent also.

CHAPTER – 8 STATIC D-LATCH DESIGN

Gates are the basic building blocks of combinational circuits and in the same way, latches and flip-flops are the building blocks of sequential circuits. While gates are built directly from transistors, latches can be built from gates, and flip-flops can be built from latches. This fact will make it somewhat easier to understand latches and flip-flops. One latch or flip-flop can store one bit of information. The main difference between latches and flip-flops is that for latches, their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either at the rising or falling edge of the enable signal. In other way it can be understood that a flip-flop is called latch, if the instance at which output should change has no well defined instances of clock input. In general, flip-flops are edgetriggered and latches are level triggered sequent ial devices. In synchronous systems, flip-flops and latches are the starting and ending points of signal delay paths, which decide the maximum speed of the systems. Since, they are clocked at the system operating frequency, so latches and flip-flops consume a large amount of power. About 30%-70% of the total power in the system is dissipated due to clocking network, latches and the flip-flops. Flip-flop and latches are commonly used as sequential elements for synchronizing data signals. A conventional single level-triggered latch typically latches data either on the positive or the negative level of the c lock cycle. There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major differences in these flip-flop types are the number of inputs they have and how they change state. By far the most important of the clocked latches, however, is the clocked D-latch. This latch has a single data line, D, as input. The effect is that D is only copied to the output Q when the clock is active.

STATIC D-LATCH DESIGN

109

Moreover, the latch can also be categorized based on whether they are dynamic or static in nature of their operation. In the case of dynamic latches the charge stored at transistor node capacitances, leaks away in the transistor’s ‘OFF’ state (clock stopped) and thus can produce faulty logic levels. On the other hand, the static latch maintains their state even when the clock is stopped and power is maintained. Latch is the fundamental component for the processor storage. The data must be stable before the falling edge of the clock and after the falling edge of the clock for correct storage in the latch. The level sensitive latches are widely used in high performance ICs, where timing analysis is more critical and challenging. Now, here in this chapter several designs of latches are proposed and their operations are defined in sub-threshold region. For V GS < V t, there are less minority carriers in the channel, but their presence comprises a current and the state is known as weak-inversion. In standard CMOS design, this current is a sub-threshold parasitic leakage, but if the supply voltage (V DD) is lowered below V t, the circuit can be operated using the sub-threshold current with ultra-low power consumption Sub-threshold circuit operation is driven by currents much weaker than standard strong-inversion circuits, and this is characterized by longer propagation delays but limited to lower frequencies. Due to the exponential dependency on the value of V t, sub-threshold circuits are very sensitive to process variations and temperature fluctuation. These along with other factors have to be taken into consideration, while designing circuits for sub-threshold operation. The total energy dissipation ET of static CMOS circuits operating in sub-V t regime is modeled as shown in Eq. (8.1) and (8.2) -

� =  +  +  � =   +    +   

(8.1) (8.2)

Where, Edyn, Eleak , and Esc are the average energy dissipation due to switching activity, the energy dissipation resulting from integrating the leakage power over one clock cycle T clk , and the energy dissipation due to short circuit currents, respectively. The energy dissipation Esc has been shown to be negligible in the sub-V t regime [21]. The dynamic and leakage power dissipation is only results from sub-threshold currents [38].


110

The dynamic power dissipation, since the input and the supply voltages are less than the threshold voltage of the transistor, is also very less as compared with the super-threshold operation of the device. The critical path delay in CMOS devices is given by [39]

   =    

(8.3)



Where, k crit is the critical path delay, n denote the slope factor and VT the thermal voltage in Eq. (8.3). Thus the total energy dissipation E T assuming operation at the maximum frequency is given in Eq. 8.4 -

   � =  [ +   ]

(8.4)

It is found that the sub-V t model predicts the energy dissipation with less than 3.8% error [40]. Flip-flop and latch are the most commonly used sequential elements whose purpose is synchronizing data signals. A latch is a three-terminal element, having two inputs, data (D) and clock (clk) and an output (Q). For timing requirements, level sensitive latches are widely used in high performance ICs, where timing analysis is more critical and challenging. The conventional edge-triggered flip-flop (FF) design methods using clock synchronization are very practical, since only the timing constraints defined by a given clock frequency are optimized. However, clock skew that has a strong influence on clock frequency design prevents the FF design because of the variations. Thus, level-triggered latch design method has been proposed as alternatives to FF-based design methods. There are three main sources o f power dissipation [41] in the latch: • Internal power dissipation of the latch, including the power dissipated for switching the output loads. • Local clock power dissipation, presents the portion of power dissipated in local clock buffer driving the clock input of the latch.


111

• Local data power dissipation, presents the portion of power dissipated in the logic stage driving the data input of the latch. Total power parameter is the sum of all three measured kinds of power.

8.1 Latch Designs 8.1.1 Conventional 8-Transistor (8T) Latch Design

The gate level schematic and block diagram of D-latch [21] is shown in figure 8.1. The conventional 8-transistor (8T) latch (as shown in figure 8.2) uses transmission gate logic [21]. The output Q assumes the value of the input D, when clock is active, i.e. for CLK=1. When the clock signal goes to zero, the output will simply preserve its state. Thus the clock input acts as an enable signal, which allows data to be accepted into the D-latch. The transmission gate at the feedback loop is activated by the inverse of CLK signal, CLKB. The conventional latch is positive level triggered, i.e., input ‘D’ is only copied to the output ‘Q’ when the clock signal is positive. The conventional latch circuit is designed using S-edit of tanner EDA tool as presented in figure 8.2.

Figure 8.1 Gate level schematic and block diagram of D-latch


112

Figure 8.2 Schematic view of conventional 8T latch

Conventional latch is a primarily used in sequential memory related applications. A transmission gate must not be called a logic gate but rather resembles a contact that makes or breaks a conducting path under the direction of a control voltage. Bistable circuit behavior is obtained by connecting two inverting gates so as to form a positive feedback loop. The two stable states of equilibrium then naturally correspond to two memory states.

Layout Design of Conventional Latch: The layout design for the conventional 8T latch is presented in figure 8.3. In the layout design of the conventional 8T latch, number of poly contacts is two and number of poly and metal overlap is only one.


113

Figure 8.3 Layout design of conventional 8T latch The designed layout of conventional latch is used to extract the parasitic capacitances. The total number of parasitic capacitances is six in this design, which are having value more than 1fF. Total capacitance and output capacitance are shown in table XVII. DRC is performed to validate a high overall yield and reliability of the design. LVS check confirms that shorts, opens, component mismatches, and missing components are not found. Table XVIII. Parasitic capacitances of conventional 8T latch Latch Existing 8T

Parasitic Capacitance (F) Output capacitance 1.80e-016

Total capacitance 7.06e-16


114

Figure 8.4 Input-output waveform of conventional 8T latch The waveform in figure 8.4 of the conventional latch shows that it is a positive level triggered latch. The output changes at positive level of the clock and remains constant during the negative level of the clock. As in this waveform when positive level of clock comes then according to data line output occurs and it maintains its output state for the negative level and again changes its state during the next positive level of clock. 8.1.2 Proposed 8-Transistor (8T) Latch Design

The proposed 8 transistor static latch uses the pass transistor logic instead of transmission gate [49]. In this design as shown in figure 8.5, the transistor P1 at the input side takes the data input and passes when the clock signal is low. The N1 is forming the feedback loop.


115

The transistor N3 is passing the signal when clock signal is high and transistor P3 is passing the intermediate signal when clock signal is low. The nMOS transistors are weak “1” and pMOS transistors are weak “0”, thus pass transistor logic gives threshold loss problem and this is overcome by the inverters present in the circuit. Output ‘QB’ suffers with some threshold loss problem and that is observed during simulation, but output inverter compensates this problem and output waveform of ‘Q’ is not showing any threshold loss.

Figure 8.5 Schematic view of proposed 8T latch

The same clock signal is given to the transistors P1 and N1, but because of the complementary behavior of pMOS and nMOS, only one transistor will act at a time time and pass the signal to the input of the first inverter. Hence, data is passed at the negative level of the clock and output remains constant at the positive level of the clock. Therefore, the presented latch design is negative level triggered. By changing the positions of the P1 and N1 transistors, the latch circuit circuit becomes beco mes positive level triggered.


116

Layout Design of Proposed 8T Latch: The layout design for the proposed 8T latch is shown in figure 8.6. In the layout design of the proposed 8T latch, number of poly contacts is two and one metal to poly overlap.

Figure 8.6 Layout design of proposed 8T latch Table XIX. Parasitic capacitance of proposed 8T latch Parasitic Capacitance (F) Latch Output capacitance

Total capacitance

1.06193e-016

5.744908e-16

Proposed 8T

The parasitic capacitance values are extracted from from the layout layout presented in figure 8.6. The total numbers of parasitic capacitance are seven in this design having value more than

1fF.

The

parasitic

capacitance

values

are

shown

in

table

XIX.


117

The waveform of the proposed latch shows that it is a negative level triggered latch as shown in figure 8.7. The output changes at negative level of the clock and remains constant during the positive level of the clock. Slight distortions are observed in the output waveform but these are acceptable accept able within the noise margin [50].

Figure 8.7 Input-output waveform of the pro posed 8T latch


118

8.1.3 Proposed 8-Transistor Latch with Delay Element

Figure 8.8 Schematic view of proposed 8T latch with delay element The 8-transistor latch design with delay element [51] is presented in figure 8.8. The source terminal of first pMOS transistor P1 is connected to the data input and this data will be available at the drain terminal only when the clock will be low. Since the pMOS transistors are weak zero transistor, so the small threshold loss is observed when data is zero. But overall performance of the device is almost unaffected because of the presence of the inverters. A delay element is used in between the path which works on charge sharing basic. The transistor N1 passes the output according to the delayed version of the clock [52]. Hence, whenever clock is high, data is not passing through the transistor P1 but output is again feedback through the circuit and output remains the same. Therefore, this proposed clocked latch acts as a negative level triggered. The delay element can be implemented using resistor or a single transistor. This D-latch requires a delay on the clock fed to the selector of Mux1. In this case, the Inv1 could switch and change the state of the entire latch. Mux should toggle only after the Q (the feedback input of Mux1) reaches the sufficient level. Without this delay, the selected input of the Mux would toggle on the negative level of the clock before the updated value arrives at its feedback input. nMOS is preferred over pMOS because nMOS has less “on” resistance and hence shows less average power consumption and it is also proved by simulations presented further.


119

If delay element is taken as transistor, then delay element can be nMOS or pMOS and their gate terminals may be connected to supply voltage or ground and thus four different combinations are possible, which are shown in figure 8.9.

Figure 8.9 Circuits of 8T latch using d ifferent delay elements: (A) nMOS connected to ground, (B) nMOS connected to VDD ,(C) pMOS connected to ground, (D) pMOS connected to VDD. The delay element can be a transistor, so the simulation results present the comparative study of all possible combination of delay element. The simulation at various frequencies is shown in the figure 8.10 to figure 8.12. The simulation is performed keeping both voltage and temperature constant at their 0

standard values of 0.22V and 25 C respectively. Simulation carried out in 45nm technology. It can be seen from the simulation results that nMOS with its gate grounded shows the best results (least power consumption, delay and hence power-delay product) among all other combinations.


120

Figure 8.10 Comparison of APC for different delay circuits at 45nm technology

Figure 8.11 Comparison of delay for different delay circuits at 45nm technology


121

Figure 8.12 Comparison of PDP for different delay circuits at 45nm technology From the above comparisons it is clear that nMOS is the most suitable delay element when its gate terminal is connected to ground as shown in figure 8.9 (a). All of these comparisons are shown with frequency variation. Tables of these graphs and other comparison results with temperature and voltage variation in 45nm and 65nm can be seen in Appendix - C. The nMOS with gate terminal connected to ground shows much less delay and hence least power-delay product, thus becomes o ptimum choice as a delay element further.

Figure 8.13 Layout design of proposed 8T latch with delay


122

Figure 8.13 shows the layout design for the proposed 8T latch with delay. In the layout design of the proposed 8T latch with delay, number of poly contacts is three and number of poly and metal overlap is only one. The designed layout of proposed 8T latch with delay is used to extract the parasitic capacitances as shown in Table XX. The total numbers of parasitic capacitance are nine in this design, which are having value more than 1fF. DRC is performed to validate a high overall yield and reliability of the design. LVS check confirms that shorts, opens, component mismatches, and missing components are not found. Table XX. Parasitic capacitance of proposed 8T latch with delay Parasitic Capacitance (F) Latch 8T Delay latch

Output capacitance

Total capacitance

1.31783e-016

1.06193e-016

Figure 8.14 Input-output waveforms of proposed 8T latch with delay


123

This proposed clocked latch acts as a negative level triggered latch. Whenever, clock is negative, the output changes with respect to data but remains constant as clock goes positive as can be seen from the waveform presented in figure 8.14. The output remains unaffected even if clock is absent, thus the latch is static in nature. The comparison results show that 8T latch with delay is better than 8T latch design [53]. 8.1.4 Proposed 7-Transistor (7T) Latch

Figure 8.15 Schematic view of proposed 7T latch

Figure 8.16 Layout design of proposed 7T latch


124

Table XXI. Parasitic capacitance of proposed 7T latch Parasitic Capacitance (F) Latch Proposed 7T

Output capacitance

Total capacitance

1.09941e-016

4.91056e-16

Figure 8.17 Input-output waveform of proposed 7T latch The extracted value of parasitic capacitances from the layout is presented in Table XXII. Total number of parasitic capacitances is seven in this design, which are having value more than 1fF. The proposed 7-transistor static latch also uses the pass transistor logic as shown in figure 8.15. In this design [54], the transistor P1 at the input side takes the data input and passes when the clock signal is low. The transistor N1 is forming the feedback loop. The transistor N4 is passing the output of first inverter.


125

The layout design for the proposed 7T latch is shown in figure 8.16. In the layout design of the proposed 7T latch, number of poly contacts is two and number of poly and metal overlap is only one. The proposed 7T latch is negative level triggered as can be inferred from the waveform presented in figure 8.17. Since nMOS transistors are weak ‘1’, thus pass transistor logic gives threshold loss problem, which is evident from the waveform of QB (Q bar). But this is overcome by using inverter at the output in the circuit. It compensates this problem and output waveform of ‘Q’ is not showing any threshold loss. The proposed 7T latch is negative level triggered. Whenever, clock is low, the output changes with respect to data but remains constant as clock goes positive. The output remains unaffected even if clock is absent; hence, the proposed latch is static in nature. 8.1.5 Proposed 7 - Transistor Latch with Delay element

Figure 8.18 Schematic view of proposed 7T latch with delay The proposed 7-transistors design with delay [55] implements pass transistor logic for the transmission of data through it as shown in figure 8.18. The source of first pMOS P1 transistor is connected to the data input and this data will be available at the drain terminal, when the clock will become low.


126

Since the pMOS transistors are weak zero transistors, so the small threshold loss is observed when data is zero. But overall performance of the device is almost unaffected because of the presence of the inverters. The N4 transistor in the path works as a delay element on a charge sharing basis. The added delay is essential for the correct operation of the latch, and it also reduces set up time. Without the delay the setup time would be the path delay of the input signal (D) to the feedback input of (Q). However, with the addition of delay, it is ensured that the new value will be ready before the feedback arrives. For the purpose of delay element, nMOS is preferred over pMOS because nMOS provides less resistance and hence shows less power consumption, and also nMOS is faster than pMOS. The transistor N1 passes the output according to the delayed version of the clock. Thus, whenever clock is high, data is not passing through the transistor P1 but output is again feedback through the circuit and output remains the same. Therefore, this proposed clocked latch acts as a negative level triggered flip-flop. The output remains unaffected even if clock is absent, thus the proposed latch is static in nature. The aspect ratio of all transistors is taken as 1, i.e., W/L = 1.

Figure 8.19 Layout design of proposed 7T latch with delay


127

The designed layout of proposed 7T delay latch as presented in figure 8.19 is used to extract the parasitic capacitances. The values of parasitic capacitance are given in table XXII. The Total numbers of parasitic capacitance are eight for this design, which are having value more than 1fF. DRC is performed to validate a high overall yield and reliability of the design. LVS check confirms that shorts, opens, component mismatches, and missing components are not found. Table XXII. Parasitic capacitance of proposed 7T latch with delay Parasitic Capacitance (F) Latch 7T latch with delay

Output capacitance

Total capacitance

1.08254e-016

4.919681e-16

Figure 8.20 Input-output waveform of proposed 7T latch with delay


128

The proposed 7T latch with delay is negative level triggered. As shown in figure 8.20, whenever clock is negative, the output changes with respect to data but remains constant as clock goes positive. The output remains unaffected even if clock is absent, thus the proposed latch is also static in nature. 8.1.6 Proposed 6-Transistor (6T) Latch

Figure 8.21 Schematic view of proposed 6T latch The proposed 6-transistors latch design [56] uses a pass transistor for the transmission of data through it. As shown in figure 8.21, the source of first pMOS transistor P1 is connected to the data input and this data will be available at the drain terminal only when the clock w ill be low. Since the pMOS transistor is weak zero transistor, so the small threshold loss is observed when data is zero. But overall performance of the device is almost unaffected because of the presence of the inverters. The transistor N1 passes the output according to the delayed version of the clock. Thus whenever clock is high, data is not passing through the transistor P1 but output is again feedback through the circuit and output remains same. Hence, this proposed clocked latch acts as a negative level triggered flip-flop. Whenever, clock is negative, the output changes with respect to data but remains constant as clock goes positive.


129

Figure 8.22 Layout design of proposed 6T latch

Table XXIII. Parasitic Capacitance of proposed 6T latch

Latch Proposed 6T

Parasitic Capacitance (F) Output capacitance

Total capacitance

1.2941e-016

5.47328e-16

The layout design for the proposed 6T latch is shown in figure 8.22. In the layout design of the proposed 6T latch, number of poly contacts is two and no poly and metal overlap takes place. The designed layout of proposed 6T latch is used to extract the parasitic capacitances. The total number of parasitic capacitances is six in proposed 6T design, which are having value more than 1fF. DRC is performed to validate a high overall yield


130

and reliability of the design. LVS check is performed to check shorts, opens, component mismatches, and missing components. Output and total parasitic capacitance are shown in table XXIII.

Figure 8.23 Input-output waveform of proposed 6T latch The proposed 6T latch is negative level triggered. Figure 8.23 shows, whenever clock is negative, output changes with respect to data but remains constant as clock goes positive. The output remains unaffected even if clock is absent; hence, the proposed latch is static in nature.


131

8.2 Comparison and Analysis

In this thesis, five designs of latches are proposed. Designs are compared along with the conventional design of 8 transistor latch. All comparison results are given in Appendix - C. All designs are simulated and analyzed in 65nm and 45nm technologies to

prove the technology independence of the proposed design. The designs are tested for power consumption, delay and PDP at various supply voltages, temperatures and frequencies. Average Power Consumption (APC) of the device increases with temperature as the carrier collision rate increases and the power is consumed in the form of thermal energy. The APC by the existing design and proposed designs at various temperatures o

o

(5 C to 75 C) is shown in figure 8.24. 1.60E ‐09 1.40E ‐09 1.20E ‐09 Existing 8T

1.00E ‐09

) t t a w 8.00E ‐10 ( C P A

8T 8T Delay 7T

6.00E ‐10

7T Delay 4.00E ‐10

6T

2.00E ‐10 0.00E+00 5

15

25

35

45

55

65

75

o

Temperature ( C)

Figure 8.24 APC at various t emperatures in 65nm technology


132

4.00E‐10

Existing 8T

3.50E‐10

8T

3.00E‐10

8T Delay 7T

2.50E‐10

) c e s ( y 2.00E‐10 a l e D

7T Delay 6T

1.50E‐10 1.00E‐10 5.00E‐11

0.00E+00 5

15

25

35

45

55

65

75

Temperature (oC)

Figure 8.25 Delay at various temperatures in 65nm technology Table XXIV. Power-delay product at various temperatures in 65nm technology Temp

PDP (watt-sec)

o

( C)

Existing 8T

8T

8T Delay

7T

7T Delay

6T

5

1.2889e-19

1.4766e-19

1.6100e-19

3.1421e-19

1.3828e-19

1.2200e-19

15

1.4928e-19

1.5760e-19

1.4900e-19

3.3191e-19

1.4451e-19

1.4100e-19

25

1.7253e-19

1.8793e-19

1.6800e-19

3.4672e-19

1.6670e-19

1.6600e-19

35

1.9835e-19

1.9940e-19

2.0800e-19

3.8845e-19

1.9237e-19

1.9000e-19

45

2.2172e-19

2.1652e-19

2.2800e-19

3.9263e-19

2.1324e-19

2.1000e-19

55

2.4217e-19

2.2106e-19

2.3500e-19

3.8224e-19

2.2307e-19

2.2000e-19

65

2.5705e-19

2.2729e-19

2.3300e-19

3.5395e-19

2.2932e-19

2.1200e-19

75

2.7843e-19

2.2496e-19

2.1800e-19

3.2689e-19

2.2577e-19

2.2800e-19


133

From figure 8.24, it can be seen that APC for 6T design is less when compared with other latch designs. In 6T latch, transistor count also decreases by two, hence area is reduced. So this design is preferable for low power device design. 7T latch design consumes more power than other designs but it also requires one less transistor than the conventional latch. So it is also preferred over existing one. The graph shown in figure 8.25 reveals that delay of all the proposed designs is remarkably reduced than the existing one. So the speed and performance of proposed designs proves to be better than existing design. As depicted in table XXIV, with increase in temperature the decrease in APC and significant decrement in delay results into reduced power-delay product (PDP) for the proposed 8T with delay, 7T with delay and 6T design. Hence the proposed latches prove its temperature sustainability over the existing 8T latch. 1.40E‐09

Existing 8T 8T

1.20E‐09

8T delay 1.00E‐09 7T ) 8.00E‐10 t t a w ( C P A 6.00E‐10

7T Delay 6T

4.00E‐10

2.00E‐10

0.00E+00 0.3

0.31

0.32

0.33

0.34

0.35

Voltage (volt)

Figure 8.26 APC at various supply voltages in 65nm technology


134

From figure 8.26, it is clear that all designs excluding 7T have almost comparable power consumption. 7T have largest power consumption so it is not as much suitable for ultra low power circuit as compared to other circuits. But due to its small area it can be preferred over existing 8T latch. 4.00E ‐10 Existing 8T 3.50E‐10

8T

3.00E‐10

8T Delay 7T

2.50E‐10

) c e s ( y2.00E‐10 a l e D

7T Delay 6T

1.50E‐10 1.00E‐10 5.00E‐11

0.00E+00 0.3

0.31

0.32

0.33

0.34

0.35

Voltage (volt)

Figure 8.27 Delay at various supply voltage in 65nm technology Table XXV. Power-delay product at various supply voltages in 65nm technology PDP (wat -sec) Supply Voltage (volt)

Existing 8T

.8362e-20 1.6798e-19

7T

7T ith Delay transistor

6T

. 984e-20

5.3530e-20 4.7963e-20

0.31

1.1385e-19 8.6196e-20 1.5561e-19 1.1895e-19

7.7714e-20 7.3041e-20

0.32

1.2788e-19 1.1282e-19 1.3448e-19 1.6279e-19

1.0969e-19 9.9312e-20

0.33

1.4525e-19 1.1507e-19 1.1024e-19 2.1604e-19

1.2023e-19 1.1945e-19

0.34

1.5970e-19 1.5712e-19 7.7435e-20 2. 501e-19

1.4879e-19 1.5393e-19

0.35

1.7253e-19 1.8793e-19 5.0499e-20 3. 672e-19

1.6670e-19 1.6572e-19

0.30

9.7465e-20

8T

8T ith Delay transistor


135

The supply voltage and the input voltage are kept always less than the threshold voltage, so that the devices should always operate in subthreshold region. Figure 8.27 shows that delay of all the proposed designs are lower than the existing 8T design. So all proposed designs are suitable for high performance circuit as compared to existing 8T design. The obtained results of PDP are shown in Table XXV. Similar results are obtained when the designs are compared using 45nm technology. Presenting the similar results in two different technologies shows the technology independent behavior of the designs. Thus all these designs are suitable to work at all CMOS technologies. 8.00E‐10

Existing 8T

7.00E‐10

8T 8T Delay

6.00E‐10

7T 5.00E‐10

) t t a w4.00E‐10 ( C P A

7T Delay 6T

3.00E‐10 2.00E‐10 1.00E‐10

0.00E+00 5

15

25

35 45 Temperature (oC)

55

65

75

Figure 8.28 APC at various t emperatures in 45nm technology As temperature increases then APC also increases. From the figure 8.28, it can be inferred that the APC is lowest for 6T design which is area efficient too. So according to this result the 6T design is best suitable for ultra low power consumption in respect of power consumption as well as area efficient.


136

Table XXVI. Delay at various temperatures in 45nm techno logy Temp (oC)

5

Delay (sec) Existing 8T

8T

8T Delay

7T

7T Delay

6T

3.2088e-010 7.9354e-011 9.5736e-008

6.3289e-011 2.6885e-010 5.0489e-011

15

3.0860e-010 9.7672e-011 5.8202e-008

8.4972e-011 1.0667e-010 5.0489e-011

25

2.9744e-010 1.0587e-010 4.3297e-008

9.9253e-011 3.2236e-011 7.3736e-011

35

2.8758e-010 1.0340e-010 3.0117e-008

1.0498e-010 9.1522e-012 9.4066e-011

45

2.7917e-010 9.0389e-011 2.5241e-008

1.0389e-010 3.3271e-011 1.0860e-010

55

2.7164e-010 7.1519e-011 2.1233e-008

9.2903e-011 4.3720e-011 1.1741e-010

65

2.6510e-010 4.4344e-011 1.8208e-008

7.4643e-011 4.0310e-011 1.1400e-010

75

2.6072e-010 1.1264e-011 1.4264e-008

4.8052e-011 2.4023e-011 9.8331e-011

Table XXVII. Power-delay product at various temperatures in 45nm technology PDP (watt-sec)

Temp (oC)

Existing T

8T

8T Delay

7T

7T Delay

5

3.4409e-20

7.5721e-21

1.0059e-17

6.3004e-21

2.4842e-20

4.7614e-21

15

3.1122e-20

1.0235e-20

6.8908e-18

1.0743e-20

1.0579e-20

4.7614e-21

25

3.9056e-20

1.3678e-20

6.3087e-18

1.6232e-20

4.0136e-21

7.2024e-21

35

4.9468e-20

1.856e-20

6.0313e-18

2.4396e-20

1.5155e-21

1.1618e-20

45

6.0381e-20

2.0823e-20

6.5296e-18

3.2684e-20

7.4426e-21

1.7729e-20

55

7.7116e-20

2.2176e-20

7.2020e-18

3.9026e-20

1.3225e-20

2.5977e-20

65

1.0273e-19

1.8558e-20

7.8752e-18

4.1121e-20

1.5669e-20

3.4239e-20

75

1.3999e-19

6.1882e-21

8.3459e-18

3.5119e-20

1.2537e-20

3.8388e-20

6T


137

From table XXVI, it is clear that delay introduced by proposed 6T design is lowest than all the designs. So this lower delay and low power consumption leads to low power delay product for proposed 6T design, as reflected from the table XXVII. Fro m the comparison presented in this table, it can be inferred that PDP and delay for proposed 6T design is lower than the existing one. This shows the superiority of 6Tdesign over other proposed designs. 2.50E‐10

Existing 8T 8T

2.00E‐10

8T Delay 7T

) s 1.50E‐10 t t a w ( C P 1.00E‐10 A

7T Delay 6T

5.00E‐11

0.00E+00 0.2

0.21 Voltage (volt)

0.22

Figure 8.29 APC at various supply voltages in 45nm technology 1.00E ‐09 Existing 8T 8T 8T Delay ) c e s ( y a l e D

1.00E ‐10

7T 7T Delay 6T

1.00E ‐11

1.00E ‐12 0.2

0.21 Voltage (volt)

0.22

Figure 8.30 Delay at various supply voltages in 45nm technology

Tanner EDA simulation Detailed

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