Study of 8086 Features of 8086: Data bus : 16 bit Address bus 20 bit . so, memory that can be addressed : 1 Mbytes ( 1048576 bytes exactly) Total no. of registers available for programmer :14 Addressing modes: 24 Clock rates : 8086 = 5 MHz , 8086-1 = 8 MHz , 8086 -2 = 10 MHz 40 DIP Technology : n channel MOSFET ( HMOS) Can operate in single or multi processor mode.
-
The architecture of 8086 supports a 16-bit ALU, a set of 16 – bit registers and provides segmented memory addressing capacity, a rich instruction set, powerful interrupt structure, prefetched instruction queue for overlapped fetching and execution . The complete architecture 8086 can be divided into two parts I) Bus Interface Unit (BIU) II) Execution Unit (EU) BUS INTERFACE UNIT :
-
It contains the ckt for physical address calculations and an instruction byte queue ( 6 bytes long). The bus interface is available for external interfacing of the devices. In other words, this unit is responsible for establishing communications with external devices and peripherals including memory via the address and data bus. BIU contains the following different parts : a) b) c) d)
Segment Registers Instruction byte queue. Address conversion Mechanism (Adder) Instruction Pointer (IP)
(a) SEGMENT REGISTERS :
-
The 8086 addresses segmented memory . The complete 1MB memory, which the 8086 is able to address, is divided into 16 logical segments. Each segment thus contains 64kb locations .. There are 4 segment registers : 1) Code segment register (CS) 2) Data segment register (DS) 3) Extra segment register (ES) 4) Stack segment register (SS)
-
The code segment register (CS) is used for addressing a memory location in the code segment of the memory where executable program is stored.
-
The data segment register points to the data segment of memory where the data (I/P / O/P) is stored.
-
The extra segment register (ES) refers to the segment which essentially is another data segment of memory. Thus extra segment also contains data.
-
The stack segment register (SS) is used for addressing stack segment of memory which is used to store stack data. The CPU uses stack for temporarily storing data. Such as return addresses, contents of registers before calling a subroutine.
(b) INSTRUCTION BYTE QUEUE :
-
The 8086 has 6 byte instruction queue.
-
It is first in first out structure. The instruction from queue is taken for decoding sequentially. Once a byte is decoded the queue is rearranged by pushing it out and queue status is checked for the possibility of next opcode fetch cycle. ( c ) ADDRESS CONVERSION MECHANISM (ADDER) : The segment register indicates the base address of a particular segment . Since the offset is a 16 bit nos, each segment can have a maximum of 64K locations. The BIU has an adder to perform this procedure for obtaining a physical address while addressing memory. It adds the segment address register depending upon whether the code, data or stack are to be accessed while the offset may be the contents of IP,BX,SI,DI,SP or an immediate 16 bit value, depending upon the addressing mode. It generates 20 bit address by shifting segment register 4 bits left & inserting 4 zero bits & and adds to it corresponding offset register contents. II ) EU The EU contains the following parts : a) General data registers. b) Pointers and index registers. c) Arithmetic and logic unit (ALU) d) Flag register. A) GENERAL DATA REGISTER : The register Ax, Bx, Cx, Dx, are the general purpose 16 bit registers. Ax is used as 16-bit accumulator. AL can be used as an 8 bit accumulator for 8 bit operations. 8
8 AH BH CH DH
AL BL CL DL
AX BX CX DX
General Data Registers. B) POINTERS AND INDEX REGISTERS : The EU contains pointers except IP. The BP (Base Pointer) ands SP (Stack Pointer) usually contains offsets within the (code, data) and (stack) segment respectively. The index registers are used as general purpose registers as well as for offset storage in case of indexed, based indexed and relative base indexed addressing modes. The register SI is generally used to store the offset of source data in data segment while register DI is used to store offset of destination in data or extra segment. The index registers are particular for string manipulations. C) ARITHMATIC AND LOGIC UNIT (ALU) : 8086 has 16 bit ALU, able to perform arithmetic and logic operations. The 16 bit flag register reflects the result of execution by ALU. D) FLAG REGISTER : 8086 has 16 bit flag register which is divided into 2 parts : (1) Condition or status Code. (2) M/C Control flag. The condition code flag register is lower byte of 16 bit flag register along with overflow flag, which is not present in 8085. This part of flag register of 8086 reflects the results of ALU. The control flag register is higher byte of flag register of 8086 affect operation of ALU. The control flag register is higher byte of flag. Register of 8086. It contains 3 flags viz. direction flag of 8086 (D), Interrupt flag (I) & trap flag (T) /* Flag register of 8086*/
15 X
14
13 X
12 X
11 X
10 0
09 D
08
07 I
06 T
05 S
04 Z
03 02 01 00 X Ac X
P
X
Cy
•
S : Sign flag : Set ,when result of comparison is negative. ( i.e. copy of MSB bit of result.)
•
Z-zero flag : set, when result of computation / comparison is zero.
•
P- Parity flag : Set, when lower byte of result contains even nos of 1’s.
•
C- carry flag : Set , when carry is there out of MSB in case of addition or borrow in case of subtraction.
•
T – Trap flag : When set , the processor enters the single step execution mode.
•
I – Interrupt flag : If it is set, external interrupt is recognized by CPU, otherwise ignored.
•
D-Direction flag : Used by string manipulation instructions. If ‘0’ then string is processed from lowest address to highest address, otherwise highest address to lowest address.
•
AC – Auxiliary carry flag : Set if there is a carry instructions from bit 3 during addition or borrow from bit 3 during subtraction.
•
O – Overflow flag : Set if overflow occurs, i.e if a result of signed operation is larger /smaller than size of destination register.
•
PIN CONFIGURATION OF 8086 :
The microprocessor 8086 is 16 bit CPU available in three clock rates. i.e 5,8 & 10 MHz. It is 40 pin DIP IC. The 8086 operates in single or multiprocessor configuration to achieve high performance. (Pins Common to max and minimum mode) HOLD (i/p)& HLDA(o/p) : Hold : if high, indicates to processor that another master is requesting the bus access. The processor after receiving HOLD request, issues back. Signal on HLDA pin. These are used with DMA controller. AD15 – AD0 (i/p o/p) : These are time multiplexed I/O address and data lines. During T1, address is available on bus and data is present on bus in T2, T3, T4 AD19 / S6 to AD16 / S3 : These are multiplexed address / status lines.
S4 0 0 1 11
S3 0 1 0 1
INDICATES Alternate data Stack Code or none data
~BHE / S7(O/P) : Bus high enable / status: BHE is used to indicate availability of valid data on the higher data bus D8- D15 . and status information is available during T2, T3, T4. BHE
A0
INDICATES
0 0 1 1
0 1 0 1
Whole word Upper byte or to odd address Lower byte or to even address none
~RD and ~WR (O/P): These are active low signals . They are used to perform memory or I/O read and write operations Ready (I/P): (Active high ) If it is low . the processor enters into wait states until assertes high. It is used to put delays so as to synchronize slower peripherals . INTR(I/P) and ~ INTA (I/P): INTR is level triggered i/p . It is sampled during last clock cycle of each instruction cycle to check if an interrupt is pening or not. ~INTA : The 8086 sends makes this signal low to indicate that it has accepted request . ~TEST (I/P): It is examined when WAIT instruction is executed. . Ie TEST pin is low , execution continues , else 8086 remains in idle state. MN/ ~MX (I/P): 0: maximum mode
1: minimum mode
NMI (I/P): It is edge triggered non maskable interrupt input . M/ ~IO(O/P) : 1: 8086 is doing memory related operations 0 : 8086 is doing IO related operations RESET : (I/P) : It clears PSW, IP, DS except CS . It sets CS to FFFFH. ALE : (O/P) Indicates that a valid address is available on AD15-AD8 during T1. DT/ ~R : (O/P) Dta tranmit / receive : Used to indicate the direction of data flow through transreceiver. ~DEN (O/P) : Data enable : Indicates a valid data is available on data lines. ~S2 , ~S1, ~S0 (O/P) : Status lines: ~S2 0 0 0 0 1 1 1 1
~S1 0 0 1 1 0 0 1 1
~S0 0 1 0 1 0 1 0 1
Indicates Interupt acknowledge I/O read I/O write Halt Code access Memory read Memory write Passive
~Lock (O/P) : When low , prevents other bus masters from taking control of system bus . QS1, QS0(O/P): Queue status: QS! 0 0 1 11
QS0 0 1 0 1
INDICATES No operation First byte of opcode from Queue Empty queue Subsequent byte from Queue
~RQ0 / ~GT0 and ~RQ1 / ~GT1 (I/O) : Request / grant Used by other local bus master to force 8086 to release local bus at the end of 8086’s current bus cycle. Addressing modes Implied - the data value/data address is implicitly associated with the instruction. e.g. STC, HALT, DAA Register - references the data in a register or in a register pair. E.g. MOV AX, BX Immediate - the data is provided in the instruction. E.G. MOV AX, 0F63DH
Direct - the instruction operand specifies the memory address where data is located.E.G. MOV AX, [0F36DH] Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers. 1)Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides. E.G. MOV AX, [BX] 2)Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. . MOV AX, [SI] 3)Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. E.G. MOV AX, [BX][SI] 4)Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides. . E.G. MOV AX, 73 [BX][SI] , . MOV AX, -1234[BP][SI]
Data Transfer Instructions General –purpose byte or word transfer instructions: MNEMONIC
DESCRIPTION
MOV
Copy byte or word from specified source to specified destination. PUSH Copy specified word to top of stack. POP Copy word from top of stack to specified location. XCHG Exchange bytes or exchange words. XLAT Translate a byte in AL using a table in memory. Simple input and output port transfer instructions: IN Copy a byte or word from specified port to accumulator. OUT Copy a byte or word from accumulator to specified port. Special address transfer instructions : LEA Load effective address of operand into specified register. LDS Load DS register and other specified register from memory. LES Load ES register and other specified register from memory. Flag transfer instructions : LAHF Load (copy to ) AH with the low byte of the flag register. SAHF Store (copy) AH register to low byte of flag register. PUSHF Copy flag register to top of stack. POPF Copy word at top of stack to flag register. ARITHMATIC INSTRUCTIONS Addition instructions: ADD Add specified byte to byte or specified word to word. ADC Add byte + byte+ carry flag or word + word + carry flag. INC Increment specified byte or specified word by 1. AAA ASCII adjust after addition. DAA Decimal (BCD) adjust after addition. Subtraction Instructions : SUB Subtract byte or word from word.
SBB DEC NEG CMP
Subtract byte and carry flag from byte or word . Decrement specified byte or specified word by 1. Negate – invert each bit of a specified byet or word and add 1 (form 2’s complement). Compare two specified bytes or two specified words.
AAS DAS
ASCII adjust after subtraction. Decimal (BCD) adjust after subtraction.
Multiplication instructions: MUL Multiply unsigned byte by byte or unsigned word by word. IMUL Multiply signed byte by byte or signed word by word. AAM ASCII adjust after multiplication. Division instructions: DIV Divide unsigned word by byte or unsigned double word by word. IDIV Divide signed word by byte or signed double word with sign bit of lower word. AAD ASCII adjust before division. CBW Fill upper word of double word with sign bit of lower word. BIT MANUPULATION INSTRUCTIONS Logical instructions : NOT Invert each bit of a byte or word. AND AND each bit in a byte or word with the corresponding bit in another byte or word. OR OR each bit in a byte or word with the corresponding bit in another byte or word. XOR Exclusive OR each bit in a byte or word with the corresponding bit in another byte or word. TEST AND operands to update flags, but don’t change operands. Shift instructions : SHL / SAL Shift bits of word or byte left, put zero (s) in LSB (s). SHR Shift bits of word or byte right, put zero (s) in MSB (s). SAR Shift bits of word or byte right, copy old MSB into new MSB. Rotate Instructions : ROL Rotate bits of byte or word left, MSB to LSB and to CF. ROR Rotate bits of byte or word right, LSB to MSB and to CF. RCL Rotate bits of byte or word left, MSB to CF and cF to LSB. RCR Rotate bits of byte or word right, LSB to CF and CF to MSB. STRING OPERATIONS A string is a series of bytes or a series of words in sequential memory locations. A string often consists of ASCII character codes. In the list, a “/ ” is used to separate different mnemonics for the same instruction. Use the mnemonic which most clearly describes the function of the instruction in a specific application. A “B” in a mnemonic is used to specifically indicate that a string of words is to be acted upon. REP An instruction prefix Repeat following instruction until CX = 0 REPE / REPZ An instruction prefix Repeat instruction until CX = 0 or zero flag ZF 1. REPNE / REPNZ An instruction prefix Repeat until CX = 0 or ZF = 1. MOVS / MOVSB/ MOVSW Move byte or word from one string to another. COMPS/COMPSB/CMPSW Compare two string bytes or two string words. SCAS/SCASB/SCASW LODS/LODSB/LODSW STOS/STOSB/STOSW
Scan a string. Compare a string byte with a byte in AL or a string word with a word in AX. Load string byte into AL or string word into AX. Store byte from AL or word from AX into string.
PROGRAM EXECUTION TRANSFER INSTRUCTIONS These instructions are used to tell the 8086 to start fetching instructions from some new address, rather than continuing in sequence. Unconditional transfer instructions : CALL Call a procedure (subprogram), save return address on stack.
RET JMP
Return from procedure to calling program. Go to specified address to get next instruction.
Conditional transfer instructions : A “/ ” is used to separate two mnemonics which represent the same instruction. Use the mnemonic which most clearly describes the decision condition in a specific program. These instructions are often used after a compare instruction. The terms below and above refer to unsigned binary numbers. Above means larger in magnitude. The terms greater than or less than refer to signed binary numbers. Greater than means more positive. JA/JNBE Jump if above /Jump if not below or equal. JAE/JNB Jump if above /Jump if not below JB/JNAE Jump if below /Jump if not above or equal. JBE/JNA Jump if below or equal /Jump if not above. JC Jump if carry flag CF = 1. JE/JZ Jump if equal/Jump if zero flag ZF = 1. JG/JNLE Jump if greater/Jump if not less than or equal. JGE/JNL Jump if greater than or equal/Jump if not less than. JLE/JNG Jump if less than or equal/Jump if not greater than. JNC Jump if no carry (CF = 0). JNE/JNZ Jump if not equal / Jump if not zero (ZF = 0). JNP / JPO Jump if not parity / Jump if parity odd (PF = 0). JNS Jump if not sign (sign flag SF = 0). JO Jump if overflow flag OF = 1. JP/JPE Jump if parity even (PF=1). JS Jump if sign (SF = 1). Iteration control instructions : These instructions can be used to execute a series of instructions some number of times. Here mnemonics separated by a “/ ” represent the same instruction. Use the one that best fits the specific application. LOOP Loop through a sequence of instructions until CX = 0. LOOPE/LOOPNZ Loop through a sequence of instructions until CX = 0. LOOPNE / LOOPNZ Loop through a sequence of instructions while ZF = 0 and CX ≠ 0. JCXZ Jump to specified address if CX = 0. Interrupt instructions : NT Interrupt program execution, call service procedure. INTO Interrupt program execution if OF = 1. IRET Return from interrupt service procedure to main program. PROCESSOR CONTROL INSTRUCTIONS Flag set/clear instructions : STC Set carry flag CF to 1. CLC Clear carry flag CF to 0. CMC Complement the state of the carry flag CF. STD Set direction flag DF to 1 (decrement string pointers). CLD Clear direction flag DF to 0. STI Set interrupt enable flag to 1 (enable INTR input). CLI Clear interrupt enable flag to 0 (disable INTR input). External hardware synchronization instructions : HLT Halt (do nothing) until interrupt or reset. WAIT Wait (do nothing) until signal on the TEST pin is low. ESC Escape to external coprocessor such as 8087 or 8089. LOCK An instruction prefix. Prevents another processor from taking the bus while the adjacent instruction executes. No operation instruction : NOP No action except fetch and decode. Pin diagram :
