soneview N1405 6-71-W2400-D03-GP.pdf

Preface

Notebook Computer W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/ W249BUQ Service Manual

P r e f a c e

I

Schematic Diagrams

Ap A p p end en d i x B : Sch Sc h emat em atii c Diagr Di agr ams am s This appendix has circuit diagrams of the W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/W249BUQ W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/W249BUQ note book’s PCB’s. The following table indicates indicates where to find the appropriate schematic schematic diagram. Di ag r am - Pag e

Di ag r am - Pag e

Di ag r am - Pag e

System Block Diagram Diagram - Page B - 2

HUDSON PCIE/ PCI/ PCI/ CLOCK/ FCH - Page B - 16

USB/ FAN/ TP/ MULTI CON - Page B - 30

ONTARIO MEM & PCIE I/F, I/F, AP - Page B - 3

HUDSON GPIO/ USB/ STRAP - Page B - 17

5VS/ 3.3VS/ 1.8VS/ 1.8VS/ 1.5VS/ 1.5VS/ 1.1VS - Page B - 31

ONTATIO DISPLAY/ CLK/ CLK/ MISC - Page B - 4

HUDSON SATA/ DEBUG DEBUG IO/ SPI - Page Page B - 18

POWER VDD3/ VDD5 VDD5 - Page B - 32

ONTARIO POWER & DECOUPLING DECOUPLING - Page B - 5

HUDSON POWER DECOUPLING DECOUPLING - Page B - 19

Power 1.5V/ 0.75 0.75 - Page B - 33

INAGUA DDR3 SO-DIMMS SO-DIMMS A - Page B - 6

POWERGOOD/ TPM - Page Page B - 20

Power 1.1V/ 1VS - Page B - 34

INAGUA DDR3 SO-DIMMS SO-DIMMS B - Page B - 7

LVDS, INVERTER INVERTER - Page B - 21

Power 1.8VS - Page Page B - 35

Robson S3 PCIE/ PCIE/ LVDS 1/6 - Page B - 8

HDMI/ CRT - Page B - 22

APU CORE/ NB CORE - Page B - 36

Robson S3 MAIN MAIN 2/6 - Page B - 9

CCD/ 3G - Page Page B - 23

VGA POWER POWER - Page B - 37

Robson S3 MEM MEM Interface 3/6 - Page B - 10

Card Reader/ LAN JMC261C - Page B - 24

CHARGER/ DC IN - Page B - 38

Robson S3 Straps Straps 4/6 - Page B - 11

MINI PCIE/ SATA SATA HDD/ ODD - Page B - 25

Click Board - Page Page B - 39

Robson S3 Power Power 5/6 - Page B - 12

AUDIO CODEC ALC261C ALC261C - Page B - 26

Audio Board/ USB USB - Page B - 40

Robson S3 Power Power 6/6 - Page B - 13

USB 3.0 VL800 VL800 - Page B - 27

Power Switch & LID Board - Page B - 41

Robson DDR3 MEM MEM CH-A - Page B - 14

KBC- ITE IT8518 - Page B - 28

Robson DDR3 MEM MEM CH-B - Page B - 15

LED/ MDC/ BT - Page B - 29

EXTERNAL ODD Board - Page B - 42

Table B - 1

Schematic Diagrams

Version Note The schematic diagrams in this chapter are based upon version 6-7P-W2405003. If your mainboard (or other boards) are a later version, please check with the Service Center for updated diagrams (if required).

B - 1

B . S c h e m a t i c D i a g r a m s

Schematic Diagrams

System Block Diagram W240BU/W250BUQ W240BU/W250BUQ/W2 /W250BAQ 50BAQ Sys tem B lock Diagram

CLICK BOARD 6-71-W2402-D01

POWER SWITCH BOARD POWER SWITCH+HOTKEY X 3 6-71-E51QS-D02

AT I ROBSO N (S3 TYPE)

AUDIO BOARD

PCIE*4

512MB DDR3

EXTERNAL ODD BOARD EXT. ODD 6-71-E51QN-D01

GPU POWER, VDDC

AMD FUSION APU Ontario FT1

MVDDQ,1.8V_REG,1.0V_REG 5V,3V,5VS,3.3VS 1.5VS,1.1VS

41 3-BALL 19 mm X19mm BGA SINGLE CHANNEL DDR3 DISPLAYPORT X2 DX11 IGP 4 X1 PCIE GEN2 GPP 1 X4 UM I-L INK GEN1 VGA DAC

USB+EARPHONE+EXT.MIC 6-71-W2408-D02

LCD CONNECTOR

1066MHz DDR3 / 1.5V

APU_CORE,NB_CORE DDRIII SO-DIMM2 SHEET 6 1.5V,0.75VS(VTT_MEM) DDRIII SO-DIMM1

CRT Connector

SHEET 5

TOUCH PAD

Sheet 1 of 41 System Block Diagram

1.8VS

USB PORT (USB4)

AMD HUDSON-M1 CLICK BOARD

MIC IN

HP OUT

INT SPK R

CHARGER,DC IN SHEET 38

605-BALL

SPI

23mmX23mmBGA TPM

(Reserve)

32.768 KHz

EC ITE 8518 128pins LQFP

LPC

14*14*1.6mm

INT. K/B

PCIE GEN1 I/F (4 x1) USB2.0(12) + 1.1 (2) SAT AII(3 PORTS) I N T. T. C L K G E N AZALIA HD AUDIO GB M AC SPII/F LPC I/F HW M ONITOR

33 MHz BIOS SPI

EC SMBUS THERMAL SENSOR W83L771AWG

SMART BATTERY AC-IN

1.1V, 1VS

UMI*4

HDMI Connector

s m a r g a i D c i t a m e h c S . B

VDD3,VDD5

SMART FAN

INT SPKER

Azalia Codec REALTEK ALC269

INT MIC

24 MHz AZALIA LINK PCIE

100 MHz

32.768KHz

US B 3 .0

USB2.0

480 Mbps

(Reserve)

(USB3)

(USB9)

Mini PCIE SOCKET (USB2)

(Optional)

3 G CA RD

WLAN

JMICRO JMC261C

LAN

CARD READER 25 MHz

RJ-4 5

SATA HDD

SATA ODD

SATA I/II 3.0Gb/s

B - 2 System System Block Diagr Diagram am

USB PORT USB PORT (USB0) (USB1)

Bluetooth CCD (USB6) (USB5)

7 IN 1 SOCKET

Schematic Diagrams

ONTARIO MEM & PCIE I/F, AP ONTARIO MEM & PCIE I/F, AP

5 ,6

M E M_ A D DR [1 5 :0 ] MEM_A DD R0

M EM _A DD R1 M EM _A DD R2 M EM _A DD R3 M EM _A DD R4 M EM _A DD R5 M EM _A DD R6 M EM _A DD R7 M EM _A DD R8 M EM _A DD R9 M EM _A DD R1 0 M EM _A DD R1 1 M EM _A DD R1 2 M EM _A DD R1 3 M EM _A DD R1 4 M EM _A DD R1 5

7 1 R

H1 9 J17 H1 8 H1 7 G1 7 H1 5 G1 8 F19 E1 9 T19 F17 E1 8 W17 E1 6 G1 5

M E M _D A T A[6 3 :0 ] 5 ,6

U1 E M_AD D0 M_AD D1 M_AD D2

ONT ARIO 2.0) 2 ( .0) PA R T1 O F5 T1

M_D AT A0 M_D AT A1 M_D AT A2

M_AD D3

M_D AT A3

M_AD D4

M_D AT A4

M_AD D5

M_D AT A5

M_AD D6

M_D AT A6

M_AD D7

M_D AT A7

5 ,6 M EM _B ANK 0 5 ,6 M EM _B ANK 1 5 ,6 M EM _B ANK 2 M E M_ D M[7 :0 ]

5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6 5 ,6

MEM _ DQ S_ H0 MEM _ DQ S_ L 0 MEM _ DQ S_ H1 MEM _ DQ S_ L 1 MEM _ DQ S_ H2 MEM _ DQ S_ L 2 MEM _ DQ S_ H3 MEM _ DQ S_ L 3 MEM _ DQ S_ H4 MEM _ DQ S_ L 4 MEM _ DQ S_ H5 MEM _ DQ S_ L 5 MEM _ DQ S_ H6 MEM _ DQ S_ L 6 MEM _ DQ S_ H7 MEM _ DQ S_ L 7

5 5 5 5 6 6 6 6

M EM_ C LK _H 0 M EM_ C LK _L 0 M EM_ C LK _H 1 M EM_ C LK _L 1 M EM_ C LK _H 2 M EM_ C LK _L 2 M EM_ C LK _H 3 M EM_ C LK _L 3

5 ,6 M EM_ R ESE T # 5 ,6 M EM_ EV E NT # 5, 6 5, 6

ME M _ CK E 0 ME M _ CK E 1

R1 8 T18 F16 M M M M M M M M

EM EM EM EM EM EM EM EM

_D _D _D _D _D _D _D _D

M0 M1 M2 M3 M4 M5 M6 M7

D1 5 B1 9 D2 1 H2 2 P2 3 V2 3 AB2 0 AA1 6 A1 6 B1 6 B2 0 A2 0 E2 3 E2 2 J22 J23 R2 2 P2 2 W22 V2 2 AC2 0 AC2 1 AB1 6 AC1 6

M_AD D9

M_D AT A8 M_D AT A9 M_D ATA 10

M_AD D12 M_AD D13

M_D ATA 11 M_D ATA 12

M_AD D14

M_D ATA 13

M_AD D15

M_D ATA 14

M_BA NK0 M_BA NK1 M_BA NK2


M_DM0


M_DM1

M_D ATA 20

M_DM2 M_DM3


M_DM4

M_D ATA 23

M_DM5 M_DM6

M_D ATA 24

M_DM7


M_DQ S_H 0

M_D ATA 27

M_DQ S_L 0

M_D ATA 28

M_DQ S_H 1

M_D ATA 29

M_DQ S_L 1

M_D ATA 30

M_DQ S_H 2 M_DQ S_L 2

M_D ATA 31

M_DQ S_H 3 M_DQ S_L 3 M_DQ S_H 4 M_DQ S_L 4 M_DQ S_H 5 M_DQ S_L 5

F / I Y R O M E M


M_D ATA 32 M_D ATA 33 M_D ATA 34 M_D ATA 35 M_D ATA 36 M_D ATA 37 M_D ATA 38 M_D ATA 39



M1 7 M1 6 M1 9 M1 8 N1 8 N1 9 L18 L17

M_C LK_H 0 M_C LK_L0


M_C LK_H 1

M_D ATA 44

M_C LK_L1 M_C LK_H 2


M_C LK_L2

M_D ATA 47

M_C LK_H 3 M_C LK_L3


L23 N1 7

M_RE SET _L

M_D ATA 50

M_EV ENT _L

M_D ATA 51

F15 E1 5

M_CK E0

M_D ATA 54

M_CK E1

M_D ATA 55


M_D ATA 56

5 D IMM 0 _O DT 0 5 D IMM 0 _O DT 1 6 D IMM 1 _O DT 0 6 D IMM 1 _O DT 1 5 D IMM 0 _C S # 0 5 D IMM 0 _C S # 1 6 D IMM 1 _C S # 0 6 D IMM 1 _C S # 1 5, 6 5, 6 5, 6

ME M _ RA S # ME M _ CA S # ME M _ W E #

W19 V1 5 U1 9 W15 T17 W16 U1 7 V1 6 U1 8 V1 9 V1 7

MEM _ DA T A0 MEM _ DA T A1 MEM _ DA T A2 MEM _ DA T A3 MEM _ DA T A4 MEM _ DA T A5 MEM _ DA T A6 MEM _ DA T A7

C18 A 19 B 21 D20 A 18 B 18 A 21 C20

MEM _ DA T A8 MEM _ DA T A9 MEM _ DA T A1 0 MEM _ DA T A1 1 MEM _ DA T A1 2 MEM _ DA T A1 3 MEM _ DA T A1 4 MEM _ DA T A1 5

C23 D23 F 23 F 22 C22 D22 F 20 F 21

MEM _ DA T A1 6 MEM _ DA T A1 7 MEM _ DA T A1 8 MEM _ DA T A1 9 MEM _ DA T A2 0 MEM _ DA T A2 1 MEM _ DA T A2 2 MEM _ DA T A2 3

H21 H23 K 22 K 21 G23 H20 K 20 K 23


N23 P 21 T20 T23 M20 P 20 R23 T22


M_AD D8

M_AD D10 M_AD D11

M_D ATA 15

5 ,6

B 14 A 15 A 17 D18 A 14 C14 C16 D16

M0_O DT0


M0_O DT1

M_D ATA 59

M1_O DT0

M_D ATA 60

M1_O DT1


M0_CS _L0

M_D ATA 63

V 20 V 21 Y23 Y22 T21 U23 W 23 Y21


Y20 A B2 2 A C1 9 A A1 8 A A2 3 A A2 0 A B1 9 Y18


A C1 7 Y16 A B1 4 A C1 4 A C1 8 A B1 8 A B1 5 A C1 5


M0_CS _L1 M1_CS _L0 M1_CS _L1

M_V RE F

For W250BAQ U1 A VGA _ R XP0 VGA _ R XN0

7 7

VGA _ R XP1 VGA _ R XN1

7 7

VG A_ RXP2 VG A_ RXN 2

7 7

VG A_ RXP3 VG A_ RXN 3 ON _Z V DD

1 VS R2

M_WE_L

M_Z VDD IO_ME M_S

R 6

P _GPP_ RXP 2

Y4 Y3

P _GPP_ RXP 3

A A1 0 Y1 0

P ART 2O F 5

P_GPP _TX P1

P _GPP_ RXN 1

P_GPP _TX N1 P_GPP _TX P2

F / I E I C P

P _GPP_ RXN 2

P _GPP_ RXN 3 P _ZV DD _10

P_GPP _TX N2 P_GPP _TX P3 P_GPP _TX N3 P_ ZVS S

1 5 C _U MI_ P _ R X 2 1 5 C _U MI_ N _ RX 2

P _UMI_RX P0

AB 6 AC6

C1 C2

* 0. u1 _1 0V_ X7R _ 40 * 0. u1 _1 0V_ X7R _ 40

V G A_ TXP0 7 V G A_ TXN 0 7

AB 3 AC3

C3 C4

* 0. u1 _1 0V_ X7R _ 40 * 0. u1 _1 0V_ X7R _ 40

V G A_ TXP1 7 V G A_ TXN 1 7

Y1 Y2

C5 C6

* 0. u1 _1 0V_ X7R _ 40 * 0. u1 _1 0V_ X7R _ 40

V G A_ T XP2 7 V G A_ T XN2 7

V3 V4

C7 C8

* 0. u1 _1 0V_ X7R _ 40 * 0. u1 _1 0V_ X7R _ 40

V G A_ T XP3 7 V G A_ T XN3 7

AA 1 4

ON _ Z V SS

R 1

Sheet 2 of 41 ONTARIO MEM & PCIE I/F, AP

1 .2 7K _ 1 % _ 0 4

P _UMI_RX P2

A C7 AB 7

P _UMI_RX P3

1 5 C _U MI_ P _ R X 3 1 5 C _U MI_ N _ RX 3

P _UMI_TX N0

AB 1 2 AC1 2

C9 C1 0

0 .1 u_ 10V _ X7 R_ 04 0 .1 u _ 10 V _ X7 R_ 0 4

C_ U MI_ P _ T X0 1 5 C_ U MI_ N _ TX0 1 5

P _UMI_TX P1 P _UMI_TX N1

AC1 1 AB 1 1

C1 1 C1 2

0 .1 u _ 10 V _ X7 R_ 0 4 0 .1 u _ 10 V _ X7 R_ 0 4

C_ U MI_ P _ T X1 1 5 C_ U MI_ N _ TX1 1 5

AA 8 Y8

C1 3 C1 4

0 .1 u _ 10 V _ X7 R_ 0 4 0 .1 u _ 10 V _ X7 R_ 0 4

C_ U MI_ P _ T X2 1 5 C_ U MI_ N _ TX2 1 5

AB 8 AC8

C1 5 C1 6

0 .1 u _ 10 V _ X7 R_ 0 4 0 .1 u _ 10V _ X 7 R_ 0 4

C_ U MI_ P _ T X3 1 5 C_ U MI_ N _ TX3 1 5

P _UMI_TX P0

P _UMI_RX N0

P _UMI_RX P1 P _UMI_RX N1

A B1 0 A C1 0

F / I I

M U

P _UMI_RX N2

P _UMI_TX P2 P _UMI_TX N2 P _UMI_TX P3

P _UMI_RX N3

P _UMI_TX N3

O NT AR IO_ AP U

ROUTE A-LINKDIFF PAIR@ 85 OHM +/-10% C8 4 2

C 84 3

C844

1 0 u_ 6 .3 V _ X 5 R_ 0 6 0 .1u _ 1 0 V_ X7R _ 04 1 0 0 0 p_ 5 0 V _ X 7R _ 0 4

1 .5 V

VT T _M EM

R 67 8 1 K_ 1 % _0 4

Analog Thermal Sensor 3. 3V

* 0 _ 04 0 _ 04

3 9 . 2 _1 % _ 0 4

2

R 68 1 1 K_ 1 % _0 4

3

C 3 65 0 .1 u _ 10 V_ X5 R_ 0 4

O N TA R IO _A PU

Note: O penthesodlermaskfor Vias onMem interface a ce

P _GPP_ RXP 1

AA 1 AA 2

A A1 2 Y1 2

1 5 C _U MI_ P _ R X 1 1 5 C _U MI_ N _ RX 1

M_CA S_L

M 2 2 M E M _Z VDD IO

P_GPP _TX P0 P_GPP _TX N0 ON TAR IO(2.0)

AB 4 A C4

Y1 4

1 .5 V

M_RA S_L

P _GPP_ RXP 0 P _GPP_ RXN 0

2 K _ 1% _ 0 4

1 5 C _U MI_ P _ R X 0 1 5 C _U MI_ N _ RX 0

R 6 79 R 68 0

M23

AA 6 Y6

7 7

Q1 5 VC C

OU T

G ND G 7 11 ST 9 U

1

1:2 (4mils:8mils)

0 .1u _ 1 0 V_ X 5R _ 0 4

R6 connectionto VDDIO_SUSshould be directly tothe planewithout along trace

T HE RM _ VOL T 2 7

C3 6 4

PLACE NEAR U1

1

3

2

ONTAR ONTARIO IO MEM MEM & PCIE PCIE I/F, I/F, AP B - 3


Schematic Diagrams

ONTATIO DISPLAY/ CLK/ MISC ONTARIO DISPLAY/CLK/MISC

1 .8 V S R 11 R 12

1K_04 1K_04

C P U_ S V C C P U_ S V D

R 14

3 0 0_ 1 % _ 0 4

A PU _ P W R G D

U1B 8 A

3 .3 V

3 .3 V S

R1 5 R2 2 R1 7 R1 9 R2 4 R2 0

*1 K _0 4 1K _ 04 1K _ 04 1K _ 04 1K _ 04 1K _ 04

A P U _ TH E R MT R IP # A P U _ TA L ERT # P RO C HO T # A P U _ S IC A P U _ S ID

HDMI 17


R2 5

S B_ P RO C HO T #

H DM IB_ D 2B P H DM IB_ D 2B N

21 21


21 21


21 21

P R OC H OT #

0_ 0 4

21 21

B9 A9

H D MI B _ C L K B P H D MI B _ C L K B N

20 20

L VDS -L 2P L VDS -L 2N

20 20


20 20


LVDS

R 13 3 0 0_ 1 % _ 0 4 L DT _ R S T #

Sheet 3 of 41 ONTATIO DISPLAY/ CLK/ MISC

C 84 0 0 .1 u _1 6 V _ Y 5 V _ 0 4

20 20

L V D S -L CL K P L V D S -L CL K N

15 15

A P U _C L KP A P U _C L KN

15 15

DIS P _ CL K P DIS P _ CL K N

35 35

CP U_ S VC C PU _ S VD

16 16 L D T RS T_ R L D T P W R GD _ R

C21

15 1 5, 35

A1 0 B1 0

TD P1 _TX P3

D6 C6

15

C22

D8 C8 V2 V1 D2 D1

A PU _S IC A PU _S ID

R 35 R 36

P3 P4 T3 T4

0_ 04 0_04

L DT R ST _ R L DT PW RG D_ R

0_04

PR OC HO T # AP U _ TH E R MT R IP#

U1 U2 T2

R38

N2 N1 P1 P2 M4 M3 M1

AP U _ TD I AP U _ TD O AP U _ TC K AP U _ TM S AP U _ TR S T # DB RD Y DB RE Q # 35

CP U _ VD DN B _ RU N _ F B_ H 3 5 C PU _V DD 0 _ RU N_ F B _ H

R 4 5 R 4 6

F4 * 1 0 m i l _ s h or t _ 04 VD DC R _ N B_ S EN S E * 1 0 m i l _ s h or t _ 04 VD DC R_ C PU _S EN S E G 1 V D DIO _ S U S _ S E N SE F 3

35 35

R 4 8 R 4 9

* 1 0 m i l _ s h or t _ 04 VS S _ S E NS E * 1 0 m i l _ s h or t _ 04

C PU _V DD 0 _ RU N_ F B _ L C PU _V DD N B _ RU N_ F B _ L

1 T R O P Y A L P S I D

TD P1 _TX N2

U44 1

5

DP_ BLO N

H1

TD P1_ AU XP

B2 C2

T DP 1_H PD

LT DP 0_TX P0

LTD P0_ AU XP

LT DP 0_TX N0

LTD P0_ AU XN

LT DP 0_TX P1

LT DP 0_H PD

0 T R O P Y A L P S I D

LT DP 0_TX N1

LT DP 0_TX P2 LT DP 0_TX N2

LT DP 0_TX P3

DAC _R ED D AC_ RE DB D AC _GRE EN DA C_G R EE NB D AC _BL UE

LT DP 0_TX N3

DA C_B LU EB

C A D A G V

C LK IN _H C LK IN _L

K L C

D I SP _CLK I N_H D I SP _CLK I N_L

2 G 2 H

D P_D IG O N DP _VA RY _BL

TD P1_ AU XN

TD P1 _TX N3

DA C_H SY NC DA C_V SY NC

D AC _SC L DAC _S DA

F1 B4 W11 V5

S VC

D AC_ ZV SS

SV D

R E S

SIC SI D

T ES T4 T ES T5 T ES T6 T ES T14

RE SE T_L

T ES T15

PW RO K

T ES T16 T ES T17

L R T C

PR O CH O T_L TH ER MTR I P _L

T ES T18 T ES T19

AL ER T_L

T S E T

TD I TD O T CK

TE ST 25_H T ES T25_L TE ST 28_H T ES T28_L T ES T31

G A T J

TMS TR ST _L

TE ST 33_H T ES T33_L

DB RD Y

TE ST 34_H

DB RE Q _L

T ES T34_L T ES T35

VD DC R_N B_ SE NS E

T ES T36

VD DC R_C PU _S EN SE

ON D P_ CA LR

R 21

1 5 0 _ 1% _ 0 4

ON _ B L O N ON _ D IGO N ON _ V A R Y

R 16 R 5 98

0_04 0 _04

HD MI_ D D C_ C LK HD MI_ D D C_ D A T A

D3 C1 2 D1 3 A1 2 B1 2 A1 3 B1 3

P O R T C_ H P D LV DS _ D D C _ C LK LV DS _ D D C _ D A T A R 60 * 10 0 K _ 0 4 R 62 * 10 0 K _ 0 4

R 27

1 5 0 _1 % _ 0 4

R 28

1 5 0 _1 % _ 0 4

R 29

T ES T37

D A C _R E D

D A C_ B LU E 2 1

1 5 0 _1 % _ 0 4 DA C_ H SY NC 2 1 DA C_ VS Y N C 21

F2 D4 D1 2

DA C _ RS E T

R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M2 1 J1 8 J1 9 U1 5 T1 5 H4 N5 R5

DA C_ D DC A C L K 2 1 DAC _ DD C A DA T A 2 1

A P U _T H ER MD A A P U _T H ER MD C

R3 1 R3 2

A P U _B P 1 _ T ST UPD _ US CL K 1

*0 _ 0 4 *0 _ 0 4

R 58

A P U _T E ST 1 8_ PL L T ES T 1 A P U _T E ST 1 9_ PL L T ES T 0 A P U _T E ST 2 5_ H _ B Y P A SS C L K A P U _T E ST 2 5_ L _ B Y P AS S CL K

A P U _T E ST 3 3_ H _ M_ C L KT S T _ H A P U _T E ST 3 3_ L _ M _C L K T ST _ L

1 K _0 4 1 K _0 4 5 1 0 _ 1 % _ 04 5 1 0 _ 1 % _ 04

* 1K_04

C 23 C 24

0 . 1u _1 6V _ Y 5V _ 04 0 . 1u _1 6V _ Y 5V _ 04

A P U _T E ST 3 5 A P U _T E ST 3 6

R 44

T ES T38 RS VD _1 RS VD _2 RS VD _3

4

A PU _ P W R G D_ B U F R 5 4

* 1K_04

D MAA CT IV E_L

K3 T1

ON _ D MA A CT IV E #

R 50

0_04

1. 8V S

1 .8 VS

R59 1K_04 A PU _ T RS T # R 6 5 R 66 R 67 R68

* * * *

0 _0 4 H DT _ T RS T # 1 0K _ 04 1 0K _ 04 1 0K _ 04

H DT + H EA D E R / P L AC E O N T O P

1 3 5 7 9 11 13 15 17 19

J1 CP U_ VD DIO

C PU _TC K

G ND

CP U_T MS

G ND G ND

CP U_ TD I CP U_T DO

CP U_ TR ST_ L

CP U_P WRO K _BU F

CP U_ DB RDY 3 CP U_ DB RDY 2

C PU _R ST_ L_BU F C PU _DB RD Y0

CP U_ DB RDY 1

CP U_D BR EQ _L

G ND

CP U_ PLLT ES T0

CP U_ VD DIO

CP U_ PLLT ES T1

* HD R 10 X2 - B LU E - VE R T ICAL P L UG

B - 4 ONTATIO DISPLAY/ CLK/ MISC

5 1 _ 04 5 1 _ 04

A L LO W _ L D T ST P 1 5

R5 1

Reserve 3

R 42 R 43

* 1K 0_ 4

O NT AR IO (2.0)

* 74 A H C 1 G 0 8 G W

2

1 6 ,17 ,2 7 1 6 ,17 ,2 7

VS S_ SEN SE

1. 8V S 5

AP U _ SIC AP U _ SID

1. 8V S

R5 6

R5 2

1 .8 V S R 53

0_04 0_04

S MD _ CP U_ T HE RM S MC _ CP U_ T HE RM

1 K _0 4

R 37 R 39 R 40 R 41

3

U45 1

R 33 R 34

4 9 9 _1 % _ 0 4

1K_04 1K_04 1K_04 L DT _ R ST # _ BUF

2 1

D A C_ G R E E N 2 1

E1 E2

ON T A R IO_ A P U

4

1 0 0 K _0 4 1 0 0 K _0 4 1 0 0 K _0 4

2 1

PA RT 3 OF 5

* 74 A H C 1 G 0 8 G W

R 5 91 R 5 92 R 5 93

LV DS _D D C_ C LK 2 0 LV DS _ D D C_ D A T A 2 0 5V S

2

A P U_ P W R GD

O N_ BL O N O N_ D IGO N O N_ VA R Y

HD MI_ D D C_ C LK 2 1 HD MI_ D D C _ D A T A 2 1

C1 A3 B3

BLO N 20 N B _ EN A V D D 2 0

VD DIO _MEM_S _S ENS E

1. 8V S

L DT _ R S T #

C S I M P D

R30 J1 J2

PRO C HO T #

1 6 CP U _ T HE RM T RIP # 1 7 ,2 7 AP U_ T A L E R T #

* 1 50 p F _ N P O _ 50 V_ 0 4 0 2* 1 5 0p F _ N P O _ 50 V _0 4 0 2

A6 B6

A P U_ S IC A P U_ S ID

L D T_ R S T # A P U_ P W RG D

L D T _R S T # A P U _P W R GD

TD P1 _TX P1 TD P1 _TX N1

TD P1 _TX P2

1 .8 V S

DP_ ZV SS

TD P1 _TX N0

D1 0 C1 0

B5 A5

3 H

ANALO G/DISPLAY/MISC TD P1 _TX P0

B8

1 .8 V S

2 4 6 8 10 12 14 16 18 20

A PU _ T CK R6 1 A PU _ T MS R6 3 A PU _ T DI R6 4 A PU _ T DO A PU _ P W R G D_ B U F L DT _ R ST # _B UF D B RD Y D B RE Q# R 69 J 1 08 _ P L L T ST 0 R 7 0 J 1 08 _ P L L T S T 1 R7 1

1 K_ 0 4 1 K_ 0 4 1 K_ 0 4

3 0 0_ 1 % _ 0 4 *0 _ 0 4 *0 _ 0 4

AP U _ T E S T 1 9 _P L LT E S T 0 A PU _ T E S T 1 8 _P L LT E S T 1

1 .8 V S

Schematic Diagrams

ONTARIO POWER & DECOUPLING ONTARIO POWER & DECOUPLING 1 .8 V S

VD DC R _C P U U 1C E5 E6 F5 F7 G6 G8 H5 H7 J6 J8 L7 M6 M8 N7 R8

VD DC R _N B

E8 E11 E13 F9 F12 G1 1 G1 3 H9 H1 2 K11 K13 L10 L12 L14 M1 1 M1 2 M1 3 N1 0 N1 2 N1 4 P11 P13

1 .5 V

C30

V DD CR _C PU _1

VD D_1 8_1

V DD CR _C PU _2

VD D_1 8_2

V DD CR _C PU _3

VD D_1 8_3

V DD CR _C PU _4

VD D_1 8_4

V DD CR _C PU _5

VD D_1 8_5

V DD CR _C PU _6

VD D_1 8_6

V DD CR _C PU _7

VD D_1 8_7

C 26

C27

C 28

C3 1

U1D A7 B7 B1 1 B1 7 B2 2 C4 D5 D7 D9 D1 1 D1 4 B1 5 D1 7 D1 9 E7 E9 E1 2 E2 0 F8 F11 F13 G4 G5 G7 G9 G1 2 G2 0 G2 2 H6 H1 1 H1 3 J4 J5 J7 J20 K1 0 K1 4 L4 L6 L8 L11 L13 L20 L22 M7 N4 N6 N8 N1 1

10 u _ 6 .3 V _ X5 R_ 0 6 1 u _ 6 .3 V _ X 5 R_ 0 4 1 u_ 6 .3 V _ X 5 R _ 04 1 u_ 6 .3 V_ X 5 R _ 04 * 1 u _6 .3 V _X 5 R _ 0 4 0. 1u _ 1 0 V_ X 5 R_ 0 4

C869

C 87 1

C870

V DD CR _C PU _8

*1 0 u _ 6 .3 V _ X5R _ 0 6 *1 0 u _ 6 .3 V _ X 5R _ 0 6 * 1 0u _ 6 .3 V _ X 5 R _0 6

V DD CR _C PU _9 V DD CR _C PU _10 V DD CR _C PU _11 V DD CR _C PU _12 V DD CR _C PU _13 V DD CR _C PU _14 V DD CR _C PU _15

V D DA N _ 1 8 _ DA C

V DD CR _N B_1

V DD _18_D AC

W 9

1 .8 VS

R 73

0 _0 4

V DD CR _N B_2 V DD CR _N B_3 V DD CR _N B_4 V DD CR _N B_5

C872

ON TA RIO ( 2.0 ) P A R T 4O F5

C 32

C33

1 0 u _ 6 .3 V_ X 5R _ 0 6 *1 0 u _ 6 .3 V _ X5R _ 0 6 1 u _ 6 .3 V _ X 5 R_ 0 4

V DD CR _N B_6 V DD CR _N B_7 V DD CR _N B_8 V DD CR _N B_9 V DD CR _N B_11 V DD CR _N B_12 V DD CR _N B_13 V DD CR _N B_14 V DD CR _N B_15

1V S

V DD P L _ 1 0

V DD CR _N B_10

R E W O P

V DD PL _10

U11

L63

C34

C35

.

HC B 1 6 0 8 K F -1 2 1 T 2 5 C 36

V DD CR _N B_16

1 0u _ 6 .3 V _ X 5 R _0 6 0 .1 u _ 1 0 V_ X 5 R_ 0 4 1 u _ 6. 3V _ X5 R _ 0 4

V DD CR _N B_17 V DD CR _N B_18 V DD CR _N B_19 V DD CR _N B_20

1VS

V DD CR _N B_21 V DD CR _N B_22

VD D_1 0_1 VD D_1 0_2

G1 6 G1 9 E17 J16 L16 L19 N1 6 R1 6 R1 9 W18 U1 6

U8 W 8 U6 U9 W 6 T7 V7

C29

VD D_1 0_3 V DD I O_MEM_S _1

VD D_1 0_4

U13 W 13 V 12 T12 C37

V DD I O_MEM_S _2

C38

C 39

C4 0

C41

C42

V DD I O_MEM_S _3

1 0u _ 6 .3 V_ X 5 R _0 6 1 u _ 6 .3 V _ X5 R_ 0 4 0 .1 u _1 0 V _ X 5 R _ 04 1 0 u _ 6 .3 V _ X5 R _ 0 6 1 u _ 6 .3 V _ X 5 R_ 0 4 0 .1 u _ 1 0 V_ X 5 R_ 0 4

V DD I O_MEM_S _4 V DD I O_MEM_S _5 V DD I O_MEM_S _6 V DD I O_MEM_S _7 V DD I O_MEM_S _8

3 .3 V S

V DD I O_MEM_S _9

C8 7 3

C874

V SS _1 V SS _2

O N TA RI O ( 2 .0) P A RT5 O F5

VS S_50 VS S_51

V SS _3

VS S_52

V SS _4

VS S_53

V SS _5

VS S_54

V SS _6

VS S_55

V SS _7

VS S_56

V SS _8

VS S_57

V SS _9

VS S_58

V SS _10

VS S_59

V SS _11

VS S_60

V SS _12

VS S_61

V SS _13

VS S_62

V SS _14 V SS _15

VS S_63 VS S_64

V SS _16

VS S_65

V SS _17

VS S_66

V SS _18

VS S_67

V SS _19

VS S_68

V SS _20

VS S_69

V SS _21

VS S_70

V SS _22

VS S_71

V SS _23

VS S_72

V SS _24

VS S_73

V SS _25

VS S_74

D N U O R G

V SS _26 V SS _27 V SS _28 V SS _29

VS S_75 VS S_76 VS S_77 VS S_78

V SS _30

VS S_79

V SS _31

VS S_80

V SS _32

VS S_81

V SS _33

VS S_82

V SS _34

VS S_83

V SS _35

VS S_84

V SS _36

VS S_85

V SS _37

VS S_86

V SS _38

VS S_87

V SS _39

VS S_88

V SS _40

VS S_89

V SS _41

VS S_90

V SS _42

VS S_91

V SS _43

VS S_92

V SS _44

VS S_93

V SS _45

VS S_94

V SS _46 V SS _47

VS S_95 VS S_96

V SS _48

VS S_97

V SS _49

V SS BG _D AC

N1 3 N2 0 N2 2 P1 0 P1 4 R4 R7 R2 0 T6 T9 T11 T13 U4 U5 U7 U1 2 U2 0 U2 2 V8 V9 V1 1 V1 3 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y1 1 Y1 3 Y1 5 Y1 7 Y1 9 AA 4 AA 2 2 AB 2 AB 5 AB 9 AB 1 3 AB 1 7 AB 2 1 AC 5 AC 9 AC 1 3 A1 1

Sheet 4 of 41 ONTARIO POWER & DECOUPLING

C875

V DD I O_MEM_S _10 V DD I O_MEM_S _11

V DD _33

A4

O NT A RI O _ A P U

*1 0 u _ 6 .3 V _ X5 R_ 0 6 * 1 0 u _6 .3 V _X 5 R _ 0 6 *1 0 u _ 6 .3 V _ X 5R _ 0 6

O N TA RIO _ AP U

C43

V D D CR _ CP U

1 u _ 6 .3 V _ X5 R_ 0 4 1 .5 V

C44

C 45

C4 6

C47

C48

C 49

C5 0

1 0 u _ 6 .3 V _ X 5 R_ 0 6 1 0 u _6 .3 V _X 5 R _ 0 6 1 0 u _ 6 .3 V _ X5 R_ 0 6 1 0 u _6 .3 V _X 5 R _ 0 6 1 0 u _ 6 .3 V _ X 5R _ 0 6 1 0u _ 6 .3 V_ X 5 R _0 6 1 0 u _ 6 .3 V _ X 5R _ 0 6

C5 1

C52

C5 3

C54

10 u _ 6 .3 V _ X 5 R_ 0 6 *2 2 u _ 6 .3 V _ X 5 R_ 0 8 1 0 u _ 6 .3 V _ X 5 R_ 0 6 *2 2 u _ 6 .3 V _ X5R _ 0 8

C55

C 56

C5 7

C58

C59

C 60

C6 1

C62

C63

1 u _ 6 .3 V _ X5 R _ 0 4 1 u _ 6. 3V _ X5 R _ 0 4 0 .1 u _ 10 V _X 5 R _ 0 4 0. 1u _ 1 0 V _ X5 R_ 0 4 0. 1u _ 1 0 V_ X 5 R_ 0 4 1 u _ 6 .3 V_ X 5 R_ 0 4 1 u _ 6 .3 V_ X 5 R_ 0 4 0 .1 u _ 1 0 V _ X 5R _ 0 4 0 .1 u_ 1 0 V _ X5 R _0 4

C6 4

EMC CAPS 1 .5 V

V D DC R _ CP U

V D D CR _ NB

C65

C6 6

0 .1 u _ 1 0 V _ X 5 R_ 0 4 * 0 .1 u _1 0 V _ X 7 R _ 04 0 .1 u _ 1 0 V _ X 5 R_ 0 4

1. 5V

V DD C R_ N B C67

C75

C 76

C7 7

C78

C68

1 0 u _ 6 .3 V _ X 5 R_ 0 6 1 0 u _6 .3 V _X 5 R _ 0 6 1 0 u _ 6 .3 V _ X5 R_ 0 6 1 0 u _ 6 .3 V _ X 5 R_ 0 6 1 0u _ 6 .3 V_ X 5 R _0 6

V D DA N_ 1 8 _ DA C

C84

C 90

C9 1

C92

C93

C 94

C70

C 71

1 8 0 P _ 5 0V _ NP O _ 0 4 1 80 P _5 0 V _ N P O _ 0 4

C7 2

C73

1 8 0 P _ 5 0 V _ NP O _ 0 4 1 8 0P _ 50 V _N P O _ 0 4

C7 4

0 .1 u _ 1 0 V _ X 5 R_ 0 4 * 0. 1u _ 1 0 V _ X 7 R_ 0 4

3. 3V S 1 .8 VS

1 8 0 P _ 5 0 V _ N P O _0 4 C89

C6 9

1 80 P _5 0 V _ N P O _ 0 4 1 8 0 P _ 5 0 V _ N P O _0 4

C79

C9 5

C96

C97

C8 5 1 8 0 P _ 5 0V _ NP O _ 0 4

C8 0

C81

C8 2

C83

1 u _ 6. 3V _ X5 R _ 0 4 1 u _ 6. 3V _ X5 R _ 0 4 1 u _6 .3 V _X5 R _ 0 4 *1 u _ 6 .3 V _ X 5 R_ 0 4

V D D P L _ 10

1 VS

C8 6 1 8 0 P_ 5 0V _ NPO _ 0 4

C8 7 1 8 0 P _ 5 0 V _ NP O _ 0 4

C88 0 .1 u _ 1 0 V _ X5 R_ 0 4

1 u _ 6 .3 V _ X5 R _ 0 4 1 u _ 6. 3V _ X5 R _ 0 4 1 u _ 6 .3 V _ X 5 R_ 0 4 0 .1 u _ 10 V _X 5 R _ 0 4 0. 1u _ 1 0 V_ X 5 R_ 0 4 1 u _ 6 .3 V _ X 5 R_ 0 4 1 u _ 6 .3 V_ X 5 R_ 0 4 0 .1 u _ 1 0 V _ X 5R _ 0 4 0 .1 u_ 1 0 V _ X5 R _0 4

ONTARIO POWER & DECOUPLING B - 5


Schematic Diagrams

INAGUA DDR3 SO-DIMMS A SO-DIMM A

INAGUA DDR3 SO-DIMMS A

2,6 MEM _ADDR[15:0] MEM_ ADDR 0 MEM_ ADDR 1 MEM_ ADDR 2 MEM_ ADDR 3 MEM_ ADDR 4 MEM_ ADDR 5 MEM_ ADDR 6 MEM_ ADDR 7 MEM_ ADDR 8 MEM_ ADDR 9 MEM_ ADDR 10 MEM_ ADDR 11 MEM_ ADDR 12 MEM_ ADDR 13 MEM_ ADDR 14 MEM_ ADDR 15


MEM _DAT A[63:0 ] 2,6

JDIMM1A A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

109 108 BA0 79 BA1 114 BA2 121 S0# 101 S1# 103 CK0 102 CK0# 104 CK1 73 CK1# 74 CKE0 115 CKE1 110 CAS# 113 RAS# # 197 WE 201 SA0 202 SA1 200 SCL SDA

2,6 MEM_BANK0 2,6 MEM_BANK1 2,6 MEM_BANK2 2 DIMM0_CS#0 2 DIMM0_CS#1 2 MEM _CLK_H 0 2 MEM _CLK_L 0 2 MEM _CLK_H 1 2 MEM _CLK_L 1 2,6 MEM_CKE0 2,6 MEM_CKE1 2,6 M EM_CAS# 2,6 M EM_RAS# 2,6 MEM_WE#

Sheet 5 of 41 INAGUA DDR3 SODIMMS A

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78

6,10,16 SCLK0 6,10,16 SDATA0

116 120

2 DIMM0_ODT0 2 DIMM0_ODT1 2,6 M EM_DM[7: 0]

MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7

ODT0 ODT1

11 28 46 63 136 153 170 187

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

12 29 47 64 137 154 171 188

2,6 MEM_DQS_H0 2,6 MEM_DQS_H1 2,6 MEM_DQS_H2 2,6 MEM_DQS_H3 2,6 MEM_DQS_H4 2,6 MEM_DQS_H5 2,6 MEM_DQS_H6 2,6 MEM_DQS_H7

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

10 27 45 62 135 152 169 186

2,6 MEM_DQS_L0 2,6 MEM_DQS_L1 2,6 MEM_DQS_L2 2,6 MEM_DQS_L3 2,6 MEM_DQS_L4 2,6 MEM_DQS_L5 2,6 MEM_DQS_L6 2,6 MEM_DQS_L7

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 12 9 13 1 14 1 14 3 13 0 13 2 14 0 14 2 14 7 14 9 15 7 15 9 14 6 14 8 15 8 16 0 16 3 16 5 17 5 17 7 16 4 16 6 17 4 17 6 18 1 18 3 19 1 19 3 18 0 18 2 19 2 19 4

MEM_DATA0 MEM_DATA1 MEM_DATA2 MEM_DATA3 MEM_DATA4 MEM_DATA5 MEM_DATA6 MEM_DATA7 MEM_DATA8 MEM_DATA9 MEM_DATA10 MEM_DATA11 MEM_DATA12 MEM_DATA13 MEM_DATA14 MEM_DATA15 MEM_DATA16 MEM_DATA17 MEM_DATA18 MEM_DATA19 MEM_DATA20 MEM_DATA21 MEM_DATA22 MEM_DATA23 MEM_DATA24 MEM_DATA25 MEM_DATA26 MEM_DATA27 MEM_DATA28 MEM_DATA29 MEM_DATA30 MEM_DATA31 MEM_DATA32 MEM_DATA33 MEM_DATA34 MEM_DATA35 MEM_DATA36 MEM_DATA37 MEM_DATA38 MEM_DATA39 MEM_DATA40 MEM_DATA41 MEM_DATA42 MEM_DATA43 MEM_DATA44 MEM_DATA45 MEM_DATA46 MEM_DATA47 MEM_DATA48 MEM_DATA49 MEM_DATA50 MEM_DATA51 MEM_DATA52 MEM_DATA53 MEM_DATA54 MEM_DATA55 MEM_DATA56 MEM_DATA57 MEM_DATA58 MEM_DATA59 MEM_DATA60 MEM_DATA61 MEM_DATA62 MEM_DATA63

JDIMM1B

1.5V 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

3.3VS

20mils C9 8

C99

1u_6.3V_X5R_04 0.1u_16V_Y5V_04

199 1.5V R75

VDDSPD

77 122 NC1 125 NC2 NC TEST

1K _0 4

198 30 EVENT# RESET#

2,6 MEM_EVENT# 2,6 MEM_RESET# MVREF_DIMM0

C100

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

1 126 VREF_DQ VREF_CA

C101

C102

1u_6.3V_X5R_04 1000p_50V_X7R_04 0.1u_10V_X7R_04

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15

44 48 49 54 55 60 61 65 66 71 72 12 7 12 8 13 3 13 4 13 8 13 9 14 4 14 5 15 0 15 1 15 5 15 6 16 1 16 2 16 7 16 8 17 2 17 3 17 8 17 9 18 4 18 5 18 9 19 0 19 5 19 6

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

VTT_MEM 20 3 20 4

VTT1 VTT2

GND1 GND2

G1 G2

DDRRK-20401-TR4B

DDRRK-20401-TR4B

(REV)4.0mm

CLOSE TO SO-DIMM A

1.5V

1.5V

+C104

+

C105

C106

C107

C108

C109

C110

C111

C112

C113

*150u_4V_B_A *220u_4V_V_A 10u_10V_Y5V_ 08 10u_10V_Y5V_08 1u_6.3V_X5R _04 1u_6.3V_X5R_04 10u_10V_Y5V_08 1u_6.3V_X5 R _04 1u_6.3V_X5R _04 1u_6.3V_X5R _04

1.5V

C114

VTT_MEM

C115

C116

C117

C118

C119

C120

C121

C122

C123

0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04

B - 6 INAGUA DDR3 SO-DIMMS A

C124

C125

C126

C127

C128

10u_10V_Y5V_08 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04

R7 6

1K _1 % _ 04

MVREF_DI MM 0

R77

C103

1K_1%_04

0.1u_10V_X5R_04

Schematic Diagrams

INAGUA DDR3 SO-DIMMS B SO-DIMM B

INAGUA DDR3 SO-DIMMS B

2,5 MEM_ADDR[15:0 ] MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9 MEM_ADDR10 MEM_ADDR11 MEM_ADDR12 MEM_ADDR13 MEM_ADDR14 MEM_ADDR15 2,5 MEM_BANK0 2,5 MEM_BANK1 2,5 MEM_BANK2 2 DIMM1_CS#0 2 DIMM1_CS#1 2 M EM_CLK_H2 2 M EM_CLK_L2 2 M EM_CLK_H3 2 M EM_CLK_L3 2,5 MEM_CKE0 2,5 MEM_CKE1 2,5 M EM_CAS# 2,5 M EM_RAS# 2,5 MEM_WE#

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 0/A P A1 1 A1 2/B C# A1 3 A1 4 A1 5

109 108 79 114 121 101 103 102 104 73 74 115 110 113 4.7K _04 197 201 202 200

R7 8

3.3VS 5,10,16 SCLK0 5,10,16 SDATA0

MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7

ODT0 ODT1

11 28 46 63 136 153 170 187

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

12 29 47 64 137 154 171 188

2,5 MEM_DQS _H0 2,5 MEM_DQS _H1 2,5 MEM_DQS _H2 2,5 MEM_DQS _H3 2,5 MEM_DQS _H4 2,5 MEM_DQS _H5 2,5 MEM_DQS _H6 2,5 MEM_DQS _H7

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

10 27 45 62 135 152 169 186

2,5 MEM_DQS _L0 2,5 MEM_DQS _L1 2,5 MEM_DQS _L2 2,5 MEM_DQS _L3 2,5 MEM_DQS _L4 2,5 MEM_DQS _L5 2,5 MEM_DQS _L6 2,5 MEM_DQS _L7

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

BA 0 BA 1 BA 2 S0 # S1 # CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA 0 SA 1 SCL SDA

116 120

2 DIMM1_ODT0 2 DIMM1_ODT1 2,5 MEM_ DM[7: 0]

M EM_DA TA[63:0] 2,5

JDIMM2A

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

MEM _DATA0 MEM _DATA1 MEM _DATA2 MEM _DATA3 MEM _DATA4 MEM _DATA5 MEM _DATA6 MEM _DATA7 MEM _DATA8 MEM _DATA9 MEM _DATA10 MEM _DATA11 MEM _DATA12 MEM _DATA13 MEM _DATA14 MEM _DATA15 MEM _DATA16 MEM _DATA17 MEM _DATA18 MEM _DATA19 MEM _DATA20 MEM _DATA21 MEM _DATA22 MEM _DATA23 MEM _DATA24 MEM _DATA25 MEM _DATA26 MEM _DATA27 MEM _DATA28 MEM _DATA29 MEM _DATA30 MEM _DATA31 MEM _DATA32 MEM _DATA33 MEM _DATA34 MEM _DATA35 MEM _DATA36 MEM _DATA37 MEM _DATA38 MEM _DATA39 MEM _DATA40 MEM _DATA41 MEM _DATA42 MEM _DATA43 MEM _DATA44 MEM _DATA45 MEM _DATA46 MEM _DATA47 MEM _DATA48 MEM _DATA49 MEM _DATA50 MEM _DATA51 MEM _DATA52 MEM _DATA53 MEM _DATA54 MEM _DATA55 MEM _DATA56 MEM _DATA57 MEM _DATA58 MEM _DATA59 MEM _DATA60 MEM _DATA61 MEM _DATA62 MEM _DATA63

JDIMM2B

1.5V 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

3.3VS

20mils C129

C130

1u_6.3V_X5R_04

0.1u_16V_Y5V_04

199

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDDSPD

77 122 NC1 125 NC2 NCTEST 198 30 EVENT# RESET#

2,5 MEM_EVENT# 2,5 MEM_RESET#

1 126

MVREF_DIMM1

C131

C132

C133

1u_6.3V_X5R_04 1000p_50V_ X7R_04 0.1u_10V_X7R_04

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43

VREF_DQ VREF_CA

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

Sheet 6 of 41 INAGUA DDR3 SODIMMS B

VTT_MEM 203 204

VTT1 VTT2

GND1 G1 GND2 G2

DDRRK-20401- TP8D

DDRRK-204 01-TP8D

(REV)8.0mm SN:6-86-24204-XXX

CLOSE TOSO-DIMM B

1.5V

R79

1 K_1 %_04

MVREF_DIMM1

1.5V

C135

+

+

C136

C137

C138

C139

C140

C141

C142

C143

C144

R80

C134

1K_1%_04

0.1u_10V_X 5R_04

*220u_4V_V_A 10u_10V_Y5V_08 10u_10V _Y5V_08 1u_6.3V_X5R_04 1u_6.3V_X5R_04 560u_2.5V_6.6*6.6*5. 9 10u_10V_Y5V _08 1u_6.3V_X5R_0 4 1u_6.3V_X 5R_04 1u_6.3V_X5R _04

VTT_MEM

1.5V

C145

C146

C147

C148

C149

C150

C151

C152

C153

C154

0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V _Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04

C155

C156

C157

C158

C159

10u_10V_Y5V_ 08 1u_6.3V_X5R_04 1u_6. 3V_X5R_04 1u_6. 3V_X5R_ 04 1u_6.3V_X5R_ 04

INAGUA DDR3 SO-DIMMS B B - 7


Schematic Diagrams

Robson S3 PCIE/ LVDS 1/6


Sheet 7 of 41 Robso n S3 PCIE/ LVDS 1/6

B - 8 Robson S3 PCIE/ LVDS 1/6

Schematic Diagrams

Robs on S3 MEM Interface 3/6 COMPONENTS SHOWN ARE EXAMPLES ONLY AND NOT NECESSARILY QUALIFIED

DDR3 Memor y Interface

U4C

13


Sheet 9 of 41 Robso n S3 MEM InTERFACE 3/6

14

DQA0_[31..0]

GDDR5/DDR3 DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

DQA1_[31..0]

PLACEMVREF DIVIDERS AND CAPS CLOSE TO ASIC MVDDQ

Ra

R122 *40.2_1%_04

K27 J29 H30 H32 G29 F28 F32 F30 C30 F27 A28 C28 E27 G26 D26 F25 A25 C25 E25 D24 E23 F23 D22 F21 E21 D20 F19 A19 D18 F17 A17 C17 E17 D16 F15 A15 D14 F13 A13 C13 E11 A11 C11 F11 A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3 E1 G7 G6 G1 G3 J6 J1 J3 J5 K26 J26

MVDDQ

Ra

Rb

R123

C204

*100_04

*0.1u_10V_X5R_04

MVDDQ R124

*243_1%_04

R125

*243_1%_04

J25 K25

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA0_6 MAA0_7/MAA0_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_13/BA 2 MAA1_6/MAA_14/BA 0 MAA1_7/MAA_15/BA 1

E C A F R E T N I

WCKA0_0/DQMA_0 WCKA0B_0/DQMA_1 WCKA0_1/DQMA_2 WCKA0B_1/DQMA_3 WCKA1_0/DQMA_4 WCKA1B_0/DQMA_5 WCKA1_1/DQMA_6 WCKA1B_1/DQMA_7

Y R O M E M

DMEM_RST

E32 E30 A21 C21 E13 D12 E3 F4

H27 QSA_0 A27 QSA_1 C23 QSA_2 C19 QSA_3 C15 QSA_4 E9 QSA_5 C5 QSA_6 H4 QSA_7

DDBIA0_0/WD DDBIA0_1/WD DDBIA0_2/WD DDBIA0_3/WD DDBIA1_0/WD DDBIA1_1/WD DDBIA1_2/WD DDBIA1_3/WD

ADBIA0/ODTA0 ADBIA1/ODTA1 CLKA0 CLKA0B CLKA1 CLKA1B RASA0B RASA1B CASA0B CASA1B CSA0B_0 CSA0B_1 CSA1B_0 CSA1B_1

MVREFDA MVREFSA

CKEA0 CKEA1

MEM_CALRN0 MEM_CALRP0

WEA0B WEA1B

CLKA0 CLKA0#

G9 H9

CLKA1 CLKA1#

G22 G17

RASA0# RASA1#

G19 G16

CASA0# CASA1#

H22 J22

CSA0b_0

G13 K13

CSA1b_0

K20 J17

CKEA0 CKEA1

G25 H10

WEA0# WEA1#

G20 G14

MAA0_8/MAA_13 MAA1_8_RSVD

MAA13 MAA1_8

L10

m o r F

*0.1u_ 10V_X5R_04

Debug only,

B - 10 Robson S3 MEM Interface 3/6

1.5V

1.5V/1.8V

40.2R

40.2R

Rb

100R

100R

13

QSA1_[3..0]

QSA0_0B QSA0_1B QSA0_2B QSA0_3B QSA1_0B QSA1_1B QSA1_2B QSA1_3B

14

13 13 13 13 14 14 14 14

O DT A0 O DT A1

13 14

C L KA0 CLKA 0#

13 13

C L KA1 CLKA 1#

14 14

R A SA 0# R A SA 1#

13 14

C A SA 0# C A SA 1#

13 14

CSA0b_0

13

CSA1b_0

14

C KE A0 C KE A1

13 14

W EA 0# W EA 1#

13 14

MA A 13

1 3 ,1 4

25mm (max) DMEM_RST

5mm (max)

25mm (max)

RSER1 *10 _04 1 0 . 0

RSER2 *49.9_1%_04

MEM_RST

13,14

CSHUNT1 *0402_120pF_50V_5%

for cloc k obser vati on, if not needed, DNI

CLKTESTB CLKTESTA

Ra

DQMA1_[3..0] 1 4

QSA0_[3.. 0]

RPD1 *4.99K_1%_04

route 50ohms singl e-ended/100ohms di ff andkeepshort

MVDDQ

A_BA2 13,14 A_BA0 13,14 A_BA1 13,14 DQMA0_[3..0] 13

T97

U P G

CLKTESTA CLKTESTB

C205

DDR3

QSA0_0B QSA0_1B QSA0_2B QSA0_3B QSA1_0B QSA1_1B QSA1_2B QSA1_3B ODTA0 ODTA1

*100_04

GDDR5

QSA0_0 QSA0_1 QSA0_2 QSA0_3 QSA1_0 QSA1_1 QSA1_2 QSA1_3

H26 H25

DRAM_RST

DDR3/GDDR3 Memory Stuff Optio n

DQMA0_0 DQMA0_1 DQMA0_2 DQMA0_3 DQMA1_0 DQMA1_1 DQMA1_2 DQMA1_3

L18 K16

*ROBSONXTS3

Rb

13,14

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12

GDDR5 /DDR3

K8 L7 R127

K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15

H28 EDCA0_0/RDQSA_0 C27 EDCA0_1/RDQSA_1 A23 EDCA0_2/RDQSA_2 E19 EDCA0_3/RDQSA_3 E15 EDCA1_0/RDQSA_4 D10 EDCA1_1/RDQSA_5 D6 EDCA1_2/RDQSA_6 G5 EDCA1_3/RDQSA_7

R126 *40.2_1%_04

MAA[12..0]

GDDR5/DDR3

DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63

C206

*0.1u_10V_X5R_04 R128

*51.1_1%_04

C207 R129 *0.1u_10V_X5R_04 *51.1_1%_04

Place all these components very close to GPU( Wi thi n 25mm) and keep al l component cl ose to each Ot her (wit hin 5mm) except Rser 2 This basi c topo l ogy s hould be use d for DRAM_RST f or DDR3/ GDDR5.Thes e Capac itor s a nd Resis t or valu es ar e an example o nly. The Seri es R an d || Cap val ues wil l d ep en d on the DRAMl oa d an d wil l h ave to be calc ulate d f or dif fe rent Mem ory ,DRAM Load and board t o pass Reset Sig nal S pec.

Schematic Diagrams

Robson S3 Straps 4/6 GPIO21 MUST BE L OW DURING PERSTB WHEN BEING USED TO CONTROL MVDDQ 3.3VS_GPU

PIN STRAPS

W250BAQ

GPIO0

R130

*10K_04

GPIO0

1

8

GPIO1

R131

*10K_04

8

GPIO2

R132

*10K_04

GPIO1 GPIO2

1 0

8

GPIO8

R133

*10K_04

8

GPIO9

R134

*10K_04

GPIO8 GPIO9

0 0

8

GPIO11

R135

*10K_04

R136

*10K_04

GPIO11 GPIO12

1 0

R137

*10K_04

GPIO13

0

8

8

GPIO12

8

GPIO13

8,21 VSYNC_DA C1 8,21 HSYNC_D AC1 8

GENERICC

8 VSYNC_DAC2 8 HSYNC_DAC2 8

GPIO21

8

GPIO22

8

GPIO5

R138

*10K_04

R139

*10K_04

RECOMMENDED SETTINGS CONFIGURATION STRAPS-- SEE EACH DATAB OOK FOR STRAP DE TAILS

ALLOW FOR PULLUP PADS FOR THESE STRAPS ANDIF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET STRAPS

*10K_04

R141

*10K_04

R142

*10K_04

HSYNC_DAC2 0

R143

*10K_04

R144

*10K_04

GPIO21 GPIO22

0 0

R145

*10K_04

GPIO5

1

GENERICC 1 VSY NC_DAC2 0

R146

R147

PC E I FULL TX OUTP U T SWI NG

GPIO1

PCIE TRANSMITTER DE-EMPHASIS ENABLE D

RSVD RSVD

GPIO2 GPIO8

RESERVED RESERVED

0 0

BIF_VGADIS

G PI O 9

VGAENABLED

0

RSVD

GP I O21

RESERVED

0

GPIO_22_ROMCSB

ROM IDCFG (2:0)

G PIO [13:1 1]

X

EN ABLEEXTER NA LBIOSR OM

X

SER IAL RO M TYPE O R MEMORY AP ER TURE S IZES ELEC T

X XX

VIP_DEVICE_ST RAP_ENA

V2SYNC

IGNOREVIP DEVICESTRAPS(Removed onSeymour/W histler)

X

RSVD

H2S YNC

RESERVED

0

HS YNC VSYNC

SEE DA TABO OK FO R DE T A IL SEE DA TABO OK FO R DE T A IL

X X

GE NERI CC

RESERVED

0

AUD[1] AUD[0]

*2.2K_04

*2.2K_04

Sheet 10 of 41 Robson S3 Straps 4/6

C208

U6 R150

*0_04

8

MXM_SDATA R151

*0_04

7

27 SMD_VGA_THERM

GPIO0

TX_DEEMPH_EN

BI OS_ROM_ EN

3.3VS _GPU *1000p_50V _X7R_04

27 SMC_VGA_THERM

TX_PW R S _ENB

3.3VS_GPU

GPUThermal Sensor

MXM_SCLK

X =DESIGNDEPENDANT NA =NOTAP PLICAB LE

DESCRIP TIONO F DEFA ULTS ETT ING S

X

VSY NC_DAC1 1 HSYNC_DAC1 1

R140

PIN

0=DO NOTINSTALLRESISTO R 1= I NS TALL 3KRESIST OR

*0_04

6

R153

*0_04

5

*2200p_50V_X7R_04

NOTE1: AMD RESERVED CONFIGURATION STRAPS

VD D 2

SDATA

R152

C209

1 SCLK

RSVD

D+

ALE RT G ND

DTHERM

GPU_ DPLUS 3 4

8

GPU_ DMINUS 8 R154

*0_04

*W83L771AWG

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW " AND NOT CONFLICT DURING RESET.

VGA_ALERT# 27 R157

GPI O 21

H2SYNC

G EN ER I CC

GPIO8

GPIO2

*2.2K_04 3.3VS_GPU

R155 R156

*0_04

GPU_TALERT# 8,17

3.3VS_GPU

SMBus gating circuit

*2.2K_04 3.3VS_GPU

7 MXM_RST# R159 *6. 8K_1%_04 R160 *6.8 K_1%_04 8

MXM_SDATA

R1 58

*0_04

G

MXM_SDATA

S

G 8

MX M_SCLK

MXM_SCLK

S

Q4 D *MTN7002Z HS3

SDA TA 0

5 ,6,16

SCLK0

5 ,6,16

Q 5 D *MTN7002ZHS3

Robson S3 Straps 4/6 B - 11


Schematic Diagrams

Robson S3 Power 5/6 U4E


Sheet 11 of 41 Robson S3 Power 5/6

AA 27 AB 24 AB 32 AC24 AC26 AC27 AD25 AD32 AE 27 AF 32 AG 27 AH32 K28 K32 L27 M3 2 N25 N27 P25 P32 R27 T2 5 T3 2 U25 U27 V32 W 25 W 26 W 27 Y25 Y32

M6 N11 N12 N13 N16 N18 N21 P6 P9 R12 R15 R17 R20 T1 3 T1 6 T1 8 T2 1 T6 U15 U17 U20 U9 V13 V16 V18 Y10 Y15 Y17 Y20 R11 T1 1

PCIE _VSS#1 PCIE _VSS#2 PCIE _VSS#3 PCIE _VSS#4 PCIE _VSS#5 PCIE _VSS#6 PCIE _VSS#7 PCIE _VSS#8 PCIE _VSS#9 PCIE _VSS#10 PCIE _VSS#11 PCIE _VSS#12 PCIE _VSS#13 PCIE _VSS#14 PCIE _VSS#15 PCIE _VSS#16 PCIE _VSS#17 PCIE _VSS#18 PCIE _VSS#19 PCIE _VSS#20 PCIE _VSS#21 PCIE _VSS#22 PCIE _VSS#23 PCIE _VSS#24 PCIE _VSS#25 PCIE _VSS#26 PCIE _VSS#27 PCIE _VSS#28 PCIE _VSS#29 PCIE _VSS#30 PCIE _VSS#31

GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86

GND

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55

A3 A3 0 AA1 3 AA1 6 AB1 0 AB1 5 AB6 AC9 AD6 AD8 AE7 AG 12 AH10 AH28 B1 0 B1 2 B1 4 B1 6 B1 8 B2 0 B2 2 B2 4 B2 6 B6 B8 C1 C32 E2 8 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K1 1 K2 K2 2 K6

PARK/ROBSON- S3 (DP Power) (1.8V@300mA DPAB_VDD18) DPAB_VDD18 U4 G

DPEF_VDD18 *1u_6 .3V_X5 R_04

*HCB1608KF -121T25 C212

A DPEF_ VDD18) LVDS mode (1. 8V@440m 18) DP mode ( 1.8V@300mADPEF_ VDD

C215

*10u_6.3V_08_H125

AG1 5 AG1 6

C213

AG2 0 AG2 1

DPEF_VDD10

L77

AG1 4 AH1 4 AM1 4 AM1 6 AM1 8

*HCB1608KF -121T25 C219

C220 C221

240m A DPEF_VDD10) *10u_6.3V_08_H125 LVDS mode (1. 0V@ A DPEF_ VD D10) DP mode (1. 0V@220m

B - 12 Robson S3 Power 5/6

C210

AE1 1 DPA_VDD18#1 AF1 1 DPA_VDD18#2

DPE_VDD10#1 DPE_VDD10#2

AF6 DPA_VDD10#1 AF7 DPA_VDD10#2

*0.1u_10V_X5R _04

*1u_6. 3V_X 5R_04

DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5

AE1 DPA_VSSR#1 AE3 DPA_VSSR#2 AG 1 DPA_VSSR#3 AG 6 DPA_VSSR#4 AH5 DPA_VSSR#5

DPF_VDD18#1 DPF_VDD18#2

AE1 3 DPB_VDD18#1 AF1 3 DPB_VDD18#2

DPF_VDD10#1 DPF_VDD10#2

AF8 DPB_VDD10#1 AF9 DPB_VDD10#2

AF2 3 AG2 3 AM2 0 AM2 2 AM2 4

R162

C216

C217

*0. 1u_ 10V_X5R_04

*150_1%_ A 04 F1 7

DPAB_VDD10

DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5

DPEF_CALR

DPAB_CALR

AE1 0 R163

*150_1%_04 DPAB_VDD18

DP PLL POW ER DPE_PVDD DPE_PVSS

AG 8 DPA_PVDD AG 7 DPA_PVSS

DPF_PVDD DPF_PVSS

AG 10 DPB_PVDD AG 11 DPB_PVSS

DPEF_VDD18

DPAB_VDD18 AG1 9 AF2 0

L74

C211

*HCB1608KF-121T25

*10u_6.3V_08_H125

A DPAB_VDD10)L76 C218

1.0V_REG

*H CB 1608KF-121T25

*10u_6.3V_08_H125

*1u_6.3V_X5R_04

AF1 0 DPB_VSSR#1 AG 9 DPB_VSSR#2 AH8 DPB_VSSR#3 AM 6 DPB_VSSR#4 AM 8 DPB_VSSR#5

DPEF_VDD18 AG1 8 AF1 9

A3 2 VSS_ME CH# 1 AM 1 VSS_ME CH# 2 AM 32 VSS_ME CH# 3

DPAB_VDD10 (1.0V@220m

DPEF_VDD10 AF2 2 AG2 2

C214

*0.1 u_10V_X 5R_04

DPAB_VDD18 AF1 6 AG1 7

DPEF_VDD18

*ROBS ON XTS3

*R O BSO N XTS3

DP A/B PO WER

DPE_VDD18#1 DPE_VDD18#2

*0. 1u_10V _X5R_04

1.0V_REG

1.8V _RE G

*1u_6.3V_X5R_ 04

DPE/ F POW ER 1.8V_REG L75

Schematic Diagrams

Robson S3 Power 6/6 MVDDQ 2.8A 21 0mi l

MV DDQ C22 2

C2 23

* 0.1 u_ 1 0V_ X5 R_ 04

*0 .1u _ 10 V_X5R_ 0 4

C22 4

C 22 5

C2 26

* 0.1 u_ 10 V_X5 R_0 4 * 0.1 u_ 1 0V_ X5 R_ 04

C23 2

C 23 3

*1 u_ 6 .3V_ X5 R_ 04

C24 8

C2 3 4

C24 9

* 10 u_ 6.3 V_0 8 _H1 2 5

C2 28

* 1u _6 .3 V_ X5R_ 0 4 C2 2 9

C23 0

* 0.1 u _ 1 0V_ X5 R_ 04

C 23 1

U4D

C2 35

H1 3 H1 6 H1 9 J1 0 J2 3 J2 4 J9 K1 0 K2 3 K2 4 K9 L1 1 L1 2 L1 3 L2 0 L2 1 L2 2

C2 38 *1 u_ 6 .3 V_ X5 R_0 4

* 1u _6 .3V_ X5 R_ 04

C25 1

C25 2

*10 u _6 .3V_ 08 _ H 12 5

PCI E _V DDR

M EMI /O

*1 u_ 6 .3V_ X5 R_ 04

*0.1 u _1 0V_ X5 R_ 04

*1 u_ 6.3 V_X5 R_0 4 * 1u _6 .3 V_ X 5R_ 0 4

*0 .1 u_ 10 V_X5 R_0 4 C22 7

*0 .1 u_ 10 V_X 5 R_0 4

*1 0u _6 .3V_ 0 8_ H 12 5

*10 u _6 .3V_ 08 _H 12 5

PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_

V DDC _CT *1 u_ 6.3 V_X 5R _0 4

* HCB 1 60 8KF -1 21 T2 5 C2 61

C 26 2

* 0.1 u_ 10 V_X 5 R_0 4 C26 3

C 26 4

* 10 u_ 6.3 V_0 8 _H 1 2 5

A A2 0 A A2 1 A B2 0 A B2 1

C2 65 *1 u _6 .3V_ X5 R_ 04

3.3 VS_GPU VDDC_CT+VDDR 4

* 1u _6 .3V_ X5R_ 04

187mA 1 0mi l

C27 6

C27 7

*1 0u _ 6.3 V _0 8_ H 1 25

C 27 8

A A1 7 A A1 8 A B1 7 A B1 8

C2 79

*1 u_ 6.3 V _X5 R_0 4

3.3VS_GPU 60mA 4mil

VDD R4 V1 2 Y1 2 U1 2

* 1u _6 .3V_ X 5R_ 04 VDDR4 L8 0

A A1 1 A A1 2

* HCB 1 60 8KF -1 21 T25 C29 0

C2 91

V1 1 U1 1

*0 .1 u _1 0V_ X5 R_ 04

*1 u _6 .3V_ X5 R_ 04

LEVEL TRA NSLATION V DD_ CT #1 V DD_ CT #2 V DD_ CT #3 V DD_ CT #4

CORE

I/O

*1 u _6 .3V_ X5 R_ 04

V DDR 3# 1 V DDR 3# 2 V DDR 3# 3 V DDR 3# 4 V DDR 4# 1 V DDR 4# 2 V DDR 4# 3

P O W E R

NC #1 NC #2 NC #3 NC #4

M EM CLK L1 7 L1 6 P CIE_ VD DR_ VG A

A M3 0

SPV1 8

L23 L24 L25 L26 M 22 N 22 N 23 N 24 R 22 T22 U 22 V22

C2 4 1

1 .8V_ REG

400mA20mil

L78

C2 43

C2 42

C2 44

C24 5

*1 u_ 6. 3 V_X5R _0 4 * 1u _6 .3V_ X5 R_ 04

* 0.1 u_ 1 0V_ X5 R_ 04

*HC B1 6 08 KF-1 2 1T 25

*1 0u _ 6.3 V _0 8_ H1 25 *1u _ 6.3 V_X 5R _0 4

VD DC

1.0V_REG 2A 80mil

1 .0V_ REG C8 37

C2 53

C 25 4

* 1u _6 .3 V_ X5R_ 0 4

C2 55

C2 56

*1 u_ 6. 3 V_X5R _0 4

*1 u_ 6.3 V _X5 R_0 4

C 25 7

C2 5 8

*1 u_ 6.3 V _X5R _0 4

*1 u_ 6.3 V_X 5 R_0 4

C2 5 9

BIF _ VDDC# 1 BIF _ VDDC# 2

* 1u _6 .3 V_ X5R_ 0 4

* 1u _6 .3 V_ X 5R_ 0 4 C2 66

C 26 7

C2 6 8

*1 u_ 6.3 V_X5R _0 4 C2 69

C2 70

C2 80

C 28 1

* 1u _6 .3V _ X5 R_ 04 C2 8 2

C2 83

*1 u _6 . 3V_ X5 R_ 04

*1 u_ 6 .3V_ X5 R_ 04

*1 u _6 .3V _ X5 R_ 04

C2 98

VDDC

* 1u _6 .3 V_ X5R_ 0 4 C 27 3

C2 74

C27 5

*1 u_ 6.3 V _X5R _0 4

C2 84

C2 8 7

*1 u_ 6. 3 V_X5R _0 4

C3 00

C28 9

* 1u _6 .3V_ X5R_ 04

C3 01

*1 0 u_ 6.3 V _0 8 _H1 25

*1 0u _ 6.3 V _0 8_ H1 25

C2 88

*1 u _6 .3V_ X5 R_ 04 *1 u_ 6.3 V_X 5R _0 4

*1u _ 6.3 V _X5R _0 4

C2 99

*1 0u _ 6.3 V _0 8_ H1 25

*1u _6 .3 V_ X5R_ 0 4

C3 02 *1 0u _ 6. 3 V _0 8_ H1 25

C3 0 3

Sheet 12 of 41 Robson S3 Power 6/6

*1 0 u_ 6.3 V _0 8_ H1 25

* 10 u_ 6.3 V _0 8 _H1 25

R 21 U 21

See Note 1

ISOLATED COR E I/O VDDCI# 1

S PV10

VDDCI# VDDCI# VDDCI# VDDCI# VDDCI# VDDCI# VDDCI#

J7 S PVSS

SPVS S

2 3 4 5 6 7 8

*1 u _6 .3V_ X5 R_ 04 M 13 M 15 M 16 M 17 M 18 M 20 M 21 N 20

C3 0 5 *1 u _6 .3V_ X5 R_ 04 VDDCI VDDCI 2A80mil

VDDC

*1 u _6 .3V_ X5 R_ 04 C3 09

C3 10

L 82 C31 1

C3 12

C3 1 3

*1 u_ 6 . 3V_ X5 R_ 04 *1 u_ 6.3 V_X5 R_0 4

*1 u_ 6.3 V_X5R _0 4

C3 14

*HC B1 6 08 KF - 12 1T 25

*1 u_ 6 .3 V_ X5 R_0 4

0.9- 1.12V@2A( D DR3)

??( G DD R5)

W arning:Select thecorrect Bead to support exp ected VDDCI curr ent. See databoo k for detail s.

MPV18

( P a r k : 18 . V @ 7 5m A M P V 1 8) L8 3 C 31 7 C3 20 C3 21 *HCB1 60 8 K F-1 2 1T 25

C3 15

*1 u _6 .3V_ X5 R_ 04 * 0.1 u_ 1 0V_ X5 R_0 4

SPV1 8

*1 0u _ 6.3 V _0 8_ H1 25

Note 1 B FI _ VDDC

C 32 3

C27 2

*1 u_ 6.3 V_X 5R _0 4

*1u _ 6.3 V_ X5R_ 0 4

* 1u _6 .3 V_ X 5R_ 0 4

*1 0u _6 .3 V_ 0 8_ H1 25

*1 u_ 6.3 V_X5 R_0 4 C27 1

*1 u_ 6 .3V_ X5 R_ 04

*ROBSON XT S3

(1.8V@75mA SPV18) L84 *HCB 1 60 8K F -1 21 T2 5 C32 2

* 22 0u _ 4V_ V_ A

*1 0u _6 .3 V_ 0 8_ H1 25

*1 u_ 6. 3 V_X5R _0 4

VDDC 12.9A 520 mi l

C 30 4

* 1u _6 .3V_ X5R_ 04

*1 0u _6 .3 V_ 0 8_ H1 25

+

C2 6 0

BIF _ VDDC

PLL

NC _MPV 1 8 S PV18

H8

C 24 0

*0 .1u _ 10 V_X5R _0 4

A A1 5 N 15 N 17 R 13 R 16 R 18 Y 21 T12 T15 T17 T20 U 13 U 16 U 18 V21 V15 V17 V20 Y 13 Y 16 Y 18 M 11 M 12

H7

1.0 V _R EG *10 u _6 .3V_ 08 _H 12 5 L8 1 * HCB 16 0 8KF -12 1 T2 5 C 30 6 C3 07 C30 8 N C1 *0 .1 u_ 10 V_X5R _0 4

S H ORT

VDDC# 1 VDDC# 2 VDDC# 3 VDDC# 4 VDDC# 5 VDDC# 6 VDDC# 7 VDDC# 8 VDDC# 9 VDD C#1 0 VDD C#1 1 VDD C#1 2 VDD C#1 3 VDD C#1 4 VDD C#1 5 VDD C#1 6 VDD C#1 7 VDD C#1 8 VDD C#1 9 VDD C#2 0 VDD C#2 1 VDD C#2 2 VDD C#2 3

A B2 3 A C2 3 A D2 4 A E2 4 A E2 5 A E2 6 AF25 A G2 6

NC _VSS RHA

MPV18 L8

1 2 3 4 5 6 7 8

NC _VDDR HA

P CIE_ PVD D

ForSeymour,PCIE_PV DDisPC IE _VDDR

VDDR# VDDR# VDDR# VDDR# VDDR# VDDR# VDDR# VDDR#

PCIE_ VDDC# 1 PCIE_ VDDC# 2 PCIE_ VDDC# 3 PCIE_ VDDC# 4 PCIE_ VDDC# 5 PCIE_ VDDC# 6 PCIE_ VDDC# 7 PCIE_ VDDC# 8 PCIE_ VDDC# 9 PCIE _VDD C#1 0 PCIE _VDD C#1 1 PCIE _VDD C#1 2

1 .8V _ REG

L7 9

PC IE _ VDDR_ VGA

PCIE

V DDR 1# 1 V DDR 1# 2 V DDR 1# 3 V DDR 1# 4 V DDR 1# 5 V DDR 1# 6 V DDR 1# 7 V DDR 1# 8 V DDR 1# 9 V DDR 1# 10 V DDR 1# 11 V DDR 1# 12 V DDR 1# 13 V DDR 1# 14 V DDR 1# 15 V DDR 1# 16 V DDR 1# 17

R 1 64

* 1 0m i _l s ho rt

1. No BA CO S upport:

* 0.1 u_ 10 V_X5 R_0 4

BIF_VDDC shorts with VDDC if BACO is not suppor ted 2. BACO Support :

S PVSS

*1 0u _ 6.3 V _0 8_ H1 25

VDDC

C3 24

*1u _ 6.3 V_X5R_ 0 4

C3 16

VDDCI and VDDC share one commo n regulator

Referto theBACOr eference schematics/Application notefordeta il about BIF_VDDC Rail if BACO is Supported

Robson S3 Power 6/6 B - 13


Schematic Diagrams

Robson DDR3 MEM CH-A COMPONENTS SHOWN ARE EXAMPLES ONLY ANDN OT NECESSARILY QUALIFIED

CHANNEL A: 64 M X 16 bit X8 DDR3 (RANK0)

U7

U8 MV DDQ


9,1 4 MAA [1 3..0 ] MAA 0 MAA 1 MAA 2 MAA 3 MAA 4 MAA 5 MAA 6 MAA 7 MAA 8 MAA 9 M AA1 0 M AA1 1 M AA1 2 MAA 13

Sheet 13 of 41 Robso n DDR3 MEM CH-A 9

9 ,1 4 9 ,1 4 9 ,1 4

M8 H1

MAA 0 MAA 1 MAA 2 MAA 3 MAA 4 MAA 5 MAA 6 MAA 7 MAA 8 MAA 9 MAA1 0 MAA1 1 MAA1 2 MAA 1 3

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

A_ BA0 A_ BA1 A_ BA2

9 9 9

CLK A0 CLK A0 # CKE A0

9 9 9 9

CSA 0b _0 RAS A0 # CAS A0 # W EA 0 #

DQMA 0_ [3..0 ]

ODT A0 DQMA0 _0 DQMA0 _1 DQMA0 _2 DQMA0 _3

9

VREF C_U 7 VREF D_U 7

QS A0 _1 QS A0 _2

QSA 0_ [3..0 ] Q SA0 _0 Q SA0 _1 Q SA0 _2 Q SA0 _3

9 9 9 9

QS A0_ 0 B QS A0_ 1 B QS A0_ 2 B QS A0_ 3 B

QS A0 _ 0B QS A0 _ 1B QS A0 _ 2B QS A0 _ 3B

M2 N8 M3

J7 K7 K9 K1 L2 J3 K3 L3 F3 C7

DQ MA 0_ 1 DQ MA 0_ 2

E7 D3

QS A0 _1 B QS A0 _2 B

G3 B7

T2

9,1 4 MEM_ RS T

L8

V REF CA V REF DQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 /A P A 11 A 12 /B C A 13 A 14 A 15 B A0 B A1 B A2

CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU

RESE T ZQ

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD# B2 VD D#D9 VD D#G7 VDD# K2 VDD# K8 VD D#N1 VD D#N9 VD D#R1 VD D#R9 V DDQ# A1 V DDQ# A8 V DD Q#C1 V DD Q#C9 V DD Q#D2 V DDQ# E9 V DDQ# F1 V DD Q#H2 V DD Q#H9 VSS # A9 VSS # B3 VSS # E1 VSS #G8 VSS # J2 VSS # J8 VSS #M1 VSS #M9 VSS # P1 VSS # P9 VSS # T1 VSS # T9

E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

DQA0_ 11 D QA0_ 9 DQA0_ 8 D QA0_ 10 D QA0_ 15 D QA0_ 12 D Q A 0 _ 14 D QA0_ 13 D QA 0_ 23 D QA 0_ 22 D QA 0_ 18 D QA 0_ 21 D QA 0_ 16 D QA 0 _ 19 D QA 0_ 17 D QA 0_ 20

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

9

DQA0 _[2 3..1 6] 9

V REFC _U8 V REFD _U8

M8 H1

MA A0 MA A1 MA A2 MA A3 MA A4 MA A5 MA A6 MA A7 MA A8 MA A9 MAA 1 0 MAA 1 1 MAA 1 2 MA A13

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

MVDD Q

MV DD Q A1 A8 C1 C9 D2 E9 F1 H2 H9

DQA 0 _[1 5..8 ]

9,1 4 9,1 4 9,1 4

A_ BA0 A_ BA1 A_ BA2

9 9 9

C LKA0 C LKA0# C KEA0 ODT A 0

9 9 9 9

CSA0 b_ 0 R ASA0 # C ASA0 # W E A0#

M2 N8 M3

J7 K7 K9 K1 L2 J3 K3 L3

QS A 0_ 3 QS A0_ 0

F3 C7

DQ MA 0 _3 DQMA0 _0

E7 D3

QSA 0 _3 B QS A0_ 0B

G3 B7

T2

9,1 4 ME M_R ST

L8

V REF CA V REF DQ

D D D D D D D D

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 /A P A 11 A 12 /B C A 13 A 14 A 15 B A0 B A1 B A2

CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU

RESE T ZQ

QL0 QL1 QL2 QL3 QL4 QL5 QL6 QL7


E3 F7 F2 F8 H3 H8 G2 H7

DQ A0 _ 27 DQ A0 _ 28 DQ A0 _ 25 DQ A0 _ 31 DQ A0 _ 29 DQ A0 _ 30 DQ A0 _ 24 DQ A0 _ 26

DQA0_ [31..24 ] 9

D7 C3 C8 C2 A7 A2 B8 A3

DQ A0 _ 3 DQ A0 _ 2 DQ A0 _ 5 DQ A0 _ 0 DQ A0 _ 7 DQ A0 _ 4 DQ A0 _ 6 DQ A0 _ 1

DQA0 _[7 ..0 ]

C33 3 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

9

VDD Q#A1 VDD Q#A8 VDDQ #C1 VDDQ #C9 VDDQ #D2 VDD Q#E9 VDD Q#F 1 VDDQ #H2 VDDQ #H9 VSS #A9 VSS #B3 VSS #E1 VSS #G8 VSS # J2 VSS # J8 VSS #M1 VSS #M9 VSS #P1 VSS #P9 VSS # T1 VSS # T9

C35 4 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

B2 D9 G7 K2 K8 N1 N9 R1 R9

C33 5 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C3 36 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C33 7 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C3 38 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C33 9 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C3 40 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C3 55 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C35 6 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C3 57 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C35 8 4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C3 59 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C36 0 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C3 61 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C37 5 6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

M VD D Q

C3 76 6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

C37 7 6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

9

ODT A0

*24 3_ 1 %_ 04

ODT A0 J1 L1 J9 L9

V SSQ# B1 V SSQ# B9 V SSQ#D1 V SSQ#D8 V SSQ# E2 V SSQ# E8 V SSQ# F9 V SSQ#G1 V SSQ#G9

NC# J1 NC# L1 NC# J9 NC# L9 10 0-BA LL SD RA M DDR3

* K 4W 1G 16 46 G-BC 11

B1 B9 D1 D8 E2 E8 F9 G1 G9

R1 66

* 24 3_ 1% _0 4

J1 L1 J9 L9

V SSQ#B1 V SSQ#B9 V SSQ #D1 V SSQ #D8 V SSQ#E2 V SSQ#E8 V SSQ#F 9 V SSQ #G1 V SSQ #G9

NC# J1 NC# L1 NC# J9 NC# L9 1 0 0-BA LL SDR AM DDR3

B1 B9 D1 D8 E2 E8 F9 G1 G9

C3 42 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C36 2

C3 63

4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C3 78 6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

M VD DQ MVDDQ

R1 69 *4 .99 K_1 %_ 04

R1 7 0 * 4.9 9K_ 1% _0 4 VREF C_ U8

VREF C_U 7 R1 65

C34 1

MV DDQ

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

MV DDQ

M VD DQ VD D#B2 V DD #D9 V DD #G7 VD D#K2 VD D#K8 V DD #N1 V DD #N9 V DD #R1 V DD #R9

C3 34

R1 7 4 R1 73

C 32 5 * 0.1 u_ 10 V_X5R _0 4 *4 .99 K_1 %_ 04

* 4.9 9K_ 1% _0 4

C3 26 *0 .1u _1 0V _ X5 R_ 04

M VD DQ

MVDDQ

* K4 W 1G1 6 46 G-BC11 R1 77 *4 .99 K_1 %_ 04

R1 7 8 * 4.9 9K_ 1% _0 4 VREF D_ U8

VREF D_U 7 R1 8 2 R1 81

C 32 9 * 0.1 u_ 10 V_X5R _0 4 *4 .99 K_1 %_ 04 9

CL KA 0 R18 5 *5 6_ 04 R18 6 *5 6_ 04

9

CL KA 0 #

B - 14 Robson DDR3 MEM CH-A

*0 .0 1u _1 6V _ X7 R_ 04 C3 5 3

* 4.9 9K_ 1% _0 4

C3 30 *0 .1u _1 0V _ X5 R_ 04

Schematic Diagrams

Robson DDR3 MEM CH-B COMPONENTS SHOWN ARE EXAMPLES ONL Y AND NOT NECESSARILY QUAL IFIED

U1 1 VREF C_U 11 VREF D_U 11 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA1 0 MAA1 1 MAA1 2 MAA1 3

9 ,1 3 MAA[1 3..0] MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA1 0 MAA1 1 MAA1 2 MAA13

9 DQ MA1 _ [3 ..0]

9

QSA1 _ [3 ..0]

9 9 9 9

QSA1_ 0B QSA1_ 1B QSA1_ 2B QSA1_ 3B

9

O DTA1

9 ,13 9 ,13 9 ,13

DQMA1 _0 DQMA1 _1 DQMA1 _2 DQMA1 _3

QSA1_ 0 Q S A 1 _ 1 QSA1_ 2 QSA1_ 3

A_BA0 A_BA1 A_BA2

9 9 9

CLKA1 CLKA1 # CKEA1

9 9 9 9

CSA 1b _0 RASA1 # CASA1 # W EA1 #

ODT A1

QSA 1_ 0B QSA 1_ 1B Q S A 1 _ 2B QSA 1_ 3B

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M2 N8 M3

J7 K7 K9 K1 L2 J3 K3 L3

QSA1 _0 QSA1 _1

F3 C7

DQ MA1_ 0 DQ MA1 _ 1

E7 D3

QSA1 _0 B QSA1 _1 B

G3 B7

T2

9 ,13 MEM_ RST

ODTA1

M8 H1

L8

U1 2

VREF CA VREF DQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 0/AP A1 1 A1 2/BC A1 3 A1 4 A1 5 BA0 BA1 BA2

CK CK C KE O DT CS R AS C AS WE D QSL D QSU D ML D MU D QSL D QSU

R ESET ZQ

R20 5 *24 3_ 1% _0 4 9

C LKA1 R23 6 *56 _0 4 R23 7 *56 _0 4

9

C LKA1#

C41 1 *0 .0 1u _ 16 V_ X7 R_ 04

J1 L1 J9 L9

CHANNEL A: 64M X 16 b it X8 DDR3 (RANK1)

N C#J 1 N C#L 1 N C#J 9 N C#L 9

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

E3 F7 F2 F8 H3 H8 G2 H7

DQA1 _0 DQA1 _2 DQA1 _7 D QA1 _ 3 DQA1 _6 DQA1 _4 DQA1 _5 D QA1 _ 1

D7 C3 C8 C2 A7 A2 B8 A3

D QA1 _ 11 D QA1 _ 12 D QA1 _ 9 D QA1 _ 8 D QA 1 _ 14 D QA1 _ 15 D QA1 _ 10 D QA1 _ 13

DQA1 _[1 5..8]

DQA1 _[7 ..0 ]

9

VREF C_U 12 M8 VREF D_U 12 H1 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA1 0 MAA1 1 MAA1 2 MAA13

9

MVDDQ VDD# B2 VD D#D9 VD D#G7 VDD# K2 VDD# K8 VD D#N1 VD D#N9 VD D#R1 VD D#R9 VDDQ# A1 VDDQ# A8 VDD Q#C1 VDD Q#C9 VDD Q#D2 VDDQ# E9 VDDQ# F1 VDD Q#H2 VDD Q#H9 VSS# A9 VSS# B3 VSS# E1 VSS#G8 VSS# J2 VSS# J8 VSS#M1 VSS#M9 VSS# P1 VSS# P9 VSS# T1 VSS# T9 VSSQ# B1 VSSQ# B9 VSSQ#D1 VSSQ#D8 VSSQ# E2 VSSQ# E8 VSSQ# F9 VSSQ#G1 VSSQ#G9

1 00 -BAL L SDRAM DDR3 *K4 W1 G16 4 6G-BC1 1

B2 D9 G7 K2 K8 N1 N9 R1 R9 MVDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9

9 ,13 9 ,13 9 ,13

A_BA0 A_BA1 A_BA2

9 9 9

CLKA1 CLKA1 # CKEA1

9 9 9 9

CSA1 b_ 0 RASA1 # CASA1 # WEA1 #

ODT A1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M2 N8 M3

J7 K7 K9 K1 L2 J3 K3 L3

QSA1_ 2 QSA1_ 3

F3 C7

DQMA1 _2 DQMA1 _3

E7 D3

QSA1_ 2B QSA1_ 3B

G3 B7

T2

9 ,13 MEM_ RST

L8

VREF CA VREF DQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 0/AP A1 1 A1 2/BC A1 3 A1 4 A1 5 BA0 BA1 BA2

CK CK C KE O DT CS R AS C AS WE D QSL D QSU D ML D MU D QSL D QSU

R ESET ZQ

R20 6 *24 3_ 1% _0 4

J1 L1 J9 L9

N C#J 1 N C#L 1 N C#J 9 N C#L 9

D D D D D D D D

QL0 QL1 QL2 QL3 QL4 QL5 QL6 QL7


E3 F7 F2 F8 H3 H8 G2 H7

DQA1 _2 1 DQA1 _2 2 DQA1 _1 6 DQA1 _2 3 DQA1 _1 8 DQA1 _2 0 DQA1 _1 9 D Q A 1 _1 7

D7 C3 C8 C2 A7 A2 B8 A3

DQA1 _2 8 DQA1 _2 6 D Q A 1 _3 1 D Q A 1 _2 4 DQA1 _2 9 DQA1 _2 5 DQA1 _3 0 DQA1 _2 7

MVDDQ

MVDDQ VDD#B2 VDD #D9 VDD #G7 VDD#K2 VDD#K8 VDD #N1 VDD #N9 VDD #R1 VDD #R9 VDDQ#A1 VDDQ#A8 VDDQ #C1 VDDQ #C9 VDDQ #D2 VDDQ#E9 VDDQ#F 1 VDDQ #H2 VDDQ #H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS# J2 VSS# J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS# T1 VSS# T9 VSSQ#B1 VSSQ#B9 VSSQ #D1 VSSQ #D8 VSSQ#E2 VSSQ#E8 VSSQ#F 9 VSSQ #G1 VSSQ #G9

DQA1 _[2 3..16 ] 9

B1 B9 D1 D8 E2 E8 F9 G1 G9

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C4 1 2

MVDDQ

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

C3 9 1

C39 2

C39 3

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C3 94

C3 95

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C3 96

C39 7

4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C39 8

4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C3 99 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C4 00 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

MVDDQ

B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9

DQA1 _[3 1..24 ] 9

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C41 3

C41 4

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

C4 15

C4 16

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

4 0 _ R 5 X _ V 3 . 6 _ u 1 *

MVDDQ C4 3 4 6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

C4 17

C41 8

4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C41 9

4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

C4 20 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

Sheet 14 of 41 Robso n DDR3 MEM CH-B

C4 21 4 0 _ R 5 X _ V 0 1 _ u 1 . 0 *

MVDDQ C43 5

C43 6

6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

C4 37

6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

6 0 _ R 5 X _ V 3 . 6 _ u 0 1 *

+C83 8

* 22 0u _4 V_V_A

MVDDQ

MVDDQ

R22 4 *4.9 9K_ 1% _0 4

R2 25 * 4.99 K _1 %_ 04

VREF C_ U11 R23 2

C3 87 *0 .1u _1 0V_ X5 R_0 4 *4.9 9K_ 1% _0 4

VREF D_U1 1 R2 33

C38 8 *0.1 u_ 10 V_X5R_ 04 * 4.99 K _1 %_ 04

10 0 -B AL L SDRAM DDR3 *K4W 1 G16 46 G-BC11

MVDDQ

MVDDQ

R22 6 *4 .9 9 K_ 1% _0 4

R2 2 7 * 4.9 9K_1 %_ 04

VR EF C_ U12 R23 4 *4 .9 9 K_ 1% _0 4

VREF D_U1 2

C3 89 R2 3 5 C39 0 *0 .1u _1 0V_ X5 R_0 4 *0.1 u_ 10 V_X5R_ 04 * 4.9 9K_1 %_ 04

Robson DDR3 MEM CH-B B - 15


Schematic Diagrams

HUDSON SATA/ DEBUG IO/ SPI HUDSON SATA/DEBUG IO/SPI DEBUGONLY DNI R652andR653 forcustomer board U19B

HUDSON-1 24 24

SATATXP0 SATATXN0

24 24

SATARXN0 SATARXP0

24 24

SATATXP1 SATATXN1

24 24

AH9 AJ9

5

SA TA _TX 0N

AJ8 AH8

SA TA _RX 0N SA TA _RX 0P

AH10 AJ10 AG10 AF10

SATARXN1 SATARXP1

SA TA _TX 1P SA TA _TX 1N

SA TA _RX 1N SA TA _RX 1P

AG12 AF12 AJ12 AH12


PA RT 2O F

SA TA _TX 0P

AH14 AJ14

F C_ IN T2/G P IO D 147 G P IO D

SA TA _TX 2P

F C_A DQ 0/G P IO D 128

SA TA _TX 2N

F C_A DQ 1/G P IO D 129 F C_A DQ 2/G P IO D 130

SA TA _RX 2N


SA TA _RX 2P


SA TA _TX 3P


SA TA _TX 3N

AG14 AF14

SA TAtrac e shoulduseonly 1viaon the custom trace. ers canuse 2vias withGNDvia within150mi ls of signal via as lo ngas they ca nensure that the ir platfor m

AG17 AF17

me ets SA TAlogorequirements. Returnloss is expected

Sheet 17 of 41 HUDSON SATA/ DEBUG IO/ SPI

toget affectedwith2vi as.AMDplatform sarevali d ated withonevi aonly

AJ17 AH17

8 2 8 H 2 A 6 G 2 FC _C LK A FC _F BC LKOU T F 8 A FC _FB CLK IN 2 9 F 2 A 6 G 2 FC _OE#/G P IO D 145 A 7 G 2 FC _AV D#/G P IO D 146 A 9 2 F C_ WE#/G P IO D 148 F 9 A E 2 F C_C E1#/G P IO D 149 A 7 F 2 F C_C E2#/G P IO D 150 A H F C_ IN T1/G P IO D 144 A


SA TA _RX 3N


SA TA _RX 3P

F C_A DQ10/G P IO D 138 F C_A DQ11/G P IO D 139

SA TA _TX 4P

F C_A DQ12/G P IO D 140

SA TA _TX 4N

F C_A DQ13/G P IO D 141 F C_A DQ14/G P IO D 142

SA TA _RX 4N

F C_A DQ15/G P IO D 143

AJ2 7 AJ2 6 AH25 AH24 AG 23 AH23 AJ2 2 AG 21 AF21 AH22 AJ2 3 AF23 AJ2 4 AJ2 5 AG 25 AH26

Debug port

NOTE:ROUT ETEMP_COMM AS A10 MI L TRAC E PLACEQ600UNDERDI MM

SA TA _RX 4P

AJ18 AH18 AH19 AJ19

S ER I ALAT A SA TA _TX 5P SA TA _TX 5N

FA NO UT 0/G PIO 52 FA NO UT 1/G PIO 53

SA TA _RX 5N

F AN IN 0/ GPIO 56

AVDD_SATA R331 R332

1K _1%_04 931 _1 %_04

SATA_CALP SATA_CALN

AB14 AA14

F AN IN 1/ GPIO 57 SA TA _CA LR P

F AN IN 2/ GPIO 58

SA TA _CA LR N T EMP IN 0/G PI O171

28

T EMP IN 1/G PI O172

AD11

SATA_LED#

W5 W6 Y9

HUDS ON_FANOUT0 ODD_PWR SB_PROCH OT#_C

W7 V9 W8

HUDSON_FANTA CH0 HDD0_PWR GPI O 58

FA NO UT 2/G PIO 54

SA TA _RX 5P

SA TA _AC T# / GP I O6 7

T EMP IN 2/G PI O173 TE MP IN3/T ALE RT #/G PI O174

B6 A6 A5 B5 C7

ODD_PW R 24 R 33 0

3.3VS

*1 0K_ 04

TEMPIN0 MB_THRMDA_SB

R 79 8

R3 3 3

* 0_ 0 4

R3 3 5

* 0_ 0 4

SMD_CPU_T HERM 3,16,27

1 0K _ 04

C

SB_TALERT# C486

B

C487

Q9 *2N3904

T EMP _C OMM

3.3VS

A3 B4 A4 C5 A7

H W MON ITO R

AD16 R5 76

*10 K _0 4

VN I 0/G PI O175 SA TA _X1

VN I 1/G PI O176 VN I 2/G PI O177 VN I 3/G PI O178 VN I 4/G PI O179 VN I 5/G PI O180

AC16

SPI_DATAIN J5 SPI_ DATAOUT E2 SPI_CLK K4 SPI_CS#_SEL K9 HUDSON_ROM_R ST# G2

V IN 6/G BE _ST AT 3/G PI O181 SA TA _X2

7 B 8 B 8 A

VIN 7/ G BE _LED 3/G PI O182

VIN_VD DCR VIN_VD DNB VIN_VDDIO_SUS R 79 9 10 K _0 4 R 80 0 10 K _0 4 R 80 1 10 K _0 4 R 80 2 10 K _0 4 R 80 3 10 K _0 4

NC

SP I _DO /G PI O163

NC

R3 3 7

* 0_ 0 4

E MB_THRMDC_SB

SMC_CPU_T HERM 3,16,27

3.3VS

U2 0

R697

10K_04

7 2 2 G Y

SP I _CLK / GP IO 162 SP I _CS 1#/G PIO 165

* 0_ 0 4

3.3VS

S PI RO M SP I _DI /G PIO 164

330p_50V_X 7R_04 330p_50V_X 7R_04 R3 3 6

5

4

*74AHC1G08GW 1

AP U_T ALERT# 3,27

2 GPU_T ALERT#8, 10

3

RO M_R ST #/ GP IO 161

HUDSON M1A13 Co nnectC7 andD8,thengot oGNDdirectly.

1.8VS

VIN_VDDCR

R34 0

*11K_ 1% _04

R 34 1

*1 0K _ 04

VDDCR_CPU

3.3V C488 R 73 2

R342 10K_04 *0. 1u_16V_Y5V_04

*0 _ 04

R346 R350

D 22 A

R347

RB 75 1 V C

3 SB_PROCHOT#

*1K_04 *10K_04

SB_PROCHOT#_C

U2 1

VIN_VDDNB

8 VDD

5

SPI_DATA OUT R57 3

0_ 04

2

SPI_DATAIN

R38 6

0_ 04

1

SPI_CS#_SEL R57 1

0_ 04

6

SPI_CLK

0_ 04

SI SO

C491 3 W P#

*0.1u_16V_Y5V _04

CE# SCK

7

R57 2

VS S

C490

*4.99K_ 1%_04 VDDCR_NB

R345

*4.99K_ 1%_04

R349 10K_04 *0. 1u_16V_Y5V_04

HSPI_MSO 27 HSPI_CE# 27 HSPI_SCLK 27 1.5V VIN_VDDIO_SUS

R 35 1

*25VF032B C492

R352 10K_04 *0. 1u_16V_Y5V_04

B - 18 HUDSON SATA/ DEBUG IO/ SPI

R344

HSPI_MSI 27

4 HOLD#

1V S

NEAR U19

*10K_04

*1 0K_ 04

Schematic Diagrams

HUDSON POWER DECOUPLING HUDSON POWER DECOUPLING U 19 C

HUDSON-1

3 .3V S

PART3 OF 5

1 .1 V S

P O WER

1 3 1 mA C4 9 4

C4 9 5

C4 96

C 49 3

0. 1u _ 1 0V_ X 5 R_ 0 4 2 2u _ 6 .3V _X 5 R_ 0 8 0 .1 u _1 0 V _ X5R _ 04 0 .1u _ 1 0V _X5 R_ 0 4

1.8 V S R 35 5

0 _ 04

A H1 V6 Y19 A E5 AC2 1 A A2 A B4 A C8 A A7 A A9 AF7 AA 1 9

VDD IO_ 1 8_ F C

V DDIO _33_PC I GP

VDDCR_11

V DDIO _33_PC I GP V DDIO _33_PC I GP

VDDCR_11 VDDCR_11

V DDIO _33_PC I GP

VDDCR_11

V DDIO _33_PC I GP

VDDCR_11

V DDIO _33_PC I GP

VDDCR_11

V DDIO _33_PC I GP

VDDCR_11

V DDIO _33_PC I GP V DDIO _33_PC I GP

C OR ES0

VDDCR_11 VDDCR_11

C5 0 4

C 5 06

V DDIO _33_PC I GP

0 .1 u _ 10 V_ X5R _ 04 4 .7 u _6 .3 V_ X5R _ 06 0 .1u _ 1 0V _X5 R_ 0 4 * 0 .1u _ 1 0V _X7 R _ 0 4 3 .3VS L 86

.

H CB1 0 05KF -121 T20

VDD PL _3 .3 V _ PCIE C 5 11

VDDAN_11_CLK

12/6D el R827

C 51 9

C5 2 0

C5 2 1

* 1 u_ 6 .3 V_ X5 R _0 4 0.1 u _ 10 V _ X5 R_ 0 4 2 2u _ 6 .3V _X5 R_ 0 8 1 u _ 6. 3V_ X 5 R_ 0 4 0 .1 u _1 0 V _ X5R _ 04

3. 3VS

L8 8

.

C 5 27

VDDAN_11_CLK

PART5 OF 5

C5 0 2

C 5 03

.

1.1 V S

T BDm A

L85 C5 0 5

C5 0 7

C 50 8

C5 1 0

.

C 49 8

0 .1 u _1 0 V_ X5R _ 04 1 u_ 6 .3 V_ X5 R _0 4 2 2u _ 6 .3V_ X5 R_ 0 8 0.1 u _ 10 V_ X 5 R_ 0 4 1 u _6 .3 V_ X5R _ 04

V DDIO _18_FC

V1

V DDI O_33_GBE _S

R 35 6

M10

0 _0 4

C 5 33

C 5 34

C5 3 5

C5 3 6

A V DD _U S B

.

HC B1 0 50 KF -12 1T20

6 5 8m A C5 4 2 C 54 3 C 54 4 C5 4 5 C 5 46 0 .1u _ 1 0V_ X5 R_ 0 4 1 u _ 6 .3V_ X 5 R_ 0 4 10 u _ 6 .3V_ X5 R_ 0 8 1u _ 6 .3 V_X5 R_ 0 4 1 0u _ 6 .3 V _X 5 R_ 0 8

VDDAN_11_PCIE

VD DC R_11_GBE _S

VDDAN_11_PCIE

VD DC R_11_GBE _S

L7 L9

R 77 2

* 10 m i _ l s h ort

VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE

V DD IO_GBE _S

VDDAN_11_PCIE

V DD IO_GBE _S

M6 P8

R 77 3

* 10 m i _ l s h ort

VDDAN_11_PCIE

SE RI ALAT A

3 .3V

3.3V_S5I /O

V DDP L_33_SA TA

VD DIO _33_S V DDA N_11_S AT A V DDA N_11_S AT A

VD DIO _33_S VD DIO _33_S

V DDA N_11_S AT A

VD DIO _33_S

V DDA N_11_S AT A

VD DIO _33_S

V DDA N_11_S AT A V DDA N_11_S AT A

VD DIO _33_S VD DIO _33_S

V DDA N_11_S AT A

VD DIO _33_S

A 21 D21 B 21 K 10 L10 J9 T6 T8

32mA

C5 2 9

C 5 30

C5 3 1

1u _ 1 0V_ Y 5V _0 6 * 0. 1u _ 1 0V_ X7 R_ 0 4 1u _ 1 0V _Y 5 V_0 6

CORE S 5

A18 A19 A20 B18 B19 B20 C1 8 C2 0 D1 8 D1 9 D2 0 E19

F 26 G26

VDDCR_11_S

V DDA N_33_U SB _S

VDD CR _ 1.1 V

VDDCR_11_S

V DDA N_33_U SB _S

M8

V DDA N_33_U SB _S V DDA N_33_U SB _S

V DDI O_AZ _S


A 11 B 11

VDDCR_11_USB_S VDDCR_11_USB_S

V DDA N_33_U SB _S V DDA N_33_U SB _S V DDA N_33_U SB _S

M21

VD DP L_33_SY S P LL


VDD PL_11_ SYS _S

V DDA N_11_U SB _S

V DDA N_33_H WM_S

V DDA N_11_U SB _S VD DX L_33_S

R 36 1

VDD IO_ AZ

C 53 7

T BDm A 1 9 7m A

1 .1 V

4 7m A

L22

62 m A

F 19

17 m A

D6

5mA

L20

TB D m A

VD DPL _ 3 .3V

L90

VDD PL _1 .1 V

C 53 9

A VD D_ U SB

C5 4 0

D8 M 19

.

H CB 1 0 0 5K F -12 1 T 20

P 21 P 20 M 22 M 24 M 26 P 22 P 24 P 26 T 20 T 22 T 24 V 20 J 23

C 5 41

10 u _ 6.3 V_ X5 R_ 0 8 0 .1u _ 1 0V_ X5 R_ 0 4 0 .1 u_ 1 0 V _ X5 R _0 4

VD DA N _ 3.3 V _ H W M

3 .3 V

VDD XL_ 3 .3 V

L92 C5 4 7

.

H CB 1 0 0 5K F -12 1 T 20

C 54 8

0.1 u _ 10 V_ X5 R_ 0 4 1 u_ 1 0 V_ Y5 V_ 06

V D DAN _ 1.1 V_ U SB

H CB 10 05KF -121 T20

Y4

C5 3 8

1u _ 6 .3V _ X5 R_ 0 4 1 u _6 .3 V_ X5R _ 04

VDD CR _ 1.1 _ USB

T BDm A

.

0 _0 4

1 .1 V

V DDA N_33_U SB _S

VDDPL_33_USB_S

C1 1 D1 1

1 1 3m A

HU DS O N M 1 A1 3

L 93

A9 B 10 K 11 B9 D 10 D 12 D 14 D 17 E9 F9 F 12 F 14 F 16 C9 G 11 F 18 D9 H 12 H 14 H 16 H 18 J 11 J 19 K 12 K 14 K 16 K 18 H 19

R7 7 1 * 10 m il _ s h ort

V DDP L_33_PC I E

US BI /O

5 6 7m A

1 u_ 6 .3 V_ X5 R _0 4 0.1 u _ 10 V_ X 5 R_ 0 4 2 2u _ 6 .3V _X5 R_ 0 8 1 u_ 6 .3 V _ X5 R _0 4 0 .1 u _1 0 V_ X5 R _0 4

3 .3 V

H CB 1 0 0 5K F - 12 1 T 2 0

1 .1V

HC B1 0 50 KF -12 1T20 C 5 32

Y 14 Y 16 A B 16 A C 14 A E 12 A E 14 AF 9 A F 11 A F 13 A F 16 AG8 AH7 A H 11 A H 13 A H 16 A J7 AJ 11 AJ 13 AJ 16

1u _ 6 .3 V_X5 R_ 0 4 10 u _ 6.3 V_ X5 R_ 0 8 0 .1u _ 1 0V_ X5 R_ 0 4 1 u _ 6.3 V_ X5 R_ 0 4 0 .1 u_ 1 0 V_ X5 R _0 4

A VDD _SA TA

1 .1V S

L 91

AD1 4 AJ2 0 AF 1 8 AH2 0 AG1 9 AE 1 8 AD1 8 AE 1 6

C 52 8

* 0 .1u _ 1 0 V_X7 R _ 0 4 1u _ 1 0V _ Y 5V _0 6

L 89

V DDIO _18_FC

C 50 1

VDDAN_11_PCIE

93mA VDD PL _3 .3 V _ SA T A

HC B 10 05 KF -12 1T 2 0

VDDAN_11_CLK VDDAN_11_CLK

C5 0 0

GBE L AN

U2 6 V22 V26 V27 V28 V29 W22 W26

60 0 m A C5 1 8

VDDAN_11_CLK

V DDIO _18_FC V DDIO _18_FC

VD DR F_GBE _S

AE 2 8

1 .1 VS

C 51 7

VDDAN_11_CLK

PCI EX PRE SS

1 u _1 0 V _ Y5 V _ 0 6 0 .1u _ 1 0V _X 5 R_ 0 4

12/9

VDDAN_11_CLK

43mA

C 51 2

K 28 K 29 J28 K 26 J21 J20 K 21 J22

VDDAN_11_CLK

FLA SH I /O

AF 2 2 AE 2 5 AF 2 4 AC2 2

HUDSON-1 C4 9 9

+1 .1 V_ CKV DD

CLK GENI/O

V DDIO _33_PC I GP

C 4 97 71mA

U 19 D 51 0 m A

V DDIO _33_PC I GP

PC/IGPI O I / O

C 50 9

N13 R15 N17 U13 U17 V 12 V 18 W 12 W 18

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S

V SSIO _SA TA V SSIO _SA TA

VS S VS S

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S


VS S VS S

V SSIO _SA TA

VS S

V SSIO _SA TA

VS S


VS S VS S

V SSIO _US B

VS S VS S

V SSIO _US B V SSIO _US B

VS S VS S


VS S VS S

V SSIO _US B

VS S

V SSIO _US B

VS S

V SSIO _US B

VS S


VS S VS S

V SSIO _US B

VS S

V SSIO _US B

VS S

V SSIO _US B V SSIO _US B V SSIO _US B

VS S VS S GR OU ND

VS S

V SSIO _US B

VS S

V SSIO _US B

VS S

V SSIO _US B

VS S


VS S VS S

V SSIO _US B

VS S

V SSIO _US B

VS S


VS S VS S

V SSIO _US B

VS S

V SSIO _US B

VS S

V SSIO _US B

VS S

V SSIO _US B

VS S VS S VS S

E FUS E

VS S

A J2 A 28 A2 E5 D23 E 25 E6 F 24 N15 R13 R17 T10 P 10 V 11 U15 M18 V 19 M11 L12 L18 J7 P3 V4 A D6 A D4 AB 7 A C9 V8 W 9 W 10 A J2 8 B 29 U4 Y18 Y10 Y12 Y11 A A11 A A12 G4 J4 G8 G9 M12 A F 25 H7 A H2 9 V 10 P6 N4 L4 L8

Sheet 18 of 41 HUDSON POWER DECOUPLING

VS S V SSA N_H WM V SSX L

V SS PL_SY S

V SSIO _PC I ECLK V SSIO _PC I ECLK

VS SIO_P CI EC LK VS SIO_P CI EC LK





V SSIO _PC I ECLK

VS SIO_P CI EC LK

V SSIO _PC I ECLK

VS SIO_P CI EC LK

V SSIO _PC I ECLK

VS SIO_P CI EC LK



V SSIO _PC I ECLK

VS SIO_P CI EC LK

V SSIO _PC I ECLK


M20

H23 H26 A A21 A A23 A B23 A D2 3 A A26 A C2 6 Y20 W 21 W 20 A E26 L21 K 20

H U D SON M1 A1 3 C 54 9

C5 5 0

0 .1 u_ 1 0 V_ X5 R _0 4 1 u _ 10 V_ Y 5V_ 0 6

3. 3 V

3 .3 V S 3 .3V

VD DPL _ 3. 3V

VD DIO _ AZ

1 .5 V

L 95 R 36 2

0 _0 4

.

H CB1 0 05KF -12 1T 20

VDD PL_ 1 .1 V

C 55 4

V DDA N _ 3 . 3V _H W M

L94

.

H CB1 0 05K F - 12 1 T20 C 5 51

L 96 C 5 53

R 36 3

1.1 V

.

H CB1 0 05 KF -121T 20

C 55 2

1 u _ 10 V _ Y 5V _ 0 6 0.1 u _ 1 0V_ X5 R_ 0 4 C5 5 5

C 5 56

* 0_ 0 4 C5 5 7

1 u _ 1 0V_ Y 5V_ 0 6 *0 .1 u _ 10 V_ X7R _ 04

1u _ 1 0V _Y 5 V_0 6 *0 .1 u _1 0 V_ X 7R _ 04

1 u _ 10 V_ Y 5 V_ 0 6

HUDSON POWER DECOUPLING B - 19


Schematic Diagrams

POWERGOOD/ TPM 3 .3 V

4 1

4

33 1 .1 V_ P W RG D 16

U2 2 B 7 4 LVC 0 8P W 6

5

SY S_ RS T#

7

3 .3 V

3 5 P W RG D_ VC ORE

3 .3 V

3 .3 V

R7 74

3 .3 V R 77 5

34 1 .8 V_ P W RG D

4 1

4 1

R 77 6

3 2 ,35 D DR 1.5 V_ P W R GD 1 6 ,2 6, 27 ,3 0

U2 2 A 7 4 LVC 0 8P W

0_ 0 4

12

1

* 0_ 0 4

3

2

SUS B#

4 1

U 22 D 7 4 LVC 0 8PW

9

11

U2 2 C 74 L VC0 8 P W

10 K_ 0 4

8

10 7

7


7

TPM 1.2 1 5 ,2 7 1 5 ,2 7 1 5 ,2 7 1 5 ,2 7 15

L P C_ A D0 L P C_ A D1 L P C_ A D2 L P C_ A D3

16

R 814 R 816 R 817 R 815

R 818 R 819 R 820

* 0_ 0 4 2 2 * 0_ 0 4 1 6 * 0_ 0 4 2 7 15

21

28

S4 _ ST ATE # T PM _ BAD D

9

T PM _ PP

7

U50 L A D0 L A D1 L A D2 L A D3 L CL K

V DD 1 V DD 2 V DD 3

8

C8 7 6

10 19 24

SY S _PW R OK

1 u_ 6 .3 V_Y 5 V _0 4

*1 0 K_ 04

L P CPD #

PP

T E ST I

C8 7 8

3 .3 VS VS B

5 C8 8 0

G PIO GP IO 2

6 2

GN D_ 1 GN D_ 2 GN D_ 3 GN D_ 4

*0 .1 u _1 6 V_ Y5 V _ 04

T P M3 0 04 T P M3 0 05

13

XTALI

14

XTALO

X T A LI XT AL O

N C_ 1 N C_ 2 N C_ 3

C 8 77

4 11 18 25

* SL B 96 3 5 TT

X12 4 3

* 3 2.7 6 8KHz 1 2

X13 4 3

* 3 2.7 6 8KHz 1 2

C8 81

C8 8 2

*1 8p _ 5 0V_ N PO_ 0 4

*1 8 p_ 5 0 V _N P O_ 0 4

Asserted beforeentering S3 LPCreset t iming: LPCPD# inactive to LRST# inactive32~96us

TPM_PP

HI:ACCESS LOW: NORMAL( Internal PD)

TPM_BADD

HI:4E/4FH LOW: 2E/ 2FH

C 87 9

*0 .1 u _1 6 V_ Y5 V _ 04 *0 .1 u_ 1 6 V_Y 5 V _0 4 *0 .1 u _1 6 V _ Y 5 V_ 04 * 1u _ 1 6V_ X5 R_ 06

TPM

L F RAM E # L RESE T# SE R IRQ C LKR UN #

T E ST B I/B AD D

T P M3 0 0 1 1 T P M3 0 0 2 3 T P M3 0 0 3 1 2

B - 20 POWERGOOD/ TPM

SB _ P W RO K

0 _0 4

R3 6 7

3 .3 VS

* 0_ 0 4 2 6 * 0_ 0 4 2 3 * 0_ 0 4 2 0 * 0_ 0 4 1 7

PC L K_T PM

15 ,2 7 LP C_ F RAM E # 1 5 ,23 ,2 4 ,26 ,2 7 BUF _ PL T _R ST # 15 ,2 7 S E R I R Q 1 5 PCI_ C LK R UN #

0 _0 4

R 36 5 C 84 1

ON

Sheet 19 of 41 POWERGOOD/ TPM

R 36 4

13

PCL K_ TP M

R 82 1

* 33 _ 04

C 8 83

3 .3 VS T PM_ PP

R 82 2

* 10 K _ 04

T PM_ BAD D

R 82 3

* 10 K _ 04

R 82 4

* 10 K _ 04

*1 0 _p 50 V_0 4

SB _ PW R GD

16

AL L _ SYS _ PW R GD 2 0 ,2 7

Schematic Diagrams

LVDS, INVERTER 3 .3 VS

PANEL CONNECTOR

R577, R578W250BAQ Delete R57 7 R57 8

J_LCD1 For sin gle channel J_LCD2 For du al channel

2 .2 K _ 0 4 2 .2 K _ 0 4

EDID Mode

VIN_ L CD

12/7

J _ LC D1

80mils

1 3 5 7 9 11 13 R L V DS L- C LK N15 R L V DS L- C LK P17 19 21 R L VDS-L 1 N R L VDS-L 1 P 23 25 R L VDS-L 0 N 27 29 R L VDS-L 0 P

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

V IN_ L CD

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

LVD S_ DAT A LVD S_ CL K BRIG HT NE S S

BR IGH TN ES S 2 7

INV_ BL ON

3 .3 V

RL V DS -L2 N RL V DS -L2 P

D2 3 BRIG HT N ESS 3.3 VS

AC

C RL V D S -LC L KN RL V D S -LC L KP

C 5 66 * 0 .1u _ 1 6V_ Y 5V _ 0 4

A

*B AV99 R E CT IF IER

RL V D S -L1 N RL V D S -L1 P RL V D S -L0 N RL V D S -L0 P

C5 6 1

87 2 1 6-3 0 0 6

0 .1u _ 1 6V _ Y 5V _0 4 P LV D D C5 6 2

C5 63

4.7 u _ 6.3 V_ X5 R _ 06

0.1 u _ 16 V_ Y5 V_ 0 4

2 1 G G

J_ L CD 2

12/7

7 7 7 7

T XCL K_ UN TXC LK _ U P T X OU T_ U 1N TX O UT _U 1 P

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

LVD S_ DAT A LVD S_ CL K

1 2 2 d d n n 4 G G 6

BRIG HT NESS

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

INV_ B L ON RL VDS-L 2 N RL VDS-L 2 P

3 .3 VS PL V D D

2A

T XO UT _ U2 N 7 T XO UT _ U2P 7 T XO UT _ U0 N 7 T XO UT _ U0P 7

* 87 2 1 6-4 0 0 6

Sheet 20 of 41 LVDS, INVERTER

12/7

PANEL POWER

3.3 V S VIN

VI N

.

3 2 1

Q46 R5 8 6

VIN_ L CD

L1 *0 _ 0 6

P 20 0 3 EV G

2A 8 7 6 5

3.3 V

3A

C 56 5 9 5 5 C

R2 3 8

1 M_ 0 4

4

R2 28 *1 0 K_0 4

C1 8

1108

D

*0 .1 u _5 0 V_ Y5 V _ 0 6

G

Q49 M T N7 0 02 Z H S3

EN AVDD

6

2G

Q 45 A 1 *M TD N7 0 02 Z H S 6 R

S

*2 00 _ 1 %_ 0 4 3

D

D

5G S Q4 5 B 4 *MT D N7 0 02 Z H S6R

S

6 0 _ V 5 Y _ V 0 5 _ u 1 . 0

0 6 5 C

C 56 4

0 .1u _ 1 6V_ Y 5V_ 0 4

P L VDD

*0 .0 1u _ 1 6V_ X7 R_ 0 4

U2 4 4 5

4 0 _ R 7 X _ V 0 5 _ u 1 0 . 0

3 NB_ E N A VDD

R 69 8

0 _0 4

7 VGA _D IGO N

R 69 9

* 0_ 0 4

EN AV DD

3

R3 8 7 1 00 K_ 0 4

VIN VIN

EN

VOU T

G ND

1

Default UMA

2A R LV DS-L 0 N

2 R LV DS-L 0 P

AP L 3 5 12 A R LV DS-L 1 N

W250BAQR698 Off, R699On

G5243A 6-02-05243-9C0 APL3512A 6-02-03512-9C0

R LV DS-L 1 P

R LV DS-L 2 N

R LV DS-L 2 P

27

R 38 8

BKL_ EN

* 1 0 mil _ sh or t _ 0 4

INVERTER CONNECTOR

BKL _ EN_ R

R 38 9

C5 6 7

* 10 0 K_ 04

*0 .4 7u _ 10 V _ Y 5V_ 0 4

3 .3V 4 1

1 3 8

B L ON GP IO 7_ BL O N

R 7 00

0_04

R 7 01

* 0_ 0 4

3 .3 V U 2 5A 7 4 L VC0 8 PW 3

2

4 1

Z 12 0 1

4

3.3 V

R LV DS-L CL KP

U2 5 B 74 L VC0 8 PW 6

*0 .1 u _1 6 V _ Y5 V _ 04

5

L VD S _D AT A

7

R 39 0

7

L VD S _C L K 4 1

16

SB_ BLO N

Z 1 20 2

3 .3 V R 3 91

16 ,2 7 ,29 L ID _SW #

L VDS -L 0 N

R 6 03

* 0 _0 4

T XOUT _ L 0N

R 6 04

0_04

L VDS -L 0 P

R 6 05

* 0 _0 4

T XOUT _ L 0P

R 6 06

0_04

L VDS -L 1 N

R 6 07

* 0 _0 4

T XOUT _ L 1N

R 6 08

0_04

L VDS -L 1 P

R 6 09

* 0 _0 4

T XOUT _ L 1P

R 6 10

0_04

L VDS -L 2 N

R 6 11

* 0 _0 4

T XOUT _ L 2N

R 6 12

0_04

L VDS -L 2 P

R 6 13

* 0 _0 4

T XOUT _ L 2P

R 6 14

0_04

LV D S-L CL KN

R 6 15

* 0 _0 4

TX CL K_ L N

R 6 16

0_04

LV D S-L CL KP

R 6 17

* 0 _0 4

TX CL K_ L P

R 6 18

0_04

LV D S_ DD C_ DAT A

R 6 19

* 0 _0 4

SDA

R 6 20

0_04

LV D S_ DD C_ CL K

R 6 21

* 0 _0 4

SCL

L VDS-L 0 N 3 T XO UT _L 0N 7 L VDS-L 0P 3 T XO UT _ L 0P 7 L VDS-L 1 N 3 T XO UT _L 1N 7 L VDS-L 1P 3 T XO UT _ L 1P 7 L VDS-L 2 N 3 T XO UT _L 2N 7 L VDS-L 2P 3 T XO UT _ L 2P 7 L VDS-L C LKN 3 T XC L K_LN

7

L VDS-L C LKP

3

T XC L K_LP 7

9

U2 5 C 7 4 LVC 0 8PW 8

L V DS_ DD C_D ATA SDA

3

8

L V DS_ DD C_ C LK 3 SCL

8

IN V_B LO N

Z 1 20 3 10

* 10 0K _ 04 4 1

1 9 ,27 A L L _ S YS_ P W R G D

0_04

C5 6 8

1 0 0K _0 4

W250BAQ R700 Off, R701 On

R LV DS-L CL KN

R 6 02

12

U2 5 D 74 L VC0 8 PW 11

13

7

R 3 92

C5 6 9

* 1 M_ 0 4

0 .1u _ 1 6V _ Y 5V _ 0 4

7

LVDS, INVERTER B - 21


Schematic Diagrams

CCD/ 3G MINI CARD 3G(Port 6) Layout Show "3.5G(HSDPA)" Note

Layout? 1. SIM? ? ? ? ? ? ? ? (10mil) 2. ? ? ? ? ? ? ? ? GND 3. SIM hold ? ? ? ? ? GND? ? 4. SIM CONN ? ? MINI CARD CONN

3 G_ 3 .3 V J _3 G 1 1 3 5

W AKE# CO EX1 CO EX2

7 11 13 9 15

CL KRE Q # REF C LKREF C LK+ GN D0 GN D1

60mils

2 6 8 10 12 14 16

3 .3 V AUX_ 0 1.5 V_ 0 U IM_ PW R UIM _D AT A UIM _C L K UIM _R ESE T UIM _VP P

U IM_ PW R U IM_ DA T A U IM_ CL K U IM_ RS T U IM_ VP P

C5 9 2

C5 9 4 0. 1u _ 16 V _ Y5 V _ 0 4

+C5 9 3

0 .1u _ 1 6V_ Y 5V_ 0 4

2 20 u _ 4V_ V _ B

4 GND 5

KEY 21 27 29 27

GN D2 GN D3 GN D4

35 23 25 31 33

3G _ DET #

3 G_ 3 .3 V

C5 9 8

C5 9 9

0 .1u _ 1 6V_ Y 5V_ 0 4

1 0u _ 1 0V_ Y 5V _ 0 8

GND GND GND GND GN D1

GN D1 1 P ET n0 P ET p0 P ERn 0 P ERp 0

17 19 37 39 41 43 45 47 49 51

18 26 34 40 50

6 7 8 9 0

Re s erv e d 0 Re s erv e d 1 GN D1 2 3.3 VAU X_ 3 3.3 VAU X_ 4 GN D1 3 Re s erv e d 2 Re s erv e d 3 Re s erv e d 4 Re s erv e d 5

SIM CONN

20 22 30 32 36 38

W _D IS ABL E # P E RSET # SM B_C L K SM B _D AT A USB_ D U SB_D +

3 G _E N

L106 2

*W C M2 0 12 F 2 S-1 61 T 0 3-s h o rt 1 USB_ P N 9 1 6

3

24 28 48 52 42 44 46

3 .3 V AUX_ 1 1.5 V_ 1 1.5 V_ 2 3 .3 V AUX_ 2 L E D_ W W AN # LED _ W LAN # L ED_ W PAN #

R 42 0

27

R 41 9

4

* 15 m il_ sh o rt_ 06

U S B _ PP 9

1 6

3 G_ 3 .3 V

UI M _C LK

R4 2 1 *1 0 mil_s h o rt_0 4

C 86 8

60mils

3G _ 3.3 V

0 .1 u_ 1 6 V_Y 5 V_0 4

LOCK (TOP VIEW)

C3 C2 C1

UIM _ RST UIM _ P W R

U IM_ CLK U IM_ RST U IM_ P W R

C6 0 5

C6 0 0

8 89 1 0 -52 0 4 M-0 1

U IM_ DAT A U IM_ VP P U IM_ GN D

David 8/25 C7 C6 C5

OPEN

*2 2 p _5 0 V _ NPO_ 0 4

*0 .1 u _1 6 V_ Y5 V_ 04

* 4 . 7 K _ 04

J _ SIM1

+ C6 01

C 1 77 0 6 61 -1 S IML OC K

R4 22 *1 0m il_s h or t_0 4

UI M _ DA T A UIM _ VPP

C6 02

C6 0 3

C 60 4

*2 2p _ 5 0V_ N P O_ 0 4

*2 2 p_ 5 0V _N P O_ 0 4

* 22 p _ 50 V_ NPO _0 4

Sheet 22 of 41 CCD/ 3G

22 0 u _4 V_ V_ B

AO3409? ? ?

CCD

3G POWER

5V

Q10 MT P3 4 03 N 3 S D

3 .3 V_ 3G 3 .3 VS 3 .3 V

R78 9

* 0_ 0 6

R79 0

0_ 06

5V_ C CD

48 mil

3G _3 .3 V Q32 A O3 41 5 S

3A 120mils

MJ_CCD1

C 6 10

3A 120mils

D

1 u _ 6.3 V_ Y5 V_ 0 4

C6 1 1

1 u_ 6 .3 V_Y 5 V_0 4 C5 9 6

C 8 57

1 u_ 6. 3 V _Y 5 V _ 0 G 4

R 42 6

C 6 13

C6 14

* 1u _ 6 .3V_ Y 5V_ 0 4

0 .1 u _1 6 V_ Y 5 V _ 04

1u _ 6.3 V _ Y5 V _ 0 4

1

5

R4 2 4

27 3

D

6

D

5 G Q3 3A

S RT 3 K4 4M

J _ CCD 1 D

1 0 _ 06

1 0 0 K_ 0 4

2 G

C 61 2

10 0 K_ 04

3 3 0 K _0 4

R 7 92

2 0K_ 1 % _0 4

3G _ POW ER

R4 23

1 00 K_ 0 4 0.1 u _1 6 V_ Y 5 V_ 04 R7 9 1

27

0 .1 u _1 6 V_ Y5 V_ 04

C5 95

1 0u _ 10 V _ Y5 V _ 0 8

R 79 3

G

C8 4 6

C CD _EN

Q1 1 MT N7 0 0 2Z H S3

G

C CD_ EN

S

From H8 default HI

16 US B_ PN5 16 US B _PP 5 2 7 C CD _D ET #

CC D_ DET #

1 2 3 4 5 8 5 20 5 -0 50 0 1

Q 3 3B

S R T 3K 4 4 M

4

1

From SB GPIOPin default HI P o w e r P l a n e : S u sp e n d S3: Defined

ADDR128,Q2 SolutionFor PDA BUG-Wh en Batte ry discharge to shutdown, the CMOS sometimes loss.

1A U4 7 4 5 C CD _E N 3

V IN V IN

EN

VO UT

GN D

1

1A 2

*G 52 4 3 A

CCD/ 3G B - 23


Schematic Diagrams

MINI PCIE/ SATA HDD/ ODD MINI CARD (WLAN,Port 5) 20 mil

3 .3 V C 84 7

Layout Show "WLAN(Wimax, 802.11N)" Note

0 .1 u _1 6 V_ Y5 V _ 04 J_ M INI1 P CIE _ WAK E #

1 6,2 3 ,2 6 P CIE _ W AK E# R 451

3 .3 VS

R 50 9

* 0_ 0 4

1 0 K _0 4 W LAN _ CL KREQ #

1 6 W L A N_ CL KR EQ# 15 C LK _ P C IE _ W LA N# 15 C LK _PC IE_ W L AN

1 3 5 7 11 13 9 15

W AK E# C OE X1 C OE X2

3 .3 V AU X_ 0 1.5 V_ 0 U IM_ P W R UIM _D AT A UIM _ CL K UIM _R E SE T UIM _ VP P

C L K RE Q # R EF C LKR EF C LK+ G ND 0 G ND 1

GN D5

2 6 8 10 12 14 16

20 mil R 45 2

* 0_ 04 R 49 6 R 72 2 R 50 8

VD D3 B T _O N 8 0 CLK

0 _0 4 1 00 K _ 0 4 0 _0 4

1 5, 2 8 27

3 IN 1

4

KEY 21 27 29

15 15 15 15

27 ,2 8 27

27 W LA N _ DET # P C IE _ RX N3 _ W L A N P C IE _R XP 3_ W L A N P C IE _ T XN 3_ W L A N P C IE _T XP 3 _ W LA N

BT _EN 3 IN1

3IN 1

R 45 4

* 0_0 4

R 73 8

* 0_0 4

VD D3 3 .3 V 1 5,2 8 2 7,2 8

B T_ ON BT _E N

S1 S2 S3 S4 S5 S6 S7

R455

* 10 K _ 0 4

3.3 V

R49 4 R45 6 R45 7 R 45 8

* 10 K_ 04 * 10 K_ 04 * 0_ 04 0 _0 4

17 19 37 39 41 43 45 47 49 51

GN D6 GN D7 GN D8 GN D9 GN D1 0

G ND 1 1 P ETn 0 P ETp 0 P ERn 0 P ERp 0

W _D IS AB L E # P E RS ET # SM B_ CL K S M B _D AT A USB _D U SB _ D+

R e se rv e d 0 R e se rv e d 1 G ND 1 2 3 .3 V AU X_ 3 3 .3 V AU X_ 4 G ND 1 3 R e se rv e d 2 R e se rv e d 3 R e se rv e d 4 R e se rv e d 5

3 .3 V AU X_ 1 1.5 V_ 1 1.5 V_ 2 3 .3 V AU X_ 2 L ED_ W W AN# LED _ W L AN# L E D _W P AN#

18 26 34 40 50

R4 5 3 *1 0 K_0 4

20 22 30 32 36 38 24 28 48 52 42 44 46

3 .3 V S

W L AN_ E N 2 7 ,2 8 BUF _ P L T _R ST # 1 5 ,1 9, 23 ,2 6 ,27

BUF _PL T _ RST #

R 7 25 R 7 26 3.3 V AU X_1

20 mil

BT _D E T# 2 7 ,2 8 US B_ P N 2 1 6 US B_ P P2 1 6

* 10 m i _l s ho rt * 10 m i _l s ho rt

20 mil

R72 7

0_04

Port 2

3.3 V

3 .3 V W LAN _ LED # 27,2 8

R 73 9

* 0_0 4

8 0 CLK

27

Sheet 24 of 41 MINI PCIE/ SATA HDD/ ODD

SATA ODD J _ OD D1

SA TA _ T XP0 SA TA _ T XN0

C6 5 3 C6 5 4

0 .0 1u_ 16 V_ X7 R_ 04 0 .0 1u_ 16 V_ X7 R_ 04

SA TA _ R XN 0 SA TA _ R XP0

C6 5 5 C6 5 8

0 .0 1u_ 16 V_ X7 R_ 04 0 .0 1u_ 16 V_ X7 R_ 04

S ATA T XP0 1 7 S ATA T XN0 1 7 S A T AR X N 0 S ATA R XP0

1 7 17

3 .3V S P1 P2 P3 P4 P5 P6 P7 P8 P9 P1 0 P1 1 P1 2 P1 3 P1 4 P1 5

* 1 0 m il_ sh o rt * 1 0 m il_ sh o rt

G ND 2 G ND 3 G ND 4

BE L LW E TH E R 8 0 0 03 -1 0 21

SATA HDD J _ HD D1

R723 R724

35 23 25 31 33

C6 6 1 C6 6 2 *0 .0 1 u_ 1 6 V _ X7 R_ 0 4 *1 0 u _1 0 V _ Y5 V _ 08

H DD _N C0 H DD _N C1 H DD _N C2 H DD _N C3

A L L T OP -C 16 6 N5 -1 2 20 5 -L A L L T O P -C1 6 6 N 5 -1 2 2 0 5 -L

W240BU6- 20-43730- 122 W250BUQ 6- 20-43750- 022

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0

4 0 _ V 5

1 7 6 C

2 7 6 C

3 7 6 C

4 7 6 C

Y _ V 3 . 6 _ u 1

5V S

8 0 _ R 5 X _ V 3 . 6 _ u 2 2

8 0 _ R 5 X _ V 3 . 6 _ u 2 2

5 7 6 C

6 7 6 C

7 . 5 * 6 . 6 _ V 3 . 6 _ u 0 2 2

S1 S2 S3 S4 S5 S6 S7

P1 P2 P3 P4 P5 P6

SA T A _ TX P1 SA T A _ TX N 1

C 65 6 C 65 7

0.0 1u _1 6V_ X7 R _0 4 0.0 1u _1 6V_ X7 R _0 4

SA T A _ RX N1 C 65 9 SA T A _ RX P1 C 66 0

0.0 1u _1 6V_ X7 R _0 4 0.0 1u _1 6V_ X7 R _0 4

R 70 5

0_ 0 4

S A T A R X N1 1 7 S AT ARXP1 17

OD D_DE T EC T#

O DD_ D ETE CT # 16

3 .3 VS

OD D_ 5 V R 70 6

S AT ATXP1 1 7 S AT ATX N 1 1 7

* 1 0 K _ 04 5VS

C 1 8 5 53 -1 1 30 5 -L PIN G ND 1 ~ 2= G ND

G

*M TN 70 0 2 Z HS3

Q7

S

OD D_ 5 V R 70 2

D

0 _ 06 Q3 0

O DD _D A # _FC H 1 6

S

D * AO3 4 0 9

R 70 3 * 1M _ 04

+

C8 4 5

G

*1 00 0 p _5 0 V _ X7 R _0 4

0 7 6 C D

17

OD D_ P W R

R70 7

R 70 4 *1 0 K_0 4 Q 31 * MT N7 0 02 Z H S3

* K 1 _0 4 G S

5 VS

OD D_ 5 V C6 77

C 6 78

C 67 9

0.0 1 u _1 6 V_ X7 R _0 4

0 .0 1 u_ 1 6 V _X7 R_ 0 4

0 .0 1u _ 1 6V _X 7 R_ 0 4

12/6Reserve C6 6 3 *0 .1 u _1 6 V_ Y5 V _ 04

C 66 4 0 .1 u _1 6 V _ Y5 V _ 04

C6 6 5 0.1 u _ 16 V_ Y5 V_ 0 4

C6 6 6 1 u_ 6 .3 V _ Y5 V_ 04

C 66 7

C 66 8

1 0 u _1 0 V_ Y5 V_ 08

+

C6 6 9 * 22 0 u _6 .3 V_ 6.6 * 5.7 *0 .1 u _1 6 V _ Y 5 V_ 04

MINI PCIE/ SATA HDD/ ODD B - 25


Schematic Diagrams

AUDIO CODEC AL C261C AUDIO CODEC

ALC269 VB VT1802P

PVD D1 _ 2

R 46 0

1. 5VS

* 0_ 04

R46 1

3 .3VS

PD#Control AZ_RST# For 3 .3V HDA Link De-pop

5 VS

C 6 80 1 0 u _1 0 V_ Y5 V _ 0 8

DVD D_ IO

For 3.3V HDA Lin k. 3 .3 VS_ AUD


5 VS R 4 59

For 1 .5V HDA Link.

Layout note: GND and AUDG space is 60mils ~ 100mils

0 _ 06

C 68 1 0 .1 u_ 1 6 V_ Y 5 V_ 04

* 1 0 m il_ s ho rt

VT1802P L75,C718 ? ? ? C6 8 2 1 0 u_ 1 0 V_Y 5 V _ 08

C6 8 3 0 .1 u _1 6 V_ Y 5 V_ 04

C 68 4 * 1 0u _ 1 0V_ Y 5V_ 0 8

C6 8 5 *0 .1 u _1 6 V_ Y5 V_ 0 4

ANAL OG

L 1 0 91

DIGITAL

5 VS_A UD

L 11 0 3.3 VS_ AU D H CB 1 0 0 5K F -12 1 T 2 0 1 2

EMI Requ ire

L 11 1 H CB 1 0 0 5KF -12 1 T 20 1 2

5 VS

C6 8 8

C6 8 9

C 69 0

C 6 91

C6 9 2

C6 9 3

C 69 4

C6 9 5

0 .1u _ 1 6V _Y 5 V_0 4

10 u _ 10 V_ Y5 V_ 0 8

0 .1 u _1 6 V_ Y 5 V_ 04

0 .1 u _ 16 V_ Y5 V_ 0 4

1 0 u_ 1 0 V_Y 5 V _ 08

0.1 u _ 16 V_ Y 5V_ 0 4

1 0 u _1 0 V_ Y5 V _ 08

1 u_ 6 .3 V_ Y 5 V_ 04

2

* H CB 1 0 0 5K F - 1 2 1 T 20

A UDG

J P1

* 10 m il _ s ho r t

J P2

* 10 m il _ s ho r t

C 68 6

0 . 1 u_ 1 6 V _Y 5V _ 0 4

C 68 7

0 . 1 u_ 1 6 V _Y 5V _ 0 4

A UDG

R 4 62 D3 3 BAT 54 AW G H 1 A

H DA_ R ST#

Sheet 25 of 41 AUDIO CODEC ALC261C

5VS

1 0 K_ 04

R 46 6

PD#

A

D

S

S

40 41

SPKO UT L + SPKO UT L -

Please Let LC Filter t o g e t he r a n d c l o s e t o Codec.IF Speaker wire length is less than 8000mils It don't need the LC Filter.

Q12 *BSS1 3 8 _N L

HD A_ RST #G

AZ_RST# Fo r 1.5V HDA L ink De-pop

PD # Q 13 * MT N7 0 0 2Z HS3

G

9

1 D D V D

4

D

* 10 0 K _ 0 4

1

U 32

C 3

2

2 7 KBC _M UT E#

9 6 3 4

O I D D V D

5 8 2 3

2 1 D D D D V V P P

2 1 D D D D V V A A

L INE2 -L L INE2 -R M IC2 -L MIC2 -R

SPKO UT RSPKO UT R+

44 4 5 SPK-R SPK-R + 47 SPD IF C2 /EAPD 48 SPD IF O C O D E C _ G P I O 02 GP IO0 -DM IC-D AT C O D E C _ G P I O 13 GP IO1 -DM IC-C L K

S en s e -B

EAPD SPDI F O

J DR EF M ON O-O UT

ANALOG

DIGITAL 5

2 2p _ 05 V _ N P O _ 0 4

SD ATA- OUT

M IC1 -L MIC1 -R L INE1 -L L INE1 -R

6 1 6 H DA_ BIT CL K 16

HDA _SD IN0

16

H DA_ SY NC

16

BIT -CL K R 4 71

2 2 _0 4

10 H DA_ R ST#

HD A_R ST #

D 28 BAT 5 4 CW G H

16

KBC_ BEEP HDA _SP KR

11

BE EP_R

PC BEEP 27

8

AZ _SD I N0 _ R

1

A

2

A

C 3

12

C7 0 6 BEEP

R 4 77

4 7 K _0 4

FOR VOLUMN ADJUST

1u _ 6 .3V _Y 5 V_0 4

BEE P_C

C7 0 9

4.7 K_ 0 4

10 0 p _5 0 V_ NPO _ 04

LD O_ C AP M IC1 -VR EF O-R MIC 2- VREF O

SY NC RE SET#

L O F E R V 1 C I M

PC BEEP 1 2 S S S S V V P P 2 3 4 4

R4 7 8

13

SENS E_A

R 46 3

2 0 K _ 1 %_ 0 4

14 15

LI NE2 _ L LI NE2 _ R

R 46 4

3 9 . 2 K _1 % _ 0 4 HP _SE NSE

16 17

MIC 2 _ L MIC 2_ R

C6 96 C6 97

18

SENS E_B

19 20

JD RE F MO NO _O UT

R 46 8 C6 99

2 0 K _ 1 %_ 0 4 * 100 p_50 V_ NPO _ 04

21 22

MIC 1_ L _ C MIC 1_ R _C

C7 00 C7 01

4 .7 u_6 .3V_ X5R _0 6 4 .7 u_6 .3V_ X5R _0 6

23 24

LI NE1 _ L LI NE1 _ R

C7 03

0 .1u _1 6V_ Y5 V_04

27

CO DEC _V REF

C7 04

2 .2 u_6 .3V_ X5R _0 6

28 30 29

LD O_ C AP MIC 1- VREF O -R MIC 2- VREF O

32 33

HEAD PHO NE- L HEAD PHO NE- R

35

CO DEC _C BN

36 34

CO DEC _C BP

VR EF

SD ATA- IN

2 S S V D 7

1 2 S S S S V V A A

D N G

7 6 2 3

9 4

AUD G

1 3

HP-O UT -L HP -OUT -R CBN CB P OPV EE

VT1802P

M IC_ SEN SE 2 9

C7 05

12/6

INT _ MIC

R 46 7

VT1802P

NC PIN

HEA DPH ONE -L 29 HEA DPH ONE -R 2 9

1 K_04

AUD G

1 2 8 8 2 66 -0 2 00 1 PCB F oo tp rint =8 8 2 66 -2 L

75_1%_04 R 47 2

1K _ 0 4

M IC1 -L _ M

MIC 1-R

R 47 4

1K _ 0 4

M IC1 -R _M

M IC1 -VRE F O-R R 47 5

2. 2 K _0 4

M IC1 -VRE F O-L R 47 6

2. 2 K _0 4

4.7K_1%_04

C 7 08 2 .2 u _6 .3 V _ X5 R _0 6 SPKOU T R+

SPKO UT R+ 2 9

AU DG SPKOU T R-

AU DG

6 8 0p _ 5 0V _X7 R_ 0 4

MIC 1-L

VT1802P

J _ INT M IC1

INT _ MIC _ OU T C 69 8

A UDG

10u

SPKO UT R- 2 9

M IC1 -VRE F O-L

T h e rm a l P a d p l a c e 9 Via hole. 3.3VS_AUD SPKO UT L +

5VS 20ms

AZ_RST# PD#

B - 26 AUDIO CODEC ALC261C

C 7 10

C7 1 1

* 1u _ 1 0V _Y 5 V_0 6

*1 8 0 p_ 5 0 V_N P O_ 0 4

C2 3 6 C2 4 6

*1 8 0p_ 50 V_ NPO _0 4 *1 8 0p_ 50 V_ NPO _0 4

AUD G J _ SPK1

S PKOU TL -

J_SPK1 2

Speaker wire length less than 8000mils , It don't need LC Filter. SPKOUTR+,R-,L+,L - Trace width Speaker 4 ohm------> 40mils Speaker 8 ohm------> 20mils

Reserve 9/8

L 1 12 * F CM 16 0 8 K-1 21 T 0 6_ s h ort SPKO UT L + _L

SP KOU TL -_L * F CM 16 0 8 K-1 21 T 0 6_ s h ort L 1 13

1

EMI Require

C7 1 2 *1 8 0 p_ 5 0 V_N PO _ 0 4

J_ SPKL 1 1 2

SPKO UT R+ SPKO UT R-

L136 L135

SPKOU T L+ _ L SPKOU T L-_ L * F CM 1 60 8 K-1 21T 0 6 _s h ort * F CM 1 60 8 K-1 21T 0 6 _s h ort

SPK OUT R +_ R SPK OUT R -_R

4 3 2 1 * 85 2 0 4-0 4 0 01

8 5 20 4 -0 20 0 1 PCB F o o tp rin t = 8 5 20 4 -0 2R

PN: 6-20-43130-104

AUD G

C2 3 7 C2 3 9

1

4 .7 K_ 04

VT1802P 330P

1 0u_1 0V_ Y5 V_08

VT1802P

2.2 u _ 6.3 V_ X5 R_ 0 6

2

R 46 5

VT1802P 2.2K_04

HP_ SEN SE 2 9

5.1K_1%_04

VT1802P

C7 0 7 A LC 2 69 Q -VB6 -GR

4 .7 u_6 .3V_ X5R _0 6 4 .7 u_6 .3V_ X5R _0 6

J_INTMIC1

MIC 2- VREF O

MI C_ SENSE

S en s e A

SPK-L + SPK-L -

1 6 H DA_ SDO UT C 70 2

AU DG

*1 8 0p_ 50 V_ NPO _0 4 *1 8 0p_ 50 V_ NPO _0 4

MIC 1 -LM 2 9 MIC 1-R M 2 9

Schematic Diagrams

USB 3.0 VL800

Sheet 26 of 41 USB 3.0 VL800

USB 3.0 VL800 B - 27


Schematic Diagrams

KBC- ITE IT8518 R 50 1

V DD3

K B C _ A V DD

* 15 m il _ sh o rt_ 06

C7 4 1

C7 4 2

0.1 u _ 16 V_ Y 5 V _ 0 4

C7 4 3

1 0u _ 10 V_ Y 5 V _ 0 8

C 74 4

0 .1u _ 1 6V _ Y 5V _ 0 4

0 .1 u_ 1 6V _Y 5V_ 0 4

V D D3

L 1 17 H CB 1 0 05 KF -1 2 1T 2 0

.

C 74 7

8

U 37

V DD 3

VDD

C8 5 6

C7 4 5

C 7 46

0.1 u _ 16 V _ Y 5 V_ 0 4

*0 .1 u_ 1 6 V _Y 5 V_0 4

* 0 . 1u _ 1 6V _ Y5 V _ 0 4

SI SO CE # SCK

0 .1 u_ 1 6 V_Y 5 V _0 4 KB C _ F LAS H

3

KB C _ HOL D #

7

5 2 1 6

VD D3

K BC _SP I _S I_ R K BC _SP I _S O _ R K BC _SP I _C E # _R K BC _SP I _S C L K _R

R 50 2

WP#

C 74 8 L 11 8 HC B 1 00 5 KF -1 21 T 2 0

.

3 .3 VS

1 0 0K _0 4

0 .1 u_ 1 6 V _Y 5 V _0 4 EC_ VCC

1 5 ,19 ,2 3 ,24 ,2 6

BUF _ P L T_ R ST# 15

E C_ RST #

R 78 5

* 0_0 4

R 78 6

0_ 0 4


2 4 ,28 25

Sheet 27 of 41 KBC- ITE IT8518

29

R 7 97

0 _ 04

( S MI# ) ( S CI# )

E C_ S MI# E C_ S CI#

W L A N _E N K B C _ MUT E #

2 9 W EB _E MA IL # C8 5 5 0 .1u _ 1 6V_ Y 5V _ 0 4

BA T _ DE T BA T _ V OL T ( A P KEY # )

37 B A T _ DET 37 B A T _ V OL T 29 AP _KE Y # 2 TH ERM _V OL T 23

22 22

R 70 8 R 70 9 R 52 3

H _P EC I

25

Pin873IN1multi functionpin 2 4,2 8

3 G_ DET # CCD _ DET #

37 S MC _BA T 37 S MD _BA T 1 0 S MC _ V GA_ T HE R M 1 0 S MD _ V GA_ T HE R M

3,1 6 ,1 7 S M C_ CP U_ TH E RM 3,1 6 ,1 7 S M D_ CP U_ TH E RM

24

L A N_ P C IE _W AK E # 3 G_ DE T# C CD_ D ET# M ODE L_ ID

L AN_ P CIE_ W A KE #

B T_ DET #

3 IN1

S MC _ B AT S MD _ B AT S MC _ V GA _ T HE RM S MD _ V GA _ T HE RM 0_ 04 0_ 04 * 0 _0 4

L CD_ BR IGH TN E S S K BC_ BE E P ( B EEP ) K B C_ B EE P 28 L ED_ SC ROL L # 28 L E D _N UM # 28 L ED _C AP # 2 8 LED _ B AT _C HG 2 8 L ED_ BA T _ F UL L 28 L E D_ P W R

24 R 787

8 0 CL K

80 CL K 1 K _0 4

2 9 W E B _W W W # 29 T P _ CL K 29 T P_ DAT A 22

8 0 DE T # ( 80 PO RT _D ET #) ( W E B 2#)

3G _E N

R 83 0 R 82 9

1 0 VG A _ AL E RT # 2 4,2 8 W L AN_ L E D# 24 W L A N_ DET #

AD AD AD AD AD AD AD AD

WEB1#---WEB_EMAIL# WEB2#---WEB_WWW#

C0 C1 C2 C3 C4 C5 C6 C7

/GPI /GPI /GPI /GPI /GPI /GPI /GPI /GPI

R 5 33

W/0 CIR)

C 753

F L F RA M E# /GP G 2 F L AD0 /S C E # F L A D1 /S I F L A D2 /SO F LA D 3 /GPG 6 F LC L K /S CK ( PD )F L R S T# /W U I7/G P G0 /T M

GPIO ( P D )K S O16 /GP C 3 ( P D )K S O17 /GP C 5 ( ( ( ( ( ( ( (

PWM

24 25 28 29 30 31 32 34

PW PW PW PW PW PW PW PW

M M M M M M M M

0 1 2 3 4 5 6 7

/GP /GP /GP /GP /GP /GP /GP /GP

A0( A1( A2( A3( A4( A5( A6( A7(

PU PU PU PU PU PU PU PU

) ) ) ) ) ) ) )

PS 2 C LK 0 /G PF 0( PS 2 D AT0 /G PF 1( PS 2 C LK 1 /G PF 2( PS 2 D AT1 /G PF 3( PS 2 C LK 2 /G PF 4( PS 2 D AT2 /G PF 5(

C 7 56

( P D )T MR I0/W U I2 /GP C 4 ( P D )T MR I1/W U I3 /GP C 6

CIR ( P D )CR X /GP C 0 ( P D )C TX/GP B2

GP I NTERRUPT

4 5 6 8 11 12 14 15

K K K K K K K K

36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55

KB -S O0 KB -S O1 KB -S O2 KB -S O3 KB -S O4 KB -S O5 KB -S O6 KB -S O7 KB -S O8 KB -S O9 KB -S O1 0 KB -S O1 1 KB -S O1 2 KB -S O1 3 KB -S O1 4 KB -S O1 5

1 2 3 7 9 10 13 16 17 18 19 20 21 22 23 24

K B -S O0 K B -S O1 K B -S O2 K B -S O3 K B -S O4 K B -S O5 K B -S O6 K B -S O7 K B -S O8 K B -S O9 K B -S O1 0 K B -S O1 1 K B -S O1 2 K B -S O1 3 K B -S O1 4 K B -S O1 5

( P D )L 80 HLAT /GP E 0

S S S S S S S S S S S S S S V V V V V V V 1 2 7 9 1 3 2 1 2 4 9 1 2 1 1

S S V A

100 101 102 103 104 105 106

( 3 G_ P W R_ EN ) K B C _ S P I_C E # K B C _ S P I_S I K B C _ S P I_S O ( V CH G-S E L) KB C_ S P I_ SCL K

-S -S -S -S -S -S -S -S

4 5 6 8 11 12 14 15

I0 I1 I2 I3 I4 I5 I6 I7

1

1 u _6 .3 V_ X5 R _0 4

24

J_KB1

EC MODULE CHOOSE ( FOR DIFFERENCE K/B TYPE)

1 2 3 7 9 10 13 16 17 18 19 20 21 22 23 24

VER .

RX

V1. 0

R503 10K/ R504 X

3.3V

V2. 0

R503 X/ R504 10K

VOLT AGE

0V

V2. 0

R503 10K/ R504 10K

1.65V

MO DE L _ ID

R 50 3

MOD EL_ID

W240BU W250BU W250BAQ

1 0 K _ 04

R5 0 4

VD D3

* 1 0K _ 04

RX V DD3

3 G_ POW ER

2 2

SM D_ BA T R 8 0 8 SM C_ BA T R 8 0 9

C C D _ EN

S U S B# S USC #

93 94 95 96 97 98 99 107

O C P P E# I C PP E#

CLOCK

EC_ VS S

C K 32 KE C K3 2K

VD D3

5 4 3 2 1

2 128

SW I #

16

C H G _ EN

37

1 0 K _0 4

CK 3 2 K E CK 3 2 K R 5 31

* 1 0 m i l _ sh o r t

For 8512E

1 2

4 3

37

R5 2 8 1 K _0 4

VDD

? ?? 3

R5 3 2 4 .7 K _ 04 K B C_ HO LD #

7

C K 3 2K

* 12 p _ 50 V _ NP O _ 04

S HO R T * MC -14 6 _3 2 .7 68 KH z

6-22-32R76-0B4 R534F or IT8518BX&

4 3

5

KB C _S P I_SI _R

R 52 6

47_04

2

K BC _S P I _S O _ R

R52 7

1 5 _1 %_ 04 K BC _S P I _S O

1

KB C _S P I_C E# _R

R52 9

1 5 _1 %_ 04KB C _S P I_ C E#

6

KB C _S P I_SC L K _R

R 53 0

47_04

CE# SCK

H OL D#

V SS

4

P C T 25 VF 0 1 6B -75 -4 I-S 2 A F

Co-l ayout X2, X3 1 2

SI SO

K B C_ F LA S H

C K 3 2K E C 7 55

KBC_SPI_*_R = 0.1"~0.5"

U39 8

0 _0 4

* 10 M _0 4

C7 5 4

80 D E T#

12/6 Reverse

1 9 ,20

C7 5 2 0 .1 u _1 6 V _ Y5 V _ 04

U37 U39Co-l ayout

* 12 p _5 0 V _ NP O _0 4

K BC_ AG ND

AL L _S Y S_ P W RG D VDD 3

3 5

CE L L C _ ON TR OL

( K BC_ PME# ) P ME#

29

C7 5 1 1 u _6 .3 V _ X5 R _0 4

80PORT

3 IN 1 8 0 CL K R 15 4

X1 0 R5 3 4

0 . 1u _1 6V _ Y 5V 0_ 4

V CO RE _ON

R 71 0

5 7

* 10 K _ 0 4

J_ 8 0D E BUG 1

2 6 2 6

CP U _F AN S EN

( P M_ PW RO K )

112

R 5 07

W L A N_ L ED#

2 9,3 0,31

RS M RS T _ GA T E # 16 K B C_RST # 1 6

VGA _ F A NS E N

19

1 0 K_ 0 4 3 .3 VS

22

EGA D

35 17

119 123

1 0 K_ 0 4

R 50 6

B A T _VO L T

DD _O N

120 124

R 50 5

CCD _ DE T #

1 6 , 19 , 26 , 3 0 1 6, 3 0,3 2

B T_ E N 2 4 , 28 B KL _E N 2 0 H S PI_ CE # 1 7 HS PI_ S C LK 1 7 HS PI_ MS O 1 7 HS PI_ MS I 17

47 48

3G _D E T #

V CHG _ S E L 37

56 57

82 83 84

2. 2 K _ 0 4 2. 2 K _ 0 4

Pin100,104&106EXT ? ? Pull hi & Pull Low.

IT8519BX Only.

B - 28 KBC- ITE IT8518

B B B B B B B B

WP#

LPC/WAKE UP

( P D )R ING #/P W RF A IL # /L PCRS T# /GP B7

* 1 0m _ li s h ort_ 0 4L C D_ B RIG HT NE SS

* 0 . 1 u_ 16 V _Y 5 V_ 04

0 1 2 3 4 5 6 7

( P D )T ACH 0 /GP D 6 ( P D )T ACH 1 /GP D 7

NC 2 R53 5

KB -S I0 KB -S I1 KB -S I2 KB -S I3 KB -S I4 KB -S I5 KB -S I6 KB -S I7

*8 52 0 5 -05 0 0 1

EC Cost Down

2 0 B R IGH TN E SS

/ID /ID /ID /ID /ID /ID /ID /ID

PWM/COUNTER

G INT /GP D 5 ( P U )

* 0_0 4

H0 H1 H2 H3 H4 H5 H6 G1

( P D ) W U I 5 / G P E5 ( P D )L P CP D # /W U I6 /GP E 6

PU) PU) PU) PU) PU) PU)

R I1# /W U I0 /GP D 0( P U ) R I2# /W U I1 /GP D 1( P U )

UART

P P P P P P P P

( P D )EGA D/GP E1 ( P D )E G C S # /GP E 2 ( P D )E G CL K /GP E 3

PW R S W /G P E 4( P U )

R XD /GPB0 ( PU ) T X D/G P B1 ( PU )

)G )G )G )G )G )G )G )G

WAKE UP

WAKE UP

1 08 1 09

PD PD PD PD PD PD PD PD

EXT GPIO

PS/2

85 86 87 88 89 90

* 8 52 0 1- 24 0 51

58 59 60 61 62 63 64 65

C 74 9

For 8502E U9 U28 Co-l ayout

V D D3

FLASH

SM CL K0 /GP B3 SM DA T 0 /GP B4 SM CL K1 /GP C 1 SM DA T 1 /GP C 2 SM CL K2 /GP F 6 ( PU ) SM DA T 2 /GP F7 ( PU )

IT8 5 1 8E

0_04 FOR IT8512CX/EX 0 . 1 U _ 0 4 F O R I T E8 5 1 2 - J ( I T E 8 5 0 2 - J

IT8518

0 1 2 3 4 5 6 7

SMBUS

33

* 0 _0 4 * 0 _0 4

PJ 0 PJ 1 AC2 /GPJ 2 AC3 /GPJ 3 AC4 /GPJ 4 AC5 /GPJ 5

ADC

18 21

P W R_ B T N#

K SO0 /P D 0 K SO1 /P D 1 K SO2 /P D 2 K SO3 /P D 3 K SO4 /P D 4 K SO5 /P D 5 K SO6 /P D 6 K SO7 /P D 7 K SO8 /A C K # K SO 9/B U SY K SO 10 /PE K S O1 1 /E RR # K S O 1 2/S L C T KS O 1 3 KS O 1 4 KS O 1 5

DAC G G D D D D

1 10 1 11 1 15 1 16 1 17 1 18

1 25

30 P W R_ S W # 16 ,2 0 ,29 L ID_ S W # 16

66 67 68 69 70 71 72 73

K SI0 /ST B # K S I1 /A F D # K S I2/IN IT # K S I3/S L IN # KS I4 KS I5 MATRIX KS I6 KS I7

KB C _W R E S ET #

VS S

* A T 25 F 5 1 2A N

FOR W250BUQ J _K B 2

8 52 0 1 -24 0 5 1

T C A C B V V A

EC S CI# /G P D3( PU ) EC S MI# /G P D4 ( PU )

76 77 78 79 80 81

M E_W E # C PU_ F A N ( W E B 1#) VG A _F A N

CP U _F A N

FOR J W240BU _KB1

G A2 0/G PB 5 KB R S T #/G P B6 ( PU ) PW U RE Q # /GP C 7( P U ) L 8 0L L AT /GP E7 ( PU )

23 15

W L A N _E N

Y Y Y Y Y Y B B B B B B

4 HO L D#

4 7

W R ST #

1 26 4 16 20

G A20

16 GA2 0 1 6,2 9 ,3 7 AC_ IN # 28 LE D _ A CIN 3 ,1 7 AP U_ T A L E RT # 1 6,2 6 16

C C

3

LAD0 T T T T T T V S S S S S S LAD1 V V V V V V LAD2 LAD3 L P C CL K L F R A ME # LPC K/B SE R IRQ L P C RST #/ W UI4 /GPD 2 ( PU )

14

KB C _W RE S ET #

4 7 6 0 2 1 1 2 2 2 5 9 1 1 1

1 1

U3 8 10 9 8 7 13 6 5 22

1 5,1 9 L P C _A D 0 1 5,1 9 L P C _A D 1 1 5,1 9 L P C _A D 2 1 5,1 9 L P C _A D 3 15 ,1 6 LP C _ CL K0 1 5 ,19 L P C_ F R AME # 1 5,1 9 S E RIR Q

K BC _ A GND

X11 * 1T J S 1 25 D J4 A 4 2 0P _ 3 2 .76 8 K Hz

6-22-32R76- 0B2 6-22-32R76- 0BG

KB C _S P I_ SI

KB C _S P I_ SC LK

Schematic Diagrams

LED/ MDC/ BT 3V _B T

Bluetooth

J _ BT 1

3 .3 V

16 US B_ P N 6 16 US B_ P P6 2 4,2 7 BT _ DE T #

R5 3 6 47 K_ 0 4

3 .3 V

*8 7 21 2 -0 6G 0 1 5,2 4

BT _ DE T # C7 5 7

R 53 7

BT _ ON

3 .3V

*1 0K _0 4

3 V_ BT R5 39

50 mi l

B T _ E N# D

C 75 8

3 .3 VS 3 .3 VS

3 .3 VS

3 .3 V S

R5 4 6

R5 4 7

R5 48

22 0 _ 04

2 20 _ 0 4

2 20 _ 0 4

22 0 _0 4

HDD/ODD D2

C

A

C

S AT A _L E D # 1 7

6- 52- 52 001 -0 27

A

NUM D3

LED

M 5 4 3 G Y 0 7 1 P S Y R

M 5 4 3 G Y 0 7 1 P S Y R

CAPS D4

LOCK LED

M 5 4 3 G Y 0 7 1 P S Y R

C

L ED_ N UM# 2 7

6- 52- 52 00 1- 027

3 .3VS

A

BT LED

M 5 4 3 G Y 0 7 1 P S Y R

C

1

3

2

4

2 2 0 _0 4

LED _A CIN 2 7

D1

2

W LAN _L ED # 2 4 ,2 7

M2 M-M ARK 1

H3 4 h t6 _ 0b 7 _0 d 3 _7

H3 5 HC 6_ 0 d 3_ 7

3 4 5

1

9 8 7 6

E

H1 C1 10 D 11 0 NP

M6 M-MA RK1

M3 M-M A RK1

M4 M-M ARK 1

H5

H1 4

3 4 5

H 18 H 6_ 0 D3 _ 7

S1 SMD 80 X8 0 1 1

S2 SMD8 0 X80

H 17 H 15 * H4 _7 B6 _ 0D 3 _7 H 4_ 7 B6 _0 D3 _ 7

H 29 H 30 H31 H 4_ 7 B6 _0 D3 _ 7 H 4_ 7 B6 _0 D 3_ 7 H 4 _7 B6 _0 D 3_ 7

1

H6 C6 7 D6 7

1

H1 9 H2 1 H 20 H4 _ 0B7 _ 0 D3 _7 C1 10 D1 1 0 NP C 11 0 D1 1 0N P

3 4 5

MT H 31 5 D1 1 1

3 4 5

H3 6 h t6 _ 0b 7 _0 d 3 _7

H3 2 H4 _ 7B 6_ 0 D 3 _ 7

H33 H T 6_ 0 BS 1 D 3 _7

H9 3 4 5

1

H7

1

1 MT H 31 5 D1 1 1

9 8 7 6

6

9 8 7 6

3 4 5

1 1

* 10 m il _ s ho rt_ 0 4 B W L AN _EN 2 4,2 7

2

Q1 6 * DT C1 1 4 E UA

3

R5 4 5

2 2 0_ 0 4

LED

1

2 20 _ 04

Y

G S

2

4

BAT LED

3

D1 3

D 14 Y

KP B-3 02 5 YS G C 2

G S

K PB- 30 2 5Y SGC

4

H1 3

1

For W240BU

9 8 7 6

1 MT H3 1 5 D1 1 1

9 8 7 6

H2 4 3 4 5

H2 6

MT H 31 5 D1 1 1

1 M TH 3 15 D1 1 1

H4 3 4 5

1

GN D

J_ T P 4 1 2 3 4 5 6

MT H3 1 5 D1 1 1

3 4 5

C 76 0 *0 .1 u_ 1 6V _Y 5V _ 0 4

VD D3 9 8 7 6

1

9 8 7 6

2 4, 2 7

Q1 7 DT C1 1 4E U A

3 4 5

MT H 31 5 D1 1 1

mt h3 1 5d 1 1 1_ 3

H 23 C 67 D6 7

H3

H1 1

1

1 MT H 31 5 D1 1 1

9 8 7 6

R 54 4

B

3 4 5

MT H 31 5 D1 1 1 H2 C 11 0 D1 1 0N P

2 2 0_ 0 4

C

6- 52- 520 01 -027

H2 5 M8 M-M A RK1

R 54 3

2 2 0 _0 4

Sheet 28 of 41 LED/ MDC/ BT

POWER ON

B T _E N

M7 M-MA RK1

R 5 42

R5 5 0

L E D _S CR O LL # 27

L E D_ B AT _F U L L 2 7

KP B-3 02 5 YSG C

4

C

L E D_ BA T _ CH G 2 7

27

WLAN LED

3

Y G S

LOCK LED

L E D _C AP # 2 7

6-5 2- 52001- 02 7

R 54 1

22 0 _0 4

1

SCROLL D5

LOCK LED

R5 40

L ED_ PW R

E

M1 M5 M -MA R K 1 M -MA R K 1

*1 0 u_ 1 0 V _Y 5V _0 8

3 . 3V S

R5 49

A

C7 5 9

4 0 _ O P N _ V 0 5 _ p 0 8 1 *

S

LED

5 0mi l

*1 5 m il _ sh o rt_ 06 Q1 4 *MT N 70 0 2Z H S3

G

BT _ EN

* 0_ 0 4

R5 38

* 18 0 p_ 5 0 V _N PO _ 0 4

2 4 ,27

1 2 3 4 5 6

BT _ EN#

9 8 7 6

L ED_ PW R L ED_ ACI N L ED_ BA T _ F UL L L ED_ BA T _ CHG

* 85 2 01 -0 6 05 1 GN D

12/9

For W250BUQ

9 8 7 6

MT H3 1 5 D1 1 1

LED/ MDC/ BT B - 29


Schematic Diagrams

USB/ FAN/ TP/ MULTI CON USB PORT*2(Port 0,Port1)

USB VCC1

USB VCC0

Reserve 9/8

* 0_ 0 6

U SB _VC C2

60 mil +

USB VC C0

100 mil

1

U SB_P N0

2

U SB_P P 0

3

7 1

U10 IN

D M_ O

D A P P

D P_O

12

O UT

VD D5 27 ,3 0 ,31

R 7 47

* 1 0 K _ 04

5

R 75 0

* 1 0 K _ 04

6

V DD5

R 74 8

* 1 0 K _ 04

7

A C_ IN

R 75 1

* 1 0 K _ 04

8

DD_ ON

* 10 K _ 0 4

R 74 9

100 mil

DP _IN

0 .1 u _1 6 V _ Y 5 V _ 04

FAN CONTROL

Port 0

5V S_ F A N

J _ USB 1 R 71 1

U S B_ PN0 _R

10

U S B_ PP 0_ R

U S B_P N0 _R

4

U S B_P P 0_ R

1

14 IL IM_ SE L

G ND

EN /DSC

IL IM0

C TL 1

IL IM1

3 *W CM2 0 1 2F 2 S-1 6 1T 0 3 2

15

R 7 37

* 17 . 8K _1 % _ 04

R7 4 5

* 01 K_ 04

5VS

F A U LT #

R 74 6

* 10 K _0 4

R 57 4 Q7 6 *M TN 70 0 2 Z H S 3

V+

* 0_ 04

G G G G

5VS

CTL2 CTL2 CTL2

CTL3: 0 CTL3: 1 CTL3: X

X 1 1

J _ F A N1

N N N N G G G G

C7 65

1 0u _ 1 0V_ Y 5V_ 0 8

US B_ O CP 0 _1 #

U S B_O CP0 _ 1 #

3 .3V

R 5 54

USB V CC1

16

US B_ PN0

16

US B _PP 0

+ C 7 72

U S B_F L G #

* 0_ 0 4

U SB _ V CC3

L 13 0 *1 5 mi l_ sh o rt _ 06

R5 53 *1 0K_ 0 4

U S B_P N 0

R 168

0_ 0 4

US B_ PN0 _ R

U S B_P P 0

R 171

0_ 0 4

US B_ PP 0 _R

JFAN

2 7 C P U_ F A N S EN

3 R 5 51

US B_ F L G#

* 10 0 u _6 .3 V _ B _A

6 VIN1

VO UT 2

VIN2

VO UT 3

3

C 76 1 1 0u _ 10 V _ Y 5 V _ 0 8

4 EN#

R71 3

U SB VCC 1

F L G# V O U T 1 2

CLICK CONN

0 .1 u _1 6 V_ Y5 V_0 4

Port 1

1

100 MIL

7

16

8

C 7 62

C7 63

C7 64 1 6

1

0 .1 u _1 6 V _ Y5 V _ 04

0.1 u _1 6 V _ Y 5 V _ 04

*1 0u _ 6 .3V_ X5 R_ 06

3 * W C M 20 1 2 F 2S-1 6 1 T0 3 2

1

US B_ PP 1

1

0 _ 04

4

U S B_P N1

L1 2 1 R71 4

R T9 7 1 5BG S

U S 0 40 3 6 B CA 0 81

W240BU 6- 21-B49C0-104 3 0,3 2 ,3 3 D D_ ON #

* 15 m il_ s ho rt_ 0 6 C 77 0 R5 56

R5 57

10 K_ 0 4

10 K_ 0 4

C7 7 1

* 10 u _ 10 V_ Y5 V_ 08

DA T A _ H GN D

0 _ 04

R 5 55

DA T A _ L

4

G ND

5V S

V+

2 3

FOR CLICK BOARD 5 V S_ T P

J _ USB 2

5

4. 7 K _ 0 4

80 mil

C 7 73

U 40 5V

8 52 0 5-0 3 7 01

1-----> Dedicated Chargi ng Port, Auto-detect 1-----> Charg ing Down dtream Por t, BC Spec 1.1 0-----> Standard Downstr eam Por t, USB 2.0 Mode.

R 5 52 1 0 K_ 04 US B_ O CP0 _ 1#

1 2 3

C7 6 6

0.1 u _1 6 V _ Y 5 V_ 04

*T P S2 5 40 N/A

3 .3V

1 6,2 6

5 V S_ F A N

1 2 3 4 D D D D

3 .3 V S

CTL1 CTL1 CTL1

8 7 6 5

G 9 9 0P 1 1 U 6 - 0 2 - 9 9 0 1 1 - B2 0 P2793A 6-02- 02793- B20

1 2 3 4 D D D D N N N N

GN D

0_ 0 4

GN D GN D GN D GN D

A X9 9 5S A

DA TA _ L

W250BUQ 6-21 - B4410-00 4

V DD3

FON VIN VO UT VS ET

3

W240BU6 - 21-B49C0-104

13

S

Sheet 29 of 41 USB/ FAN/ TP/ MULTI CON

U41 1 2 3 4

CPU _F A N

2

US0 40 3 6 B CA 0 8 1

9

27

DA TA _ H

R 7 12

NC

C TL 3

0 _0 4

4

16

C TL 2

1

L 1 20

D

G

AC _IN #

C7 6 8

*1 0 0u _ 6 .3V _ B _ A

12/7

11 DM _IN

4

V DD 5

+ C7 6 9

2 2 0u _ 6. 3V _ 6 .6 *4 . 5

F ON #

USB PORT Charge

1 6 ,27 ,3 7

0 _ 06

R 74 1

C 7 40 VDD 5


R 74 0

J_ T P 1 1 2 3 4 D D D D N N N N G G G G

1 2 3 4 8 52 0 1-0 4 0 51

1 2 3 4 D D D N N N D N G G G G

1 u_ 6 .3V _Y 5V_ 0 4

T P_D A T A 2 7 T P _C LK 2 7 C7 74

C7 75

47 p _ 50 V _ NPO _0 4

47 p _ 50V_ NP O _0 4

W250BUQ 6- 21-B4410 -004

VDD 3

Audio/B

POWER SWITCH CONN.

CONN.(Port 2)

A P_ KEY #

FOR P OWER SWITCH BOARD US B V CC1

5V

R 73 3

3 .3V S

* 0_ 0 6

C7 7 8

0 .0 1 u_1 6 V_X7 R_ 0 4

3.3 V

C7 7 6

C 7 77

J _ AUDIO 1

12/10 DeleteR559 2 5 M IC1 -R M 2 5 M IC1 -L M

2 5 H E ADP H ON E-R 2 5 H E ADP H ON E-L

2 5 M IC_ SE N S E 2 5 H P _ S ENSE

2 5 SP KOUT R + 2 5 SP KOUT R 16

USB _ PN4

R 56 1

* 1 0 m l_i sh o rt_ 04

U SB N4 _ R

16

USB _ PP 4

R 56 2

* 1 0 m l_i sh o rt_ 04

U SB P4 _R

M IC1 -R M MIC1-L M HE AD P HO NE -R HE AD P HO NE -L M IC_ SENS E SP K _H P # H P _ S ENSE U S BN4 _ R U S BP 4 _R SP K OUT R+ SP KO UT R-

1 2 3 4 5 6 7 8 9 10 11 12 13 14 8 5 20 1 -14 0 5 1-0 1

Change connect or

0 .01 u _ 16 V _ X 7R _0 4

1 2 3 4 5 6 7 8

Q18 S

0.0 1 u_ 1 6 V_X7 R_ 0 4

3 .3 VS

* MT N7 0 02 Z HS3

3 .3 V

10 K_04 * 10 K_ 0 4 * 10 K_ 0 4 J_ SW 2

2 7

D

G

FOR AUDIO BOARD

B - 30 USB/ FAN/ TP/ MULTI CON

A P _KEY #

R83 1 R83 2 R83 3

0 _ 06

1.1A 60mils R 73 4

AP _ K EY # W E B _W W W # W E B _EM AIL #

CLOSE TO J_SW1

20mil MB T N R55 8 W E B_ W W W # W E B_ EMAIL # LID _ S W #

* 10 m l_i sh o rt_ 04 M_ BT N#

AP _ K EY #

88 4 8 6-0 8 01 J _ SW 1 1 2 3 4 5 6 7 8 9 10

M_ BT N#

20mil M _B TN #_ R W E B_ W W W # W E B_ EM AI L# L ID_ S W #

30

R5 6 0 *1 0m il_s h or t_0 4 M _B TN #

M_ BT N#

1

P C2 3 0 W E B _W W W # 2 7 W E B _EM AIL # 2 7 L ID_ S W # 1 6,2 0,2 7

AP_ON

30

P R 21 5 * 47 K_ 0 4 *0 .1u _ 5 0V_ Y 5V_ 0 6 2

AP _ ON

PV 2 *V1 5 AV L C0 40 2

VIN 2

* 5 05 0 0- 01 0 41 -0 0 1L

I f syst emhas APON fu ncti on, uses J_ SW 1 I f sy st emhas no APON f unct i on, uses J_ SW2

12/8

12/8 PV1 *V1 5 A V L C0 4 02

1

Schematic Diagrams

5VS/ 3.3VS/ 1.8VS/ 1.5VS/ 1.1VS VI N VA

VIN

VIN 1

3 .3 V

VIN 1 R8 1 0 VA

*1 2 K_ 06

VI N 29

P R 2 10

M_ BT N # 29

AP_ ON

1K _0 4

PU 1

8

VA 2 3

1 K _0 4

P R 2 11

1

4

12/6

VIN1

VIN

DD _ ON _L AT CH

M _BT N #

PW R_ SW #

IN STA NT -ON

GND

7

R 56 3

1 K _ 04

6

D D_ O N

P R1 8

ON

2 7 , 92 , 3 1

1 K _0 4

PW R_ SW # 2 7

PC 6

PC 7

PC 8

C 7 79

0 .1 u_ 5 0 V_Y 5 V_ 06

0 .1 u _5 0 V_ Y5 V_ 0 6

0 .1 u_ 5 0 V_ Y5 V_ 0 6

0 .0 1 u _1 6 V_ X7 R _0 4

DD_ON"L" T O "H" FROM EC

5 PR 3

10 0 K _ 0 4

VDD 3

P2 8 0 8B 0 SYS 5V

5V

SY S5V

PR 4

PR 5

1 0 K_ 0 4

1 0 K_ 0 4

SY S5 V

PR6 10 K_ 0 4

ON

ON C 78 0

C7 8 1

C7 8 2

0 .0 1 u_ 1 6 V_X7 R _0 4

0.0 1 u _1 6 V_ X7R _ 04

0 .01 u _ 1 6V_ X7 R _ 0 4

D D_ ON #

PQ1 A 6 M TD N7 0 0 2Z HS6 R

C 78 4

0. 01 u _ 16 V_ X7 R _ 0 4

0 .0 1u _ 1 6V _X7 R _ 0 4

PQ1 B 3 M TD N7 0 0 2Z HS6 R

ON PC 9

1

C7 8 3

SU SB

2 9,3 2 ,33

D

2G

27 ,2 9 ,3 1 D D_ ON

3.3 VS

D D_ O N#

1 6,1 9 ,2 6 ,27

S

PR 8

1 0 0K _0 4

1 0 0 K_0 4

5VS SY S1 5V

PR1 0

3A

8 7

PQ3 A MT NN 20 N 03 Q 8 2 1

8 7

Power Plane

4

5VS

S Y S 15 V

PR1 1

PC 22 6

PC 2 27

PR2 0 7

0 .1 u_ 1 6 V_Y 5 V_ 04

1 0 u _1 0 V_ Y5 V _ 0 8

10 0 _ 1% _ 0 4

PQ3 B M T NN 20 N 03 Q 8

D

5

47 0 p _ 50 V_ X7 R_ 0 4

DD _O N#

G

1 6

1.5V

Sheet 30 of 41 5VS/ 3.3VS/ 1.8VS/ 1.5VS/ 1.1VS

3

PC1 2

PC2 2 5

0.1 u _ 16 V_ Y 5V_ 0 4

1 0u _ 1 0V _Y 5 V _0 8

PR 2 06

NMOS PQ 5A *M T NN 20 N 03 Q 8 2 1

8 7

PR1 2

4

PQ4 B M TN N2 0 N0 3 Q8

PC1 8

PQ6 1 MT N7 0 0 2Z H S3

1 .5V S

*1 M_ 0 4

S USB

G

1 6

1 0 0 _1 % _ 04 D

5

4 70 p _ 50 V_ X7 R_ 0 4

PQ 6 0 M TN 7 00 2 Z H S3

S

10/20

PJ 2

S

PJ1 2

* 0 .1u _ 1 6 V_Y 5 V_ 04

10 0 K_ 04

1.5VS

PQ 4 A M TN N2 0 N0 3 Q8 2 1

1 M_ 0 4

3

P C1 7

P C1 1 S

PR9

3

1M _ 04

G

SUSC #

* 0.1 u _ 16 V_ Y 5V_ 0 4

NMOS

VDD 5

5V

3A

1 6 ,27 ,3 2

S

ON

5V VDD 5

3 3 ,3 5

PQ2 MT N7 0 0 2 Z HS3

ON ON

SYS 15 V

D

PC 1 0 4

* 0.1 u _ 16 V_ Y 5V_ 0 4

PR 7

SUS C

3 2, 3 3, 3 4, 3 6

D

5G

SU SB#

SUSC

SUSB

2

4

PC1 3

PC1 4

*0 .1 u _1 6 V_ Y5 V_ 0 4

*1 0 u_ 1 0 V_ Y5 V _ 08

P R1 4

PQ 5B *M TN N2 0 N0 3 Q8

PC1 9

5

*0 .1 u_ 1 0 V_ X7 R _0 4

* 1 00 _ 1 % _0 4

D

P Q1 3 * MT N 70 0 2 Z HS 3

G

SUS B

S 6

4 0 m li SU SB

4 0m il

3 ,23 3, 3 4, 3 6

ON

ON

1.1VS

VDD 3

3A

SY S1 5 V

NMOS SY S1 5V

S Y S 1 5V

NMOS

3.3VS

3.3V 8 7

PQ8 A MT NN 20 N 03 Q 8 2 1

3 .3 V

3A

8 7

Power Plane

PQ9 A MT NN 2 0N 0 3Q 8 2 1

4

PC2 5 22 0 0 p _5 0 V_ X7R _ 04

PC 22 8

PC 2 29

PR2 0 8

0 .1 u_ 1 6 V_Y 5 V_ 04

1 0 u _1 0 V_ Y5 V _ 0 8

10 0 _ 1% _ 0 4

PQ8 B M T NN 20 N 03 Q 8 5

D

D D_ ON #

1 .1V

P Q6 A 8 7

1 M_ 0 4 3

G

3

4

PC 26 PQ6 2 MT N7 0 0 2Z H S3

1 .1 VS

M T NN 20 N 03 Q 8 2 1

4

1 M_ 0 4 3

PR 1 3

PR 17

PR1 6 1M _ 04

VD D3

3.3 VS

PC2 1

P C2 2

PR 1 9

0.1 u _ 1 6V_ Y 5V _0 4

1 0 u _1 0 V_ Y 5 V_ 0 8

1 0 0 _1 % _ 04

5

PC 1 6

0 .1 u _ 16 V_ Y5 V_ 0 4

1 0 u_ 1 0 V_ Y5 V _ 0 8

D

SU SB

G S

PQ 1 0 M TN 7 00 2 Z H S3

PR 15

5

D

SU S B

G

0 .0 1 u_ 1 6 V_ X7 R _0 4

PQ9 B MT NN 2 0N 0 3Q 8

2 20 0 p _ 50 V_ X7 R_ 0 4

PC 2 0

P C1 5

P Q6 B M T NN 20 N 03 Q 8

1 0 0_ 1 % _0 4

PQ 7 MT N 70 0 2 Z HS3

S 6

ON

6 S

12/8

6

ON

5VS/ 3.3VS/ 1.8VS/ 1.5VS/ 1.1VS B - 31


Schematic Diagrams

POWER VDD3/ VDD5 VR E F

P R2 1

* 0 _0 4

P R 22

0_ 04 P C2 8

1u _ 1 0 V _ Y5 V_ 0 6

PR2 3

PR2 4 E N _3 V

PC2 9

E N _5 V

1 00 K_ 0 4

10 0 K _ 0 4 6

10 0 0 p _5 0 V _ X7 R_ 0 4

2 N E

7

PC 3 2

PC3 1

4 .7 u _2 5 V_ X5 R_ 0 8

8 7 6 5

P Q 14 P 1 2 0 3B V

P C3 4 1u _ 1 0 V_ Y5 V _ 0 6


P J3

1

* 5 mm

7 . 5 * 6 . _ + 6 V 3 . 0 6 4 _ C u P 0 2 2

P C3 9

Sheet 31 of 41 POWER VDD3/ VDD5

PL 1 T M PC0 6 0 3H -4 R7 M -Z 0 1 2 1

5A

0 .1 u_ 1 6 V _ Y 5 V_ 0 4

3 2

PC 4 2

1 3 K _ 1 % _0 6

4 0 _ O P N _ V 0 5 _ p 0 0 1

P R2 9 20 K_ 1 % _ 04

2

F E R V

1

1 B F V

VI N VO 1

L D O3 PC 35

24 P R 25

* 1 0K _ 04 PC3 7

PC3 6

22 B OO T2

PC 33

SY S5 V

POK

9

5 6 7 8

B O OT 1

uP6182

1 u_ 1 0 V_ Y 5 V _ 0 6

21

U GA TE 2

UG AT E1

P HAS E 2

PH AS E1

PR1 5 2 5. 1_ 0 6

P Q 16 P 1 2 0 3B V

12 L G AT E2

4 0 N E

L E S P I K S

S YS 5 V

1

5 6

5 O D L

PQ17 P1 2 0 3BV

4

K L C V

PD4

A

3 1

C

4 1

5 5 2 1

6 1

7 1

8 1

C

A

PR 3 0 * RB 0 5 4 0 S 2

EN _ A L L

VREF

P R 34

0 _ 04

P R 35

* 0_ 0 4

3 0 K_ 1 % _0 6

V REG 5

P C 46 0 .01 u _ 5 0V _X 7 R _0 4

PD 5 B AT 54 SW GH A 1

3 C

A 2

V IN

PC 4 8

A

4 .7 u _ 25 V_ X 5 R _ 0 8 R B0 54 0 S2

68 0 K_ 1 % _ 06

1 9 .1 K _ 1 % _0 6

12/7 SY S5 V

1 u _1 0 V _ Y 5V _0 6

P C 50 0 .01 u _ 5 0V _X 7 R _0 4

PD 6 B AT 54 SW GH A 1

SY S1 0 V

A 2

2 20 0 p _ 50 V_ X 7 R_ 0 4

SY S1 5 V P C 51 2 20 0 p _ 50 V_ X 7 R_ 0 4

8 1 4 2 Z

P R 37

1 0K _0 4

D

P C

1

G

PJ5 *6 m i l

D D_ ON P Q 19 M T N7 0 0 2 Z HS3

S 2

D

AC IN P Q2 2 *M T N7 0 0 2Z HS3

B - 32 POWER VDD3/ VDD5

0 . 1 u _ 1 0 V _ X 7 R _ 0 4

G 37

5 5

S

*0 _ 0 4

E N_ 3 V

P R 38

0 _ 04

E N_ 5 V

PQ1 8

G

2 7 ,2 9 ,30

P R 36

D

P R 3 9

1 0 0 K _ 0 4

S

MT N 70 0 2 Z HS 3

+

P R2 8

PC 4 9

3 C

VR E G 5

Rb

P R2 1 6

P C 47

PD7

2 *5 m m

P R2 6

V RE G 5 C

1

P C 41

PR 32 *0 _ 0 4

P R3 3 2 .2_ 0 6

VIN 1

PJ 4

5A

* RB0 5 4 0 S2 P R3 1 0_04

* 68 0 K _ 1 % _0 4

VR EG 5

P R 1 46 5 .1 _ 06

1 0 00 p _ 5 0 V_X7 R _0 4 P C 1 74 2 2 00 p _ 5 0V _X 7 R _0 4

1 2 3

PD3 VR EG 5 PC2 3 8 22 0 0 p _ 50 V _ X7 R_ 0 4

7 8

LG AT E1 N I V

VD D5

P L2 T MPC 0 60 3 H -4 R7 M-Z 01 2

Ra 19

D A P D D N N G G

4 .7 u_ 2 5 V_ X5R _ 0 8 4 .7 u _ 25 V_ X5 R_ 0 8

PQ 1 5 P1 2 0 3 B V

4

20

1

PC 3 8

0 .1u _ 5 0 V_ Y5 V_ 0 6

1 2 3

11

3 2

PC 3 0 1 0 0 0p _ 5 0 V_ X7 R _ 04

PU 2

1 N E

1

8 7 6 5

P R2 7

3

L E S N O T

23

0 .1 u _1 0 V_ X7 R_ 0 4 10

4 S YS 3 V 2

4

8

4 .7 u _2 5 V_ X5 R_ 0 8

V D D3

2 B F V

VO 2

VRE G 3

VIN

5

5 . 4 * 6 . 6 _ V 3 . 5 6 4 _ C u P 0 2 2

P C4 4 0 .1 u _ 1 6V _Y 5 V_ 04

Schematic Diagrams

Power 1.5V/ 0.75 PD 1 2 A

5V

C R B0 5 40 S2

PU 4

VD DQ

6 0 _ V 5 Y _ V 0 5 _ u 1 . 0 *

8 0 _ R 5 X _ V 5 2 _ u 7 . 4 *

8 0 _ R 5 X _ V 5 2 _ u 7 . 4 *

6 6 C P

7 6 C P

8 6 C P

VIN

12/6 Dis able

u P6 1 63 5 6 7 8

PC 6 9 10 u _ 1 0V _ Y5 V _ 0 8 PC 7 0 23

VL DO IN

VBST

4

0 . 1u _1 0V _ X 7 R _ 04

22

PQ 2 3 MD S2 6 5 9

2 3 1

2

1

24

* OP EN_ 2 A PC 7 1

PC 7 2

5V

P R 49

11/5

0 _ 06

P R 53

*0 _ 0 4

P R 55

*0 _ 0 4

VT T SNS

DR VL

GN D

0 .1 u_ 10V_ X7 R_ 04

5

P R 47

PL 4 1 .0 U H_ 1 0 *1 0 *4 .5 1 2

0_0 6

LL

3

4

21

10A 1 9 . 5 * 6 . 6 * 6 . 6 _ + V 5 . 2 _ u 9 0 7 6 C 5 P

20 VT T GN D

2

11/5

PC8 0

D RVH

1

PC 7 3

PR 4 8 1 0 u _ 10 V _Y 5 V_ 0 8 0_06 1 0 u _ 10 V_ Y 5 V_ 08 * 10 u _ 1 0 V_ Y5 V_ 0 8 VD DQ

VT T

PG ND CS _G ND

MO DE

CS PVC C5 VC C5

VT T REF

19

5 6 7 8

18 17

4 PR 52

16

PR 54

0_06

PQ 2 4 MD S2 6 5 5

A

1 0K _ 1% _0 6

PR 56

Z 26 2 1 PD 1 3 * SK3 4 SA

2 3 1

5V

15 14

C

2 P 2 C 0 7 0 4 p _ 5 0 V _ X 7 R _ 0 6

P R5 0 5 .1 _ 0 6

2 .2 _0 4

PR 5 7 P R5 8

5V

0_06

6

8 P R 5 9

9

CO MP

7 R _ 0 4

S3

C N

P C * 1 8 0 4 0 0 p _ 5 0 V _ X 7 R _ 0 4

_ X

S5

VD DQ SET

* 1 0 _ 0 4

* P 1 C 0 0 8 0 3 p _ 5 0 V

PGO OD

VD DQ SNS

7

C N

2 1

13

PC8 1

PC 8 2

1 u _ 1 0 V _ Y 5 V _ 0 6

11

10

D N G

3 .3 V

1 u _ 1 0 V _ Y 5 V _ 0 6

1.5V

VD DQ

PJ 7 V TT _ M EM

0_06

9 . 5

* 6 . 6 * 6 . 6 _ + V 5 . 2 _ u 6 0 7 6 C 5 P *

PJ 8

2 1 .5 V

* OPEN _ 8 A P C

P C

7 5

7 7

0 . 1 u _ 1 6 V _ Y 5 V _ 0 4

0 . 0 1 u _ 1 6 V _ X 7 R _ 0 4

Sheet 32 of 41 Power 1.5V/0.75V

PR6 0 1 0 0 K_ 0 4 DD R1 .5 V_ PW RG D

5 2

DD R1 .5 V_ PW RG D 1 9 ,3 5

P R6 2 5V *1 0 K_ 1 % _ 04

PR 6 3

PR 6 4

1 0K _1 % _ 0 6

1 0 K_ 1 %_ 0 6

5V

P R 65

1 .5 VEN

4 7K _0 4 D

P R 66

G

1 0 0 K _ 04 D

2

PQ 27

G

1 6 ,2 7 ,3 0 S U S C #

S

* 2 2 _0 4

PQ2 6 S

*M T N7 0 0 2 Z HS 3

1

D D _O N#

+1 .5 S_ C PU_ PW RG D

P R6 7

1 0 0K _0 4

PR69

* 10 0 K _ 0 4

D

3 0 ,3 3 ,3 4,3 6 S U S B

SU SB

S

V TT EN

D

PQ 2 8

G

0 .1 u_ 1 6 V_ Y5 V_ 0 4

M TN 7 0 02 Z H S3

5V P R 68

PC 85

G

S

PJ 9 *6 m il 2 9 ,3 0, 33

VT T _ ME M

D

PQ2 5 MT N 70 0 2 Z H S3

* MT N 7 00 2 Z H S3

S USB

PC8 6 PQ 2 9

G S

0. 1u _ 1 6 V_ Y5 V_ 0 4

M TN 7 0 0 Z2 HS 3

Power 1.5V/ 0.75 B - 33


Schematic Diagrams

Power 1.1V/ 1VS 5V V IN 5V PR70 D

1 0 0 K_ 1 % _0 4

3 0 ,35

SU SC

SU SC

P R 72

G

* 6 K2 _ 1% _ 0 4

S

P R 1 79

29 ,3 0 ,3 2 D D_ O N#

6 2 K_ 1 %_ 04

A

OCP=10uA X RILI M/ Rdson

EN _ 1 .1 V

PQ30

P C 89

M TN 7 0 0 2Z HS 3

0 .1 u_ 1 0 V_ X7 R_ 0 4

PD14 R B0 5 40 S2

P R 71

1 0K _1 % _ 0 4

C 5 6 7 8

PQ31 M D S2 65 8 4

PC 9 1 0 .1 u _1 0 V _ X5 R_ 0 4

2 3 1

PC92

1

PJ 2 3 O P EN -1 mm 3 .3 V

3 1

5 1

PU5 uP 6 12 7

6 1

PC 8 7

PC 90

6 0 _ V 5 Y _ V 0 5 _ u 1 . 0

8 0 _ R 5

8 0 _ R 5 X _ V 5 2 _ u 7 . 4 *

X _ V 5 2 _ u 7 . 4

P R7 3

11

2 2 0 K _ 1 % _ 04

10

EN

C . N

H D

PL 5 TM P C 0 60 3 H -4 R 7 M -Z 0 1 1 2

1

LX

V O UT

4

DL

P C9 5 PR 74

8

C . N 7

N T R

6

5 6 7 8

3

VCC

FB

V 1 .1

D N PAD G

2 3 1

. + 6

P Q3 2 MD S2 6 5 8

_ V 5 . 3 2 _ 9 u C 0 6 P 5

PC 78

5

P C9 6 2 2 00 p _ 5 0 V_ X7 R _ 0 4

1 .1 V

1

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0

9 . 5 * 6 . 6 * 6

PR 51 5 .1 _0 6

4

17

P J1 0

5A

2

B ST

C . N

* 0 .1 u_ 1 0 V_ X 7 R_ 0 4

C . N

PGD

9

19 1.1V _PWR GD

M I L I

1.1V

0 .1 u _ 10 V_ X 7 R_ 0 4

2

12


4 1

P C8 8

2 5mm

4 9 C P

1 u_ 1 0 V _ Y 5 V _0 6 * 1 0 m il _ s h ort

Sheet 33 of 41 Power 1.1V/ 1VS

P C 97

PR 7 5

PC98

0 .0 1u _ 1 6 V _ X 7R _ 0 4

1 0 K _ 1 % _ 04

* 2 0p _ 5 0 V_ NP O_ 0 4

5V PC99

1. 1VS_VTT=0. 75 X (1+PR101 / PR102)

PR 7 6

P C 2 13

* 2 0p _ 5 0 V_ NP O_ 0 4

1 u _1 0 V _ Y 5 V _ 06

2 1 K _ 1 % _ 04 1. 5V P C 2 15

P U1 1

3A

0 .1u _ 1 6 V _ Y5 V_ 0 4 P C2 1 8

5 9 7

1V S_ P W R GD

1 0 u_ 6 .3 V _ X 5 R_ 0 6

VI N VI N P OK

8

E N_ 1 VS

EN

1

GN D

VC NT L V O UT V O UT

VFB

V1 S _ R EG

6

3A

4

Ra

3 .2 4 K_ 1% _ 0 4

PC 2 14

P C2 1 6

8 2 p _5 0 V _ N P O_ 0 4

1 0 u _ 6 .3 V _ X5 R _ 06 1 0 u _6 .3 V_ X 5 R _0 6

PC219

A X66 1 0 P R 1 95 5V

Rb

1 0 .2 K_ 1% _ 0 4

VIN

Vout = 0.8V ( 1 + Ra / Rb )

5V

10/22 1.0V=>1.054V

P R7 7 10 0 K _ 1 % _ 0 4

3 0 ,3 2 ,3 4, 36 S US B

SU SB

P R 78

P D1 6

D

PQ 3 3 M TN 7 0 0 2Z HS3

G

6 2K _ 1% _0 4

A

OCP=10uA X RILI M / Rdson

E N_ 1 V S

S

P C 10 0

PR 79

C

0 .1 u_ 1 0 V _ X 7 R_ 0 4

5 6 7 8

P Q3 4 *M DS 26 5 9 4

P C1 0 4 0 .1 u _ 1 0V _ X5 R _ 04

2 3 1

P C1 0 5

3 1

3 .3 V 12

35 1VS_ PWRGD

P R8 0

11

2 20 K _ 1 % _ 0 4

10

4 1

M C I . L N I

EN

5 1 C . N

PU 6 *u P 6 1 2 7

6 1 H D

PG D

LX

BS T

VO UT

VCC

9

1 VS _P W R GD

C . N

P C1 0 8

8

PR 8 1

*0 .1 u _ 10 V_ X7 R _0 4

7

N T R 6

D N PAD G

PC1 1 1

* 0. 01 u _ 1 6 V_ X7 R _ 0 4

*1 .2 K _ 1 % _0 4

*2 0 p _5 0 V _ N P O_ 0 4

P R8 3

PC1 1 2 *2 0 p _5 0 V _ N P O_ 0 4

*3 K_ 1 % _0 4

B - 34 Power 1.1V/ 1VS

Y _ V 0 5 _ u 1 . 0 *

1VS V1 .0 S

6.5A

2 5 mm

9 . 5 * 6 . 6 * 6 .

5 6 7 8

3

PQ 35 *M DS 26 5 5

4

C

PD 1 7 * CSO D 14 0 S H

2 3 1

17

5

A

+ 6

_ V 5 . 2 6 _ 0 u 1 6 0 C 5 P *

7 0 1 C P

4 0 _ V 5 Y _ V 6 1 _ u 1 . 0 *

1VS

PJ 1 1 1

2

*1 u _ 1 0 V_ Y5 V_ 0 6

P R8 2

8 0 _ R 5 X _ V 5 2 _ u 7 . 4 *

1

PC 1 09

*1 0 m i _ l s h o rt PC 1 1 0

PC102

8 0 _ R 5 X _ V 5 2 _ u 7 . 4 *

PL6 *2 .5 U H_ 6 .8 *7 .3 * 3 1 2

DL C . N

P C1 0 3

6 0 _ V 5

* 0 .1 u_ 1 0 V _ X 7 R_ 0 4

4 FB

P C 10 1 * RB 05 4 0 S 2

* 6 . 8 K_ 1% _0 4

2 3mm

P R 1 96 2

1 VS

PJ18 1

3

Schematic Diagrams

Power 1.8VS 5V

PR40

EN_1.8V

100K_1%_04 30,32,33,36 SUSB

SUSB

VIN

OCP=10uA X RILI M / Rdson

5V

PR42

10K_1%_04

PR41

A

*15K_1%_04

PD10

D

PQ20

G

PC56

S MTN7002ZHS3 *0.1u_10V_X7R_04

0.01u_16V_X7R_04

PU3 3 4 5 6 1 1 1 1 *uP6127

3.3V

12

H M C I . C . L N N D LX 1 EN I

11

2

10 9

PR43

PGD

BST

VOUT

VCC

FB

220K_1%_04 1.8V_PWRGD

DL

N D C . C . T N PAD N N R G

*0. 1u_10V_X7R_04

PC54 8 0 _ R 5 X _ V 5 2 _ u 7 . 4 *

PL3 *TMPC0603H-4R7M-Z01 1 2

5 6

4

3

17

PQ21B *AP6901GSM

4

PC61

PC62

V1.8S

4A 9 . 5 * 6 . 6 * 6 . + 6 _ V 5 . 2 9 _ 5 u C 0 6 P 5 *

3

8 7 6 5

PR44

7

PC58

PC53

8 0 _ R 5 X _ V 5 2 _ u 7 . 4 *

6 0 _ V 5 Y _ V 0 5 _ u 1 . *

1 2

PQ21A *AP6901GSM 8

PC57

19 1.8V_PWRGD

PC52

*RB0540S2 C

2 5mm

4 0 _ V 5 Y _ V 6 0 1 _ 6 u C 1 . P 0 *

1.8VS

PJ6 1

1.8VS

*1u_10V_Y5V_06 *10mil_short

*0. 1u_10V_X7R_04

PR45 PC64

Sheet 34 of 41 Power 1.8VS

PC63

*14K_1%_04 *20p_50V_NPO_04

*0.01u_16V_X7R_04

PR46

PC65

*10K_1%_04 *20p_50V_NPO_04

3.3V PC217

5V

0.1u_16V_Y5V_04

PC224 PC221 1u_10V_Y5V_06

10u_6.3V_X5R_06

3A 1.8V_PWRGD EN_1.8V

PU12 5 9 VIN 7 VIN POK 8 1

EN GND

VCNTL VOUT VOUT VFB

6

V1.8S_REG

3A

4

PJ22 1

3

3mm PR204

2

1.8VS 2

Ra

PC222

PC223

PC220

12.7K_1%_1/1 6W_04 10u_6.3V_X5R_06 82p_50V_NPO_04 10u_6.3V _X5R_06

AX6610 PR205

Rb

10K_1%_04

Vout = 0.8V ( 1 + Ra / Rb )

Power 1.8VS B - 35


Schematic Diagrams

APU CORE/ NB CORE Offset & Droop O

OFS/VFIXEN GND +3.3V +5V

SVI

VFIX

O

X

X O

O X

X X

VDDCR_ CPU

EMI

PR10 9 10 _0 4 NB_VDDCR

C78 9 0 .1u _10 V_X5R_0 4

C79 0 * 0.01 u_ 16V_ X7 R_04

CPU_ VDDNB_ RUN_F B_H 3

Meta l VID C odes SVC 0

SVD 0

Output 1.1

0

1

1.0

1

0

0.9

1

1

0.8

CPU_ VDDNB_ RUN_F B_L 3

5VS PR11 0 10 _0 6

SGND5

SVC

SVD

Output

0

0

1.4

0 1

1 0

1.2 1.0

1

1

0.8

4 0 _ % 1 _ K 2 2

1 u_1 0V_Y 5V_0 6

SGND5 VIN 6 0 _ 6 V 5 4 Y 1 _ C V P 0 5 _ u 1 . 0

PR11 4 10 _0 6

3.3V S

P R 11 9

5 VS 3 .3VS PR12 1 1 0K_0 4 PR124

1 9 PWRGD_ VCOR E

SGND5

0 0_ 6

9 4

P R 1 22

* 0_ 0 6

P R 1 23

* 10 K _0 6

SGND5

*1 0m il_short

2

APU_ PW RGD_R 3

CPU_ SVD

3

CPU_ SVC EN_ VCORE

P R 1 26

* 10 m il_s ho rt * 10 m il_s ho rt

4

* 10 m il_s ho rt

5 6 7

PR1 34

PC16 5

2 55 _1 %_0 4

4 70 0p_ 50 V_ X7 R_0 4

P R 1 35

SGND5

PR1 33 62 K_ 1%_ 04

PR1 32 54 9. K_1% _0 4

8 9

1 K _1 %_ 04 10

PR1 36

PC16 6

5 4.9 K_ 1%_ 04

11

1 00 0p _5 0V_X7R_0 4

P R 137

PC1 67 18 0p_ 50 V_ NPO_0 4

PC168

7 4 C C V

N I V

6 4 B N _ B F

OF S/VF IXEN

5 4

3 1 1 1 4 1 R C t P P r o h s _ l i m 0 1 *

UGAT E_ NB

M O C

L GATE_NB

PR1 16 8 .2K_1 %_0 4

B N _ T E S F

B N _ N E S V

B N _ N T R

6 .8 K_1% _0 4

PD2 0

B N _ T E S C O

H S 0 4 1 D O S C *

PQ43 MDS26 A 55

4

VIN

8 0 _ R 5 X _ V 9 5 3 2 1 _ C u P 7 . 4

1

+ 2

C79 1 0 .1u _10 V_X5R_0 4

PC1 40 *3 30 U_2 5V

NB_VDDCR PL8

1

5 6 7 8

t r o h s l_ i m 0 1 *

2 3 1

T MPC06 03H-R6 8M-Z 01 2 9 . 5 * 6 . 6 * + 6 . 6 _ V 5 . 2 _ u 3 0 4 1 6 5 C P

PR21 7 5 .1_0 6

PC23 4 2 20 0p_ 50 V_ X7 R_0 4

10A

PJ1 9 VDDCR _NB 1

2 *8 mm

A _ V + _ V 5 . 2 _ u 0 3 4 3 4 * 1 C P

PC1 45 1 0u _6 .3 V_X5R_0 8

PC1 48 0.22 u_ 16V_ 06 9 3

0 4 B N _ D N G P

B N _ E T A G L

8 3

7 3

B N _ E S A H P

PU9

B N _ E T A G UBOOT

PGOOD

35

2 3 1

PR 125 1_ 1% _0 6

34

SVD

33

PHASE_0

SVC

UGAT E_0

LGATE_1

VDI FF _0

PGND_1

F B_ 0

PHASE_1

COMP_0

UGATE_1

PC157

0.1 u_ 50V_ Y5V_0 6

*0.1 u_ 50V_ Y5V_0 6 0 5 X

PR21 8 5 .1_0 6

C

PD21 *CSOD1 40SH

PR12 8 *1 0m il_s ho r t

PC15 8

2 3 1 A

2 20 0p_ 50 V_ X7 R_0 4

LGATE_0

PR14 1 10 _0 4 CPU_VDDCR

VW_ 0 0 _ N S I

0 _ P S I

4 1

0 _ N E S V 5 1

0 _ N T R 6 1

1 _ N T R 7 1

1 _ N E S V 8 1

1 _ F

F I D V 9 1

1 _ B F 0 2

8 0 _ R 5 X _ V 3 . 6 _ u 0 1

9 5 1 C P

4 0 _ V 5 Y _ V 0 1 _ u 2 2 . 0

4 0 _ R 7 X _ V 0 5 _ u 1 0 . 0

0 6 1 C

2 6 1 C

P

VDDCR_ CPU PJ 20

1

2 *8mm

P

28 27

ISN_ 0

26

1 _ P

M O C 1 2

BOOT_1 1 _ W V 2 2

1 _ P S I 3 2

1 _ N S I 4 2

PR139

5V

PC1 69 0 .1u _5 0V _Y5 V_ 06

ISN_ 0

t t r r o o h h s s 2 l_ 3 l_ 4 i 4 i 1 m 1 m R 0 R 0 P 1 * P 1 *

VCORE_ON

3 0,3 3

SUSC

5 10 K _0 4

EN_ VCORE

* 0 _ 04

P R 1 47

* 0 _ 04

U4 6

0 _ 04

Z 33 01

PQ4 7 MTN7 00 2Z HS3 2

G

PR14 9 10 _0 4

33 1 VS_ PW RGD 19 ,32 DDR1 .5V_PW RGD

1 0K _1 %_ 04

3.3 VS

PC17 1 *0 .1u _10 V_X7 R_0 4

1

4

2 3

1 .8VS

MTN7 00 2Z HS3 3,1 5 APU_ PW RGD

S

G

3.3VS

Q29 D

R6 82 1 0K_0 4 APU_PWRGD_R

*74 AHC1 G08 GW

PQ46 MT N700 2Z HS3

G 1

D

5

PC17 2

D

10 0K_0 4

S

3 CPU_VDD0 _RUN_ FB_ L

P R14 8

P R 1 44

P R 2 09

3 CPU_VDD0_ RUN_F B_H

B - 36 APU CORE/ NB CORE

CPU_VDDCR

11A

ISP _0

ISN_1

1 .5V

*1 5u _2 5V_6 .3*4 .4 _C

PR1 45

7.5 K_1% _04 PR1 40 4 .02 K_ 1%_ 04

A _ V _ V 5 . 2 _ u 0 3 3 * 4 6 1 C P

PC163 2.2 u_6 .3V_Y5 V _06

29

27

Close to CPU socket

+

1 6 1 C P

30

ISP_1 PR138

9 . 5 * 6 . 6 * 6 . 6 _ V 5 . 2 _ u 0 5 + 6

+

25

3 1

ISP_0

PR12 9 *1 0m il_s ho r t

5 VS

PVCC

OCSET

PC14 9

*0 .1 u_ 50 V_ Y5V_0 6

PL9 T MPC0 60 3H-R6 8M-Z 01 1 2

PQ45 MDS26 55

4

8 8 8 0 0 0 _ _ _ R R R 5 5 5 X X _ 2 X 1 _ 5 3 _ 5 _ 5 V 5 V 1 5 V 1 5 1 5 1 5 V C 2 C 2 C 2 C _ P P 2 _ P _ P u _ u u u 7 7 7 . . 7 . . 4 4 4 4 * *

PC15 4

8 0 _ R

P C15 6

PQ44 MDS26 59

5 6 7 8

PHASE_ 0

31

LGATE_0

RBIAS

PC15 5 0 .2 2u _1 6V_0 6

32

PGND_0

ISL6265C

4

36

_NB

UGATE_0

Pin 49 is GND Pin

VIN

5 6 7 8

PR1 20 1_1 %_ 06

BOOT_0

ENABL E

PQ42 MDS26 59

C

12

1 00 0p_ 50V_ X7 R_0 4

4 2 3 1

7 8 1 1 1 1 R R P P 2 3 1 4 4 4

4 4

B N _ P

PWROK

P R 1 30

0 _ 06

5 6 7 8

3

P R 1 27

P R 13 1

PR11 1 10 _0 4

PR115 44 .2K_1 %_0 4

8 4

D N G

1

4 0 _ R 7 SGND5 X _ V 0 5 _ p 0 0 0 1

PHASE_ NB

7 2 4 1 4 1 C C P P

SGND5

Sheet 35 of 41 APU CORE/ NB CORE

4 0 _ R 7 X _ V 0 5 _ p 0 0 0 1

4 0 _ O P N _ V 0 5 _ p 3 3

P R11 2 *1 0mil_s hort

VFIX EN VID Codes


PC13 7

8 0 _ R 5 X _ V 5 8 3 2 _ 1 u C 7 P . 4

S

PJ1 6 OPEN-1 mm

0.1 u_ 10 V_ X7 R_0 4

Schematic Diagrams

Click Board CLICK BOARD

CC1 0.1u_16V_Y5V_04

CC2 *0.1u_16V_Y5V_04

C5VS CGND 1 2 3 4

CTP_DATA CTP _CLK

85201-04051 CGND

6- 20-9 4A50-104 6- 20-94AA0- 104 6- 20-9 4A70-104

CGND

1 1

1 CTP_CLK 2 CTP _DATA 3 CTPBUTTON_L 4 CTPBUTTON_R 5 6 85201-06051

2

CGND

CJ_TP3

CR2

CR3

CR4 *220_04 *220_04

CD27 Y G S

2

CGND

BAT LED

3

CD26

G Y S

*KPB-3025Y SGC

4

CGND

6-21-91A00-106 6-21-91A20-106

1

LED

*KPB-3025YSGC

4

Sheet 38 of 41 Click Board

CGND CGND

6-52-55002-042 6-52-55002-04E

CGND

6- 21-9 1A00-106 6- 21-9 1A20-106

CLED_BAT_FULL

3

2

1 CLED_PWR 2 CLED_ACIN 3 CLE D_BAT_FULL 4 CLED_BAT_CHG 5 6 *85201-06051

CGND

CLED_BAT_CHG

CLED_PWR

*220_04 *220_04 POWER ON

CVDD3

CJ_TP2

CJ_TP1

CR1

CC3 *0.1u_16V_Y5V_04

C5VS

CLED_ACIN

6-52-55002-0 42 6-52-55002-0 4E

For W250BUQ

CSW1~4 2 1

4 3

LIFT KEY

1 3

RIGHT KEY

CSW1 TJG-533-S-T/R

2 4

1 3

CTPBUTTON_L

CSW2 TJG-533-S-T/R

5 6

1

9 8 7 6

2 3 4 5

MTH237D91 CGND

CSW3 *TJG-533-S-T/R 2 4

CH1

1

9 8 7 6

2 3 4 5

CGND

CH4

1

9 8 7 6

CGND

1 3

CTPBUTTON_L

CGND

2 3 4 5

MTH237D91 CGND

RIGHT KEY

5 6

6-53- 3050B- 041

MTH237D91 CGND

1 3

CTPBUTTON_R

CGND

6-53- 3050B- 041

CH3

2 4

5 6

CGND

2 3 4 5

LIFT KEY

CH2

1

CTPBUTTON_R

5 6

CGND

6-5 3-3050B-041

9 8 7 6

CSW4 *TJG-533-S-T/R 2 4

CH5 C95D95

6-5 3-3050B-041

CH6 HO-165X94_5NP

MTH237D91 CGND

CGND

CGND

Cl ic k B oar d B - 39


Schematic Diagrams

Au di o B oar d/ USB USB PORT A R7 3 5

0 _0 6 A_ USB VCC AL 1 H CB 1 60 8 KF -1 2 1T 25

A_ USBVC C2

60 mil

A_U SBVCC A_ 5 V

5

AU 1

50mils

6

2 3

1 0u _ 1 0V_ Y5 V_ 0 8

4

V I N 1 VO UT 2 V I N 2 VO UT 3 EN#

G ND

7 AC3


AG ND

AJ _ U S B 1 A R1

*0 .1 u_ 1 6V _Y 5V_ 0 4

0.1 u _ 16 V_ Y5 V _ 0 4

A GN D A G N D

* 1 0 mil _ sh o r t _ 0 4

AGND

1

AL 1 2 2

1

6-02-09715-920

0 .1u _ 1 6V_ Y 5V_ 0 4

AC4

8

* RT 9 71 5 BGS A GND

AC2

* 10 0 u_ 6 .3 V_ B _A 2 2 u _6 .3 V_ X5 R _0 8

F L G# VO UT 1

50mils AC5

+AC 1

AC1 0

A USB_ PN2

4

A USB_ PP2

1 2 *W C M2 0 12 F 2 S -1 6 1T 0 3

A G ND

3

AUSB_ PN2 _ R

2

AUSB_ PP2 _ R

3 4

A R2

* 1 0 mil _ sh o r t _ 0 4

V+ D ATA_ L D ATA_ H 1 2 3 4 D D D D N N N N G G G G

G ND

US0 4 03 6 BCA0 8 1

1 2 3 4 D D D D N N N N G G G G

6-21- B49C0-104

AG ND

Sheet 39 of 41 Aud io Boar d/ USB

TO M/B

AUDIO JACK

EMI Requir e

AM IC1 -R

A L1 213

2

F C M 1 0 0 5K F -1 2 1 T0 3

AM IC1 -L

A L1 214

2

F C M 1 0 0 5K F -1 2 1 T0 3

AC 7 92 A_ 5 V

5 AJ _ MIC1 4 3 R

AM IC_ SEN SE M IC1 _ OUT _ R M IC1 _ OUT _ L NC _M IC1

2 6 L 1 2SJ -T 3 51 -S2 3

AC7 9 3

AJ _ AUD IO1 * 1 00 p _5 0 V_ NPO _0 4 *1 00 p _ 50 V_ NPO _ 04 1 2 3 4 5 6 7 8 9 10 11 12 13 14

AM IC1 -R AM IC1 -L AH EADPH ON E-R AH EADPH ON E-L AM IC_ SEN SE ASP K_H P# AH P_ SENSE AU SB_ PN2 AU S B _ P P 2 ASP KOUT R + ASP KOUT R -

Resisto r 3 2or 33_04 meet WLK Test 10/28Modifyvalue

A_ AUD G

VT1802P 33_1%_04 AR5 6 9

1 8 _0 1 %_04

PHO NE-R

A L 121 5

2

F C M1 0 5K F - 12 1T 03

AHEAD PHO NE-L

AR5 7 0

1 8 _0 1 %_04

PHO NE-L

A L 121 6

2

F C M1 0 5K F - 12 1T 03 AC 7 94

Layout note: H e ad p h on e ? ? ? ? > 1 0m i l s ? ? ph o n e ja ck ? ? ? ? ? ? ? ? ? R/L ? ? ? ? GND ? ? ? ? 3* ? ?

Reverse

6- 20- B2800- 106

BLACK

AHEAD PHO NE-R

8 52 0 1 -14 0 5 1-0 1 A_ AU DG AG ND

MIC IN

*1 0 0 p_ 5 0V _N P O_ 0 4

5 AJ _ HP1 4 3 R

AHP_ SEN SE PHO NE_ OU T_ R

2 L 6 1 2SJ -T 3 51 -S2 3

P H O N E_ OU T_ L ASPK_ HP# AC7 9 5 *1 00 p _ 50 V_ NPO _ 04

HEADPHONE

BLACK

EMI Requir e

A_ AUD G

2 1

AC6

0 . 1u _1 6V _ Y V 5 _ 04

HP-L

AC7

0 . 1u _1 6V _ Y V 5 _ 04

HP-R

AC8

0 . 1u _1 6V _ Y V 5 _ 04

AC9

0 . 1u _1 6V _ Y V 5 _ 04

6-20- B2800- 106 3 4

GND

6

3 * R/ L ? ?

5

GND

AL 12 7 *F CM1 6 0 8K-1 2 1 T0 6 _ sh o rt ASPKO U TR + AGND

A_ AUDG AC7 9 6

AC7 9 7

*1 u _1 0 V_ 06

*1 8 0p _ 5 0V_ N P O_ 0 4 A _AU DG

ASPKO U TR *F CM1 6 0 8K-1 2 1 T0 6 _ sh o rt AL 12 8 J_SPK1

AH 1 C 59 D 59

AH3 C5 9 D5 9

2 3 4 5

AH2

1

9 8 7 6

2 3 4 5

M TH 2 76 D1 1 1 A GND

B - 40 Audio Board/ USB

AH4

1

9 8 7 6

MT H2 7 6 D1 11 AGN D A G N D

AG ND

2

AC7 9 8

ASPKO UT R+ _ R ASPKO UT R-_ R

AJ _ S P K R 1 1 2

J_SPK1 2 1

85 2 0 4-0 2 0 01 PC B F o otp rin t =8 5 2 04 -0 2 R

*1 8 0 p_ 5 0V _N P O_ 0 4

1

A_AU DG

6- 20-43150- 102 6- 20-43110- 102

Schematic Diagrams

Power Switch & L ID Board POWER SW & LED & HOT KEY S_ 3.3 VS

S_ 3.3 VS

S_ 3.3 VS SJ _ S W 1 1 2 3 4 5 6 7 8 9 10

S_3 .3 V

POWER SWITCH LED

S_ 3 .3V SR2

S_ 3 .3V

LID SWITCH IC

SJ _ S W 2 SM _B T N # SW E B_ W W W # SW E B_ EM AIL # SL ID_ SW # SA P_ ON

S M GN D

S_ VIN

* 50 5 0 0-0 1 0 41 -0 01 L

20mil

20mil

1 2 3 4 5 6 7 8

S M GN D

SM _B T N# SW E B_ W W W # SW E B_ EM AI L# SL ID_ S W #

co-lay

SR1

Z4301

1

S D3 * HT -1 50 N B-DT

S MGN D

SAP_ ON

A

6- 52-56001- 023 6- 52-56001- 028 6- 52-56000- 020 6- 52-56001- 022

6- 20- 94K10- 108

*0 .1 u_ 1 0 V _X7 R_ 0 4

SU1

2

C

A

S C1

M H2 4 8-A LF A -E SO

SM GN D

*1 00 p _ 50 V_ NPO _ 04 S M GND

SM GN D

C

6-526-526-526-52-

SLID _ SW #

OU T

3

0 .1 u_ 1 6 V_Y 5 V_0 4 S MGN D HT -1 5 0N B-DT

S MG ND

56001-023 56001-028 56000-020 56001-022

S MGN D

6- 02-00248- LC2 6- 02-00268- LC1

SU1, SU2 3 1

FOR E5128Q

6- 53- 3150B-245 6- 53- 3050B-241 6- 53- 3050B-240

HOT KEY

6- 53- 3150B-245 6- 53- 3050B-241 6- 53- 3050B-240

POWER BUTTON SPW R _ SW 1 T J G-5 33 -S-T /R 1 3

2 4

S M_ B T N#

1 3

5 6

FOR E4120Q/ E5120Q

6- 53-3150B- 245 6- 53-3050B- 241 6- 53-3050B- 240

WEB_WWW# SW W W _S W 1 *T J G-5 3 3 -S-T/ R 2 4

1 3

SC4

5 6

2 4

SA P _SW 1 * T JG -53 3 -S-T /R

SW EB_EM AIL #

1 3

SC3

5 6

* 0.1 u _ 16 V_ Y 5 V _ 04

1 2

S M GN D

SM GN D

*0 .1u _ 1 6V_ Y 5V_ 0 4

S M GN D

S MG ND

2 4

S A P _O N

SC 5

5 6

SR4 *0 _ 0 4

PSW1~8 3 4

Sheet 40 of 41 Power Switch & L ID Board

AP_KEY#

SR 3 * 10 0 K_ 1% _ 0 4

S MAIL _ S W 1 * T JG -5 33 -S-T /R SW EB_W W W #

2

6-53- 3150B-245 6-53- 3050B-241 6-53- 3050B-240

S_ V IN

WEB_EMAIL#

*BA V 99 RE CT IF IER

AC

D N G

SC 2

SD 1

SMG ND

1 0 0 K _0 4

VC C

SC6

8 8 48 6 -0 80 1

10 pin & 8 pin

20mil

A

SD2 C

S _ 3 .3 V

22 0 _0 4

20mil

SR5 * 4 7K_ 0 4

* 0 .1u _ 1 6V_ Y 5V_ 0 4

S MG ND

S MGN D

S MGN D

SM GND

FOR E5120Q

SMG ND

POWER BUTTON

1 3

SPW R _ SW 2 *T J G-5 3 3 -S -T/ R

SMH2 H7 _0 D 2_ 3 2 4

SMH 5 H7 _ 0D 2 _3

SMH6 T1 5 8B 11 8 X8 7 D1 1 8 X8 7

S MH 7 T1 5 8 B91 D 91

SM H1 2 3 4 5

S M_ BT N#

1

S MH3 9 8 7 6

2 3 4 5

1

SMH 4 9 8 7 6

2 3 4 5

9 8 7 6

1

5 6

PSW1~8 3 4

SM GN D

1 2

M TH 2 37 D8 7 S MG ND S MG ND

M T H2 37 D 87 SMG ND

MT H2 3 7D 1 18 SM GND

SM GN D

S MG ND

6- 53- 3150B-245 6- 53- 3050B-240 6- 53- 3050B-241

FOR E5128Q

Power Switch & LID Board B - 41


Schematic Diagrams

EXTERNAL ODD Board QJ_ODD2 S1 S2 S3 S4 S5 S6 S7

QJ_ODD1 S1 S2 S3 S4 S5 S6 S7

QJ_SATA_TXP1 QJ_SATA_TXN1 QJ_SATA_RXN1 QJ_SATA_RXP1

QGND P1 P2 P3 P4 P5 P6


QGN D QJ_ODD_DETECT# Q_5VS

P1 P2 P3 P4 P5 P6

Q_5VS QJ_SATA_ODD_D A#

1-162-100562

242001-1 PIN GND1~3=QG ND

PIN GND1~2=WGND

Sheet 41 of 41 EXTERNAL ODD Board

QGND

QGND

6-21-14010-013 6-21-14020-013 6-21-14030-013

6- 21-13A00- 013

Q_5VS

QC1

QC2

0.1u_16V_Y5V_04

*0.1u_16V_Y5V_04

QGND

B - 42

QH1 C237D91

QH4 C237D91

QGND

QGND

QH3 C67D67

QH2 C67D67

BIOS Update

Appendix C:Updating the FLA SH ROM BIOS To upd ate the FLASH ROM BIOS you mus t: • • • • • • •

Download the BIOS update from the web site. Unzip the files onto a bootable CD/DVD/USB Flash Drive. Reboot your computer from an external CD/DVD/USB Flash Drive. Use the flash tools to update the flash BIOS using the commands indicated below. Restart the computer booting from the HDD and press F2 at startup enter the BIOS. Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer. After rebooting the computer you may restart the computer again and make any required changes to the default BIOS settings.

Download the BIOS 1. Go to www.clevo.com.tw and point to E-Services and click E-Channel. 2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files (the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model (see sidebar for important information on BIOS versions ).

Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive 1.

Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the downloaded files. 2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software).

BIOS Versio n Make sure you download the latest correct version of the BIOS appropriate for the computer model you are working on. You should only download BIOS versions that are V1.01.XX or higher as appropriate for your computer model. Note that BIOS versions are not backward compatible and therefore you may not downgrade your BIOS to an older version after upgrading to a later version (e.g if you upgrade a BIOS to ver 1.01.05, you MAY NOT then go back and flash the BIOS to ver 1.01.04).

Set the comput er to boot f rom th e external drive 1. 2. 3. 4. 5.

With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the computer and press F2 (in most cases) to enter the BIOS. Use the arrow keys to highlight the Boot menu. Use the “+” and “-” keys to move boot devices up and down the priority order. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS. Press F4 to save any changes you have made and exit the BIOS to restart the computer.

C - 1

C : B I O S U p d a t e

soneview N1405 6-71-W2400-D03-GP.pdf

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