Custom Design (SDL)
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Custom Design with Pyxis Schematic Capture
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In this tutorial, you will need each of the NMOS, PMOS, VDD, Ground, PortIn and PortOut to build the simple inverter schematic. The screenshot below shows the schematic diagram that you will be done in this tutorial.
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Invoking the Pyxis Design Manager To invoke the Pyxis Design Manager Open the new terminal on Linux OS To invoke the pyxis design manager, type “dmgr_ic”
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Invoking the Pyxis Design Manager
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Pyxis Design Manager
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Creating New Project 1. Click on “File > New > Project” and under the technology library path, point to “/EDA/MentorGraphics/tech_libs/sil013_kit”. After that, name your project in the Project path, e.g /home/training/tutorial. Then click “OK” to continue.
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2. On the Manage External/Logic Libraries, click on “Add Standard Libraries”, to add the Pyxis Libraries.
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The external libraries will be included as shown.
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3. Select your project name at the Project Navigator, click on the “New Library” icon; and name your library name as shown below. e.g “component” and click “OK” to continue.
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4. Select the library which you created at the previous step, then click on “New Schematic” icon; and name your schematic folder as shown below. * Then the Pyxis Design Manager will automatically invoke the Pyxis Schematic.
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Pyxis Schematic Introduction Menubar
Toolbar
Palette Message Area / Transcript Area
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5. On the Pyxis Schematic, click on “Add > Instance…”,then point the browser to “$SIL013_KIT/lib/mosfet” and select “nm_hp” and click on “OK”. Then paste the nmos on the schematic sheet.
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6. Use the hotkey “Q” to change the width of the nm_hp to 1u. Then click “OK” to proceed.
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7. Use the hotkey “I” to call the instance and “Q” to change the symbol path to obtain a pm_hp and change the width of the pm_hp to 2u. * You may change the path under the attribute to obtain different component.
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8. Repeat step 5 to obtain the VDD, VSS, PortIn and PortOut from the library “$SIL013_KIT/lib” directory.
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6. Connect all the components as shown below by using wires. Click on “Add > Wire” or you may use the hotkey “W”.
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9. Rename the NetName of the PortIn and PortOut to “in” and “out” respectively by selecting the instance and use the hotkey “Q” to change the properties of the instance.
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10. Once the schematic is done, click on “File > Check Schematic” to check for connection error. If errors occurred, fix the error and run the schematic check again. If your design is error free, then you may close the schematic checking report and save your schematic by clicking on “File > Save Sheet > Default” and proceed to the next step.
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*You may close the schematic checking report by using the strokes command by clicking “MMB > drag to the left”. For othe strokes commands, you may find it by drawing a “?” with MMB on the screen.
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11. Click on “Add > Generate Symbol…” a window will pop up. 12. Click on “Choose Shape” to choose the shape of your symbol. In this case, “Buffer” is selected.
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13. Click on “Customize Pinlist” to customize the pinlist according to the screenshot below.
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The symbol will be generated as shown.
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14. Click on “File > Check Symbol” to check for connection error. If errors occurred, fix the error and run the schematic check again. If your design is error free, then you may close the symbol checking report and save your schematic by clicking on “File > Save Symbol > Default” and proceed to the next step.
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15. Click on the “component” library on the Project Navigator. 16. Click on the “New Schematic” icon, a window will pop up to name your schematic folder and click on “OK”. e.g “inverter_tb”.
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18. Click on “Add > Instance… > Choose Symbol” , a file browser will pop up. 19. Click on the “component” library and select the “inverter” as you created at the previous chapter. Then, click “OK” to get the inverter symbol.
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20. Paste the “inverter” on the schematic sheet. 21. Click on “Add > Instance… > Choose Symbol” or with the hotkey “I”, to call the components from the library. 22. Click on “$SIL013_KIT/lib > vdd” to select the VDD port and paste it on the schematic. *Select also the VSS at the same library and paste it on the schematic.
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23. Repeat step 21&22 to obtain the pulse_v_source and dc_v_source in the library path “$SIL013_KIT/lib/source/voltage_source” and paste it on the schematic.
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24. Connect all the components as shown below by using wires. Click on “Add > Wire” or you may use the shortcut key “W”.
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25. Select the pulse_v_source by clicking the instance and press “Q” to change its properties. Change the delay from 1us to 1ns. *Perform the same way to change the property of dc_v_source. Change the DC from 1V to 1.2V.
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26. Add the NetName of the wire to “in” and “out” respectively as shown below by selecting the wire and click on “RMB > Name Net”.
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27. Once the schematic is done, click on “File > Check Schematic” to check for connection error. If errors occurred, fix the error and run the schematic check again. If your design is error free, then you may close the schematic checking report and save your schematic by clicking on “File > Save Sheet > Default” and proceed to the next step.
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28. Click on “Enter Simulation Mode” on the left toolbar to enter to the Simulation Mode. 29. On the Enterting Simulation Mode window, select “Analog Mixed Signal” as the Simulation Type, then click on “OK” to continue.
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30. To setup the simulation, first click on “Setup Netlister” on the toolbar. Make sure the setting of the Setup SPICE Netlister is similar with the screenshot as shown below and click “OK” to confirm the setting.
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31. Click on “Setup Libraries…” on the toolbar to setup the simulation. 32. On the Libraries, select “Typical” in the “Active model scenario:”.
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33. On the same window, click on Analysis Setup and check the Transient as the analysis method, then click on “Apply”.
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34. Expand the Analysis Setup and select the Transcient Setup. 35. Key in the Output Start Time with the value of 0 and click on “Apply”.
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36. On the same window, click on Edit Waveforms. 37. Click on “Probe All Voltages” to probe all the nodes at the end of the simulation.
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38. Close the Setup Simulation window then click on the “Run Simulator” icon on the toolbar to run the simulation.
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39. Once the simulation is completed, click on “View Wave > New Window” on the toolbar to view the simulation result.
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40. Click on the TRAN folder to view all the waveforms. You may double clicks on the node to view the waveform in time domain.
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41. Click on “Add Cursor” on the toolbar or you may use “F5” as the hotkey to add a cursor to the waveform for analysis purpose. *You may select the cursor and move along the waveform.
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42. Select the cursor and click on “RMB > Move To…” to locate the cursor to a specific location.
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43. Enter the location you want to locate the cursor in the Move Cursor window e.g “5e-8” or “50n”, then click on “OK”.
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The cursor will then move to the specified location.
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Custom Design with Pyxis Layout Drawing
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1. Select your “inverter” cell on the Explorer pane. Then click on the “New Layout” icon to create a new layout sheet. Click “OK” to continue with the default setting.
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Pyxis Layout will be invoked automatically with all files setting are retrieved from the sil013_kit design kit. 2. Click on “OK” to confirm with the layout setting.
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Pyxis Layout will automatically create a Schematic Driven Layout (SDL) with both schematic and layout sheet is display at the same time.
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3. Select the pm_hp transistor on the schematic sheet, and click on “Inst” on the DLA Logic Palette.
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4. The pm_hp layout will be automatically generated, then paste it on the layout sheet.
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5. Repeat step 4 to generate the nm_hp transistor layout on the layout sheet. *You may use the hotkey “V” to align the 2 transistors. (can be seen from the Dynamic Status which has been highlighted in the screenshot below.) *Your layout now will be look like the screenshot below. The Overflow in the middle are showing their connection from 1 pin to another.
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6. Select the PortIn on the schematic and click on “Port” on the DLA Logic palette.
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7. The PortIn will be generated and paste it on the bottom left corner of the pm_hp transistor.
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8. Repeat step 7 to paste the PortOut on the bottom right of the pm_hp. Do the same thing to the VDD and VSS; paste it on the top left corner of the pm_hp transistor and bottom left corner of the nm_hp transistor respectively. *You may use the hotkey “V” to align the ports.
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Once you are done, the layout will look as the screenshot shown below.
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9. Use the hotkey “E” to expand the VDD port by clicking on the right side of the VDD port and drag it to the right. *You may use the hotkey “V” to find the alignment with the pm_hp transistor.
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10. Repeat step 9 to expand the VDD port vertically upward with the size of 0.35um.
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The VDD port will be expanded as shown below.
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11. Repeat step 9 and 10 to expand the VSS port at the bottom part of the nm_hp transistor.
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12. Select the VDD port and click “Easy Edit > Via > Fill Selected” on the IC Palette. 13. Select the “m1nwell” on the ICdevice Shape Via window, and click on “OK” to add the nwell contact to the pm_hp transistor.
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The nwell contact will be automatically generated base on the size of the MET1.
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14. Repeat step 12 and 13 to generate the pwell contact to the nm_hp transistor by selecting “m1pwell” on the Icdevice Shape Via window.
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Once you are done, the layout will look as the screenshot shown below.
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15. Use the hotkey “I” to route the source terminal of the pm_hp transistor to the VDD port.
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*You may use the hotkey “H” to view the available hotkeys for IRoute in the IRoute Single Path Hotkeys window.
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16. Move the MET1 layer upward to connect to the VDD port and use the hotkey “W” to change the width of the MET1 layer to “0.26” or use “Shift+W” to automatically change the MET1width as the same with the width of the source pin of the pm_hp transistor.
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17. Repeat step 15 and 16 to route the source terminal of the nm_hp transistor to the VSS; alsothe drain of the pm_hp transistor to the drain of the nm_hp transistor.
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18. Click on Path on the pallete, then use the hotkey “Q” to modify the property accordingly, then draw a POLY path to connect the gates of the 2 transistors.
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19. Repeat step 15 to route the output port to the drain of the 2 transistors.
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20. Select the “in” port and use the hotkey “Q” to modify its width and height to 0.35um; then fill the port with the “polym1” via.
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21. Connect the poly gate to the “in” port by using a POLY path.
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22. To label the ports, first select the M1.TEXT layer on the Layer Palette.
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23. Click on “Add Text” icon on the toolbar or use the hotkey “T” to add the text to the ports of the inverter. 24. Use the hotkey “Q” to change the Attribute of the text in the Add text window. (Value = in; Text Height = 0.2)
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25. Move the Add Text window aside and paste the text (in) to the input port. 26. Repeat step 23 to 24 to add the text for output, VDD and VSS port with text value “out”, “VDD” and “VSS” respectively.
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The complete layout of the inverter is shown as below.
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Design Rule Check (DRC) DRC is a verification of the process design rules and supplementary rules. Basically, it verifies whether all the polygons and layers from the layout database meet all of the manufacturing process rules. Fundamentally, these design rule represent the physical limits of the manufacturing process.
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Layout Versus Schematic (LVS) LVS is to verify whether physical layout is correctly matched with reference to the schematic. In LVS, the following is verified: 1. Electrical connectivity of all signals (input, output and power) to their corresponding devices. 2. Devices size: transistor, resistor, capacitor… 3. Identification of any extra components and signals which is not found in the schematic.
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Parasitics Extraction (PEX) Extraction process of the parasitics from a completed layout. Simulation is done on the extracted netlist to ensure the design is function within the specification.
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27. Click on “Tools > Calibre > Run DRC” to invoke the Calibre nmDRC. 28. Click on “Run DRC” to start to perform checking.
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29. On the Calibre RVE window, click the “down arrow” to find the errors in the report. 30. If error occurred, you may double clicks on the coordinate to locate the error on the layout. *Fix the layout and run the DRC again until all errors are solved.
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You should obtain an error free DRC report before proceed to next stage.
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31. Click on “Tools > Calibre > Run LVS” to invoke the Calibre nmLVS.
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32. Click on “Setup” on the menubar of the nmLVS window to enable the LVS Options. 33. On the LVS Options, key in VDD and VSS at the Power nets: and Ground nets: respectively to define the power and ground net of the layout.
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34. Click on “Run LVS” to perform the LVS checking.
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Once the LVS checking process is done, a LVS checking report will display the LVS results. Similarly, if error occurred, you may need to fix all the errors before proceed to the next stage; else close the report and exit the LVS checking.
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35. Click on “Tools > Calibre > Run PEX” to invoke the Calibre PEX.
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36. Click on “Inputs” and select the “Netlist” tab and check the Export from schematic viewer option, then click on “OK” to continue.
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37. Click on “Outputs” and under the “Netlist” tab, select “DSPF” as the format instead of “ELDO”.
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38. Click on “Setup” and enable the “PEX Options”. 39. Under the “LVS Options” tab, key in VDD as the Power nets and VSS as the Ground nets.
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40. Click on “Run PEX” to run the parasitics extraction process.
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A new netlist with parasitics will be generated as shown below.
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41. Open the “inverter_tb > eldonet” on the Vire Pane to invoke Pyxis Schematic to enter to the simulation mode of the testbench directly.
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42. Select the “INVERTER1” instant and click on “Tools > Parasitics > Add DSPF” to include the parasitics netlist for simulation. 43. Browse the parasitics netlist file which generated in step 6 “$TUTORIAL/component/inverter/inverter.cal/inverter_layout.pex.netlist”; then select “Schematic” in the “Simulate using devices from:” options.
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Once the parasitics netlist is included, it will be displayed on the schematic as shown below.
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44. Click on “Run Simulator” on the toolbar to perform the post simulation.
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45. Once the simulation is completed, click on “View Waves > New Window” to view the simulation output waveforms.
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46. Click on the TRAN folder to view all the waveforms. You may double clicks on the node to view the waveform in time domain.
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You may open the original simulation waveform to compare with the output waveform with parasitics.
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The End
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