SemiconductorDevicePhysics_4pt3 [Sze]

Introduction to

Semiconductor Device Physics

Tom Cunningham Rev. 4.3, November 2001

Introduction to Semiconductor Device Physics / Electronic Electronic Properties of of Silicon / rev 4.3

Tom Cunningham Cunningham

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Introduction to

Semiconductor Device Physics A user-friendly introduction to semiconductor device physics and digital CMOS circuits



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1 Electronic Properties of

Silicon



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This is the first module in a five-module introduction to semiconductor device physics. The modules are: 1. Electronic Properties of Silicon 2. The PN Junction 3. The MOS Capacitor 4. The MOSFET 5. Small Circuits

The purpose of this module is to study the electronic properties of silicon (and other semiconductors), to understand what a semiconductor is and how they behave. We will begin by studying pure silicon, and then move on to study doped silicon – N-type and P-type.

The objectives of this module are: • Understand the covalent bonding of silicon atoms • Understand the energy band diagram – conduction band, valence band, band, and band gap • Understand thermal generation and recombination • Understand the charge carriers in a semiconductor semiconductor – electrons and holes • Understand the conduction properties of pure (intrinsic) silicon • Understand the bonding diagram, band diagram, and conduction properties of N-type silicon • Understand the bonding diagram, band diagram, and conduction properties of P-type silicon • Understand the meaning and importance importance of the Fermi distribution and the Fermi energy level

Looking Ahead: After studying the electronic behavior of N-type and P-type silicon in this module, we will combine these concepts in the next module to understand the physics of the PN Junction.



1-5

Silicon - Atomic Structure I 1

3

H Li

11

Na

II 2

4

III

IV

V

VI

VII

VIII 2

He

Periodic Table of Elements 5

(abridged)

Be

12

6

B

14

13

Mg

C

Al

Si

7

N

15

P

8

O

16

S

9

F

17

He

10

Ne

18

Cl

Ar

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

K Ca

Rb

Sc

Sr Y

Ti

V

Zr Nb

Cr Mn

Mo

Tc

Fe Ru

Co Rh

Ni Pd

Cu

Ag

Zn Cd

Ga In

Ge Sn

As Sb

Se Te

nucleus

Br Kr I

Xe

14

Si Atomic Number (Z) valence electrons (4) (outermost shell)

n=1

28.0855

Atomic Mass [amu]

n=2 core electrons (10) (inner shells)

n=3

1s22s22p63s23p2



1-6

Silicon is the semiconductor of choice for the modern digital microelectronics industry. (The reasons for this will be presented in module 4, when we are in a better position to discuss them.) We will begin by studying the electronic properties of silicon to understand what a semiconductor is.

Silicon has atomic number Z = 14 on the Periodic Table of Elements, indicating that the Si atom has 14 protons in its nucleus and 14 electrons surrounding the nucleus. Using Bohr’s “planetary” model of the atom, the four electrons in the outermost orbit or “shell” are the valence electrons; the other ten are core electrons. Note that Si resides in column 4 of the Periodic Table, and therefore has four valence electrons. The valence electrons participate in chemical bonding.



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Pure Silicon - Bonding Diagram

Si

Si

Si

Si

Si

Si

nucleus + core electrons Si

valence electron

covalent bond Silicon Atom

Si

Si

Si

Schematic Diagram of Covalent Bonding in Silicon (T = 0 K)

Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1-8

Those elements in column 8 of the Periodic Table are called the noble gasses ; they have a full outer shell (8 valence electrons). The noble gas structure is the lowest energy configuration, hence the noble gasses are chemically inert.

Other, “non-noble” atoms will form chemical bonds in order to approximate the noble gas structure. Silicon forms covalent bonds as shown schematically; by sharing valence electrons with nearest neighbors, each Si atom is surrounded by eight valence electrons, like a noble gas. These bonds hold the atoms together to form a solid, and play a key role in the electronic properties of the material as well.


Tom Cunningham

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Pure Silicon - Energy Band Diagram

Si

Conduction Band

Si

EC

Si

Si

Si

y g r e n E n o rt c e l E

Ei

EG = 1.1 eV

EV

Si

0 eV

Valence Band

Energy Band Diagram (T = 0 K)

Bonding Diagram (T = 0 K)


1.1 eV

Tom Cunningham

1 - 10

Energy band diagrams are very useful for studying what the electrons inside a semiconductor material are doing. The vertical axis represents electron energy. The horizontal axis represents distance or positionx() in the semiconductor sample. An electron in a chemical bond resides in the valence band on this diagram (the top of the valence band E is usually taken to be the zero of the V energy scale, which is a conventional but arbitrary choice).

At absolute zero* all of the electrons are in the valence band.

The Fermi energy level , E , will be introduced later. E F i is the Fermi level in pure (aka. intrinsic) Si, and hence is called the intrinsic Fermi level ; it is near the middle of the band gap.

* Technical Aside: Absolute zero (0 Kelvin = -273 oC) is the theoretical minimum of temperature, i.e. as “cold” as an object or material can possibly get. It is sometimes described as the temperature at which all molecular motion ceases, though perhaps a more precise definition (from the standpoint of quantum physics) is that absolute zero is the temperature at which no thermal energy whatsoever is available to, or extractable from, the system. Real objects/materials can approach absolute zero asymptotically in a laboratory setting, but never reach it. It is, however, a very useful concept for discussing the behavior of a material in the absence of thermal energy.


Tom Cunningham

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Pure Silicon - Thermal Generation (Low Temp) n = p = ni free electron

Si

Si

free electron Si

n = concentration of electrons in conduction band (cm-3)

EC

Si

Si

Si

E

hole

Si

Si

thermal generation (electron hole pair)

Ei

EG = 1.1eV

EV Si hole

Bonding Diagram (Low Temperature)


p = concentration of holes in valence band (cm-3)

Energy Band Diagram (Low Temperature)

Tom Cunningham

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At temperatures above absolute zero, thermal generation takes place - i.e. an electron gains enough energy to break out of the covalent bond and becomes free to roam about inside the solid. This leaves behind h aole (vacancy) in the bond. Thus, thermal generation is said to create electron-hole pairs .

Thermal generation is also depicted in the band diagram. The electron traverses theband gap and resides in the conduction band. A hole is left in the valence band. For silicon, the band gap is 1.1 eV, meaning that the electron must gain at least this much energy to break free from the covalent bond. If it has less than this, it can not break free from the bond, and remains in the valence band on the band diagram. Hence, electrons are not found inside the band gap; they reside in either the valence band or the conduction band. The band gap can be thought of as forbidden energy states for the electrons.

Because free electrons and holes are created in pairs, the concentration of free electrons in the conduction band n (electrons / cm3) is equal to the concentration of holes in the valence band p (holes / cm3). Theintrinsic carrier concentration n i is equal to the number of electron-hole pairs, i.e. n = p = ni for pure silicon.


Tom Cunningham

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Pure Silicon - Thermal Generation (Room Temp) n = p = ni

Si

Si


Si

EC

Si

Si

Si

E

Ei

EG = 1.1eV

EV Si

Si

Si p = concentration of holes in valence band (cm-3)

Bonding Diagram (Room Temperature)


Energy Band Diagram (Room Temperature)

Tom Cunningham

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As the temperature increases, more thermal generation takes place, hence n and p increase.


Tom Cunningham

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Pure Silicon - Thermal Generation (High Temp) n = p = ni

Si

Si


Si

EC

Si

Si

Si

E

Ei

EG = 1.1eV

EV Si

Si

Si p = concentration of holes in valence band (cm-3)

Bonding Diagram (High Temperature)


Energy Band Diagram (High Temperature)

Tom Cunningham

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At a high temperature, there is a lot of thermal generation.

(Note: When the temperature reaches the melting point, so many covalent bonds will be broken that the solid will not be able to o hold together, and the material will become liquid. Silicon has a melting point of about 1400 C. In this course, we will concern ourselves only with temperatures well below the melting point.)


Tom Cunningham

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Aside: A Closer Look at Covalent Bonds r U(r) coulombic repulsion of nuclei

Si

Si

r eq r

equilibrium bond length

isolated atoms

r eq Si

Si

U(r) r electron in coulombic potential well of nucleus

electron in coulombic potential well of two nuclei (covalent bond)

n=3 n=2

( r )= U n=1

1

barrier lowering

q1q 2

o 4πε r

Si nucleus

Si nucleus

r eq

r Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Si nucleus

Tom Cunningham

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The top diagram shows two silicon atoms as they are brought closer to each other. Their separation distancer )( is plotted against the potential energy of the system, U(r). When the atoms are far apart (isolated), they have no interaction and the net potential energy is zero. As they are brought closer together, their valence electrons start to interact and form a covalent bond; this bond is energetically favorable, and the total potential energy of the system is reduced. (Recall that, in general, nature favors lower energy.) There is some equilibrium separation (the “valley” on the energy plot) that represents the equilibrium bond length (at a given temperature). If the atoms are pushed closer together than this, a sharp rise in the potential energy of the system occurs due to the coulombic repulsion of the (positively-charged) nuclei.

The bottom diagram shows the potential energy of an electron in an atom, due to the coulombic attraction between the positivelyr charged nucleus (protons) and the negatively-charged electron. The potential energy goes as 1/ , where r is the separation between the electron and the nucleus (determined by which shell the electron is in). Thus, we can say that the electron is in a coulombic potential energy “well”, as shown on the diagram.

When two atoms are brought together to form a covalent bond, the electron in the bond now feels the attraction of both nuclei, and thus it has a lower potential energy. The energy “barrier” is lowered in the region between the two nuclei, and the electron can be shared between the two. Thus, the covalent bond is formed, and holds the two atoms together.


Tom Cunningham

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Aside: Where the Band Gap Comes From Si

Si

Si

Si

n =3

Levels split when atoms form bond

Electron energy levels of isolated atoms

n =2 n =1

Si electron configuration: 1s22s22p63s23p2

r req


Tom Cunningham

1 - 20

The electrons in an atom occupy different energy levels. When two atoms are brought together to form a covalent bond, these levels split. (This is required by the Pauli Exclusion Principle, which says that no two electrons in an interacting system can have the same quantum numbers.)

For an assemblage of silicon atoms, N -way splitting will occur (in a real sample N is very large – e.g. there are 5x1022 Si N 3 atoms/cm ). This is shown for the case of silicon in the diagram. At the far right of the graph, the silicon atoms are isolated (their separation is large). As they are brought together to their equilibrium separation, band splitting occurs as shown, resulting in the conduction band, valence band, and band gap. (Because there are so many energy levels and they are so closely spaced, each band can be treated as a continuum of energies.)

Note from the electron configuration and the diagram that the valence band is full of electrons (contains all the valence electrons, i.e. the 3s2sp2 electrons), and the conduction band is empty – this of course is at absolute zero, where there is no thermal generation taking place.


Tom Cunningham

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Aside: Inside a Semiconductor

EC EG EV

Si

Si

Si

Si

tunneling


Tom Cunningham

1 - 22

Combining the concepts from the previous two slides.

Note that the movement of electrons in the valence band is carried out via tunneling*. A hole must exist on the other side of the barrier for the electron to tunnel into (which is equivalent to the hole tunneling in the opposite direction). We will discuss carrier motion later in more detail when we discuss conduction.

* Technical Aside: Tunneling is a central concept in modern physics (but having no analog in classical physics). Tunneling refers to the transport of a particle (like an electron) across or through a potential energy barrier even though that particle does not have sufficient energy to overcome that barrier according to classical physics. In the example presented here, the electron does not have enough energy to travel over the potential energy “hill” shown in the diagram, and hence according to classical physics it can not get to the other side of the barrier. But according to modern physics, under the right conditions the electron can tunnel through the barrier to the other side. Despite its somewhat esoteric and counterintuitive nature, the phenomenon of tunneling has a sound theoretical foundation, and has been experimentally observed in a wide variety of physical systems. We will encounter this concept several times during this course.


Tom Cunningham

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Fermi Function & Fermi Level

Fermi Function

f(E)

1 f ( E) = E − EF · § 1 + exp ¨ ¸ © kBT ¹

1

T1 T2

1/2

0 E = electron energy EF = Fermi energy level -5 -23 J/K k B = Boltzmann constant = 8.617x10 eV/K = 1.381x10 T = Temperature (K) k BT = thermal energy = 0.260 eV at 300 K


T = 0 K

0 < T1 < T2

Tom Cunningham

EF

E

1 - 24

Thermal generation is a statistical process, i.e. it is not possible to predict whether a particular electron will be promoted to the conduction band or not, but it is possible to predict statistically how many (or what percentage) of a large population will be promoted. TheFermi function is used for this purpose. Derived based on Fermi-Dirac statistics, theFermi function f(E) gives the probability of finding an electron at energy E .* Hence, it takes on values in the range 0 to 1 (i.e. 0% to 100%).

is the Fermi energy or E Fermi level. It is the “pivot-point” of the tail of the distribution, and the length of the tail is determined F by the temperature T . Note from the equation that the probability of finding an electron at the Fermi energyE ( = E ) is always F 50% (regardless of temperature). Think of the Fermi level as a “water mark” for the electron energies. It will prove to be a very important quantity in the foregoing discussion.

*

Technically, f(E) is the probability of finding the electron in some energy interval E to E + dE , where dE is an infinitesimal increment in energy.


Tom Cunningham

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Density of States conduction band:

gc ( E )=

g(E)

C mn * 2mn * ( E ) − E

2

3

π 

)~ g ( E

E

E ≥ EC

valence band:

gv ( E )=

mp * 2mp * ( E ) V − E 2

3

π 

E ≤ EV

0

E

carrier concentrations: ≡ h/2π = 1.055x10-34 J•s h = Planck’s constant = 4.136x10 -15 eV.s = 6.626x10 -34 J.s mn* = Electron effective mass mp* =Hole effective mass 

∞

n=

f ( E ) g ( E )dE ³ c

E C V E

p=

( E )]g ( E ) dE [1 − f ³ −∞ V


Tom Cunningham

1 - 26

The Fermi function gives the probability of finding an electron at energy E , but it doesn’t tell us whether (or how many) available energy states exist at that energy. Thedensity of states function, g(E), is derived from a quantum-mechanical treatment of the conduction/valence bands, and approximates the number of energy states per unit volume at energy E .* The probability of finding an electron at energy E is given by f(E)*g(E). Integrating f(E)*g(E) over the conduction band energy range gives n, the total concentration of electrons in the conduction band. (Note that since the Fermi function goes to zero beyond the Fermi level, it is possible to make the integral unbounded at the upper end, thus simplifying the integration.)

Since the probability of finding an electron at energy E is given by f(E), it follows that the probability of finding a hole (vacancy) at energy E is given by 1 – f(E). Integrating [1f(E )]*g(E) over the valence band energy range gives p, the total concentration of holes in the valence band.

The quantities mn* and mp* are the electron and hole effective mass, respectively (numeric values are provided later in this module). Newton’s second law of motion for an electron in free space is F = m0a (where F is the force acting on the electron, m0 is the mass of the electron in free space, and a is the acceleration of the electron). For an electron inside a semiconductor, the analogous expression isF = mn*a, where mn* is the effective mass (particular to the semiconductor material).

The mass of a hole may seem like a contradiction of terms at this point. We will clarify it shortly.

g(E For our purposes, we are less interested in the mathematical details of the expression for ), and more interested in the general shape of the curve, specifically the observation that thatg(E) goes as the square root of energy E .

*

Technically, g(E) is the density of available energy states in some energy interval E to E + dE , where dE is an infinitesimal increment in energy. Rarely f(E) and g(E) are used primarily in derivations of other quantities does one plug in numeric values to calculate f(E) and g(E) themselves; the expressions for (e.g. deriving expressions for the carrier concentrations by finding closed-form solutions for the integrals shown above).


Tom Cunningham

1 - 27

Density of States - Analogy

SILICON

visitors

g(E) = number of available energy states at energy E f(E) = probability of finding an electron at energy E f(E)*g(E) = number of electrons at energy E

³ f(E)*g(E) dE = total number of electrons in conduction band

STADIUM g(E) = number of seats in row E

EC

f(E) = probability of someone sitting in row E

EG (no seats)

f(E)*g(E) = number of people in row E

Σ f(E)*g(E) = total number

EV

of people in the visitors side of the stadium

home


Tom Cunningham

1 - 28

An analogy to help us understand the density of states, and how it is used.

The conduction and valence bands are like the home and visitor sections of a football stadium. Each row has a certain number of seats (though all the rows do not necessarily have the same number of seats). There is some probability that a person will want to sit in a given row; like electrons preferring lower energies, fans tend to prefer the front rows. By multiplying the number of seats in a given row by the probability of someone wanting to sit in that row, the ticket agent can predict how many people total will be sitting in that row (on average). (Whereas the ticket agent would have to come up with a probability function of his own, perhaps based on historical data, we have the Fermi function.) By summing (integrating) this for all rows in the visitor section, the ticket agent can predict how many people total will sit in the visitor section (on average).

And similarly for the home section.

The field is like the band gap – there are no seats there, so people are not found sitting there; they may cross the field to the other side, but they do not sit on the field.


Tom Cunningham

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The Relationship Between the Fermi Function, Density of States, and Carrier Concentrations

1 - f(E)

f(E)

source: Pierret & Neudeck (editors), Modular Series on Solid State Devices, vol. 1, Addison-Wesley Publishing, 1988.


Tom Cunningham

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This slide shows graphically the relationship between the Fermi function, the density of states, and the electron and hole concentrations for pure silicon. You can “visually” multiply the Fermi function and the density of states function together to generate the electron concentration shown. Repeat using [1 f(E) – ] to generate the hole concentration.

Aside -- A Closer Look at Energy: We are now in a position to understand the energy band diagram in greater detail. The vertical axis E represents the total energy of the electron (potential energy + kinetic energy). E represents the - E G = E C V potential energy of the electron (with E represents the potential energy of the electron). The ≡ 0 we can simply say that E V C kinetic energy of the electron is then given by E – E (the higher the electron is in the conduction band, the more kinetic energy it C has). In other words,E is the minimum amount of thermal energy the electron must acquire to break free from the bond (enter C the conduction band), and any additional energy acquired by the electron becomes its kinetic energy. As for holes, the argument is analogous. We will see shortly that hole energy increases in the downward direction on a band diagram, and it follows that the hole kinetic energy is |E | (the deeper the hole is in the valence band, the more kinetic energy it has). Treating the hole as an – E V independent positively-charged particle, it is easy to visualize what it means for a hole to have kinetic energy. Thinking of the hole as a bond vacancy, it means that an electron occupying an energy level down in the valence band was promoted to the conduction band. (Conservation of energy will require that the electron which fills this vacancy (during recombination) have sufficient kinetic energy to “balance the books”.) Try to relate these concepts: the temperature of the sample increases, more electrons are released from covalent bonds and with higher kinetic energy, the tail of the Fermi distribution pushes farther into the 1-f(E) conduction band and the higher energy states become populated by these higher-kinetic-energy electrons. Meanwhile the tail pushes farther into the valence band (by symmetry), releasing electrons from deeper energy levels, and thus the “books balance” and the total energy of the system is conserved.


Tom Cunningham

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Pure (Intrinsic) Silicon - Useful Equations n = p = ni intrinsic carrier concentration: 3/ 2

ª 2π m *k º T N = 2 « » h2 ¬ ¼ ª 2π m *k º T N = 2 « » h2 ¬ ¼ n

− E G · § C V exp¨ ni = N N ¸ 2k BT © ¹

B

C

where

3/ 2

p

B

V

intrinsic Fermi level: EG = Energy band gap -5 -23 J/K k B = Boltzmann constant = 8.617x10 eV/K = 1.381x10 T = Temperature (K) k BT = thermal energy = 0.260 eV at 300 K h = Planck’s constant = 4. 136x10-15 eV.s = 6.626x10 -34 J.s mn* = Electron effective mass mp* =Hole effective mass m0 = Mass of the electron (free space) = 9.1095x10 -31 kg

mp * · § + k E ln¨ i = BT ¸ mn * ¹ 2 4 © E 3 G

At 300 K: material Si Ge GaAs

mn*/mo 1.18 0.55 0.066

mp*/mo 0.81 0.36 0.52

-3

ni (cm ) 1.18E10 2.33E13 2.25E6


Tom Cunningham

EG (eV) 1.12 0.66 1.42

Ei (eV)

0.5527 0.3218 0.7501 1 - 32

Performing the integrations on the previous slide yields expressions for n and p (not shown).

Given that np = ni2, these expressions can be combined to yield the expression above for the intrinsic carrier concentration. Note that ni increases with increasing temperature, as expected. Note also thatni is larger for a semiconductor material with a smaller band gap, as expected.

These expressions for n and p can also be used to derive the above expression for the intrinsic Fermi energy, E i.


Tom Cunningham

1 - 33

Intrinsic Carrier Concentration vs. Temperature



Tom Cunningham

1 - 34

Note the relationship between intrinsic carrier concentration, temperature, and band gap.


Tom Cunningham

1 - 35

Pure Silicon - Conduction I

Si

+

-

electrons holes

Si

Si

+

Si

V

+ Si

Si

Si

qV

EC

Si

Si

Si

+

Ei

-

EG

EV

Conduction in Intrinsic Si Bonding Diagram (T ~ 300 K) Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Conduction in Intrinsic Si Energy Band Diagram (T ~ 300 K) Tom Cunningham

1 - 36

Pure Silicon - Conduction, A Closer Look . . . I electron conduction (in conduction band)

Si

+

-

electrons holes Si

Si

Si

+ hole conduction (in valence band)

Si

Si

V

Si

EV

Si

Si

EV

Si

EV

e m it

electrons

EV

holes


Tom Cunningham

hole

1 - 38

In the valence band, electrons moving toward the positive terminal means that holes are moving toward the negative terminal (the direction a positive charge would move). Therefore, we can treat holes like independent, positively-charged particles inside the semiconductor. This key concept is reiterated here because it will be used throughout the rest of the course.

Note that, because the electrons are “rolling downhill” in response to the band bending (energy gradient), holes are moving “uphill”. Therefore, whereas electron energy increases going upward on a band diagram, it follows that hole energy increases in the downward direction on the band diagram. An easy way to remember this is that electrons like to “sink” and holes like to “float” on a band diagram. Given the opportunity, electrons will roll downhill, and holes will “roll uphill”.


Tom Cunningham

1 - 39

Pure Silicon - Conduction (con’t) conductivity (σ)

resistivity (ρ)

σ = qµnn + qµpp = qni(µn+µp)

(Ω.cm)−1

ρ =

q = elementary charge = 1.602x10 -19 coul. µn = electron mobility [= 1350 cm2/(V.s) for Si, room temp.] µp = hole mobility [= 480 cm2/(V.s) for Si, room temp.]

1

(Ω.cm)

σ

resistance (R)

= R

ρL A

A

L

(Ω)

Si

ρ

L = length of sample(cm) A = cross-sectional area of sample (cm2)

I

Ohm’s Law

V=IR V = applied voltage (volts) I = current (amps)

R

Si

) s p slope = 1/R m a (

electrons holes

A

I

-

+

V (volts)

V Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 40

Mobility & Velocity Saturation Si at 300 K

velocity saturation

slope = µ

ε

vd = µ



Tom Cunningham

1 - 42

As discussed previously, the carriers (electrons and holes) in the sample are in random thermal motion at equilibrium. When an electric field (voltage) is applied, the influence of this field is superimposed on this random thermal motion, causing the carriers to “drift” in the direction dictated by the field. Thus, there is a net movement of charge through the sample, i.e. a current referred to as drift current .

This plot shows the speed or , at which an electron or hole moves through the Si sample as a function of the applied drift velocity, vd electric field ε . Carrier velocity varies linearly with field strength for low and moderate applied fields, and the proportionality constant (slope) is the mobility, µ (often referred to as the low-field mobility in this context). As previously noted, the electron mobility is greater than the hole mobility, meaning that electrons move through the sample faster than holes in response to an applied electric field.

As the carriers travel inside the solid in response to the electric field, their forward-progress is retarded by collisions (scattering events) with vibrating Si atoms. At higher field strengths, these collisions become more frequent and more severe, thus reducing the mobility. On the graph, this is the region where the curve slopes-over and eventually saturates (at vd ≈ 1.7x107 cm/s). This is referred to as velocity saturation . In other words, increases in field strength contribute more to increased scattering than increased carrier velocity.

(In fact, if the electric field accelerates carriers to sufficiently high speeds they can cause impact ionization when colliding with Si atoms. These energetic carriers are called “hot” carriers. The impact ionization events give rise to an “avalanche” of hot carriers, which results in a large current. We will discuss this in more detail in the next module.)

Other factors, such as temperature, also affect the mobility. These effects will be discussed in more detail later in this module.


Tom Cunningham

1 - 43

Pure Silicon – Recombination & Generation (“R-G”) n = p = ni generation

dynamic equilibrium Si

Si

Si

EC generation

Si

Si

Si

E

Ei

EG recombination

EV

recombination

Si

Si

Si

Bonding Diagram


Energy Band Diagram

Tom Cunningham

1 - 44

Recombination is the reverse of thermal generation: an electron meets a hole and fills the vacancy. On the band diagram, an electron in the conduction band returns to the valence band.

Recombination and generation both take place continuously inside a semiconductor material, and at any given temperature a dynamic equilibrium is established between these two competing processes. Thus, n and p represent the carrier concentrations inside the semiconductor at any given “snap shot” in time.

Recombination and generation are collectively referred to by the abbreviation “R-G” (e.g. one might refer to “minority carrier RG” in a silicon sample).


Tom Cunningham

1 - 45

Properties of Common Semiconductors Some useful semiconductor properties

Matl.

Band gap EG (eV)

Intrinsic carrier conc. ni -3 (cm )

Electron effective mass mn*/m0

Hole effective mass mp*/m0

Electron mobility

µn

2

.

Hole mobility

µp

2

.

Resistivity

Permittivity

Melting Point

ρ

εr (=εs/ε0)

TM o ( C)

11.8

1415

16

936

13.2

1238

cm /(V s)

cm /(V s)

(Ω cm)

0.81

1350

480

2.5x105

.

Si

1.12

1.18x10

10

Ge

0.66

2.33x10

13

0.55

0.36

3900

1900

43

GaAs

1.42

2.25x10

6

0.066

0.52

8500

400

4x10

1.18

8

All values in table are for T = 300 K (room temperature). m0 = 9.11x10-31 kg (mass of electron in free space) ε0 = 8.85x10-14 F/cm (permittivity of free space) εS = permittivity of the semiconductor


Tom Cunningham

1 - 46

This table summarizes some physical properties of three important semiconductors: silicon (Si), germanium (Ge), and galliumarsenide (GaAs).

Although the foregoing discussion focuses on silicon, keep in mind that the concepts in this module are directly applicable to other semiconductor materials as well.


Tom Cunningham

1 - 47

Aside: Band Gap Variation with Temperature

source: S.M. Sze,Physics of Semiconductor Devices, John Wiley & Sons, 1981.


Tom Cunningham

1 - 48

The band gap decreases with increasing temperature, but the variation over the range of normal operating temperatures is very small and can usually be neglected.


Tom Cunningham

1 - 49

Metals, Insulators, & Semiconductors Semiconductor (e.g. Si)

Metal (e.g. Al) Al nucleus & core electrons

Insulator (e.g. SiO2)

free (delocalized ) electrons

silicon dioxide (SiO2)

Si Si

Si O

O

Aluminum (Al) (room temperature) Si

Si EC

(room temperature) conduction & valence bands overlap

- OR -

many electrons in conduction band, very conductive

Band Gap is too large for thermal generation to occur → no carriers, not conductive ( σ ∼ 0)

EC

EG = 9 eV

EG ~ 0.1 eV Ei EC EV

EG = 1.1eV

EV

Small or No Band Gap

EV

Moderate Band Gap


Tom Cunningham

Large Band Gap

1 - 50

In a metal, the band gap is very small (sometimes referred to as a “semi-metal”) or nonexistent (i.e. the conduction and valence bands overlap). Hence, metals have a very high concentration of free (“delocalized”) electrons, and are very conductive. Metal lines are used to carry electrical signals between transistors to form a circuit, as discussed later.

Insulators (dielectrics) have a very large band gap, and hence there is a negligible concentration of electrons in the conduction band and the material is non-conductive. Such materials are useful for electrically isolating certain regions or features in a semiconductor device or circuit, as discussed later.

Semiconductors have moderate band gaps, intermediate between conductors and insulators. Silicon can behave more like a conductor or more like an insulator depending on the circumstances, hence the name semiconductor - e.g. the temperature or the doping (discussed next) can vary the conductivity over orders of magnitude.


Tom Cunningham

1 - 51

N-Type Silicon - Example: Phosphorous I 1

3

II 2

H

4

Li

11

III

VI

VII

VIII 2

He


(abridged)

Be

12

Na

V

IV

B

13

Mg

Al

6

C

14

7

N

15

Si

8

O

16

P

S

9

F

17

He

10

Ne

18

Cl

Ar

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

K Ca Rb

Sc

Sr Y

Ti

V

Zr Nb

Cr Mn Mo

Tc

Fe Ru

Co Rh

Ni

nucleus (15 protons + 15 neutrons)

Pd

Cu Ag

Zn Cd

Ga In

Ge Sn

As Sb

Se Te

Br Kr I

Xe

15

P 30.97376

valence electrons (5) (outermost shell)

core electrons (10) (inner shells)

n=1 n=2 n=3

1s22s22p63s23p3


Tom Cunningham

1 - 52

Up to this point, we have been discussing the electronic properties of pure (intrinsic) silicon.

N-type or P-type. Note that doped silicon is also calledextrinsic Silicon can be doped with other substances to make it either silicon. We will discuss N-type silicon first.

N-type dopants reside in column 5 on the Periodic Table; common N-type dopants are phosphorous (P), arsenic (As), and antimony (Sb). We will use phosphorous for example.

Column-5 elements like phosphorous have 5 valence electrons.


Tom Cunningham

1 - 53

N-Type Silicon - Bonding Diagram (T = 0 K)

Si Si

Si

Si

Si

Si

P

Si

Si

Si

Si

Si

P

fifth valence electron

Silicon (4 valence electrons)

P

Phosphorous (5 valence electrons)

Bonding Diagram: Silicon Doped with Phosphorous (N-Type) (Absolute Zero)


Tom Cunningham

1 - 54

When the silicon is doped with phosphorous, the fifth valence electron of each phosphorous atom is not needed for covalent bonding. At absolute zero, this fifth valence electron is weakly held by the phosphorous atom; i.e. very little thermal energy will be required for this electron to break free and become a conduction electron.

For this reason, the phosphorous atoms are c alled donor atoms, because they will readily “donate” their fifth valence electrons to the material as conduction electrons.

(Recall that at absolute zero there is absolutely no thermal energy available to the sample.)


Tom Cunningham

1 - 55

N-Type Silicon - Energy Band Diagram (T = 0 K) “Extra” (5th) valence electrons of the phosphorous dopant atoms

n=p=0 ~ 0.1 eV

EC ED EF

E

Ei EG = 1.1 eV

EV

Energy Band Diagram: N-Type Si(Absolute Zero)


Tom Cunningham

1 - 56

On the corresponding band diagram, these fifth valence electrons occupy a new energy level, called the donor level (E D), just below the conduction band; i.e. very little energy will be required to promote these electrons to the conduction band.

The Fermi level (E ) has moved up toward the conduction band. The higher the concentration of phosphorousN (D), the more E F F moves up. Recall that the Fermi level is like a “water mark” for the electron energies in the sample.

(Aside: Previously, we discussed how energy bands and the band gap form via the splitting of energy levels when silicon atoms are brought together into covalent bonds. When phosphorous atoms are introduced into this bonding scheme, the splitting of energy levels is altered so as to form the donor level, and raise the Fermi level toward the conduction band.)


Tom Cunningham

1 - 57

Fermi Level vs. Dopant Concentration

N-type

P-type



Tom Cunningham

1 - 58

For N-Type silicon, the Fermi level moves toward the conduction band as the doping concentration N D is increased.

(The behavior of P-Type silicon, also shown on this diagram, will be discussed later.)


Tom Cunningham

1 - 59

N-Type Silicon - Very Low Temperature

EC Si

Si

P

} 0.1 eV

ED EF

P

Si

Si

Ei EG = 1.1 eV

Si

Si

P

EV

Energy Band Diagram: N-Type Si (Freeze Out, 0 < T < 77 K)


Energy Band Diagram: N-Type Si (Freeze Out, 0 < T < 77 K)

Tom Cunningham

1 - 60

At temperatures close to but above absolute zero, these fifth valence electrons begin to break free from their weak bonds to the phosphorous atoms. On the band diagram, they move from the donor level to the conduction band. Again, this is a statistical process; as the temperature increases, more of these electrons will be promoted to the conduction band.

This temperature range (0 to about 77 kelvin for this example) is called the Freeze Out range, because the temperature is so cold as to prevent all of these electrons from reaching the conduction band.


Tom Cunningham

1 - 61

N-Type Silicon - Low Temperature n>p n ≈ ND

Extrinsic Temperature Region

where N D is the concentration of phosphorous atoms (atoms/cm3)

EC Si

Si

P

} 0.1 eV

ED EF

P

Si

Si

Ei EG = 1.1 eV

thermal generation

Si

Si

thermal generation

P

EV

Energy Band Diagram: N-Type Si (Low Temperature)

Bonding Diagram: N-Type Si (Low Temperature) Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 62

Once the temperature rises out of the Freeze Out range, all of the fifth valence electrons have been released from their phosphorous host atoms and have joined the conduction band.

Some small amount of thermal generation also takes place, as previously discussed. (Recombination also takes place, though it is not explicitly shown on these diagrams. Recall that, at thermal equilibrium, the generation rate and the recombination rate are equal, giving rise to a dynamic equilibrium. Thus,n and p denote the carrier concentrations at any “snap shot” in time.)

However, the concentration of electrons in the conduction band, n, is dominated by the population of “donated” electrons; the contribution from thermal generation is negligible. Because each phosphorous atom donates one electron, we can write that n ≈ N D, where N is the concentration of phosphorous atoms in the sample. D

This is the onset of the extrinsic temperature range .

Note also that, for N-type silicon, the concentration of free electrons is greater than the concentration of holes, due to the presence of the “donated” electrons. It is no longer the case thatn = p as it was in pure silicon; for N-type silicon n > p, and hence electrons are called the majority carriers , holes are the minority carriers.

This is where the name N -type comes from: the majority carriers are electrons, which have a N egative charge. (Note however that the sample is macroscopically neutral; i.e. the “extra” electron donated by each phosphorous atom is balanced by a proton in its nucleus. The sample as a whole has no net electrical charge under normal, equilibrium conditions.)


Tom Cunningham

1 - 63

N-Type Silicon - Room Temperature n>p n ≈ ND


EC Si

Si

P

} 0.1 eV

ED EF

P

Si

Si

Ei EG = 1.1 eV

thermal generation

Si

Si

P

EV

Energy Band Diagram: N-Type Si (Room Temperature ≈ 300 K)

Bonding Diagram: N-Type Si (Room Temperature ≈ 300 K) Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 64

As the temperature rises, more thermal generation takes place, as expected. However, note that the approximation n ≈ N D is still valid at room temperature, as the “donated” electrons in the conduction band far outnumber the thermally generated electrons. This is a useful fact, since most semiconductor devices operate around room temperature, and the majority carrier concentration is simply equal to the dopant concentration (which is generally known from the fabrication process, or can be measured).


Tom Cunningham

1 - 65

N-Type Silicon - High Temperature n → ni n = p = ni

Intrinsic Temperature Region

donated electrons

many more electrons created thermally (n ≈ ni)

EC Si

P

ED

Si

Si

EF Ei

Si

P

Si

P

} 0.1 eV

EG = 1.1 eV

thermal generation

Si

EV holes approach their intrinsic concentration (p ≈ ni)

Bonding Diagram: N-Type Si (High Temperature, T > 450 K) Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Energy Band Diagram: N-Type Si (High Temperature, T > 450 K) Tom Cunningham

1 - 66

As the temperature increases, the concentration of thermally generated electrons becomes significant and eventually surpasses the n concentration of “donated” electrons (which is a fixed quantity, determined by the dopant concentration). In this case, approaches ni , the intrinsic carrier concentration. Hence, this is called theintrinsic temperature region . Also note thatE → E F i, consistent with the intrinsic behavior of the material and the fact that n = p = ni.


Tom Cunningham

1 - 67

Fermi Level vs. Temperature



Tom Cunningham

1 - 68

This graph summarizes what we have already seen – E → E F i as the temperature increases, consistent with the fact that n → ni 2 and p → ni (per np = ni ).

(This graph shows both N-type and P-type; P-type silicon will be discussed shortly.)


Tom Cunningham

1 - 69

Summary: Carrier Concentration vs. Temperature



Tom Cunningham

1 - 70

This graph summarizes the electron concentration as a function of temperature for N-type silicon.


Tom Cunningham

1 - 71

Revisiting the Relationship Between f(E), g(E), n & p

N-Type

Intrinsic (pure)

P-Type

source: Pierret & Neudeck (editors), Modular Series on Solid State Devices, vol. 1, Addison-Wesley Publishing, 1988. Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 72

This graph shows the relationship between the Fermi function, the density of states function, and the carrier concentrations for pure and doped silicon. We have already seen this for pure silicon, and will discuss P-type silicon later. For now, we will compare and contrast N-type silicon and pure silicon.

Looking at the graphs corresponding to N-type silicon, we see that the Fermi level is near the conduction band, as previously discussed. This is consistent with the fact that there is a greater concentration of electrons in the conduction band for N-type material. Recall that the Fermi level is like a “water mark” for the electron energies, and is the pivot point of the tail of the distribution (the length of the tail being determined by the temperature).

Also recall that as the dopant concentration (N D) increases, the Fermi level moves up toward the conduction band. Visualize this in the diagram above; this will increase the concentration of conduction electrons.

Other than the position of the Fermi energy level, the Fermi function itself does not change. Nor does the density of states function, as it is not dependent on doping.

Note that the electron concentration is much greater than the hole concentration (n > p), as expected.


Tom Cunningham

1 - 73

N-Type Silicon - Useful Equations Freeze-Out Temperature Region D N

+

n = N D =

− E E F D· § ¸ BT ¹ © k

ND+ = conc. of ionized donor atoms (cm-3) gD = spin degeneracy of donor level [= 2 (standard value)]

1 + gD exp¨

Extrinsic & Intrinsic Temperature Regions These equations hold for nondegenerately doped Si (EC - EF < 3k BT) in the extrinsic and intrinsic temperature regions

− E E F C § · ¸ BT ¹ © k

exp¨ C n = N

− E E F i· § ¸ BT ¹ © k

n = ni exp¨

n· § ¸ ni ¹ ©

ln¨ E F = E i + k BT

n p = ni2 extrinsic temperature region:

n ≈ N D

intrinsic temperature region:

n = p = ni


Tom Cunningham

1 - 74

These equations can be used to calculate the carrier concentrations in an N-type sample if the Fermi level is known, or, conversely, to calculate the Fermi level if the carrier concentrations are known.

The equations for the extrinsic and intrinsic temperature regions are valid for non-degenerately doped semiconductor materials only. For N-type material, this means that the Fermi level is below the conduction band edgeE (C ) and is not too close to it (specifically, E is at least 3k below E ). If the Fermi level is close to the conduction band, or inside the conduction band, the F BT C sample is said to be degenerately doped, and these equations are not valid.*

p) is known, the other can be calculated using np = ni2 . This relationship holds for pure Note that, if one carrier concentration (n or n = p = ni (hence np = ni2). This is obviously and doped semiconductor materials alike! For pure silicon (only!) it is the case that not the case for N-type material; we know that n > p. However, the productnp is still equal to ni2 . This fact represents a balance between thermal generation and recombination inside the material; when the electron concentration n is raised, the likelihood of a hole meeting an electron (recombination) increases, and hence the hole concentration p decreases proportionately. Sincep is reduced by the same factor that n is raised, the relationship np = ni2 is preserved. (This applies to any nondegenerately-doped semiconductor sample at equilibrium - i.e. no optical generation, etc.)

*

Note that heavily (degenerately) doped silicon is very conductive, similar to a metal. Also note that such high doping levels perturb the silicon crystal structure (due the presence of so many dopant atoms), and alter the band gap (usually making it narrower) and the internal conduction properties (e.g. the mobility, discussed later).


Tom Cunningham

1 - 75

N-Type Silicon - Conduction conductivity (σ)

resistivity (ρ)

σ = qµnn + qµpp ≈ qµnND

(Ω.cm)−1

ρ =


1

(Ω.cm)

σ

resistance (R)

R =

ρL A

I

(Ω)

electrons

Ohm’s Law

holes

A

-

V=IR V = applied voltage (volts) I = current (amps)


R

Si

L = length of sample (cm) A = cross-sectional area of sample (cm2)

+ V

Tom Cunningham

1 - 76

The conductivity and resistivity of an N-type sample can be calculated from the doping concentration. Note that the conductivity increases as the doping concentration increases, as expected.

Similar to our discussion of pure silicon, the resistance of the sample can be calculated from the resistivity and the physical dimensions. Ohm’s law can then be used to relate the current through the sample to the applied voltage. (At higher voltages, the sample will deviate from ohmic behavior due to velocity saturation, as previously discussed.)

Note that the current is dominated by electrons, the majority carriers.


Tom Cunningham

1 - 77

Resistivity vs. Dopant Concentration

source: Pierret & Neudeck (editors), Modular Series on Solid State Devices, vol. 1, Addison-Wesley Publishing, 1988. Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 78

The resistivity of N-type silicon decreases as the doping concentration increases, as expected. The same is true for P-type silicon, discussed later.

(On this graph, the reason for the difference between the two is the higher mobility of electrons vs. holes, thus making the N-type sample more conductive than a P-type sample with the same dopant concentration.)


Tom Cunningham

1 - 79

Aside: Mobility is not a constant

P+ low te mperature (low kinetic energy)



Tom Cunningham

P+ high temperature (high kinetic energy)

1 - 80

There are two scattering mechanisms which impede the motion of a carrier through the material, reducing the mobility. Lattice scattering (aka. phonon scattering) refers to the interaction of the carrier with vibrating Si atoms in the material. The amount of lattice scattering increases with increasing temperature (because the atomic vibration increases). Ionized impurity scattering refers to the interaction of the carrier with an ionized dopant (or other impurity) atom. The amount of impurity scattering increases with increasing dopant concentration.

is relatively constant wrt. doping concentration - ionized Mobility varies with doping concentration. For lighter doping, µ impurity scattering is negligible, lattice scattering is dominant. For higher doping, ionized impurity scattering can no longer be neglected, and µ declines with increasing doping concentration.

Mobility varies with temperature. For a lightly-doped semiconductor, ionized impurity scattering can be neglected. Lattice scattering dominates, and µ decreases with increasing temperature. For a heavily-doped semiconductor, ionized impurity scattering can not be neglected. However, the ionized impurity scattering component actually decreases as temperature increases, because the carriers have a higher kinetic energy and are less susceptible to the coulombic attraction of an ionized impurity. This is the reason for the small positive-slope region in the µ vs. T graph (which appears only for the heavier-doped cases, shown toward the bottom of the graph). This positive-slope region is small, however, because the lattice scattering component dominates as the temperature rises, resulting once again in a negative slope.


Tom Cunningham

1 - 81

P-Type Silicon - Example: Boron I 1

3

H Li

11

Na

III

II 2

4

IV

V

VI

VII

VIII 2

He


(abridged)

Be

12

B

13

Mg

Al

6

C

14

7

N

15

Si

8

O

16

P

S

9

F

17

He

10

Ne

18

Cl

Ar

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

K Ca Rb

Sc

Sr Y

Ti

V

Cr Mn

Zr Nb

Mo

Tc

Fe Ru

Co Rh

Ni Pd

Cu Ag

Zn Cd

Ga In

Ge Sn

As Sb

Se Te

Br Kr I

Xe

5

nucleus (5 protons + 5 neutrons)

core electrons (2) (inner shells)

B 10.811

n=1 valence electrons (3)

n=2

1s22s22p1 Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 82

We will now discuss P-type silicon. The discussion will be analogous to N-type silicon.

P-type dopants are found in column 3 of the Periodic Table, hence having 3 valence electrons. Common P-type dopants are boron (B) and indium (In); we will use boron for example.


Tom Cunningham

1 - 83

P-Type Silicon - Bonding Diagram (T = 0 K)

Si Si

Si

Silicon (4 valence electrons)

Si

Si

hole

Si

B

Si

Si

Si

Si

Si

B

B

Boron (3 valence electrons)

Bonding Diagram: Silicon Doped with Boron (P-Type) (Absolute Zero)


Tom Cunningham

1 - 84

Boron has only three valence electrons. When incorporated into silicon, one covalent bond will be vacant as shown. Thus, boron contributes holes to the material. Because a hole is a vacancy that will “accept” and electron, the boron dopant atoms are called acceptor atoms.


Tom Cunningham

1 - 85

P-Type Silicon - Energy Band Diagram (T = 0 K) n=p=0 EC

E

Ei EG = 1.1 eV EF EA EV

}~ 0.1 eV

Holes provided by Boron atoms

Energy Band Diagram: P-Type Si(Absolute Zero)


Tom Cunningham

1 - 86

On the band diagram, the holes from the boron atoms reside at the acceptor energy level, E A, just above the valence band.

Note that the Fermi level has moved down toward the valence band. The higher the dopant concentration, the closer it is to the valence band (see previous slide showing Fermi level vs. dopant concentration for N-Type and P-Type silicon).

Note also that, at absolute zero, there are no charge carriers available for conduction. There are no electrons in the conduction band, and no holes in the valence band. (If a voltage is applied across this material, there is no where for the electrons to move in the valence band - recall that they require holes to facilitate their movement.)


Tom Cunningham

1 - 87

P-Type Silicon - Very Low Temperature

EC

Ei EG = 1.1 eV

EF EA EV

Energy Band Diagram: P-Type Si (Freeze Out)


Tom Cunningham

1 - 88

As the temperature rises above absolute zero, some electrons in the conduction band gain enough thermal energy to rise to the E acceptor level, E A. Note that this is equivalent to a hole moving from A to the valence band. Again, this is a statistical process.

This is the Freeze Out temperature region.


Tom Cunningham

1 - 89

P-Type Silicon - Low Temperature p>n p ≈ NA


where N A is the concentration of boron atoms (atoms/cm3)

EC Si

B

Si

thermal generation

Ei B

Si

Si thermal generation

Si

Si

EF EA EV

B

Holes provided by Boron atoms

Energy Band Diagram: P-Type Si (Low Temperature)

Energy Band Diagram: P-Type Si (Low Temperature) Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 90

At some temperature, all of the holes will have moved from E A to the valence band. This makes the sample more conductive.

Recall that we will treat holes as independent, positive charge carriers.

Thermal generation will also begin to take place. However, the number of holes created by thermal generation is negligible compared to the number provided by the boron atoms, so p ≈ N A.

This is the extrinsic temperature region .

Holes are now the majority carriers, p > n. Electrons are the minority carriers. The material is called P-type because the majority carriers are Positive. (Again, note that the sample is macroscopically neutral.)


Tom Cunningham

1 - 91

P-Type Silicon - Room Temperature p>n p ≈ NA


EC Si

Si

B

B

Si

Si

Ei EF

Si

Si

B

EA EV

Energy Band Diagram: P-Type Si (Room Temperature)

Energy Band Diagram: P-Type Si (Room Temperature) Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 92

At room temperature, more thermal generation takes place.


Tom Cunningham

1 - 93

P-Type Silicon - High Temperature p → ni n = p = ni

Intrinsic Temperature Region

electrons approach their intrinsic concentration (n ≈ ni)

EC Si

Si

B

B

Si

Si

Si

Si

B

Ei EF

EA EV many more holes created thermally (p ≈ ni)

Energy Band Diagram: P-Type Si (High Temperature)

Energy Band Diagram: P-Type Si (High Temperature) Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 94

At very high temperatures, enough holes will be created by thermal generation to overshadow the (fixed) concentration of holes intrinsic from the boron atoms. Thus,n and p approach their intrinsic value, ni . E approaches its intrinsic value, E F i. This is the temperature region .


Tom Cunningham

1 - 95

P-Type Silicon - Useful Equations Freeze-Out Temperature Region A N

−

p = N A =

NA- = conc. of ionized acceptor atoms (cm-3) gA = spin degeneracy of acceptor level [= 4 (standard value)]

E A − E F § · 1 + gA exp¨ ¸ BT ¹ © k

Extrinsic & Intrinsic Temperature Regions These equations hold for nondegenerately doped Si (EF - EV < 3k BT) in the extrinsic and intrinsic temperature regions

− E E V F § · ¸ BT ¹ © k

p = N V exp¨

E i − E F § · ¸ BT ¹ © k

p = ni exp¨

p· § ¸ ni ¹ ©

E F = E i − k BT ln¨

n p = n i2 extrinsic temperature region:

p ≈ N A

intrinsic temperature region:

n = p = ni


Tom Cunningham

1 - 96

Equations for calculating carrier concentrations and Fermi level. Similar to those discussed previously for N-type silicon.


Tom Cunningham

1 - 97

P-Type Silicon - Conduction conductivity (σ)

σ = qµnn + qµpp ≈ qµpNA

resistivity (ρ) (Ω.cm)−1

ρ =


1

(Ω.cm)

σ

resistance (R)

= R

ρL A

I (Ω)

L = length of sample (cm) A = cross-sectional area of sample (cm2)

Ohm’s Law

R

Si electrons

holes

A

-

V=IR

+ V

V = applied voltage (volts) I = current (amps)

current is dominated by holes (majority carriers) Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3

Tom Cunningham

1 - 98

Note that the current is dominated by hole flow (the majority carriers).

This concludes our discussion of P-type silicon. Note that many of the earlier slides presented during the discussion of N-type silicon also contained related information about P-type silicon (in particular, some of the graphs). It is advised that you take a moment to review these slides and take note of this.


Tom Cunningham

1 - 99

Donor & Acceptor Energy Levels



Tom Cunningham

1 - 100

This chart shows donor and acceptor energy levels of various dopants (impurities) in Si, Ge, and GaAs.

The levels below midgap are acceptor levels unless otherwise indicated by a “D” and are measured wrt. the top of the valence band. The levels above midgap are donor levels unless otherwise indicated by an “A” and are measured wrt. the bottom of the conduction band.

These values were determined from measured ionization energies for these various impurities in Si, Ge, and GaAs.


Tom Cunningham

1 - 101

Mid-Gap States (Traps) 1 T

contaminant atom (trap)

2

EC

EC 1

2

ET

ET

trap site

Ei

trap site

Ei

EG = 1.1eV 1

EG = 1.1eV 2

EV

EV

indirect thermal generation


indirect recombination

Tom Cunningham

1 - 102

There are no states inside the band gap for truly pure silicon.

However, as shown on the previous slide, various contaminants can introduce allowed energy states inside the band gap. These impurity states (aka. traps) act as “stepping stones” for carriers to traverse the band gap, thus facilitating generation and recombination. For example, an electron in the valence band can gain enough energy to jump into a trap state inside the band gap, and then subsequently gain energy to jump to the conduction band (called indirect thermal generation). Similarly, an electron and hole might meet at an impurity (trap) site in the silicon and recombine there (called indirect recombination) as shown above. (The electron might be trapped first by the impurity atom and then the hole arrives later, or visa-versa.)

The most influential traps are those near mid-gap. They are the most effective recombination-generation (R-G) centers, because they place a “stepping stone” about half way between the valence and conduction bands. Noteworthy contaminants are sodium (Na), potassium (K), and iron (Fe), which are common impurities encountered during manufacturing. The cleanroom manufacturing environment goes to great lengths to minimize contaminants.

Key distinctions between contamination (traps) and doping (donor/acceptor levels): (1) doping is intentional and controlled; (2) doping produces donor and acceptor energy levels very close to the band edges, whereas contaminants tend to produce deeper energy states near mid-gap; (3) trap sites are distinct points (or perhaps small clusters) encountered at specific locations in the silicon sample, whereas dopant is spread throughout the sample in a more uniform fashion; (4) donors and acceptors contribute charge carriers to the sample, whereas traps introduce R-G centers.


Tom Cunningham

1 - 103

Aside: Silicon Crystal Structure

diamond unit cell (e.g. Si, Ge)

zincblende unit cell (e.g. GaAs)



Tom Cunningham

1 - 104

Exercise Suppose the sample shown here is doped with an Arsenic (As) concentration of 5x1016 cm-3. (1) Is this sample N-type or P-type, and how do you know this? (2) If 0.5 V is applied across the sample, how much current flows (assume it is ohmic)? (3) Is this current dominated by electrons or holes, and how do you know this?

1.0 cm

0.15 cm

Si

0.30 cm

Suppose the sample is doped with Indium (In) instead (same concentration). Repeat parts 1 – 3 above.


Tom Cunningham

1 - 106

Explain why the N-type sample conducts more current than the P-type sample.


Tom Cunningham

1 - 107

Solution Arsenic is an N-type dopant, because it is in column 5 on the Periodic Table and hence has five valence electrons. Majority carriers are electrons, hence current is dominated by electrons.

conductivity

2 § · −1 −3 −1 σ 16 cm = 10.8 Ω cm = qµ nN D = (1.602 E − 19coul.)¨1350 cm ¸ 5E ¨ ¸ © V ⋅ s ¹

resistivity

ρ =

resistance

Ohm’s law

(

1

1

= 0.092Ω ⋅ cm σ 10.8 ρ L (0.092Ω ⋅ cm)(1.0cm) R= = = 2.05Ω A (0.15cm)(0.30cm) = I

=

)

V 0.5V R

=

2.05Ω

= 0.243 A = 243mA

Indium is a P-type dopant, because it is in column 3 on the Periodic Table and hence has three valence electrons. Majority carriers are holes, hence current is dominated by holes. conductivity

2 § · −3 −1 −1 σ = qµ − 19coul.)¨ 480 cm ¸ 5E 16 cm = 3.84 Ω cm pN A = (1.602 E ¨ ¸ © V ⋅ s ¹

resistivity

= ρ

resistance

Ohm’s law

(

1

1

= 0.26Ω ⋅ cm σ 3.84 ρ L (0.26Ω ⋅ cm)(1.0cm) = = 5.78Ω R= A (0.15cm)(0.30cm) = I

=

)

V 0.5V R

=

5.78Ω


= 0.086 A = 86mA Tom Cunningham

1 - 108

The N-type sample has a lower resistance and hence conducts more current because electrons have a higher mobility than holes ( µ n > µ p).


Tom Cunningham

1 - 109

2 The

PN Junction

Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham

2-1

This is the second module in a five-module introduction to semiconductor device physics. The modules are: 1. Electronic Properties of Silicon 2. The PN Junction 3. The MOS Capacitor 4. The MOSFET 5. Small Circuits

Understanding the physics of the PN junction is an important step toward understanding the MOSFET transistor, because the source and drain regions of the MOSFET are PN junctions. The PN junction is also an important microelectronic device in its own right; we will see that it functions as a diode.

Objectives of this module: • Understand what the depletion region is and how it forms • Understand what the built-in voltage is and how it forms • Understand the band diagram for a PN junction at equilibrium • Understand the behavior of the PN junction under forward bias • Understand the behavior of the PN junction under reverse bias • Understand the ideal diode behavior, and compare it to a real diode • Understand reverse junction breakdown

Looking Back: We are prepared to understand the physics of the PN junction because we understand, from the previous module, the behavior of N-type and P-type silicon.

Looking Ahead: We will study the MOS capacitor in the next module, then combine this with our knowledge of the PN junction to understand how a transistor works.


2-2

PN Junction - Schematic Diagram N-Type Si

P-Type Si

P

N

PN Junction P+ P+ B- B-

N

P+ P+ B- BP+ P+ B- B-

P

P+ P+ B- B-

ε bi,Vbi ε εb i, Vbi

Built-in electric field, voltage

W

Width of Depletion Region

P+

Uncovered phosphorous ion

B-

Uncovered boron ion

W

Depletion Region


2-3

When N-type and P-type materials are put in contact, a PN junction is formed.

Diffusion drives majority carriers across the junction, in response to the concentration difference (gradient), exposing or “uncovering” dopant ions in the vicinity of the junction, as shown. However, an electric field builds up (due to the uncovered ions) in a direction opposing diffusion, and at some point these competing effects balance one another and an equilibrium is reached.

There is a depletion region near the junction, and a built-in electric field (voltage) in this region.

We will discuss all of this in more detail.


2-4

PN Junction - Energy Band Diagram EC

EC

EF E

EF EV

Isolated N-Type & P-Type Materials

EV

P

N

EC qVbi EF

E

EV

PN Junction

Fermi levels aligned at equilibrium

W Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham

2-5

We can construct an energy band diagram for the PN junction. We start with the energy band diagrams for N-type and P-type material, discussed previously.

The key to combining them is to understand that the Fermi levels must align at equilibrium. As long as the Fermi levels are not aligned, carriers will flow across the junction, because it is energetically favorable for them to do so.

Visualize putting the top two diagrams together, then sliding them vertically until the Fermi levels line up.


2-6

Diffusion Illustration Fish Tank Example

glass fish tank

remove partition

water-tight partition

Water

Blue Ink

Water Ink

Isolation water and ink not in contact

Introduction Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham

Contact

Equilibrium

diffusion begins

uniform concentration

2-7

diffusion. diffusion . Diffusion is a natural process that takes place when a concentration This is an example to illustrate the concept of difference (gradient) exists in a system. Diffusion refers to transport from areas of higher concentration to areas of lower concentration, until a uniform concentration is achieved throughout (at which point there is no longer a concentration gradient, and diffusion ceases).


2-8

PN Junction - Diffusion & Drift

N

P Isolation

N

P+ B-

+

h

P

hole diffusion electron diffusion P+ B-

P+ B-

N

*

Contact - Diffusion Begins

W P+ B-

e-

P

ε bi bi

Equilibrium: Drift = Diffusion


N

P+ BP+ B-

+

P

- electron drift hole drift

Drift & Diffusion Compete

2-9

PN Junction - Diffusion & Drift (cont.) EC

EC

EF

Contact EF EV

EV

Electron Diffusion

Recombination EC

EC

Drift & Diffusion Compete

EF

time

EF EV EV

W

Hole Diffusion

EC

qVbi EC

Equilibrium

EF

EF

Fermi levels aligned

EV EV

W Introduction Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham

2 - 11

This tells the same story, but from an energy band perspective.

Before we begin, it is important to reiterate that electron energy increases going upward on a band diagram, and hole energy increases going downward. As discussed in the previous module, electrons like to sink (roll downhill) and holes like to float (roll uphill).

Immediately after contact, contac t, electrons diffuse from N-side to P-side. Holes diffuse from P-side to N-side. They recombine in the depletion region, as shown.

The band diagrams slide vertically wrt. each other as drift and diffusion compete. The potential of the P-side is being raised wrt. the N-side, as the uncovered charge gives rise to a built-in voltage. The potential “hill” or “barrier” (built-in voltage) across the depletion region gets bigger as the bands slide, making it more difficult for carriers to diffuse across the junction. When the Fermi levels have aligned, it is no longer energetically favorable for carriers to move from one side to the other. The barrier is sufficiently high so as to impede further diffusion. d iffusion.* Drift and diffusion have balanced each other, and there is no net movement of carriers across the junction – equilibrium has been established.

Finally, it is important to note that equilibrium is established very rapidly after contact – it is instantaneous for all practical purposes.

dynamic * Aside -- Technical Technical Note: It is a equilibrium (as opposed to a static equilibrium) because there are carriers crossing the junction, but there is no movement of carriers. This tiny population of carriers arises from thermal generation of minority carriers inside the depletion region or in the quasinet neutral regions (described later), where they can drift across the junction due to V bi. It also arises from the fact that, statistically, some majority carriers in the far “tail” of the Fermi distribution will have enough energy to overcome the barrier and diffuse across the junction. The key point is that, at equilibrium, drift counterbalances diffusion. At any “snap shot” in time, thenet flow of electrons across the junction is zero, and the net flow of holes across the junction is zero.


2 - 12

The Depletion Region: A Closer Look Si

P

Si

Si

Si

B

B

Si

Si

Si

B

W P+ BP

Si

Si

N

thermal generation

Si

P+ B-

+

P

Si

P+ B-

P

ε -

Si

bi bi

thermal generation

Si

Si

P+

Si

Si

B-

P+

Si

Si

B-

Si

Si

Si

Si

P+

Si

Si

B-

fixed ions, depleted of electrons

thermal generation


fixed ions, depleted of holes

thermal generation

2 - 13

A closer look inside the PN junction.

neutral regions, away from the junction, have the bonding diagrams discussed earlier for The N-type and P-type bulk regions or doped silicon. Nothing new here.

However, in the depletion region on the N-side, note that there are uncovered, positively-charged phosphorous ions. The free electrons (i.e. the fifth valence electrons discussed earlier) diffused out of this region and into the P-side.

Similarly, in the depletion region on the P-side, note that there are negatively-charged boron ions. One way to understand this, treating holes as independent positively-charged particles, is to say that the holes diffused to the N-side leaving behind boron dopant ions with a net negative charge. An equivalent way of understanding this is to observe that the electrons that diffused into the P-side from the N-side now fill the holes in the boron-doped bonding diagram, as shown; i.e. recombination has taken place, as stated earlier. The presence of this electron gives the boron atom a net negative charge.


2 - 14

Summary - PN Junction at Equilibrium ε bi , Vbi P+ P+ B- B-

N

P+ P+ B- B-

Schematic Diagram

P

P+ P+ B- BP+ P+ B- BW

EC qVbi EF E


Energy Band Diagram

EV

2 - 15

The built-in voltage (V bi) is a “hill” or “energy barrier” on the band diagram, and exists only across the depletion region (as indicated by the sloped bands), because all of the charge is contained there. (Note that this is an idealization.)

The magnitude of the built-in voltage (i.e. the height of the hill) is equal to the difference between the two Fermi levels before contact. It follows that increasing the dopant concentration in one or both sides of the junction will result in a larger built-in voltage.

* Note: To be specific,equilibrium means: (1) no applied voltage; (2) no electric or magnetic fields present; (3) thermal equilibrium (no thermal gradients in the device); (4) no mechanical stress; (5) no external sources of excitation (e.g. no light or radiation).


2 - 16

Equilibrium - Energy, Voltage, Field, & Charge metallurgical junction

W

N

0

-xn

P xp

E

E or E C V (from band diagram)

Electron Energy

x V

V =−

V bi

Voltage

x

E q

ε Electric Field

0

x

ρ 0 Axp = N Dxn N


dx

abrupt junction

qN D

Charge Density

dV ε =−

2

+

-

x

V ρ ~ − d 2 dx

-qN A

2 - 17

PN Junction at Equilibrium - Useful Equations The following equations are valid for an abrupt (step) junction with uniform doping on both sides.

Built-in Voltage -3 EFN = Fermi energy level, n-type side (eV) n n = electron concentration, n-type side (cm ) -3) EFP = Fermi energy level, p-type side (eV) p = hole concentration, p-type side (cm p -3 q = elementary charge (1.602x10 -19 coul.) n i = intrinsic carrier concentration (cm ) -5 eV/K) N -3) k = Boltzmann constant (8.62x10 = dopant concentration, n-type (cm B D -3 T= temperature (K) NA = dopant concentration, p-type (cm ) k T = thermal energy = 0.260 eV at 300 K k B BT/q = thermal voltage = 0.260 V at 300K

ª º FN FP k BT nnpp E − E bi = ln « 2 » V = q q « » ¬ ni ¼

in the extrinsic temperature region, nn ≈ N D and pp ≈ N A

Depletion Region Width (equilibrium) xn =

xp =

sV bi 2ε

q

⋅

N A N D ( N A + N D)

2ε sV bi

q

⋅

= xn + xp = W

D N

2ε sV bi ( N A + N D)

qN AN D

εs = permittivity of semiconductor (1.036x10 -12 F/cm for Si)

A( N A + N D) N

Junction Capacitance (equilibrium)

C j0 =

ε sA

=

W

ε sA 2ε sV bi ( N A + N D)

A = area of junction

qN AN D Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham

2 - 19

PN Junction - Forward Bias I Forward Biased: P-side at positive potential wrt. N-side Depletion Region Narrows Energy Barrier Height Decreases by amount qV A Some carriers overcome barrier - traverse depletion region Diode is “ON” - diffusion current I (~mA)

T

N

T T

Forward Biased PN Junction

T

P +

T

VA q(Vbi-VA)

qVA EC Energy Band Diagram

EFN

qVA

E

EFP qVA EV

W W(eq.) Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham

Equilibrium (VA=0) Forward Biased

2 - 21

We will now discuss what happens when a voltage is applied across the PN junction. Since a voltage source has two terminals, positive and negative, it follows that there are two ways to bias the junction. They are calledforward bias and reverse bias. We will examine forward bias first.

When the N-side is held at a negative potential relative to the P-side, the PN junction is forward biased. The applied voltage V ( A) acts to reduce the height of the barrier or potential “hill”, as shown. Thus, some electrons can now overcome the barrier and diffuse from the N-side to the P-side. Similarly, holes can diffuse from the P-side to the N-side. Hence, a diffusion current is observed and the device is considered “on”.

We will take a more detailed look at forward bias shortly.


2 - 22

PN Junction - Reverse Bias I0 T

N

P

-

+ Reverse Biased PN Junction

T T T T

Reverse Biased: N-side at positive potential wrt. P-side Depletion Region Widens Energy Barrier Height Increases by amount qV A Carriers can not overcome barrier - no diffusion current Diode is “OFF” - BUT, there is a tiny leakage current I 0 (~pA)

VA

qVA EC q(Vbi+VA)

EFP qVA

EFN E

Energy Band Diagram

qVA EV

W(eq.)

Equilibrium (VA=0) Reverse Biased

W Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham

2 - 23

With the opposite polarity of applied voltage, the N-side is held at a higher potential than the P-side, and the PN junction is reverse biased. Notice that the applied voltage increases the potential hill on the band diagram, and the carriers can not diffuse across the junction. The device is “off”. (A small leakage current does exist through the device, which will be discussed shortly.)

The PN junction behaves like a diode*, an electronic device that conducts current in one direction (polarity) but not the other.

*

Note: Not all diodes are PN junctions. Other types of semiconductor diodes exist - e.g. Schottky diode, PIN diode, etc. The right diode for the job depends on the application – they all have the same fundamental behavior characteristic of a diode (e.g. the exponential forward I-V ) but differ in the details (e.g. maximum switching speed, etc.). These various diodes are not discussed in this course. However, this course does provide a basic background in device physics, so that you will be able to study and understand these devices (and many others), e.g. by consulting an introductory text on the subject.


2 - 24

Forward Bias, A Closer Look . . . Barrier = q(Vbi - VA) n(E) = ³f(E)*g c(E)dE

Electron Diffusion Current

qVA

EC

from supply

EFN

•

recombination

•E

qVA

recombination

FP

qVA EV

Hole Diffusion Current

W

Lp QuasiNeutral Region

Lp= hole minority carrier diffusion length Ln = electron minority carrier diffusion length

-

Ln +

VA


from supply

p(E) = ³[1-f(E)]*g v(E)dE

QuasiNeutral Region

Equilibrium (VA=0) Forward Biased 2 - 25

A more detailed look at forward bias.

If you understood how equilibrium is achieved in the PN junction, you will recognize forward bias as tipping the scales back in favor of diffusion (vs. drift). * The Fermi levels are separated “in the direction of diffusion” by an amount qV A and are held there by the applied bias . (When the applied bias is removed, the Fermi levels will quickly re-align, restoring equilibrium.) Electrons in the tail of the Fermi distribution with energy greater than the (lowered) barrier diffuse across the junction from N-side to P-side. Similarly, holes diffuse from P-side to N-side.

The electron minority carrier diffusion length (Ln) represents the mean free path of an electron injected into P-type material (i.e. wherein it is the minority carrier). It is how far the electron will travel, on average, before recombining with a hole. Typically, this is on the order of a few microns. Obviously, it 3 depends on the dopant concentration on the P-side ( N A) – for heavier doping there are more holes/cm , so injected electrons will travel a shorter distance on average before recombining. The hole minority carrier diffusion lengthL(p) is analogous.

The region within Ln of the depletion region edge on the P-side is called the quasi-neutral region ; it is where the recombination takes place. And similarly for holes injected into the N-side.

The power supply provides new carriers to replace those that recombine, thus sustaining the current. Hence, the forward-bias diffusion current is determined by the recombination rate in the quasi-neutral regions. (Note that some recombination also takes place inside the depletion region itself, but this is ignored for the “ideal” diode discussed here.) A higher recombination rate means more current.

Note that the depletion region narrows in forward bias – less uncovered charge is required to sustain the reduced voltage drop ( V bi – V A).

* The applied voltage is shown “connecting to” the Fermi levels on the diagram because it shifts the Fermi distributions relative to each other by an amount qV A (i.e. the electron potential on one side is lower than the other), and the easiest way to represent this is to treat the Fermi level like a “handle” which the applied voltage can grab and slide vertically, translating the entire Fermi distribution with it.


2 - 26

Reverse Bias, A Closer Look . . . Barrier = q(Vbi + VA) from supply electron drift current

qVA EC thermal generation

EFN

•

•E

FP

qVA

qVA EV

thermal generation

hole drift current

from supply

W

Lp QuasiNeutral Region

-

+ VA


Ln QuasiNeutral Region

Equilibrium (VA=0) Reverse Biased 2 - 27

A more detailed look at reverse bias.

The Fermi levels are separated and held apart by the applied voltage. The barrier height is increased, thus further inhibiting diffusion current across the junction. If you understood how equilibrium is achieved in the PN junction after contact, you will recognize reverse bias as tipping the scales in favor of drift (vs. diffusion).

Recall that electrons (minority carriers) are thermally generated throughout the P-side (assume the sample is at room temperature). Those electrons generated inside the quasi-neutral region on the P-side can diffuse to the edge of the depletion region, where they will be swept across by the electric field. Similarly, holes (minority carriers) thermally generated in the quasi-neutral region on the N-side can diffuse to the edge of the depletion region and be swept across. Thus, aminority carrier drift current exists in the device, referred to as reverse saturation current or leakage current . It is small, however, because the supply of minority carriers in the quasi-neutral regions is small (the current is supply-limited). The reverse current or leakage current is governed by thethermal generation rate. (Note that some generation also takes place inside the depletion region, but this is ignored for the “ideal” diode discussed here.)

Note that the depletion region widens in reverse bias – more charge is required for the larger electric field ( V bi + V A).

Aside: Note that I 0 is present in the device under forward bias as well, because thermal generation is always taking place. However, I 0 is negligible compared to the diffusion current.


2 - 28

Energy, Voltage, Field, & Charge Revisited Reverse Bias equilibrium applied bias

W

N

0

-xn

Forward Bias

P

N

W

P

-xn0 xp

xp

E

E

Electron Energy

x

x

V

V

V bi+V A

Voltage

x

ε Electric Field

0

ε x

0

x

ρ

ρ

qN D

Charge Density

0

N Axp = N Dxn

x

V bi - V A

qN D

+

-


x -qN A

+

0

N Axp = N Dxn

-

x -qN A 2 - 29

This graph shows the electron energy, voltage, electric field, and charge density for forward and reverse bias compared to + V equilibrium. In reverse bias, the energy barrier or “hill” is increased, the voltage drop across the junction in increased V ( bi A), the electric field in the depletion region is larger (in magnitude), and the depletion region expands to uncover more charge. Under forward bias, the energy barrier is reduced, the voltage drop across the depletion region is reduced ( V bi – V A), the electric field is smaller (in magnitude), and the depletion region shrinks. (Note that, per our earlier discussion, the idealized “block” charge approximations have been used here for illustration purposes.)


2 - 30

PN Junction - Useful Equations Revisited The following equations are valid for an abrupt (step) junction with uniform doping on both sides.

Depletion Region Width

xn =

xp =

2ε s (V bi − V A)

N A

q

N D ( N A + N D)

⋅


q

⋅

= xn + xp = W

s (V bi − V A)( N A + N D) 2ε AN D qN

N D

VA = applied voltage (equilibrium VA=0; fwd bias VA>0; rev bias V A<0)

A( N A + N D) N

Junction Capacitance ∆V → ∆Q A → ∆W j = C

sA ε

=

W

C j0 1

ª V º 1 + «¬ V »¼

2

where

C j0 =

sA ε

2ε sV bi ( N A + N D)

A

bi


∆W

N

∆W

W

P

qN AN D electrons move to cover/uncover P+ ions as needed

holes move to cover/uncover Bions as needed

2 - 31

PN Junction - Drift & Diffusion Currents

= J J p + J n

The total current through the junction is the sum of the electron current and hole current.

where:

n = J n ( drift n ( diff ) + J ) J p = J p ( drift p ( diff ) + J ) J

The electron current, in turn, is made up of drift and diffusion current components. So is the hole current.

where:

ε ε J ε pε = qµ (drift ) = σ n ( drift J nn ) = σ = qµ p

p

The drift current is calculated from Ohm’s Law. q = elementary charge (magnitude) = 1.602x10 -19 coul. µn = electron mobility [= 1350 cm2/(V.s) for Si, room temp.] µp = hole mobility [= 480 cm2/(V.s) for Si, room temp.]

and:

J ) = qDn n ( diff

dn

dx dp J p ( diff ) = −qDp dx Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham

The diffusion current is calculated from Fick’s law. DN = electron diffusion coefficient [= 33.75 cm 2/s for Si at 300 K] Dp = hole diffusion coefficient [=12.4 cm 2/s for Si at 300 K]

2 - 33

J is the current density, i.e. the current per unit area through the junction. J = I/A, where I is the current and A is the crosssectional area of the junction.

The total current through the junction is the sum of the electron current through the junction and the hole current through the junction.

The electron current, in turn, is made up of the electron drift current and the electron diffusion current. The hole current is made up of the hole drift current and the hole diffusion current. (Note that at equilibrium the drift and diffusion components are equal but opposite, maintaining a dynamic equilibrium and zero net current.)

The drift current can be calculated from Ohm’s Law. In the previous module, we used Ohm’s Law in the formV = I R. Here, we

ε,

use it in the equivalent form J = σ where σ is the conductivity (discussed in the previous module) and

ε is the electric field.

ρ, and ε (To convert this back to the form V = I R, simply make the substitutions R=ρ L/A, σ =1/ = V/L.)

The diffusion current can be calculated from Fick’s first law of diffusion, which states that the diffusion rate (particles per unit area per unit time) is directly proportional to the concentration gradient ( dn/dx or dp/dx). The proportionality constant,D, is called the diffusion constant . Multiplying byq (the elementary charge) puts it in terms of coulombs per unit area per unit time, or current density. (The negative sign in the hole diffusion equation results from the fact that the hole concentration gradient is in a direction opposite to the electron concentration gradient).


2 - 34

Ideal Diode - Current-Voltage Characteristic

I

Ideal Diode: I-V Characteristic

= I

ª º § A· qV « ¨ ¸ 1» 0 exp I « ¨¨ ¸¸ » B k T «¬ © ¹ »¼

−

0

Ideal Diode: Reverse saturation/leakage current

Dp º 2 ª Dn 0 = qA + I ni «¬ LnN » LpN A D¼

Reverse Bias

Forward Bias

(Off / Leakage)

(On)

Dn = electron diffusion coefficient [= 33.75 cm 2/s at 300 K] Dp = hole diffusion coefficient [=12.4 cm 2/s at 300 K] Ln = electron minority carrier diffusion length [~ 10 µm] Lp = hole minority carrier diffusion length [~10 µm]

Diffusion coefficient can be calculated from mobility

D

=

BT k

µ q


I

I 0

N

+

(Einstein relationship)

VA

I0

P

VA

N

diode circuit symbol

P

-

+ VA

2 - 35

Reverse Current - Analogy

I0

I0

I0 h

I0

waterfall

I0

I0

h

I0 I0 reverse-biased PN junction

I0

I0

q(Vbi + VA)


I0 I0

q(Vbi + VA)

2 - 37

An analogy to explain why the reverse-bias current is saturated, i.e. constant wrt. the applied voltage.

Consider a river with current I 0. Assume the river flows over a short waterfall: the current flowing down the waterfall and out of the base of the waterfall must also be I 0 (unless there is a large elephant drinking water at the bottom!). Now, assume that same river encounters a tall waterfall instead of the short one. Still, it is the case that the water flowing down the waterfall and out of the base of the waterfall is I 0 (water is not being added or removed anywhere along the path). Basically, the current is supply-limited, and the height of the waterfall has nothing to do with the amount of current. The height does influence the speed (kinetic energy) with which water hits the bottom. Sitting under the short waterfall on a hot day might be pleasant, sitting under the tall one might be painful - the water gains more kinetic energy, because it falls (accelerates) longer.

Similarly, increasing the reverse bias on a PN junction increases the height of the potential hill on the band diagram, but this does not change the current (i.e. the number of electrons flowing down the hill per unit time), only the amount of kinetic energy the electrons gain in crossing the junction. (If they gain too much kinetic energy, this can cause problems, as discussed later.) Like the waterfall example, the current in a reverse-biased PN junction is supply-limited, and is not influenced by the height of the hill.


2 - 38

PN Junction Diode - Non-Idealities Deviations from the ideal:

IR s

Generation / Recombination in Depletion Region

slope ≈ q/2k BT

ª § º ª § º qAniW A · A · « ¨ qV » « ¨ qV » ¸ ¸ I = I − + − 0 exp « ¨¨ « exp ¨¨ ¸¸ 1» ¸¸ 1» nk n 2 k BT BT 0 2τ ¹ ¼» ¹ ¼» ¬« © ¬« ©

slope = q/nk BT (n = 1 for ideal)

(f)

|

Ideality Factor

0

J / J |

where

~√VA

VBR

slope = q/n2k BT

τ 0 =

2

Forward bias (VA > 0): Exponential increase in recombination current. Reverse bias (VA < 0): Increase in generation current goes as W ~ √VA.

n = diode ideality factor [n = 1 for ideal diode, n > 1 for non-ideal] n2 = a slope factor for the second term [n 2 → 2 is typical] τn = electron minority carrier lifetime [~1µs typical] τp = hole minority carrier lifetime [~1µs typical] τ0 = effective (average) minority carrier lifetime

aside:

q|VA|/kBT

τ n + τ p

Ln ≡

Dnτ n

Lp ≡

Dpτ p

source: S.M. Sze,Physics of Semiconductor Devices, John Wiley & Sons, 1981, p. 91; and G.W. Pierret, Modular Series on Solid State Devices, vol. 2, Addison-Wesley Publishing, 1988, p. 83-85.


2 - 39

PN Junction Diode - Reverse Breakdown

Avalanche Breakdown Voltage

V BR =

εCR

εs

2q

2

N A + N D

Junction Breakdown

VBR

N AN D

I

0

VA

I0

ε = critical field for impact ionization [= 4x10V/cm for Si] CR

5

Reverse Bias

Forward Bias

Increasing the doping on either or both sides of the junction decreases the breakdown voltage.


2 - 41

junction breakdown voltage. Note that breakdown A large current arises when V A = V BR , called the reverse breakdown voltage or is not necessarily destructive to the diode.

There are two mechanisms for junction breakdown: 1. Avalanche Breakdown (impact ionization) - most common 2. Zener Breakdown (tunneling) - if both sides of junction are heavily doped


2 - 42

PN Junction Diode - Reverse Breakdown (cont.)

|VA| > |VBR| impact ionization events

both sides heavily doped

* *

|VA| > |VBR|

-

*

EC

*

direct band-to-band tunneling

EC

+

EV

Si

-

from supply

an impact ionization event

EC

+ EV

electron-hole pair creation

EV

electron-hole pair creation narrow bands

Si

Avalanche Breakdown


Zener Breakdown

2 - 43

Avalanche breakdown begins when the applied reverse-bias voltage is so large that the minority carriers traversing the depletion region gain sufficient kinetic energy to cause impact ionization. Impact ionization occurs when an energetic (aka. “hot”) carrier collides with a Si atom, breaking Si-Si covalent bonds and forming electron-hole pairs. These electrons and holes are then accelerated by the high electric field, and can go on to cause subsequent impact ionization events – i.e. an “avalanche” of energetic carriers, causing a large reverse current. Note that impact ionization is typically caused by electrons; holes have a lower mobility and are difficult to accelerate to impact ionization speed. Note also that the breakdown voltage decreases as the doping concentration on either or both sides of the junction increases. Increasing the doping concentration will increase the difference between the Fermi levels (E and E ), thus creating a larger built-in voltage (potential hill) when they are combined to form the FN FP junction. This larger built-in voltage means that less reverse-bias voltage is required to accelerate carriers to ionization speeds, hence a lower breakdown voltage is observed for the device.

Zener breakdown occurs in PN junctions which are heavily doped on both sides. The band “stretching” becomes so severe that direct band-to-band tunneling occurs. This results in a reverse “tunnel” current.


2 - 44

PN Junction Diode - One-Sided Junction ND >> NA

NA >> ND

W

W

P+ B-

N+

P+

P

B-

P+

+

N

P+ BP+

B-

ε bi

= W

B-

P+

-


qN A

2

ε

s CR ε BR = V A 2qN


+

B-

ε bi

= W

P+

-


qN D

2

ε

s CR ε BR = V D 2qN

2 - 45

A one-sided junction means that one side is doped heavily (degenerately) and the other is not. The “+” indicates the heavily-doped side (note: the “+” has nothing to do with electrical charge in this case, it only indicates which side is heavily doped). The PN junctions shown above are one-sided abrupt (step) junctions.

Aside: In module 4, we will see that the source and drain regions of the transistor (MOSFET) are one-sided PN junctions.

The equations for the depletion region width and breakdown voltage can be simplified, as shown. Note that they are more sensitive to the doping concentration on the lighter-doped side of the junction. The depletion region is contained mostly in the lighter-doped side (recall that N Axp = N Dxn for charge neutrality), therefore the voltage drop occurs mostly in this side, and this side np = ni2), dominates the electrical characteristics of the diode. This side will also have a higher minority carrier concentration (per and thus the larger leakage current component of I 0.


2 - 46

Breakdown Voltage vs. Dopant Concentration



2 - 47

This graph shows the avalanche breakdown voltage vs. dopant concentration for a one-sided abrupt PN junction ( N B denotes the dopant concentration on the lighter-doped side of the junction). The dashed line indicates the dopant concentration beyond which the Zener (tunneling) mechanism will dominate the voltage breakdown characteristic.


2 - 48

Aside: Linearly Graded Junction implant profiles

metallurgical junction (N A = N D)

W

N -xn

N A(x)

P

A( x ) = N

xp

xj

§ −

2

·

exp¨ x ¸ ¸ 4 Dt A π Dt ¨© ¹ Q

abrupt

N A(x)

graded

~ abrupt junction

NA - ND

~ linearly graded junction ND

slope = a

graded junction

0

x N A – N D = ax

+

≤ xp

0

xj

(abrupt)

(graded)

S

-

x V bi =

ε ε

j = C

x

bi

illustration of shallow (abrupt) vs. deep (graded) junction

x

xj

ª12ε −V (V )º = W « » qa ¬ ¼

ρ

= −qax for ρ -xn ≤ x = 0 otherwise ρ

Si surface

x N D

1 3

A

2k BT ª aW oº ln « q ¬ 2ni »¼

where W 0 is the equilibrium depletion region width (V A = 0)

S ε A

W

1

§ 2ε · − V = ε ¨¨ ¸¸ a 3 q © 2

4

BR

abrupt junction (for comparison) Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham

3 2

s

1 2

C

2 - 49

Aside: Non-Uniformly Doped Silicon n(x) = N D(x)

1

2

x lower doping concentration

− E E F i1 · § ¸ BT ¹ © k − E E F i2 · § n 2 = ni exp¨ ¸ BT ¹ © k n2 E i1 − E i2 · qΨ12 · § = exp§ ¨ ¸ = exp¨ ¸ n1 BT ¹ k BT © k © ¹ n1 = ni exp¨

N-type Si

higher doping concentration

EC EF Ei EV


2 - 51

Exercise: Back-to-Back PN Junctions E

N

B

P

C

N

In the space below, draw the band diagram for this structure at equilibrium.


2 - 53

Draw the band diagram for this N-P-N structure at equilibrium (assume that the sample is at room temperature, that each region is uniformly doped, and that both junctions are abrupt). Hint: Remember that the Fermi levels must be aligned at equilibrium. Don’t worry too much about the quantitative details, just try to get the qualitative picture right.

Label the depletion regions and built-in voltages on your diagram.


2 - 54

Exercise: Back-to-Back PN Junctions (cont.) B

E

P

N -

C

+ VEB

N -

+ VBC

Draw the band diagram for this structure (E-B junction forward biased and B-C junction reverse biased ).


2 - 55

Suppose the device is constructed such that the P-region is much narrower than Ln (the minority carrier diffusion length of electrons). If we forward bias the E-to-B junction and reverse bias the B-to-C junction (see diagram), what would happen? Specifically, would current flow through the device from E to C?

Have you ever seen this device before?


2 - 56

Exercise: Solution B

E

P

N

EC

C

••••••••••••••

qVbi

N

qVbi

••••••••••••••

EF

Equilibrium oooooooooooooooooo

EV W

EC

W

••••••••••••••

EF

••••••••••••••

Applied Voltages EV

ooooooooooooooo


2 - 57

When the E-B junction is forward biased, electrons flow from E to B. Since the B region is narrower thanLn, the electrons diffuse through the B region (most of them, anyway) and are swept into the C region by the reverse-biased B-C junction. Hence, electrons flow from E to C under these biasing conditions.

This device is called a Bipolar Junction Transistor, or BJT. Specifically, it is an NPN BJT. (A PNP BJT can also be constructed, and its behavior is analogous, though the voltage polarities are opposite and the current is dominated by holes.)

The region labeled E is called the Emitter – under forward bias it emits or injects carriers into the B region, which is called the Base. Most of the carriers diffuse across the base and are swept into the C region, called theCollector . A small fraction of them recombine in the base, giving rise to a small base current. In typical applications, the (small) base current is used to control the (larger) current flow through the device. Thus, the BJT behaves like an amplifier (i.e. the emitter-to-collector current is an amplification of the much smaller base current). In digital electronics applications, the analog nature of the emitter-to-base current is ignored, and the device is treated like a simple switch - i.e. on (conducting current) or off (not conducting).

Later, in module 4, we will study transistors, though our focus will be on a related but different style of transistor called the MOSFET. While the physics of the BJT and the MOSFET are quite different, understanding PN junctions (and this N-P-N band diagram) will help us understand the MOSFET.


2 - 58

3 The

MOS Capacitor

Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham

3-1

This is the third module in a five-module introduction to semiconductor devices. The modules are: 1. Electronic Properties of Silicon 2. The PN Junction 3. The MOS Capacitor 4. The MOSFET 5. Small Circuits Understanding the MOS capacitor is a key step toward understanding the MOSFET transistor, because the gate region of the MOSFET is a MOS capacitor. The MOS capacitor is also an important semiconductor device in its own right, with a variety of applications in microelectronic circuits. Objectives of this module: • Understand the band diagram for an ideal MOS capacitor • Understand accumulation, depletion, inversion, and strong inversion (threshold) • Understand the surface potential, and its relationship to the gate voltage and threshold voltage • Understand how gate oxide thickness and substrate doping affect the surface potential and threshold voltage • Understand how C-V testing is performed, and explain the shape of the C-V curve • Understand the band diagram for a real (non-ideal) MOS capacitor, including the work function mismatch, flatband voltage, and oxide charge effects • Understand all of the above for both a P-type MOS capacitor and an N-type MOS capacitor Looking Back: We are prepared to study the MOS capacitor because we understand the electronic properties of N-type and P-type silicon from the first module. Looking Ahead: We will combine our knowledge of the MOS capacitor with our prior study of the PN junction to understand how a transistor (MOSFET) works. Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham

3-2

MOS Capacitor (Ideal) - Equilibrium

M etal (aka. the Gate) Oxide (aka. the Gate Oxide) Semiconductor

P-type

Three possible biasing regimes: • Accumulation • Depletion • Inversion


3-3

“MOS” is short for Metal-Oxide-Semiconductor. A capacitor is a circuit element which stores charge. The MOS capacitor is formed using a metal such as aluminum for the “top plate” or gate, silicon dioxide (SiO2) as the dielectric or gate oxide, and a semiconductor material such as silicon (N-type or P-type) as the “bottom plate” or substrate . We will use P-type silicon for illustration, then summarize for the N-type case by analogy at the end of the discussion. There are three possible biasing conditions for a MOS capacitor; they are called study each in detail.


accumulation , depletion, and inversion. We will

3-4

MOS Capacitor - Accumulation

- - - - - - -

M O S o o o o o o o

+

VG

P-type

Holes accumulate underneath the oxide to balance the charge on the metal/gate - surface “looks” more P-type

ps > N A ps = hole concentration at semiconductor surface (cm-3)


3-5

The MOS capacitor is biased into accumulation when the gate is held at a negative potential relative to the substrate. Recall that P-type material has an abundance of holes (the majority carrier). The negative bias on the gate causes holes to accumulate underneath the gate oxide at the surface of the semiconductor. However, the holes can not travel through the oxide to the negative terminal, because it is an insulator (dielectric) and hence is not conductive. The hol es remain accumulated underneath the oxide. The more voltage applied, the greater the accumulation. The surface of the semiconductor “looks” more P-type than the bulk, i.e. ps > N A, where ps is the concentration of holes at the surface and N is the dopant concentration in the P-type semiconductor. A


3-6

MOS Capacitor - Depletion

VG < VT Depletion

+ + + + + + +

M O S B- B- B- B- B- B- B-

+

-

VG

Depletion W Region

P-type

QG = -QD

Uncovered charge in the depletion region (QD) balances charge on gate (QG)

Charge in the depletion region QD = qAN AW (A = gate area)

As V increases → QD increases → G increases → QG increases → W


Q G = QD

3-7

When the gate is held at a positive potential relative to the substrate, the MOS capacitor is biased into depletion (provided that the applied voltage is not greater than some threshold voltage , V , described later). Holes are repelled from the semiconductor surface T by the positive charge on the gate, and thus the surface is depleted of majority carriers, leaving only the uncovered boron dopant atoms. The charge in this depletion region balances the gate charge. As the applied voltage is increased, the depletion region widens, uncovering more charge to maintain this balance. The applied voltage drops across the gate oxide and the depletion region.


3-8

MOS Capacitor - Inversion VG → VT Inversion

M O S

+

-

VG

+++++++ ++++++++++++++

Electrons (minority carriers) pile up underneath the oxide → surface “looks” Ntype → surface inversion

• • • • • • • B- B- B- B- B- B- BB- B- B- B- B- B- B-

W (wider)

QG = - (QD + Qn)

P-type

VG = VT Strong Inversion (Threshold)

M O S

+

-

VG

++++++++++++++ ++++++++++++++

••••••••••••••

B- B- B- B- B- B- BB- B- B- B- B- B- BP-type


Surface looks as N-type as bulk is P-type → strong inversion → threshold voltage

W = WT (maximum) Depletion region reaches its maximum width (W ) at threshold T

3-9

As the applied voltage is increased further, electrons (minority carriers) begin to pile up underneath the gate oxide, forming an inversion layer . The semiconductor surface is now starting to “look” N-type, hence the term “inversion”. Now, the charge o n the gate is balanced by the charge in the depletion region and the charge in the inversion layer. When the threshold voltage (V ) is reached, the surface is “as N-type as the bulk is P-type”; i.e. the concentration of electrons in T the inversion layer ( ns) is equal to the concentration of holes in the bulk substrate (N A). This will be a very important concept when we discuss the transistor (MOSFET).


3 - 10

MOS Capacitor - Inversion (cont.)

+++++++++++++++++++ +++++++++++++++++++

VG > VT Beyond Threshold

M O S

+

-

VG

•••••••••••••••••••••••• B- B- B- B- B- B- BB- B- B- B- B- B- B-

W = WT (maximum)

P-type


3 - 11

As the applied gate voltage increases beyond threshold, the surface becomes more strongly inverted ( ns increases). Note that beyond threshold further increases in gate charge are compensated by increasing charge in the inversion layer; the depletion region has reached its maximum width ( W = W ) at threshold. T


3 - 12

MOS Capacitor (Ideal) - Band Diagram, Isolated Materials Ideal MOS Capacitor: φM = φS

M

O

S

EVAC EC

qφM

qφS EC EG(Si) = 1.1eV

EG(SiO2) ≈ 9 eV

Ei EFS

EFM

EV

delocalized electrons P-Type

EVAC = vacuum level (free electron) φM = metal work function φS = semiconductor work function Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham

EV 3 - 13

ideal MOS capacitor. We can construct an energy band diagram for the MOS capacitor. We will first consider an

φ We begin by considering the band diagrams of the isolated components, before they are brought into contact. A work function is defined for both the metal and the semiconductor; it is a measure of the amount of energy required to remove an electron from the material entirely (i.e. to the vacuum level, E ), and is measured from the Fermi level as shown. For an ideal MOS capacitor, we VAC φ = assume that φ (note that this is equivalent to assuming that the Fermi levels line up). M S

photoelectric effect Aside: If you are familiar with the , you might have seen the work function φ before. Albert Einstein received the Nobel Prize in Physics for his theoretical explanation of the photoelectric effect in the early 1900’s. The photoelectric effect occurs when ultraviolet light is shined onto a metal surface, causing electrons to be “knocked out” o f the metal surface by the ν incident photons. If the incident light is of frequency , then the photon energy is E = hν (where h is Planck’s constant), and the φ kinetic energy of the electrons emitted from the metal is E = hν - φ , where φ is the work function of the metal. In other words, is the minimum amount of energy required to pull an electron out of the metal, and any additional energy supplied by the photon is turned into the kinetic energy of the electron (in accordance with the conservation of energy).


3 - 14

MOS Capacitor (Ideal) - Band Diagram, Equilibrium M O S

Ideal MOS Capacitor: φM = φS P-type

M

O

S

EVAC

qφM

qφS EC EG(SiO2)

EFM

EG(Si)

Ei EFS

EV


3 - 15

The materials are brought into contact to form the MOS capacitor. The Fermi levels align at equilibrium (analogous to the PN junction discussion). Because we assume that the work functions are equal for the ideal case, there is no band bending (all energy bands are flat) at equilibrium.


3 - 16

MOS Capacitor (Ideal) - Band Diagram, Accumulation - - - - - - M O S o o o o o o o

+

ε, VG

+Qp

VG

-QG

qVOX

P-type

M O S

EC

-

EG(Si)

Ei

EFM

+

EFS

EV

M

O

S Holes (majority carriers) accumulate underneath the oxide to compensate the gate charge → surface “looks” more P-type (ps > NA)


3 - 17

When the MOS capacitor is biased into accumulation, band bending occurs as shown (the potential energy of electrons in the semiconductor is lowered wrt. the metal). Recall that hole energy increases downward on a band d iagram (“holes like to float”). Therefore, they follow the energy gradient and accumulate at the semiconductor surface, as previously discussed. Recall that a voltage drop exists where bands are bent, i.e. across the oxide and the semiconductor surface. No volt age drop exists where bands are flat. The charge is represented in the upper right diagram. The negative charge on the gate is compensated by the equal but opposite charge in the accumulation layer.


3 - 18

MOS Capacitor (Ideal) - Band Diagram, Depletion + + + + + + + M O S B- B- B- B- B- B- BW

+

-

0 < VG < VT +Q G

VG

W

ε , VG

P-type

-Q D

qVOX

M O S

VG = VOX + ΨS = voltage drop across oxide V OX Ψ = surface potential (voltage drop across W) S

EC EG(Si)

+

qΨS

qφB

qΨS

EFM

M Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham

O

Ei

-

EFS

EV

W Depletion Region

S 3 - 19

In depletion, the bands bend as shown (the potential energy of electrons in the semiconductor are raised wrt. the metal). Note that the electric field (voltage) drops across the oxide and the depletion region (where the bands are sloped). V is the OX voltage drop across the oxide. Ψ S is the surface potential , and represents the voltage drop across the depletion region of the V V semiconductor. Therefore, = + Ψ G OX S. The quantity φ B on the band diagram is the bulk potential (sometimes called the Fermi potential ), the difference between the Fermi level and the intrinsic Fermi level in the bulk of the semiconductor (i.e. far away from the surface, in the neutral region). The charge diagram shows that the positive charge on the gate is balanced by the equal but opposite charge in the depletion region.


3 - 20

MOS Capacitor (Ideal) - Band Diagram, Inversion M O S

+ VG

-

+++++++ +++++++++ +++++

VG → VT

ΨS → 2φB

+QG

• • • • • • • B- B- B- B- B- B- BB- B- B- B- B- B- B-

W

W→WT

, VG ε

(wider)

P-type

-QD -Qn

qVOX

VG = VOX + ΨS

M O S

EC

+

Ei dips below EF → surface “looks” N -type → onset of surface inversion B) º B) º ª q(ΨS − φ ª q(ΨS − 2φ = N A exp » « »¼ BT ¼ BT k ¬ k ¬

ns = ni exp«

qφB

qΨS

Ei EFS

-

EV EFM W (wider)


O

S 3 - 21

As V , electrons (minority carriers) begin to pile up at the silicon surface underneath the oxide, following th e G gets closer to V T gradient of the band diagram. These electrons come from thermal generation inside the depletion region. Ψ The equation above relates the surface electron concentration ns to Ψ = E S and φ B. Note that for S = φ B, ns = ni (and hence E F i at Ψ the surface) as expected. This point where the surface looks intrinsic is the demarcation between depletion and inversion. As S increases beyond this “intrinsic” point, E near the surface, indicating that the surface now looks N-type. This is i dips below E F called surface inversion.

The charge diagram shows that the charge on the gate is now compensated by the depletion charge and the the inversion charge. An incremental increase in gate charge causes both to increase somewhat to compensate. * Note also that ns is not actually zero in depletion, but it is negligibly small -ns is much less than N A for Ψ S << 2φ B (negative exponent).


3 - 22

MOS Capacitor (Ideal) - Band Diagram, Strong Inversion (Threshold) M O S

+

-

VG

+++++++++++ +++ +++++++++++ +++

••••••••••••••

VG = VT

B- B- B- B- B- B- B-

W = WT

B- B- B- B- B- B- B-

(maximum)

ΨS = 2φB

+QG WT

ε , VG

P-type

-QD -Qn

qVOX

M O S

VG = VOX + ΨS

EC ΨS = 2φB → surface is as N-type as the bulk is P-type (ns = NA) → “strong” inversion → threshold voltage

+

B) º B) º ª q( ΨS − φ ª q(ΨS − 2φ A exp ns = ni exp« » = N « » B B k T k T ¬ ¼ ¬ ¼

qφB

qΨS

Ei EFS

EV

-

EFM W = WT (maximum )


O

S 3 - 23

At threshold, E at the surface as it does above E in the bulk. In other words, the surface is as N-type as the i lies as far below E F F *. B. This is one common definition of the threshold voltage bulk is P-type (ns = N A), and Ψ S = 2φ

“Strong” inversion is sometimes defined as Ψ S = 2φ B + 6k BT/q (and hence Ψ S = 2φ B is “moderate” inversion). (For a sense of scale, φ is about 0.4V for normal doping levels and = 0.16V at room temperature.) This places well into 6k T/q V B B T the exponential turn-on for Ψ S > 2φ B (positive exponent), where ns is significantly larger than N A and hence a “strong” channel is present. The definition of the “strong” inversion or “threshold” point is somewhat arbitrary, because it is the assignment of a discrete “turn-on” point to what is fundamentally an analog turn-on characteristic. For our purposes here, we will continue the discussion in terms of the most basic and straightforward definition of threshold voltage, Ψ S = 2φ B, but we will mention the alternate definition from time to time as well. *Technical Note:


3 - 24

MOS Capacitor (Ideal) - Band Diagram, Beyond Threshold VG > VT

++++++++++++ +++++++ +++++++++++++++++++

M O S

+

-

VG

•••••••••••••••••••••••• B- B- B- B- B- B- BB- B- B- B- B- B- B-

ΨS > 2φB +QG

ε , VG

W = WT

WT

(maximum)

-QD

P-type

-Qn M O S

qVOX

VG = VOX + ΨS

+

EC

More electrons pile up at semiconductor surface (n s > NA)

qφB qΨS

Ei EFS

EV

B) º B) º ª q(ΨS − φ ª q (ΨS − 2φ A exp » = N « » k T k T B B ¬ ¼ ¬ ¼

ns = ni exp«

-

EFM W = WT (maximum )


O

S 3 - 25

At threshold, the depletion region has reached its maximum width. Further increases in gate voltage are compensated by an increase in the electron concentration in the inversion layer as depicted in the charge diagram; any increase in W is negligibly small. Additional gate charge beyond threshold is compensated by an increase in inversion layer charge, rather than d epletion region expansion, because ns increases exponentially with Ψ S for Ψ S > 2φ B (positive exponent), whereas the depletion region expands as (see equation, next slide). Once a good channel forms, it effectively “shields” the depletion region below (i.e. the electric √Ψ S field lines emanating from the gate charge terminate on the channel charge and are not “felt” at the far edge of the depletion region). Hence, the inversion charge dominates the sub-gate dc electrostatics beyond threshold.

Summary: P-Type MOS Capacitor biased into:

Applied voltage

Surface Potential

Surface carrier concentration

Additional gate charge compensated by:

Accumulation

VG < 0

ΨS < 0

ps > NA

accumulation of holes (majority carriers) at surface

Depletion

0 < VG < VT

0 < ΨS < φB

ps < NA ns < ni

additional depletion charge (expansion of depletion region)

Inversion

0 < VG < VT

φB ≤ ΨS < 2φB

ni ≤ ns < NA

additional depletion charge and additional inversion layer charge

Strong Inversion

0 < VT ≤ VG

ΨS ≥ 2φB

ns ≥ NA

additional inversion layer charge


3 - 26

MOS Capacitor - Useful Equations MOS capacitor voltage drops (ideal):

V + Ψ G = V OX S These equations assume the MOS capacitor is in the extrinsic temperature region (e.g. around room temperature).

Depletion region width: W =

2ε S

ΨS

W =

P-type

qN A

2ε S

Ψ

qN D

N-type

S

Bulk potential: φ B =

φ B =

E i (bulk F k BT § N A· ) − E

=

q

E ) − E i (bulk F

=−

q

P-type

ln¨

¸ ni ¹ ©

q

k N BT § D· q

ln¨

N-type

¸

ni ¹ ©

Definition of strong inversion (threshold):

(alternate definition: Ψ S = 2φ B + 6k BT/q)

Ψ S = 2φ B

Maximum depletion region width (occurs at threshold): W T =

2ε S (2φ ) P-type

qN A

B

Introduction Introduction to Semiconductor Semiconductor Device Physics / MOS Capacitor Capacitor / rev 4.3 Tom Cunningham Cunningham

W T =

2ε S (2φ ) N-type

qN D

B

3 - 27

Useful equations for the MOS capacitor.


3 - 28

A Closer Look at the Surface Potential (Ideal)

= γ

where:

exp ª«

k BT

V G = Ψ S − γ Ψ S +

¬

q

2ε qN C ' s

A

q ( ΨS − 2φ B) º

»¼ k BT γ is called the body γ

P-Type

factor - contains all the physical attributes and constants

OX

also note:

= γ

2ε qN for N-Type C ' s

D

C ' OX =

OX

OX ε (gate capacitance per unit area) OX t

ΨS 2φB + 6kBT/q 2φB G ≈ Ψ S − γ Ψ S V

φB

V T

(our definition)

0

depletion

inversion (weak)


V T

(alternate def.)

inversion (moderate/strong)

inversion (strong)

V G 3 - 29

It is desirable to minimize V OX and maximize Ψ S , meaning that the gate voltage has maximum influence over the semiconductor surface. The importance of this will become more obvious when we discuss the MOSFET transistor in the next module. Since surface potential can not be measured m easured directly, it is useful to have h ave an expression relating Ψ S to the applied gate voltage V Operation and Modeling of the MOS G. This is given above (for a detailed derivation, the reader is referred to Chapter 2 of Ψ McGraw-Hill, 1987). The expression is plotted as vs. (although the equation can not be solved Transistor, Y.P. Tsividis, McGraw-Hill, V S G explicitly for Ψ inS are required to accommodate the S ). For weak inversion, the steeper slope indicates that large changes Ψ Ψ gate charge from small changes in V . In strong inversion, however, onl only y slight changes in G S are required, because of the strong exponential response of the inversion charge to Ψ as discussed previously. (This graph also makes it clear why some S authors prefer that threshold be defined as Ψ h as saturated somewhat.) S = 2φ B + 6k BT/q, where the surface potential has Aside -- Looking Ahead: The The weak-inversion slope is very important because it influences MOSFET parametrics. Optimal MOSFET performance is achieved by maximizing this slope, which corresponds to minimizing the body factor γ . As γ → 0, V d ropped across the oxide (V = 0). This gives the gate voltage maximum control over G → Ψ S, as if none of the gate voltage dropped OX the semiconductor surface, resulting in a sharper on-off o n-off transition for the transistor and a lower threshold voltage, which γ translates into a higher drive current and hence faster circuits. Minimizingγ in turn means minimizing the gate oxide thickness γ t N and the substrate doping (this can be seen from the equation for above, and is discussed further in the next slides). ox A * Note on nomenclature: C is used to represent the oxide ox ide capacitance, ε (in Farads). C’OX is used to denote oxide A/t OX OX OX 2 µm ). This module and the next capacitance per unit area , ε /t (e.g. Farads/ n ext one will use these two quantities often. OX OX


3 - 30

MOS Capacitor - Surface Potential & Gate Ox Thickness VG = VOX + ΨS

Thinner Oxide

Thicker Oxide

MOS

M O S

+VG

+VG

ΨS

ΨS

0

W

y


0 W

y

3 - 31

For a thinner gate oxide, there is less voltage drop across the oxide (lower V ) and hence more voltage drop across the depletion OX region in the semiconductor surface (higher ψ s). Therefore, the gate voltage has more control over the semiconductor surface, and strong inversion (threshold) will be achieved at a lower applied gate voltage; i.e. the threshold vo ltage V will be lower. As T previously mentioned, a lower threshold voltage is advantageous for a transistor (MOSFET), as it typically means that the transistor will produce a higher drive current, which in turn allows for faster transistor circuits.


3 - 32

MOS Capacitor - Surface Potential & Doping Lighter Doping

Heavier Doping

MOS

MOS

VG = VOX + ΨS +VG

QG = -QD

+VG

QD = qAN AW

ΨS

ΨS

0

W

y


0 W

y

3 - 33

Lighter doping necessitates a wider depletion region (to uncover enough fixed ions to balance the gate charge). The depletion region can be thought of as an insulator (i.e. very few mobile charge carriers, very high resistance). V G must drop across the Ψ oxide (V ) and the depletion region ( ). The wider the depletion region, the larger the voltage drop in the semiconductor, i.e. OX S larger Ψ . S


3 - 34

MOS Capacitor (Ideal) - Threshold Voltage Calculation Threshold Voltage P-Type MOS Capacitor

B = where φ

2ε qN 2φ V = 2 φ + C ' S

T

A

B

BT § k p·

ln¨ ¸ n¹ ©

q

i

p ≈ NA for extrinsic temperature region (e.g. room temp.)

B

OX

' OX = C

ε OX OX t

(gate capacitance per unit area)

N-Type MOS Capacitor

2ε qN 2φ V = 2 φ − C ' S

T

D

where

B = φ

BT § k n·

B

B

OX

n¹ © i

n ≈ ND for extrinsic temperature region (e.g. room temp.)

C ' OX =


q

ln¨ ¸

ε OX OX t


3 - 35

Threshold voltage expressions. Note that the threshold voltage is smaller (in magnitude) for thinner gate oxide and/or light er silicon doping, as previously discussed. φ Temperature Dependence of V : The temperature dependence of V comes from φ T T B. As the temperature increases, B decreases due to the fact that p → ni. Recall that the P-type substrate/well will approach intrinsic behavior at higher temperatures, i.e.p → ni → E → 0. Thus, threshold voltage (as discussed in module 1), so φ decreases with increasing temperature. B → 0 (i.e. E F i), so V T


3 - 36

MOS Capacitor (Ideal) - AC Behavior & The C-V Curve A

The C-V Test:

~

M O S

C =

dQ dV

VG

P-type

V G

slow dc ramp

V G

low-frequency ac signal

slow dc ramp high- frequency ac signal

time

0 Low-Frequency Test Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham

time

0 High-Frequency Test 3 - 37

is a measure of how effectively a capacitor handles charge. In dc terms, it is the propo rtionality constant between the voltage applied across the capacitor and the amount of charge stored, Q = C V (i.e. a device with a higher capacitance stores more charge for a given applied voltage). For ac voltage signals, it is better thought of as a measure of how the charge on the capacitor changes in response to changes in the applied voltage, C = dQ/dV (a device with a high capacitance exhibits a large change in Q for a small change in V , and thus is very responsive to changes in the applied voltage). Capacitance

The capacitance-voltage characteristic of the capacitor is measured using the C-V test described here. A small-amplitude ac signal is superimposed on a slow dc ramp of the gate voltage. The transient currents in the circuit are measured, and used to calculate the charge (i = dQ/dt ), which is then used to calculate the capacitance as a function of the applied voltage V G. We will consider two cases, a low-frequency ac signal vs. a high-frequency signal. We will see that the frequency of the si gnal does not affect the C-V of the device in accumulation or depletion, but has a pronounced effect on its inversion behavior.

Aside – Technical Note: The slow dc ramp makes this a “quasi-static” test, allowing the device to maintain thermal equilibrium as it is being tested. The idea here is to increment the dc gate voltage a small amount, then use the ac signal and measure the transient currents to calculate the capacitance, then increment again to the next dc gate voltage point. Repeating this over the dc voltage range of interest, with slow and gradual increases in the dc voltage, generates the “quasi-static” C-V curve.)


3 - 38

MOS Capacitor (Ideal) - The C-V Characteristic equivalent circuit

VOX, COX +

C OX =

VA

P-Type Si

C

-

ΨS,

C S

ε A OX

OX t

CS

ε A S

=

≈ C OX = C

W

ε OX A OX t

OX = ≈ C C

C =

Accumulation

C C OX S

=

C OX S +C

C OX ε W OX

1+

OX ε A OX t

+QG t OX

-Q G +QS W

-Q S

low frequency

St OX ε

COX

COX

Depletion COX CS

C =

Inversion

OX S C C

=

OX S C +C

1+

OX C OX T W ε St OX ε

COX CS(min)

high frequency

0 Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham

V T

VG 3 - 39

MOS Capacitor - Qualitative Description of the C-V (cont.) M O S

(a) accumulation

(b) depletion

∆QG

+Qp

+QG -QG

W

∆QP

-QD ∆Q D

∆QG X O

X O

C

(c) inversion (low-frequency)

C

∆QG

S

C

(d) inversion (high-frequency)

∆QG +QG

+QG

WT

WT

-QD ∆Q -Qn

-QD ∆Q D -Qn

n

X O

C


X O

C

) n i m (S C

3 - 41

MOS Capacitor - Band Diagram, Isolated Materials Real For a real (non-ideal) MOS capacitor, φM < φS

M

O

S

EVAC EC

qφM qφS EG(SiO2) ≈ 9 eV EFM

EC EG(Si) = 1.1eV (aluminum)

Ei EFS

EV EV Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham

3 - 43

Let us consider a real (non-ideal) MOS capacitor, where the work functions are not equal. We will consider an aluminum gate for example, as historically this is the most common choice (we will consider poly-Si gates in the next module). For an aluminum gate over a silicon substrate, φ < φ M S. This is generally true regardless of whether P-type or N-type silicon is φ used as the substrate. The value of S depends on the position of the Fermi level E FS, which of course depends on the doping (type and concentration). We will continue to use P-type silicon for illustration; the N-type MOS capacitor will be summarized at the end.


3 - 44

Real MOS Capacitor - Band Diagram, Equilibrium + + + + + + + W

B- B- B- B- B- B- B-

Vbi

equilibrium (no applied voltage)

ΦMS ≡ φM - φS

P-type

Vbi = - ΦMS

Vbi

(built-in voltage)

source: Solid State Electronic Devices, B.G. Streetman, Prentice Hall, 1990.

EC EG(Si) ΨS = ΦMS

qφB

EFM

Ei EFS

EV

M (aluminum)


O

W

S

3 - 45

* Because φ < φ M S, the bands bend as shown above when the Fermi levels align at equilibrium (no applied voltage).

φ - φ The quantity Φ < φ MS (≡ φ M S) is the work function mismatch. Because M S for an aluminum gate over silicon, Φ MS is a negative number. This is generally true for both N-type and P-type Si, as shown on the graph aboveΦ (MS vs. doping concentration).

As indicated by the band bending, the device has a built-in voltage V in depletion at equilibrium as bi equal to -Φ MS. The device is depicted on the band diagram (i.e. Ψ S = Φ MS).

*

Electrons can not flow through the oxide (an insulator) to facilitate this equilibration. So to visualize how this works, imagine connecting a wire between the gate and substrate while they are isolated, and then assembling the MOS structure. Electrons will flow through the wire and the band diagrams will slide vertically wrt. one another until the Fermi levels have aligned (equilibrium). In practice, if electrical contact is made to the MOS capacitor, there is alwa ys some “back door” path like this by which equilibration can take place (e.g. through a power supply or battery).


3 - 46

Real MOS Capacitor - Band Diagram, Flatband VFB = -Vbi = ΦMS +

Vbi VFB

M O S

VFB

VFB P-type

Vbi

VG = VOX + ΨS + VFB VFB = Flatband Voltage for an ideal MOS Capacitor, VFB = 0

for an Al gate on Si, V FB < 0

EC Ei EFM

VFB

EFS

EV (aluminum)


3 - 47

A voltage can be applied to the gate to compensate for the work function mismatch and “flatten” the bands; this voltage is called the flatband voltage, V FB. Applying a negative gate voltage V FB = -V bi (= Φ MS) will attract holes to the semiconductor surface and reduce the depletion region to zero ( W = 0, Ψ = 0), shifting the band diagram to the flat-band condition as shown above S (zero net voltage across the capacitor).


3 - 48

Real MOS Capacitor - Oxide Charge


If there is a non-negligible amount of oxide charge, the flatband voltage becomes: Qi Flatband voltage w/ Qi = effective net oxide charge V FB = Φ MS − COX = oxide capacitance = εOXA/tOX oxide charge included C OX ΦMS < 0 for Al gate over Si


3 - 49

Another non-ideality is the presence of charge in the gate oxide. There are four general categories of oxide charge: •

+, K+, Li+), usually from the processing environment Mobile ionic charge: due to contaminants (e.g. Na

•

Oxide trapped charge:

•

Fixed oxide charge:

•

Interface states (traps):

from plasma processing, or hot electron injection (in a transistor)

due to unoxidized Si within ~20 Å of the Si-SiO2 interface due to dangling/incomplete bonds at the Si-SiO2 interface

These charges contribute to band-bending at equilibrium, and are taken into account in the flatband voltage. Historically, these charges (particularly the mobile ionic charge) inhibited the development of high-quality MOS devices because they were not well understood and were difficult to control. Modern manufacturing processes minimize the amount of oxide charge, enabling th e mass production of high-quality, high-performance MOS devices. Note that, for Φ MS < 0, positive oxide charge ( Qi > 0) will push the P-type semiconductor surface further into depletion (i.e. will require more B- charge under the gate to compensate the positive charges in the oxide). N egative oxide charge will work against Φ MS, reducing the degree of depletion. Qi is almost always positive, for both P-type and N-type substrates (wells).


3 - 50

Real MOS Capacitor - Surface Potential Revisited Adding the flatband voltage into the previous (ideal) relationship: V + ΨS G = V FB + V OX

G = V FB + Ψ S − γ Ψ S + V

recall:

= γ

exp ª«

k BT q

¬

qN 2ε C ' s

A

q (ΨS − 2φ B) º

» k BT ¼

P-Type

OX

or:

= γ

2ε qN C ' s

D

where:

' OX = C

OX ε OX t

N-Type

OX


3 - 51

The flatband voltage, which accounts for the work function mismatch and any oxide charge, is added into our previous derivation of the relationship between the applied gate voltage and the surface potential.


3 - 52

MOS Capacitor – Threshold Voltage Revisited Threshold Voltage

P-Type MOS Capacitor

B = where φ

2ε qN 2φ V = V + 2 φ + C ' S

T

FB

A

BT § k p·

ln¨ ¸ n¹ ©

q

i


B

B

OX

' OX = C

(V in magnitude) FB < 0 for Al gate on Si → Increases P-type V T

ε OX t OX


N-Type MOS Capacitor

2ε qN 2φ V = V − 2 φ − C ' S

T

FB

D

where

B = φ

BT § k n·

B

B

OX

(V in magnitude) FB < 0 for Al gate on Si → Decreases N-type V T


q

ln¨ ¸ n¹ © i


C ' OX =

ε OX OX t


3 - 53

The flatband voltage must also be added to the ideal threshold voltage calculation. Note from the foregoing discussion that, for an aluminum gate over P-type silicon (and reasonably low amounts of oxide ch arge) the flatband voltage is negative (i.e. negative potential on gate relative to substrate) and hence reduces the threshold voltage for a P-type MOS capacitor per the equation shown above. This makes sense: the capacitor is biased slightly into depletion at equilibrium, thus strong inversion (threshold) will be achieved at a lower applied voltage. (V FB is generally negative for an aluminum gate over N-type silicon as well, and will serve to increase case.)


V in magnitude in that T

3 - 54

Real MOS Capacitor - C-V Characteristic Revisited

C

P-Type Si

VFB

A ε OX

low frequency

t OX

ideal

Accumulation

real

Depletion

Inversion

high frequency

0 Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham

V T

(ideal) V T

VG 3 - 55

The MOS capacitor is slightly in depletion at equilibrium, and hence the whole C-V curve is shifted to the left by an amount equal to the flatband voltage. As previously noted, the threshold voltage of a P-type MOS capacitor will be reduced (vs. the ideal case), because the capacitor is already biased into depletion at equilibrium.


3 - 56

MOS Capacitor -N-Type Si at a Glance VG = 0

VG < 0, |V G| < |V T|

- - -

-

-

P+ P+ P+ P+ P+ N-Type

+ + + + + + + +

••••••••

------------W

N-Type

Equilibrium (ideal)

VG > 0

VG < 0, |V G| = |V T|

WT

N-Type

Depletion

VG < 0, |V G|

o o o o o o o o

Strong Inversion (Threshold)

→ |VT|

- - - - - - - - o o o o

N-Type

Accumulation


W

N-Type

Inversion

3 - 57

This is a summery of an (ideal) N-type MOS capacitor. It is analogous to P-type (note that the volt age polarities are reversed).


3 - 58

MOS Capacitor -N-Type Si at a Glance (cont.) Depletion VG < 0, |VG| < |VT| Equilibrium (Ideal) VG = 0

M

O

ϕB

Inversion VG < 0, |VG| → |VT|

-

Accumulation VG > 0

EC EFS Ei EV

EV

••••••••••

EFM

+

VG = VOX + ΨS ΨS → 2ϕB ps → ND

W

ϕB o o

••• ••••••••••

EC EFS Ei

o

EV

EFM

••••••••••

EC EFS Ei

EFM

+

W EFM

-

S (N-Type)

VG = VOX + ΨS ΨS < 2ϕB

EC EFS Ei

+

EV

o

Strong Inversion (Threshold) VG < 0, |VG| = |VT|

VG = VOX + ΨS ΨS = 2ϕB ps = ND

WT EFM


••••••••••

ΨS o oo oo o

ϕB o

EC EFS Ei

+

EV 3 - 59

This is a summary of the band diagrams for an (ideal) N-type MOS capacitor. It is analogous to P-type. Also note that the equations provided in this module are written for both N-type and P-type MOS capacitors.


3 - 60

MOS Capacitor -N-Type Si at a Glance (cont.)

N-Type Si C A ε OX

low frequency

t OX

Accumulation Depletion Inversion

high frequency V T


0

V G

3 - 61

The C-V curve for an (ideal) N-type MOS capacitor. For a real (non-ideal) aluminum-gate N-type MOS capacitor, Φ MS < 0 and hence V FB < 0. The C-V curve shown above will be shifted to the left by an amount V (i.e. the device is in accumulation at equilibrium, and V is increased in magnitude). FB T


3 - 62

4 The

MOSFET

Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

4-1

This is the fourth module in a five-module introduction to semiconductor devices. The modules are: 1. Electronic Properties of Silicon 2. The PN Junction 3. The MOS Capacitor 4. The MOSFET 5. Small Circuits The transistor is the heart of modern electronic devices, allowing integrated circuits to perform logic functions and store information (memory). I n this module, we will combine the concepts of the previous three modules to understand how transistors work. Objectives of this module: • Show that the MOSFET consists of two PN junctions (source and drain) separated by a MOS capacitor (gate) • Identify the various layers and features of the MOSFET • Understand the similarities and differences of N-channel vs. P-channel MOSFETs • Understand MOSFET operation as a voltage-controlled switch • Understand the different biasing regimes of the MOSFET – subthreshold, linear, saturation • Understand the band diagram of the MOSFET in these biasing regimes • Understand the I-V curve of a MOSFET • Understand how the channel length and gate oxide thickness affect the performance of the transistor • Understand how circuit speed is related to transistor drive current and RC delay • Understand some short-channel effects and challenges associated with shrinking transistor dimensions Looking Back: We are prepared to study the MOSFET because we understand the physics of the PN junction and the MOS capacitor from the previous modules. Looking Ahead: At the end of this module we will understand how transistors work. In the next module, we will combine transistors together to build some basic logic and memory circuits. Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

4-2

MOSFET - Layer/Feature ID Metal-Oxide-Semiconductor Field-Effect Transistor Top & Cross-Section View (Layered) Source

•

Gate

•

Drain

•

Source-to-Drain Cross-Section

metal lines contact / via interlayer dielectric (ILD)

Source

•

Gate

•

Drain

•

N+

poly-Si gate gate oxide

N+

P

source / drain regions isolation substrate / well


N+

Source: PN Junction (Diode)

Gate: MOS Capacitor

Drain: PN Junction (Diode)

4-3

MOSFET stands for Metal-Oxide-Semiconductor Field-Effect Transistor. The MOSFET consists of a source, gate, and drain. Current flows from the source to the drain under the influence of the gate voltage. (Note that the MOSFET structure is symmetrical; i.e. which end is the “source” and which is the “drain” is determined by the applied voltages, which will be discussed shortly. The side that carriers flow out of is called the source, and the side they flow into is the drain.) The source and drain regions in the semiconductor are PN junctions. The gate region is a MOS capacitor. We will combine our knowledge of these to understand the physics of the MOSFET. Other features of the structure include the metal lines (typically aluminum or copper), which carry signals among transistors to form the circuit, and the interlayer dielectric or ILD (typically SiO 2) which isolates the metal lines from one another and from the silicon substrate. In modern integrated circuits there are typically several layers of metal, separated by layers of ILD for isolation, and vertical connections are made between metal layers by vias (typically tungsten or copper). Also note the isolation oxide, which electrically isolates neighboring transistors. In our discussion of the MOS capacitor, we used a metal gate. Early MOSFETs were fabricated with aluminum gates, however, modern transistors use a heavily (degenerately) doped poly-silicon * gate. The poly-Si gate has certain processing advantages (e.g. can withstand higher processing temperatures than aluminum and has certain patterning advantages). The poly-Si gate is doped simultaneously with the source and drain regions in aself-aligned gate process, which helps to optimize the alignment of the gate to the source/drain regions. More on poly-Si gates later.

* The term “poly-silicon” is short for “poly-crystalline silicon”. Poly-Si does not have a perfect crystal structure like single-crystal silicon. On a molecular level, poly-Si consists of “grains” - within a grain the silicon has the single-crystal structure, but the crystal orientation is not preserved across grain boundaries. Note: Enhancement-mode (“normally off”) MOSFETs are discussed here, as they are the predominant choice for modern IC production. Depletion-mode (“normally on”) transistors are not discussed.


4-4

MOSFET - Two Types gate

source

•

drain

•

•

source

•

gate

•

N+

•

P+

N+

device structure

drain

N+

P+

P+

N

P

N-Channel Transistor

P-Channel Transistor gate

gate circuit symbol

source


drain

source

drain

4-5

There are two types of MOSFET, N-channel and P-channel (the term “channel” will be explained shortly). The d evice structure is the same, only the doping differs, as shown.


4-6

Part 1 – Large Geometry MOSFET


4-7

We will divide our study of the MOSFET into two parts. First, we will study the large-geometry MOSFET. In Part 2, we will extend this study to small-geometry (short-channel) MOSFETs.


4-8

The Basics - Turning the MOSFET On & Off

source

•

gate

•

drain

•

MOSFET at Equilibrium (no applied voltages) N+

N+

P

depletion region

•

backside/well


4-9

The MOSFET is actually a four-terminal device, when the backside contact is considered (this may also be referred to as the body, substrate , tub, or well contact or “tap”). We will use the N-channel MOSFET for example. The operation of the P-channel transistor is analogous, and will be summarized later. The N-channel transistor is shown here at equilibrium, i.e. no applied voltages. Note th e depletion regions formed by the source and drain PN junctions. If the width of these depletion regions is negligibly small relative to the gate length and width, the transistor is considered a large-geometry MOSFET. We will study the physics of large-geometry MOSFETs first, and then extend this to small-geometry MOSFETs in Part 2. The MOSFET behaves like a microscopic electrical switch in digital applications, and we will start by understanding how to turn it on and off. (In analog applications the MOSFET behaves like a microscopic amplifier. The focus of this course is digital applications, but the concepts can be applied to analog applications as well.)


4 - 10

The Basics - Turning the MOSFET On & Off (cont.) V GS = 0

•

+V DS

•

No Applied Gate Voltage MOSFET is “OFF” N+

N+

reverse-biased PN junction: depletion region widens, only leakage current

P

V GS < V T

•

+V DS

•

Subthreshold MOSFET is “OFF” N+

N+

P


MOS capacitor is biased into depletion, only leakage current 4 - 11

V For normal operation, the source and backside are grounded, and a positive drain-to-source voltage V DS is applied. With GS = 0 (the gate-to-source voltage), the device is considered to be OFF. Note that the source PN junction is zero-biased and the drain PN junction is reverse biased , so there is only a small leakage current in the device.

V For V , the MOS capacitor is biased in depletion. As surface inversion begins, but is not sufficient to GS << V T GS approaches V T turn the device on (see next page). The transistor is still considered to be OFF (only a tiny drain current due to junction leakage and V subthreshold current). Note that the voltage under the gate increases from source to drain due to the presence of DS, hence so does the depletion layer width W .


4 - 12

The Basics - Turning the MOSFET On & Off (cont.)

V V GS ≥ T

•

I D

+V DS I D

•

At or Beyond Threshold MOSFET is “ON” N+

•••••••••••••••••

N+

P

The depth of the channel is exaggerated for illustration purposes in this diagram. It is actually more like a “sheet” of charge right under the gate oxide. Note:


4 - 13

When V (threshold voltage), strong inversion occurs in the MOS capacitor, forming an inversion layer or channel of GS = V T electrons underneath the gate oxide. This channel shorts the source and drain regions, forming a con ductive path. Once this V channel is formed, electrons flow from source to drain under the influence of DS, giving rise to the drain current I D. The transistor is ON. The MOSFET behaves like a microscopic, voltage-controlled switch. The gate voltage determines whether the switch is open (no current) or closed (current). Note that the channel is formed by the gate voltage (vertical electric field). This is where the termField Effect Transistor (FET) comes from.

*

In the diagram above, the drain current I D is shown flowing in the direction of conventional current. Conventional current, by definition, flows from the positive terminal to the negative terminal (in this case, ground) and hence is always opposite to the direction of electron flow. As noted in module 1, the slides in this course show currents in the direction of conventional current flow unless otherwise specified.


4 - 14

MOSFET - I-V Characteristic ramp V DS constant V GS > V T

•

I D

•

For a constant gate voltage (above threshold), ramp V DS and measure I . D

••••••••••••••••• N+

N+

P

I D constant V GS

I D(SAT) Linear

0 Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

Saturation

V DS(SAT)

V DS 4 - 15

The graph above is the DC current-voltage (I-V ) characteristic of the MOSFET. It shows the drain current vs. source-to-drain V V voltage for a constant gate voltage. For DS < V DS(SAT), I D increases linearly with V DS (ohmic behavior). Near DS(SAT), the V (SAT) V V current begins to saturate. Beyond the current is constant (saturated) and does not increase with . DS , DS DS(SAT) is called the saturation voltage . I is the , aka. . (SAT) saturation current drive current D We will discuss the physics behind this I-V characteristic in detail.


4 - 16

MOSFET - Band Diagram Equilibrium

gate

source

•

•

Applied Drain Voltage

drain

•

N+

+V DS

V GS = 0

•

•

N+

N+

N+

P

P

•

backside/well reverse biased drain

EC

••••••••••••••

qVbi

••••••••••••••

EC

••••••••••••••

qVbi

••••••••••••••

EF

EF

oooooooooooooooo

oooooooooooooooooo

EV

EV

W

qVDS

W

W W


4 - 17

The source and drain regions form two back-to-back PN junctions, hence the band diagrams shown here. (These should look familiar - see the exercise at the end of the PN Junction module.)


4 - 18

MOSFET - Subthreshold V GS 0 → V T +

small V DS I + D

•

•

Gate MOS capacitor is biased into depletion

e-

N+

N+

P

leakage

EC

••••••••••••••

q(Vbi-ΨS)

••••••••••••••

EF

ooooooooooooooo

EV

W W Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

from previous band diagram, for reference 4 - 19

The source barrier height is reduced a small amount by the surface potential ( Ψ S), slightly forward biasing the source diode. There is not enough gate voltage to produce a good channel (V ), but some electrons are present in the region underneath the gate, GS < V T subthreshold current V and a small amount of (aka. leakage current) does flow from source to drain under the influence of DS. Increasing V GS increases Ψ S, further reducing the barrier height and increasing the subthreshold drain current I DS. The transistor is still considered OFF (but leaky) in this subthreshold regime. The threshold voltageV represents the OFF-to-ON T transition point in gate voltage. Subthreshold leakage current is undesirable in a MOSFET – it leads to increased static power consumption and may contribute to other non-idealities such as noise or latchup. A well-designed transistor will have low leakage and an abrupt tu rn-on transition at V . T 

Remember that the subthreshold characteristics of the MOSFET are dominated by the source diode.


4 - 20

MOSFET - Subthreshold (cont.)

+V GS

•

N+

•

µ eff

+V DS

•

N+

electron

effective/surface mobility illustrated

Subthreshold Swing:

S=

S≈


dV GS

(log 10 I d D)

= ln(10)

ln(10) ª«1 +

k BT q

¬

dV GS

(ln I d D)

C D º

» C OX ¼ 4 - 21

MOSFET - Linear Regime V GS ≥ V T +

•

N+

V DS < V DS(SAT) I + D

•

N+

P

EC

••••••••••••••

ID

••••••••••••••

EF

N-type channel, behaves like a resistor (ohmic) EV

hole current negligible Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

o o o oo o o o o o o o o o o

from previous band diagram, for reference 4 - 23

V When the gate voltage exceeds the threshold voltage ( V ), the transistor turns ON. The source barrier height is reduced to GS ≥ T near zero by the surface potential ( Ψ S), and the source diode is strongly forward biased. Electrons flow out of the source (diffusion V current) forming the channel. Electrons flow to the drain under the influence of DS.

Increasing V GS (for a constant V DS) increases Ψ S, sucking more electrons into the channel from the source, hence increasing the drain current I D. As discussed previously, there is a limit to this: although the channel carrier concentration increases, the effective/surface mobility decreases. Increasing V DS (for constant V GS) increases the source-to-drain potential, linearly increasing I D - the transistor is in the linear region of operation and the I D-V DS characteristic is ohmic. The channel is behaving like a simple resistor (as indicated by the band diagram). 

Remember that the behavior of the MOSFET in the linear regime is dominated by the Gate (MOS) capacitor.

This band diagram is taken at a cross-section just under the gate oxide (through the channel). What do es the band diagram look like deeper into the substrate, e.g. through a cross-section near the bottom of the source/drain regions, out in the Ptype bulk, etc? (See next slide ...) Question:

Inversion Charge - MOS Capacitor vs. MOSFET:In our discussion of the MOS

capacitor, the inversion charge came from minority carrier generation near the semiconductor surface. In the MOSFET, however, the inversion charge comes mainly from the source via source barrier lowering (i.e. forward biasing the source junction). Electrons diffuse from the source into the region under the gate to form the channel. Therefore, the MOSFET has a much better supply of electrons for the inversion layer (channel) than the MOS capacitor. In other words, the inversion layer in the MOS capacitor is electrically isolated from the outside world – thermal generation is its only source of electrons. The MOSFET inversion layer (channel) is electrically connected to the outside world (power supply) through the source and drain. More on this later. Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

4 - 24

MOSFET - 3-D Band Diagram L

y x



4 - 25

These are 3-D band diagrams for the MOSFET. They show the combined influence of the gate and drain voltages, and at various depths into the substrate. Diagram (a) shows the orientation of the structure, with the gate facing out of the page. Diagram (b) shows the bands at equilibrium. Diagram (c) shows an applied gate voltage but no drain voltage. Diagram (d) shows applied gate and drain voltages. By observing the energy gradients on these diagrams, it is easy to see how electrons will “roll downhill” to th e gate region (channel V V formation, under the influence of GS) and then “roll downhill” from source to drain (conduction, under the influence of DS).


4 - 26

MOSFET - Linear Into Saturation V GS ≥ V T +

•

N+

V DS → V DS(SAT) I D → I D(SAT) +

V GS ≥ V T +

•

•

N+

N+

P

V DS = V DS(SAT) I D = I D(SAT)

•

+

N+

P At V DS = V DS(SAT), the channel is pinched off at the drain edge

EC EF

••••••••••••••

ID

EC

••••••••••••••

••••••••••••••

ID(SAT)

EF

•••••••••••••• EV


EV

4 - 27

Increasing V DS widens the depletion region at the drain end of the channel. The depletion region encroaches on the channel near the drain, starting to “pinch off” the channel. AtV DS = V DS(SAT), the channel is pinched off at the drain edge.


4 - 28

MOSFET - Saturation ≥ V V GS T +

V DS > V DS(SAT) I D = I D(SAT)

•

•

+

V DS(SAT) ≈ V GS - V T

∆L N+

N+

P

EC

••••••••••••••

No longer behaving like a simple resistor. Now looks like a depletion region being fed by the channel.

ID(SAT)

EF

EV

••••••••••••••


4 - 29

For V DS > V DS(SAT), the pinch-off point pulls back from the drain. ∆L = 0 at V DS = V DS(SAT). As V DS is increased beyond V DS(SAT), ∆L becomes larger. is a useful approximation of the saturation voltage, V V GS -V T DS(SAT).

At the source end of the channel, the whole gate voltage is effective in inverting the surface (because the source is grounded, hence the voltage drop at the source end of the channel is always V simply V (GS – GS). At the drain end of the channel, however, only the difference between the gate and drain voltages is effective V V – V V ). When the drain voltage equals , it follows that the voltage drop across the drain end of the channel is just , and DS GS T T hence the channel (inversion) charge falls to zero at the drain end – i.e. pinch-off occurs and saturation begins. In other words, , then V when V (V DS ≥ V GS – V T GD ≤ V T GD is the gate-to-drain voltage), and the channel is pinched off at the drain end. Note that the subgate region is no longer behaving like a simple resistor. It now looks more like a reverse-biased junction being fed by the channel. The next slide will explain this in more detail.


4 - 30

MOSFET - Saturation (cont.) electrons (minority carriers)

P

I D(SAT)

I 0

electron channel

• • •

•••••••••• •••••••• •••••••

N+

Reverse-Biased PN Junction Diode

∆L

+

V DS > V DS(SAT)

•

N+

drain

W

+

P

VA

substrate/ well MOSFET in Saturation

P I D

I

constant V GS

I D(SAT) Linear

0

I0 Reverse Bias

Forward Bias

(Off / Leakage)

(On)

Saturation

VA


0

V DS(SAT)

V DS 4 - 31

Why does the drain current saturate?

A parallel exists between the reverse saturation current ( I 0) of a PN junction diode and the saturation current of a MOSFET. In both cases, the current is constant with respect to applied voltage because the current through the depletion region is supply limited . In the case of a reverse-biased PN junction, the carriers are supplied by minority carrier generation in the quasi-neutral region . These carriers are swept across the depletion region by the applied voltage ( V A). The currentI 0() is very small because there are V few carriers available. Increasing does not increase the supply of carriers (only their kinetic energy as they traverse the A depletion region), therefore I 0 is supply limited and constant wrt. V A. For the MOSFET in saturation, the carriers are supplied by the channel (inversion layer). The electrons in the channel get swept across the depletion region (∆L) by the applied drain voltage ( V V DS). Increasing DS does not increase the supply of carriers (only their kinetic energy as they traverse the depletion region), therefore I D(SAT) is supply limited and constant wrt. V DS. The key difference is that the channel is a much better supplier of carriers than the minority carrier generation in a PN junction diode, so I D(SAT) is a much larger current (~mA) than I 0 (~pA).



Remember that the behavior of the MOSFET in saturation is dominated by the drain diode.


4 - 32

MOSFET - Saturation Analogy Linear ID

water in

water out

source

channel drain

ID(SAT)

water in

Saturation channel water out

source

drain Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

4 - 33

An analogy to illustrate saturation. The top drawing shows a canal which is analogous to the MOSFET in its linear regime. The water d roplets represent electrons and the water current represents the the flow of electrons. The height of the hill representsV DS. By lowering the drain end (i.e. increasing V ) the hill becomes steeper and the current increases. DS The bottom drawing depicts saturation. The drain becomes discontinuous with the channel (representing the pinch-off and pullback of the channel). There is a waterfall at the drain edge (analogous to the reverse-biased drain junction). Lowering the drain end represents making V DS > V DS(SAT). The current is supply limited, and lowering the drain end does not increase the current flow. Note that in either case, increasing the gate voltage is analogous to making the water deeper – it will increase the current.


4 - 34

MOSFET - I-V Characteristic, Revisited

V DS(SAT) = V GS - V T

I D

V GS = +3 V Saturation Linear

V GS = +2 V

V GS = +1 V

0

aside


V DS

4 - 35

The I-V characteristic is shown for several gate voltages. Note that the drain current increases with increasing gate voltage, as expected, but the basic shape of the I D-V DS curve remains the same. Note that the plot has been extended to show V DS < 0. In this case, the drain junction becomes forward-biased and starts to I-V V behave like a diode. The typical diode characteristic is observed for V GS = 0 (gate grounded). For GS > 0 the gate voltage increases the magnitude of the drain forward-bias somewhat (try to visualize this on the band diagram), giving rise to the curves shown to the right of the true diode curve. The MOSFET is not usually operated this way -- normal operation requires that the drain be reverse-biased per the forgoing discussion. This is mentioned as an aside for completeness, because it is possible for some transistors (particularly in analog circuits) to enter this region of operation under certain conditions. Aside:


4 - 36

MOSFET - Useful Equations Threshold Voltage

N-Channel MOSFET

where

2ε qN 2φ V = V + 2 φ + C ' S

T

FB

A

B

φ =

BT § k p·

B

ln¨ ¸ n¹ ©

q

i


B

OX

C ' OX =

ε OX

t OX


P-Channel MOSFET

qN 2φ 2ε V = V − 2 φ − C ' S

T

FB

D

B

OX

where

φ =

BT § k n·

B

B

ln¨ ¸ n¹ © i


' OX = C Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

q

ε OX

OX t


4 - 37

Recall these threshold voltage expressions from the MOS capacitor module. They can be used to approximate the threshold voltage of an ideal (large geometry) MOSFET. Keep in mind, however, that the MOSFET inversion charge comes from the source rather than from thermally-generated minority carriers in the substrate/well, so this is only an approximation.


4 - 38

Aside: Work Function Mismatch for Poly-Si Gate

Poly-Si gate P-channel transistor

Al-gate P-channel transistor Poly-Si gate N-channel transistor

Al-gate N-channel transistor

substrate/well doping concentration Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham


4 - 39

MOSFET - Useful Equations (cont.) I D-V DS Equation: Square-Law Theory Drain Current - Linear Region

β D = I

for

eff µ Z C ' OX ª

L

GS − V T )− «(V

¬

V DS º DS »V

2¼

L = channel length Z = channel width (perpendicular to L) µeff = surface mobility [~ 500 cm 2/V·s for electrons in Si at 300K, ~ 150 cm2/V·s for holes] C OX = gate capacitance per unit area = εOX/tOX β = gain / transconductance factor ’

V , V GS ≥ V T DS < V DS(SAT)

Drain Current - Saturation Region (Drive Current)

substituting

I )= D ( SAT

DS ( SAT GS − V T ) = V V

Z C ' OX µ eff

2L

2

(V −V ) GS

T

, V for V GS ≥ V T DS ≥ V DS(SAT)


4 - 41

The Square Law Theory is a simple model of MOSFET operation. It assumes that the depletion region width for all points in the I channel remains fixed at W , even when V , i.e. V T DS > 0. Note that D varies linearly with V DS when V DS is small ( V DS << V GS – V T DS 2 (SAT) V V (SAT) I V /2 I -V << V ). As approaches , is reduced by the term, and the curve starts to slope over leading DS DS DS D DS D DS into saturation; this “slope over” transition region between linear and saturation is commonly called thetriode region. The multiplier out in front of the equation is sometimes referred to as the gain (aka. gain factor , transconductance factor ), β , of the MOSFET. Note that the electron mobility is typically much greater than the hole mobility - the exact values depend a great deal on the transistor design and process technology, but typically the electron mobility is 2 to 4 times greater than the hole mobility. Therefore, all other factors being equal, an N-channel transistor will have a higher drive current than a P-channel transistor (discussed later) - again, the difference is technology-dependent, but it is common to see N-channel transistors with 2 to 4 times more drive current than the equivalent P-channel transistor. Note also that surface mobility decreases with increasing temperature, due to the increased frequency of scattering events. Thus, the MOSFET will have a lower I D at higher temperature. The utility of the Square-Law Theory lies in its simplicity; it is useful for understanding general trends, basic inter-relationships, etc.


4 - 42

MOSFET MOSFET - Useful Useful Equatio Equations ns (cont.) (cont.) I D-V DS Equation: Bulk-Charge Theory

3 ª º½ 2 °°§ C V · ' Z 4V φ «§ V · § 3V ·» °° µ I = − ¨1 + ¸» ¾ «¨1+ ®¨V − V − ¸V − ¸ L 2¹ 3 « 4φ ¹» ° °© 2φ ¹ © © °¯ «¬ »¼ °¿ eff

D

OX

DS

GS

DS

W B

T

DS

DS

for

V , V GS ≥ V T DS < V DS(SAT)

B

B

Square-Law Theory

φ =

k BT § N A ·

B

V W ≡

2º °ª V V V − § · ° V ( SAT ) = V − V − V ®« + ¨ 1+ ¸» ° 2φ © 4φ ¹ Square-Law »¼ ¬ °« Theory ¯ GS

DS

GS

T

T

W

W

B

Introduction Introduction to Semiconductor Semiconductor Device Device Physics Physics / MOSFET / rev 4.3 Tom Cunningham Cunningham

B

1 2

½ ° § V ·° ¸¸¾ − ¨¨1 + ϕ 4 © ¹° ° ¿ W

W T =

q

ln¨

¸ n ¹ © i

qN AW T qN AW T t OX C ' OX

=

ε OX

(2ϕ ) 2ε S

B

qN A

B

4 - 43

The Bulk-Charge Theory is more complex than the Square-Law Theory, but gives results that are in better agreement with experimental observations. It takes into account the fact that the depletion region width (“bulk charge”) v aries from source to drain, i.e. looking down the MOSFET channel, gate charge is not balanced solely by changes in the inversion charge, but also by by changes in the depletion layer charge. The extra terms in the Bulk Charge model act primarily to reduce I D and V DS(SAT) wrt. the Square Law Theory. The accuracy of the Square-Law Theory improves as the substrate doping and/or gate oxide thickness is decreased (i.e. as the body factor γ is → 0), the Bulk-Charge Theory mathematically reduces to the decreased). In fact, forN A → 0 (i.e. φ B → 0) and t ox → 0 (i.e. V W Square-Law Theory (because the multiplier in front of the second term goes to zero). Many other models exist. Typically, accuracy is gained at the expense of simplicity. Many models are empirical or semiempirical. Many apply to only a certain subset of MOSFETs, such as those of a certain size or geometry, or those fabricated on a particular fab process.


4 - 44

MOSFET MOSFET - Useful Useful Equatio Equations ns (cont.) (cont.)

source: Pierret & Neudeck (editors), Modular Series on Solid vol. 4, Addison-Wesley Publishing, 1988.

State Devices,


4 - 45

This graph compares the Square-Law Theory to the Bulk-Charge Theory. Note that th e Bulk-Charge result approaches the SquareLaw prediction as the substrate doping is lowered.


4 - 46

MOSFET MOSFET -- Useful Useful Equatio Equations ns (cont.) (cont.) Conductance for VDS << (VGS – VT)

[(V β GS − V T DS ] ≈ β GS − V T ) − V (V )

D dI

gd =

linear

=

DS dV

0

saturation

drain voltage

where:

β =

Z C eff ' OX µ L

Transconductance

gm =

dI D

β DS V

dV GS

β (V ) GS − V T

linear

= saturation

gate voltage


4 - 47

Conductance (g) is the reciprocal of

R. It measures the change in current for a given change in applied resistance, i.e. g = 1/

voltage. When the transistor is operated in the linear regime, it behaves like a simple resistor. TheI ID -V DS characteristic is a straight line, the (constant) slope of which is equal to the conductance g d (aka. drain conductance or output conductance ) of the device, i.e. the gd change in drain current that results for a given change in source-drain voltage. To obtain an expression for , we differentiate the I -V V relationship from the Square Law Theory wrt. (to obtain an expression for the slope). Furthermore, in the linear region, D DS DS << V (SAT) , V << (V V ) far from saturation, we can make the simplification that V i.e. . We see that the resulting DS DS DS GS T V VGS , decreasing expression for gd is constant wrt. V It also shows that the conductance increases in creases with increasing DS , as expected. It V Z L V V (SAT) = V , wider (channel width), and/or shorter (channel length), as expected. Note that as approaches , the T DS DS GS – V T conductance diminishes (triode region) and eventually becomes zero (saturation). This is also expected: the drain current does not change with drain voltage in saturation (slope = 0), as previously discussed. The transconductance (gm) measures how the drain current changes with applied gate voltage. It is obtained b y differentiating the I gm is proportional to V D expression from the Square-Law Theory wrt. V GS. For the linear region of operation, DS. In saturation = V – V I (SAT) (i.e. substituting V , or differentiating the square-law expression for directly) the transconductance is seen to DS GS T D be proportional to V I ID -V V GS. (These facts can be verified by careful inspection of the DS plots for various values of GS.) As expected, the transconductance increases for decreasing V , wider (channel width), and/or shorter (channel length). Z L T The conductance and transconductance are useful for modeling the behavior of transistors in circuits, especially when ac signals are applied to the th e transistors.


4 - 48

Aside: Back Bias / Body Effect

•

• Surface potential at threshold with back bias:

Ψs = 2φ + V BB B

N+ N+

N+ Threshold voltage with back bias:

P

S

• -V

T

BB

EC

••••••••••••••

q(Vbi + VBB)

2ε 2φ + V BB qN V = V + 2 φ + ' C FB

A

B

B

OX

••••••••••••••

EF oooooooooooooooooo

EV


4 - 49

We have studied the transistor with the backside/well contact grounded. We now study the case where the backside/well is biased , and hence the barrier height is increased to as shown*. Consider the effect on the source: the source diode is reverse biased byVBB V + V , which increases the threshold voltage of the MOSFET. The net effect is thatV is increased – the surface potential at bi BB T = 2 + V S smaller (i.e. threshold is now Ψ . This also reduces subthreshold leakage and tends to make the subthreshold swing φ S B BB S is more pronounced for devices with a larger body factor γ steeper I . The MOSFET’s reaction to D-V GS slope). The effect on backside biasing is sometimes called the body effect . V Back biasing was used as an electrical technique for increasing and tailoring the threshold voltage prior to the use of adjust T ® TM implants. It is still used in some specialized applications. For example, the Intel StrongARM (aka. XScale ) microprocessor employs this technique to reduce leakage current and achieve impressively low static power consumption, ideal for mobile/handheld applications and systems with low thermal tolerances/budgets (such a closely-packed microprocessor banks). (Note: This is just one of it’s power-saving techniques.)

*

Note: One would not apply +V a BB bias to the substrate/well of an N-channel transistor. Doing so would forward bias the source –V diode, hence the gate would no longer control the transistor (it would always be on). Similarly, one would not apply a bias to BB a P-channel transistor. The backside bias can only be used to increase, not decrease, the threshold voltage.


4 - 50

MOSFET - Speed

+ Vcc (logic 1)

V

I D(SAT)

0V (logic 0)

R

t ideal

C

+ Vcc (logic 1) −

t

V

~e

~ e RC

t RC

0V (logic 0)

t higher drive current reduces this rise time, as does lower RC

real

time


higher drive current reduces this fall time (pull down), as does lower RC

4 - 51

The speed (maximum clock frequency) of a circuit can be very important, e.g. for a microprocessor. The speed of a circuit/chip depends heavily on its architecture and design. Architects and design engin eers have become quite good at maximizing circuit speed. Speed also depends a great deal on the transistors and interconnects (i.e. the fab process capabilities). Device engineers and process engineers have become quite good at tweaking every last drop of performance out of th e transistors. It is very challenging to do this while maintaining good throughput, yield, and reliability. The speed of a circuit depends on the amount of charge that must be moved to charge/discharge nodes (RC ) and the current (SAT) available to move it (I ). From the transistor and process technology standpoint, to maximize clock speed (frequency): D 1. Increase the drive current,I D(SAT). This allows the transistor to charge an interconnect line faster, thus driving the next stage (RC load) from logic 0 → 1 faster. It also allows a pull-down transistor to discharge a line faster, driving it from logic 1→ 0

faster.

time delay of the circuit, 2. Decrease the resistance and/or capacitance of the metal interconnect lines.This reduce the RC allowing signals to propagate faster.


4 - 52

MOSFET - Speed (cont.)

)= D ( SAT I source

•

' OX Z eff C

2

(V −V )

2L

GS

gate

T

drain

•

•

tOX

N+

L

N+

P

•

backside/well


4 - 53

MOSFET - Parasitic Capacitances

metal 2 lines

ILD 1

metal 1 lines

gate oxide

ILD 0

L

Cgs Cgb N+

Leff

Csb

vias / contacts

Cgd LOV

N+

Cdb

P


4 - 55

MOSFET - Parasitic Capacitances (cont.) Off

Linear

Saturation

(subthreshold) (triode) 1

COV

Cgd

COV

Cgb

COX

0

0

Csb

Cj

Cj

Cj

Cdb

Cj

Cj

Cj

where:

2 1 2

MOSFET:

- Inversion layer (channel) is electrically connected to source/drain - Source is an ample supply of electrons at any practical frequency - Charge fluctuates on either side of gate oxide (like parallel-plate) - MOSFET gate capacitance is ε A/t at any practical frequency OX OX Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

? what about the MOS capacitor C-V frequency dependence?

COX + COV

3

COX + COV

COV

OX

t OX

C OX = C j =

COX + COV

ε

C OV =

MOS Capacitor:

- Inversion layer is electrically isolated from the outside world - Inversion charge comes from R-G of minority carriers - Capacitance depends on frequency

2

Cgs

ZLOV

ε OX

t OX

ZLeff

ε A s

j

W

overlap (Miller) capacitance

gate capacitance

PN junction capacitance 4 - 57

MOSFET - Series Resistance gate

source

•

drain

•

•

Rs

I D

Rs

V’DS

N+

Rs

Rs

N+ VDS

P

•

' DS = V V DS − 2 I DRs

backside/well

I D =

eff ( Z / L) µ C ' OX (V )V D = GS − V T I GS − V T 1 + α (V ) DS

R


eff ' OX Z C µ

where:

(V )V GS − V T '

DS

L

α = R

2µ C ' RsZ eff

OX

L 4 - 59

MOSFET - Speed (cont.)

maximum clock frequency

Transistor Limited (drive current) Interconnect Limited (RC)

I D(SAT)


4 - 61

By plotting the maximum clock frequency of the chip vs. the drive current, we can see where the circuit becomes RC limited -a.k.a. “interconnect limited”, or “back-end limited” since the metal/ILD layers (and perhaps the chip package is included here too) are the “back end” of the IC manufacturing process. In the RC limited regime, increasing the drive current of the transistors has little or no effect on the speed of the circuit, because the limiting factor is the RC time (propagation) d elay in the circuit interconnects. Appreciable speed improvements can only be made by reducing the RC of the interconnect circuitry. For example, this is the main reason why the industry has switched from aluminum interconnects to copper, because copper has a much lower * for ILD -- the lower dielectric constant means lower capacitance for resistance. Another example is the use of low-k dielectrics the interconnect circuitry. Delays along the critical “speed paths” (bottlenecks) in the circuit can be reduced by improving the circuit design. Thus, it is common to see subsequent versions/revisions of an IC become progressively faster, as the critical speed paths are identified and reengineered by the design team. So improving the speed of a chip is a joint effort between the design community and the manufacturing / CMOS process development community.

*

ε0 , where ε The name “low-k” refers to the common definition of the dielectric constant as k = ε / is the permittivity of the material in question and ε 0 is the permittivity of free space. Recalling that, in general, capacitance can be expressed as C = ε A/t , where A is the overlap area and t is the thickness of the dielectric, we see that lower k implies lower ε , which in turn implies lower capacitance. As previously discussed, ILD is typically made of SiO 2 (perhaps with small amounts of phosphorous to act as a contamination gettering agent), and the addition of fluorine can be used to form a low-k dielectric.


4 - 62

The P-Channel MOSFET at a Glance

V DS(SAT) = V GS - V T

I D

Saturation

V < V T GS < 0

•

-V DS • I D

Linear

V GS = +3 V

N-channel MOSFET V GS = +2 V

P+

P+

oooooooooo

V GS = +1 V

0

P+

V DS

V GS = -1 V V GS = -2 V

N

Linear Saturation

V GS = -3 V

P-channel MOSFET


4 - 63

The forgoing discussion has focused on the N-Channel MOSFET for illustration purposes, but the basic concepts are directly applicable to P-Channel MOSFETs as well. For the P-Channel MOSFET, the current carriers are holes rather than electrons, and therefore the polarities of the gate voltage, threshold voltage, and drain voltage are negative, opposite to the case of the N-Channel device. The basic operation of the device is analogous to that of the N-Channel MOSFET. A negative gate voltage greater than (in magnitude) the threshold voltage is applied to invert the semiconductor surface in the channel region, creating a hole channel which connects the source and drain. A negative drain voltage is applied to attract the holes, creating a drain current. For lower V drain voltage, the I ) (in magnitude), the drain current is saturated. Note that the D-V DS relationship is linear; for DS ≥ V DS(SAT drain current flows in the opposite direction of the N-channel case. As previously noted, holes have a lower effective mobility than electrons, and therefore, all other things being equal, a P-Channel MOSFET will have lower drive current than an N-channel transistor. This can readily be seen on the graph above. And because the lower mobility limits acceleration, “hot hole” effects (discussed later) are generally not observed.


4 - 64

Why Silicon? Silicon is the semiconductor of choice for the modern digital IC industry: S

Good native oxide (SiO2)

S

Low junction leakage

S

Good thermal and mechanical properties

S

Manufacturing maturity and lower cost

Counter points - GaAs preferred for high-frequency analog devices and photonic devices - SiGe, the future choice for high-speed circuits?


4 - 65

Exercise: Linear I-V of a MOSFET 1.

Derive an expression for the amount of inversion charge in an N-Channel MOSFET for a given applied gate voltage V . (Hint: Q = CV .) GS ≥ V T

2.

If a source-to-drain voltage V DS is applied across this channel, derive an expression for the current through the MOSFET, assuming it is in the linear region of operation (i.e. V << V Q is injected into the channel at the source end by the forward-biased junction and drifts to DS DS(SAT) ). (Hint: the charge the drain under the influence of the source-to-drain electric field

3.

ε µ = V /L.) = v / d n

DS

What is the resistance R of the channel?


4 - 67

Are the equations you have derived here consistent with those presented earlier in this module?


4 - 68

Exercise: Linear I-V of a MOSFET - Solution 1.

Only values of V create inversion charge, therefore ( V ) is the “effective voltage” for inversion. GS above V T GS - V T

= Q = CV

ε A OX

t OX

(V − V )= GS

ε ZL

T

OX

t OX

(V − V ) = ZLC ' (V − V ) GS

T

OX

GS

T

The drain current is the amount of charge moving across the channel per unit time. The forward-biased source junction injects a chargeQ of electrons into the channel, which will drift across the channel to the drain in a time t dictated by the source-to-drain electric field, effective electron mobility, and channel length. 2.

Q

I D = t =

t L v d

D = I

3.

L

=

ε µ eff

' OX Z C µ eff

=

L L ) µ (V / DS

eff

2

V DS µ eff

ε = source-to-drain electric field

vd = drift velocity (speed) of electrons

(V − V )V GS

L

=

L

T

DS

The conductance is readily obtained from the above expression. Resistance is the reciprocal of conductance.

g= R=

D µ eff I Z C ' OX

=

DS V

L

(V − V ) GS

T

1 g


4 - 69

These equations are consistent with those presented earlier in this module. Note that we have only considered the linear region of operation of the MOSFET here.


4 - 70

Part 2 - Small Geometry MOSFET


4 - 71

We will now study the physics of small-geometry (short-channel) MOSFETs.


4 - 72

MOSFET - Short Channel

source

•

N+

gate

•

L

drain

•

N+

P

•

backside/well


4 - 73

When the depletion regions at the source and drain junctions are a negligible fraction of the channel length (L) and width (Z ), the transistor is said to be a large-geometry MOSFET. Up to this point, we have been discussing large-geometry MOSFETs. When the source/drain depletion regions are an appreciable fraction of ), the transistor is called a short-channel L (but not Z Z MOSFET. If the source/drain depletion regions are also an appreciable fraction of , it is a small-geometry MOSFET. In either case, the behavior deviates from that of the large-geometry MOSFET. The presence of the depletion regions can no lon ger be ignored, as they have a noticeable impact on the threshold voltage and the I D-V DS relationship. There are also some reliability issues associate with short-channel transistors, such as hot electron effects. Note that making the poly gate shorter will reduce L, and increase the short-channel behavior. Note also that reducing the well/substrate doping will increase the depletion region width at the source/drain edge, also increasing the short-channel behavior. (It is also worthwhile to note that making the gate oxide thinner will reduce the amount of short-channel behavior, as it gives the gate more control over the channel region and makes the electric field lines more vertical in the depletion regions.)

*

Technical Aside: For a large-geometry MOSFET, the source and drain depletion regions are of negligible size compared to the length and width of the channel, and therefore the electric field lines are regarded as vertical for all points along th e channel, even near the source and drain (this is sometimes referred to as the gradual channel approximation). This essentially allows us to ignore the “edge effects” and model the subgate electric field as one-dimensional. However, if the depletion regions are an appreciable L only (or Z fraction of only, though this “narrow-width transistor” is not common) the subgate electric field becomes twoL and Z dimensional. If they are an appreciable fraction of it becomes three-dimensional.


4 - 74

Short Channel MOSFET – Hot Electron Effects Channel Hot Electron (CHE) Injection peak electric

+V GS field region

•

DS

•

gate oxide N+

• +V

•

N+

electron

Impact Ionization peak electric

+V GS field region

•

gate oxide N+

•

• +V DS

••••

*

electron

o o N+ oo

I SUB Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

4 - 75

Short Channel MOSFET – DIBL & Punchthrough V GS = 0

•

ramp +V DS

ε εd rain

N+ Ws

V GS > V T

•

•

N+

N+

•

N+ Ws

Wd

P

V BR

ramp +V DS

Wd

P

I D

Punchthrough

observed drain breakdown voltage

DIBL / Punchthrough

Normal Junction Breakdown

(short-channel FET)

(large-geometry FET) L


0

V DS 4 - 77

Short Channel MOSFET – Threshold Voltage

L

rj

N+

WT

rj

N+

L’ W

W

s

d

P

V T

∆V = V ( short ) − V (long ) = T

T

T

qN AW T r j §

W · ¨ 1 + 2 − 1¸ C ' L ¨© r ¸¹ OX

(short-channel FET)

T

j

(large-geometry FET) L


4 - 79

I Short Channel MOSFET – D-V DS Relationship § V DS · ¸¸ I D ( SAT DS ) I D ( SAT D ( SAT I V ) short = (1 + λ )long = ¨¨1 + )long | V a | ©

¹

short-channel long-channel

I D

V GS = +3 V Saturation Linear

V GS = +2 V

V GS = +1 V

V a


0

V DS

4 - 81

For a large-geometry MOSFET, it was assumed that the drain depletion region width (W ) was a negligible fraction of the channel d Wd due to V length (L), and hence could be ignored when considering the I D-V DS relationship in saturation. Any change in DS was assumed to be insignificant, having no impact on the saturation characteristic. W For a small-geometry MOSFET, W is a non-negligible fraction of the channel length, and modulation of d d by V DS can not be V ignored. As also increases, thus resulting in a smaller effective channel length Leff and an DS is increased beyond pinchoff, W d . increased drain current I Hence, the drain current is not constant wrt. V D DS in the saturation regime for a short-channel MOSFET.

As gate length is reduced, the slope of the I D-V DS curve in saturation becomes greater. The Early voltage, V a, is the extrapolated zero-current intercept of the saturation I D-V DS characteristic. It can be used for a semiempirical calculation of the short-channel saturation current, as shown in the equation above. Note that its reciprocal,λ (units of I (SAT) V-1), is sometimes used instead. In this equation, is the long-channel saturation current (e.g. calculated from the squareD long law theory). Observe that as varies linearly with V V → I V a → ∞, I D(SAT)short D(SAT)long, as expected. For a given a, I D(SAT) short DS.


4 - 82

Short Channel MOSFET – Velocity Saturation Drain voltage for velocity saturation:

sat = L V

ε = sat

I D

steps are linear for velocity saturation

I D(SAT) – V GS

V GS = +3 V

vd ( sat ) L

V GS = +2 V

ueff

V GS = +2 V

Drain current and transconductance: D ( SAT GS − V T I ) ≈ ZC ' OX (V )

V GS = +1 V

V GS = +1 V

ε

eff

sat

vd(sat)

ε

eff sat ' OX µ ' OX vd ( sat ) = ZC gm ≈ ZC

Vsat = drain voltage at which velocity saturation occurs vd(sat) = saturation drift velocity

εsat = electric field for velocity saturation (assumed same for electrons/holes)

0

with velocity saturation without velocity saturation

velocity saturation voltage

V DS

channel pinch-off voltage

| MOSFET Saturation Voltage | =min[ |Vsat| , |VGS - VT| ] Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

4 - 83

Aside: Modeling Non-Idealities & Small-Geometry Effects models DIBL, and short-channel and narrow-width effects on V T

Z

empirical parameter modeling subgate depletion region slope from source to drain ( δ → 0 as γ → 0)

1 2

½ ¿ for VDS < VDS(SAT)

2 ' OX ®[V ' ( L, Z ,V (1 + δ )V 0C µ GS − V T DS )]V DS − DS ¾ D = I

L¯

ª {1 + θ [V ' ( L, Z ,V GS − V T DS ) ] + θ BV BS } 1 + « ¬

models effective mobility dependence on vertical field

DS º V L sat »¼

ε

models velocity saturation

saturation voltage

Z 1 0C µ GS − V T DS )]V DS ( SAT DS ( SAT ' OX ®[V ' ( L, Z ,V ) − (1 + δ )V ) 2 ½¾ 2 L¯ ¿ D ( SAT I )= )º DS ( SAT § ∆L · ª V { GS T DS B BS } [ ] 1 1 ' ( , , ) 1 − + θ − + θ + V V L Z V V ¨ ¸ «¬ » sat ¼ L Lε © ¹ models saturation ID-VDS slope, due to channel length modulation (∆L is a function of V DS)

for VDS ≥ VDS(SAT)

µ0 = empirical parameter representing the low-field effective/surface mobility (in the absence of vertical field degradation) δ = empirical parameter to model the fact that the depletion region is not uniform in depth from source to drain as the Square-Law model assumes θ = empirical parameter to model the amount by which the vertical field (V GS - VT’) degrades the surface mobility -1 θB = empirical parameter to model the effect of back bias V BS (substrate bias wrt. source) on mobility (typically on the order of 0.01V )

ε sat = critical source-drain electric field for velocity saturation VT’(L,Z,VDS) = threshold voltage adjusted for DIBL and channel length and width effects: V T’(L,Z,VDS) = VT - ∆VT(L,VDS) + ∆VT(Z) VDS(SAT) = the saturation voltage of the transistor (due to pinchoff or velocity saturation) Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham

Source: Y.P. Tsividis, Operation and Modeling of the MOS Transistor , McGraw-Hill, 1987.

4 - 85

Appendix: The CMOS Fabrication Process Isolation

P Well

N Well

Si

(a)

N+ Poly-Si

(b)

P+ Poly-Si

N+ Source/Drain

Poly-Si Gate

Gate Oxide

P+ Source/Drain

(d)


(c)

4 - 87

Appendix: The CMOS Fabrication Process (cont.)

Contacts / Vias (first layer)

Interlayer Dielectric (ILD)

(e)

Repeat for subsequent metal/via layers

Metal Interconnect Lines (first layer) N-Channel MOSFET


P-Channel MOSFET

(f)

4 - 89

5 Small But Important

Transistor Circuits

Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

5-1

This is the last module in a five-module introduction to semiconductor devices. The modules are: 1. Electronic Properties of Silicon 2. The PN Junction 3. The MOS Capacitor 4. The MOSFET 5. Small Circuits The goal of this module is to present the “big picture” surrounding all this device physics, i.e. to explain why we want to make transistors in the first place, and how a bunch of “microscopic switches” can be used to make useful chips such as logic gates and memory cells. We will also see how these can be used to make larger, more sophisticated circuits, like a microprocessor. We will obtain a high-level, big-picture understanding of how a chip is born – from design to manufacture and test. And we will study the motivations, methodologies, and technical challenges associated with shrinking (scaling) the MOSFET and advancing the state of semiconductor technology from one generation to the next. Objectives of this module: • Explain what CMOS means • Study a few basic CMOS logic gates: inverter, AND, NAND, OR, NOR • Illustrate how these basic logic gates can be combined to make larger, more complex circuits • Understand how semiconductor memory works in general, and build three basic memory cells: SRAM, DRAM, Flash EEPROM • Provide a high-level overview of how a chip is born – from design and layout to manufacture and test • Study the methodologies and technical challenges involved in shrinking (scaling) transistors and advancing the state of semiconductor technology • Provide a brief overview of the history of Intel® microprocessors and Moore’s Law Looking Back: We are prepared to understand CMOS transistor circuits because we understand how N-channel and P-channel MOSFETs work.


5-2

Transistors - So What? Transistors are used to build: Logic

Memory +V cc +V cc

•

A

B

b

b

o

•

• o

o

o

•

•

•

•

•

•

•

•

•

C

•

• word line

(example: NOR gate)

•

•

(example: SRAM cell)

(example: Pentium® 4 microprocessor) Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

5-3

Transistors can be used to build logic circuits and memory circuits. Logic circuits manipulate and transform data (bits), performing logical operations (e.g. comparing pieces of data, encoding and decoding data, etc.) and arithmetic functions (e.g. addition, multiplication, etc.). Memory circuits store information (bits) for future use. A typical chip will contain both logic and m emory. We will use transistors to build the following logic circuits: • Inverter • AND & NAND gates • OR & NOR gates • A simple control circuit • A simple decoder And we will study the following memory circuits: • SRAM cell • DRAM cell • Flash EEPROM cell


5-4

CMOS Complimentary Metal-Oxide-Semiconductor

B

•

S

•

G

•

N+

D

•

N+

P


S

•

G

•

P+

D

•

B

•

P+

N

5-5

CMOS stands for Complimentary Metal-Oxide-Semiconductor . When N-Channel and P-Channel MOSFETs are fabricated together on the same chip, the chip or circuit is called CMOS. The term “complimentary” refers to the fact that N-channel and Pchannel transistors are turned on by opposite polarities of gate voltage. N-well Note that CMOS processing requires the fabrication of N-type and/or P-type wells (aka. tubs) in the silicon substrate. In an process , N-type wells are created in a P-type substrate. The P-channel transistors are then fabricated inside these N-well regions, while the N-channel transistors are fabricated outside the wells in the P-type substrate. In tawin-well or twin-tub CMOS process, both N-wells and P-wells are created in the substrate. N-channel transistors are then fabricated in the P-wells, and P-channel transistors in the N-wells.

As we will see later, the complimentary behavior allows CMOS circuits to exhibit much lower power consumption than NMOS circuits (i.e. all N-Channel transistors) or PMOS circuits (i.e. all P-Channel transistors). For this reason, CMOS circuits are the technology of choice for most modern, large-scale digital circuits.


5-6

Logic Circuits


5-7

Transistors can be interconnected into circuits that perform logical operations (such as control circuits) and arithmetic operations (such as binary mathematics). For example, a microprocessor contains circuitry that performs a wide variety of logical and mathematical functions. In general, the more transistors a chip contains, the “smarter” it is. The purpose of this section is to examine a few basic logic circuits for illustration.


5-8

CMOS Inverter truth table

logic circuit symbol +V cc

o

V in

•

V out o V in

•

V in

V out

+Vcc

0V

(logic 1)

(logic 0)

0V

+Vcc

(logic 0)

(logic 1)

β p

•

+V cc

+V cc

• • •

• • •

• •

V out

transistor circuit β n

• V in

V out

+ V cc

• •

S •

G•

D•

•

•D

G

•

S

•

• • •

N+

P+

P

V out

V out

•

2 2 Pdynamic = CV cc f tog = CV cc K Df clk

+V cc

V out N+

• •

transfer function current

P+

N 0V

V in


5-9

CMOS Inverter - Layout P-channel transistor

poly-Si (gates)

Vcc

N-channel transistor

gnd

metal-1 via / contact P source/drain (aka. diffusion) N-well N source/drain (aka. diffusion)


source: Principles of CMOS VLSI Design, Weste & Eshraghian, 1993, AT&T.

5 - 11

This is a circuit layout or cell layout for a CMOS inverter (in an N-well CMOS process). It is a top view, showing the layout of the various regions and components of this logic gate. There are design rules governing the layout. Considering poly-Si for example, there are design rules specifying the minimum poly line width, minimum pitch (spacing) between poly lines, minimum pol y-to-contact distance, etc. The design rules come from the capabilities of the CMOS fabrication process, for example the critical dimension (CD) that can be resolved by the lithography and etch processes, the tolerance in aligning one litho layer to another, the thermal budget and the amount of lateral diffusion that takes place in the doped (implanted) regions, etc.


5 - 12

Aside: Latchup

source: Principles of CMOS VLSI Design, Weste & Eshraghian, 1993, AT&T.


5 - 13

CMOS AND & NAND Gates AND Gate inputs

A

C

B

and C = A B = A B •

output

A

B

C

1

1

1

1

0

0

0

1

0

0

0

0

logic 1 = + V cc logic 0 = 0 volts

+V cc

NAND Gate A

o

B

C

=

A

• o

C

B

o

o

not C = (A and B) = A• B inputs

output

A

B

C

1

1

0

1

0

1

0

1

1

0

0

1


• •

A

B

C

•

5 - 15

Transistors can be interconnected to make AND and NAND (“Not AND”) logic gates. (We will use 2-input gates for example, but these principles can be extended to gates with more inputs.) An AND gate returns a logic 1 only when all of its inputs (in this case A and B) are logic 1; otherwise, its output is logic 0. Thus, the output bit can be calculated by multiplying the two input bits, as shown in the equation and the truth table. Another way to look at it is in Boolean terms, where each input is evaluated as true (1) or false (0), and the output is true only when A and B are true. This is the origin of the term “truth table”. The NAND gate, as the name implies, always returns the opposite (compliment) of what an AND gate produ ces. This can be observed by comparing the two truth tables. The bar in the equation means to take the compliment of the expression underneath. The transistor circuit for a NAND gate is shown. By treating the transistors as switches, similar to the inverter example discussed previously, we can see how this circuit generates the output shown in the truth table. Again, note that this CMOS circuit conducts current between V cc and ground only during the brief transient period while it is switching, and thus consumes very little power.


5 - 16

CMOS NAND Gate – Layout Vcc

P-channel transistors

B A

C (out)

poly-Si (gates) N-channel transistors

metal-1 via / contact P source/drain (aka. diffusion)

gnd

N source/drain (aka. diffusion) source: Introduction to VLSI Design, Eugene D. Fabricius. McGraw-Hill, 1990. Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

5 - 17

This is a cell layout for a two-input CMOS NAND gate. The color scheme has changed slightly from that used previously for the inverter layout, because this cell was created by a different layout tool. Also, the MOSFET and contact regions are highlighted, making th em easier to identify.


5 - 18

CMOS OR & NOR Gates OR Gate inputs

A

C

B

or C = A B=A+B

output

A

B

C

1

1

1

1

0

1

0

1

1

0

0

0

NOR Gate

+V cc

A

o

B

C

=

A B

C =not (A or B) = A + B inputs

o

•

C A

B

o

•

o

output

A

B

C

1

1

0

1

0

0

0

1

0

0

0

1


•

C

• 5 - 19

Transistors can be interconnected to make OR and NOR (“Not OR”) logic gates. An OR gate outputs a 1 whenever one or more of its inputs is 1. In this case, the output is 1 when A or B is 1. In Boolean terms, the output is true (1) when one or both of the inputs, A or B, is true. The NOR gate, as the name implies, produces output that is opposite (complimentary) to the OR gate. The transistor circuit for a NOR gate is shown for example.


5 - 20

CMOS NOR Gate - Layout

poly-Si (gates) metal-1 via / contact P source/drain (aka. diffusion) N source/drain (aka. diffusion) source: Introduction to VLSI Design, Eugene D. Fabricius. McGraw-Hill, 1990. Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

5 - 21

NOR gate layout.


5 - 22

Exercise: 3-Input NAND Gate 1.

Draw the truth table for a 3-input NAND gate.

2.

Draw the circuit symbol.

3.

Draw the transistor-level circuit for a 3-input CMOS NAND gate. Hint: You will need three N-channel transistors and three P-channel transistors.


5 - 23

Exercise


5 - 24

Exercise: 3-Input NAND Gate - Solution +V cc

A

B

C

Y

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 0

• o

o

o

•

Y

•

A

•

B A B

o

Y

C


C

•

5 - 25

Solution


5 - 26

Example: A Simple Control Circuit

Burglar alarm for a room with one window and one door signal from contact sensor on window frame

window is closed ?

door is closed ?

o

signal to an alarm horn or bell

sound the alarm ?

o

signal from contact sensor on door frame

alarm system is armed ?


signal from a keypad control panel

5 - 27

Other types of basic logic gates exist, besides the five we have studied here (inverter, AND, NAND, OR, NOR); we will not attempt to study them all. Our purpose here is simply to illustrate that transistors can be interconnected to make useful circuits, such as the simple control circuit shown here. It controls a burglar alarm for a room with on e window and one door. The system has three inputs. When an input is “true” or “yes”, it is a assigned a value of logic 1. When it is “false” or “no”, it is logic 0. When the alarm is armed (alarm system is armed? = yes = 1) and both the window and door are closed (window is closed? = door is closed? = yes = 1), both AND gates produce output of 0 and hence the OR gate has output 0 and the alarm is not sounding (sound the alarm? = 0 = no). If either the window or the door (or both) is opened while the alarm is armed, one (or both) of the AND gates will produce an output of 1. This will cause the OR gate to produce output of 1, triggering the alarm. This is certainly not the best burglar alarm in the world! But it illustrates how the basic logic gates we have studied in this module can be used to create digital circuits that perform logical operations. Note that any arithmetic operation is essentially a sequence of logic operations, hence logic circuits can be constructed to perform mathematical calculations as well. Of course, a digital circuit will perform all of these calculations in binary (0’s and 1’s). Any base-10 number can be represented as a binary number, including negative numbers and fractions. And any mathematical operation can be performed on these binary numbers (e.g. addition, subtraction, multiplication, division, etc.).


5 - 28

Exercise: A Decoder Using inverters and AND gates, construct a 2-bit decoder. The circuit has two 1-bit input lines and four 1-bit output lines. For a given combination of inputs, one (and only one) output line will be selected (logic 1) as indicated in the truth table below.

inputs W0 A0 A1

decoder

W1 W2 W3


outputs

A0

A1

W0

W1

W2

W3

0

0

1

0

0

0

0

1

0

1

0

0

1

0

0

0

1

0

1

1

0

0

0

1

5 - 29

This example will come in handy later when we discuss semiconductor memory.

(Aside: If you know how to count in binary, you will recognize this as a 2-bit binary-to-decimal decoder.)


5 - 30

Exercise: A Decoder - Solution A0

A1

•

•

o

o

•

• •

W0

• • •

W1

W2

• •


W3

5 - 31

Note that this can easily be extended to handle more than two inputs. For example, for three inputs (A 0 – A2), we would use three 3 3 inverters along with 2 = 8 AND gates, to decode all 2 = 8 possible combinations of the three inputs. Later, when we discuss semiconductor memory, we will see an example of an 8-bit memory address decoder, which can decode an 8-bit memory address and select one of 28 = 256 unique word lines (memory addresses).


5 - 32

Levels of Abstraction functional blocks/units/modules sub-blocks reg decoder reg

M U X

ALU

reg

logic gates

o

transistor circuits

•

o

o

• • •


5 - 33

The Big Picture: How A Chip Is Born logic design

cell set / custom circuit design •

A

o

B

+V cc

o

•

m rf o

o

•

layout

S

e iv

nd

o

r

start Si

C

chip

w ol F b s a s F e c or P

•

finished wafer

E-Test

to to mask shop

a F

b

transistor

Sort Assembly Class Test

packaged chip

photomask set Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

5 - 35

Memory


5 - 37

Transistors can also be interconnected to form circuits that store bits. In this section, we will study three types of memory: DRAM, SRAM, and Flash EEPROM. Each of these is widely used in a variety of microelectronic devices, including personal computers and mobile / handheld devices.


5 - 38

Memory Storage & Access – The Big Picture address lines (8-bit address = 28 = 256 unique addresses)

word lines (256)

memory array (each cell stores 1 bit)

data / bit lines W0

•

A0 r e d o c e D s s e r d d A

A1 A2 A3 A4 A5 A6 A7

•

W1

BIT CELL

•

BIT CELL

•

•

0

Sense/Write

•

BIT CELL

•

•

BIT CELL

• b5 Sense/Write

•

•

BIT CELL

• b4 Sense/Write

1

•

•

•

b3 Sense/Write

BIT CELL

•

b2 Sense/Write

0

•

BIT CELL

•

BIT CELL

• •

•

•

BIT CELL

• 0

•

•

BIT CELL

•

•

BIT CELL

•

•

0

•

BIT CELL

•

•

0

•

BIT CELL

•

•

b6

Sense/Write

•

BIT CELL

•

b7

•

•

BIT CELL

• these cells are read from / written to (in parallel)

•

•

W255

this address (word line) is selected

•

•

BIT CELL

• • b1 Sense/Write

1

• •

1

b0 Sense/Write

R/W

0 0 0

I/O data lines (8 bits = 1 byte) Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

read / write sense amp circuitry

5 - 39

In addition to logic, transistors can also be used to make memory. Logic manipulates and transforms data, whereas memory stores data for future use. Each plays a vital role in modern microelectronics; for example, a microprocessor contains large amounts of both. Before discussing different types of memory, let’s understand how a semiconductor memory works in general. We will use the simple memory scheme shown here for illustration. A memory is an array of memory cells, each of which stores one bit. Each cell is a transistor circuit. (Later, we will study three memory cells: the DRAM cell, the SRAM cell, and the Flash EEPROM cell.) Reading a byte from memory:

A binary address is placed on the address lines; in this example, an 8-bit address is used and hence there are 8 address lines A0 – A7 . The address decoder is an 8-bit decoder (analogous to the 2-bit decoder we designed earlier as an exercise). It accepts the binary address as input and selects the appropriate output line or word line. Note that, with 8 bits (one byte), it is possible to specify 2 8 = 256 unique addresses (i.e. 256 word lines). A voltage is placed on the selected word line, thus accessing each cell in that line simultaneously. In this example, there are 8 cells on each word line. Each sense amp (a.k.a. read/write circuit cell then places the bit it is storing (a 0 or 1) on its bit line (aka. data line). A ) is used to sense and amplify the bit so it can be used by the outside world. Note that all 8 bits are read out simultaneously, as one byte (a.k.a. one “word”). Note also that the bit lines are shared among word lines, but only one word line will be active at any given time, and only those cells will use the bit lines. Storing (writing) a byte into memory:

The byte to be stored is placed on the bit lines. These bits are sensed and amplified by the sense amps. The address to which the byte should be stored is placed on the address lines, and the address decoder selects the corresponding word line. This activates the memory cells on that word line (only), and they accept and store the bits present on the bit lines. How the cell stores a bit will be explained next; it depends o n what kind of cell is being used. We will study three types of memory cells: a DRAM cell, an SRAM cell, and a Flash EEPROM cell. Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

5 - 40

DRAM Cell • • b i t

word line

• •

access transistor

storage capacitor

l i n e

• •

•

this row address is selected

•

this byte is read or written

0

•

•

no charge

b i t

•

•

• •

•

access transistor

storage capacitor

l i n e

• •

•

word line

0

•

• •

• •

no charge

•

0

•

• •

• •

no charge

•

•

• •


0

•

•

no charge

•

•

•

charge

1

•

•

•

•

0

•

• •

• •

no charge

•

• •

• •

• •

charge

1

charge

1 5 - 41

DRAM Cell – Trench Capacitor source (bit line)

•

gate (word line)

plate bias

•

•

ILD

N+

N+ MOS capacitor

Planar Capacitor

P

source (bit line)

•

gate (word line)

plate bias

•

•

ILD

N+

N+

poly-Si trench oxide

Trench Capacitor MOS capacitor

P Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

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A popular design of the DRAM cell uses a trench capacitor . A deep, narrow trench is etched into the silicon. The sidewalls of this trench are oxidized (forming the dielectric for the capacitor) and then the trench is filled with poly-Si to form th e other “plate” of the capacitor. The primary advantage of this design is that it uses less silicon surface area than the planar capacitor. This allows for a denser DRAM, storing more bits per unit area. This means the DRAM chip can be smaller (more die per wafer), for improved yield and lower manufacturing cost. The main tradeoff is manufacturing complexity – there can be man y technical challenges in the trench fabrication module, especially as the trend continues toward narrower and deeper trenches (higher aspect ratio) and more stringent charge storage requirements. Aside – Some Technical Details: In a real DRAM cell, the “plate bias” is usually held at some positive supply voltageV (DD), contrary to the previous schematic in which it is shown going to ground. This biases the capacitor into inversion; i.e. a depletion region exists in the substrate and an inversion layer of electrons is present at the oxide interface. Whether the capacitor stores a 0 or a 1 is then determined by the sense amp circuitry according to whether (and how much) charge flows into or out of the storage capacitor when it is accessed. This level of technical detail is beyond the scope of this course; our pu rpose here is simply to demonstrate that a DRAM cell stores a bit in the form of charge on a storage capacitor, and that different strategies exist for capacitor fabrication (e.g. planar vs. trench).


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SRAM Cell +V cc

b

b

•

’

inverter

inverter

access transistor

o

o

•

•

•

access transistor

•

•

•

•

•

bit line

•

•

word line

• b

b

•

1

o

1 0

o0

•

storing a 1 Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

’

b

b

•

0

o

0 1

o1

’

•

storing a 0 5 - 45

SRAM Cell - Layout

inverter

inverter

poly-Si (gates) metal-1 via / contact

access transistors

P source/drain (aka. diffusion) N-well N source/drain (aka. diffusion) source: Principles of CMOS VLSI Design, Weste & Eshraghian, 1993, AT&T. Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

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VDD and Layout for a “6T” (6-Transistor) SRAM cell (in an N-well CMOS process). (The supply voltage in this diagram is called ground is called V ss .)


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Flash EEPROM Cell Vt

Gate (V)

Program Erase 12 -10

Read 5

Source (V)

0

5

0

Drain (V)

5

Float

1

0

Level 1

1

Level 0

Conventional Flash Cell

Vt 00

Level 3

01

Level 2

10

Level 1

11

Level 0

StrataFlashTM Cell (2 bit/cell)


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Aside: The Memory Hierarchy of a PC closer to processor

er w lo ve i s r, ns e e ap exp e ch re , o er m s , n r e de sa t , f , ity c y t a p ci a a rc ap e c g r al r la le sm

registers

internal to the microprocessor, made from basic logic gates (flip-flops), contains data the processor is currently using (e.g. operands for a calculation)

cache

L0 L1 L2

SRAM, internal to the microprocessor, contains data/instructions the processor thinks it will need again soon

Main Memory

Hard Drive External Memory

(Tape, Floppy Disk, Diskette, CD, etc.)

DRAM, external to the processor but on the motherboard, contains data/instructions for operating system and programs that are running not semiconductor memory (magnetic storage), not volatile, external to the motherboard, permanently stores the operating system, programs, files, etc. not semiconductor memory (magnetic or optical storage), not volatile, portable, external to the PC

farther from processor


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Transistor Scaling & Technology Trends


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We have discussed how MOSFETs can be used to build logic and memory circuits, and some of the important circuit performance characteristics and trade-offs involved. We have also taken a big-picture view of how a large and complex circuit like a microprocessor is made. With this knowledge in hand, we now turn our attention to the topic of transistor scaling (methodologies for making smaller transistors and denser circuits) and a discussion of the technology trends in the semiconductor industry. It is important to understand the methods, challenges, and trade-offs involved in advancing the state of semiconductor technolog y.


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Optional Topic: Transistor / IC Scaling same different

Attribute or Feature

Symbol

Channel length

L

Channel width

Z

Device area Packing density (devices per u. area) S/D junction depth

Full (Constant Field) Scaling factor

(s > 1) 1/s 1/s 1/s2 s2

xj

1/s

Gate oxide thickness

t OX

1/s

Gate oxide capacitance

C OX

1/s

Gate oxide capacitance per unit area

C’OX

s

Comments: Scale all physical device dimensions (L, Z, tOX, xj, etc.) AND all voltages (VDD, VDS, VGS, VT) uniformly by 1/s to produce a smaller transistor with the same large-channel behavior. Strategy:

Scale down all physical device dimensions by 1/s. Scale down all physical device dimensions by 1/s. Area = ZL, scales down by 1/s 2. Die size reduced – improves yield and number of die on the wafer. Scale down all physical device dimensions by 1/s. Junctions must be made shallower to preserve subgate electrostatics. (Increases source/drain series resistance.) Scale down all physical device dimensions by 1/s.

Gate area (ZL) reduced by 1/s 2 and tOX reduced by 1/s, so COX (=εOXZL/tOX) reduced by 1/s. tOX reduced by 1/s (and gate area ignored), so C’OX (=εOX/tOX) increases by s.

Constant Voltage Scaling factor

(s > 1) 1/s 1/s 1/s2 s2 1/s 1/s

1/s s

Comments: Scale all physical device dimensions (L, Z, tOX, xj, etc.) by 1/s but do NOT scale the voltages (VDD, VDS, VGS, VT), e.g. in order to maintain compatibility with industry standard voltage specs or existing products and applications. Scale down all physical device dimensions by 1/s. Scale down all physical device dimensions by 1/s. Area = ZL, scales down by 1/s2. Die size reduced – improves yield and number of die on the wafer. Scale down all physical device dimensions by 1/s. Junctions must be made shallower to preserve subgate electrostatics. (Increases source/drain series resistance.) Scale down all physical device dimensions by 1/s. (Note: May scale by less if this results in an unacceptably large vertical gate field. Large field increases susceptibility to oxide wearout, hot carrier effects, vertical field mobility degradation, gate leakage, and dielectric breakdown.) Gate area (ZL) reduced by 1/s2 and tOX reduced by 1/s, so COX (=εOXZL/tOX) reduced by 1/s. tOX reduced by 1/s (and gate area ignored), so C’OX (=εOX/tOX) increases by s Strategy:

(chart continued ….) Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham

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The interconnect capacitances tend to be reduced, because the metal-to-metal overlap area and metal sidewall area are reduced. Because the resistance scales up by about the same amount as the capacitance c apacitance scales down, the RC product in principle remains about the same *. This implies that ICs will become progressively more RC limited from one generation to the next -- i.e. the transistor switching speed is improving while the interconnect RC delay remains roughly the same. As discussed previously, this has resulted in the industry’s migration to copper interconnects (lower resistance) and low-k interlayer dielectrics (lower capacitance) to reduce RC delay and take full advantage o f the transistor performance improvements. improvements.

*

For global wires (long wires that run across all or most of the chip), the RC delay tends to become worse from one microprocessor generation to the next because the chip size tends to increase as discussed previously, making global lines longer.

Introduction Introduction to Semiconductor Semiconductor Device Physics / Small Circuits Circuits / rev 4.3 Tom Cunningham Cunningham

5 - 62

Transistor / IC Scaling (cont.) same different

Attribute or Feature

Contact/via area

Symbol

Full (Constant Field) Scaling factor

(s > 1) 1/s2

Contact/via current density

s

Contact/via resistance

s2

Contact/via voltage drop

s

Comments: Scale all physical device dimensions (L, Z, tOX, xj, etc.) AND all voltages (VDD, VDS, VGS, VT) uniformly by 1/s to produce a smaller transistor with the same large-channel behavior. Strategy:

Reduction of each side of contact/via “window” opening by 1/s results in a reduction in area of 1/s 2. The current (I D) scales as 1/s and the contact area scales as 1/s 2, therefore the current density scales as s (J = I/A). Contact/via “window” opening reduced by 1/s2 results in resistance increase as s 2. (neglecting any change in via/contact height/depth that may result from changes in ILD thickness). The current (I D) scales as 1/s but the contact/via resistance scales as s 2, hence the voltage drop across the contact/via scales by s (V = IR) – opposite the direction of the voltage (VDD) scaling! Larger voltage drop across smaller contacts leads to reliability concerns.


Constant Voltage Scaling factor

(s > 1) 1/s2 s3 s2

s3

Comments: Scale all physical device dimensions (L, Z, tOX, xj, etc.) by 1/s but do NOT scale the voltages (VDD, VDS, VGS, VT), e.g. in order to maintain compatibility with industry standard voltage specs or existing products and applications. Reduction of each side of contact/via “window” opening by 1/s results in a reduction in area of 1/s 2. The current (ID) scales as s and the contact area scales as 1/s 2, therefore the current density scales as s 3 (J = I/A). Reduced contact/via “window” opening (neglecting any change in via/contact height/depth that may result from changes in ILD thickness). Strategy:

The current (ID) scales as s and the contact/via resistance scales as s 2, hence the voltage drop across the contact/via scales as s3 (V = IR). Larger voltage drop across smaller contacts leads to reliability concerns.

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The contact/via resistance also scales up, due to the reduction of the co ntact/via cross-sectional area. Therefore, the industry is moving toward copper-filled vias, which have a lower resistance than traditional tungsten vias. Using copper vias in combination with copper metal lines results in a large reduction in overall interconnect resistance.

For a broader and more indepth summary of IC scaling trends and challenges, the interested reader is referred to chapter 1 of the text: Digital Systems Engineering, by W.J. Dally and J.W. Poulton, Cambridge U. Press, 1998. Also, chapter 5 of the text: Operation and Modeling of the MOS Transistor , by Y.P. Tsividis, McGraw-Hill, 1987.


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Pulling It All Together: Intel ® Microprocessors 4004

386

Pentium® II

Pentium® 4

(note: not to scale wrt. one another)


5 - 65

Intel® Microprocessors & Moore’s Law P2

10,000,000

PPro PMMx every 2 yrs double every year

every 1.5 yrs

80486

80486

P1 every 2.5 yrs

80486

1,000,000

s r o t s i s n a r T f o r e b m u N

80386 80186 80286 100,000

8088 8086

10,000

8085 8008

8080

4004

1,000 Jan-70

Jan-72

Jan-74

Jan-76

Jan-78

Jan-80

Jan-82

Jan-84

Jan-86

Jan-88

Jan-90

Jan-92

Jan-94

Jan-96

Jan-98

Intro Date


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SemiconductorDevicePhysics_4pt3 [Sze]

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