Sect-7

Section 7: UPS System Control

Chapter 1 - UPS System Control Principles

1.1 Introduction ........................................ .............................................................. ............................................ ................................ .......... 7-1 Chapter 2 - High Voltage Interface Board

2.1 Chapter overview ........................................ ............................................................. ........................................... ........................ .. 7-5 2.2 General description ........................................ .............................................................. ........................................... ..................... 7-5 2.3 Detailed description ........................................................... ................................................................................. ........................ 7-7 2.3.1 X1 Low Low voltage signals to/from the UPS Logic Board. Board. .............. 7-7 2.3.2 X2 (Page (Page 2) – DC bus bus (battery) voltage sense ............................. 7-7 2.3.3 X3 (Page 2) – Rectifier input voltage sense ............................... ................................. .. 7-7 2.3.4 X4 (Page 2) – UPS output voltage sense ..................................... ..................................... 7-7 2.3.5 X5 (Page (Page 2) – Inverter output voltage sense ................................ ................................ 7-7 2.3.6 X6 (Page 2) – Bypass voltage sense ........................................... ............................................. 7-8 2.3.7 X7 (Page 1) – Power switch auxiliary auxiliary contacts ........................... ........................... 7-8 2.3.8 X8 (Page 1) – Interface to external connection block .................. .................. 7-8 2.3.9 X9 (Page (Page 2) – Battery cabinet temperature .................................. .................................. 7-9 2.3.10 X10 (Page 2) – Input air temperature sensor ............................. ............................. 7-9 2.3.11 X11 (Page 2) – Inverter output output air temperature sensor .............. 7-9 2.3.12 X12 X12 (Page 2) – Transformer cubicle air temperature sensor ..... 7-9 2.3.13 X13 (Page 1) – Inverter assembly thermostats thermostats ........................ ........................ 7-10 2.3.14 X14 (Page 1) – Not Not in use ........................................................ ........................................................ 7-10 2.3.15 X15 (Page 1) – Battery fuse monitor ....................................... ....................................... 7-10 2.3.16 X16 (Page 1) – Not in use (linked out) out) .................................... .................................... 7-10 2.3.17 X17 (Page 1) – Not in use (linked out) out) .................................... .................................... 7-10 2.3.18 X18 (Page 1) – Rectifier current sensing ................................. ................................. 7-10 2.3.19 X19 (Page 1) – Output Output current monitoring W-ph .................... 7-10 2.3.20 X20 (Page 1) – Output current monitoring V-ph ..................... ..................... 7-10 2.3.21 X21 (Page 1) – Output current monitoring U-ph ..................... ..................... 7-11 2.3.22 X22 (Page 1) – Battery current monitoring ............................. ............................. 7-11 2.3.23 X23 (Page 1) – Inverter current monitoring U-ph ................... ................... 7-11 2.3.24 X24 (Page 1) – Inverter current monitoring V-ph ................... ................... 7-11 2.3.25 X25 (Page 1) – Inverter current monitoring W-ph .................. 7-11 2.3.26 X26 (Page 1) – Not Not in use ........................................................ ........................................................ 7-11 2.3.27 X27 (Page 1) – Not Not in use ........................................................ ........................................................ 7-11 2.4 Summary information ........................................................... ............................................................................. .................. 7-12 Chapter 3 - UPS Logic Board (4550007 H)

3.1 Chapter overview ........................................ ............................................................. ........................................... ...................... 7-13 3.2 General description ........................................ .............................................................. ......................................... ................... 7-13 3.2.1 Circuit board board functions ............................................. .............................................................. ................. 7-13 3.2.2 Input/Output connections connections ........................................................... ........................................................... 7-14 3.2.3 Block Diagram ...................................................... ........................................................................... ..................... 7-20

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i

SECTION 7 - UPS Sy s t em Co n t r o l

7200 Ser i es UPS Ser v i c e Man u al

3.3 Detailed circuit description ........................................ .............................................................. ............................ ...... 7-23 3.3.1 Introduction ...................................................... ............................................................................. .......................... ... 7-23 3.3.2 Basic microcontroller system ................................... ..................................................... .................. 7-24 3.3.3 Data bus, address bus and control bus buffers ........................... ........................... 7-26 3.3.4 Ni-Cad Battery back-up controller ................................. ............................................. ............ 7-26 3.3.5 Reset generator ............................................... ..................................................................... ............................ ...... 7-27 3.3.6 System System RAM and ROM memory addressing ............................ ............................ 7-28 3.3.7 Basic system control logic (D88) .......................................... ............................................... ..... 7-29 D88 Status Status signals to processor processor system ........................... ........................... 7-31 D88 Reset circuit [RES_EXT> ........................................ ........................................ 7-32 Major control signal outputs outputs ............................................ ............................................ 7-32 Load transfer control control ........................................................ ........................................................ 7-34 3.3.8 CAN bus bus communications drivers and control logic ................. 7-35 3.3.9 Real-time clock (RTC) .............................................. ............................................................... ................. 7-35 3.3.10 Data bus buffers ‘chip select’ decoding ................................... ................................... 7-37 3.3.11 Data bus input buffers ............................................................ .............................................................. .. 7-38 3.3.12 Data bus output buffers .......................................................... ............................................................ .. 7-45 3.3.13 Frequency sensing and control signals .................................... .................................... 7-55 Frequency control principles ............................................ ............................................ 7-55 Frequency sync sync control and operation operation ............................. ............................. 7-56 Non-Sync detection and alarm ......................................... ......................................... 7-58 External ‘sync inhibit’ ..................................... ...................................................... ................. 7-58 3.3.14 Analogue signal processing ............................................ ..................................................... ......... 7-59 Bypass voltage signal signal processing ..................................... ..................................... 7-59 Inverter voltage voltage sensing ................................................... ................................................... 7-60 Battery (bus) voltage sensing ........................................... ........................................... 7-61 Battery current sensing .......................................... .................................................... .......... 7-61 Output voltage sensing ................................................... ..................................................... .. 7-62 Output current sensing ..................................................... ..................................................... 7-63 Analogue signal monitoring multiplexers 7-64 3.3.15 Power Power supplies ....................................... ............................................................. .................................. ............ 7-65 3.3.16 External communications .............................. ..................................................... ........................... .... 7-67 3.3.17 On board 7-segment indications summary summary .............................. .............................. 7-68 3.4 Summary information ........................................................... ............................................................................. .................. 7-72 Chapter 4 - UPS Logic Board (4550004 E)

4.1 Chapter overview ........................................ ............................................................. ........................................... ...................... 7-75 4.2 General description ........................................ .............................................................. ......................................... ................... 7-75 4.2.1 Circuit board board functions ............................................. .............................................................. ................. 7-75 4.2.2 Input/Output connections connections ........................................................... ........................................................... 7-76 4.2.3 Block Diagram ...................................................... ........................................................................... ..................... 7-81 4.3 Detailed circuit description ........................................ .............................................................. ............................ ...... 7-84 4.3.1 Introduction ...................................................... ............................................................................. .......................... ... 7-84 4.3.2 Basic microcontroller system ................................... ..................................................... .................. 7-85 4.3.3 Data bus, address bus and control bus buffers ........................... ........................... 7-88 4.3.4 Ni-Cad Battery back-up controller ................................. ............................................. ............ 7-88 4.3.5 Reset generator ............................................... ..................................................................... ............................ ...... 7-89 4.3.6 System System RAM and ROM memory addressing ............................ ............................ 7-90

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SECTION 7 - UPS Sy s t em Co n t r o l

4.3.7 Basic system control logic ............................................ ......................................................... ............. 7-92 D22 Functional Functional description .............................................. .............................................. 7-92 D23 Functional Functional description .............................................. .............................................. 7-94 4.3.8 CAN bus bus communications drivers and control logic ................. 7-96 4.3.9 Real-time clock (RTC) .............................................. ............................................................... ................. 7-96 4.3.10 Data bus buffers ‘chip select’ decoding ................................... ................................... 7-98 4.3.11 Data bus input buffers ............................................................ .............................................................. .. 7-99 4.3.12 Data bus output buffers .......................................................... .......................................................... 7-105 4.3.13 Frequency sensing and control signals .................................. .................................. 7-113 Frequency control principles .......................................... .......................................... 7-113 Frequency sync sync control and operation operation ........................... ........................... 7-114 Non-Sync detection and alarm ....................................... 7-116 External ‘sync inhibit’ ..................................... .................................................... ............... 7-116 4.3.14 Analogue signal processing ............................................ ................................................... ....... 7-117 Bypass voltage signal signal processing ................................... ................................... 7-117 Inverter voltage voltage sensing ................................................. ................................................. 7-118 Battery (bus) voltage sensing ......................................... ......................................... 7-119 Battery current sensing .......................................... .................................................. ........ 7-119 Output voltage sensing ................................................... ................................................... 7-120 Output current sensing ................................................... ................................................... 7-121 Analogue signal monitoring multiplexers ...................... 7-122 4.3.15 Power Power supplies ....................................... ............................................................. ................................ .......... 7-123 4.3.16 External communications .............................. ..................................................... ......................... .. 7-125 4.3.17 On board 7-segment indications summary summary ............................ ............................ 7-126 4.4 Summary information ........................................................... ........................................................................... ................ 7-130 Chapter 5 - Operator Logic Board

5.1 Chapter overview ........................................ ............................................................. ......................................... .................... 7-133 5.2 General description ........................................ .............................................................. ....................................... ................. 7-133 5.2.1 Circuit board board functions ............................................. ............................................................ ............... 7-133 5.2.2 Input/Output connections connections ......................................................... ......................................................... 7-134 5.2.3 Block Diagram ...................................................... ......................................................................... ................... 7-135 5.3 Detailed circuit description ........................................ .............................................................. .......................... .... 7-137 5.3.1 Introduction ...................................................... ............................................................................. ......................... 7-137 5.3.2 Basic microcontroller system ................................... ................................................... ................ 7-138 5.3.3 Data bus, address bus and control bus buffers ......................... ......................... 7-139 5.3.4 Reset generator ............................................... ..................................................................... .......................... .... 7-140 5.3.5 Alarm buzzer ......................................................... ............................................................................ ................... 7-140 5.3.6 Address decoding – D10 ............................................... .......................................................... ........... 7-140 5.3.7 System System RAM and ROM memory addressing .......................... .......................... 7-141 5.3.8 Interface to the Operator Control Control Panel ................................... ................................... 7-142 5.3.9 Interface to the CAN Bus ..................................... ......................................................... .................... 7-143 5.3.10 Serial (modem) Interface ...................................... ....................................................... ................. 7-144 5.3.11 RS232 RS232 & RS485 Interface .......................................... ..................................................... ........... 7-144 5.3.12 Power Supply ..................................................... ......................................................................... .................... 7-145 5.4 Summary information ........................................................... ........................................................................... ................ 7-146


iii

SECTION 7 - UPS System Control

7200 Series UPS Service Manual

Chapter 6 - Operator Control Panel

6.1 Section overview .................................................................................. 7-149 6.2 General description ............................................................................... 7-149 6.2.1 Circuit board functions ............................................................ 7-149 6.2.2 Input/Output connections ......................................................... 7-149 6.3 Detailed circuit description .................................................................. 7-150 6.3.1 LED Display indication ........................................................... 7-150 6.3.2 Operator input switches ........................................................... 7-151 6.3.3 LCD Display Panel .................................................................. 7-151 Chapter 7 - System software

7.1 Introduction .......................................................................................... 7-153 7.2 Program structure and execution .......................................................... 7-153 7.2.1 Initialisation/Reset ................................................................... 7-156 7.2.2 Rectifier ON/OFF subroutine .................................................. 7-158 7.2.3 Inverter OFF/ON Sub-routine .................................................. 7-160 7.2.4 Frequency synchronisation control .......................................... 7-162 7.2.5 Battery circuit breaker control ................................................. 7-168 7.2.6 Low Battery Pre-alarm ............................................................. 7-172 7.2.7 Battery undervoltage trip threshold ......................................... 7-174 7.2.8 Battery Boost charge ................................................................ 7-176 7.2.9 Battery Test .............................................................................. 7-178 7.2.10 Load transfer control logic ..................................................... 7-180

iv



Chapter 1 - UPS System Control Principles

1.1

Introduction Previous descriptions in this manual show that the UPS can broadly be divided into three major areas, each of which is largely independently controlled – i.e: • • •

the rectifier – (See section 4) the inverter – (See section 5) the static switch – (See section 6)

However, a study of these sections show that there is also a degree of commonality concerning certain of their control functions; for example, the way in which their required analogue sense signals are processed and applied, and their operating parameters set from the Operator Control Panel. The chapters in this section (7) describe those boards concerned with servicing the control requirements of all three of the major power sections mentioned above, and as such are the boards that bring together the control functions of the entire UPS system – hence the section title UP S System Control. A block diagram showing the relationship between the System Control boards and the other UPS control areas is shown in Figure 7-1. High Voltage Interface Board

Analogue signal processing. The High Voltage Interface Board is responsible for processing the analogue sense signals obtained from various parts of the UPS power sections – as illustrated in Figure 7-1. It attenuates, and where necessary isolates, the sensed signals to levels acceptable to the low voltage operating environment of the other control boards, and in certain instances also provides a means of signal calibration. The board’s output are then passed to the major control logic boards via the UPS Logic Board, which is at the heart of the System Control function.

Digital signal processing. This board also monitors various digital status signals and passes them once again to the UPS Logic Board, where they are used by the decision-making processes in its microcontroller’s software. For example, Figure 7-1 shows inputs from the power switch auxiliaries; but not shown are various external inputs from circuits such as the Emergency Stop facility, battery cabinet thermostats etc. Operator Control Panel & Operator Logic Board

These two boards provide the digital interface between the Operator and the UPS Logic Board and permit two-way data communication – i.e. metering data generated on the UPS Logic Board are processed on the Operator Logic Board and then presented to the Operator Control Panel; conversely, parameter settings and manual control inputs entered at the Operator Control Panel are passed through the Operator Logic Board processing circuits to the UPS Logic Board where they impinge on the microcontroller’s decision-making operation.

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7-1

SECTION 7 - UPS System Control CHAPTER 1 - UPS System Contr ol Princ ipl es


Figure 7-1: UPS Control system block diagram

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7-2

d e r g a a o t l B o e V c a h f g r i e H t n I

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l o r t n o l C e r n o a t P a r e p O

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Alarm Interface Board

Several forms of Alarm Interface Board are available to allow remote indication of the alarms generated on the UPS Logic Board (refer to the Options Section of this manual). These boards also permit the connection of certain basic external controls; such as on-generator, sync inhibit, second stage current limit etc. UPS Logic Board

As is evident from reading the earlier part of this chapter, the UPS Logic Board is central to the whole System Control function. This board, which is micro-controller driven, accepts various analogue and digital inputs from the High Voltage Interface Board, Operator Control Board and Alarm Interface Board (optional) and provides the necessary control and ala rms signals used by the remainder of the UPS control areas. It also monitors various alarm and status signals from the rectifier, inverter and static switch control sections and produces appropriate alarms and control logic signals. The board is software-driven and a description of the software functions and flowcharts are provided at the end of this section (see Chapter 7). In a 1+1 configured system the UPS Logic Board is also fed with various control and status signals from the Parallel Logic Board pertaining to the parallel-control functions (See section 8).

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7-4


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Section 7:

Chapter 2 - High Voltage Interface Board

2.1

Chapter overview This chapter contains a circuit description of the High Voltage Interface Board used across the whole model 7200 Series UPS range and should be read in con junction with circuit diagram SE-4590054-O (2 pages). Signal annotations shown on the circuit diagrams are shown in italics in the following text – e.g. VINV_A.

2.2

General descri pti on The purpose of this board is to provide an interface between the high voltage environments of the UPS power circuitry and the low voltage environment of the system control boards. The high voltage sense signals taken from various parts of the power circuitry are therefore attenuated on this board before being applied to their appropriate control circuits. In addition to providing signal attenuation the board also contains calibration facilitates for those signals which are power-related. This allows the board to be used across the entire model range providing the calibration links are set appro priately. All the low-voltage signals are connected to the U PS Logic Board via socket X1 and ribbon cable W8: the remaining IDC connectors (X2 to X27) carry the high voltage signals. Table 7-1on the following page provides an overview of each connectors’ function and this is followed by a more detailed circuit description. Power supplies

The ±12V control power rails required by the board’s op-amps are obtained from the UPS Logic Board and connected via X1 pins 1-12 as shown on the circuit diagram page 2.

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SECTION 7 - UPS System Control CHAPTER 2 - High Voltage Interface Board


. Table 7-1: Connector summary

7-6

X1

Low voltage signals to/from the UPS Logic Board.

X2

DC bus (battery) voltage sense inputs.

X3

Rectifier input voltage sensing inputs

X4

UPS output voltage sensing inputs

X5

Inverter output voltage sensing inputs

X6

Bypass voltage sensing inputs

X7

Power switch auxiliary contacts

X8

Interface to customer connection block X8

X9

Battery cabinet temperature

X10

Input air temperature sensor inputs

X11

inverter output air temperature sensor inputs

X12

Transformer cabinet air temperature sensor inputs

X13

Inverter assembly thermostats (n/c)

X14

Not in use

X15

Battery fuse monitor

X16

Not in use (linked out) – inverter fuse fail

X17

Not in use (linked out) – rectifier fuse fail

X18

Rectifier input current monitor

X19

Output current monitoring W-ph

X20

Output current monitoring V-ph

X21

Output current monitoring U-ph

X22

Battery current monitoring

X23

Inverter current monitoring U-ph (12 pulse inverter only)

X24

Inverter current monitoring V-ph (6 pulse & 12 pulse inverter)

X25

Inverter current monitoring W-ph (6 pulse & 12 pulse inverter)

X26

Not in use – 12 pulse rectifier DC current ½ bridge

X27

Not in use – 12 pulse rectifier DC current ½ bridge

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2.3

SECTION 7 - UPS System Control CHAPTER 2 - High Volt age Interfac e Board

Detailed descrip tio n The remainder of this chapter contains a detailed description of the circuits associated with each of the above connectors.

2.3.1

X1 Low voltage sign als to/from the UPS Log ic Board. X1 carries various signals between the High Voltage Interface Board and the UPS Logic Board, each of which is described in detail below. It also carries ±12V power supplies from the UPS Logic Board to the High Voltage Interface Board to provide it with general control power supply rails and also power the DCCT devices used to monitor the battery current and inverter output current.

2.3.2

X2 (Page 2) – DC bu s (battery ) vol tage sens e The DC Bus (battery) voltage is monitored at connector X2, attenuated by N4d and connected to the UPS Logic Board via X1-27. The attenuation factor is ap proximately 136:1 – i.e. V_B has a sensitivity of approximately 7.3mV per V(battery) and is therefore approximately 3.255Vdc. at a nominal float charge of 446V.

2.3.3

X3 (Page 2) – Rectifier input volt age sense The input mains line voltage is connected to connector X3, attenuated by three sections of N4 and connected to the UPS Logic Board via X 1 terminals 24,25,26. Each section of N4 monitors the input voltage on a line-to-line basis; for example N4a inputs are connected to the input U (Vrec-A) and V ( Vrec-B) phases. The attenuation factor is approximately 75:1 – i.e. VREC_AB has a sensitivity of ap proximately 13.3mV per Vl-l (input volts) and therefore equals 5.8Vrms (15V p-p) when the input mains voltage is at a nominal 400Vac. Note: the input voltage is applied to X3 only when the input power switch Q1 is closed and the main input power fuses are healthy.

2.3.4

X4 (Page 2) – UPS ou tpu t vol tage sens e The UPS output voltage is connected to connector X4, attenuated by three sections of N3 and connected to the UPS Logic Board via X1 terminals 21,22,23. Each section of N3 monitors the output voltage on a line-to-neutral basis; for example N3a inputs are connected to the output neutral ( Vout-0) and U phase (Vout-A). The attenuation factor is approximately 100:1 – i.e. VO_A has a sensitivity of approximately 10mV per Vl-n (output) and therefore equals 2.2V rms (8V p-p) when the UPS output voltage is at a nominal 220Vac. Note: the output voltage is connected to X4 from the ‘live’ side of the output power switch Q4 and is present when the inverter output contactor is closed (load on inverter) OR the bypass static switch is closed (load on bypass) but not when the load is running on the maintenance bypass and the UPS is shut down.

2.3.5

X5 (Page 2) – Invert er ou tp ut voltag e sens e The inverter output voltage is connected to connector X5, attenuated by three sections of N2 and connected to the UPS Logic Board via X1 terminals 18,19,20. Each section of N2 monitors the inverter voltage on a li ne-to-neutral basis; for example N2a inputs are connected to the inverter neutral ( Vinv-0) and U phase (Vinv-A). The attenuation factor is approximately 100:1 – i.e. VINV_A has a sensitivity of approximately 10mV per Vl-n (inverter) and therefore equals 2.2V rms (8V p-p) when the inverter voltage is at a nominal 220Vac.

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7-7



Note: the inverter voltage is connected to X5 from the junction of the output transformer and inverter output contactor and is present only when the inverter is operating. When the inverter output contactor is closed (load on inverter) the voltage applied to X5 is identical to the output voltage sense signals applied to X4 (see above) – these two signal groups can therefore be considered as monitoring either side of the inverter output contactor.

2.3.6

X6 (Page 2) – By pass volt age sens e The UPS bypass voltage is connected to connector X6, attenuated by three sections of N1 and connected to the UPS Logic Board via X1 terminals 15,16,17. Each section of N1 monitors the bypass voltage on a line-to-neutral basis; for example N1a inputs are connected to t he bypass neutral ( Vin-0) and U phase (Vin-A). The attenuation factor is approximately 100:1 – i.e. VI_A has a sensitivity of ap proximately 10mV per Vl-n (bypass) and therefore equals 2.2V rms (8V p-p) when the UPS output voltage is at a nominal 220Vac. Note: the bypass voltage is connected to X4 from the ‘switched’ side of the bypass power switch Q2 and is present when the switch is closed (normal).

2.3.7

X7 (Page 1) – Power swi tch auxiliary contact s Each of the UPS power switches has an auxiliary contact which signals the switch status to the UPS Logic Board via the High Voltage Interface Board Q7. In each case the auxiliary contact is open when the main switch is open, and one side is connected to 0V which is available at X7-5. When the powe r switches are closed they therefore pull their respective status signals at X1 terminals 43-46 to 0V which is interpreted as logic low by the switch monitoring circuits on the UPS Logic Board. Conversely, when the power switches are open the outputs to X1 terminals 43-46 are pulled up to +4.7V and interpreted as logic high.

2.3.8

X8 (Page 1) – Interface to external conn ection blo ck X8 is connected to the customer terminal block (X3) by m eans of the wires identified in Figure 7-1 below: Figure 7-2: Connection between X8 and customer T.B X3 1 2 3 4 5 6 7 8 9 10 11 12

X8 79 81 82 77 76

1 2 3 4 5 6 7

HVI Board

Customer T.B

Battery circuit breaker “enable”

A +5V battery circuit breaker “enable” signal is generated on the UPS Logic Board and connected to the High Voltage Interface Board X1-54 from where it passes directly through X8-2 to the customer T.B. X3-6. From here, the signal is taken via external wiring to the trip circuit on the Battery Circuit Breaker Controller Board. The battery circuit breaker will “trip” if this “enable” supply is removed (note that X8-5 provides the enable signal 0V return path).

7-8

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Battery circuit breaker auxiliary

Auxiliary contacts of the battery circuit breaker ‘make’ the circuit between X8 terminals 4 and 5 (0V) when the breaker is closed. This is fed as a logic low ‘circuit breaker closed’ status signal ( SW_BAT) to the UPS Logic Board via X1-53. When the circuit breaker is open SW_BAT is pulled up to 4.7V due to V11. Emergency Stop

The emergency stop circuit is connected in a ‘normally-closed’ fashion between the customer T.B. terminals 10 and 11. This is connected via wires 76 and 77 to X8 terminals 6 and 7 and then passed to the UPS Logic Board via X1-52 in the form of a logic low ESD signal. When the emergency stop circuit is open, ESD is pulled up to 4.7V due to V10. If the emergency stop facility is not used then a link must be fitted between terminals 10 and 11 on the customer T.B. in order for the UPS to operate. Note: when the emergency stop circuit is activated it shuts down the UPS power sections and isolates the load but does not disconnect the UPS i nput power source (unless an optional external mains circuit breaker is used) therefore the UPS control logic will maintain its operating control power from the input mains supply if it is still available.

2.3.9

X9 (Page 2) – Batt ery cabi net temp eratur e The battery cabinet temperature is monitored by an LM355A temperature sensor which produces a temperature-proportional voltage of 10mV/°C. This is buffered on the High Voltage Interface Board and the resulting T4 signal is connected to the UPS Logic Board via X1-60 and is ultimately used by the Rectifier Logic Board to reduce the regulated battery float charge voltage by 1V per degree centigrade of increase in battery temperature.

2.3.10

X10 (Page 2) – Inpu t air temperatu re sens or The input air temperature is monitored by an LM355A temperature sensor which produces a temperature-proportional voltage of 10mV/°C. This is buffered on the High Voltage Interface Board and the resulting T3 signal is connected to the UPS Logic Board via X1-59. The UPS Logic Board uses this signal to present the actual input cooling air-flow temperature on the appropriate Operator Control Panel metering display window.

2.3.11

X11 (Page 2) – Invert er ou tpu t air temperatu re sens or The inverter output air temperature is monitored by an LM355A temperature sensor which produces a temperature-proportional voltage of 10mV/°C. This is buffered on the High Voltage Interface Board and the resulting T2 signal is connected to the UPS Logic Board cooling air-flow temperature on the appropriate Operator Control Panel metering display window.

2.3.12

X12 (Page 2) – Transf orm er cub ic le air temp eratur e senso r The transformer cubicle air temperature is monitored by an LM355A temperature sensor which produces a temperature-proportional voltage of 10mV/°C. This is buffered on the High Voltage Interface Board and the resulting T1 signal is connected to the UPS Logic Board via X1-57. This signal is ultimately used by the Rectifier Logic Board to reduce the regulated battery float charge voltage by 1V per degree centigrade of increase in transformer temperature (between 25°C and 35°C).

s7-c2.f m5 - Issu e 2 Dated 21/08/97

7-9


2.3.13


X13 (Page 1) – Inverter assembly thermo stats (norm ally closed) The thermostats fitted to the inverter heatsink provide a normally closed circuit between X13 pins 1 and 2, and open only if the temperature rises above 90°C. The TH status signal to the UPS Logic Board via X1-51 is therefore normally low, and rises to 4.7V (due to V9) following an inverter overtemperature event. If an overtemperature condition occurs an “inverter overtemperature” alarm is immediately activated (alarm #34) and the inverter is shut down after one minute if the condition is still present – “overtemp shutdown” (alarm #62) annunciated. The shut-down condition is latched, and the reset button must be pressed to restar t the inverter and cancel the alarm.

2.3.14

X14 (Page 1) – Not in use

2.3.15

X15 (Page 1) – Batt ery fu se mo ni to r The battery fuse contains a micro-switch failure detection device which provides a normally closed circuit between X15 pins 1 and 2. The FUS_BAT status signal to the UPS Logic Board via X1-50 is therefore normally low, and rises to 4.7V (due to V8) following a fuse failure. Alarm #54 annunciates a fuse failure event.

2.3.16

X16 (Page 1) – Not in use (lin ked out)

2.3.17

X17 (Page 1) – Not in use (lin ked out)

2.3.18

X18 (Page 1) – Rectif ier cur rent sensin g Two CTs mounted on the U and V phases of the rectifier assembly provide input current sense signals to X18 pins 1-3. These signals are rectified by V12-V17 and the resulting dc voltage ( IREC_I) is developed across a selectable burden resistor and fed to the UPS Logic Board via X1-35. The appropriate resistance i s selected by a three-position jumper identified as X40 which should be set to position 0-3 in all cases of 30kVA, 40kVA and 60kVA models. This signal is used by the Rectifier Logic Board to limit the maximum input current allowed through the rectifier in order to protect the rectifier SCRs.

2.3.19

X19 (Page 1) – Output current moni tori ng W-ph A CT mounted on the UPS output W phase provides a current sense signal to X19 pins 1-3. The resulting voltage (IO_C) is developed across a selectable burden resistor and fed to the UPS Logic Board via X1-34. The appropriate resistance is selected by a three-position jumper identified as X39 which should be set to position 0-3 in all cases of 30kVA, 40kVA and 60kVA models. This signal is used by the UPS Logic Board to initiate an overload warning (alarm #66) and overload latches (alarm #62), and also to initiate the overload timer.

2.3.20

X20 (Page 1) – Output curr ent mon itor ing V-ph A CT mounted on the UPS output V phase provides a current sense signal to X20 pins 1-3. The resulting voltage (IO_B) is developed across a selectable burden resistor and fed to the UPS Logic Board via X1-33. The appropriate resistance is selected by a three-position jumper identified as X38 which should be set to position 0-3 in all cases of 30kVA, 40kVA and 60kVA models. This signal is used by the UPS Logic Board to initiate an overload warning (alarm #66) and overload latches (alarm #62), and also to initiate the overload timer.

7-10

s7-c2.f m5 - Issu e 2 Dated 21/08/97


2.3.21


X21 (Page 1) – Output curr ent mon itor ing U-ph A CT mounted on the UPS output U phase provides a current sense signal to X21 pins 1-3. The resulting voltage (IO_A) is developed across a selectable burden resistor and fed to the UPS Logic Board via X1-32. The appropriate resistance is selected by a three-position jumper identified as X37 which should be set to position 0-3 in all cases of 30kVA, 40kVA and 60kVA models. This signal is used by the UPS Logic Board to initiate an overload warning (alarm #66) and overload latches (alarm #62), and also to initiate the overload timer.

2.3.22

X22 (Page 1) – Battery current monit ori ng A DCCT mounted in the battery positive line provides a current sense signal to X22 pin 2 (pins 1 and 3 carry the ±12V operating power supply to the DCCT device). The signal voltage ( IO_A) is developed across a selectable burden resistor and fed to the UPS Logic Board via X1-31. The appropriate resistance i s selected by a three-position jumper identified as X31 which should be set to position 0-2 in standard 30kVA, 40kVA and 60kVA models and 0-3 in a 60kVA model. The sense signal is used by the Rectifier Logic Board to limit the maximum battery charge current (to protect the battery), and also by the UPS Logic Board to calculate the percentage capacity and remaining autonomy time.

2.3.23

X23 (Page 1) – Inverter curr ent monito ring U-ph Not used – the inverter U-phase current is not monitored in a standard 7200 Series UPS model.

2.3.24

X24 (Page 1) – Inverter curr ent monito ring V-ph A DCCT mounted in the inverter output V-phase line provides a current sense signal to X24 pin 2 (pins 1 and 3 carry the ±12V operating power supply to the DCCT device). The signal voltage ( IINV_B) is developed across a selectable burden resistor and fed to the UPS Logic Board via X1-29. The appropriate resistance is selected by a three-position jumper identified as X33 which should be set to 0-2 in standard 40kVA models and 0-3 in a 30kVA and 60kVA models. This signal is used by the Inverter Logic Board to: • •

2.3.25

regulate the PWM drives in order to sustain the inverter output during load changes (i.e. act as a feed-forward control). introduce a 150% inverter current limit (achieved by blocking the PWM signal and reducing the inverter voltage) in order to limit the maximum current drawn through the inverter and protect the inverter IGBT devices.

X25 (Page 1) – Inverter curr ent monito rin g W-ph A DCCT mounted in the inverter output W-phase line provides a current sense signal to X25 pin 2 (pins 1 and 3 carry the ±12V power supply to the DCCT device). The signal voltage ( IINV_C) is developed across a selectable burden resist or and fed to the UPS Logic Board via X1-30. The appropriate resistance i s selected by a three-position jumper identified as X34 which should be set to position 0-2 in standard 40kVA models and 0-3 in a 30kVA and 60kVA models. This signal is used in the same way as the V-phase signal described above.

2.3.26


2.3.27


s7-c2.f m5 - Issu e 2 Dated 21/08/97

7-11


2.4


Summary inf orm ation Table 7-2: High Voltage Interface Board configuration links

Jumper —

7-12

Link Position

Function

0-1

X31

0-2

X31 : X32 : X33 : X34 : X35 : X37 : X38 : X39 : X40

0-3

—

0-1

X31 : X32 : X33 : X34

0-2

X35 : X36 : X37 : X38 : X39 : X40

0-3

—

0-1

—

0-2

X31 :X32 : X33 : X34 : X35 : X36 : X37 : X38 : X39 : X40

0-3

30 kVA CT burden selection



s7-c2.f m5 - Issu e 2 Dated 21/08/97


Chapter 3 - UPS Logic Board (4550007 H)

3.1

Chapter overview This chapter contains a circuit description of the current UPS Logic Board used across the whole 7200 Series UPS model range, and should be read in conjunction with circuit diagram SE-4550007-H (7 pages). Part N º SE-4550007-H is a direct replacement for Part Nº SE-4550004-E which may be fitted to units manufactured prior to February 1997. Though their are only minor differences in the two PCBs a full explanation of the UPS Logic Board Part Nº SE-4550004-E can be found in Section 20 Chapter 4. Signal annotations shown on the circuit diagrams are shown in italics in the following text – e.g. [CLKOUT>.

3.2 3.2.1

General descri pti on Circuit board functio ns Figure 7-3: UPS Logic Board connections Rectifier Logic Board X2

Inverter Logic Board X4

Static Switch Driver Board X13

X1

X3

X5 X7

UPS Log ic Bo ard X2

X8

X1 High Voltage I/face Board

X1 External Alarm Options

X6

Parallel X2 Control Logic X3

X4

X2 X9 Operator Logic Board

Operator Control Panel

The position of the UPS Logic Board with respect to the other control boards places it at the heart of the UPS control operation and its functional responsibilities can be broadly summarised as follows: • Motherboard – One of the most basic functions provided by the UPS Logic Board is to act as a ‘motherboard’ for signals travelling directly between any of the other circuit boards connected to it: e.g. the input voltage sense signals passes directly from the High Voltage Interface Board to the Rectifier Logic

s7-c3a.fm 5 - Issu e 2 Dated 21/08/97

7-13

SECTION 7 - UPS System Control CHAPTER 3 - UPS Logi c Boar d (4550007 H)

•

•

•

•

3.2.2


Board. System control – The UPS Logic Board contains a microprocessor-based control system which reads various status signals derived on the other circuit boards and produces several ‘system’ control logic signals: e.g. ‘stop/start’ signals to the Rectifier/Inverter Logic Boards, and ‘transfer command’ signals to the Static Switch Interface Board. Alarms control – The UPS Logic Board acts as an assembly point for alarm signals generated on the various other boards, together with t hose generated on the UPS Logic Board itself, and controls their distribution to the Operator Control Panel and External Alarms Options under microprocessor supervision. Operator programming interface – The UPS Logic Board microprocessor enforces the programmable system operating parameters selected by the operator, via the Operator Logic Board, onto the ‘system’ control logic Static Switch transfer control – The UPS Logic Board contains decision-making logic which controls the load transfer events between the inverter and static bypass supplies.

Input/Outpu t con nectio ns The UPS Logic Board has eight connectors (See Figure 7-3) whose connections are summarised below. • • • • • • • •

7-14

X1 – System control and monitoring signals to/from the Rectifier Board 4520074-A (See Table 7-3). X2 – System control and monitoring signals to/from the High Voltage Interface Board 4590054-O (See Table 7-4). X3 – System control and monitoring signals to/from the Inverter Logic Board 4530025-T (See Table 7-5). X4 – Power supply to Operator Logic Board 4550005-F (see circuit diagram sheet 7). X5 – System control and monitoring signals to/from the Static Switch Driver Board 4542043-Z (See Table 7-6). X6 – Data/logic to/from Operator Logic Board 4550005-F (see circuit diagram sheet 7). X7 – System control and monitoring signals to/from the Parallel Logic Board 4520075-B. (See Table 7-1) X8 – Alarm outputs to optional external (remote) alarm display boards (see relevant external alarm interface board in the Options section of this manual).



SECTION 7 - UPS System Control CHAPTER 3 - UPS Logic Boar d (4550007 H)

Table 7-3: Connector X1 (To Rectifier Logic Board) PIN

I/O

1-4

I

0V – ground reference for digital electronics

5-8

I

+12V power supply derived from AC-DC Power Supply Board

9-12

I

-12V power supply derived from AC-DC Power Supply Board

13-14

I/O

Common – ground reference for analogue sense signals

15

O

VREC_AC: Input mains voltage sense signal (phases U-W) – through connection from HVI Board – (15Vp-p)

16

O

VREC_BA: Input mains voltage sense signal (phases V-U) – through connection from HVI Board – (15Vp-p)

17

O

VREC_CB:Input mains voltage sense signal (phases W-V) – through connection from HVI Board – (15Vp-p)

18

O

IB: Battery current sense signal – through connection from HVI Board – battery current limit control

19

–

Not used in standard modules

20

O

IREC: Rectifier input current sense signal – through connection from HVI Board – input current limit control

21-23

–


24

I

IREC_T: Used in parallel systems only (not available)

25

O

VB: DC Bus (battery) voltage feedback – through connection from HVI Board (-3.225Vdc @446V DC Bus)

26

O

T_BAT: Battery cabinet temperature sensor – through connection from HVI Board (2.98V @ 25°C)

27

O

IDC_1: Not used in standard model (12 pulse rectifier only)

28

O


29

O

DB: Used in parallel systems only (input current sharing)

30

O

DB_0: Used in parallel systems only (input current sharing)

31

–


32

I

OVLREC: Rectifier overload error status (Overload = 1)

33

I

BLKREC: Rectifier OFF/ON status (OFF = 1, ON = 0)

34

I

SEQREC: Input mains phase sequence error status (Error = 1)

35

I

IN_LOW: Low input volts 20% error status (Error = 1)

36

O

ON_REC: Rectifier Run(1)/Stop(0) command from UPSLB micro

37

O

XRADD_1: Reduced current limit from UPSLB micro (On Gen = 1)

38

O

REC_A: Charge mode selection from UPSLB micro

39

O

REC_B: Charge mode selection from UPSLB micro

40

–



Function

7-15



Table 7-4: Connector X2 (To High Voltage Interface Board)

7-16

PIN

I/O

Function

1-4

–


5-8

O

+12V supply to HVI Board

9-12

O

-12V supply to HVI Board

13-14

–


15-17

I

VI-A, VI-B, VI-C: Bypass sense voltages for U-V-W phases respectively. Approximately 1% of bypass L-N voltage

18-20

I

VINV-A, VINV-B, VINV-C: Inverter sense voltages for U-V-W phases. Approximately 1% of inverter L-N voltage (8Vp-p)

21-23

I

VO-A, VO-B, VO-C: UPS output sense voltages for U-V-W phases respectively. Approximately 1% of UPS output L-N voltage (8Vp-p)

24-26

I

VREC-AC, VREC-BA, VREC-CB: Input mains sense voltages. Approximately 1.3% of input L-L voltage – e.g. approx. range 5V - 5.5V (15Vp-p) for 380-415V nominal input

27

I

V-B: DC Bus (Battery) volts sense signal. Approximately 0.7% of the DC Bus voltage (+3.225Vdc @446V DC Bus)

28-30

I

IINV-A, IINV-A, IINV-C: Inverter current sense (150% phaseback)

31

I

I-B: Battery current sense signal (Batt I limit and current display)

32-34

I

IO-A, IO-B, IO-C: Output current – O/load alarm/timer/display

35

I

IREC-1: Input current sense signal (dc)

36-42

–


43

I

SW-REC: Rectifier Input Switch auxiliary contact status

44

I

SW-IN: Static Bypass Switch auxiliary contact status

45

I

SW-BYP: Maintenance Bypass Switch auxiliary contact status

46

I

SW-OUT: Output Switch auxiliary contact status

47

–


48

I

FUSINV: Inverter fuse monitor (not used in standard module)

49

I

FUSREC: Rectifier fuse monitor (not used in standard module)

50

I

FUSBAT: Battery fuse monitor

51

I

TH: Inverter thermostat contact status

52

I

ESD: Emergency shutdown

53

I

SW-BAT: Battery isolator auxiliary contact status

54

O

BATTRP: Battery isolator trip signal

55-56

–


57-60

I

T1, T2, T3, T4: Temperature sensing monitoring signals




Table 7-5: Connector X3 (Inverter Logic Board) PIN

I/O

1-4

I

0V power supply rail

5-8

I

+12V power supply derived from DC-DC Power Supply Board

9 - 12

I

-12V power supply derived from DC-DC Power Supply Board

13

–

Common

14

–

Common

15-17

O

[VI-A>, [VI-B>, [VI-C>: Bypass volts sense signals – through connection from HVI Board

18-20

O

[VIN-A>, [VIN-B>, [VIN-C>: Inverter volts sense signals – through connection from HVI Board

21-23

O

[IINV_A>, [IINV_B>, [IINV_C>: Inverter current sense signals – through connection from HVI Board

24

O

[XINVOI>: Mains error – load transfer to inverter (H)

25

O

[DREF>: Output voltage adjustment - used in parallel modules

26

O

[DREF0>: Output voltage adjustment - used in parallel modules

27-30

O

[DV-A>, [DV-B>, [DV-C>, [DV-0>: Load sharing signals used for parallel modules only

31

O

[INV-L>: Transfer load to inverter command from processor system

32

I

[OVL-INV>: Inverter overload status to processor system (OVL = L)

33

I

[BLK-INV>: Inverter On/Off status to processor system (Off = H)

34

I

[BACK>: Inv. frequency back to processor system from Inverter Logic Board

35

O

[SYNC>: Produced by processor system to Inverter Logic Board

36

O

[ON-INV>: Inverter On/Off control from processor system (Off = L)

37

O

[INV-F>: from processor system (Inv Freq)

38-39

O

[INV_A>, [INV_B>: from processor system - used in output volts selection

40

I

Inverter thermostat status signals (optional)


Function

7-17



Table 7-6: Connector X5 (Static Switch Driver Board) PIN

I/O

Function

1-4

O


5-8

O

+12V power supply rail

9 - 12

O

-12V power supply rail

13

I

XSTAI1: Not used in standard module. Details required as to what is connected to SSDB connector X7

14

I

XSTAI2: Output contactor (inverter output) auxiliary contact status – low = contactor closed

15-16

O

INV-L: Transfer load to inverter command from processor system

17-18

O

MNS-L: Transfer load to bypass command from processor system

19

–

XSTAD1: Not used in standard module.

20

–


Table 7-1: Connector X7 (See Table 8-2) PIN

I/O

1-4

–


5-8

O


9-10

O


11-13

–


14

I

Common – ground reference for analogue sense signals VI-A, VI-B, VI-C: Bypass sense voltages for U-V-W phases respectively. Approximately 1% of bypass L-N voltage

15-17

I


18

I

I_B_P:

19 20-22

COMM_P: DV-A, DV-B, DV-C:

23

DV-0:

24

IREC-T:

25

DB:

26

DB-0:

27-28

0V – ground reference

29-30

+5V – Supply to

31

7-18

Function

PAOU10:




Table 7-1: Connector X7 (See Table 8-2) PIN

I/O

Function

32

INV_DIS:

33

SW-OUT:

34

SWBYP:

35

I_BST_BAT:

36

I_TST_BAT:

37

MNS_DIS:

38

BLK_SEL:

39

OFF_INV:

40

C_L_INV:

41

RES_EXT:

42

V-AUX:

43

O_BLK_SW:

44

O_MNS_L_SS:

45

O_MNS_D_SS:

46

TST_BAT:

47

BST_BAT:

48

MNS_SYN_KO:

49

O_MNS_DIS:

50

SYN_INV_OK:

51

PAR_REC:

52

INV-L:

53

FRQ_SYN:

54

FRQ_PAR:

55

FRQ_MNS:

56

BACK:

57

INV_OK:

58

CON_SEL:

59

I_SW_BYP:

60

XSTAIZ:


7-19


3.2.3


Blo ck Diagram Figure 7-4: UPS Logic Board basic block diagram

N O F F O

n u R r e t r e v n I

n u N R r O e i f i t c e R

r d e B i f i c t i c g e o R L

F F O

1 X

d r a o B I . V . H

r d e B t r i c e g v o n L I

2 X

3 X

d r a o B S B S

l e l l c i a r g a o P L

5 X

7 X

3 2 D

N O F F O

F F O

r r l s l o t o o r e t s t r a n r c t p o e a n t v o y n n c B c I o R n n c C O r O e S s s a p y B

t r e v n I

8 X

e g u i n g r o f e l a f n u A B

2 2 D

N O

d m r r a a l o A B

t r u e p f f t u u B O

5 1 2 3 S S S S

f f t f e f f f O O O s / / e n / n n R O O O r s r e i e s t f a r i p e t y v c n e B I R

t r e u f p f u n I B

S C

X a t a D

X s s e r d d A

M O R P E X 3 8 9 4 4 4 U D D D M M A R

z k H c o M l 0 C 2

t r e e 8 s w e o 2 X R P

l a n g i S e u g o l a n A

0 P

4 P

3 P

l o r t n o C

1 P

D s r / e A t r e v n o C

5 P

2 P t a a D

e c a N f A r e C t n I

t y u l a p p t s u i O D

7-20



3.2.3.1


Syst em overv iew Processor system

The UPS Logic Board control system is based on a type 80C166 microcontroller, as shown in Figure 7-4. This device contains six ports through which it communicates with peripheral circuits/devices, together with several ‘system control lines’. It also contains an internal A/D converter, four programmable timers and internal ROM & RAM. The ports are configured by an initialisation routine performed by the system software on power-up and can be summarised as follows. • •

•

•

•

•

•

Port 0 This port is configured as a 16-bit bi-directional data bus Port 1 This port is configured as the first 16-bits of an 18-bit address bus the other two address lines are provided by port 4. Port 2 The lower half of this port carries various synchronising/timing signals and the upper half comprises the CAN data bus , which carries the data to/from the Operator Logic Board Port 3 This 16-bit port is configured as a mixture of inputs and outputs generally concerned with controlling the CAN Bus data exchange. Port 4 The lower two lines only are utilised on port 4. These form the upper two address lines the lower address lines are provided by port 1. Port 5 The lower ten lines of this port are configured to act as inputs to the internal A/D converter. System control lines In addition to the I/O ports the microcontroller also has the general control I/O lines normally associated with a microprocessor-based system; such as a system clock, reset, and Read/Write control.

Memory

The microcontroller uses both internal and external memory. 2 X 126k of battery backed RAM and 2 X 516k of EPROM are fitted to the board as standard which holds the system operating software. Faci lities are included on the board to allow alternative memory configurations to be used as described later. Data buffers

The 16-bit data bus is connected to various control circuit boards via input and output data buffers, as shown in Figure 7-4, which are controlled by individual ‘chip select’ enable lines to direct the data flow to/from the appropriate source, as required by the system control software. Analogue signal processing

The microcontroller monitors various analogue signals which are connected to the UPS Logic Board from the peripheral boards. These signals are processed by suitable analogue circuitry, buffered where necessary, and applied to the microcontroller’s A/D inputs via a series of multiplexer devices.


7-21



Primary output control signals

Although the micro-controller produces numerous control logic signals, its primary outputs can be considered to be: • Inverter Start/Stop Signal to the Inverter Logic Board which determines whether or not the inverter section is ‘enabled’ or ‘inhibited’. • Rectifier Start/Stop Signal to the Rectifier Logic Board which determines whether or not the rectifier section is ‘enabled’ or ‘inhibited’. • Load on inverter Signal which controls the ‘inverter-side’ contactor (K1) and connects the inverter output to the load. • Load on bypass Signal which controls the static switch and connects the load to the static bypass supply. Note: the ‘load on inverter’ and ‘load on bypass’ signals are interlocked such that they cannot be activated simultaneously. As shown on the block diagram, these signals are produced by a dedicated logic block which is controlled by the data bus together with individual switches which allow each of the above functions to be manually overridden. Operator Interface

The microcontroller is connected to the Operator Logic Board via the CAN Bus, which is a bi-directional serial communications link that enables the operator to program several operational parameters into the micro-controller and also enables various alarms and indications to be displayed on the Operator Control Panel.

7-22



3.3 3.3.1


Detailed cir cui t descrip tio n Introduction The UPS Logic Board circuit diagram (SE-4540007-H) comprises 7 sheets. With reference to the block diagram description (See Figure 7-4) , the drawings can broadly be described as follows: •

Sheet 1 contains a ‘signal map’ identifying the functions covered on the remaining pages. It also contains a summary chart detailing the various configuration jumpers. • Sheet 2 contains the – basic microcontroller system – data bus, address bus and control line buffers – Ni-Cad battery back-up controller – reset generator • Sheet 3 contains the – system RAM and ROM memory and its associated configuration links – Inverter/Rectifier Start/Stop control logic – load transfer control logic – CAN bus communications drivers and control logic – Real-time clock (RTC) • Sheet 4 contains the – data bus input buffers – data bus output buffers – on-board 7-segment indication circuit • Sheet 5 contains analogue signal processing circuits for the – input voltage sense signals – inverter voltage sense signals – DC (battery) bus voltage sense signal – Battery current sense signal it also contains reference voltage generators; power supply monitors; and inverter overvoltage and input overvoltage fault detection circuits. • Sheet 6 contains analogue signal processing circuits for the – output voltage sense signals – output current sense signals it also contains the analogue signal multiplexers (for the A/D inputs), out put overvoltage and overcurrent fault detection circuits. • Sheet 7 contains the – input/output signal identifications details – serial communications (RS485) driver and port Note: On the diagrams, a ‘negative’ symbol at the end of a signal’s annotation indicates that the signal is ‘active low’ – e.g. [RD> = [RD->. As with all micro-based system, the microcontroller’s operation is determined by the program held in the system’s memory: and as this is hidden to the service engineer there is very little that can be done to ascertain that the board is working correctly apart from checking the validity of its input and output signals, and other signals generated on the board which are required by the central processor system. The following description deals with the board on this basis, and should provide sufficient information to determine whether or not the board is functioning correctly when it comes to troubleshooting. A full software description is beyond the scope of this manual.


7-23


3.3.2


Basic microco ntroller system (circuit diagram sheet 2) Figure 7-5: Micro system control signals Power Supply

Clock

20

Reset

27

Power Fail

29

Vref (+5V)

54

Ready

97

Clock out

ALE

25

Address latch enable

BHE

92

Bus high enable

CLKOUT RSTIN NMI

RSTOUT VAREF

D42

Caution

96

READY

XTAL1

96

Reset out

RD

26

Read

WR

95

Write

C o n t r o l B u s

When monitoring the signals described in this section it is best done with control power only – i.e. with the UPS power sections shut down and the circuit boards live via the control power supply. The signals entering the left of the above diagram are constant and can be monitored with a meter/oscilloscope; those shown on the right of the diagram are not constant and best monitored with a logic probe. The logic sequence/timing of these signals depend upon various circuit conditions and cannot therefore be accurately defined; however, for field test purposes, the presence of a ‘variable switching’ logic signal at these points would generally indicate that the basic processor control bus is serviceab le and the system software is running. Power supply

The microcontroller is powered from the general +5V rail which is provided by a three-terminal 5V regulator (N1) shown on diagram sheet 7. System clock (XTAL1)

A dedicated crystal-controlled clock generator (E2) provides a system clock signal which is connected to the microcontroller (D12) pin 20. This signal is a 20MHz squarewave switching between +5V and 0V. System reset (RSTIN)

On power-up, a 1 second logic low reset pulse, [RSTIN->, is applied to D42 pin 27 from the ‘reset generator’ circuit. This can also be manually applied for troubleshooting purposes by temporarily bridging jumper X28 (See paragraph 3.3.5). The [RSTIN-> pulse forces the processor to resta rt its operation from the beginning of its operating program which forces it to run through its initialisation routine. Non-Maskable Interrupt (NMI)

When the input to D42 pin 29 (NMI) goes low it instructs the system software to interrupt its present operation and execute a power-down routine to save critical data. The source of this input is determined by X17 w hich is normally ‘made’ 2-3 and selects the power failure detection circuit output [PFO> as the controlling signal – this circuit is shown on diagram sheet 5 (See paragraph 3.3.15.4).

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Reference voltage (VAREF)

The input to D42 pin 54 (VAREF) is a +5V reference voltage used by the internal A/D converters to compute the digital values for all analogue signals – e.g volts/ current/VA etc. An adjustable reference voltage generator (N45 pin 8) (See paragraph 3.3.15.2), shown on diagram sheet 5, provides this input ( [VREF>) via X20 which is normally ‘made’ 1-2. Clock out (CLKOUT)

This output is a 20MHz squarewave synchronised to the processor clock input and is used by the RAM/ROM memory address decoding logic D33 (See paragraph 3.3.6) shown on the diagram sheet 3. This is to ensure that when the processor wishes to read from/write to memory the memory access is synchronised to the internal microprocessor action – i.e. it ensures that the accessed memory address is relevant to the current processor’s requirements. Address latch enable (ALE)

This output goes high to enable the address bus to be latched into the RAM/ROM memory address decoding logic D33 shown on the diagram sheet 3 – (See paragraph 3.3.6). Bus high enable (BHE)

The logic state of this output indicates whether the processor is internally enabling its ‘high’ or ‘low’ byte data bus – i.e. it indicates if the micro wishes to read from (or write to) the lower byte (D0....D7) or the higher byte (D8....D15). [BHE-> is low when the high byte is being accessed, and vice versa, and is used by the RAM/ ROM memory address decoding logic shown on the diagram sheet 3 – (See paragraph 3.3.6). Reset out (RSTOUT) [RSTO-> is controlled by the reset input signal, [RSTIN->, and goes high while the

input rest signal is applied. This signal is synchronised to the system clock and returns high an integral number of clock pulses after the input reset signal is removed. The [RSTO-> signal is used by the RAM/ROM memory address decoding logic shown on the diagram sheet 3 (See paragraph 3.3.6); and a buffered version, [RSTOX->, is connected to the data bus output buffers as shown on diagram sheet 4 via jumper X25 (2-3) – (See paragraph 3.3.12). Ready (Ready)

This input, when low, inserts wait states in the processor’s operation; thus slowing it down. It is driven by the RAM/ROM memory address decoding logic s hown on the diagram sheet 3 – (See paragraph 3.3.6) – and holds off the processor’s operation until the appropriate address latching has taken place, thus effectively extending the read/write times when slower memory elements are being used. Read (RD)

This output goes low when the processor wishes to read the data from the device or memory location currently addressed by the address bus. Write (WR)

This output goes low when the processor wishes to write data to the device or memory location currently addressed by the address bus.


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3.3.3


Data bus, address bus and con trol bus buf fers (circuit diagram sheet 2). Data bus buffer

Two type ACT245 octal bus transceivers (D32 & D 36) are employed as bi-directional protection buffers between the microcontroller (D0....D15) and the data bus (DX0....DX15). D32 buffers the ‘low’ byte (D0....D7) and D36 the ‘high’ byte; however both are controlled by a common data direction signal – i.e. the microcontroller’s [RD-> output – therefore the data direction of all 16 data bus lines are controlled by a single signal. These devices are described in appendix A (See paragraph A.1). When the microcontroller drives its [RD-> output low it sets the data direction through the buffers from B-to-A, which allows the data bus contents through to the microcontroller’s data inputs. At other times, when [RD-> is high, data flows through the buffers from A-to-B, allowing the micro to place data onto the data bus, which can then be written to a peripheral circuit as required. Address bus buffer

The address bus is also buffered by two ACT245 devices (D38 & D41) but, unlike the data bus described above, in this case the data direction is fixed by connecting pin 1 of each device to a permanent +5V supply. Thus the address bus data always flows through the devices in the A-to-B direction and used to select a memory location – the buffered address bus is annotated (AX0....AX17). Note: AX16 & AX17 are buffered by the control bus buffer described below. Control bus buffer

The control bus signals [RD->, [WR->, [BHE->, [RSTO-> are all buffered by D47. This device is configured with fixed data direction A -to-B, in the same manner as the address bus buffer described above, by the application of a fixed +5V supply at D47 pin 1. The buffered control signals [RDX->, [WRX->, [BHEX->, [RSTOX-> are used by various circuits distributed throughout the circuit diagrams. In all cases the above mentioned buffers have pull-up resistors connected to t heir input and output pins – e.g. resistor packs R307, R309 etc.

3.3.4

Ni-Cad Battery back-up cont roll er (circuit diagram sheet 2). A 3.6V 280mAh Ni-Cad battery is fitted to the UPS Logic Board to back-up the RAM contents and maintain the RTC time-keeping operation when the UPS is turned OFF; when fully charged the battery offers a back-up period of up to 4 to 5 months. The charger circuit is activated by t he [OUTBAT> signal which is produced by the processor via D25 pin 19 (diagram sheet 4). When [OUTBAT> goes high it turns on V152 which then turns on V151 to supply the battery charge current via led H8, R32 and V73. The charge voltage is limited to 4.7V by zener V14. Note: the battery can be disabled for shipping/storage by opening jumper X31.

The battery is connected to the RAM memory devices and Real Time Clock device – shown on diagram sheet 3 – via V32 and the battery supply annotated [VRAM>. Thus, if the board’s power supply is turned off (i.e. UPS fully powered down) the programmable parameters held in RAM (e.g. kVA, working voltage

7-26




and frequency, battery charging parameters and display language) are maintained; and the real-time clock keeps running. It is not therefore necessary to re program these parameters following every start-up. Note: Jumper X31 must be made in order to enable this function.

The [VBATT> output is not connected to other parts of the circuit, but it is monitored by the microcontroller’s analogue input [AN9> via D44, which is a quad analogue switch. [VBATT> is switched through D44 pin 2, by [FL-12> when it goes high; this is controlled by a ±12V supply rail monitor circuit (diagram sheet 5) which inhibits the [VBATT> sense signal if the ±12V power rails are invalid, thus preventing an erroneous battery voltage fault being detected by the micro under these conditions. Note: the other three gates within D44 are not used and their inputs are tied to 0V. [OUTBAT> signal details

The micro-controller monitors the NiCad battery voltage (3.6V nom) via AN9 and its internal A/D converter (as described above) and turns on the Ni-Cad charger, by driving the [OUTBAT> signal high, if the Ni-Cad voltage falls below 2.8V. When the charger is active, the [INTERNAL BATTERY LOW] message is displayed on the Operator Control Panel ( alarm #76) and led H8 illuminates. Once the battery is recharged to 3.6V the charger is turned off by the [OUTBAT> signal returning low and the alarm message is cancelled. Thus the Ni-Cad battery is charged only when necessary and is not permanently trickle-charged. Note: the NiCad charger may be active for several hours when the UPS is first commissioned (depending on the initial battery charge state) – jumper X31 must be fitted to ‘enable’ the battery back-up facility.

3.3.5

Reset generat or (circuit diagram sheet 2). A purpose-designed Supply Voltage Supervisor (N24) provides the micro with a 1 second sec logic low [RSTIN-> reset signal on power-up. This signal, which is applied to the micro pin 27, can also be initiated manually by temporarily making jumper X28 (1-2). The [RSTIN> signal also resets the RAM chip select signals produced by D19a/d (shown on circuit diagram sheet 3) and points the micro to its initialisation routines.

Caution

Using X28 to activate the reset circuit during normal UPS operation will crash the unit, because the ‘run’ signals to the rectifier, inverter and static switch will be disabled for the 1 second reset period.

On power-up (reset) the micro-controller receives initialisation data from D20 which is an EEPROM used to store the Emerson/Liebert/SICE software passport identification. Amongst other things this configures the micro’s programmable ports P0-P5 to the parameters required to operate in this application. Without this security interlock the micro-controller will be inactive. An inverse output, [V AUX>, goes high on reset and is connected to D22 and D23 in the ‘Inverter/Rectifier Start/Stop control logic’ and ‘Load transfer control logic’ (circuit diagram sheet 3). This resets the logic latches (Emergency Stop, DC Overvolts, etc.) and re-applies the ‘run’ signals to the rectifier, inverter and static switch. Note: the reset time is determined by R157/C97, and begins when the +5V supply rail reaches 3.6V on initial power-up.


7-27


3.3.6


System RAM and ROM memory addressi ng (circuit diagram sheet 3). The system memory comprises 2 x 512k EPROMs (D35 & D46) and 2 x 128k RAM chips (D28 & D40). All these devices have an 8-bit data bus output; however, the EPROMs have a 16-bit address input while the RAM chips have a 17 bit address facility. Random Access memory (RAM)

This is the read/write memory store; sometimes referred to as the temporary store. Any data fed in from the peripheral devices or produced during the execution of the main program will be temporarily held in RAM – e.g. UPS setup parameters such as kVA, nominal voltages/frequency, serial number, passwords, etc. This is a ‘volatile’ location, meaning that when power is lost to the component all data is also lost; thus the need for the on-board back-up Ni-Cad battery. Read Only Memory (ROM)

This memory contains the ‘operating system program’, or firmware , which is basically a sequence of instructions to be carried out by the micro-controller in order to make it perform the actions required of it. Upon power-up the micro is pointed to the first instruction as part of its reset initialisation, and from then on it steps through the programmed instructions in a sequence dictated by various events and monitored conditions. ROM is ‘non-volatile’, which means that it does not lose its memory contents in the event of a loss of power. Address decoding – D33 / D19

The ‘output enable’ pins of all four memory devices are controlled by the control bus [RD-> line, therefore when this line goes low the processor can read the data held at the current address from any of the devices. The purpose of the ‘address decoding’ circuit is to enable the microcontroller to select which of the EPROM or RAM devices it wishes to communicate with at any given time. The memory devices’ ‘chip select’ inputs are controlled by a circuit comprising an ASIC i.c. (D33) and two gates of D19. D33’s inputs are connected to A0, A14....A17, and several control bus signals – as described in paragraph 3.3.2. – which are all controlled by the microcontroller. The output signals, [CSEP1L->, [CSEP1H->, [CSRA1L->, and [CSRA1H->, adopt logic states determined directly by these processor-controlled inputs and are synchronised to the processor operation by the 20MHz [CLKOUT> signal. When low, [CSEP1L-> and [CSEP1H-> enable the EPROM devices via their ‘chip enable’ inputs (pin 20), while [CSRA1L-> and [CSRA1H-> perform a similar function on the RAM chips. The [READY> output from D33 is fed back to the micro to inform it that the appro priate addresses have been loaded into D33’s internal latches (See paragraph 3.3.2). As D19 provides the ‘chip select’ inputs to the RAM devices it is powered from the battery-backed RAM supply to prevent RAM data corruption on UPS power down. Note: jumper X14 provides a test facility for bench testing only and all links should be open during normal operation.

7-28




AX15 & AX16 configuration links

The UPS Logic Board has been designed to facilitate future software upgrades by including configuration links to permit the addressing of alternative memory devices. These links affect the routing of the AX15 and AX16 address lines, and the standard configuration is shown below in Figure 7-6. In the standard configuration the signals annotated [PIN29EP> and [PIN3EP> are connected to the EPROMs’ A14 and A15 inputs and are therefore driven by the AX15 and AX16 address lines respectively. The [PIN31RAM> signal (AX16) is connected to the A15 input of both RAM devices and the [PIN3RAM> signal (AX15) is connected to the RAM ‘write enable’ inputs. Figure 7-6: AX15 & AX16 decoding configuration links X19

X13

1

1

2

2

3

3

[AX16>

X22

[PIN3EP>

X21

1

1

2

2

3

3

X23

[AX15> [PIN29EP> [WRX–>

3.3.7

[PIN31RAM>

[PIN3RAM>

X24

5

5

4

4

3

3

2

2

1

1

[PIN29RAM>

Basic syst em con trol log ic (D88) The term ‘Basic System Control Logic’ is used here to described the signals generated by the UPS Logic Board which control the rectifier and inverter ‘start/stop’ commands; battery circuit breaker ‘trip’, and the ‘load transfer’ control between inverter and static bypass. These functions are controlled by a single ASIC device annotated D88 which is shown on sheet 3 of the diagram and also in greater detail in Figure 7-7. D88 also provides the processor system with various status signals, as illustrated in the block diagram. The following description begins by identifying D88’s input logic signals, and continues by explaining their influences on the individual output control signals.


7-29



Figure 7-7: Basic system control logic (internal detail)

ESD_I

X2-52

09

D88 29

N15-8 N15-14

R97

SCR_OPN

M_ESD D26-5

28

R86 32 M_SCR_OP

D26-4

Z39 0V

BAT_MA

D34-12

08 20 M_BAT_MA

2 1 1 R

1 1 1 R

3 1 1 R

D26-6

26 BAT_MA_D 27 SCR_OP_D 24 ESD_D MRESET

43

N24-6

V-AUX

44

D21-2

ALM_RES

16

3 6 C

39

RES_EXT

SEQ_MNS

D26-7

13

BLK_BYP_M D55-9

D21-16

D21-5 X7-39 D21-9 X7-32 D54-6 D1-4 D21-12

MNS_KO

11

IBOPEN

12

BLK_INV_M

02

INV_ON OFF_INV

17

34 BAT_TRP

33 ON_INV

14 07

SYN_KO

18

B-INV L_MAINS

31 41

BLK_REC_M

04

REC_ON

40

Q3 R320 Q2

S1

+5V

7-30

X2-54

X3-36

36

INV_L

38 MNS_L

ON_REC

D51-8

D51-6

X1-36

Block Rectifier

Block Inverter

R320

Block Bypass

R320

Manual RESET

Q1

D26-3

06

INV_DIS

R320

X7=41

05

37

D21-15

BLK_MNS

0V

01

C_L_INV L_INV

X7-40

25

2 4 5 6 6 C

0V



3.3.7.1


D88 Status signals to proc essor system Emergency shutdown [M_ESD>

The ‘emergency shutdown’ signal [ESD_I> to D88-9 is driven by external circuitry and connected via X2-52 (sheet 7) as a logic high when the emergency shutdown is applied. This drives pin 29 ( [M_ESD>) high which is connected to the processor system via D26-5 where it initiates alarm #63 [CUT-OFF: EMERGENCY] (See paragraph 3.3.11.4) and also provides a latching input back to D88 pin 24 ( [ESD_D>) which holds pin 29 in its high state until the reset circuit is activated – the latching signal is debounced by R112/C63. The high [ESD_D> input to D88 pin 24: • • • •

turns off the ‘bypass enable’ signal ( [BLK_MNS> = 0) D88 pin 25. trips the battery circuit breaker ([BAT_TRP> = 0) D88-34 turns OFF (stops) the rectifier ( [ON_INV> = 0) D88-33 turns OFF (stops) the inverter ( [ON_REC> = 0) D88-37

Static switch SCR open [M_SCR_OP>

The ‘static switch SCR open’ signal [SCR_OPN> to D88-28 is produced by N158 or N5-14 (sheet 6) as a logic high when the detection circuits ‘sees’ a voltage drop across one of the static bypass SCRs. This drives pin 32 ( [M_SCR_OP> ) high (provided the ‘load on mains’ ( [MNS_L>) output to D88-38 is also high) which is connected to the processor system via D26-4 where it annunciates alarm #15 [BYP: SCR FAILURE] (See paragraph 3.3.11.4) and also provides a latching input back to D88 pin 27 ( [SCR_OP_D> ) which holds pin 32 in its high state until the reset circuit is activated – the latching signal is debounced by R111/C62. In addition to latching the output on pin 32, the logic high [SCR_OP_D> input also blocks the static switch by forcing high the [BLK_MNS> output at D88-25 (see details of [BLK_MNS> below). DC Overvoltage – fast

The ‘DC Fast Overvoltage’ signal ( [BAT_MA>) to D88-8 is produced by N13-8 (sheet 5) and is logic high when a DC busbar (battery) overvoltage condition (>620V) is present. This drives pin 20 ( [M_BAT_MA> ) high which is connected to the processor system via U26-6 where it initiates alarm #58 [DC BUS: FAST OVERVOL.] (See paragraph 3.3.11.4) and also provides a latching input back to D88 pin 26 ([BAT_MA_D> ) which holds pin 20 in its high state until the reset circuit is a ctivated – the latching signal is debounced by R113/C64. The logic high latching signal to pin 20 ( [M_BAT_MA> ) also: • • •

trips the battery circuit breaker ([BAT_TRP> = 0) D88-34 turns OFF (stops) the rectifier ( [ON_INV> = 0) D88-33 turns OFF (stops) the inverter ( [ON_REC> = 0) D88-37


7-31


3.3.7.2


D88 Reset circ uit [RES_EXT>

There are three sources of reset signal applied to D88: •

• •

D88-16 receives a logic high reset signal from the microcontroller via the data bus output buffer D21-2 (See paragraph 3.3.12.5). This is a software reset programmable via the Operator Control Board D88-44 receives a logic high reset pulse when the board is powered up (See paragraph 3.3.5) D88-43 is driven high when the manual reset button (S1) is pressed

Common functions

In each case, a logic high activation on any of the above inputs: • •

resets the ‘Emergency shutdown’, ‘Bypass SCR open’ and ‘DC overvoltage’ latches described above. provides a [RES_EXT> reset signal at D88-39 which is applied via X7-41 to the Parallel Logic Board in a ‘1+1’ configured system.

[V_AUX> signal functions

In addition to the common functions described above the [V_AUX> signal also: • • • • •

applies a reset signal directly to the Parallel Logic Board – via X7-42. resets (turns off) the static bypass – ([BLK_MNS> = 1) D88-25. resets (opens) the battery circuit breaker– ([BAT_TRP> = 0) D88-34. resets (turns off) the inverter – ([ON_INV> = 0) D88-33. resets (turns off) the rectifier – ([ON_REC> = 0) D88-37.

The [V_AUX> ‘power-up’ reset signal to D88-44 also resets the [BLK_MNS> output from D88-25, described immediately above. 3.3.7.3

Major contr ol sign al outpu ts Static bypass inhibit [BLK_MNS>

The [BLK_MNS> output from D88 pin 25 goes high when D88 detects any condition which requires the load to be prevented from being connected to the static bypass supply. This output is fed to the microcontroller via the data bus buffer U26-3 where it initiates alarm #16 [BYP:HARDWARE BLOCK.] (See paragraph 3.3.11.4) and is also connected to the ‘load-on-bypass’ control logic within D88 where it inhibits the ‘load-on-bypass’ command [MNS_L> output from D88 pin 38. The [BLK_MNS> signal can be driven high, disabling the s tatic bypass, by any one of the following conditions: • • • •

‘Emergency shutdown’ latch set – ([ESD_D> = 1) D88-24 (see above). ‘Bypass SCR open’ latch set – ([M_SCR_OP> = 1) D88-27 (see above). 1 second Power-up reset pulse ([V_AUX> =1) D88-44 (see above). Static bypass mains phase sequence error ([SEQ_MNS> = 1) D88-13. This is derived from D27a on diagram sheet 5 (see paragraph 3.3.13.2 on page 7-56). • ‘Manual block’ applied from switch Q1 – ([BLK_MNS_M>) = 1) D88-1. • ‘Mains error’ signal – ([MNS_KO>) = 1) D88-11. This is produced by the processor system under software control and applied via data bus buffer D55 (see paragraph 3.3.12.7 on page 7-50).

7-32




Battery circuit breaker trip [BAT_TRP>

A logic low [BAT_TRP> output from D88-34 trips the battery circuit breaker via X2-54 (sheet 7), which is connected to the High Voltage Interface Board (See section 7 paragraph 2.3.8). The [BAT_TRP> signal can be driven low by any one of the following inputs: • • • •

‘DC Fast Overvoltage’ latch set ([BAT_MA_D> = 1) D88-26 (see above). ‘Emergency shutdown’ latch set – ([ESD_D> = 1) D88-24 (see above). 1 second Power-up reset pulse ([V_AUX> =1) D88-44 (see above). ‘Software trip’ – ([IBOPEN> = 1) D88-12. This is produced by the processor system under software control and applied via data bus buffer D21-16 (See paragraph 3.3.12.5). Note: This signal trips the battery breaker on low DC voltage as follows: – UPS on greater than 15% load = 330V – UPS on less than 15% load = 360V The low voltage trip level is programmable via the Operator Control Panel SET-UP screen, and is adjustable between 1.6V/cell and 1.69V/cell; however the 30V window between the <>15% levels is not adjustable.

Inverter Start/Stop (On/Off)

The [ON-INV> output from D88-33 is connected to the Inverter Logic Board via X3-36 (sheet 7) where it controls the inverter ‘Start/Stop’ status (see paragraph 2.3.8 on page 5-51). A logic low [ON-INV> signal commands the inverter to ‘STOP’ and can be effected by any one of the following D88 inputs (conversely, all the following inputs must be in their ‘healthy’ low state in order for the inverter to run): • • • •

•

•

‘DC Fast Overvoltage’ latch set ([BAT_MA_D> = 1) D88-26 (see above). ‘Emergency shutdown’ latch set – ([ESD_D> = 1) D88-24 (see above). 1 second Power-up reset pulse ([V_AUX> =1) D88-44 (see above). ‘Software control’ – ([INV-ON> = 0) D88-17. This is produced by the processor system under software control and applied via data bus buffer D21-6 (See paragraph 3.3.12.5). This signal is ‘low’ to inhibit the inverter and ‘high’ to enable it. When this signal is actively blocking the inverter (i.e. low) it initiates alarm #30 [INV:SOFTWARE BLOCK.]. ‘Manual inverter block’ – ([BLK_INV_M> = 1) D88-2 – logic high from the manual inverter inhibit switch Q2. If the [ON-INV> signal at D88 pin 33 is active (low), blocking the inverter, alarm #32 [INV: HARDWARE BLOCK] will be active. Note that alarm #32 will be disabled if alarm #31 is active. Alarm #31 can be interpreted that the inverter has been selected off, while alarm #32 suggests that the inverter has been turned off for some other reason. Parallel Logic ‘Inverter OFF’ request – ([OFF_INV> = 1) D88-5. This input allows the Parallel Logic Board to enable/inhibit the inverter in a ‘1+1’ configured system (see paragraph 2.3.1 on page 8-12). [OFF_INV> is high to inhibit the inverter and vice-versa.

Rectifier Start/Stop (ON/OFF) [ON_REC>

The [ON_REC> output from D88-37 is connected to the Rectifier Logic Board via X1-36 (sheet 7) where it controls the rectifier ‘Start/Stop’ status (see paragraph 2.3.6 on page 4-35). A logic low [ON_REC> signal turns OFF the rectifier and can be effected by any one of the following D88 inputs: •

‘DC Fast Overvoltage’ latch set ([BAT_MA_D> = 1) D88-26 (see above).


7-33



• • •

‘Emergency shutdown’ latch set – ([ESD_D> = 1) D88-24 (see above). 1 second Power-up reset pulse ([V_AUX> =1) D88-44 (see above). ‘Software control’ – ([REC-ON> = 0) D88-40 – [REC-ON> . This is produced by the processor system under software control and applied via the data bus output buffer D21-15 (See paragraph 3.3.12.5). [REC-ON> is ‘low’ to inhibit the rectifier and ‘high’ to enable it. When this signal is actively blocking the rectifier (i.e. low) it initiates alarm #20 [RECT:SOFTWARE BLOCK]. • ‘Manual rectifier block’ – ([BLK_REC_M> = 1) D88-4. This input is obtained from the manual rectifier inhibit switch Q3. If the [ON-REC> signal at D88 pin 37 is active (low), blocking the recti fier, alarm #22 [RECT:HARDWARE BLOCK] will be active. Note that this will be disabled if alarm #21 is active. Alarm #21 can be interpreted that the rectifier has been selected off via the Operator Control Panel, while alarm #22 suggests that the rectifier has been turned off for some other reason 3.3.7.4

Load transfer contr ol

The transfer control logic within D88 is interlocked such that the ‘load on inverter’ [INV_L> and ‘load-on-bypass’ [MNS_L> commands are mutually exclusive. ‘Load on inverter’ command [INV_L>:

The Load on inverter’ command ( [INV_L>) output from D88-36 goes high to transfer the load to the inverter; and is connected to the Static Switch Driver Board via X5-15 (sheet 7), where it turns OFF the static switch (disconnecting the load from the bypass supply) and energises the ‘inverter-side’ contactor (K1) driver circuit. It is also connected to the Inverter Logic Board, via X3-31, where it triggers the latches within D11 which makes the inverter voltage track the bypass supply voltage for 100ms (See section 5 paragraph 2.3.3). This is done to provide a smooth transfer from bypass to inverter and reduce the w ear on the ‘inverter-side’ contactor (K1). In order for D88 pin 36 ( [INV_L>) to go high, all of the following conditions must be satisfied: •

•

•

‘Inverter Logic Board OK’ – ([B-INV> = 0) D88-31. This input is driven by the fault detection circuit on the Inverter Logic Board and applies a 1 second logic high hold-off command to X3-33 ( [BLKINV> diagram sheet 7) when any of its internal faults are active (e.g. Vsat) (see paragraph 2.3.7 on page 5-50). This is connected to D88-31 in the form of [B-INV>, and must therefore be logic low, indicating “no fault” in order to permit the load to be connected to the inverter. ‘Software request’ – ([L_INV> = 1) D88-14. This is produced by the processor system and applied via the data bus output buffer D21-9 when all its software-monitored parameters have been verified (e.g. Inverter voltage OK, Sync OK etc.)(See paragraph 3.3.12.5). Parallel Logic ‘Inverter on inverter’ request – ( [C_L_INV> =0) D88-6. This input is generated by the Parallel Logic Board in a ‘1+1’ configured system and goes low when the parallel system control conditions request connecting the load on inverter. In a single-module application this input, which is applied via X7-40, is tied to logic low and has no affect.

‘Load on bypass’ command [MNS_L>:

The ‘load on bypass’ command output from D88-38 goes high to transfer the load to the bypass; and is connected to the Static Switch Dr iver Board via X5-17 (sheet

7-34




7), where it turns on the static switch driver circuit, connecting the load to the bypass supply. It is also connected internally (within D88) to disable the ‘bypass SCR open’ annunciation circuit when ‘load on bypass’ is not being commanded – i.e. the ‘Open Circuit SCR’ fault is discounted while the load is ‘on-inverter’. In order for D88 pin 38 ( [MNS_L>) to go high, all of the following conditions must be satisfied: 1. The static bypass must be ‘enabled’ – i.e. the [BLK_MNS> output on D88 pin 25 must be low (see above). 2. Parallel Logic ‘Inverter on bypass’ request – ( [INV-DIS> =0) D88-6. This input is generated by the Parallel Logic Board in a ‘1+1’ configured system and goes low when the parallel system control conditions request connecting the load on bypass. In a single-module application this input, which is applied via X7-32, is tied to logic low and has no affect. Note: on the Parallel Logic Board the signal at X1-32 is identified as [I_BUS_INV_L>. 3. In addition to conditions (1) and (2) above, one of the following conditions must also be valid: a) ‘Software request’ – ([L_MNS> = 1) D88-41. This is produced by the processor system when all software-monitored parameters are correct (e.g. Critical bus volts not OK, overload, bypass volts OK etc.) and applied via the data bus output buffer D21-12 (See paragraph 3.3.12.5). b) No ‘Load-on-inverter’ is being requested – i.e. D88-6 [C_L_INV> AND D88-14 [L_INV> are both logic high (see above). This means that neither the Parallel Logic Board nor the microprocessor system are calling for the load to be connected to the inverter c) Inverter is blocked, but still in-sync – i.e. D88-31 [BLK_INV> is high (see above) AND the [SYN_KO> input to D88-18 is low. Note that [SYN_KO> is derived via the processor system and D54, and is logic high when the inverter and bypass are not in sync (see paragraph 3.3.12.8 on page 7-52).

3.3.8

CAN bus communi cations drivers and control logic (circuit diagram sheet 3). The CAN bus communications system is described in paragraph 5.3.9. (Operator Logic Board).

3.3.9

Real-time cl ock (RTC) (circuit diagram sheet 3) The MC68698 (D18) is a peripheral device which contains a real-time clock/calendar, a 32 x 8 bit static RAM, and a synchronous, serial, three-wire interface for communicating with the micro-controller. As it’s title suggests, the real time clock accurately counts seconds, minutes, hours (AM/PM), Day-of-the week, date, month and year (including auto-incrementing leap-year). In the UPS Logic Board application it provides ‘date stamping’ for the Operator Control Panel messages and ‘service data’ entered via the Maintenance Menu Screen (see paragraph 2.4.6.3 on page 2-40). The device operates from the Ni-Cad back-up battery to maintain its time-keeping function and prevent data loss when the general +5V control power is turned off. It also contains many other circuit functions,


7-35



such as an alarm facility, watchdog timer etc. which are not used in this application but may be mentioned briefly in the following description. Power supply details

D18 is powered from the +5 volt power supply, which is connected to pin 16 (Vcc) and available at all times provided the unit is powered up. When jumper X33 is made 1-2 the battery-backed RAM supply [VRAM] (See paragraph 3.3.4) is connected to pin 13 [Vbatt> and also, via an R-C delay circuit (R108/C54), to pin 10 [POR>. The delayed input to pin 10 is seen as a ‘Power On Reset’ [POR> and resets the device by briefly holding pin 10 low while the device is powered-up. However, as the battery-backed supply is present at all times, this is effectively a ‘onceonly’ reset that takes place when X33 is initially made 1-2 (i.e. battery connected) and is not affected by subsequent application/removal of the UP S Logic Board’s +5V control power supply. The board’s +5V supply rail is monitored at D18 pin 12; and when the voltage at this pin is less than 0.7V above the Ni-Cad voltage (pin 13) the device switches to a low-power stand-by mode whereby it maintains its time-keeping function but internally inhibits serial communication facilities with the micro-controller. This prevents the passage of invalid or spurious data while the micro-controller is powering-down and so prevents RTC data corruption. Clock control

The RTC’s internal timer operation can be controlled from one of two sources; either from an external crystal-controlled clock reference or a 50/60Hz mains-derived sinusoidal signal. In this particular application an external crystal is used and the 50/60Hz input to pin 11 (LINE) is grounded via R107. For crystal operation pins 14 and 15 are connected to a 32.768kHz, 1.048576kHz, 2.097152kHz or 4.194304kHz crystal, as shown on the circuit diagram. A programmable internal divider circuit enables the particular external clock frequency to be scaled down to that used by the internal logic. The internal clock signal is made available at pin 1 (CLKO) but in this particular application is not used, and remains unterminated. Serial communications interface

Four lines, connected to pins 4 to 7, implement a bi-directional communications interface with the micro-controller, and allow the micro to write configuration and control data to the RTC and read the ‘time’ and register data. As described above, such communication is inhibited if the UPS Logic Board’s +5V power rail is unavailable. The [ORCS> input to pin 7 (SS) is seen as a ‘chip select’ input in this application and must be held high while either a read or write event is taking place. Data is input (written) to the RTC by [ORDI> to pin 5; and output (read) from the device by [ORDO> from pin 7. In each case the data takes the form of a serial data stream clocked in/out by the ‘serial clock’ signal [ORSK> applied to pin 4. Note that all four of these signals are under direct control of the micro-controller and applied to the data bus via the buffers shown on diagram sheet 4. Other connections

The functions connected to pin 2, pin 3 and pin 9 are not used in this particular application and these pins are tied to their default logic levels as shown.

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SECTION 7 - UPS System Control CHAPTER 3 - UPS Logic Boar d (4550007 H) Section 7:

3.3.10

Data bus buf fers ‘ch ip select’ decodi ng The data bus communicates with the peripheral circuits and devices via 16 octal buffers which are selected in ‘pairs’ to provide a 16 bit data bus transfer. The micro-controller selects a particular buffer-pair by appropriately addressing the ‘chip select’ decoding circuit (D52) which then ‘enables’ the required buffers. Details of the digital signals handled by each buffer are provided in the following paragraphs. Figure 7-8: Data bus buffer control (block diagram) D8 [CSIN1->

D17

OE

CP

D2

D25 CP

OE

D1 [CSIN2->

D9

OE

CP

D26

CP

D51

D50 CP

OE

D60

CP

D7

D54 CP

CP

D10 CP

D55

OE

[CSDIS->

D21

OE

[CSIN3->

D56 CP

DATA BUS

Control Bus

Microcontroller Address Bus AX11 AX12 AX13 AX14 AX15 AX16 AX17 [RDX-> [WRX->

s7-c3b .fm5 - Iss ue 2 Dated 21/08/97

1 2 3 4 5 6 7 8 9

D52

12 13 14 15 16 17 18 19

[CSDIS-> [CSIN1-> [CSIN2-> [CSIN3-> [CSOU1-> [CSOU2-> [CSOU3-> [CSOU4->

7-37


3.3.11


Data bus inp ut buff ers (diagram sheet 4). Digital signals which are read by the microcontroller as part of its control function are connected to the data bus via six type HCT 245 octal bus transceivers (See Ap pendix A.1) which are accessed in pairs to provide a 16-bit data transfer (See Figure 7-8). The buffers ‘data direction’ pins are held permanently high, therefore the data flow is fixed from ‘A-to-B’ in each device. ‘Chip select’ signals from D52 are connected to the buffers ‘output enable’ pins which provides the means for the micro to select each pair of devices as required. The remainder of this sub-section lists the digital signals connected to the data bus through the bus input buffers, and provides signal details where appropriate. Note: The alarms shown are for version 4 software. These may vary from earlier software versions, which will have different screen descriptions, the alarm number and definition however remains the same.

3.3.11.1

Buf fer D8 – activ ated by CSIN1 XRADT1

Source: Sheet 7 X1-31 Description: From the Power Rectifier overtemperature sensing device – this input is not normally used and is held permanently low by jumper X10 (1-2) on the Rectifier Logic Board. If used, in an overtemperature situation this input initiates alarm #24 [RECT: OVERTEMPERAT.] and the rectifier and inverter are shut-down 1 minute later accompanied by alarm #62 [CUT-OFF: OVERTEMPER] . This alarm must be reset by pressing the manual reset push-button. OVLREC

Source: Sheet 7 X1-32 Description: Rectifier Overload – this input goes high when the rectifier is operating in input current limit mode (H6 illuminated on the Rectifier Logic Board) – (See section 4 paragraph 2.3.4.2). This initiates alarm #23 [RECTIFIER: I/P LIMIT]. BLKREC

Source: Sheet 7 X1-33 Description: Rectifier Blocked – this input goes high when the Rectifier Logic board is in its ‘stop’ mode (See section 4 paragraph 2.3.6). This can be due to the Rectifier Logic Board detecting an internal fault or a ‘stop’ (block) command issued by the UPS Logic Board (See paragraph 3.3.7). The internal fault channel is triggered by either: incorrect phase rotation; Rectifier Logic Board power supply failure; or low input voltage (-20%). The external fault channel initiated by the UPS Logic Board will be accompanied by alarm #21 [RECT: OFF VIA DISPL.] or alarm #22 [RECT: HARDWARE BLOCK] (See paragraph 3.3.7).

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s7-c3b.fm5 - Issue 2 Dated 21/08/97



SEQREC

Source: Sheet 7 X1-34 Description: Rectifier input phase sequence error – this input goes high when the Rectifier Logic board phase sequence monitor detects an error on the incoming 3 phase mains supply (H8 illuminated on the Rectifier Logic Board) (See section 4 paragraph 2.3.6.1). IN-LOW

Source: Sheet 7 X1-35 Description: Rectifier input undervoltage – this input goes high when the Rectifier Logic board input voltage monitor detects a -20% undervoltage condition on the incoming 3 phase mains supply (H9 illuminated on the Rectifier Logic Board) (See section 4 paragraph 2.3.6.2). XATI1 / XATI2 / XATI3

Source: Sheet 7 X2-40 / 41 / 42 Description: Not used – no connection on High Voltage Interface Board. 3.3.11.2

Buf fer D2 – activ ated by CSIN1 SW-REC

Source: Sheet 7 X2-43 Description: Rectifier input switch monitor – this input goes low when the rectifier input mains power switch is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the input switch is open, this signal initiates alarm #04 [RECTIF. SWITCHOPEN]. SW-IN

Source: Sheet 7 X2-44 Description: Static Bypass switch monitor – this input goes low when the Static Bypass mains power switch is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the bypass switch is open, this signal initiates alarm #02 [BYPASS SWITCH OPEN]. SW-BYP

Source: Sheet 7 X2-45 Description: Maintenance Bypass switch monitor – this input goes low when the Maintenance Bypass switch is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the maintenance bypass switch is closed, this signal initiates alarm #06 [MANUAL BYPASS CLOSED].


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SW-OUT

Source: Sheet 7 X2-46 Description: Output switch monitor – this input goes low when the Output switch is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the output switch is open, this signal initiates alarm #03 [OUTPUT SWITCH OPEN]. FUSINV

Source: Sheet 7 X2-48 Description: Not used - held permanently low due to link fitted to connector X16 on the High Voltage Interface Board (see main equipment wiring diagrams). If used, this input monitors the inverter fuse and on fuse failure initiates alarm #38 [INV: FUSE FAIL]. FUSREC

Source: Sheet 7 X2-49 Description: Not used - held permanently low due to link fitted to connector X17 on the High Voltage Interface Board (see main equipment wiring diagrams). If used, this input monitors the rectifier (input) fuses and on fuse failure initiates alarm #25 [RECT: FUSE FAIL]. FUSBAT

Source: Sheet 7 X2-50 Description: Battery fuse monitor – this input goes high if the battery fuse ruptures (See section 7 paragraph 2.3.15). The fuse is detected by a micro-switch l ocated on the fuse which, when activated, initiates alarm #57 [BATTERY: FUSE FAIL]. TH

Source: Sheet 7 X2-51 Description: Inverter thermostat monitor – this input goes high if an inverter thermostat opens (overtemperature > 90°C) (See section 7 paragraph 2.3.13). In the event of an overtemperature situation occurring, this input initiates alarm #34 [INV: OVERTEMPERATURE.] and the rectifier and inverter are shut-down 1 minute later accompanied by alarm #62 [CUT-OFF: OVERTEMPER.]. This alarm must be reset by pressing the manual reset push-button (S1). 3.3.11.3

Buf fer D1 – activ ated by CSIN2 SW-BAT

Source: Sheet 7 X2-53 Description: Battery circuit breaker monitor – this input goes low when the Battery switch (or contactor) is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the battery switch is open, this signal initiates alarm #05 [BATTERY SWITCH OPEN].

7-40




OVLINV

Source: Sheet 7 X3-32 Description: Inverter Overload – this input goes high when the inverter is operating in current limit mode (H14 illuminated on the Inverter Logic Board) – (See section 5 paragraph 2.3.7). In an Overload condition, this signal initiates alarm #33 [INV: CURRENT LIMIT]. BLKINV

Source: Sheet 7 X3-33 Description: Inverter Blocked – this input goes high when the Inverter Logic Board is in its ‘stop’ mode (See section 5 paragraph 2.3.8). This can be due to the Inverter Logic Board detecting an internal fault or a ‘stop’ (block) command issued by the UPS Logic Board (See paragraph 3.3.7). The internal fault channel is triggered by either: IGBT desaturation, ribbon cable disconnected, Inverter Logic Board power failure. The external fault channel initiated by the UPS Logic Board will be accompanied by alarm [#30], [#31] or [#32]. XINVI1

Source: Sheet 7 X3-40 Description: Not used – held permanently low due to X13 (2-3) on the Inverter Logic Board which disables this alternative temperature sensor route. The active thermostat route is via [TH> described earlier. XSTAI1

Source: Sheet 7 X5-13 Description: Not used – held permanently low due to X11 (1-2) on the Static Switch Driver Board. No thermostat is fitted on the heatsink. XSTAT2

Source: Sheet 7 X5-14 Description: Inverter output contactor monitor – goes low when the inverter output contactor is closed (load on inverter) and is used by the transfer control logic software routine. LINK X12

Source: On-board jumper X12 Description: The normal position is open – link is closed to disable Initialisation 3.3.11.4

Buf fer D26 – activ ated by CSIN2 MRESET

Source: Sheet 3 – switch S1 Description: RESET switch – goes high when the on-board manual reset switch (S1) is pressed and is used by the micro to unlatch “block commands” issued by some of its software routines.


7-41



BLK-MNS

Source: Sheet 3 – D88 pin 25 Description: ‘Static Switch blocked’ monitor – this input goes high to inform the micro that the static switch control logic (on this Board) is inhibiting the static switch (alarm #16 [BYP: HARDWARE BLOCK ). This can be invoked by any of the following signals applied to D88 (See paragraph 3.3.7.1). – static switch manual inhibit switch (Q1) closed – bypass phase sequence error detected – emergency shutdown operated (latched) – open circuit SCR (latched) – UPS Logic Board power supply failure M-SCR-OP

Source: Sheet 3 – D88 pin 32 Description: ‘Static Switch SCR open circuit’ monitor – this input goes high to inform the micro that an open circuit static switch SCR has been detected (on this Board) (alarm #15 BYP: SCR FAILURE]). This signal is latched within D88 and must be reset using S1 to return to normal conditions. M-ESD

Source: Sheet 3 – D88 pin 29 Description: ‘Emergency shutdown’ monitor – this input goes high to inform the micro that an emergency shutdown (Emergency Stop) has been applied (See paragraph 3.3.7.1) (alarm [#63] [CUT-OFF: EMERGENCY]). This signal is latched within D88 and must be reset using S1 to return to normal conditions. M-BAT-MA

Source: Sheet 3 – D88 pin 20 Description: DC Overvoltage – this input goes high to inform the micro that a ‘DC Overvoltage’ has been detected (See paragraph 3.3.7) (alarm [#58] [DC BUS: FAST OVERVOL.]). This signal is latched within D88 and must be reset by S1 to return to normal conditions. SEQMNS

Source: Sheet 5 – D34 pin 10 Description: Bypass phase sequence error – this input goes high to inform the micro that a ‘Bypass phase sequence error’ has been detected (See paragraph 3.3.14.1). Note that the Rectifier Logic Board detects a phase sequence error on the UPS (rectifier) input mains supply (See section 4 paragraph 2.3.6.1). A phase sequence error initiates alarm [#14] [BYP: PHASE ROT.ERROR] and also ena bles alarm [#16] [BYP: HARDWARE BLOCK] via the micro. EEDO

Source: Sheet 2 – D20 pin 4 Description: Output from the security EPROM to initiate the micro-controller.

7-42




DRDO

Source: Sheet 3 – D18 pin 6 Description: Real Time Clock output (See paragraph 3.3.9). 3.3.11.5

Buf fer D51 – activ ated by CSIN3 I-BST-BAT

Source: Sheet 7 – X7-35 Description: The signal to this input is generated on the Parallel Logic Board when the modules in a 1+1-configured system are connected in ‘common battery’ mode; and is logic high when ‘battery boost’ is requested by either module (see paragraph 2.6.2 on page 8-37). This informs the processor system to command the Rectifier Logic Board to enter Boost Mode (see D17 [REC_A> [REC_B> out puts). I-TST-BAT

Source: Sheet 7 – X7-36 Description: The signal to this input is generated on the Parallel Logic Board when the modules in a 1+1-configured system are connected in ‘common battery’ mode; and is logic high when ‘battery test’ is selected in either module (see paragraph 2.6.3 on page 8-37). This informs the processor system to command the Rectifier Logic Board to enter Battery Test Mode (see D17 [REC_A> [REC_B> out puts). MNS-DIS

Source: Sheet 7 – X7-37 Description: The signal to this input is generated on the Parallel Logic Board, and is applicable only in a 1+1-configured system. It is logic high if the [D_MNS_DIS> output from D50-16 (via X1-49) is driven high in either module. BLK-SEL

Source: Sheet 7 – X7-38 Description: The signal to this input is generated on the Parallel Logic Board when the modules in a 1+1-configured system; and is logic high if the Parallel Logic Board’s selective shutdown circuit is active (LED H1 illuminated on Parallel Logic Board) (see paragraph 2.3.1.1 on page 8-13). MNS-L

Source: Sheet 3 D88-38 Description: This input goes high when the control logic requests ‘load-on-by pass’. This signal is also fed to the Static Switch Driver Board (X5-17) I-SW-BYP

Source: Sheet 7 – X7-59 Description: The signal to this input is generated on the Parallel Logic Board and is logic low when the Maintenance Bypass Switch is closed is either module connected to a 1+1-configured system.


7-43



INV-L

Source: Sheet 3 – D88-36 Description: This input goes high when the control logic requests ‘load-on-inverter’. This signal is fed to the Static Switch Driver Board X5-15 where it initiates the output contactor closure; and it is also connected to the Parallel Logic Board where it enables the current sharing function in a 1+1-configured system (see paragraph 2.5 on page 8-31). INV-DIS

Source: Sheet 7 – X7-32 Description: This input signal is produced by the Parallel Logic Board in a 1+1configured system and is logic when the Parallel Logic Board requests ‘load-on bypass’ (see paragraph 2.3.2 on page 8-15). The signal is also applied to the transfer control logic within D88 (See paragraph 3.3.7.4). 3.3.11.6

Buf fer D60 – activ ated by CSIN3 BLK-EXT

Source: Sheet 7 – X8 pin 11 Description: From external alarms (AS400 interface board). This input provides a means of allowing the inverter to be turned OFF/ON from an external signal via the Remote Alarms Board. The ‘Block’ (OFF) signal is applied as a closed contact across the Remote Alarms Board terminal block X5 pins 1-2. Note: Jumper X6 on the Remote Alarms Board must be selected 2-3 in order to enable this function. BLK-SYN

Source: Sheet 7 – X8 pin 12 Description: Sync disable – this is an input from the optional ‘remote alarm’s board’ (AS400 interface board) which goes high (+5V) when the UPS is “ONGENERATOR” – and is normally used to prevent the inverter synchronising to a frequency-wild standby generator. The On Generator status signal is a pplied as a closed contact across the Remote Alarms Board terminal block X5 pins 3-4. Note: The response to the “ON-GENERATOR” event is programmable via the Operator Control Panel FUNCTION software screen which allows three separate functions to enabled/disabled:

•

Synchro Block – is concerned with the [BLK-SYN> signal mentioned here and, when enabled, prevents the inverter from tracking the bypass frequency when it is being provided by the standby generator. • Charge Inhibit – is concerned with the battery recharge current limit function which, when enabled, reduces the RECTIFIER current limit by 15%. • Current Limit – is concerned with the rectifier input current limit [XRADD1> function which, when enabled, reduces the input current limit by 35%. The reduced current limit functions are employed to lower the potential maximum current demand if the standby generator is undersized.

7-44




BLK-01

Source: Sheet 7 – X8 pin 9 Description: From external alarms (AS400 interface board) Not used. BLK-CHG

Source: Sheet 7 – X8 pin 10 Description: Rectifier Disable – This input provides a means of allowing the rectifier to be turned OFF/ON from an external signal via the Remote Alarms Board. The ‘Block’ (OFF) signal is applied as a closed contact across the Remote Alarms Board terminal block X5 pins 1-2. Note: Jumper X6 on the Remote Alarms Board must be selected 1-2 in order to enable this function. Links X26

Source: Sheet 4 jumper X26 Description: The four sections of jumper X26 are detailed in a Table on the circuit diagram sheet 1 and summarized below: Table 7-7: X26 Jumper details

Open (Standard)

Auto-transfer mode enabled (“on-line” operation). Automatic load transfer from bypass to inverter when the inverter is available – i.e. the inverter is the preferred supply source

Closed

Manual-transfer mode enabled (“off-line” operation). Automatic load transfer from bypass to inverter only when the bypass is unavailable – i.e. the bypass is the preferred supply source. Note: there will be a 3-cycle break on transfer to inverter,

LINK 1-2

Open LINK 3-4

Closed (Standard)

“Inverter voltage fail lockout monitor” enabled. i.e. The inverter is given 5 seconds to reach nominal voltage otherwise it is latched O FF.

Open (Standard)

Enables the “Event History” monitor to store up to a maximum of 10 alarms.

LINK 5-6 Closed

LINK 7-8

3.3.12

“Inverter voltage fail lockout monitor” disabled

Resets the “Event History” monitor. Note: After the 10th “event”, the monitor buffer is full an cannot store any further “events”. The buffer should be reset to 0 after each maintenance or commissioning to enable new “events” to be captured.

Open (Standard)

Password protection enabled.

Closed

Password protection disabled

Data bus out put buff ers (circuit diagram sheet 4). Digital signals generated by the microcontroller as part of its control function are fed to the peripheral circuits via 10 type-74C273 octal latches (See Appendix A.2) which are accessed in pairs to provide a 16-bit data transfer (See Figure 7-8). The


7-45



‘chip select’ signals from D52 provide the latch clock signals and data is therefore transferred through the latches when the appropriate ‘chip select’ signal switches from low to high. A logic low [RSTDX-> reset signal is connected to all the data bus output buffers via jumper X25 (3-2) and drives all their outputs low when ap plied. [RSTDX-> is produced by the microcontroller (See paragraph 3.3.3) and shown on the circuit diagram sheet 2. The remainder of this sub-section lists the digital signals connected through the latches, and provides signal details where appropriate. 3.3.12.1

Buf fers D7 and D10– activ ated by CSDIS

These two devices connect the data bus output to the two on-board 7-segment diagnostic displays (H11 & H12). For a detailed description of the displayed parameters (see paragraph 3.3.17 on page 7-68). 3.3.12.2

Buf fer D17 – activ ated by CSOUT1 XRADD1

Destination: Sheet 7 – X1 pin 37 Description: Reduced current limit – when this output goes high it reduces the Rectifier Logic Board’s input current limit threshold by 35% (See section 4 paragraph 2.3.4.2).

Conditions: This software-selectable output is activated when the UPS is running on ‘standby generator’ as described on page 7-44 ([BLK_SYN>). REC-B & REC-A

Destination: Sheet 7 – X1 pin 38 / 39 Description: Charge mode selection – these two outputs are connected to a decoder on the Rectifier Logic Board where they invoke one of four permissible charge modes (see section 4 table 4-3).

Conditions: These outputs select Test, Boost, Float and Manual charge modes in response to selections made on the Operator Control Panel. The automatic Boost mode parameters, i.e. duration and threshold, are also operator-defined – (see paragraph 2.5.6 on page 2-53). LEDs on the Rectifier Logic Board illuminate to indicate the active charge mode. XAT01 & XATO2

Destination: Sheet 7 – X2 pin 55 / 56 Description: Not used INV-F

Destination: Sheet 7 – X3 pin 37 Description: Base frequency selection – informs the Inverter Logic Board’s ‘staircase pattern generator’ of the UPS system’s base frequency (i.e. 50/60Hz). (See section 5 paragraph 2.3.2).

Conditions: This output is high for 50Hz and low for 60Hz as selected on the Operator Control Panel – see ‘Selecting the UPS SETUP parameters’ in the commissioning procedure (see paragraph 2.4.5.3 on page 2-35).

7-46




INV-B & INV-A

Destination: Sheet 7 – X3 pin 38 / 39 Description: Inverter working voltage selection – these two outputs are connected to a decoder on the Inverter Logic Board where they select one of four permissible charge modes (see section 5 table 5-3).

Conditions: The logic states of these outputs are determined by the working voltage selected by the operator – see commissioning procedure (see paragraph 2.4.5.2 on page 2-34). LEDs on the Inverter Logic Board illuminate to indicate the active selection. 3.3.12.3

Buf fer D25 – activ ated by CSOUT1 XSTAO1 & XSTAO2

Destination: Sheet 7 – X5 pin 19 / 20 Description: Not used RE485-

Destination: Sheet 7 – D58 pin 2 Description: This output selects the ‘Read Enable’ pin of D58, which is an RS485 communications driver connected to the parallel interface connector X7 pins 59/60 – not used. OE485

Destination: Sheet 7 – D58 pin 3 Description: This output selects the ‘Output Enable’ pin of D58, which is an RS485 communications driver connected to the parallel interface connector X7 pins 59/60 – not used. TP5

Destination: Sheet 7 – X18 pin 5 Description: Not used (test point for system software). OUTBAT

Destination: Sheet 2 – V152 Description: This output, when high, ‘enables’ the on-board Ni-Cad battery charger.

Conditions: This output enables the Ni Cad battery charger if its voltage falls to 2.8Vdc and disables it again once the battery voltage rises to 3.6V. Note: when the charger is enabled the [INTERNAL BATTERY LOW] warning is annunciated (alarm [#76] active). 3.3.12.4

Buf fer D9 – activ ated by CSOUT2 EECS / EESK / EEDI

Destination: Sheet 3 – D18 pin 7 Description: These outputs control the data acquisition of EEPROM D20


7-47



ORCS

Destination: Sheet 3 – D18 pin 7 Description: Real Time Clock (RTC) ‘chip select’ (See paragraph 3.3.9). ORSK

Destination: Sheet 3 – D18 pin 4 Description: Real Time Clock (RTC) ‘serial communications clock input’ (See paragraph 3.3.9). ORDI

Destination: Sheet 3 – D18 pin 5 Description: Real Time Clock (RTC) ‘serial data input’ (See paragraph 3.3.9). SELANA / SELANB

Destination: Sheet 6 Description: These two outputs are connected to the address inputs of three 2 pole multiplexers which select the analogue signals for the microcontroller’s A/D inputs – e.g. selecting the analogue signals for display purposes (kVA values are calculated in software using V x I). 3.3.12.5

Buf fer D21 – activ ated by CSOUT2 ALMRES

Destination: Sheet 3 – D22 pin 1 Description: Software controlled RESET – This output, when high, resets the Emergency Shutdown, DC Overvoltage and Open SCR fault latches within D 22.

Conditions: This facility is not programmed into the current software and it is therefore not used. INV-ON

Destination: Sheet 3 – D88 pin 17 Description: ‘Inverter ON’ request – This output, when high, requests D88 to issue an [ON_INV> command signal which is connected to the Inverter Logic Board and turns ON the inverter – provided other D88 inputs are correct (See paragraph 3.3.7).

Conditions: (see paragraph 7.2.3 on page 7-160) L-INV

Destination: Sheet 3 – D88 pin 14 Description: ‘Load-on-inverter’ request – This output is connected to the load transfer control logic within D88 where it is interlocked with the [BLK_INV> and [C_L_INV> signals within D88 (See paragraph 3.3.7.4). This signal is high when the processor system requests ‘load-on-inverter’.

Conditions: (see paragraph 7.2.10 on page 7-180)

7-48




L_MAINS

Destination: Sheet 3 – D88 pin 41 Description: ‘Load-on-bypass (mains)’ request – This output is connected to the load transfer control logic within D88 where it is interlocked with several other signals within D88 (See paragraph 3.3.7.4). This signal goes high when the processor system requests ‘load-on-bypass’.

Conditions: (see paragraph 7.2.10 on page 7-180) REC-ON

Destination: Sheet 3 – D88 pin 40 Description: ‘Rectifier ON’ request – This output, when high, requests D88 to issue an [ON_REC> command signal, which is connected to the Rectifier Logic Board and turns ON the rectifier (provided other D88 inputs are correct (See paragraph 3.3.7)).

Conditions: (see paragraph 7.2.2 on page 7-158). IBOPEN

Destination: Sheet 3 – D88 pin 12 Description: Trip battery circuit breaker– This output, when high, requests D88 to issue a [BAT_TRP> command signal which is connected to the High Voltage Interface Board and turns OFF the battery circuit breaker driver transistor.

Conditions: This signal is software driven via a programmable parameter setting entered from the Operator Control Panel to trip the battery circuit breaker when the battery is fully discharged (see page 2-37). The Emergency Shutdown and DC Overvoltage inputs to D88 pins 9 and 8 also trigger the battery trip signal when active (See paragraph 3.3.7). TP6

Destination: Sheet 7 – X18 pin 6 Description: Not used (test point for system software). 3.3.12.6

Buf fer D50 – activ ated by CSOUT3 O_BLK_SW

Destination: Sheet 7 – X1-43 Description: This output is used in a multi-module system only and has no affect in a single-module or 1+1 system. In a multi-module system the output is connected to the Parallel Logic Board where, when high, it turns off the inverters in all the modules connected to the system. O_MNS_L_SS

Destination: Sheet 7 – X1-44 Description: This output is used in a multi-module system only and has no affect in a single-module or 1+1 system. In a multi-module system the output is connected to the Parallel Logic Board where, when high, it opens the output contactor in every module when a transfer to bypass is commanded.


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O_MNS_D_SS

Destination: Sheet 7 – X1-45 Description: This output goes high when the bypass supply parameters are deemed valid by the processor system. This is connected to the ‘bypass frequency validation circuit on the Parallel Logic Board where it determines if the GVCO is allowed to synchronise to the bypass (see paragraph 2.4.4.1 on page 8-27). TST_BAT

Destination: Sheet 7 – X1-46 Description: This output goes high when the processor system requests a ‘battery test’ function and is connected to the Parallel Logic Board. If the UP S is configured as a 1+1 system with common battery, the Parallel Logic Board passes this signal along the parallel control bus where it switches both modules to the battery test mode – i.e. ensures both modules operate at the same charge voltage (see paragraph 2.6.3 on page 8-37). BST_BAT

Destination: Sheet 7 – X1-47 Description: This output goes high when the processor system requests a ‘battery boost’ function and is connected to the Parallel Logic Board. If the UPS is configured as a 1+1 system with common battery, the Parallel Logic Board passes this signal along the parallel control bus where it switches both modules to the battery boost mode – i.e. ensures both modules operate at the same charge voltage (see paragraph 2.6.2 on page 8-37). MNS_SYN_KO

Destination: Sheet 7 – X1-48 Description: This output goes high when the processor system senses that the Inverter Logic Board has achieved internal synchronism and is connected to the Parallel Logic Board. If the UPS is configured as a 1+1 system this is used by the GVCO synchronisation control system as part of its inter-module synchronisation function (see paragraph 2.4 on page 8-19). O_MNS_DIS

Destination: Sheet 7 – X1-49 Description: This high signal is connected to the Parallel Logic Board via X149 which, via the parallel control bus, immediately returns a logic low [MNS_DIS> signal back to X1-37 in both modules of a 1+1 configured system. This is input to the processor system via D51-4. 3.3.12.7

Buf fer D55 – activ ated by CSOUT3 PAR_REC

Destination: Sheet 7 – X7-51 Description: This signal is driven high by the processor system when it requests ‘parallel rectifier’ operation. It is connected to the Parallel Logic Board where it energises relay K5, whose contacts complete the rectifier current sharing control circuit.

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OUT-03

Destination: Sheet 7 – X8 pin 31 Description: Output to Parallel Logic Board Conditions: Not used in a 1+1-configured system. OUT-03

Destination: Sheet 7 – X8 pin 25 Description: Output to I/O interface (remote alarms, AS400 interface etc.). Conditions: Not used MNS-KO

Destination: Sheet 7 – X8 pin 26 Description: Output to I/O interface (remote alarms, AS400 interface etc.). Conditions: Logic high if mains (bypass) supply error – i.e. overvoltage [#11], undervoltage [#12], absent [#10] or bypass blocked [#17]. BATED

Destination: Sheet 7 – X8 pin 27 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Logic high if the battery voltage falls to its end-of-discharge level [#56] – as set by operator through Operator Control Panel (see page 2-37). It is also active if the battery breaker is open [#05] or the battery fuse is open [#57]. CHG-INH

Destination: Sheet 7 – X8 pin 28 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Logic high if the battery charger is inhibited (driven by the [BLK-CHG> signal described on page 7-45). Jumper X4 pins 1-2 must be linked on

the Alarm Board. SWBYP

Destination: Sheet 7 – X8 pin 29 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Logic high if maintenance bypass isolator is closed – accompanied by alarm #06 [MANUAL BYPASS CLOSED] . OUT-01

Destination: Sheet 7 – X8 pin 23 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Not used in the present software implementation


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3.3.12.8


Buf fer D54 – activ ated by CSOUT4 OUT-02

Destination: Sheet 7 – X8 pin 24 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Not used in the present software implementation OVT-BAT

Destination: Sheet 7 – X8 pin 18 Description: Output to I/O interface (remote alarms, AS400 interface, Remote Alarms Monitor etc).

Conditions: Logic high in the event of battery overtemperature – Not used in the present software implementation. SYN-KO


Conditions: Logic high if the inverter is unsynchronised to the bypass supply – i.e. if the phase displacement is more than ±9°. This condition will initiate alarm #35 [INV: UNSYNCHRONISED] . ALL-GEN

Destination: Sheet 7 – X8 pin 17 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: This is the “Common Alarm” output to the Alarm Board and is active if any of the following alarms are present: [#05], [#06], [#10], [#11], [#12], [#16], [#17], [#24], [#33], [#34], [#52], [#56], [#57], [#66]. A400ON

Destination: Sheet 7 – X8 pin 31 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: This alarm is active when the load is on the UPS (inverter or by pass) and is interlocked with the Maintenance Bypass being closed. A400UF

Destination: Sheet 7 – X8 pin 32 Description: Output to I/O interface (remote alarms, AS400 interface etc). Condition: Mains Failure alarm; enabled by alarm [#01] and active when [#22] is energised. A400BL

Destination: Sheet 7 – X8 pin 33 Description: Output to I/O interface (remote alarms, AS400 interface etc).

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Conditions: Low Battery warning; enabled by alarm [#01] and active when [#56] is energised. A400BY

Destination: Sheet 7 – X8 pin 34 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Load on Bypass; active when alarm [#18] is energised. 3.3.12.9

Buf fer D56 – activ ated by CSOUT4 MNSREC

Destination: Sheet 7 – X8 pin 20 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Rectifier input voltage failure – active when H9 is illuminated on the Rectifier Logic Board. CS-KO

Destination: Sheet 7 – X8 pin 19 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Bypass-side Static Switch blocked – goes high if a fault is detected on the static switch (alarm [#16] present). BAT-DSC

Destination: Sheet 7 – X8 pin 13 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Battery discharging – active when alarm [#22] is present. OVL

Destination: Sheet 7 – X8 pin 14 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Overload – active when alarm [#33] or [#66] is present. OVT-DIS

Destination: Sheet 7 – X8 pin 15 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Overtemperature – active when alarm [#24] or [#34] is present. OVT-AMB

Destination: Sheet 7 – X8 pin 30 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Output Air overtemperature – not used. XINV01

Destination: Sheet 7 – X3 pin 24


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Description: Mains error inhibit to Inverter Logic Board transfer control. Conditions: On the Inverter Logic Board a circuit within D11 provides a control signal [RIF> which briefly transfers the voltage reference signal t o the bypass supply just before the ‘inverter-side’ contactor is closed; (see paragraph 2.3.3 on page 5-45) . This signal, [XIN01>, goes high to inform the Inverter Logic Board of a mains (bypass) voltage error and prevents the switch-over to the bypass supply reference from taking place; and so prevents the inverter locking to an out-of-spec voltage. TP7

Destination: Sheet 7 – X18 pin 7 Description: Not used (test point for system software).

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3.3.13

Frequency sensin g and cont rol sign als Figure 7-9: Frequency synchronisation control

Parallel logic

54

X7 2

D42

X18-2 62 15

D53

X2 5

F-INM

VI-A

15

X4

X3 4

BACKM

[O_BACK>

34

BACK

D17 DATA BUS D54

34

INV-F

15 INV-F 50 /60 Hz selection

37

D1

37 Clock signals to tri-wave generator

SYNC-KO

6

44

Frequency Divider

Sync error detection

D60

2

SYNCM

5

)

X34:2-3 = Single 1-2 = Parallel 14 1 D59 SYNC

50/60Hz signal synchronised to bypass (when present)

15

UPS Logic B oard

Important Note:

5V

2

3 Master Freq reference for Inverter Osc (correction)

R247 phase align

z K H k L 8 C 8 2 4

BLK-SYN

(M:S variations

27

43

Sync Inhibit

64

8Vp-p

F-IN

X18-3 63 16

R E L L O R T N O C O R C I M

Bypass supply R-phase voltage sensing

35

35

Phase Locked D1 Loop 20 21 14 SYNC

z H 0 6 / 0 9 5

VCO 13

Phase Comparator

D6 3

Inverter Logi c Board

This section describes the frequency control operation for a ‘single-module’ installation – i.e. where the module is operating as a single, stand-alone UPS system. Where the module is part of a ‘1+1 System’, the control operation is very similar except that the “bypass R_phase supply” signal to which the u nit attempts to synchronise is obtained from the Parallel Logic Board, and is subject to a complex inter-module synchronisation regime. To understand to synchronisation principles o f a ‘1+1’ system, you are advised to read section 8 paragraph 2.4 prior to this section.

3.3.13.1

Frequency contr ol princ iples

The inverter frequency is determined by the VCO section of a phase locked loop i.c. (D6) on the Inverter Logic Board which provides a 288kHz (nominal) clock signal to a frequency-divider (within D1) which then clocks the multiplexers in the ‘reference voltage generator’ circuit section 5 paragraph 2.3.2.

s7-c3c .fm5 - Issu e 2 Dated 21/08/97

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Base frequency selection

The inverter base frequency is selected via the Operator Control Panel during commissioning and is read by the microcontroller through the CAN bus. The micro responds by appropriately setting the [INV-F> output from D17-15 – Low = 50Hz and High = 60Hz. This is connected to the ‘frequency divider’ on the Inverter Logic Board where it determines the division factor – i.e. when [INV-F> is low the 288kHz VCO output is divided by 5760 to produce a 50Hz output at D1-27; when [INV-F> is high the division is 4800 and produces a 60Hz output. Frequency synchronisation

It is desirable that the inverter output is synchronised to the bypass supply under normal operating conditions as this enables a ‘closed’ load transfer to be carried out in the event of a UPS fault – where-by the static switch SCRs are turned on at the same time as the inverter contactor is opened, and the load does not experience a supply break. If the inverter is not synchronised to the bypass supply there could be a large voltage difference across the static switch SCRs while the load is ‘on-inverter’ (i.e. SCRs OFF) which might damage the UPS/load equipment during a subsequent ‘closed’ transfer: in such circumstances an ‘open’ transfer takes place if the UPS develops a fault, where-by the inverter contactor is opened prior to turning ON the static switch SCRs. This causes a load supply break of up to 1 second, which is an inbuilt feature designed to avoid load damage. The frequency synchronisation control mechanism is quite complex and effectively based on two nested phase locked loops. The inner loop comprises D6 on the Inverter Logic Board and the outer loop is functionally provided by the microcontroller, under software control. 3.3.13.2

Frequency sync control and operation Inverter Logic Board phase-locked-loop (assuming 50Hz operation.)

The ‘phase comparator’ section of D6 compares the 50Hz output from D1-27, connected to D6-3, with a frequency reference signal annotated [SYNC> which is produced by the microcontroller and connected to D6-14 (available at test point X18-4). If the ‘phase comparator’ detects any phase difference between these two signals its output at D6-13 will modify the VCO’s frequency in such a way as to make the ‘frequency divider’ output at D1-27 match the [SYNC> signal frequency – i.e. the VCO frequency will be modified until the ‘phase comparator’ within D6 sees no error between these signals, whereupon the circuit can be considered to be phase-locked . Thus the inverter frequency tracks the [SYNC> signal ‘reference’ frequency. [SYNC> signal generation (assuming 50Hz)

The microcomputer monitors the bypass supply R-phase waveform [VI-A> via a comparator which extracts its frequency information, [F-INM>. This signal can be seen at X18-2 as a squarewave coinciding with the bypass supply R-phase zerocrossing points. The Inverter Logic Board frequency divider’s 50Hz output (D127) is also monitored and is available at X18-3, annotated [BACKM>. Under software control, the micro operates on these two signals in the same way as described above for the Inverter Logic Board’s phase-locked-loop. That is, it performs the ‘phase comparator’ and ‘VCO’ functions described above and produces a 50Hz output, [SYNC>, whose absolute frequency is controlled by the de-

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s7-c3c.fm5 - Issue 2 Dated 21/08/97



tected phase difference between [F-INM> and [BACKM> – i.e. the width of the pulse is directly proportional to the amount of phase difference. Example of sync control

The overall operation of the synchronisation control circuits can best be explained by example. Consider the case where the bypass frequency suddenly jumps from 50Hz to 50.5Hz: 1. The micro will sense the jump in bypass frequency through a rise in [F-INM> to 50.5Hz. 2. The micro will sense a phase error between [F-INM> and [BACKM> due to their frequency difference and will ramp-up the [SYNC> signal frequency because it senses that the bypass frequency is higher than that of the inverter. Note: ramp-up speed is controlled under a slew rate software program factory set at 0.1Hz /Second. 3. The ‘phase comparator’ in the Inverter Logic Board’s phase-locked-loop will see the ramping [SYNC> frequency and detect that it is now higher than the frequency divider’s ‘50Hz’ output. 4. The phase comparator error output (pin 13) will call for an increase in VCO frequency, which will thus increase the ‘frequency divider’ clock rate and thereby demand an increased inverter frequency. 5. The ‘50Hz’ outputs from the frequency divider also ramp-up in line with the inverter frequency and have two affects: a) The increasing output at D1-27 is fed back to the phase-locked-loop (D6-3) where it maintains phase-lock – i.e. it ties the clock frequency to the [SYNC> signal and maintains close tracking of this signal. b) The same increasing output from D1-27 is fed back to the microcontroller via R247 where it allows the phase error function to maintain a close check on the ‘bypass/inverter’ frequency and phase relationship. 6. When the inverter frequency has risen to match the 50.5Hz bypass frequency, and the [F-INM> and [BACKM> signals are in phase: a) The [SYNC> frequency will stop ramping up and remain at 50.5Hz, synchronised to the bypass supply due to the action of the micro. b) The VCO clock frequency will remain constant – i.e. 290.88kHz (5760 x 50.5 – as 5760 is the divider factor for 50Hz systems). c) The output from D1 pin 27 will be steady at 50.5Hz and synchronised to the [SYNC> signal. 7. If [SYNC> is synchronised to the bypass supply (6a) and the frequency divider outputs/inverter are synchronised to the [SYNC> signal (6c) then this results in the inverter being effectively synchronised to the bypass supply, are required.

Important notes: The above description requires qualification by the following notes. a) The internal mechanism of the frequency divider chip ties its ‘50Hz’ out puts to the zero-crossing points of the R-phase inverter voltage. Thus, as the micro uses the bypass R-phase supply as its frequency sensing source, this effectively ensures that the inverter and bypass supplies are synchronised correctly from a phase alignment viewpoint.


7-57



b) To aid description the above example assumed that the bypass frequency underwent a stepped change; however, in practice any change in bypass frequency is likely to occur gradually: in which case the circuit dynamics are usually able to maintain a phase-locked condition during the period of change, resulting in the inverter frequency tracking the bypass frequency at all times without incurring a detectable phase error. c) The synchronising ‘window’ and ‘slew-rate’ are adjustable and selected from the Operator Control Panel setup menus. The ‘window’ defines the limits to which the inverter is allowed to track the bypass frequency and normally set to ±2%; while the ‘slew-rate’ defines the maximum permitted rate-of-change of inverter frequency and is usually set to 0.1Hz/s.– i.e. this determines the fastest rate of change of bypass frequency tolerated by the synchronisation circuit whilst maintaining sync. If the bypass frequency goes outside the permitted window for longer than 1 minute, the inverter frequency will return to its base frequency and await the mains return within the sync window, where-upon it will re-synchronise. An [INV:UNSYNCHRONIZED] (alarm #35) warning will be dis played while this situation is in effect. d) In the event of a bypass supply failure the microcontroller will drive its [SYNC> output to the ‘centre’ frequency – i.e. 50Hz. Sync phase adjustment

R247 is connected to a ‘phase-shift’ circuit on the Inverter Logic Board and provides the means for trimming any error in the phase relationship between the inverter [BACKM> and bypass [F-INM> sense signals once the sync control circuit is phase-locked – due mainly to component tolerances. Therefore, once the inverter is synchronised this resistor can be adjusted to reduce the residual phase difference between the inverter R-phase output and the bypass R-phase supply. 3.3.13.3

Non-Sync detecti on and alarm

An alarm condition [SYN-KO> is flagged by the microcontroller when it detects that the [BACKM> and [F-INM> signals are more than 11° out-of-phase. This is communicated to the Operator Logic Board via the CAN bus and also, via D54-6, to the I/O interface connector X8-16 where it can be used to provide a remote alarms indication (sheet 7). [SYN-KO> is ‘high’ when a non-sync condition is present. 3.3.13.4

External ‘sync inhibi t’

In certain circumstances it may be necessary to inhibit the synchronisation loop – for example when supplying the UPS from a stand-by generator whose frequency regulation is poor. This can be achieved by an external input via the I/O connector X8-11 [BLK-SYN> which is connected to the microcontroller via D60-2. This input must be taken ‘high’ to inhibit the synchronisation function (See paragraph 3.3.11.6). Note: The control can be activated only after being ‘enabled’ in the ‘ Function’ parameter software setup screen (see paragraph 2.4.7.3 on page 2-43).

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3.3.14


Analo gue sig nal pro cessing The UPS Logic Board monitors the UPS input voltage, output voltage, inverter voltage, battery voltage, output current and battery current. These inputs are processed by analogue circuits (sheets 6 & 7) which provide appropriate signals for the microcomputers A/D input port. In some cases the inputs are also converted to digital alarm/status signals which are connected to the micro via the data bus.

3.3.14.1

Bypass voltage signal processi ng

Figure 7-10: Bypass voltage sensing block diagram Line-Neut

Line-Line

N6 Buffer

N29 Sum-Amp

3-Phase Bypass Volts Sense

+5V +2.5V 0V

VIABM To A/D Multiplexers (Display uses)

VIBCM VICAM REF-2 (2.5V)

8Vp-p

N29d Rectifier

[SVI>

To SCR OPEN det.

[SVIM> To A/D Multiplexers (Bypass volts monitor)

A-Ph

B-Ph

N14 Filter

N14 Filter

[F-IN> To Micro

(sync control - bypass R-ph)

D27 Ph-Seq

[SEQMNS> To Micro (Phase Sequence error detector)

Voltage sensing

The bypass voltage sense signals ( [VI-A> - [VI-C>) are developed on the High Voltage Interface Board (See paragraph 2.3.6) and connected via X2 pins 15, 16, 17 to N6b/c/d which are unity-gain buffers (sheet 5). The signals at N6 outputs therefore equate to approximately 1% of the bypass supply line-neutral voltage (e.g. 2.4Vrms at 240V working) and are connected to several blocks as shown in Figure 7-10. Voltage monitoring

N29a-c take the line-to-neutral sense voltages produced by N6 and converts them into line-to-line sense voltages suitable for connecting to the microcontroller A/D inputs. Taking N29a as an example; this amplifier differentially sums the [VI-A> and [VI-B> signals from N6 and produces the [VIABM> L-L signal. However the amplifier attenuates the resultant signal to about 30% (e.g. 1.38V for 240V w orking) due to its feedback resistance ratios: also, the non-inverting input is connected to VREF-2 (2.5V reference voltage) rather than to the 0V rail, which therefore applies a 2.5V offset to [VIABM>. Thus in a 240V system working at nominal voltage [VIABM> is approximately 3.9Vp-p centred on a 2.5V reference. This signal sits well within the microcontroller’s A/D 0-5V input level, a nd is shown connected to the A/D multiplexer circuit (sheet 6). Note: if the bypass voltage is missing [VIABM> will be 2.5Vdc due to the absence of any ac signal.


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Bypass frequency and phase sequence monitors

The bypass R-phase signal [VI-A> from N6-14 is connected to a zero-crossing circuit comprising N14a/d which produces a squarewave output [F-IN> at D34-6 which coincides with the R-phase zero-crossing points. This signal is used by the microcontroller in its frequency synchronisation control (See paragraph 3.3.13.1). A similar squarewave coinciding with the S-phase is obtained via N14b/c and buffered by D34-8. These two squarewave signals are connected to a D-type flipflop (D27) which detects their phase relationship. Under normal circumstances the R-phase signal should lead that of the S-phase; therefore when the rising-edge R-phase signal clocks D27, its data ( D) input should be ‘low’, producing a permanent ‘high’ on its Q output which inverted to a ‘low’ [SEQMNS> signal at D34-10. In the event of a phase sequence error, D27 will have a permanent ‘low’ clocked through to its Q output and produce a ‘high’ [SEQMNS> signal. [SEQMNS> is connected to the microcontroller via the data bus buffer D28-7

where it flags a phase rotation error – [BYP: PHASE ROT.ERROR] alarm #14 (See paragraph 3.3.11.4). 3-phase voltage monitor

A full-wave, three-phase diode bridge comprising V34-V36 & V40-V42, produces a dc voltage proportional to the full three-phase supply which is fed to N29d. This amplifier attenuates the signal by 55% due to the values of the feedback resistors; therefore the output at N2-14 is approximately 2.5Vdc at nominal working voltage. Note that this is a ripple voltage since there is very little capacitance around the amplifier. Thus if any bypass phase voltage goes out of tolerance (e.g. ±10% window) the detector will sense the error. It does not require all three phases to go outside the error window. N2-14 provides signals to two other areas: [SVIM> is connected to the microcontroller A/D input via the multiplexer circuit shown on sheet 6 and used by the micro to monitor the bypass voltage for a each individual phase (e.g. ±10% voltage error); and [SVI> is connected to the circuit (also on sheet 6) which detects an open circuit static switch SCR. 3.3.14.2

Inverter vol tage sensi ng

Figure 7-11: Inverter voltage sensing block diagram error detected on individual phase

8Vp-p

2.2Vdc

Line-Neut 3-Phase Inverter Volts Sense

N3a-c Buffer

N3d Rectifier

[SVINVM> To A/D Multiplexers

Voltage sensing

The inverter voltage sense signals ( [VINV-A> - [VINV-C>) are developed on the High Voltage Interface Board (See paragraph 2.3.5) and connected via X2 pins 18, 19, 20 to N3a-c which are unity-gain buffers (sheet 5). The signals at N3 outputs therefore equate to approximately 1% of the inverter line-neutral voltage. A fullwave, three-phase diode bridge produces a dc voltage proportional to the full three-phase output which is then fed to N3d. This amplifier attenuates the signal

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by 55% due to the values of the feedback resistors; therefore the output at N3-14 is approximately 2.5Vdc at nominal voltage, and connected to the microcontroller A/D input via the multiplexer circuit s hown on sheet 6. This is a ripple voltage as described previously, and is monitored by the inverter voltage error software function (i.e. ±10%). 3.3.14.3

Batter y (bus) vol tage sensi ng

Figure 7-12: Battery voltage sensing block diagram [VBM> 3.25Vdc @ 446V(bat)

To A/D Multiplexers

N13a Buffer

[V-B>

N13c Comparator

[BAT-MA> DC Overvoltage (Fast) (set to 620V(bat))

Battery volts monitor

The DC busbar (battery) voltage sense signal [V-B> is developed on the High Voltage Interface Board (See paragraph 2.3.3) and connected via X2 pin 27 to N13a which is a unity-gain buffer (sheet 5). The signal sensitivity is set on the High Voltage Interface Board to approximately 7.3mV per Volt (bat) therefore [VBM> is about 3.255V at nominal 446V float charge voltage. This signal is connected to the microcontroller A/D input, via the multiplexer circuit shown on sheet 6, where it is used by several software functions, such as: display metering; slow DC overvoltage (max 2.4V/cell window); Low Battery warning (1.82V/cell window); End of Discharge (1.67V/cell window); and % Charge/autonomy Time algorithms. DC Overvolts detection (Fast) [VBM> is also monitored by N13c, which is configured as a comparator and used

to detect a DC Bus overvoltage condition. N13c has a fixed threshold which operates ([BAT-MA> goes high) when [VBM> reaches approximately 4.45V, which equates to a DC Bus voltage of around 620Vdc. [BAT-MA> is connected to the ‘Basic System Control Logic’ where it trips the bat-

tery circuit breaker, turns off the rectifier and inverter, and trips a latch (See paragraph 3.3.7.1). In an overvoltage situation – [DC BUS: FAST OVERVOL.] alarm #58 – the ‘Basic System Control Logic’ responds by issuing a ‘high’ [MBATMA> signal which flags the micro-controller via data bus buffer D26 (See paragraph 3.3.11.4). 3.3.14.4

Batter y cur rent sensi ng

Figure 7-13: Battery current sensing block diagram REF-2 (2.5V)

[I_B> [I_B_P>

N13b Buffer

[IBM> To A/D Multiplexers

X36: 1-2 = Separate battery 2-3 = Common battery


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Battery current monitor

The battery current sense signal [I_B> is developed on the High Voltage Interface Board (See paragraph 2.3.22) and connected via X2 pin 31 to N13b which has a gain of approximately1.5 (sheet 5). The signal sensitivity is set on the High Voltage Interface Board by jumper X38 and the output [IBM> is connected to the micro-controller A/D input via the multiplexer circuit shown on sheet 6 where it is used for display purposes, and % Charge and Autonomy Time algorithms. I_B_P is used in a 1+1 installation when the rectifier is paralleled in order to share

current in a common battery system (see paragraph 2.6.1 on page 8-36) 3.3.14.5

Outpu t vol tage sensi ng

Figure 7-14: Output voltage sensing block diagram +5V +2.5V

Line-Line 3-Phase Output Volts Sense

N5 Buffer

N31 Sum-Amp

0V

VOABM VOBCM VOCAM REF-2 (2.5V)

8Vp-p

N15a Rectifier

[SVI>

To A/D Multiplexers (Monitoring & display)

[SVOM> To A/D Multiplexers (Critical bus monitor)

N15b-d Comparator

[SCROPN> To Micro (SCR open cct.)

Line-Neut N30 Buffer

VOAM VOBM VOCM

To A/D Multiplexers (monitoring & display)

REF-2 (2.5V)

Voltage sensing

The bypass voltage sense signals ([VO-A> - [VO-C>) are developed on the High Voltage Interface Board (See paragraph 2.3.6) and connected via X2 pins 21, 22, 23 to N5a-c which are unity-gain buffers (sheet 6). The signals at N5 outputs therefore equate to approximately 1% of the output line-neutral voltage (e.g. 2.4V (8Vp-p) at 240V) and connected to several blocks as shown in Figure 7-14. Voltage monitoring

The signals from N5a-c are connected to two sets of buffers which provide lineto-neutral and line-to-line monitoring voltages which are connected to the microcontroller A/D inputs via the multiplexer circuit shown on sheet 6 and used for metering & display purposes.

L-N voltage monitoring. is provided by N38a-c which attenuate the voltage sense signals by approximately 55% and also applies a 2.5Vdc offset due to the non-inverting connection being terminated at VREF-2 (2.5V reference voltage). At 240V nominal voltage the monitor output signals [VOAM>, [VOBM>, VOCM> are therefore 1Vrms (2.8V p-p) centred about a +2.5V reference which sits well within the microcontroller’s A/D 0-5V input level.

7-62




Note: if the output voltage is missing [VOAM> etc. will be 2.5Vdc due to the absence of any ac signal.

L-L voltage monitoring. is provided by N31a-c. Taking N31a as an example; this amplifier differentially sums the A and B phase signals from N5 and produces the [VOABM> L-L signal. However, the amplifier attenuates the resultant signal by about 70% (e.g. 1.38V for 240V working) due to its feedback resistance ratios: also, as with the L-N circuit described above, the non-inverting input is connected to VREF-2 (2.5V reference voltage) rather than to the 0V rail, which applies a 2.5V offset to [VOABM>. Thus in a 240V system working at nominal voltage [VOABM> is approximately 3.9Vp-p centred on a 2.5V reference. 3-phase voltage monitor

A full-wave, three-phase diode bridge comprising V29-V31 etc, produces a dc voltage proportional to the full output three-phase supply which is fed to N15a. This amplifier attenuates the signal by 55% due to the values of the feedback resistors; therefore the [SVOM> output at N15-1 will be approximately 2.5Vdc at nominal working voltage. Note that this is a ripple voltage s ince there is very little capacitance around the amplifier. [SVOM> is connected to the microcontroller Ato-D inputs via the multiplexer circuit shown on sheet 6. This is used by the micro-controller as a critical bus voltage error monitor (factory set to ±10%) for transfer functions. Open Circuit Static Switch SCR detection

As shown in Figure 7-14, the output voltage (3-phase) sense signal [SVOM> and bypass voltage (3-phase) sense signal [SVI> are both connected to the Static Switch ‘SCR open circuit’ detector. 3.3.14.6

Output curr ent sensing

Figure 7-15: Output sensing block diagram REF-2 (2.5V)

3-Phase Output Current Sense

N4a-c Buffer

N4d Sum-amp

[IOAM> [IOBM> [IOCM>

[IONM> To A/D Multiplexers (Overload & Timers)

(Display Metering)

Output current monitor

The UPS output current sense signals ( [IO-A> - [IO-C>) are developed on the High Voltage Interface Board (See paragraph 2.3.19) and connected via X2 pins 32, 33, 34 to N4a-c which attenuate the sense signals by approximately 75% and also applies a 2.5Vdc offset due to the non-inverting connection being terminated at VREF-2 (2.5V reference voltage). The output signals [IOAM> etc. are connected to the microcontroller A/D inputs via the multiplexer circuit, and the 2.5V offset is sufficient to make the a.c. current signal sit within the 0-5V A/D input voltage range. These signals are by the micro’s ‘overload’ algorithm (i.e. 150% for 1


7-63



minute, 125% for 10 minutes, 110% for 1 hour, 101% for 9 hours). They also represent the values shown on the Operator Control Panel ‘ Measurements’ display screen. N4d calculates the neutral current by differentially summing the three line currents – in a balanced three phase system the algebraic sum of the currents should equal zero, thus if the system is unbalanced then the amount of imbalance represent the current flowing in the neutral path. The neutral current signal [IONM> is also subject to the 2.5V offset and applied to the microcontroller A/D inputs via the multiplexers in the same way as the line current signals. 3.3.14.7

Analogue signal monit oring multi plexers

The microcontroller has ten A/D inputs ( [AN0> to [AN9>). [AN6> to [AN9> are fed by fixed inputs signal sources; however, [AN0> to [AN5>

are fed via a series of multiplexers which allow the micro to select from various signal sources. Three type 4052 multiplexers are used for this purpose, each addressed by two signals ([SELANA> and [SELANB>) produced by the microcontroller via data bus buffer D9 (See paragraph 3.3.12.4). Sheet 6 contains the multiplexer circuit and illustrates the various monitored signals connected to t heir data pins (See Appendix A.3) . The multiplexers are inhibited if the -12V power supply monitor detects an undervoltage by applying a logic high [FL-12-> to the multiplexer inhibit inputs (pin 6) (See paragraph 3.3.15.3). Note: the inputs annotated [T1> - [T4> are temperature sensing inputs – refer to the High Voltage Interface Board description (See paragraph 2.3.12). Note: the micro can access the A/D signals in parallel and where necessary can calculate values for the display – e.g. kW = V x I.

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3.3.15 3.3.15.1

Power supp lies General descripti on and voltage regulators

The UPS Logic Board ±12V power supply rails are provided from two parallel sources and will be available if either source is live. The first source is from the Rectifier Logic Board, which is itself powered from the AC-DC Power Supply and available whenever the UPS input (rectifier) supply is live (see paragraph 2.1 on page 3-5); the second if from the Inverter Logic Board, which is powered from the DC-DC Power Supply and is available whenever the rectifier is working or the batteries are connected to the DC Busbar (see paragraph 3.1 on page 3-7). From the UPS Logic Board the ±12V supplies are passed directly to all the remaining circuit boards and the communications port etc. 3.3.15.2

Reference vol tage generator s

Several devices require a stable +5V power supply which is provided by a simple 3-terminal +5V regulator (N1), shown on sheet 7. In addition to the +5V power supply rail, there are also two reference voltage generators on the circuit board. One generates a regulated +5V, [VREF>, from the +12V line and the other generates a regulated 2.5V output, [VREF-2>, from the +5V supply rail. These reference voltages are used in conjunction with the microcontroller’s A/D analogue inputs and are shown on sheet 5 of the circuit diagram. +5V reference voltage [VREF>

This provides a stable power supply for the A/D converters within the micro which is necessary for them to maintain their conversion accuracy. 2.5V reference voltage [VREF-2>

The micro-controller’s internal A/D converters operate on stable 0V and +5V power rails, as described above. Therefore if an AC signal is to be monitored (e.g. bypass voltage), or a positive-and-negative going DC signal (e.g. battery current), then a 2.5V offset is required shift the 0V point of the monitored signal into the centre of the A/D converters’ input working range. This enables the A/D circuit to convert both halves of an AC waveform and both positi ve and negative transitions of a dc signal voltage. 3.3.15.3

-12V und ervol tage detecto r

Comparator N45a (sheet 5) serves as a -12V supply rail monitor and detects when the -12V is less than approximately -9.8V. The operating threshold for this circuit is set by V70 which applies a zener referenced voltage across R242/243 from the +12V rail and under normal conditions sets N45-3 at about 1.86V. The -12V rail is monitored via a resistor divider (R240/241) which is fixed at +3V at one end by V70. Due to the chosen resistor ratios, the voltage at N45-2 rises above 1.86V when the -12V rail is less than -9.8V, at which point N45-1 switches low and produces a logic high [FL-12-> signal and low [FL-12>. When [FL-12> goes low it inhibits the back-up battery voltage sense signal to the microcontroller via D44, as shown on diagram sheet 2 (See paragraph 3.3.4). When [FL-12-> goes high is disables the microcontroller’s A/D input multiplexers, as shown on sheet 6 (See paragraph 3.3.14.7).

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7-65


3.3.15.4


+12V und ervol tage detecto r

Comparator N45b (sheet 5) serves as a +12V supply monitor. The operating threshold for this circuit is set by [VREF-2> which applies a stabilised +2.5V to N45-6, at about 1.86V. The +12V rail is monitored via a resistor divider (R246/ 245/R244) which pulls the input to N45-5 below the 2.5V threshold when the +12V rail fall below the 9.8V level. When this occurs the output at N45-7 switches from high to low which is reflected at D57-8 and the resulting ‘low’ [PFO> flag resets the microcontroller via its non-maskable interrupt (NMI) (See paragraph 3.3.2). The micro jumps to a ‘save data’ subroutine as the supply rails are crashing.

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3.3.16


External comm uni cation s RS232 communications

In addition to the bi-directional communication facility with the Operator Logic Board via the CAN Bus, the microcontroller can also be accessed externally via a standard RS232 communications connection (X9). This is designed to be used with a portable computer for diagnostic, calibration and configuration purposes. Communication takes place through D16 which is a standard RS232 line driver/ receiver connected to the micro via [TXO0> and [RXO0>, as shown on sheet 7 (See Appendix A.6) . RS-485 Parallel control communications

An RS485 communications facility is also shown on sheet 7, based around D58 (See Appendix A.5). The differential I/O bus of this device (pins 6 & 7) is connected to the Parallel Logic Board via X7 ( [TXRX+>, [TXRX->).

Transmit mode. the transmit mode is enabled when

[DE485> is high, whereup-

on the [TXDI> data from the microcontroller, applied to D58 pin 4, passes through the device and drives its differential outputs as described in appendix A.5. Note that X32 should be made in order to connect the bus termination resistor (R250) across the transmission line to present the correct impedance to the differential outputs.

Receive mode. the receive mode is enabled when

[RE485-> is taken low, where-

upon the data on the differential I/O bus is converted into a data-stream and connected to the microcontroller via [RXDI>.


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3.3.17


On board 7-segment ind icatio ns sum mary The following table provides a summary of the alarm codes indicated on the two 7-segment LEDs together with their alarm interpretations and associated Operator Panel audible and visible alarm annunciations. Note that there is no on-screen alarm history facility, but where two (or more) alarms are active simultaneously the associated codes will be displayed in a cyclic fashion at 1 second intervals Note: Where the fault LED state is annotated (*) this indicates that the alarm is latched and must be reset using S1 on the UPS Logic Board Note: The following table has been updated for version 4.0 software alarm descriptions. Earlier software versions may differ slightly though the alarm function remains the same.

CODE

Display Alarm Messages (Correct Meaning )

Aud ib le A lar m (Operator Panel)

FAULT LED (red) (Operator Panel)

01

[ NORMAL OPERATION ]

OFF

OFF

02

[ BYPASS SWITCH OPEN ]

Continuous

ON

03

[ OUTPUT SWITCH OPEN ]

Continuous

ON

04

[ RECTIF. SWITCH OPEN ]

Continuous

ON

05

[ BATTERY SWITCH OPEN ]

Continuous

ON

06

[ MANUAL BYPASS CLOSED] Manual bypass breaker closed

Pulsed

Flashing

10

[BYP: ABSENT ] Bypass supply absent – i.e. <50V

Intermittent

Flashing

11

[ BYP: OVERVOLTAGE ] Bypass supply over voltage – upper limit set via mimic menu

Intermittent

Flashing

12

[ BYP: UNDERVOLTAGE ] Bypass supply under voltage – lower limit set via mimic menu

Intermittent

Flashing

13

[ BYP: FREQUENCY ERROR] Bypass supply over/under freq – window limit set via mimic menu

Intermittent

Flashing

14

[ BYP: PHASE ROT. ERROR ] Bypass phase rotation error

Continuous

ON

15

[ BYP: SCR FAILURE ] Bypass SCR open circuit

Continuous

ON *

16

[ BYP:HARDWARE BLOCK ] Bypass supply blocked – hardware block on UPS Logic Board

Pulsed

Flashing

17

[ BYP: OFF VIA DISPLAY] Bypass blocked via operator menu

Pulsed

Flashing

18

[ LOAD ON BYPASS ]

Intermittent

Flashing

19

[ BYP: OVERTEMPERATURE ] Static bypass overtemperature warning

Continuous

ON

7-68







20

[ RECT:SOFTWARE BLOCK] Software block via micro

Intermittent

Flashing

21

[ RECT: OFF VIA DISPL. ] Rectifier blocked via operator menu

Pulsed

Flashing

22

[ RECT: HARDWARE BLOCK ] Hardware block via UPS Logic Board

Continuous

ON

23

[ RECT: CURRENT LIMIT ] Rectifier input current limit

Intermittent

Flashing

24

[ RECT: OVERTEMPERAT. ] Rectifier overtemperature

Continuous

ON

25

[ RECT: FUSE FAIL ] Input fuse failure (F10,F11,F12)

Continuous

ON

30

[ INV: SOFTWARE BLOCK ] Software block via micro

Intermittent

Flashing

31

[ INV: OFF VIA DISPLAY ] Inverter blocked via operator menu

Intermittent

Flashing

32

[ INV: HARDWARE BLOCK ] Hardware block via UPS Logic Board

Continuous

ON

33

[ INV: CURRENT LIMIT ] Inverter 150% current limit active

Continuous

ON

34

[ INV: OVERTEMPERATURE ] Inverter overtemperature

Continuous

ON

35

[ INV: UNSYNCHRONIZED ] Inverter unsynchronised to bypass warning

Intermittent

Flashing

36

[ INV: OVERVOLTAGE ] Inverter overvolts warning

Continuous

ON

37

[ INV: UNDERVOLTAGE ] Inverter undervolts warning

Continuous

ON

38

[ INV: FUSE FAIL ] Inverter fuse failure

Continuous

ON

39

[ OUTPUT: OVERVOLTAGE ] Inverter overvoltage trip – critical bus overvoltage trip to bypass

Continuous

ON

40

[ OUTPUT: UNDERVOLTAGE ] Critical bus undervoltage trip to bypass – level set via mimic menu

Continuous

ON

41

[ OUTPUT: NO VOLTAGE ] UPS in off-line mode

Continuous

ON

42

[ OUTPUT: WAVEFORM ERR. ] Critical bus peak voltage error

Continuous

ON

CODE


7-69






43

[ INV: FREQUENCY ERROR ] lnverter frequency error – inverter frequency window is twice the bypass window

Continuous

ON

44

[ INV: PARALLEL ERROR ] Paralleling current error

Continuous

ON *

45

[ CONTACTOR FAILURE ]

50

[ BATTERY: UNDER TEST ] Battery test in operation

Pulsed

OFF

51

[ BATTERY: TEST FAILED ] Battery test has failed

Intermittent

Flashing *

52

[ BATTERY: DISCHARGING ] Battery is discharging

Intermittent

Flashing

53

[ BATTERY: E.O.D. ] Battery end_of_discharge trip – level set via mimic menu

Continuous

ON

54

[ BOOST: TIME EXPIRED] Boost charge period expired

Pulsed

Flashing

55

[ DC BUS: SLOW OVERVOL. ] DC slow overvolts warning – level set via mimic menu

Continuous

ON *

56

[ DC BUS: UNDERVOLTAGE ] Low battery warning – level set via mimic menu

Continuous

ON

57

[ BATTERY: FUSE FAIL ] Battery fuse (F13) failure

Continuous

ON

58

[ DC BUS: FAST OVERVOL. ] Fast dc overvoltage – fixed at 620V

Continuous

ON *

60

[ BYP: XFER COUNT BLOCK ] Transfer counter exceeded – i.e. >8 transfers in 1 minute

Continuous

ON *

61

[ CUT-OFF: OVERLOAD ] Overload timer expired

Continuous

ON *

62

[ CUT-OFF: OVERTEMPER. ] Overtemperature timer expired

Continuous

ON *

63

[ CUT-OFF: EMERGENCY ] “Emergency power-off” activated

Continuous

ON *

66

[ OVERLOAD PRESENT ] Overload present (warning)

Continuous

ON

67


Continuous

ON *

CODE

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SECTION 7 - UPS Sy s t em Co n t r o l CHAPTER 3 - UPS Lo gi c Boar d (4550007 (4550007 H)

Display Alarm Messages Messages (Correct (Correct Meaning Meaning )

Aud A ud ib le A lar m (Operator Panel)


70

[ BAD EEPROM PROGRAM. ] Start-up error – use mimic reset

Pulsed

ON

71

[ ERR. LRC PAR. PAG 1 ] Incorrect display variable

Pulsed

ON

72


Pulsed

ON

73


Pulsed

ON

74

[ ERR LRC ALARM HIS. ] Alarm History buffer buffer error

Pulsed

ON

75

[ ERR LRC EVENT HIS. ] Alarm History buffer buffer error

Pulsed

ON

76

[ INTERNAL BATTERY LOW ] Internal PCB ni-cad battery Low

Pulsed

ON

80

[ ERROR LRC TABLE ]

81

[ ERROR LRC PANEL ]

82

[ MODEM WRONG CONFIG. ]

83

[ ERROR LRC ALARM MEM. ]

84

[ MODEM NO RESPONSE ] Modem incorrectly connected

85

[ MODEM FALSE COMMAND ] Modem incorrectly configured

86

[ MODEM TIMEOUT TRASM. ] Modem baud-rate error

87

[ CAN BUS NO RESPONSE ] UPS-to-display not connected

88

[ AUTONOMY XXXX min ] Battery autonomy time

CODE

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7-71

SECTION 7 - UPS Sy s t em Co n t r o l CHAPTER 3 - UPS UPS Logi c Boar d (4550007 (4550007 H)

3.4 3.4


Summary inf orm ation Table 7-8: UPS Logic Board configuration configuration jumpers

Jumper

Link Position OPEN

X12

Function (standard)

1-2

Not Required

3 - 4

Not Required

1 - 2

EPROM Enable

2-3

RAM Enable (standard)

1 - 2

Not Required

3 - 4

Not Required

5-6

Not Required

7-8

Not Required

1-2

PLL option with CAP IN

2-3

PLL option with FIN AUX

X13

Testing only normally open

X14

X15

OPEN

(standard)

CAN Bus to display disable bled

X16 1 -2

CAN Bu Bus to to di displ splay en enabled (s (standa ndard)

1-2

ALE enable data save

2 -3

Powe Powerr sup suppl ply y fai faill ena enab ble data data save save (sta (stand ndar ard) d)

1-2

EPROM II enable (not required)

2-3

RAM II enable (not required)

1-2

+5V PCB enables microprocessor ref. For VA calculations (standard)

2-3

V ref ref.. ena enabl bles es micr microp opro roce cess ssor or ref. ref. For For VA VA cal calcu cula lati tion ons s

1-2

Not Required

2-3

RAM enable (standard)

1-2

EPROM enable (standard)

2-3

Not Required

1-2

Not Required

2-3


3-4

Not Required

4-5

Not Required

1-2


2-3

EPROM enable (not required)

3-4


4-5


X17

X19

X20

X21

X22

X23

X24

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s7-c3d.fm5 - Issue 2 Dated 21/08 21/08/97 /97


Jumper

SECTION 7 - UPS Sy s t em Co n t r o l CHAPTER 3 - UPS Lo gi c Boar d (4550007 (4550007 H)

Link Position

Function

1-2

Manual reset of output buffers

2- 3

Micr Microp opro roce cess ssor or rese resett of of outp output ut buff buffer ers s (st (stan anda dard rd))

1-2

Open (Standard) Auto-transfer mode enabled (“on-line” operation). Automatic load transfer from bypass to inverter when when the inverter is available – i.e. the inverter is is the preferred supply source. Closed Manual-transfer mode enabled (“off-line” operation). Automatic load transfer from bypass to inverter only when when bypass is the preferred the bypass is unavailable – i.e. the bypass is supply source. Note: source. Note: there there will be a 3-cycle break on transfer to inverter.

3-4

Open “Inverter voltage fail lockout monitor” disabled. Closed (Standard) “Inverter voltage fail lockout monitor” enabled. i.e. The inverter is given 5 seconds to reach nominal voltage otherwise it is latched OFF. OFF.

5-6

Open (Standard) Enables the “Event History” monitor to store up to a maximum of 10 alarms. Closed Resets the “Event History” monitor. Note: After the 10th “event”, the monitor buffer is full an cannot store any further “events”. The buffer should be reset to 0 after each maintenance or commissioning to enable new “events” to be captured.

7-8

Open (Standard) Password protection enabled Closed Password protection disabled

X25

X26

OPE OP EN

Power wer up rese resett enab enable led d (s (stand tanda ard) rd)

X28 CLOS OSED ED OPEN OP EN

Powe Powerr up up res reset et disa disab bled led 2.5V 2.5V powe powerr sup suppl ply y mon monit itor or enab enable led d (st (stan anda dard rd))

X29 1-2 OPEN

2.5V power supply ply monito itor disab isablled Internal battery ery disa isabled

X31 1-2 OPEN

Inte Intern rnal al bat batte tery ry ins insta tall lled ed and and char charge gerr ena enabl bled ed (st (stan anda dard rd)) RS485 port disabled

X32 1-2

RS485 po port enabled (standard)

1-2

Calendar IC IC sup supply from VRAM (St (Staandard dard))

2 -3

Calendar IC IC supply fro from in internal nal ba battery

1 -2

G.V.C.O .C.O.. to to in invert verter er logi logicc = pa parall rallel el modu module le

2 -3

Micr Micro o V.C. .C.O. to inv inverte erterr log logic ic = sin singl glee mo module dule

X33

X34

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7-73

SECTION 7 - UPS Sy s t em Co n t r o l CHAPTER 3 - UPS UPS Logi c Boar d (4550007 (4550007 H)


Link Position

Jumper

Function

1 -2

Sepa Separa rate te batt batteery per per mod module ule (p (paral aralle lell sys syste tem) m)

2-3

Common battery (parallel sy system)

1 -2

Sepa Separa rate te batt batteery per per mod module ule (p (paral aralle lell sys syste tem) m)

2-3

Common battery (parallel sy system)

X35

X36

Table 7-9: UPS Logic Board potentiometer adjustment Po t en t i o m et er

Fu n c t i o n

R209

5 vo volt re reference adju djustment ent. Ch Check eck at at X2 X20 pi pin 1

R212 212

2.5 2.5 vo volt refe referrenc ence adj adju ustme stmen nt. Check eck at at an anode ode of V45

Table 7-10: UPS Logic Board LED indication

7-74

L ED

Co l o u r

H1

Red

Fu n c t i o n Internal battery charger operating

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Chapter 4 - UPS Logic Board (4550004 E)

4.1

Chapter overvi over view ew This chapter contains a circuit description of t he UPS Logic Board used across the whole 7200 Series UPS model range, and should be read in conjunction with circuit diagram SE-4550004-E (7 pages). Signal annotations shown on the circuit diagrams are shown in italics in the following text – e.g. [CLKOUT>.

4.2 4.2 4.2. 4.2.1 1

General General descri pti on Circuit board functio ns Figure 20-16: UPS Logic Board connections Rectifier Logic Board X2

Inverter Logic Board X4

Static Switch Driver Board X13

X1

X3

X5 X7

UPS Log ic Bo ard X2

X8

X1 High Voltage I/face Board

X1 External Alarm Options

X6

Parallel Control Logic

X4

X2 X9 Operator Logic Board

Operator Control Panel

The position of the UPS Logic Board with respect to the other control boards places it at the heart of the UPS control operation and its functional responsibilities can be broadly summarised as follows: • Motherboard – One of the most basic functions provided by the UPS Logic Board is to act as a ‘motherboard’ for signals travelling directly between any of the other circuit boards connected to it: e.g. the input voltage sense signals passes directly from the High Voltage Interface Board to the Rectifier Logic Board. • System control – The UPS Logic Board contains a microprocessor-based control system which reads various status signals derived on the other circuit boards and

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SECTION 7 - UPS Sy s t em Co n t r o l CHAPTER 4 - UPS Lo gi c Boar d (4550004 (4550004 E)


produces several ‘system’ control logic signals: e.g. ‘stop/start’ signals to the Rectifier/Inverter Logic Boards, and ‘transfer command’ signals to the Static Switch Interface Board. • Alarms control – The UPS Logic Board acts as an assembly point for alarm signals generated on the various other boards, together with t hose generated on the UPS Logic Board itself, and controls their distribution to the Operator Control Panel and External Alarms Options under microprocessor supervision. • Operator programming interface – The UPS Logic Board microprocessor enforces the programmable system operating parameters selected by the operator, via the Operator Logic Board, onto the ‘system’ control logic • Static Switch transfer control – The UPS Logic Board contains decision-making logic which controls the load transfer events between the inverter and static bypass supplies.

4.2.2 4.2.2

Input/Outpu t con nectio ns The UPS Logic Board has eight connectors (See Figure 20-16) whose connections are summarised below. • • • • • • • •

20-372

X1 – System System control control and monitoring monitoring signals signals to/from to/from the the Rectifie Rectifierr Board Board 4520074-A (See Table 20-11). X2 – System System control control and monitor monitoring ing signals signals to/from to/from the the High Voltage Voltage Interface Board 4590054-O (See Table 20-12). X3 – System System control control and monitor monitoring ing signals signals to/from to/from the Inverte Inverterr Logic Logic Table 20-13) 20-13 ). Board 4530024-S (See Table X4 – Power Power supp supply ly to Oper Operato atorr Logic Logic Board Board 4550 4550005 005-F -F (see circuit diagram sheet 7). X5 – System System control control and monitor monitoring ing signals signals to/from to/from the Static Switch Switch Table 20-14) 20-14 ). Driver Board 4542041-X (See Table X6 – Data/lo Data/logic gic to/fr to/from om Operat Operator or Logic Logic Board Board 45500 455000505-F F (see circuit diagram sheet 7). X7 – Used in multi-m multi-module odule parallel parallel operati operating ng systems systems only. only. X8 – Alarm Alarm outputs outputs to optional optional external external (remote (remote)) alarm display display boards boards (see relevant external alarm interface board in the Options section of this manual).

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SECTION 7 - UPS System Control CHAPTER 4 - UPS Log ic B oard (4550004 E)

Table 20-11: Connector X1 (To Rectifier Logic Board) PIN

I/O

1-4

I


5-8

I

+12V power supply derived from AC-DC Power Supply Board

9-12

I

-12V power supply derived from AC-DC Power Supply Board

13-14

I/O


15

O

VREC_AC: Input mains voltage sense signal (phases U-W) – through connection from HVI Board – (15Vp-p)

16

O

VREC_BA: Input mains voltage sense signal (phases V-U) – through connection from HVI Board – (15Vp-p)

17

O

VREC_CB:Input mains voltage sense signal (phases W-V) – through connection from HVI Board – (15Vp-p)

18

O

IB: Battery current sense signal – through connection from HVI Board – battery current limit control

19

–


20

O

IREC: Rectifier input current sense signal – through connection from HVI Board – input current limit control

21-23

–


24

I

IREC_T: Used in parallel systems only (not available)

25

O

VB: DC Bus (battery) voltage feedback – through connection from HVI Board (-3.225Vdc @446V DC Bus)

26

O

T_BAT: Battery cabinet temperature sensor – through connection from HVI Board (2.98V @ 25°C)

27

O


28

O


29

O

DB: Used in parallel systems only (input current sharing)

30

O

DB_0: Used in parallel systems only (input current sharing)

31

–


32

I

OVLREC: Rectifier overload error status (Overload = 1)

33

I

BLKREC: Rectifier OFF/ON status (OFF = 1, ON = 0)

34

I

SEQREC: Input mains phase sequence error status (Error = 1)

35

I

IN_LOW: Low input volts 20% error status (Error = 1)

36

O

ON_REC: Rectifier Run(1)/Stop(0) command from UPSLB micro

37

O

XRADD_1: Reduced current limit from UPSLB micro (On Gen = 1)

38

O

REC_A: Charge mode selection from UPSLB micro

39

O

REC_B: Charge mode selection from UPSLB micro

40

–


s7c3aOLD.fm - Issu e 2 Dated 21/08/97

Function

20-373

SECTION 7 - UPS System Control CHAPTER 4 - UPS Logic Boar d (4550004 E)


Table 20-12: Connector X2 (To High Voltage Interface Board)

20-374

PIN

I/O

Function

1-4

–


5-8

O


9-12

O


13-14

–


15-17

I

VI-A, VI-B, VI-C: Bypass sense voltages for U-V-W phases respectively. Approximately 1% of bypass L-N voltage

18-20

I

VINV-A, VINV-B, VINV-C: Inverter sense voltages for U-V-W phases. Approximately 1% of inverter L-N voltage (8Vp-p)

21-23

I


24-26

I

VREC-AC, VREC-BA, VREC-CB: Input mains sense voltages. Approximately 1.3% of input L-L voltage – e.g. approx. range 5V - 5.5V (15Vp-p) for 380-415V nominal input

27

I

V-B: DC Bus (Battery) volts sense signal. Approximately 0.7% of the DC Bus voltage (+3.225Vdc @446V DC Bus)

28-30

I

IINV-A, IINV-A, IINV-C: Inverter current sense (150% phaseback)

31

I

I-B: Battery current sense signal (Batt I limit and current display)

32-34

I


35

I

IREC-1: Input current sense signal (dc)

36-42

–


43

I

SW-REC: Rectifier Input Switch auxiliary contact status

44

I

SW-IN: Static Bypass Switch auxiliary contact status

45

I

SW-BYP: Maintenance Bypass Switch auxiliary contact status

46

I

SW-OUT: Output Switch auxiliary contact status

47

–


48

I

FUSINV: Inverter fuse monitor (not used in standard module)

49

I

FUSREC: Rectifier fuse monitor (not used in standard module)

50

I

FUSBAT: Battery fuse monitor

51

I

TH: Inverter thermostat contact status

52

I

ESD: Emergency shutdown

53

I

SW-BAT: Battery isolator auxiliary contact status

54

O

BATTRP: Battery isolator trip signal

55-56

–


57-60

I

T1, T2, T3, T4: Temperature sensing monitoring signals

s7c3aOLD.f m - Issu e 2 Dated 21/08/97



Table 20-13: Connector X3 (Inverter Logic Board) PIN

I/O

Function

1-4

I


5-8

I

+12V power supply derived from DC-DC Power Supply Board

9 - 12

I

-12V power supply derived from DC-DC Power Supply Board

13

–

Common

14

–

Common

15-17

O

[VI-A>, [VI-B>, [VI-C>: Bypass volts sense signals – through connection from HVI Board

18-20

O

[VIN-A>, [VIN-B>, [VIN-C>: Inverter volts sense signals – through connection from HVI Board

21-23

O

[IINV_A>, [IINV_B>, [IINV_C>: Inverter current sense signals – through connection from HVI Board

24

O

[XINVOI>: Mains error – load transfer to inverter (H)

25

O

[DREF>: Output voltage adjustment - used in parallel modules

26

O

[DREF0>: Output voltage adjustment - used in parallel modules

27-30

O

[DV-A>, [DV-B>, [DV-C>, [DV-0>: Load sharing signals used for parallel modules only

31

O

[INV-L>: Transfer load to inverter command from processor system

32

I

[OVL-INV>: Inverter overload status to processor system (OVL = L)

33

I

[BLK-INV>: Inverter On/Off status to processor system (Off = H)

34

I

[BACK>: Sync signal back to processor system (Sync pulse train)

35

O

[SYNC>: Produced by processor system (Sync pulse train)

36

O

[ON-INV>: Inverter On/Off control from processor system (Off = L)

37

O

[INV-F>: from processor system (Inv Freq)

38-39

O

[INV_A>, [INV_B>: from processor system - used in output volts selection

40

I

Inverter thermostat status signals (optional)


20-375



Table 20-14: Connector X5 (Static Switch Driver Board)

20-376

PIN

I/O

Function

1-4

O


5-8

O

+12V power supply rail

9 - 12

O

-12V power supply rail

13

I

XSTAI1: Not used in standard module. Details required as to what is connected to SSDB connector X7

14

I

XSTAI2: Output contactor (inverter output) auxiliary contact status – low = contactor closed

15-16

O

INV-L: Transfer load to inverter command from processor system

17-18

O

MNS-L: Transfer load to bypass command from processor system

19

–


20

–




4.2.3


Blo ck Diagram Figure 20-17: UPS Logic Board basic block diagram

N O

n u R r e t r F e F O v n I

n u R N r O e i f i t c e R

r d e B i f i c t i c g e o R L

F F O

1 X

d r a o B I . V . H

r d e B t r i c e g v o n L I

2 X

3 X

d r a o B S B S

l e l l c a r i a g o P L

5 X

7 X

3 2 D

N O F F O

F F O

l r l s o r o o e t r t s t r a n r c t a n p o e t y c v n o n o c B I n R n c C r O S O e s s a p y B

t r e v n I

8 X

e g u i g n r o f e l a f n u A B

2 2 D

N O

m d r r a a l o A B

t r u e f p f t u u O B

5 1 2 3 S S S S

f f f f f t f e O s O / / / O e n n n R O O O r s r e i e s t a r f i t p e c y v e n B I R

t r e u f p f u n I B

S C

X a t a D

X s s e r d d A

M O R P E X 3 8 9 U 4 4 4 M D D D l a n g i S e u g o l a n A

M A R

z H k c o M l 0 C 2

t r e e 8 s w 2 e o R P X

0 P

4 P

3 P

1 P

s D r / e A t r e v n o C

5 P

2 P

l o r t t a n a o C D

e c N f a A r e C t n I

t y u l p a t p s u i O D


20-377


4.2.3.1



The UPS Logic Board control system is based on a type 80C166 microcontroller, as shown in Figure 20-17. This device contains six ports through which it communicates with peripheral circuits/devices, together with several ‘system control lines’. It also contains an internal A/D converter, four programmable timers and internal ROM & RAM. The ports are configured by an initialisation routine performed by the system software on power-up and can be summarised as follows. • •

•

•

•

•

•

Port 0 This port is configured as a 16-bit bi-directional data bus Port 1 This port is configured as the first 16-bits of an 18-bit address bus the other two address lines are provided by port 4. Port 2 The lower half of this port carries various synchronising/timing signals and the upper half comprises the CAN data bus , which carries the data to/from the Operator Logic Board Port 3 This 16-bit port is configured as a mixture of inputs and outputs generally concerned with controlling the CAN Bus data exchange. Port 4 The lower two lines only are utilised on port 4. These form the upper two address lines the lower address lines are provided by port 1. Port 5 The lower ten lines of this port are configured to act as inputs to the internal A/D converter. System control lines In addition to the I/O ports the microcontroller also has the general control I/O lines normally associated with a microprocessor-based system; such as a system clock, reset, and Read/Write control.

Memory

The microcontroller uses both internal and external memory. 2 X 126k of battery backed RAM and 2 X 516k of EPROM are fitted to the board as standard which holds the system operating software. Faci lities are included on the board to allow alternative memory configurations to be used as described later. Data buffers

The 16-bit data bus is connected to various control circuit boards via input and output data buffers, as shown in Figure 20-17, which are controlled by individual ‘chip select’ enable lines to direct the data flow to/from the appropriate source, as required by the system control software. Analogue signal processing

The microcontroller monitors various analogue signals which are connected to the UPS Logic Board from the peripheral boards. These signals are processed by suitable analogue circuitry, buffered where necessary, and applied to the microcontroller’s A/D inputs via a series of multiplexer devices.

20-378




Primary output control signals

Although the micro-controller produces numerous control logic signals, its primary outputs can be considered to be: • Inverter Start/Stop Signal to the Inverter Logic Board which determines whether or not the inverter section is ‘enabled’ or ‘inhibited’. • Rectifier Start/Stop Signal to the Rectifier Logic Board which determines whether or not the rectifier section is ‘enabled’ or ‘inhibited’. • Load on inverter Signal which controls the ‘inverter-side’ contactor (K1) and connects the inverter output to the load. • Load on bypass Signal which controls the static switch and connects the load to the static bypass supply. Note: the ‘load on inverter’ and ‘load on bypass’ signals are interlocked such that they cannot be activated simultaneously. As shown on the block diagram, these signals are produced by a dedicated logic block which is controlled by the data bus together with individual switches which allow each of the above functions to be manually overridden. Operator Interface

The microcontroller is connected to the Operator Logic Board via the CAN Bus, which is a bi-directional serial communications link that enables the operator to program several operational parameters into the micro-controller and also enables various alarms and indications to be displayed on the Operator Control Panel.


20-379


4.3 4.3.1


Detailed cir cui t descrip tio n Introduction The UPS Logic Board circuit diagram (SE-4540004-E) comprises 7 sheets. With reference to the block diagram description (See Figure 20-17), the drawings can broadly be described as follows: •

Sheet 1 contains a ‘signal map’ identifying the functions covered on the remaining pages. It also contains a summary chart detailing the various configuration jumpers. • Sheet 2 contains the – basic microcontroller system – data bus, address bus and control line buffers – Ni-Cad battery back-up controller – reset generator • Sheet 3 contains the – system RAM and ROM memory and its associated configuration links – Inverter/Rectifier Start/Stop control logic – load transfer control logic – CAN bus communications drivers and control logic – Real-time clock (RTC) • Sheet 4 contains the – data bus input buffers – data bus output buffers – on-board 7-segment indication circuit • Sheet 5 contains analogue signal processing circuits for the – input voltage sense signals – inverter voltage sense signals – DC (battery) bus voltage sense signal – Battery current sense signal it also contains reference voltage generators; power supply monitors; and inverter overvoltage and input overvoltage fault detection circuits. • Sheet 6 contains analogue signal processing circuits for the – output voltage sense signals – output current sense signals it also contains the analogue signal multiplexers (for the A/D inputs), out put overvoltage and overcurrent fault detection circuits. • Sheet 7 contains the – input/output signal identifications details – serial communications (RS485) driver and port Note: On the diagrams, a ‘negative’ symbol at the end of a signal’s annotation indicates that the signal is ‘active low’ – e.g. [RD> = [RD->. As with all micro-based system, the microcontroller’s operation is determined by the program held in the system’s memory: and as this is hidden to the service engineer there is very little that can be done to ascertain that the board is working correctly apart from checking the validity of its input and output signals, and other signals generated on the board which are required by the central processor system. The following description deals with the board on this basis, and should provide sufficient information to determine whether or not the board is functioning correctly when it comes to troubleshooting. A full software description is beyond the scope of this manual.

20-380



4.3.2



Clock

20

Reset

27

Power Fail

29

Vref (+5V)

54

XTAL1

READY

96

Ready

CLKOUT

97

Clock out

ALE

25


92

Bus high enable

RSTIN

BHE

NMI

RSTOUT VAREF

D42

Caution

RD WR

96

Reset out

26

Read

95

Write

C o n t r o l B u s

When monitoring the signals described in this section it is best done with control power only – i.e. with the UPS power sections shut down and the circuit boards live via the control power supply. The signals entering the left of the above diagram are constant and can be monitored with a meter/oscilloscope; those shown on the right of the diagram are not constant and best monitored with a logic probe. The logic sequence/timing of these signals depend upon various circuit conditions and cannot therefore be accurately defined; however, for field test purposes, the presence of a ‘variable switching’ logic signal at these points would generally indicate that the basic processor control bus is serviceab le and the system software is running. Power supply

The microcontroller is powered from the general +5V rail which is provided by a three-terminal 5V regulator (N1) shown on diagram sheet 7. System clock (XTAL1)

A dedicated crystal-controlled clock generator (E2) provides a system clock signal which is connected to the microcontroller (D12) pin 20. This signal is a 20MHz squarewave switching between +5V and 0V. System reset (RSTIN)

On power-up, a 1 second logic low reset pulse, [RSTIN->, is applied to D42 pin 27 from the ‘reset generator’ circuit. This can also be manually applied for troubleshooting purposes by temporarily bridging jumper X28 (See paragraph 4.3.5). The [RSTIN-> pulse forces the processor to resta rt its operation from the beginning of its operating program which forces it to run through its initialisation routine. Non-Maskable Interrupt (NMI)

When the input to D42 pin 29 (NMI) goes low it instructs the system software to interrupt its present operation and execute a power-down routine to save critical data.


20-381



The source of this input is determined by X17 w hich is normally ‘made’ 2-3 and selects the power failure detection circuit output [PFO> as the controlling signal – this circuit is shown on diagram sheet 5 (See paragraph 4.3.15.4). Reference voltage (VAREF)

The input to D42 pin 54 (VAREF) is a +5V reference voltage used by the internal A/D converters to compute the digital values for all analogue signals – e.g volts/ current/VA etc. An adjustable reference voltage generator (N45 pin 8) (See paragraph 4.3.15.2), shown on diagram sheet 5, provides this input ( [VREF>) via X20 which is normally ‘made’ 1-2. Clock out (CLKOUT)

This output is a 20MHz squarewave synchronised to the processor clock input and is used by the RAM/ROM memory address decoding logic D33 (See paragraph 4.3.6) shown on the diagram sheet 3. This is to ensure that when the processor wishes to read from/write to memory the memory access is synchronised to the internal microprocessor action – i.e. it ensures that the accessed memory address is relevant to the current processor’s requirements. Address latch enable (ALE)

This output goes high to enable the address bus to be latched into the RAM/ROM memory address decoding logic D33 shown on the diagram sheet 3 – (See paragraph 4.3.6). Bus high enable (BHE)

The logic state of this output indicates whether the processor is internally enabling its ‘high’ or ‘low’ byte data bus – i.e. it indicates if the micro wishes to read from (or write to) the lower byte (D0....D7) or the higher byte (D8....D15). [BHE-> is low when the high byte is being accessed, and vice versa, and is used by the RAM/ ROM memory address decoding logic shown on the diagram sheet 3 – (See paragraph 4.3.6). Reset out (RSTOUT) [RSTO-> is controlled by the reset input signal, [RSTIN->, and goes high while the

input rest signal is applied. This signal is synchronised to the system clock and returns high an integral number of clock pulses after the input reset signal is removed. The [RSTO-> signal is used by the RAM/ROM memory address decoding logic shown on the diagram sheet 3 (See paragraph 4.3.6); and a buffered version, [RSTOX->, is connected to the data bus output buffers as shown on diagram sheet 4 via jumper X25 (2-3) – (See paragraph 4.3.12). Ready (Ready)

This input, when low, inserts wait states in the processor’s operation; thus slowing it down. It is driven by the RAM/ROM memory address decoding logic s hown on the diagram sheet 3 – (See paragraph 4.3.6) – and holds off the processor’s operation until the appropriate address latching has taken place, thus effectively extending the read/write times when slower memory elements are being used. Read (RD)

This output goes low when the processor wishes to read the data from the device or memory location currently addressed by the address bus.

20-382




Write (WR)

This output goes low when the processor wishes to write data to the device or memory location currently addressed by the address bus.


20-383


4.3.3


Data bus, address bus and con trol bus buf fers (circuit diagram sheet 2). Data bus buffer

Two type ACT245 octal bus transceivers (D32 & D 36) are employed as bi-directional protection buffers between the microcontroller (D0....D15) and the data bus (DX0....DX15). D32 buffers the ‘low’ byte (D0....D7) and D36 the ‘high’ byte; however both are controlled by a common data direction signal – i.e. the microcontroller’s [RD-> output – therefore the data direction of all 16 data bus lines are controlled by a single signal. These devices are described in appendix A (See paragraph A.1). When the microcontroller drives its [RD-> output low it sets the data direction through the buffers from B-to-A, which allows the data bus contents through to the microcontroller’s data inputs. At other times, when [RD-> is high, data flows through the buffers from A-to-B, allowing the micro to place data onto the data bus, which can then be written to a peripheral circuit as required. Address bus buffer

The address bus is also buffered by two ACT245 devices (D38 & D41) but, unlike the data bus described above, in this case the data direction is fixed by connecting pin 1 of each device to a permanent +5V supply. Thus the address bus data always flows through the devices in the A-to-B direction and used to select a memory location – the buffered address bus is annotated (AX0....AX17). Note: AX16 & AX17 are buffered by the control bus buffer described below. Control bus buffer

The control bus signals [RD->, [WR->, [BHE->, [RSTO-> are all buffered by D47. This device is configured with fixed data direction A -to-B, in the same manner as the address bus buffer described above, by the application of a fixed +5V supply at D47 pin 1. The buffered control signals [RDX->, [WRX->, [BHEX->, [RSTOX-> are used by various circuits distributed throughout the circuit diagrams. In all cases the above mentioned buffers have pull-up resistors connected to t heir input and output pins – e.g. resistor packs R307, R309 etc.

4.3.4

Ni-Cad Battery back-up cont roll er (circuit diagram sheet 2). A 3.6V 280mAh Ni-Cad battery is fitted to the UPS Logic Board to back-up the RAM contents and maintain the RTC time-keeping operation when the UPS is turned OFF; when fully charged the battery offers a back-up period of up to 4 to 5 months. The charger circuit is activated by t he [OUTBAT> signal which is produced by the processor via D25 pin 19 (diagram sheet 4). When [OUTBAT> goes high it turns on V152 which then turns on V151 to supply the battery charge current via led H8, R32 and V73. The charge voltage is limited to 4.7V by zener V14. Note: the battery can be disabled for shipping/storage by opening jumper X31.

The battery is connected to the RAM memory devices and Real Time Clock device – shown on diagram sheet 3 – via V32 and the battery supply annotated [VRAM>. Thus, if the board’s power supply is turned off (i.e. UPS fully powered down) the programmable parameters held in RAM (e.g. kVA, working voltage

20-384



SECTION 7 - UPS Sy s t em Co n t r o l CHAPTER CHAPTER 4 - UPS UPS Log ic B oard (4550004 (4550004 E)

and frequency, battery charging parameters and display language) are maintained; and the real-time clock keeps running. It is not therefore necessary to re program these parameters following every start-up. start-up. Note: Jumper X31 must be made in order to enable this function.

The [VBATT> output is not connected to other parts of the circuit, but it is monitored by the microcontroller’s analogue input [AN9> via D44, which is a quad analogue switch. [VBATT> is switched through D44 pin 2, by [FL-12> when it goes high; this is controlled by a ±12V supply rail monitor circuit (diagram sheet 5) which inhibits the [VBATT> sense signal if the ±12V power rails are invalid, thus preventing an erroneous battery voltage fault being detected by the micro under these conditions. Note: the other three gates within D44 are not used and their inputs are tied to 0V. [OUTBAT> signal details

The micro-controller monitors the NiCad battery voltage (3.6V nom) via AN9 and its internal A/D converter (as described above) and turns on the Ni-Cad charger, by driving the [OUTBAT> signal high, if the Ni-Cad voltage falls below 2.8V. When the charger is active, the [BACK-UP BATTERY LOW] message is dis played on the Operator Control Panel ( alarm #76) and led H8 illuminates. Once the battery is recharged to 3.6V the charger is turned off by the [OUTBAT> signal returning low and the alarm message is cancelled. Thus the Ni-Cad battery is charged only when necessary and is not permanently trickle-charged. Note: the NiCad charger may be active for several hours when the UPS is first commissioned (depending on the initial battery charge state) – jumper X31 must be fitted to ‘enable’ the battery back-up facility.

4.3.5 4.3.5

Reset generat or (circuit diagram sheet 2). A purpose-designed Supply Voltage Supervisor (N24) provides the micro with a 1 second sec logic low [RSTIN-> reset signal on power-up. This signal, which is applied to the micro pin 27, can also be initiated manually by temporarily making jumper X28 (1-2). (1-2). The [RSTIN> signal also resets the RAM chip select signals signals produced by D19a/d (shown on circuit diagram sheet 3) and points the micro to its initialisation routines.

Caution

Using X28 to activate the reset circuit during normal UPS operation will crash the unit, because the ‘run’ signals to the rectifier, inverter and static switch will be disabled for the 1 second reset period.

On power-up (reset) the micro-controller receives initialisation data from D20 which is an EEPROM used to t o store the Emerson/Liebert/SICE software passport identification. Amongst other things this configures the micro’s programmable ports P0-P5 to the parameters required required to operate operate in this application. Without this this security interlock the micro-controller will be inactive. An inverse output, [V AUX>, goes high on reset and is connected to D22 and D23 in the ‘Inverter/Rectifier Start/Stop control logic’ and ‘Load transfer control logic’ (circuit diagram sheet 3). This resets the logic latches (Emergency Stop, DC Overvolts, etc.) and re-applies the ‘run’ signals to the rectifier, inverter and static switch. Note: the reset time is determined by R157/C97, and begins when the +5V supply rail reaches 3.6V on initial power-up.


20-385


4.3. 4.3.6 6


System RAM and ROM ROM memory addressi addressi ng (circuit diagram sheet 3). The system memory comprises 2 x 512k EPROMs (D35 & D46) and 2 x 128k RAM chips (D28 & D40). All these devices have an 8-bit data bus output; however, the EPROMs have a 16-bit address input while the RAM chips have a 17 bit address facility. Random Access memory (RAM)

This is the read/write memory store; sometimes referred to as the temporary store. Any data fed in from the peripheral devices or produced during the execution of the main program will be temporarily held in RAM – e.g. UPS setup parameters such as kVA, nominal voltages/frequency, serial number, passwords, etc. This is a ‘volatile’ location, meaning that when power is lost to the component all data is also lost; thus the need for the on-board back-up Ni-Cad battery. Read Only Memory (ROM)

This memory contains the ‘operating system program’, or firmware , which is basically a sequence of instructions to be carried out by the micro-controller in order to make it perform the actions required of it. Upon power-up the micro is pointed to the first instruction as part of its reset initialisation, and from then on it steps through the programmed instructions in a sequence dictated by various events and monitored conditions. ROM is ‘non-volatile’, which means that it does not lose its memory contents in the event of a loss of power. Address decoding – D33 / D19

The ‘output enable’ pins of all four memory devices are controlled by the control bus [RD-> line, therefore when this line goes low the processor can read the data held at the current address from any of the devices. The purpose of the ‘address decoding’ circuit is to enable the microcontroller to select which of the EPROM or RAM devices it wishes to communicate with at any given time. The memory devices’ ‘chip select’ inputs are controlled by a circuit comprising an ASIC i.c. (D33) and two gates of D19. D33’s inputs are connected to A0, A14....A17, and several control bus signals – as described in paragraph in paragraph 4.3.2. 4.3.2. – which are all controlled by the microcontroller. The output signals, [CSEP1L->, [CSEP1H->, [CSRA1L->, and [CSRA1H->, adopt logic states determined directly by these processor-controlled inputs and are synchronised to the processor operation by the 20MHz [CLKOUT> signal. [CSEP1H-> enable the EPROM devices via their ‘chip When low, [CSEP1L-> and [CSEP1H-> enable’ inputs (pin 20), while [CSRA1L-> and [CSRA1H-> perform a similar function on the RAM chips.

The [READY> output from D33 is fed back to the micro to inform it that the appro priate addresses have been loaded into D33’s internal latches (See paragraph 4.3.2). As D19 provides the ‘chip select’ inputs to the RAM devices it is powered from the battery-backed RAM supply to prevent RAM data corruption on UPS power down. Note: jumper X14 provides a test facility for bench testing only and all links should be open during normal operation.

20-386

s7c3aOLD.f m - Issu e 2 Dated 21/08/97 21/08/97



AX15 & AX16 configuration links

The UPS Logic Board has been designed to facilitate future software upgrades by including configuration links to permit the addressing of alternative memory devices. These links affect the routing of the AX15 and AX16 address lines, and the standard configuration is shown below in Figure 20-19. 20-19. In the standard configuration the signals annotated [PIN29EP> and [PIN3EP> are connected to the EPROMs’ A14 and A15 inputs and are therefore driven by the AX15 and AX16 address lines respectively. The [PIN31RAM> signal (AX16) is connected to the A15 input of both RAM devices and the [PIN3RAM> signal (AX15) is connected to the RAM ‘write enable’ inputs. Figure 20-19: AX15 & AX16 decoding configuration links X19

X13

1

1

2

2

3

3

[AX16>

X22

[PIN3EP>

X21

1

1

2

2

3

3

X23

[AX15> [PIN29EP> [WRX–>


[PIN31RAM>

[PIN3RAM>

X24

5

5

4

4

3

3

2

2

1

1

[PIN29RAM>

20-387


4.3.7


Basic system control logic The term ‘Basic System Control Logic’ is used here to described the signals generated by the UPS Logic Board which control the ‘start/stop’ commands to the rectifier and inverter, the battery circuit breaker ‘trip’ control, and the ‘load transfer’ control between inverter and static bypass. These functions are controlled by two ASICs annotated D22 and D23 which are shown on sheet 3 of the diagram and also in greater detail in Figure 20-20 below. Figure 20-20: Basic system control logic (internal detail)

M_RESET

1 2 3

ESD

4

ALARMS_RES V-AUX

D21-2 N24-6

D22

R97 N15-8 N15-14

R86 Z39 0V

D34-12

M-ESD SCR_OPN

5 6

MNS_L

7

MSCROP

8

BAT_MA

9

M_BAT_MA

M_ESD

16

MSCROP

15

M_BAT_MA

12

BLK_MAINS

D26-5

D26-4

D26-6

11

13 BLK_BYP 14

SEQ_MAINS

D26-7

17

D26-3

2 1 1 R

3 6 C

M_BAT_MA

M_ESD

1 2 3 4

BLK_INV_M

5

INV_ON

6

RST_OUT

8

L_INV

9

BLK_MAINS

7

IB_OPEN

D21-16

V-AUX

D21-5 D21-6 D21-9

+5V

Q1

9 0 1 R

S1

Q2

Q3

4 5 1 R

6 0 1 R

0 1 1 R

Manual RESET

Block Inverter

Block Rectifier

D21-12

0V Block Bypass

4.3.7.1

D21-15

L_MAINS

11

BLK_REC_M

13 14

1 1 1 R

3 1 1 R

2 4 6 6 C C

0V

D23 12 BAT_TRP

15 ON_INV

16 INV_L

X2-54

X3-36

X5-16 X5-31

17 MNS_L

19 ON_REC

X5-17

X1-36

REC_ON

D22 Funct ion al descr ipt ion

D22 provides four status signals which are used by D23 and are also monitored by the microcontroller via the data bus input buffers.

20-388




Emergency shutdown [ESD>

The ‘emergency shutdown’ signal [ESD> to D22-4 is driven by external circuitry and connected via X2-52 (sheet 7) as a logic high when the emergency shutdown is applied. When D22 pin 4 goes high it drives pin 17 high which then provides a latching input back to D22 pin 5 which holds pin 17 high until the reset circuit is activated – the latching signal is debounced by R112/C63. D22 pin 5 also turns off the bypass enable signal via D22 pin 12 – i.e. turns off the bypass SCRs. In addition to providing the latching function, the ‘high’ output from D22-17, [M_ESD>, is fed to the microcontroller via data bus buffer D26-5 to initiate alarm #63 [CUT-OFF: EMERGENCY] (See paragraph 4.3.11.4) and it is also connected to D23-4 where it: • • •

Trips the battery circuit breaker ([BAT_TRP> = 0) Turns Off (stops) the rectifier ([ON_INV> = 0) Turns Off (stops) the inverter ([REC> = 0)

Static switch SCR open

The ‘static switch SCR open’ signal [SCROPN> to D22-6 is produced by N15-8 or N5-14 (sheet 6) as a logic high when the detection circuits ‘sees’ a voltage drop across one of the static bypass SCRs. When D22 pin 6 goes high it drives pin 16 high (provided the ‘load on mains’ input to D22-7 is also high) which then provides a latching input back to D22 pin 8. This inhibits the output on pin 12 and holds pin 16 high until the reset circuit is activated – the latching signal is de bounced by R111/C62. Thus [SCROPN> will block the bypass only when the load is ‘on-bypass’. In addition to providing the latching function, the ‘high’ output from D22-16, [MSCROP>, is fed to the microcontroller via the data bus buffer D26-4 (See paragraph 4.3.11.4) where it annunciates alarm #15 [I/P: SCR CUT OFF]. DC Overvoltage – fast

The ‘DC Fast Overvoltage’ signal [BAT_MA> to D22-9 is driven by N13-8 (sheet 5) and is logic high when a DC busbar (battery) overvoltage condition (>620V) is present. When D22 pin 9 goes high it drives pin 15 high which then provides a latching input back to D22 pin 11 which holds pin 15 high until the reset circuit is activated – the latching signal is debounced by R113/C64. In addition to providing the latching function the ‘high’ output from D22-15, [MBATMA>, is fed to the microcontroller via the data bus buffer U26-6 to initiate alarm #58 [DC BUS: FAST OVERV.] (See paragraph 4.3.11.4) and it is also connected to D23-1 where it: • • •

Trips the battery circuit breaker ([BAT_TRP> = 0) Turns Off (stops) the rectifier ([ON_INV> = 0) Turns Off (stops) the inverter ([REC> = 0)

Static bypass inhibit

The [BLKMNS> output from D22 pin 12 goes high when D22 detects any condition which requires the load to be prevented from being connected to the static bypass supply. This output is fed to the microcontroller via t he data bus buffer U26-3 to initiate alarm #17 [BYPASS INHIBIT REM.] (See paragraph 4.3.11.4) and is also connected to D23-7 where, when ‘high’, it inhibits the ‘load-on-bypass’ command [MNS_L> output from D23 pin 17. The [BLKMNS> signal can be driven high by any of the following conditions:


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• • • • •


‘Emergency shutdown’ latch set (D22-5 = high) ‘Bypass SCR open’ latch set (D22-8 = high) 1 second Power-up reset pulse (D22-5 = positive-going pulse) Static bypass mains phase sequence error (D22-13 = high) from D27 on diagram sheet 5 ‘Manual block’ applied from switch Q1 (D22-14 = high)

RESET

There are three reset signal sources applied to D22: •

D22-1 receives a logic high reset signal from the microcontroller via the data bus output buffer D21-2 (See paragraph 4.3.12.5). This is a software reset programmable via the Operator Control Board • D22-2 receives a logic high reset pulse when the board is powered up (See paragraph 4.3.5) • D22-3 is driven high when the manual reset button (S1) is pressed The ‘Emergency shutdown’, ‘Bypass SCR open’ and ‘DC overvoltage’ latches described above are all reset when any one of the three reset inputs are active. Note: the ‘power-up’ reset signal to D22-2 also resets the [BLKMNS> output from D22-12, described immediately above. 4.3.7.2

D23 Funct ion al descr ipt ion

D23 provides five major control signals, as detailed below: Battery circuit breaker trip

A logic low [BATTRP> output from D23-12 trips the battery circuit breaker via X2-54 (sheet 7), which is connected to the High Voltage Interface Board (See section 7 paragraph 2.3.8). This signal can be driven low by any of the following D23 inputs: • • • •

‘DC Fast Overvoltage’ to D23-1 ([MBATMA> = 1) from D22-15 (see above) ‘Emergency shutdown’ to D23-4 ([MSDD> = 1) from D22-17 (see above) ‘Power-up reset’ to D23-3 (see above) ‘Software trip’ to D23-2 – [IBOPEN> generated by the microcontroller and connected via the data bus output buffer D21-16 (See paragraph 4.3.12.5). Note: This signal trips the battery breaker on low DC voltage as follows: – UPS on less than 15% load = 330V – UPS on greater than 15% load = 360V The low voltage trip is programmable via the Operator Control Panel SetUp parameters, and is adjustable between 1.6V/cell and 1.69V/cell. The 30Volt window at the 15% level is not adjustable.

Inverter Start/Stop (On/Off)

The [ON-INV> output from D23-15 is connected to the Inverter Logic Board via X3-36 (sheet 7) where it controls the inverter ‘Start/Stop’ status. A logic low [ON-INV> signal commands the inverter to ‘Stop’ and can be effected by any one of the following D23 inputs (conversely, all the following inputs must be in their ‘healthy’ low state in order for the inverter to run): • • •

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‘DC fast overvoltage’ (>620V) to D23-1 – ([MBATMA> = 1) from D22-15 (see above) ‘Emergency shutdown’ to D23-4 – ([MSDD> = 1) from D22-17 (see above) ‘Power-up reset’ to D23-3 (see above)




•

‘Software control’ to D23-6 – [INV-ON> generated by the microcontroller and connected via the data bus output buffer D21-6 (See paragraph 4.3.12.5) . This signal is ‘low’ to inhibit the inverter and ‘high’ to enable it. When this signal is actively blocking the inverter (i.e. low) it initiates alarm #31 [INVERTER: OFF REM.]. • ‘Manual inverter block’ to D23-5 – logic high from the manual inverter inhibit switch Q2. If the [ON-INV> signal at D23 pin 5 is active (low), blocking the inverter, alarm #30 [INVERTER: OFF] will be active. Note that alarm #31 will be disabled if alarm #30 is active. Alarm #31 can be interpreted that the inverter has been selected off, while alarm #30 suggests that the inverter has been turned off for some other reason. Rectifier Start/Stop (On/Off)

The [ON-REC> output from D23-19 is connected to the Rectifier Logic Board via X1-36 (sheet 7) where it controls the rectifier ‘Start/Stop’ status. A logic low [ON-REC> signal turns OFF the rectifier and can be effected by any one of the following D23 inputs (conversely, all the following inputs must be in their “healthy” state in order for the rectifier to run): • • • •

•

‘DC Fast Overvoltage’ (>620V) to D23-1 – ( [MBATMA> = 1) from D22-15 (see above) ‘Emergency shutdown’ to D23-4 – ([MSDD> = 1) from D22-17 (see above) ‘Power-up reset’ to D23-3 (see above) ‘Software control’ to D23-14 – [REC-ON> generated by the microcontroller and connected via the data bus output buffer D21-12 (See paragraph 4.3.12.5) this signal is ‘low’ to inhibit the rectifier and ‘high’ to enable it. When this signal is actively blocking the rectifier (i.e. low) it initiates alarm #20 [RECTIFIER: OFF]. ‘Manual rectifier block’ to D23-13 – logic high from the manual rectifier inhibit switch S2. If the [ON-REC> signal at D23 pin 19 is active (low), blocking the rectifier, alarm #22 [RECTIFIER: BLOCK] will be active. Note that this will be disabled if alarm #21 is active. Alarm #21 can be interpreted that the rectifier has been selected off via the Operator Control Panel, while alarm #22 suggests that the rectifier has been turned off for some other reason

Load transfer control

The transfer control logic within D23 is interlocked such that the ‘load on inverter’ [INV_L> and ‘load-on-bypass’ [MNS_L> commands are mutually exclusive.

[INV-L>: This output, from D23-16, goes high to transfer the load to the inverter and is connected to the Static Switch Driver Board via X5-15 (sheet 7), where it turns off the static switch (disconnecting the load from the bypass supply) and energises the ‘inverter-side’ contactor (K1) driver circuit. It is also connected to the Inverter Logic Board, via X3-31 where it triggers the latches within D11 which makes the inverter voltage track the bypass supply voltage for 100ms (See section 18 paragraph 3.3.3). This is done to provide a smooth transfer from bypass to inverter and reduce the w ear on the ‘inverter-side’ contactor (K1). In order for D23 pin 16 to go high, D23 requires pin 8 ( [RSTOUT>) to be low and pin 9 ( [L-INV>) high. Both these signals are produced by the microcontroller and connected to D23 via the data bus output buffer D21 (See paragraph 4.3.12.5).


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[RSTOUT> is a 1 second hold-off command iss ued by the microcontroller when it

is performing its initialisation checks during power-up; and [L-INV> is the ‘transfer-load-to-inverter’ command issued when all its software-controlled parameters have been verified (e.g. Inverter voltage OK, Sync OK etc.).

[MNS-L>: This output, from D23-17, goes high to transfer the load to the bypass and is connected to the Static Switch Driver Board via X5-17 (sheet 7), where it turns on the static switch driver circuit, connecting the load to the bypass supply. It is also connected to D22-7 where (when low) it disables the ‘bypass SCR open’ input to D22-6 when the load is not connected to the bypass supply. In order for D23 pin 17 to go high D23 requires: •

pin 7 to be low (i.e. no [BLKMNS> from D22)

AND • either pin 8 [RSTOUT> to be high – not requesting ‘load-on-inverter’ OR pin 11 ([L-MNS>) high – requesting ‘load-on-bypass’.

The signals to pins 8 and 11 are produced by the microcontroller and connected to D23 via the data bus output buffer D21 (See paragraph 4.3.12.5). [RSTOUT> is a 1 second hold-off command issued by the microcontroller when it is performing its initialisation checks during power-up; and [L-MAINS> is the “transfer-load-to bypass” command issued when all its software-controlled parameters have been verified for appropriate action (e.g. Critical bus volts not OK, overload, bypass volts OK etc.).

4.3.8

CAN bus communi cations drivers and control logic (circuit diagram sheet 3). The CAN bus communications system is described in paragraph 5.3.9. (Operator Logic Board).

4.3.9

Real-time cl ock (RTC) (circuit diagram sheet 3) The MC68698 (D18) is a peripheral device which contains a real-time clock/calendar, a 32 x 8 bit static RAM, and a synchronous, serial, three-wire interface for communicating with the micro-controller. As it’s title suggests, the real time clock accurately counts seconds, minutes, hours (AM/PM), Day-of-the week, date, month and year (including auto-incrementing leap-year). In the UPS Logic Board application it provides ‘date stamping’ to the Operator Control Panel messages and ‘service data’ as entered via the Maintenance Menu Screen (see paragraph 2.4.6.3 on page 2-40). The device operates from the Ni-Cad back-up battery to maintain its time-keeping function and prevent data loss when the general +5V control power is turned off. It also contains many other circuit functions, such as an alarm facility, watchdog timer etc. which are not used in this application but may be mentioned briefly in the following description. Power supply details

D18 is powered from the Ni-Cad-backed [VRAM> supply which is available at all times provided jumper X31 is made 1-2 (See paragraph 4.3.4). This supply is connected to pin 16 (Vcc), pin 13 (Vbatt) and also, via an R-C delay circuit (R1087/C54), to pin 10 (POR). The general +5V control power rail is also monitored by the device at pin 12 (VSYS).

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The delayed input to pin 10 is seen as a Power On Reset (POR) and resets the device by briefly holding pin 10 low w hile the device is powered-up. Note that as the battery-backed supply is present at all times, this is effectively a ‘once-only’ reset that takes place when X13 is initially made (i.e. battery connected) and is not affected by subsequent application/removal of the UPS Logic Board’s +5V control power supply. The board’s +5V supply rail is monitored at D18 pin 12; and when the voltage at this pin is less than 0.7V above the Ni-Cad voltage (pin 16) the device switches to a low-power standby mode whereby it maintains its time-keeping function but internally inhibits the serial communication facilities with the micro-controller. This prevents the passage of invalid or spurious data while the micro-controller is powering-down and so prevents RTC data corruption. Clock control

The RTC’s internal timer operation can be controlled from one of two sources; i.e. either from an external crystal-controlled clock reference or a 50/60Hz mains derived sinusoidal signal. In this particular application an external crystal is used and the 50/60Hz input to pin 11 (LINE) is grounded via R107. For crystal operation pins 14 and 15 are connected to a 32.768kHz, 1.048576kHz, 2.097152kHz or 4.194304kHz crystal, as shown on the circuit diagram. A programmable internal divider circuit enables the particular external clock frequency to be scaled down to that used by the internal logic. The internal clock signal is made available at pin 1 (CLKO) but in this particular application is not used, and remains unterminated. Serial communications interface

Four lines, connected to pins 4 to 7, implement a bi-directional communications interface with the micro-controller, and allow the micro to write configuration and control data to the RTC and read the ‘time’ and register data. As described above, such communication is inhibited if the UPS Logic Board’s +5V power rail is unavailable. The [ORCS> input to pin 7 (SS) is seen as a ‘chip select’ input in this application and must be held high while either a read or write event is taking place. Data is input (written) to the RTC by [ORDI> to pin 5; and output (read) from the device by [ORDO> from pin 7. In each case the data takes the form of a serial data stream clocked in/out by the ‘serial clock’ signal [ORSK> applied to pin 4. Note that all four of these signals are under direct control of the micro-controller and applied to the data bus via the buffers shown on diagram sheet 4. Other connections

The functions connected to pin 2, pin 3 and pin 9 are not used in this particular application and these pins are tied to their default logic levels as shown.


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Section 20:

4.3.10

Data bus buf fers ‘ch ip select’ decodi ng The data bus communicates with the peripheral circuits and devices via 16 octal buffers which are selected in ‘pairs’ to provide a 16 bit data bus transfer. The microcontroller selects a particular buffer-pair by appropriately addressing the ‘chip select’ decoding circuit (D52) which then ‘enables’ the required buffers. Details of the digital signals handled by each buffer are provided in the following paragraphs. Figure 20-21: Data bus buffer control (block diagram) D8 [CSIN1->

D17

OE

CP

D2

D25 CP

OE

D1 [CSIN2->

D9

OE

CP

D26

CP

D51

D50 CP

OE

D60

CP

D7

D54 CP

CP

D10 CP

D55

OE

[CSDIS->

D21

OE

[CSIN3->

D56 CP

DATA BUS

Control Bus

Microcontroller Address Bus AX11 AX12 AX13 AX14 AX15 AX16 AX17 [RDX-> [WRX->

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1 2 3 4 5 6 7 8 9

D52

12 13 14 15 16 17 18 19

[CSDIS-> [CSIN1-> [CSIN2-> [CSIN3-> [CSOU1-> [CSOU2-> [CSOU3-> [CSOU4->

s7c3bOLD.fm - Issue 2 Dated 21/08/97


4.3.11


Data bus inp ut buff ers (diagram sheet 4). Digital signals which are read by the microcontroller as part of its control function are connected to the data bus via six type HCT 245 octal bus transceivers (See Ap pendix A.1) which are accessed in pairs to provide a 16-bit data transfer (See Figure 20-21). The buffers ‘data direction’ pins are held permanently high, therefore the data flow is fixed from ‘A-to-B’ in each device. ‘Chip select’ s ignals from D52 are connected to the buffers ‘output enable’ pins which provides the means for the micro to select each pair of devices as required. The remainder of this sub-section lists the digital signals connected to the data bus through the bus input buffers, and provides signal details where appropriate.

4.3.11.1

Buf fer D8 – activ ated by CSIN1 XRADT1

Source: Sheet 7 X1-31 Description: From the Power Rectifier overtemperature sensing device – this input is not normally used and is held permanently low by jumper X10 (1-2) on the Rectifier Logic Board. If used, in an overtemperature situation this input initiates alarm #24 [RECTIFIER: OVERTEMP.] and the rectifier and inverter are shut-down 1 minute later accompanied by alarm #62 [CUT-OFF: OVERTEMP]. This alarm must be reset by pressing the manual reset push-button. OVLREC

Source: Sheet 7 X1-32 Description: Rectifier Overload – this input goes high when the rectifier is operating in input current limit mode (H6 illuminated on the Rectifier Logic Board) – (See section 4 paragraph 2.3.4.2). This initiates alarm #23 [RECTIFIER: I/P LIMIT]. BLKREC

Source: Sheet 7 X1-33 Description: Rectifier Blocked – this input goes high when the Rectifier Logic board is in its ‘stop’ mode (See section 4 paragraph 2.3.6). This can be due to the Rectifier Logic Board detecting an internal fault or a ‘stop’ (block) command issued by the UPS Logic Board (See paragraph 4.3.7.2). The internal fault channel is triggered by either: incorrect phase rotation; Rectifier Logic Board power supply failure; or low input voltage (-20%). The external fault channel initiated by the UPS Logic Board will be accompanied by alarm #21 [RECTIFIER: OFF REM.] or alarm #22 [RECTIFIER: BLOCK] (See paragraph 4.3.7.2). SEQREC

Source: Sheet 7 X1-34 Description: Rectifier input phase sequence error – this input goes high when the Rectifier Logic board phase sequence monitor detects an error on the incoming 3 phase mains supply (H8 illuminated on the Rectifier Logic Board) (See section 4 paragraph 2.3.6.1).


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IN-LOW

Source: Sheet 7 X1-35 Description: Rectifier input undervoltage – this input goes high when the Rectifier Logic board input voltage monitor detects a -20% undervoltage condition on the incoming 3 phase mains supply (H9 illuminated on the Rectifier Logic Board) (See section 4 paragraph 2.3.6.2). XATI1 / XATI2 / XATI3

Source: Sheet 7 X2-40 / 41 / 42 Description: Not used – no connection on High Voltage Interface Board. 4.3.11.2

Buf fer D2 – activ ated by CSIN1 SW-REC

Source: Sheet 7 X2-43 Description: Rectifier input switch monitor – this input goes low when the rectifier input mains power switch is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the input switch is open, this signal initiates alarm #04 [RECTIF. BREAKER OPEN] . SW-IN

Source: Sheet 7 X2-44 Description: Static Bypass switch monitor – this input goes low when the Static Bypass mains power switch is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the bypass switch is open, this signal initiates alarm #02 [BYPASS BREAKER OPEN] . SW-BYP

Source: Sheet 7 X2-45 Description: Maintenance Bypass switch monitor – this input goes low when the Maintenance Bypass switch is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the maintenance bypass switch is closed, this signal initiates alarm #06 [ON MANUAL BYPASS] . SW-OUT

Source: Sheet 7 X2-46 Description: Output switch monitor – this input goes low when the Output switch is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the output switch is open, this signal initiates alarm #03 [OUTPUT BREAKER OPEN]. FUSINV

Source: Sheet 7 X2-48 Description: Not used - held permanently low due to link fitted to connector X16 on the High Voltage Interface Board (see main equipment wiring diagrams). If used, this input monitors the inverter fuse and on fuse failure initiates alarm #38 [INVERTER: FUSE FAIL].

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FUSREC

Source: Sheet 7 X2-49 Description: Not used - held permanently low due to link fitted to connector X17 on the High Voltage Interface Board (see main equipment wiring diagrams). If used, this input monitors the rectifier (input) fuses and on fuse failure initiates alarm #25 [RECTIFIER: FUSE FAIL]. FUSBAT

Source: Sheet 7 X2-50 Description: Battery fuse monitor – this input goes high if the battery fuse ruptures (See section 7 paragraph 2.3.15). The fuse is detected by a micro-switch l ocated on the fuse which, when activated, initiates alarm #57 [BATTERY: FUSE FAIL]. TH

Source: Sheet 7 X2-51 Description: Inverter thermostat monitor – this input goes high if an inverter thermostat opens (overtemperature > 90°C) (See section 7 paragraph 2.3.13). In the event of an overtemperature situation occurring, this input initiates alarm #34 [INVERTER: OVERTEMP.] and the rectifier and inverter are shut-down 1 minute later accompanied by alarm #62 [CUT-OFF: OVERTEMPER]. This alarm must be reset by pressing the manual reset push-button (S1). 4.3.11.3

Buf fer D1 – activ ated by CSIN2 SW-BAT

Source: Sheet 7 X2-53 Description: Battery circuit breaker monitor – this input goes low when the Battery switch (or contactor) is closed. This signal passes through the High Voltage Interface Board (See section 7 paragraph 2.3.7). When the battery switch is open, this signal initiates alarm #05 [BATTERY BREAKER OPEN] . OVLINV

Source: Sheet 7 X3-32 Description: Inverter Overload – this input goes high when the inverter is operating in current limit mode (H14 illuminated on the Inverter Logic Board) – (See section 18 paragraph 3.3.7). In an Overload condition, this signal initiates alarm #33 [INVERTER: CURR.LIMIT]. BLKINV

Source: Sheet 7 X3-33 Description: Inverter Blocked – this input goes high when the Inverter Logic Board is in its ‘stop’ mode (See section 18 paragraph 3.3.8). This can be due to the Inverter Logic Board detecting an internal fault or a ‘stop’ (block) command issued by the UPS Logic Board (See paragraph 4.3.7.2). The internal fault channel is triggered by either: IGBT desaturation, ribbon cable disconnected, Inverter Logic Board power failure. The external fault channel initiated by the UPS Logic Board will be accompanied by alarm [#30], [#31] or [#32].


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XINVI1

Source: Sheet 7 X3-40 Description: Not used – held permanently low due to X13 (2-3) on the Inverter Logic Board which disables this alternative temperature sensor route. The active thermostat route is via [TH> described earlier. XSTAI1

Source: Sheet 7 X5-13 Description: Not used – held permanently low due to X11 (1-2) on the Static Switch Driver Board. No thermostat is fitted on the heatsink. XSTAT2

Source: Sheet 7 X5-14 Description: Inverter output contactor monitor – goes low when the inverter output contactor is closed (load on inverter) and is used by the transfer control logic software routine. LINK X12

Source: On-board jumper X12 Description: Not used. 4.3.11.4

Buf fer D26 – activ ated by CSIN2 MRESET

Source: Sheet 3 – switch S1 Description: RESET switch – goes high when the on-board manual reset switch (S1) is pressed and is used by the micro to unlatch “block commands” issued by some of its software routines. BLKMNS

Source: Sheet 3 – D22 pin 12 Description: ‘Static Switch blocked’ monitor – this input goes high to inform the micro that the static switch control logic (on this Board) is inhibiting the static switch (alarm #16 [BYPASS INHIBIT]). This can be invoked by any of the following signals applied to D22 (See paragraph 4.3.7.1). – static switch manual inhibit switch (Q1) closed – bypass phase sequence error detected – emergency shutdown operated (latched) – open circuit SCR (latched) – UPS Logic Board power supply failure MSCROP

Source: Sheet 3 – D22 pin 16 Description: ‘Static Switch SCR open circuit’ monitor – this input goes high to inform the micro that an open circuit static switch SCR has been detected (on this Board) (alarm #15 [I/P: SCR CUT-OFF]). This signal is latched within D22 and must be reset using S1 to return to normal conditions.

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M-ESD

Source: Sheet 3 – D22 pin 17 Description: ‘Emergency shutdown’ monitor – this input goes high to inform the micro that an emergency shutdown (Emergency Stop) has been applied (See paragraph 4.3.7.1) (alarm [#63] [CUT-OFF: EMERGENCY]). This signal is latched within D22 and must be reset using S1 to return to normal conditions. MBATMA

Source: Sheet 3 – D22 pin 15 Description: DC Overvoltage – this input goes high to inform the micro that a ‘DC Overvoltage’ has been detected (See paragraph 4.3.7.2) (alarm [#58] [DC BUS: FAST OVERV.] ). This signal is latched within D22 and must be reset by S1 to return to normal conditions. SEQMNS

Source: Sheet 5 – D34 pin 10 Description: Bypass phase sequence error – this input goes high to inform the micro that a ‘Bypass phase sequence error’ has been detected (See paragraph 4.3.14.1). Note that the Rectifier Logic Board detects a phase sequence error on the UPS (rectifier) input mains supply (See section 4 paragraph 2.3.6.1). A phase sequence error initiates alarm [#14] [I/P: PHASE ROT.ERROR] and also enables alarm [#16] [BYPASS INHIBIT] via the micro. EEDO

Source: Sheet 2 – D20 pin 4 Description: Output from the security EPROM to initiate the micro-controller. DRDO

Source: Sheet 3 – D18 pin 6 Description: Real Time Clock output (See paragraph 4.3.9). 4.3.11.5

Buf fer D51 – activ ated by CSIN3 PAIN1 to PAIN8

Source: Sheet 7 – X7 Description: Data from parallel control bus – not used in a ‘single-module’ installation. The Parallel Logic board interfaces with the micro via this buffer and is active only in the “1+1” and “multi-module” system configurations 4.3.11.6

Buf fer D60 – activ ated by CSIN3 BLK-SYN

Source: Sheet 7 – X8 pin 11 Description: Sync disable – this is an input from the optional ‘remote alarm’s board’ (AS400 interface board) which goes high (+5V) when the UPS is “ONGENERATOR” – and is normally used to prevent the inverter synchronising to a frequency-wild standby generator. The On Generator status signal is a pplied as a closed contact across the Remote Alarms Board terminal block X5 pins 3-4.


20-399



Note: The response to the “ON-GENERATOR” event is programmable via the Operator Control Panel FUNCTION software screen which allows three separate functions to enabled/disabled:

Synchro Block – is concerned with the [BLK-SYN> signal mentioned here and, when enabled, prevents the inverter from tracking the bypass frequency when it is being provided by the standby generator. • Charge Inhibit – is concerned with the battery recharge current limit function which, when enabled, reduces the RECTIFIER current limit by 15%. • Current Limit – is concerned with the rectifier input current limit [XRADD1> function which, when enabled, reduces the input current limit by 35%. The reduced current limit functions are employed to lower the potential maximum current demand if the standby generator is undersized.

•

BLK-EXT

Source: Sheet 7 – X8 pin 12 Description: From external alarms (AS400 interface board). This input provides a means of allowing the inverter to be turned OFF/ON from an external signal via the Remote Alarms Board. The ‘Block’ (OFF) signal is applied as a closed contact across the Remote Alarms Board terminal block X5 pins 1-2. Note: Jumper X6 on the Remote Alarms Board must be selected 2-3 in order to enable this function. BLK-01

Source: Sheet 7 – X8 pin 9 Description: From external alarms (AS400 interface board) Not used. BLK-CHG

Source: Sheet 7 – X8 pin 10 Description: Rectifier Disable – This input provides a means of allowing the rectifier to be turned OFF/ON from an external signal via the Remote Alarms Board. The ‘Block’ (OFF) signal is applied as a closed contact across the Remote Alarms Board terminal block X5 pins 1-2. Note: Jumper X6 on the Remote Alarms Board must be selected 1-2 in order to enable this function. Links X26

Source: Sheet 4 jumper X26 Description: The four sections of jumper X26 are detailed in a Table on the circuit diagram sheet 1 and summarized below:

20-400




Table 20-15: X26 Jumper details LINK 1-2

Open (Standard)

Auto-transfer mode enabled (“on-line” operation). Automatic load transfer from bypass to inverter when when the inverter is available – i.e. the inverter is is the preferred supply source

Clos Closed ed

Manu Manual al-t -tra rans nsfe ferr mode mode enab enable led d (“of (“offf-li line ne”” oper operati ation on). ). Automatic load transfer from bypass to inverter only bypass is the when the bypass is unavailable – i.e. the bypass is preferred supply source. Note: source. Note: there there will be a 3-cycle break on transfer to inverter,

LINK 3-4

LINK 5-6

Open Closed (Standard)

“Inverter voltage fail lockout monitor” enabled. i.e. The inverter is given 5 seconds to reach nominal voltage otherwise it is latched OFF.

Open (Standard)

Enables the “Event History” monitor to store up to a maximum of 10 alarms.

Clos Closed ed

LINK 7-8

4.3.1 4.3.12 2

“Inverter vo voltage fa fail lo lockout monitor” di disabled

Rese Resets ts the the “Ev “Even entt Hist Histor ory” y” moni monito torr. Note: Note: Afte Afterr the the 10th 10th “event”, the monitor buffer is full an cannot store any further “events”. The buffer should be reset to 0 after each maintenance or commissioning to enable new “events” to be captured.

Open (Standard)

Password protection enabled.

Close losed d

Pass Passw word ord pro prottect ection ion dis disa able bled

Data bus out put buff ers (circuit diagram sheet 4). Digital signals generated by the microcontroller as part of its control function are fed to the peripheral circuits via 10 type-74C273 octal latches (See Appendix A.2) which are accessed in pairs to provide a 16-bit data transfer (See Figure 20-21). The ‘chip select’ signals from D52 provide the latch clock signals and data is therefore transferred through the latches when the appropriate ‘chip select ’ signal switches from low to high. A logic low [RSTDX-> reset signal is connected to all the data bus output buffers via jumper X25 (3-2) and drives all their outputs low when applied. [RSTDX-> is produced by the microcontroller mic rocontroller (See paragraph 4.3.3) and shown on the circuit diagram sheet 2. The remainder of this sub-section lists the digital signals connected through the latches, and provides signal details where appropriate.

4.3.12. 4.3.12.1 1

Buf fers D7 and D10– D10– activ ated by CSDIS CSDIS

These two devices connect the data bus output to the two on-board 7-segment diagnostic displays (H11 & H12). For a detailed description of the displayed parameters (see paragraph 4.3.17 on page 20-422). 4.3.12. 4.3.12.2 2

Buf fer D17 D17 – activ ated by CSOU CSOUT1 T1 XRADD1


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20-401



Description: Reduced current limit – when this output goes high it reduces the Rectifier Logic Board’s input current limit threshold by 35% (See section 4 paragraph 2.3.4.2).

Conditions: This software-selectable output is activated when the UPS is running on ‘standby generator’ as described on page 20-399 ([BLK-SIN>). REC-B & REC-A

Destination: Sheet 7 – X1 pin 38 / 39 Description: Charge mode selection – these two outputs are connected to a decoder on the Rectifier Logic Board where they invoke one of four permissible charge modes (see section 4 table 4-3).

Conditions: These outputs select Test, Boost, Float and Manual Manual charge modes in response to selections made on the Operator Control Panel. The automatic Boost mode mode parameters, i.e. duration and threshold, are also operator-defined – (see paragraph 2.5.6 on page 2-53). LEDs on the Rectifier Logic Board illuminate to indicate the active charge mode. XAT01 & XATO2

Destination: Sheet 7 – X2 pin 55 / 56 Description: Not used INV-F

Destination: Sheet 7 – X3 pin 37 Description: Base frequency selection – informs the Inverter Logic Board’s ‘staircase pattern generator’ of the UPS system’s base frequency (i.e. 50/60Hz). (See section 18 paragraph 3.3.2).

Conditions: This output is high for 50Hz and low for 60Hz as selected on the Operator Control Panel – see ‘Selecting the UPS SETUP parameters’ in the commissioning procedure (see paragraph 2.4.5.3 on page 2-35). INV-B & INV-A

Destination: Sheet 7 – X3 pin 38 / 39 Description: Inverter working voltage selection – these two outputs are connected to a decoder on the Inverter Logic Board where they select one of four permissible charge modes (see section 18 table 18-10).

Conditions: The logic states of these outputs are determined by the working voltage selected by the operator – see commissioning procedure (see paragraph 2.4.5.2 on page 2-34). LEDs on the Inverter Logic Board illuminate to indicate the active selection. 4.3.12. 4.3.12.3 3

Buf fer D25 D25 – activ ated by CSOU CSOUT1 T1 XSTAO1 & XSTAO2

Destination: Sheet 7 – X5 pin 19 / 20 Description: Not used

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RE485-

Destination: Sheet 7 – D58 pin 2 Description: This output selects the ‘Read Enable’ pin of D58, which is an RS485 communications driver connected to the parallel interface connector X7 pins 59/60 – not used. OE485

Destination: Sheet 7 – D58 pin 3 Description: This output selects the ‘Output Enable’ pin of D58, which is an RS485 communications driver connected to the parallel interface connector X7 pins 59/60 – not used. TP5

Destination: Sheet 7 – X18 pin 5 Description: Not used (test point for system software). OUTBAT

Destination: Sheet 2 – V152 Description: This output, when high, ‘enables’ the on-board Ni-Cad battery charger.

Conditions: This output enables the Ni Cad battery charger if its voltage falls to 2.8Vdc and disables it again once the battery voltage rises to 3.6V. Note: when the charger is enabled the [BACK-UP BATTERY LOW] warning is annunciated (alarm [#76] active). 4.3.12. 4.3.12.4 4

Buf fer D9 – activ ated by CSOU CSOUT2 T2 EECS / EESK / EEDI

Destination: Sheet 3 – D18 pin 7 Description: These outputs control the data acquisition of EEPROM D20 ORCS

Destination: Sheet 3 – D18 pin 7 Description: Real Time Clock (RTC) ‘chip select’ (See paragraph 4.3.9). ORSK

Destination: Sheet 3 – D18 pin 4 Description: Real Time Clock (RTC) ‘serial communications clock input’ (See paragraph 4.3.9) 4.3 .9). ORDI

Destination: Sheet 3 – D18 pin 5 Description: Real Time Clock (RTC) ‘serial data input’ (See paragraph 4.3.9).


20-403



SELANA / SELANB

Destination: Sheet 6 Description: These two outputs are connected to the address inputs of three 2 pole multiplexers which select the analogue signals for the microcontroller’s A/D inputs – e.g. selecting the analogue signals for display purposes (kVA values are calculated in software using V x I). 4.3.12.5

Buf fer D21 – activ ated by CSOUT2 ALMRES

Destination: Sheet 3 – D22 pin 1 Description: Software controlled RESET – This output, when high, resets the Emergency Shutdown, DC Overvoltage and Open SCR fault latches within D 22.

Conditions: This facility is not programmed into the current software and it is therefore not used. INV-ON

Destination: Sheet 3 – D23 pin 6 Description: ‘Inverter ON’ request – This output, when high, requests D23 to issue an [ON_INV> command signal which is connected to the Inverter Logic Board and turns ON the inverter – provided other D23 inputs are correct (See paragraph 4.3.7.2).

Conditions: (see paragraph 7.2.3 on page 7-160) RSTOUT

Destination: Sheet 3 – D23 pin 8 Description: Software controlled “reset” – When low, this output resets the “load-on-inverter” signal the [L_INV> and “load-on-mains” signal [L_MAINS>.

Conditions: The signal deactivates the above signals while the micro is reloading the default parameters, which can be activated using the RELOAD UPS DATA selection on the Operator Control Panel menu screens. Note: the load should always be on the “Maintenance Bypass” before performing a “system reload”. L-INV

Destination: Sheet 3 – D23 pin 9 Description: ‘Load-on-inverter’ request – This output is interlocked with the [RSTOUT> signal within D23 (See paragraph 4.3.7.2). In order to command the

‘load-on-inverter’ this signal must be high and the [RSTOUT> signal low.

Conditions: (see paragraph 7.2.10 on page 7-180) LMAINS

Destination: Sheet 3 – D23 pin 11 Description: ‘Load-on-bypass (mains)’ request – In order to command the ‘load-on-bypass’ this signal and the [RSTOUT> signal must be high– see also [RSTOUT>, above.

Conditions: (see paragraph 7.2.10 on page 7-180)

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REC-ON

Destination: Sheet 3 – D23 pin 14 Description: ‘Rectifier ON’ request – This output, when high, requests D23 to issue an [ON_REC> command signal which is connected to the Rectifier Logic Board and turns ON the rectifier (provided other D23 inputs are correct (See paragraph 4.3.7.2)).

Conditions: (see paragraph 7.2.2 on page 7-158). IBOPEN

Destination: Sheet 3 – D23 pin 2 Description: Trip battery circuit breaker– This output, when high, r equests D23 to issue a [BAT_TRP> command signal which is connected to the High Voltage Interface Board and turns OFF the battery circuit breaker driver transistor.

Conditions: This signal is software driven via a programmable parameter setting entered from the Operator Control Panel to trip the battery circuit breaker when the battery is fully discharged (see page 2-37). The Emergency Shutdown and DC Overvoltage inputs to D23 pins 4 and 1 also trigger the battery trip signal when active (See paragraph 4.3.7.2). TP6

Destination: Sheet 7 – X18 pin 6 Description: Not used (test point for system software). 4.3.12.6

Buf fer D50 – activ ated by CSOUT3 PAOUT1....PAOUT8

Destination: Sheet 7 – X7 Description: Data to parallel control bus – used in ‘parallel’ installations only. 4.3.12.7

Buf fer D55 – activ ated by CSOUT3 PAOUT9 / PAOUT10

Destination: Sheet 7 – X7 Description: Data to parallel control bus – not used in a ‘single-module’ installation. OUT-03

Destination: Sheet 7 – X8 pin 25 Description: Output to I/O interface (remote alarms, AS400 interface etc.). Conditions: Not used MNS-KO

Destination: Sheet 7 – X8 pin 26 Description: Output to I/O interface (remote alarms, AS400 interface etc.).


20-405



Conditions: Logic high if mains (bypass) supply error – i.e. overvoltage [#11], undervoltage [#12], absent [#10] or bypass blocked [#17]. BATED

Destination: Sheet 7 – X8 pin 27 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Logic high if the battery voltage falls to its end-of-discharge level [#56] – as set by operator through Operator Control Panel (see page 2-37). It is also active if the battery breaker is open [#05] or the battery fuse is open [#57]. CHG-INH

Destination: Sheet 7 – X8 pin 28 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Logic high if the battery charger is inhibited (driven by the [BLK-CHG> signal described on page 20-400). Jumper X4 pins 1-2 must be linked

on the Alarm Board. SWBYP

Destination: Sheet 7 – X8 pin 29 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Logic high if maintenance bypass isolator is closed – accompanied by alarm #06 [ON MANUAL BYPASS] . OUT-01

Destination: Sheet 7 – X8 pin 23 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Not used in the present software implementation 4.3.12.8

Buf fer D54 – activ ated by CSOUT4 OUT-02

Destination: Sheet 7 – X8 pin 24 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Not used in the present software implementation OVT-BAT


Conditions: Logic high in the event of battery overtemperature – Not used in the present software implementation. SYN-KO


20-406




Description: Output to I/O interface (remote alarms, AS400 interface, Remote Alarms Monitor etc).

Conditions: Logic high if the inverter is unsynchronised to the bypass supply – i.e. if the phase displacement is more than ±9°. This condition will initiate alarm #35 [INVERTER: OUT OF SYNC]. ALL-GEN

Destination: Sheet 7 – X8 pin 17 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: This is the “Common Alarm” output to the Alarm Board and is active if any of the following alarms are present: [#05], [#06], [#10], [#11], [#12], [#16], [#17], [#24], [#33], [#34], [#52], [#56], [#57], [#66]. A400ON

Destination: Sheet 7 – X8 pin 31 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: This alarm is active when the load is on the UPS (inverter or by pass) and is interlocked with the Maintenance Bypass being closed. A400UF

Destination: Sheet 7 – X8 pin 32 Description: Output to I/O interface (remote alarms, AS400 interface etc). Condition: Mains Failure alarm; enabled by alarm [#01] and active when [#22] is energised. A400BL

Destination: Sheet 7 – X8 pin 33 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Low Battery warning; enabled by alarm [#01] and active when [#56] is energised. A400BY

Destination: Sheet 7 – X8 pin 34 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Load on Bypass; active when alarm [#18] is energised. 4.3.12.9

Buf fer D56 – activ ated by CSOUT4 MNSREC

Destination: Sheet 7 – X8 pin 20 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Rectifier input voltage failure – active when H9 is illuminated on the Rectifier Logic Board.


20-407



CS-KO

Destination: Sheet 7 – X8 pin 19 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Bypass-side Static Switch blocked – goes high if a fault is detected on the static switch (alarm [#16] present). BAT-DSC

Destination: Sheet 7 – X8 pin 13 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Battery discharging – active when alarm [#22] is present. OVL

Destination: Sheet 7 – X8 pin 14 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Overload – active when alarm [#33] or [#66] is present. OVT-DIS

Destination: Sheet 7 – X8 pin 15 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Overtemperature – active when alarm [#24] or [#34] is present. OVT-AMB

Destination: Sheet 7 – X8 pin 30 Description: Output to I/O interface (remote alarms, AS400 interface etc). Conditions: Output Air overtemperature – not used. XINV01

Destination: Sheet 7 – X3 pin 24 Description: Mains error inhibit to Inverter Logic Board transfer control. Conditions: On the Inverter Logic Board a circuit within D11 provides a control signal [RIF> which briefly transfers the voltage reference signal t o the bypass supply just before the ‘inverter-side’ contactor is closed; (see paragraph 3.3.3 on page 18-251) . This signal, [XIN01>, goes high to inform the Inverter Logic Board of a mains (bypass) voltage error and prevents the switch-over to the bypass supply reference from taking place; and so prevents the inverter locking to an outof-spec voltage. TP7

Destination: Sheet 7 – X18 pin 7 Description: Not used (test point for system software).

20-408



SECTION 7 - UPS System Control CHAPTER 4 - UPS Log ic B oard (4550004 E) Section 20:

4.3.13

Frequency sensin g and cont rol sign als Figure 20-22: Frequency synchronisation control

D42

X18-2 62 15

X2 D53

5

F-INM

VI-A

15

X4

X3 4

BACKM

34

BACK

D17 DATA BUS D54

D60

R247 15 INV-F 50 /60 Hz selection

6

37

37

SYNCM

5

50/60Hz signal synchronised to bypass (when present)

SYNC-KO

2

44

D1 27

Frequency Divider

26

z H 0 6 / 0 5

43 z H K k L 8 8 C 2 4

BLK-SYN Phase Locked Loop

9 VCO

X18-4 15

SYNC

Master Freq reference for Inverter Osc (correction)

UPS Logi c Board

4.3.13.1

INV-F

Clock signals to tri-wave generator

Sync Inhibit

D59

phase align

FRFB

34

Sync error detection

64

8Vp-p

F-IN

X18-3 63 16

R E L L O R T N O C O R C I M

Bypass supply R-phase voltage sensing

35

35

SYNC

14

13

Phase Comparator

D6 3 Inverter Logic Board

Frequency contr ol princ iples

The inverter frequency is determined by the VCO section of a phase locked loop i.c. (D6) on the Inverter Logic Board which provides a 288kHz (nominal) clock signal to a frequency-divider (within D1) which then clocks the multiplexers in the ‘reference voltage generator’ circuit (See section 18 paragraph 3.3.2). Base frequency selection

The inverter base frequency is selected via the Operator Control Panel during commissioning and is read by the microcontroller through the CAN bus. The micro responds by appropriately setting the [INV-F> output from D17-15 – Low = 50Hz and High = 60Hz. This is connected to the ‘frequency divider’ on the Inverter Logic Board where it determines the division factor – i.e. when [INV-F> is low the 288kHz VCO output is divided by 5760 to produce a 50Hz output at D1-26/ 27; when [INV-F> is high the division is 4800 and produces a 60Hz output. Frequency synchronisation

It is desirable that the inverter output is synchronised to the bypass supply under normal operating conditions as this enables a ‘closed’ load transfer to be carried

s7c3cOLD.fm - Issue 2 Dated 21/08/97

20-409



out in the event of a UPS fault – where-by the static switch SCRs are turned on at the same time as the inverter contactor is opened, and the load does not experience a supply break. If the inverter is not synchronised to the bypass supply there could be a large voltage difference across the static switch SCRs while the load is ‘on-inverter’ (i.e. SCRs OFF) which might damage the UPS/load equipment during a subsequent ‘closed’ transfer: in such circumstances an ‘open’ transfer takes place if the UPS develops a fault, where-by the inverter contactor is opened prior to turning ON the static switch SCRs. This causes a load supply break of up to 1 second, which is an inbuilt feature designed to avoid load damage. The frequency synchronisation control mechanism is quite complex and effectively based on two nested phase locked loops. The inner loop comprises D6 on the Inverter Logic Board and the outer loop is functionally provided by the microcontroller, under software control. 4.3.13.2

Frequency sync control and operation Inverter Logic Board phase-locked-loop (assuming 50Hz operation.)

The ‘phase comparator’ section of D6 compares the 50Hz output from D1-26, connected to D6-3, with a frequency reference signal annotated [SYNC> which is produced by the microcontroller and connected to D6-14 (available at test point X18-4). If the ‘phase comparator’ detects any phase difference between these two signals its output at D6-13 will modify the VCO’s frequency in such a way as to make the ‘frequency divider’ output at D1-26 match the [SYNC> signal frequency – i.e. the VCO frequency will be modified until the ‘phase comparator’ within D6 sees no error between these signals, whereupon the circuit can be considered to be phase-locked . Thus the inverter frequency tracks the [SYNC> signal ‘reference’ frequency. [SYNC> signal generation (assuming 50Hz)

The microcomputer monitors the bypass supply R-phase waveform [VI-A> via a comparator which extracts its frequency information, [F-INM>. This signal can be seen at X18-2 as a squarewave coinciding with the bypass supply R-phase zerocrossing points. The Inverter Logic Board frequency divider’s 50Hz output (D127) is also monitored and is available at X18-3, annotated [BACKM>. Under software control, the micro operates on these two signals in the same way as described above for the Inverter Logic Board’s phase-locked-loop. That is, it performs the ‘phase comparator’ and ‘VCO’ functions described above and produces a 50Hz output, [SYNC>, whose absolute frequency is controlled by the detected phase difference between [F-INM> and [BACKM> – i.e. the width of the pulse is directly proportional to the amount of phase difference. Example of sync control

The overall operation of the synchronisation control circuits can best be explained by example. Consider the case where the bypass frequency suddenly jumps from 50Hz to 50.5Hz: 1. The micro will sense the jump in bypass frequency through a rise in [F-INM> to 50.5Hz. 2. The micro will sense a phase error between [F-INM> and [BACKM> due to their frequency difference and will ramp-up the [SYNC> signal frequency because it senses that the bypass frequency is higher than that of the inverter.

20-410




3. The ‘phase comparator’ in the Inverter Logic Board’s phase-locked-loop will see the ramping [SYNC> frequency and detect that it is now higher than the frequency divider’s ‘50Hz’ output. 4. The phase comparator error output (pin 13) will call for an increase in VCO frequency, which will thus increase the ‘frequency divider’ clock rate and thereby demand an increased inverter frequency. 5. The two ‘50Hz’ outputs from the frequency divider also ramp-up in line with the inverter frequency and have two affects: a) The increasing output at D1-26 is fed back to the phase-locked-loop (D6-3) where it maintains phase-lock – i.e. it ties the clock frequency to the [SYNC> signal and maintains close tracking of this signal. b) The increasing output from D1-27 is fed back to the microcontroller via R247 where it allows the phase error function to maintain a close check on the ‘bypass/inverter’ frequency and phase relationship. 6. When the inverter frequency has risen to match the 50.5Hz bypass frequency, and the [F-INM> and [BACKM> signals are in phase: a) The [SYNC> frequency will stop ramping up and remain at 50.5Hz, synchronised to the bypass supply due to the action of the micro. b) The VCO clock frequency will remain constant – i.e. 290.88kHz (5760 x 50.5 – as 5760 is the divider factor for 50Hz systems). c) The outputs from D1 pins 26 and 27 will be steady at 50.5Hz and synchronised to the [SYNC> signal. 7. If [SYNC> is synchronised to the bypass supply (6a) and the frequency divider outputs/inverter are synchronised to the [SYNC> signal (6c) then this results in the inverter being effectively synchronised to the bypass supply, are required.

Important notes: The above description requires qualification by the following notes. a) The internal mechanism of the frequency divider chip ties its ‘50Hz’ out puts to the zero-crossing points of the R-phase inverter voltage. Thus, as the micro uses the bypass R-phase supply as its frequency sensing source, this effectively ensures that the inverter and bypass supplies are synchronised correctly from a phase alignment viewpoint. b) To aid description the above example assumed that the bypass frequency underwent a stepped change; however, in practice any change in bypass frequency is likely to occur gradually: in which case the circuit dynamics are usually able to maintain a phase-locked condition during the period of change, resulting in the inverter frequency tracking the bypass frequency at all times without incurring a detectable phase error. c) The synchronising ‘window’ and ‘slew-rate’ are adjustable and selected from the Operator Control Panel setup menus. The ‘window’ defines the limits to which the inverter is allowed to track the bypass frequency and normally set to ±2%; while the ‘slew-rate’ defines the maximum permitted rate-of-change of inverter frequency and is usually set to 0.1Hz/s.– i.e. this determines the fastest rate of change of bypass frequency tolerated by the synchronisation circuit whilst maintaining sync. If the bypass frequency goes outside the permitted window the inverter frequency will return to its base frequency and await the mains return


20-411



within the sync window, where-upon it will re-synchronise. An [INVERTER: OUT OF SYNC] (alarm #35) warning will be displayed while this situation is in effect. d) In the event of a bypass supply failure the microcontroller will drive its [SYNC> output to the ‘centre’ frequency – i.e. 50Hz. Sync phase adjustment

R247 is connected to a ‘phase-shift’ circuit on the Inverter Logic Board and provides the means for trimming any error in the phase relationship between the inverter [BACKM> and bypass [F-INM> sense signals once the sync control circuit is phase-locked – due mainly to component tolerances. Therefore, once the inverter is synchronised this resistor can be adjusted to reduce the residual phase difference between the inverter R-phase output and the bypass R-phase supply. 4.3.13.3

Non-Sync detecti on and alarm

An alarm condition [SYN-KO> is flagged by the microcontroller when it detects that the [BACKM> and [F-INM> signals are more than 11° out-of-phase. This is communicated to the Operator Logic Board via the CAN bus and also, via D54-6, to the I/O interface connector X8-16 where it can be used to provide a remote alarms indication (sheet 7). [SYN-KO> is ‘high’ when a non-sync condition is present. 4.3.13.4

External ‘sync inhibi t’

In certain circumstances it may be necessary to inhibit the synchronisation loop – for example when supplying the UPS from a stand-by generator whose frequency regulation is poor. This can be achieved by an external input via the I/O connector X8-11 [BLK-SYN> which is connected to the microcontroller via D60-2. This input must be taken ‘high’ to inhibit the synchronisation function (See paragraph 4.3.11.6). Note: The control can be activated only after being ‘enabled’ in the Function parameter software setup screen (see paragraph 2.4.7.3 on page 2-43).

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4.3.14


Analo gue sig nal pro cessing The UPS Logic Board monitors the UPS input voltage, output voltage, inverter voltage, battery voltage, output current and battery current. These inputs are processed by analogue circuits (sheets 6 & 7) which provide appropriate signals for the microcomputers A/D input port. In some cases the inputs are also converted to digital alarm/status signals which are connected to the micro via the data bus.

4.3.14.1

Bypass voltage signal processi ng

Figure 20-23: Bypass voltage sensing block diagram Line-Neut

Line-Line

N6 Buffer

N29 Sum-Amp

3-Phase Bypass Volts Sense

+5V +2.5V 0V

VIABM To A/D Multiplexers (Display uses)

VIBCM VICAM REF-2 (2.5V)

8Vp-p

N29d Rectifier

[SVI>

To SCR OPEN det.

[SVIM> To A/D Multiplexers (Bypass volts monitor)

A-Ph

B-Ph

N14 Filter

N14 Filter

[F-IN> To Micro

(sync control - bypass R-ph)

D27 Ph-Seq

[SEQMNS> To Micro (Phase Sequence error detector)

Voltage sensing

The bypass voltage sense signals ( [VI-A> - [VI-C>) are developed on the High Voltage Interface Board (See paragraph 2.3.6) and connected via X2 pins 15, 16, 17 to N6b/c/d which are unity-gain buffers (sheet 5). The signals at N6 outputs therefore equate to approximately 1% of the bypass supply line-neutral voltage (e.g. 2.4Vrms at 240V working) and are connected to several blocks as shown in Figure 20-23. Voltage monitoring

N29a-c take the line-to-neutral sense voltages produced by N6 and converts them into line-to-line sense voltages suitable for connecting to the microcontroller A/D inputs. Taking N29a as an example; this amplifier differentially sums the [VI-A> and [VI-B> signals from N6 and produces the [VIABM> L-L signal. However the amplifier attenuates the resultant signal to about 30% (e.g. 1.38V for 240V w orking) due to its feedback resistance ratios: also, the non-inverting input is connected to VREF-2 (2.5V reference voltage) rather than to the 0V rail, which therefore applies a 2.5V offset to [VIABM>. Thus in a 240V system working at nominal voltage [VIABM> is approximately 3.9Vp-p centred on a 2.5V reference. This signal sits well within the microcontroller’s A/D 0-5V input level, a nd is shown connected to the A/D multiplexer circuit (sheet 6). Note: if the bypass voltage is missing [VIABM> will be 2.5Vdc due to the absence of any ac signal.


20-413



Bypass frequency and phase sequence monitors

The bypass R-phase signal [VI-A> from N6-14 is connected to a zero-crossing circuit comprising N14a/d which produces a squarewave output [F-IN> at D34-6 which coincides with the R-phase zero-crossing points. This signal is used by the microcontroller in its frequency synchronisation control (See paragraph 4.3.13.1). A similar squarewave coinciding with the S-phase is obtained via N14b/c and buffered by D34-8. These two squarewave signals are connected to a D-type flipflop (D27) which detects their phase relationship. Under normal circumstances the R-phase signal should lead that of the S-phase; therefore when the rising-edge R-phase signal clocks D27, its data ( D) input should be ‘low’, producing a permanent ‘high’ on its Q output which inverted to a ‘low’ [SEQMNS> signal at D34-10. In the event of a phase sequence error, D27 will have a permanent ‘low’ clocked through to its Q output and produce a ‘high’ [SEQMNS> signal. [SEQMNS> is connected to the microcontroller via the data bus buffer D28-7

where it flags a phase rotation error – [I/P: PHASE ROT.ERROR] alarm #14 (See paragraph 4.3.11.4). 3-phase voltage monitor

A full-wave, three-phase diode bridge comprising V34-V36 & V40-V42, produces a dc voltage proportional to the full three-phase supply which is fed to N29d. This amplifier attenuates the signal by 55% due to the values of the feedback resistors; therefore the output at N2-14 is approximately 2.5Vdc at nominal working voltage. Note that this is a ripple voltage since there is very little capacitance around the amplifier. Thus if any bypass phase voltage goes out of tolerance (e.g. ±10% window) the detector will sense the error. It does not require all three phases to go outside the error window. N2-14 provides signals to two other areas: [SVIM> is connected to the microcontroller A/D input via the multiplexer circuit shown on sheet 6 and used by the micro to monitor the bypass voltage for a each individual phase (e.g. ±10% voltage error); and [SVI> is connected to the circuit (also on sheet 6) which detects an open circuit static switch SCR. 4.3.14.2

Inverter vol tage sensi ng

Figure 20-24: Inverter voltage sensing block diagram error detected on individual phase

8Vp-p

2.2Vdc

Line-Neut 3-Phase Inverter Volts Sense

N3a-c Buffer

N3d Rectifier

[SVINVM> To A/D Multiplexers

Voltage sensing

The inverter voltage sense signals ( [VINV-A> - [VINV-C>) are developed on the High Voltage Interface Board (See paragraph 2.3.5) and connected via X2 pins 18, 19, 20 to N3a-c which are unity-gain buffers (sheet 5). The signals at N3 outputs therefore equate to approximately 1% of the inverter line-neutral voltage. A fullwave, three-phase diode bridge produces a dc voltage proportional to the full three-phase output which is then fed to N3d. This amplifier attenuates the signal

20-414




by 55% due to the values of the feedback resistors; therefore the output at N3-14 is approximately 2.5Vdc at nominal voltage, and connected to the microcontroller A/D input via the multiplexer circuit s hown on sheet 6. This is a ripple voltage as described previously, and is monitored by the inverter voltage error software function (i.e. ±10%). 4.3.14.3

Batter y (bus) vol tage sensi ng

Figure 20-25: Battery voltage sensing block diagram [VBM> 3.25Vdc @ 446V(bat)

To A/D Multiplexers

N13a Buffer

[V-B>

N13c Comparator

[BAT-MA> DC Overvoltage (Fast) (set to 620V(bat))

Battery volts monitor

The DC busbar (battery) voltage sense signal [V-B> is developed on the High Voltage Interface Board (See paragraph 2.3.3) and connected via X2 pin 27 to N13a which is a unity-gain buffer (sheet 5). The signal sensitivity is set on the High Voltage Interface Board to approximately 7.3mV per Volt (bat) therefore [VBM> is about 3.255V at nominal 446V float charge voltage. This signal is connected to the microcontroller A/D input, via the multiplexer circuit shown on sheet 6, where it is used by several software functions, such as: display metering; slow DC overvoltage (max 2.4V/cell window); Low Battery warning (1.82V/cell window); End of Discharge (1.67V/cell window); and % charge/autonomy time algorithms. DC Overvolts detection (Fast) [VBM> is also monitored by N13c, which is configured as a comparator and used

to detect a DC Bus overvoltage condition. N13c has a fixed threshold which operates ([BAT-MA> goes high) when [VBM> reaches approximately 4.45V, which equates to a DC Bus voltage of around 620Vdc. [BAT-MA> is connected to the ‘Basic System Control Logic’ where it trips the bat-

tery circuit breaker, turns off the rectifier and inverter, and trips a latch (See paragraph 4.3.7.1). In an overvoltage situation – [DC BUS: FAST OVERV.] alarm #58 – the ‘Basic System Control Logic’ responds by issuing a ‘high’ [MBATMA> signal which flags the micro-controller via data bus buffer D26 (See paragraph 4.3.11.4). 4.3.14.4

Batter y cur rent sensi ng

Figure 20-26: Battery current sensing block diagram REF-2 (2.5V)

[I-B>


N13b Buffer

[IBM> To A/D Multiplexers

20-415



Battery current monitor

The battery current sense signal [I-B> is developed on the High Voltage Interface Board (See paragraph 2.3.22) and connected via X2 pin 31 to N13b which has a gain of approximately1.5 (sheet 5). The signal sensitivity is set on the High Voltage Interface Board by jumper X38 and the output [IBM> is connected to the micro-controller A/D input via the multiplexer circuit shown on sheet 6 where it is used for display purposes, and % charge and Autonomy Time algorithms. 4.3.14.5

Outpu t vol tage sensi ng

Figure 20-27: Output voltage sensing block diagram +5V +2.5V

Line-Line 3-Phase Output Volts Sense

N5 Buffer

N31 Sum-Amp

0V

VOABM VOBCM VOCAM REF-2 (2.5V)

8Vp-p

N15a Rectifier

[SVI>

To A/D Multiplexers (Monitoring & display)

[SVOM> To A/D Multiplexers (Critical bus monitor)

N15b-d Comparator

[SCROPN> To Micro (SCR open cct.)

Line-Neut N30 Buffer

VOAM VOBM VOCM

To A/D Multiplexers (monitoring & display)

REF-2 (2.5V)

Voltage sensing

The bypass voltage sense signals ([VO-A> - [VO-C>) are developed on the High Voltage Interface Board (See paragraph 2.3.6) and connected via X2 pins 21, 22, 23 to N5a-c which are unity-gain buffers (sheet 6). The signals at N5 outputs therefore equate to approximately 1% of the output line-neutral voltage (e.g. 2.4V (8Vp-p) at 240V) and connected to several blocks as shown in Figure 20-27. Voltage monitoring

The signals from N5a-c are connected to two sets of buffers which provide lineto-neutral and line-to-line monitoring voltages which are connected to the microcontroller A/D inputs via the multiplexer circuit shown on sheet 6 and used for metering & display purposes.

L-N voltage monitoring. is provided by N38a-c which attenuate the voltage sense signals by approximately 55% and also applies a 2.5Vdc offset due to the non-inverting connection being terminated at VREF-2 (2.5V reference voltage). At 240V nominal voltage the monitor output signals [VOAM>, [VOBM>, VOCM> are therefore 1Vrms (2.8V p-p) centred about a +2.5V reference which sits well within the microcontroller’s A/D 0-5V input level. Note: if the output voltage is missing [VOAM> etc. will be 2.5Vdc due to the absence of any ac signal.

20-416




L-L voltage monitoring. is provided by N31a-c. Taking N31a as an example; this amplifier differentially sums the A and B phase signals from N5 and produces the [VOABM> L-L signal. However, the amplifier attenuates the resultant signal by about 70% (e.g. 1.38V for 240V working) due to its feedback resistance ratios: also, as with the L-N circuit described above, the non-inverting input is connected to VREF-2 (2.5V reference voltage) rather than to the 0V rail, which applies a 2.5V offset to [VOABM>. Thus in a 240V system working at nominal voltage [VOABM> is approximately 3.9Vp-p centred on a 2.5V reference. 3-phase voltage monitor

A full-wave, three-phase diode bridge comprising V29-V31 etc, produces a dc voltage proportional to the full output three-phase supply which is fed to N15a. This amplifier attenuates the signal by 55% due to the values of the feedback resistors; therefore the [SVOM> output at N15-1 will be approximately 2.5Vdc at nominal working voltage. Note that this is a ripple voltage s ince there is very little capacitance around the amplifier. [SVOM> is connected to the microcontroller Ato-D inputs via the multiplexer circuit shown on sheet 6. This is used by the micro-controller as a critical bus voltage error monitor (factory set to ±10%) for transfer functions. Open Circuit Static Switch SCR detection

As shown in Figure 20-27, the output voltage (3-phase) sense signal [SVOM> and bypass voltage (3-phase) sense signal [SVI> are both connected to the Static Switch ‘SCR open circuit’ detector. 4.3.14.6

Output curr ent sensing

Figure 20-28: Output sensing block diagram REF-2 (2.5V)

3-Phase Output Current Sense

N4a-c Buffer

N4d Sum-amp

[IOAM> [IOBM> [IOCM>

[IONM> To A/D Multiplexers (Overload & Timers)

(Display Metering)

Output current monitor

The UPS output current sense signals ( [IO-A> - [IO-C>) are developed on the High Voltage Interface Board (See paragraph 2.3.19) and connected via X2 pins 32, 33, 34 to N4a-c which attenuate the sense signals by approximately 75% and also applies a 2.5Vdc offset due to the non-inverting connection being terminated at VREF-2 (2.5V reference voltage). The output signals [IOAM> etc. are connected to the microcontroller A/D inputs via the multiplexer circuit, and the 2.5V offset is sufficient to make the a.c. current signal sit within the 0-5V A/D input voltage range. These signals are by the micro’s ‘overload’ algorithm (i.e. 150% for 1 minute, 125% for 10 minutes, 110% for 1 hour, 101% for 9 hours. They als o represent the values shown on the Operator Control Panel ‘ Measurements’ display screen.


20-417



N4d calculates the neutral current by differentially summing the three line currents – in a balanced three phase system the algebraic sum of the currents should equal zero, thus if the system is unbalanced then the amount of imbalance represent the current flowing in the neutral path. The neutral current signal [IONM> is also subject to the 2.5V offset and applied to the microcontroller A/D inputs via the multiplexers in the same way as the line current signals. 4.3.14.7

Analogue signal monit oring multi plexers

The microcontroller has ten A/D inputs ( [AN0> to [AN9>). [AN6> to [AN9> are fed by fixed inputs signal sources; however, [AN0> to [AN5>

are fed via a series of multiplexers which allow the micro to select from various signal sources. Three type 4052 multiplexers are used for this purpose, each addressed by two signals ([SELANA> and [SELANB>) produced by the microcontroller via data bus buffer D9 (See paragraph 4.3.12.4). Sheet 6 contains the multiplexer circuit and illustrates the various monitored signals connected to t heir data pins (See Appendix A.3) . The multiplexers are inhibited if the -12V power supply monitor detects an undervoltage by applying a logic high [FL-12-> to the multiplexer inhibit inputs (pin 6) (See paragraph 4.3.15.3). Note: the inputs annotated [T1> - [T4> are temperature sensing inputs – refer to the High Voltage Interface Board description (See paragraph 2.3.12). Note: the micro can access the A/D signals in parallel and where necessary can calculate values for the display – e.g. kW = V x I.

20-418



SECTION 7 - UPS System Control CHAPTER 4 - UPS Log ic B oard (4550004 E) Section 20:

4.3.15 4.3.15.1

Power supp lies General descripti on and voltage regulators

The UPS Logic Board ±12V power supply rails are provided from two parallel sources and will be available if either source is live. The first source is from the Rectifier Logic Board, which is itself powered from the AC-DC Power Supply and available whenever the UPS input (rectifier) supply is live (see paragraph 2.1 on page 3-5); the second if from the Inverter Logic Board, which is powered from the DC-DC Power Supply and is available whenever the rectifier is working or the batteries are connected to the DC Busbar (see paragraph 3.1 on page 3-7). From the UPS Logic Board the ±12V supplies are passed directly to all the remaining circuit boards and the communications port etc. 4.3.15.2

Reference vol tage generator s

Several devices require a stable +5V power supply which is provided by a simple 3-terminal +5V regulator (N1), shown on sheet 7. In addition to the +5V power supply rail, there are also two reference voltage generators on the circuit board. One generates a regulated +5V, [VREF>, from the +12V line and the other generates a regulated 2.5V output, [VREF-2>, from the +5V supply rail. These reference voltages are used in conjunction with the microcontroller’s A/D analogue inputs and are shown on sheet 5 of the circuit diagram. +5V reference voltage [VREF>

This provides a stable power supply for the A/D converters within the micro which is necessary for them to maintain their conversion accuracy. 2.5V reference voltage [VREF-2>

The micro-controller’s internal A/D converters operate on stable 0V and +5V power rails, as described above. Therefore if an AC signal is to be monitored (e.g. bypass voltage), or a positive-and-negative going DC signal (e.g. battery current), then a 2.5V offset is required shift the 0V point of the monitored signal into the centre of the A/D converters’ input working range. This enables the A/D circuit to convert both halves of an AC waveform and both positi ve and negative transitions of a dc signal voltage. 4.3.15.3

-12V und ervol tage detecto r

Comparator N45a (sheet 5) serves as a -12V supply rail monitor and detects when the -12V is less than approximately -9.8V. The operating threshold for this circuit is set by V70 which applies a zener referenced voltage across R242/243 from the +12V rail and under normal conditions sets N45-3 at about 1.86V. The -12V rail is monitored via a resistor divider (R240/241) which is fixed at +3V at one end by V70. Due to the chosen resistor ratios, the voltage at N45-2 rises above 1.86V when the -12V rail is less than -9.8V, at which point N45-1 switches low and produces a logic high [FL-12-> signal and low [FL-12>. When [FL-12> goes low it inhibits the back-up battery voltage sense signal to the microcontroller via D44, as shown on diagram sheet 2 (See paragraph 4.3.4). When [FL-12-> goes high is disables the microcontroller’s A/D input multiplexers, as shown on sheet 6 (See paragraph 4.3.14.7).

s7c3dOLD.fm - Issue 2 Dated 21/08/97

20-419


4.3.15.4


+12V und ervol tage detecto r

Comparator N45b (sheet 5) serves as a +12V supply monitor. The operating threshold for this circuit is set by [VREF-2> which applies a stabilised +2.5V to N45-6, at about 1.86V. The +12V rail is monitored via a resistor divider (R246/ 245/R244) which pulls the input to N45-5 below the 2.5V threshold when the +12V rail fall below the 9.8V level. When this occurs the output at N45-7 switches from high to low which is reflected at D57-8 and the resulting ‘low’ [PFO> flag resets the microcontroller via its non-maskable interrupt (NMI) (See paragraph 4.3.2). The micro jumps to a ‘save data’ subroutine as the supply rails are crashing.

20-420



4.3.16


External comm uni cation s RS232 communications

In addition to the bi-directional communication facility with the Operator Logic Board via the CAN Bus, the microcontroller can also be accessed externally via a standard RS232 communications connection (X9). This is designed to be used with a portable computer for diagnostic, calibration and configuration purposes. Communication takes place through D16 which is a standard RS232 line driver/ receiver connected to the micro via [TXO0> and [RXO0>, as shown on sheet 7 (See Appendix A.6) . RS-485 Parallel control communications

An RS485 communications facility is also shown on sheet 7, based around D58 (See Appendix A.5). The differential I/O bus of this device (pins 6 & 7) is connected to the Parallel Logic Board via X7 ( [TXRX+>, [TXRX->).

Transmit mode. the transmit mode is enabled when

[DE485> is high, whereup-

on the [TXDI> data from the microcontroller, applied to D58 pin 4, passes through the device and drives its differential outputs as described in appendix A.5. Note that X32 should be made in order to connect the bus termination resistor (R250) across the transmission line to present the correct impedance to the differential outputs.

Receive mode. the receive mode is enabled when

[RE485-> is taken low, where-

upon the data on the differential I/O bus is converted into a data-stream and connected to the microcontroller via [RXDI>.


20-421


4.3.17


On board 7-segment ind icatio ns sum mary The following table provides a summary of the alarm codes indicated on the two 7-segment LEDs together with their alarm interpretations and associated Operator Panel audible and visible alarm annunciations. Note that there is no on-screen alarm history facility, but where two (or more) alarms are active simultaneously the associated codes will be displayed in a cyclic fashion at 1 second intervals Note: Where the fault LED state is annotated (*) this indicates that the alarm is latched and must be reset using S1 on the UPS Logic Board

CODE




01

[ NORMAL OPERATION ]

OFF

OFF

02

[ BYPASS BREAKER OPEN ]

Continuous

ON

03

[ OUTPUT BREAKER OPEN ]

Continuous

ON

04

[ RECTIF. BREAKER OPEN ]

Continuous

ON

05

[ BATTERY BREAKER OPEN ]

Continuous

ON

06

[ ON MANUAL BYPASS ] Manual bypass breaker closed

Pulsed

Flashing

10

[ I/P: ABSENT ] Bypass supply absent – i.e. <50V

Intermittent

Flashing

11

[ I/P: OVER LIMITS ] Bypass supply over voltage – upper limit set via mimic menu

Intermittent

Flashing

12

[ I/P: UNDER LIMITS ] Bypass supply under voltage – lower limit set via mimic menu

Intermittent

Flashing

13

[ I/P: FREQUENCY ERROR] Bypass supply over/under freq – window limit set via mimic menu

Intermittent

Flashing

14

[ I/P: PHASE ROT. ERROR ] Bypass phase rotation error

Continuous

ON

15

[ I/P: SCR CUTOFF ] Bypass SCR open circuit

Continuous

ON *

16

[ BYPASS INHIBIT ] Bypass supply blocked – hardware block on UPS Logic Board

Pulsed

Flashing

17

[ BYPASS INHIBIT REM. ] Bypass blocked via operator menu

Pulsed

Flashing

18

[ LOAD ON BYPASS ]

Intermittent

Flashing

19

[ BYPASS OVERTEMPERAT. ] Static bypass overtemperature warning

Continuous

ON

20

[ RECTIFIER: OFF ] Software block via micro

Intermittent

Flashing

20-422







21

[ RECTIFIER: OFF REM. ] Rectifier blocked via operator menu

Pulsed

Flashing

22

[ RECTIFIER: BLOCK ] Hardware block via UPS Logic Board

Continuous

ON

23

[ RECTIFIER: I/P LIMIT ] Rectifier input current limit

Intermittent

Flashing

24

[ RECTIFIER: OVERTEMP. ] Rectifier overtemperature

Continuous

ON

25

[ RECTIFIER: FUSE FAIL ] Input fuse failure (F10,F11,F12)

Continuous

ON

30

[ INVERTER: OFF ] Software block via micro

Intermittent

Flashing

31

[ INVERTER: OFF REM. ] Inverter blocked via operator menu

Intermittent

Flashing

32

[ INVERTER: BLOCK ] Hardware block via UPS Logic Board

Continuous

ON

33

[ INVERTER: CURR. LIMIT ] Inverter 150% current limit active

Continuous

ON

34

[ INVERTER: OVERTEMP. ] Inverter overtemperature

Continuous

ON

35

[ INVERTER:OUT OF SYNC ] Inverter unsynchronised to bypass warning

Intermittent

Flashing

36

[ INVERTER: OVERVOLTA. ] Inverter overvolts warning

Continuous

ON

37

[ INVERTER: UNDERVOLTA. ] Inverter undervolts warning

Continuous

ON

38

[ INVERTER: FUSE FAIL ] Inverter fuse failure

Continuous

ON

39

[ OUTPUT: OVERVOLTAGE ] Inverter overvoltage trip – critical bus overvoltage trip to bypass

Continuous

ON

40

[ OUTPUT: UNDERVOLTAGE ] Critical bus undervoltage trip to bypass – level set via mimic menu

Continuous

ON

41

[ OUTPUT: NO VOLTAGE ] UPS in off-line mode

Continuous

ON

42

[ OUTPUT: WRONG W.FORM ] Critical bus peak voltage error

Continuous

ON

43

[ INVERTER: WRONG FREQ ] lnverter frequency error – inverter frequency window is twice the bypass window

Continuous

ON

CODE


20-423






44

[ INVERTER: SEL. BLOCK ] Paralleling current error

Continuous

ON *

50

[ BATTERY: UNDER TEST ] Battery test in operation

Pulsed

OFF

51

[ BATTERY: TEST FAILED ] Battery test has failed

Intermittent

Flashing *

52

[ BATTERY: DISCHARGING ] Battery is discharging

Intermittent

Flashing

53

[ BATTERY: E.O.D. ] Battery end_of_discharge trip – level set via mimic menu

Continuous

ON

54

[ MAX.DUR.BOOST CHARGE ] Boost charge period expired

Pulsed

Flashing

55

[ DC BUS: OVERVOLTAGE ] DC slow overvolts warning – level set via mimic menu

Continuous

ON *

56

[ DC BUS: UNDERVOLTAGE ] Low battery warning – level set via mimic menu

Continuous

ON

57

[ BATTERY: FUSE FAIL ] Battery fuse (F13) failure

Continuous

ON

58

[ DC BUS: FAST OVERVOLT. ] Fast dc overvoltage – fixed at 620V

Continuous

ON *

60

[ BYPASS OVERUSE ] Transfer counter exceeded – i.e. >8 transfers in 1 minute

Continuous

ON *

61


Continuous

ON *

62

[ CUT-OFF: OVERTEMPER. ] Overtemperature timer expired

Continuous

ON *

63

[ CUT-OFF: EMERGENCY ] “Emergency power-off” activated

Continuous

ON *

66

[ OVERLOAD ] Overload present (warning)

Continuous

ON

67


Continuous

ON *

70

[ BAD EEPROM PROGRAM. ] Start-up error – use mimic reset

Pulsed

ON

CODE

20-424







71

[ ERR. LRC PARAM.PAG1 ] Incorrect display variable

Pulsed

ON

72


Pulsed

ON

73


Pulsed

ON

74

[ ERR LRC ALARM HIST. ] Alarm History buffer error

Pulsed

ON

75

[ ERR LRC EVENT HIST. ] Alarm History buffer error

Pulsed

ON

76

[ BACK-UP BATTERY LOW ] Internal PCB ni-cad battery Low

Pulsed

ON

80

[ ERROR LRC TABLE ]

81

[ ERROR LRC PANEL ]

82

[ MODEM WRONG CONFIG. ]

83

[ ERROR LRC ALARM MEM. ]

84

[ MODEM NO RESPONSE ] Modem incorrectly connected

85

[ MODEM FALSE COMMAND ] Modem incorrectly configured

86

[ MODEM TIMEOUT TRASM. ] Modem baud-rate error

87

[ CAN BUS NO RESPONSE ] UPS-to-display not connected

88

[ AUTONOMY XXXX min ] Battery autonomy time

CODE


20-425


4.4


Summary inf orm ation Table 20-16: UPS Logic Board configuration jumpers

Jumper

Link Position

X11

NO LINK

X12

X13

X14

X15

X16

X17

X19

X20

X21

X22

X23

20-426

Function Disable RS232 port (standard)

1 - 2

Enable RS232 port

OPEN

(standard)

1-2

Not Required

3 - 4

Not Required

1-2

EPROM Enable

2-3

RAM Enable (standard)

1-2

Not Required

3 - 4

Not Required

5-6

Not Required

7-8

Not Required

1-2

PLL option with CAP IN

2-3

PLL option with FIN AUX

OPEN

Testing only normally open

(standard)

CAN Bus to display disabled

1 -2

CAN Bus to display enabled (standard)

1-2

ALE enable data save

2 -3

Power supply fail enable data save (standard)

1-2

EPROM II enable (not required)

2-3

RAM II enable (not required)

1-2

+5V PCB enables microprocessor ref. For VA calculations (standard)

2-3

V ref. enables microprocessor ref. For VA calculations

1-2

Not Required

2-3


1-2


2-3

Not Required

1-2

Not Required

2-3


3-4

Not Required

4-5

Not Required




Jumper

Link Position

X24

1-2


2-3


3-4


4-5


1-2

Manual reset of output buffers

2- 3

Microprocessor reset of output buffers (standard)

1-2

Open (Standard) Auto-transfer mode enabled (“on-line” operation). Automatic load transfer from bypass to inverter when the inverter is available – i.e. the inverter is the preferred supply source. Closed Manual-transfer mode enabled (“off-line” operation). Automatic load transfer from bypass to inverter only when the bypass is unavailable – i.e. the bypass is the preferred supply source. Note: there will be a 3-cycle break on transfer to inverter.

3-4

Open “Inverter voltage fail lockout monitor” disabled. Closed (Standard) “Inverter voltage fail lockout monitor” enabled. i.e. The inverter is given 5 seconds to reach nominal voltage otherwise it is latched OFF.

5-6

Open (Standard) Enables the “Event History” monitor to store up to a maximum of 10 alarms. Closed Resets the “Event History” monitor. Note: After the 10th “event”, the monitor buffer is full an cannot store any further “events”. The buffer should be reset to 0 after each maintenance or commissioning to enable new “events” to be captured.

7-8

Open (Standard) Password protection enabled Closed Password protection disabled

X25

X26

X28

OPEN CLOSED

X29

OPEN 1-2

X31

OPEN 1-2

X32

OPEN 1-2


Function

Power up reset enabled (standard) Power up reset disabled 2.5V power supply monitor enabled (standard) 2.5V power supply monitor disabled Internal battery disabled Internal battery installed and charger enabled (standard) RS485 port disabled RS485 port enabled (standard)

20-427



Table 20-17: UPS Logic Board potentiometer adjustment Potentiometer

Function

R209

5 volt reference adjustment. Check at X20 pin 1

R212

2.5 volt reference adjustment. Check at anode of V45

Table 20-18: UPS Logic Board LED indication

20-428

LED

Colour

H1

Red

Function Internal battery charger operating


Section 7:

Chapter 5 - Operator Logic Board

5.1

Chapter overview This chapter contains a circuit description of the Operator Logic Board used across the entire 7200 Series UPS model range, and should be read in conjunction with circuit diagram SE-4550005-F (4 pages). Signal annotations shown on the circuit diagrams are shown in italics in the following text – e.g. [CLKOUT>. Where a signal is ‘active low’ it is followed by a negating symbol – e.g. [RSTD->

5.2 5.2.1

General descri pti on Circuit board functio ns The Operator Logic Board provides a microprocessor-controlled interface between the Operator Control Panel and the microcontroller-based UPS control system on the UPS Logic Board. Its primary functions can be summarised as follows: • Display indication– The UPS Logic Board provides the Operator Logic Board with data pertaining to various system operating parameters which are converted to a format suitable for driving the Operator Control Panel LCD display. • Operator input– The Operator Control Panel switches are monitored by the Operator Logic Board which converts any switch operation into a format understood by the UPS Logic Board. • External communications options – The Operator Logic Board provides several external communications facilities for use with remote alarm/control stations. Connector X8 – provides a two-way RS232 read/write control port. Connector X5 – provides a one-way RS232 read only control port. Connector X5 – provides a one-way RS485 read only control port. The board also contains an RS232/modem interface which can be used for diagnostic purposes. • Isolated power supply – An isolated power supply is contained on the Operator Logic Board which is used by the circuits associated with t he communications facilities. Internal communications between the Operator Logic Board and the UPS Logic Board is by means of a CAN bus (Controller Area Networking). Power supply isolation increases noise immunity a nd helps avoid spurious data transfer between the micro-computer systems contained on each board.

s7-c4.f m5 - Issu e 2 Dated 21/08/97

7-133

SECTION 7 - UPS System Control CHAPTER 5 - Operator Log ic Board

5.2.2


Input/Outpu t con nectio ns Figure 7-29: Operator Logic Board connections RS232 Modem Facility (read/write)

RS232 Comms (Reserved) (read only)

RS485 Comms Facility (read only)

X8

X5

X4

Operator Logic Board X1

X9

X2 Isolated power supply feed

X4 Operator Panel

CAN Bus

X6 UPS Logic Board

The Operator Logic Board has six connectors (See Figure 7-29) whose connections are summarised below. • • • • • •

7-134

X1 – Connection to the Operator Control Panel X2 – System control and monitoring signals to/from the UPS Logic Board. This connection takes the form of a serial data link (CAN Bus). X4 – Standard RS485 comms port (read only) X5 – Standard RS232 comms port (read only) X8 – Standard RS232 comms port/modem interface available for external control/monitoring/diagnostics facilities (read/write) X9 – Control power supplies (±12V) from the system control power rails via the UPS Logic Board.

s7-c4.f m5 - Issu e 2 Dated 21/08/97


5.2.3


Blo ck Diagram Figure 7-30: Operator Logic Board basic block diagram

s u B N A C

r s G h c a r i a D r t E a w h 1 L B S C X

/ 3 X d e 2 t i r a t S o e r R P R W

2 1 e D d o N c e A D C

M A R

t n t e s m a r t s t u 1 n j 2 o d R C A

e l d a o 1 i r c 1 e e D S D

s u B a t a D r o s u B s s e r d d A

y h a c l p t s a i D L

a t a D

M O R s e h c t i w S

s D E L

h c t a L X A

S D E L

X D

z H k c o M l 0 C 2

0 P

4 P

t r e e 6 s w 2 e o R P X

1 P

5 P 6 6 1 C 0 8 = 2 D

3 P

3 n r 2 o X H

s7-c4.f m5 - Issu e 2 Dated 21/08/97

s e h c t i w S

9 1 D

0 2 D

2 d y 3 a l 2 e n S R O R

5 d y 8 a l 4 e n S R O R

7-135


5.2.3.1



The Operator Logic Board control system is based on a type 80C166 microcontroller, as shown in Figure 7-30. This device, which is identical to that used on the UPS Logic Board, contains six configureable ports through which it communicates with peripheral circuits/devices, together with several ‘system control lines’. It also contains several internal A/D converters, four programmable timers and internal ROM (32k) and RAM (1k). The ports are configured by an initialisation routine performed by the system software on power-up and can be summarised as follows. •

•

•

•

•

•

•

Port 0 Port 0 is configured as a multiplexed Data/Address bus and is connected to both the Address and Data bus ports of the peripheral devices through a series of controlled latches, providing an 8-bit data bus or 16 bit address bus . Port 1 This is configured as a 16-bit output port. Its primary outputs, [LD1> to [LD9> drive the Operator Control Panel LEDs. Other outputs provide the LCD display ‘read’ and ‘write’ control signals and ‘chip select’ signals for the RS485 communications port device. Port 2 Three lines of this port are used in conjunction with the CAN serial data controller. For reasons of clarity this port is not shown in Figure 7-30. Port 3 This port is configured to work with the internal timers and is used to control the RS232 and RS485 access, and also the audible warning sounder associated with the UPS Alarms annunciation. Port 4 The lower two lines only are utilised on port 4. These provide the upper two address lines – the lower address lines are provided by port 0. These lines, which do not pass through the selectable buffers used by the lower 16 address lines, are always available and used as inputs by the ‘address decoding’ which produce the ‘chip select’ signals used by the various peripheral devices. Port 5 The lower five lines of this port monitor the Operator Control Panel switches and detects their operation. System control lines In addition to the I/O ports, the mi crocontroller also has a control bus with I/O lines generally associated with a microprocessor-based system; such as a system clock, reset, address latch enable, power reset and Read/Write control. These are connected to the peripheral devices where required.

Memory

The microcontroller uses both internal and external memory; 256k of RAM and 256k of EPROM are fitted to the board as standard and holds the system operating software. Facilities are included on the board to allow alternative memory configurations to be used as described later.

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Data/Address latch & buffers

The 16-bit data/address bus is connected to the various peripheral devices and boards via input and output data latches/buffers, as shown in Figure 7-30. These buffers are controlled by individual ‘chip select’ select lines to direct the data flow to/from the appropriate source, as required by the system control software.

5.3 5.3.1

Detailed cir cui t descrip tio n Introduction The Operator Logic Board circuit diagram (SE-4550005-F) comprises 4 sheets. With reference to the block diagram description, the drawi ngs can broadly be described as follows: •

Sheet 1 contains a ‘signal map’ identifying the functions covered on the remaining pages. It also contains a summary chart detailing the various configuration jumpers (X11 – X25). • Sheet 2 contains the switched-mode isolated power supply circuit. • Sheet 3 contains the – basic microcontroller system. – data bus, address bus and control bus buffers. – address decoding. – system RAM and ROM memory and its associated configuration links. – power-up reset generator. • Sheet 4 contains the – CAN bus communications drivers and control logic. – RS232 (modem) communications interface. – RS485 communications interface. – Operator Control Panel interface. As with all micro-based system, the microcontroller’s operation is determined by the program held in the system’s memory and, as this is hidden to the service engineer, there is very little that can be done to ascertain that the board is working correctly apart from checking the validity of its input and output signals, and other signals generated on the board which are required by the central processor system. The following description deals with the board on this basis, and should provide sufficient information to allow a troubleshooting engineer to determine whether or not the board is functioning correctly. A detailed software description is beyond the scope of this manual.

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5.3.2



Clock

20

Reset

27

+5V Vref

54

XTAL1

ALE

RSTIN

RSTOUT

VAREF

D2

Caution

RD WR

25


28

Reset Out

26

Read

95

Write

C o n t r o l B u s

When monitoring the signals described in this section it is best done with control power only – i.e. with the UPS power sections shut down and the circuit boards live via the control power supply. Some signals are irregular, or have very large mark:space ratios, and are best monitored with a logic probe. The logic sequence/timing of these signals depend upon various circuit conditions and cannot therefore be accurately defined; however, for f ield test purposes, the presence of a ‘variable switching’ logic signal at these points would generally indicate that the basic processor control bus is serviceable and the system software is running. Power supply

The microcontroller is powered from the isolated +5V rail which is provided by a switched-mode power supply circuit shown on diagram sheet 2 (See paragraph 5.3.12). System clock (XTAL1)

A dedicated crystal-controlled clock generator (E2) provides a system clock signal which is connected to the microcontroller pin 20. This signal is a 20MHz squarewave switching between +5V and 0V. System reset (RSTIN)

A one second logic low reset pulse, [RSTIN->, is applied to D42 pin 27 on powerup from the ‘reset generator’ circuit. This can also be manually applied for trou bleshooting purposes by bridging and un-bridging jumper X26. Reset out (RSTOUT) [RSTO-> is controlled by the reset input signal, [RSTIN->, and goes high while the

input rest signal is applied. This signal is synchronised to the system clock and returns high an integral number of clock pulses after the input reset signal is removed. The [RSTO-> signal is connected to the ‘address decoder’ circuit from where it resets the peripheral devices. That is, upon receipt of the “wake-up” request ( [RSTIN->) the microprocessor issues a “wake-up” call ( [RSTO->) to all the other relevant devices.

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Reference voltage (VAREF)

The input to D2 pin 54 ( VAREF) is a reference voltage used by the internal A/D converters; however, in this application the A/D circuits are not used and this input is connected directly to the general +5V supply rail. Address latch enable (ALE)

When the multiplexed Address/Data bus (port 0) c arries Address information this output goes ‘high’. This is used to control the address bus buffers as described below. Read (RD)

This output goes low when the processor wishes to read the data from the device or memory location currently addressed by the address bus. Write (WR)

This output goes low when the processor wishes to write data to the device or memory location currently addressed by the address bus

5.3.3

Data bus, address bus and con trol bus buf fers (circuit diagram sheet 3.) Overview

As described above, the microcontroller’s Port 0 acts as a multiplexed 16-bit Address/Data bus. When this bus carries Address information the [ALE> output goes ‘high’ to enable the address bus latches (D5 and D6) whose buffered outputs are then treated as a 16-bit address bus [AX0...AX15>. Conversely, when [ALE> is ‘low’ the bus information is interpreted as Data and connected to the peripheral devices via an 8-bit data bus latch (D7) in conjunction with the ‘read’ [RD-> control line. Address bus buffer

Two 74HCT573 devices serve as the address buffers (D5 & D6) – these are described in Appendix A (See appendix A.4). In this application the Output Enable pins are connected to a permanent logic low (0V) and the devices are therefore permanently enabled . The Address/Data bus contents are thus transferred to the buffers’ output when the Address Latch Enable [ALE> signal, connected to D5/D6 pin 11, goes high. The buffered address bus is annotated (AX0....AX15) and is shown connected to the ROM (D8) and RAM (D9) memory. It is also connected to the peripheral devices shown on the circuit diagram sheet 4. Data bus buffer

A type 74HCT245 octal bus transceiver (D7) is employed as bi-directional buffer between the microcontroller (D0....D7) and the data bus (DX0....DX7). The data direction through D7 is controlled by the microcontroller’s [RD-> output. Thus, when the microcontroller drives its [RD-> output low it sets the data direction from B to A through the buffers (See appendix A.1), which allows the data bus contents through to the microcontroller’s data inputs. At other times, when [RD-> is high, data flows through the buffers from A to B, allowing the micro to place data onto the data bus which can then be written to a peripheral circuit as required.

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Control bus buffer (diagram sheet 4)

Two 74HCT245 devices serve as the control bus buffers (D18 & D17). These are identical to the data bus buffer but have a fixed data direction (A-to-B) as pin 1 is permanently connected to +5V in each case. D17 interfaces the tactile switches (ENTER, UP, DOWN ) and the three mimic LEDs on the Operator Control Panel. D18 deals with the 6-segment bargraphs (%load & autonomy time) and the control bus [RD> and [WR-> signals. The buffered control signals [RDX-> and [WRX->, are used by various devices distributed throughout the circuit diagrams. In all cases the above mentioned buffers have pull-up resistors connected to t heir input and output pins to protect their internal logic – e.g. resistor packs R52 - R54.

5.3.4

Reset generat or (circuit diagram sheet 3.) A purpose-designed Supply Voltage Supervisor (N4) provides the micro with a one second logic low [RSTIN-> reset signal on power-up. This logic low pulse, which is applied to the micro pin 27, can also be initiated manually by ‘making’ jumper X26 (1-2). It also sends a logic high reset signal [RSTO-> to the ‘address decoding’ circuit (D10) from where it resets the peripheral devices via their ap propriate ‘chip select’ or ‘chip enable’ inputs (See paragraph 5.3.6). Note: the reset time is determined by R4/C1, and begins when the +5V supply rail reaches 3.6V on initial power-up.

5.3.5

Al arm bu zzer (circuit diagram sheet 3.) The alarm buzzer is driven by the processor’s port 3.0 output via driver transistor V11. Various alarm sound sequences are used to annunciate different types of alarm warning and responses. These are obtained by the processor producing various mark:space drive waveforms and are therefore strictly processor dependant. During troubleshooting the alarm sounder can be inhibited by fitting a jumper to X23 (1-2) which clamps the base of V11 to 0V and prevents it from turning on.

5.3.6

Add ress decodi ng – D10 (circuit diagram sheet 3.) The microcontroller communicates with • • • •

the system memory – RAM and ROM (D8 and D9). the Operator Control Panel – via connector X1. the UPS Logic Board – via D12 and the CAN Bus. the Serial Line Controller (D11) – which interfaces with the RS232 and RS485 communications facilities. Under the control of the micro, the ‘address decoding’ circuit (D10) produces individual ‘enable’ signals for each of the above mentioned devices which allows the micro to select a particular device with which it wishes to communicate at any point in time. D10 is a purpose-designed ASIC chip which decodes address lines AX11...AX17 together with the control bus [RD->, [WR-> and [RSTO-> lines, and from these inputs it provides the following controlled signals:

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•

[CSEPR-> – logic low selects the EPROM memory chip (D8).

•

[CSRAM-> – logic low selects the RAM memory chip (D9).

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• • • •

5.3.7


[CSCAN-> – logic low selects the CAN bus interface (D12 on sheet 4). [CSER-> – logic low selects the Serial Line Controller (D11 on sheet 4). [CSDISP-> – logic low selects the Operator Control Panel (X1 on sheet 4).

Buffered AX16 and AX17 address bus lines.

System RAM and ROM memory addressi ng (Refer to diagram sheet 3.) Figure 7-32: AX14 & AX15 decoding configuration links X14 [WRX-> [PIN31EP>

X19

1

1

2

2

3

3

[AX15>

X15

[PIN3EP>

X18

1

1

2

2

3

3

X16 [RDX-> [PIN29EP> [AX14>

+5V

[AX17>

[PIN3RAM>

X17

1

1

2

2

3

3

4

4

5

5

X12

[PIN3EP>

[PIN31RAM>

[PIN29RAM>

X13

3

3

2

2

1

1

D9 pin 28

The system memory comprises a 256k EPROM (D8) and 256k of RAM (D9). AX14 & AX15 configuration links

The Operator Logic Board has been designed to ease future software upgrades by including configuration links to permit the addressing of alternative memory devices. These links affect the routing of the AX15 and AX16 address lines, and the standard configuration is shown in Figure 7-32.

EPROM (D8) Configuration. In the standard configuration the signals annotated [PIN29EP> and [PIN3EP> are connected to EPROM D8’s A14 and A15 inputs and are therefore driven by the AX14 and AX15 address lines respectively. The [PIN31EP> input to D8 is concerned with selecting the “program” mode, and is left open circuit due to the lack of jumper on X14. [PIN30EP> is held at a permanent +5V (due to the jumper 2-3) on X12.

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Two conditions must be satisfied to connect the device’s D0....D7 outputs to the data bus. First, the EPROM’s ‘output enable’ pin (pin 24), which is controlled by the control bus [RDX->, must be low. Second, the ‘chip select’ (CS) input to pin 22, which is connected to the buffered [AX16> address line obtained from D10, must also be low. Note that [AX16> is not subject to the [ALE> signal switching through D5/D6 and is therefore permanently accessible by the processor.

RAM (D9) Configuration. In the standard configuration the signals annotated [PIN29RAM> and [PIN3RAM> are connected to the RAM’s A14 and A15 inputs. [PIN29RAM> is not used and is open-circuit due to the lack of jumper fitted to X17

pin 2. [PIN3RAM> is connected to the buffered Address line [AX14> due to the jumpers on X18 and X17 Once again, two conditions must be s atisfied to connect the device’s D0....D7 out puts to the data bus. First, the RAM’s ‘output enable’ pin (pin 22), which is controlled by the control bus [RDX->, must be low. Second, the ‘chip select’ (CS) input to pin 20, which is connected to the [CSRAM-> output from D10, must also be low.

5.3.8

Interface to the Operator Contro l Panel (circuit diagram sheet 4 – see also drawing SM-0360803-B sheets 2/3.) The Operator Control Panel is connected to X1 and its interface signals can be segregated into three areas; namely LED Driver; LCD Driver; and Push-button Detection – each of which is described below. LED Driver

Multiplexed power supplies. The operator control panel contains 17 leds arranged in three ‘banks’ – two banks of 6 led and one bank of 5 leds. The anodes of all the leds forming a particular bank are connected, via current limiting resistors, to a common +5V power supply; therefore three supplies are required in total. Referring to the diagram sheet 4, these supplies are obtained by three multiplexed signals ([LD7>, [LD8>, [LD9>) which are produced by the microcontroller and then buffered by D17 and transistors V12-V14 to provide [LC0>, [LC1>, [LC2>. These transistors are thus switched sequentially (i.e. “strobed”) to provide the positive power feed to each ‘bank’ of leds in turn.

LED Control. Each ‘bank’ of leds are controlled by a common control bus produced by the microcontroller annotated [LD1> to [LD6>. These signals are buffered by D18 and connected X1 as [LD0> to [LD5>. As the micro strobes the positive supply to each ‘bank’ of leds it drives its control bus lines ‘low’ to illuminate a particular led within the ‘bank’. By driving the leds in this manner the micro has full control over which leds are illuminated. Note: the positive supply is strobed at a rate of 83.3Hz and therefore the leds do not appear to flicker when illuminated. LCD Driver

The LCD Display device on the Operator Control Panel displays 4 lines of twenty characters and is used to indicate status information, alarm warning messages and also provides the messaging system used by the operator to select various operational parameters. The textual message information is stored in the Operator Logic Board’s ROM and output to the Operator Control Panel by the microcontroller, via the data bus

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[DX0> to [DX7>, at convenient intervals in a suitable form which can be interpreted

by LCD display device. As the microcontroller “sees” the LCD device as just another device on the data bus it must also provide a means of addressing it when required. This is achieved through a combination of the [CSDISP> ‘chip select’ signal from the address decoding circuit of D10 (See paragraph 5.3.6) and a ‘Write’ signal [RWDISP> produced directly by the processor port 1. To access the LCD display [CSDISP> must be taken ‘high’ and [RWDISP> ‘low’. Note: A reset signal [RSDISP> is also produced by the micro port 1 which can totally reset the LCD display device.

Other lines connected to the LCD device are concerned with its power s upply requirements. The device requires +5V at X1-32; 0V at X1-30 and X1-2; and a variable “contrast” supply in the range 0V to +5V at X1-4. Push-button Detection

The five push-button on the Operator Control Panel are connected to a common 0V supply presented to X1 pin 31 and, when pressed, they route this 0V back to: • X1 pin 21 (UP) • X1 pin 23 (DOWN) • X1 pin 25 (ENTER) • X1 pin 27 (ESCAPE) • X1 pin 29 (ALARM CANCEL) These signals, annotated [P-0> to [P-4>, are buffered by D17 and the resulting [TST1> to [TST5> signals are polled by the microcontroller at regular intervals to enable it to detect when a particular push-button is pressed.

5.3.9

Interface to the CAN Bus (circuit diagram sheet 4.) The Operator Logic Board uses the CAN bus to communicate with the UPS Logic Board. This bus carries bi-directional data between these two boards; e.g. operational status and alarm parameters are passed from the UPS Logic Board to the Operator Logic Board for processing and display on the Operator Control Panel. Selections made by the operator at the Operator Control Panel are passed via the Operator Logic Board to the UPS Logic Board to set the system operating parameters. The CAN bus (see appendix B) utilises an 82C200 controller and 82C250 interface chip, both of which are described in appendix A.

82C200 control signals. The CAN bus controller is connected to the microcontroller’s 8-bit data bus (DX0....DX7) in the same way as the other peripheral devices. The microcontroller must therefore provide a means of addressing it when required. This is achieved through a combination of the [CSCAN> ‘chip select’ signal from the address decoding circuit of D10 (See paragraph 5.3.6) and buffered read/write signals ([RDX-> and [WRX-> ). Note: an initialising reset signal [RSCAN> is also produced by the micro port 3 which starts communications.

82C250 control signals. This device is described in detail in appendix A (See appendix A.10). Jumper X24 should be made 1-2 to connect the 120 Ohm line termination resistor across its I/O line terminals. “High speed” mode is permanently selected due to pin 8 being grounded.

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5.3.10


Serial (mod em) Interf ace (circuit diagram sheet 4.) Serial (modem) communications is afforded by D11, which is a type 8521A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) working in conjunction with D13, which is a bi-directional line driver device type LT1133.

8521A operation. This device (D11) converts the parallel data into a serial data format for transmission, and vice-versa for data reception. This device is described in detail in appendix A (See appendix A.8). D11 is connected to the 8-bit data bus (DX0....DX7) and selected by a logic low [CSSER-> signal produced by the address decoding circuit. Read/Write control is afforded by the buffered [RDX-> and [WRX->, both of which are active ‘low’. The microcontroller port 3 provides the 8521 with its general clock signal, [CLKSER> at approximately 1.25MHz, and also a reset signal [RESSER> which is active ‘high’. The Data/Control input (D11 pin 12) is controlled by the buffered address line [AX0>, which is ‘high’ for data transfer and ‘low’ for control word transfer. The serial I/O data and control lines are interfaced to the modem port (X8) via the LT1133 driver circuit which converts the 8521A outputs to RS232C levels.

5.3.11

RS232 & RS485 Interf ace (Refer to diagram sheet 4.) Two of the controlled timers within the microcontroller (D2) are configured to operate as further communication interfaces. Data I/O transfer is processed via port 3 with one port annotated [TXD0> & [RXD0>, and the other [TXD1> & [RXD1>. These I/O data lines are raised to RS232 levels by D19 (MAX232) and RS485 levels by D20 (75176) – D20 is controlled by the [RE485-> & [OE485> outputs from port 1. RS232 communications via D19 and X5

The RS232 interface (D19) is provided by a standard MAX232 device (See ap pendix A.7) . This is a dual channel device: channel 1 interfaces [TXD0> & [RXD0> which is permanently connected to the RS232 I/O port at X5. Channel 2 interfaces [TXD1> & [RXD1> and is connected to X4 via jumpers X20 (1-2), X21 (2-3), X22 (2-3). This is the “standard” configuration for these jumpers. RS485 communications via D20 and X4

The RS485 interface (D20) is provided by a SN75176A differential bus transceiver (See appendix A.5). This is a single channel device which interfaces [TXD1> & [RXD1> only, via jumpers X20 (2-3), and is connected to X4 via jumpers X21 (1-2), X22 (1-2). When the jumpers are configured in the above positions they effectively route the RS485 communications through to X4 whilst still enabling RS232 communications at X5. The transmit data and receive data flow is controlled through D20 by means of the [RE485-> & [OE485> inputs to pins 2 and 3. A truth table showing the full affects of these inputs is provided in appendix A (See appendix A.5).

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5.3.12


Power Supp ly (circuit diagram sheet 1.) As many of the circuits on the Operator Logic Board are connected to external (possibly remote) devices, such as a modem, they are all powered from an i solated +5V power rail which is derived from an on-board dc-dc power converter based on a purpose-designed current-mode PWM controller (UC3845). This controller is fully described in appendix A (See appendix A.9). Power circuit operation

The dc-dc converter’s input power is obtained from the UPS Logic Board’s ±12V which is connected to X9 pins 1 and 3. This is filtered by C41 and L1/L2 to provide an unregulated power rail of approximately 24V; although the -12V rail is taken as the 0V reference by the control electronics. The converter operation is based on FET V10. When this device is turned ON it draws current through the transformer primary (1-10) which induces opposing currents into the secondary windings – note the winding polarities. In practice, V10 is driven by a variable PWM output from N1 (at a basic rate of 40kHz) and the net result is an alternating current induced in winding 5-6 which is full-wave rectified by V9 to provide a d.c. voltage smoothed by L3/C52/C53. This “smoothed” voltage is regulated at +5V by appropriately controlling V10’s PWM gate drive signal. PWM control operation

The PWM controller (N1) is powered from a 16V zener-regulated supply obtained from the unregulated 24V rail – note that N1 requires a minimum of 8.4Vdc to function correctly (See appendix A.9). The base PWM frequency is set to approximately 40kHz by R35/C44 (i.e. the PWM pulse repetition rate is ap proximately 25µs.).

Current feedback signal. A current feedback signal is obtained from R40 (0.33R) which is connected in series with the transformer primary current switched by V10. The voltage across this resistor will thus be proportional to the current drawn through the primary winding when V10 is turned on. This current feedback signal is fed to N1 pin 1 which internally regulates the mark-to-space ratio of the PWM output at pin 6 for load stepping and overloads.

Voltage feedback signal. A voltage feedback signal is obtained via an optocoupled circuit which monitors the voltage across the isolated +5V rail. N3 is a reference voltage generator which aims at maintaining 2.5V at its reference input (N3 pin 1 – i.e. at the junction of R47/R48). This means that it therefore attempts to maintain +5V at the top of R47 – which is connected directly to the output +5V rail. If the +5V rail therefore rises above or falls below its nominal +5V level then N3 will reduce/increase (respectively) the conduction through the opto-isolator, which is thus sensed by N1. The feedback voltage is source via the +5V r eference voltage produced by N1 at pin 8 and superimposed on the junction of R33 and R34 according to the amount of conduction of V21, as shown in Figure 7-33.

Indications. An led (H1 is connected across the isolated +5V rail and illuminates when this supply is correct.

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Figure 7-33: Voltage feedback signal N1 2

5V(ref)

8

R32

Output voltage sensing

V21

1

22k

3

R33 10k

4

VFB

7

VCC

VREF COMP

O/P

6

ISENSE RT/CT VCC

UC3842

5

R34 4k7

5.4

Summary inf orm ation Table 7-19: Operator Logic Board configuration jumpers

Jumper

Link Position

X11

OPEN CLOSED

X12

X13

X14

X15

X16

X17

X18

7-146

Function +5v enable main CPU (Standard) ALE enable main CPU

1-2

Main CPU enable EPROM

2-3

+5v enable EPROM (Standard)

1-2

Main CPU enable RAM

2-3

+5v enable RAM (Standard)

1-2

Not Required

2-3

Not Required

1-2

Main CPU enable EPROM (Standard)

2-3

Not Required

1-2

Not Required

2- 3

Main CPU enable EPROM (Standard)

3-4

Not Required

4-5

Not Required

1-2

Write to RAM enable

2-3

Not Required

3-4

Main CPU enable RAM (Standard)

4-5

Not Required

1-2

Not Required

2-3

Main CPU enable RAM (Standard)

Testing Only Open = Standard

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Jumper

Link Position

X19

1-2

Not Required

2-3

Not Required

1-2

Read/Write RS232 enable (Standard)

2-3

Read/Write RS485enable

1-2

Enable port x4 for RS485

2-3

Enable port x4 for RS232 (Standard)

1-2

Enable port x4 for RS485

2-3

Enable port x4 for RS232 (Standard)

1-2

Inhibit buzzer

2-3

Enable buzzer (Standard)

1-2

Enable CAN bus to UPS logic (Standard)

2-3

Disable CAN bus to UPS logic

1-2

Enable RS485 bus to port x4 (Standard)

2-3

Disable RS485 bus to port x4

X20

X21

X22

X23

X24

X25

X26

OPEN

Function RAM extension Normally open

+5v power supply reset enabled (Standard)

CLOSED

+5v power supply reset disabled

Table 7-20: Operator Logic Board potentiometer adjustment Potentiometer R21

Function Display contrast adjustment

Table 7-21: Operator Logic Board LED indication LED

Colour

H1

Green

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Function Internal power supply operating

7-147


7-148


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Section 7:

Chapter 6 - Operator Control Panel

6.1

Sectio n overvi ew This section contains a circuit description of the Operator Control Panel used across the entire 7200 Series UPS model range, and should be read in conjunction with circuit diagram SE-0360803-B. Signal annotations shown on the circuit diagrams are shown in italics in the following text – e.g. [CLC2>.

6.2 6.2.1

General descri pti on Circuit board functio ns The Operator Control Panel functions can be summarised as follows: • LED Display indication– This board contains LED which provides the operator with various status indications – i.e. UPS module mimic; load bargraph; battery charge/autonomy time bargraph; alarm warning indication. •

Operator input switches– The Operator Control Panel switches provide the means for the operator to effect system control through a menu/messaging system.

• LCD Display Panel– The LCD display panel provides status and alarm messages for the operator together with the menus used by the operator in setting up and interrogating the UPS control system.

6.2.2

Input/Outpu t con nectio ns All input/output signals are connected to the Operator Logic Board via a single 34-way ribbon connector.

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SECTION 7 - UPS System Control CHAPTER 6 - Operator Cont rol Panel

6.3 6.3.1


Detailed cir cui t descrip tio n LED Display ind icatio n Figure 7-34: LED Display indication LC0

X7-5

LC1

X7-3

LC2

X7-1

R3

R2

1 2 3 4 5 6 7 8 C R R R R R R R R

X7-7

LD4

X7-9

LD3

X7-11

LD2

X7-13

LD1

X7-15

LD0

X7-17

1 2 3 4 5 6 7 8 C R R R R R R R R

1 2 3 4 5 6 7 8 C R R R R R R R R

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

D17

D11

D5

D15

D16

LD5

R1

D13

D14

D12

D9

D10

D7

D8

D6

D3

D4

D1

D2

The operator control panel contains 17 leds arranged in three ‘banks’ as shown in Figure 7-34 – two banks of 6 led and one bank of 5 leds. • • •

LEDs 1-5 provide module mimic indication, alarm active and battery CB LEDs 6-11 provide the load bargraph indication and overload LEDs 12-17 provide the battery charge bargraph indication and autonomy

The anodes of all the leds forming each of the above ‘banks’ are connected, via current limiting resistors, to a +5V power supply. These +5V supplies are provided by three multiplexed signals ( [LC0>, [LC1>, [LC2>) which are provided by the Operator Logic Board – i.e. these supplies are “strobed” to provide the positive power feed to each ‘bank’ of leds in turn (See paragraph 5.3.8) . Each ‘bank’ of leds are controlled by a common control bus produced by the Operator Logic Board annotated [LD1> to [LD6>. As the positive supply is strobed to each ‘bank’ of leds, the leds illuminate according to which of the control bus lines are ‘low’. By driving the leds in this manner the microcontroller on the Operator Logic Board has full control over which individual leds are illuminated at any particular time. Note: the positive supply is strobed at a high frequency and therefore the leds do not appear to flicker when illuminated

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6.3.2

SECTION 7 - UPS System Control CHAPTER 6 - Operator Contr ol Panel

Operator inp ut swi tches Figure 7-35: Operator switches

0V

X7-31

S1

P4

X7-21

UP S2

P3

X7-23

DOWN S3

P2

X7-25

ENTER S4

P1

X7-27

ESCAPE S5

P0

X7-29

ALARM CANCEL

The five push-button on the Operator Control Panel are connected to a common 0V supply presented to X7 pin 31 from the Operator Logic Board; when pressed, they route a 0V signal (annotated [P-0> to [P-4>) back to the microcontroller on the Operator Logic Board via the connections shown in Figure 7-35.

6.3.3

LCD Disp lay Panel Figure 7-36: LCD Display module X7-14 X7-16 X7-18 X7-20 X7-22 X7-24 X7-26 X7-28 X7-4 X7-6 X7-2 X7-10 X7-8 X7-12 X7-32 X7-30

7 8 9 10 11 12 13 14 2 3 1 5 4 6 K A

D0 D1 D2 D3 D4 D5 D6 D7 VDD VL VSS R/WR RS E +5V 0V

4 x 20

LCD_MODULE

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SECTION 7 - UPS System Control CHAPTER 6 - Operator Cont rol Panel

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Chapter 7 - System software

7.1 Introduction The general UPS control operation is based on the microcontroller system contained on the UPS Logic Board, as described in chapter 3 of t his section (see paragraph 3.3.2 on page 7-24). The following description explains in basic terms how the microcontroller system is programmed to operate and provides details of the conditional flowcharts applicable to the major UPS control signals (e.g. rectifier OFF/ON, inverter OFF/ON, load transfer control). Despite the fact that the software is not generally accessible to the service engineer, an understanding of some of the sub-routines described later can be an invaluable troubleshooting aid to differentiate between the ‘cause and effects’ of certain conditions. The “C” programming language used to write the system software is closely related to the actual digital processing, and comprises a sequence of instructions which determines the microcontroller operation. The program is held in two 512k Read-Only Memory chips (EEPROM) D35 & D46 which are accessed by the microcontroller via the system address and data busses. D20 is also a ROM device, and contains initialisation data. Although it does not contain the “system software” itself, the Random Access Memory (RAM) holds important data concerning the system’s operation, such as that programmed by the operator from the Operator Control Panel, which is required by the main program. Battery back-up is provided to maintain such data when the UPS is powered down. RAM also provides a temporary store for data produced by the main program during its routine execution.

7.2 Program str uct ure and executi on Initialisation

When the UPS is first powered up the microcontroller receives a 1 second reset pulse from the reset generator (see paragraph 3.3.5 on page 7-27) which forces the micro to read the instruction contained in a particular memory location (usually 0000). This is the start point of an initialisation routine which sets up the com plete microcontroller system in readiness for entry into the main program. The initialisation routine performs functions such as configuring the microcontroller I/O ports, peripheral communication ports and protocols, internal timers and A/D converters; and reading system data (such as UPS module rating and configuration) from the non-volatile RAM. Some of these functions are performed once only during the initial set-up whilst others are also revisited during the main program execution – e.g. if the module kVA rating or single/parallel configuration data is changed whilst the module is running it will not affect the main program until the microcontroller is reset. Note: the reset generator can also be triggered manually through the selection of jumper X28; however, if a reset is applied whilst the UPS is running it will crash due to the rectifier, inverter and static switch all being turned off during the reset period. USE WITH CAUTION!

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SECTION 7 - UPS System Control CHAPTER 7 - System sof tware


Main program

The system software will enter its main program once the initialisation routines have been completed. The main program comprises a series of instructions which are executed sequentially in a continuous loop (See Figure 7-37). Figure 7-37 shows that the main program operates on two levels; identified in the illustration as the ‘foreground’ and ‘background’ routines. Notice that both the ‘foreground’ and ‘background’ routines call various ‘sub-routines’ whilst working through the main program loop. A sub-routine is a self-contained “mini-program” that can be called from various points in the main program loop. The ‘foreground’ routine services vital functions which are required to be performed at regular intervals, or at a particular time, in order to secure proper system control: while the ‘background’ routine is of secondary importance and executed on an opportunity basis when the ‘foreground’ routine is idle. For example, the sub-routine that checks that the inverter output voltage is within limits is considered ‘critical’ and is called every 250µs; while the sub-routine that checks the state of the inverter ON/OFF menu selection is less-critical and perhaps executed once per second. All program timing functions are tied to the microcontroller system clock (20MHz), which also synchronises the address/data bus transfer operations, and the microcontroller’s internal programmable timers. A successful ‘real-time’ program requires that the main program loop is completed as fast as possible and it is therefore good practice to return to the main program from a sub-routine as quickly as possible. ‘Background routine’

The background routine is responsible for managing the calculation of the voltage and current signals produced by the A/D converters and storing the results in the appropriate RAM memory locations from where they are read at regular intervals by the foreground routine. It also reads the condition of the Operator Control Panel buttons and sets status flags in the RAM memory. ‘Foreground routine’

The foreground routine calls a series of sub-routines to carry out a check of the many variables and status flags held in memory and perform various functions de pending on the results – i.e. the sub-routines make decisions based on the state of the memory contents that they read. For example: a sub-routine that controls the state of the [REC_ON> signal is called every 500msecs. This signal determines whether or not the rectifier is requested to turn ON (see page 7-33) and in making the decision, the sub-routine looks at the following status flags stored in memory:

•

the manual ‘rectifier inhibit’ switch status (UPS Logic Board).

•

the rectifier fuse fail status.

•

the selected rectifier ON/OFF status (from Operator Control Panel menu screen). If all three of the above conditions are conducive to starting the rectifier, the software will drive the [REC_ON> signal high which turns on the rectifier, and also sends a status signal via the CAN bus to inform the display system of the new rectifier status. Several other sub-routines which control similar signals to [REC_ON> , and are therefore of prime interest to the service engineer, are illustrated in detail later in this chapter.

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SECTION 7 - UPS System Control CHAPTER 7 - Syst em softwar e

Figure 7-37: Main program “Foreground” and “Background” routines

SUB: Look-up A/D input (Vb)

START

Clock

Calculate Vb

Set Initial flags

Calculate Vinv

If clock=0001 Exec SUB: INV-ON

SUB: INV-ON See Flow-chart 1

If clock=0010 Exec SUB: REC_ON

SUB: REC-ON See Flow-chart 2

If clock=0150 Exec SUB: SYNC_OK

SUB: SYNC_OK See Flow-chart 3

If clock=0200 Exec SUB: IB_OPEN

SUB: IB_OPEN See Flow-chart 4

B a c k g r o u n d R o u t i n e

Calculate Ib : : :

Running in background

CPU

START

Set Flags Check Display Buttons

e n i t u o R d n u o r g e r o F

: : :

: : : If clock=nnnn Execute SUB: nnnn

Return to START

: Return to START

Page 1 Vb=432

Ib

:

Inv. Volts Window

flag_1 REC_ON

Vout

:

:

Low Batt Warning

flag_2 INV_ON

:

Vinv

:

:

DC Over voltage

flag_3

:

Vin

:

:

In. Volts Window

flag_4

:

:

:

:

Start

s e n i t u o R d n u o r g k c a B

Start

Execute Chk1 if t=0.5µs

CHK Vb

Execute Chk2 if t=100µs

CHK Vin

..........

..........

..........

.......... .......... ..........

..........

e m m a r g o r P n i a M

:

Page 2

RAM MEMORY

:

Sub-Routin e 1

Sub-Routin e 2

Begin SUB:

.......... Question 1?

No

Process A

.......... .......... Yes

Question 2

..........

..........

..........

..........

..........

End (Return to start)

..........

Process B Process C

End (Return to start)

No Process D

End SUB:

Question a condition (e.g. Is Vb < undervoltage trip level)

Perform a function (e.g. Set BatU/V Flag - Trip battery etc.)

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7.2.1 Initialisation/Reset The system reset routine is activated w hen the UPS is first powered up or following the application of the hardware reset (see paragraph 3.3.5 on page 7-27). Note: the reset pulse is applied for approximately 10/20ms in order to allow the +5V power rail to stabilise. The Initialise/Reset routine: •

resets the micro’s peripheral devices by forcing the output digital signals to logic low (with the exception of the [SYNC>, [PWM1>, [PWM2>, [PLLOU1> signals, whose states remain undefined).

•

verifies no-reversal of the output digital connectors.

•

initialises the software application into the working RAM

•

starts the ‘watch-dog’ timer

•

verifies that the EEPROM holds valid system parameters (See Chart 7-1).

•

checks the nominal sync frequency

•

checks the visual display and 7-segment led (for 5 seconds)

•

returns a Pass/Fail status.

Checking the system parameter data

The initialisation/reset routine checks that the programmed system parameters are acceptable for the correct operation of the UPS equipment. The parameters are held in three pages of the EEPROM. Page 1 holds the parameters set by the Operator Control Panel and pages 2 & 3 contain the internal parameters. A Longitudinal Redundancy Counter (LRC) is associated with each page to allow error checking. Default values for the system parameters are held in fixed memory addresses in the system EPROMS. The EEPROMs’ data can thus be reinitialised with the EPROM default values by following the “RELOAD DATA” procedure on the Operator Control Panel (see paragraph 2.4.7.5 on page 2-46). This should be carried out if an LRC error is found with the page associated with the O perator Panel entered data.

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Flow Chart 7-1: Initialisation/Reset

Begin SUB: [RESET>

Does memory page 2 initialse correctly?

No

Failed LRC P2 set error 72 [ERROR LRC PAR PAG 2]

No


No


No

set error 70 [BAD EEPROM PROGRAMM]

Yes


Yes


Yes

Does UPS Power rating parameter exist?

Yes

Is link X12 made 1-2?

Yes

No

Initialisation passed

Initialisation failed

End SUB

Return to main program

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7.2.2 Rectifier ON/OFF subr outi ne This subroutine enables the software to control the rectifier ON/OFF function. The sub-routine is affected by the following inputs:

•

Rectifier fuse-fail monitor ([FUSREC>) – connected to X2 pin 49 from the fuse’s fault detection micro-switch. A fuse failure event activates alarm #25.

•

‘Rectifier Block’ (BLK_RAD>) – derived from the fault detection logic on the Rectifier Logic Board which shuts down the rectifier if that board detects an internal fault (applied to X3 pin 33).

•

Operator Control Panel ON/OFF selection ([TLC_REC>) – Applied via the CAN Bus from the Operator Logic Board. An OFF status event activates alarm #21.

The sub-routine produces the following output:

•

7-158

Rectifier ON/OFF command signal [REC_ON> – connected as an input to D88 where it affects the logic state of the ultimate rectifier control signal [ON_REC> (see paragraph 3.3.7 on page 7-29). This signal is applied via the CAN Bus from the Operator Logic Board and activates alarm #20 [ RECT: SOFTWARE BLOCK] when in its OFF status.

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Flow Chart 7-2: Rectifier RUN control [REC_ON>

Begin SUB: [REC_ON> (every 500ms)

Is the Rectifier Block signal active on the Rectifier Logic Board?

Yes

No

Is the Rectifier Fuse Fail active?

Yes

No

Is the Rectifier selected ON at the Operator Control Panel?

No

Yes Set [REC_ON> output to ON (Logic high) [Turn OFF Alarm #20]

Set [REC_ON> output to OFF (Logic Low) [Turn ON alarm #20]

End SUB (return to main prog.)

REC_ON EPO PS FAIL

D88

[ON_REC>

To Rectifier Logic Board

Man Inhibit (Q3) DC O/volts

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7.2.3 Invert er OFF/ON Sub-ro uti ne This subroutine enables the software to control the inverter ON/OFF function The sub-routine is affected by the following inputs:

•

Battery voltage validation ([ST_BAT>) – as determined by the battery voltage monitor sub-routine (See Chart 7-7).

•

Inverter block (BLK_INV>) – derived from the fault detection logic on the Inverter Logic Board which shuts down the inverter if that board detects an internal fault (applied to X3 pin 33).

•

Output Isolator status ([SW_OUT>) – connected to X2 pin 46 from Isolator’s auxiliary contact. When open, it initiates alarm #03.

•

Maintenance Bypass Isolator status ([SW_BYP>) – connected to X2 pin 45 from Isolator’s auxiliary contact. When Closed, it initiates alarm #06.

•

External ‘Inverter Block’ command ([BLK_EXT>) – connected to X8 pin 11 and applied via the optional Alarms Interface Board.

•

Operator Control Panel ON/OFF selection ([TLC_INV>) – applied from the Operator Logic Board via the CAN bus. When OFF, it initiates alarm #31.

•

Load status ([ST_CA>) – signifies load on inverter/bypass/open as determined by the load transfer control sub-routine (See Figure 7-39).

The sub-routine produces the following output:

•

7-160

Inverter ON/OFF command signal [INV_ON> – connected as an input to D88 where it affects the logic state of the ultimate inverter control signal [ON_INV> (see paragraph 3.3.7 on page 7-29). This signal is applied via the CAN Bus from the Operator Logic Board and activates alarm #30 [ INV: SOFTWARE BLOCK] when in its OFF status.

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Flow Chart 7-3: Inverter RUN control [INV_ON> Begin SUB: [INV_ON> (every 500ms)

Is the battery voltage within permissible range?

Yes

Is the Inverter Block signal active on the Inverter Logic Board?

No

Yes

No

Is an External Block being applied?

Yes

No

Are the Output Isolator and Maint. Isolator closed together?

Yes

No

Is the Inverter selected ON at the Operator Control Panel?

No

Yes

Set [INV_ON> output to ON (Logic high) [Remove alarm #30]

Set [INV_ON> output to OFF (Logic low) [Activate alarm #30]

End SUB (return to main prog.)

INV_ON EPO PS FAIL Man Inhibit (Q2)

D88

[ON_INV>

To Inverter Logic Board

DC O/volts

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7.2.4 Frequency synchroni sation control The Inverter synchronisation control is complex and, for the purpose of this description, is divided into three flow charts. Figure 7-38: Frequency synchronisation software block diagram [FOK> (alarm #13) [PLL>

Window Limits [F_IN>

Mains OK Routine

[SVI>

[BLK_SYN> External Sync Inhibit

Sync Source Selector

Sync Source

PLL Calculate Phase Displacement

Error

PLL Slew Rate Control

[SYNC>

[BACK> Inverter Freq F/Back

[SYNC_OK> (alarm #35)

“Mains OK” routine. This routine is responsible for verifying t hat the bypass supply is fully available and the bypass frequency is within the selected voltage and frequency window limits. The major output from this routine is monitored by the Sync Source Selector routine which determines whether the inverter is to: 1. Synchronise to the bypass supply (if the bypass is valid). 2. Synchronise to the last available valid frequency – i.e. if the frequency goes outside the sync-window the selected frequency will remain at the window edge frequency for 1 minute (debounce) then revert to the internally generated base frequency reference clock (50/60Hz). Note: when the bypass frequency returns to within the window the PLL will revert to synchronising to the bypass after 1 second. 3. Synchronise to the internal reference clock if the bypass supply disappears. The sub-routine is affected by the following inputs:

7-162

•

Bypass R-phase frequency ([F-IN>) – Manufactured from X2 pin 15 via the High Voltage Interface Board.

•

Nominal frequency (50/60Hz) – Selected via the Operator Control Panel and applied via the CAN bus.

•

Acceptable sync window (±1Hz) – Programmed via the Operator Control Panel through the “set-up” menu, and applied via the CAN bus.

•

Bypass voltage status (SVI) – This flag is set by another subroutine depending on the bypass voltage status – i.e: 0 = OK (bypass voltage within the mimic-programmed limits [±10%]) 1 = LOW (bypass undervoltage [below -10%]) alarm #12 active. 2 = HIGH (bypass voltage high [above +10%]) alarm #11 active. 3 = ABSENT (bypass voltage less than 50V) alarm #10 active.

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The sub-routine affects the following outputs:

•

Frequency status flag ([FOK>) – OFF = FAULT ON = OK.

Disables/enables alarm #13 •

PLL enable flag – Enables/disabled frequency slew-rate control (See Chart 7-5)

•

Reference frequency status ([Sync Source>) – Selects the frequency value to which the PLL will lock – i.e. to the “Last frequency” or “internal clock.”

.

Flow Chart 7-4: “ Mains OK” Routine Begin SUB: Frequency Calculation

Is the bypass voltage present? (SVI = Not 3)

Yes

No

No

Is the bypass frequency within the selected window? (±1Hz)

Yes

Has the 1Sec stability timer expired?

No

Yes

Has the 1Sec stability timer expired?

Sync Source = PREVIOUS (2) frequency (Use last available frequency as reference)

Yes

Set FOK = OFF (bypass frequency is not OK) Annunciate a larm #13 [BYP: FREQUENCY ERROR] Reset delay counter = 0

Set FOK = ON (bypass frequency is OK) Set PLL> flag = ON Enable the PLL slew rate control Sync Source = MAINS (1)

Start the "re-enable" timer (1minute) Set [PLL> flag = OFF Disable the PLL slew-ratre control Increment the 1 sec "PLL re-enable" counter No

Yes

Has the "1 min re-enable" counter timed-out?

Sync Source = BASE FREQ (3)

No

End SUB: Return to main program

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Sync Source Selector. This subroutine enables the software to control the PLL frequency selection (see paragraph 3.3.13 on page 7-55). The sub-routine is affected by the following inputs:

•

External sync inhibit ([BLK-SYN>) – connected to X8 pin 12 from External Alarms Interface option.

•

External sync inhibit ([ON_GEN>) – One of the functions of the “On-Generator” i nput is to disable the inverter synchronisation (selected via the Operator control Panel SET-UP menu).

•

Permission to enable sync inhibit operation ([GREL_BLK_SINC>) – this is a programmable parameter (see paragraph 2.4.7.3 on page 2-43).

•

PLL Phase Locked ([PLL_ON>) – A software routine which determines if the inverter and bypass are within ±9° of each other. PLL_ON = within ±9° of each other PLL_OFF = not within ±9° of each other

•

Timeout value for bypass frequency monitor ([FOK>) – this is a programmable parameter associated with the timeout of the “Bypass Frequency Not OK” status.

The sub-routine produces the following outputs:

7-164

•

Sync Source – master frequency reference to the phase displacement calculation routine.

•

PLL locked ([SYNC_OK> ) Enables/Disables alarm #35

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Flow Chart 7-5: Sync Source Selector Routine Begin SUB: PLL Sync

Is the external block facility enabled (ON_GEN) & (GREL_BLK_SINC)

No

Is an external Block synch inhibit signal being applied (BLK_SYN)?

Yes

Is the mains frequency within the selected window? (FOK=ON)?

No

Yes

From Mains frequency validation chart

No Sync Source = Present PLL held to present frequency Yes

Has the mains been out of limits for > 10Secs?

No

Is the PLL phase locked within ±9°? (PPL Flag=ON)

No

No Has the PLL been locked for at least 1 Sec?

Sync Source = BASE FREQ PLL locked to internal clock 50/60Hz frequency

Sync Source = PREVIOUS PLL held to previous frequency

SYNC_OK = OFF

Yes

SYNC_OK = OFF Active alarm 35 [INV: UNSYNCHRONIZED]

No

Active alarm 35 [INV: UNSYNCHRONIZED]

SYNC_OK = ON

De-active alarm 35 [INV: UNSYNCHRONIZED]


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Phase displacement calculation. This routine controls the rate of change of the inverter frequency in order to track the bypass supply frequency. The “target” slew rate is programmable via the Operator Control Panel – i.e. the amount of dis placement error is multiplied the gain factor entered under the “Speed” menu on the Operator Control Panel. The sub-routine is affected by the following inputs:

•

Sync Source – The is the master frequency reference as selected by the Sync Source Selector and Mains OK routines. This reference may be:

a) Present frequency – Holds the inverter frequency constant at the present value when an external inhibit is applied (e.g. via the optional Alarm Board). b) Previous frequency – If the mains frequency goes outside its window limits, this holds the inverter frequency constant at the last valid mains frequency (e.g. at the window edge frequency). c) Base frequency– Reverts the inverter back to the Bas e Frequency if no mains reference frequency is available. d) Mains frequency – Forces the inverter to track the bypass frequency as long as it remains available and within the window limits. •

Inverter Frequency [BACK> – Actual inverter frequency as presented to the Inverter Logic Board.

The sub-routine produces the following outputs:

7-166

•

Inverter Sync ([SYNC>) – Master frequency reference to the Inverter Logic Board.

•

Error – A phase displacement is calculated depending on the relationship between the two inputs (Sync Source & [BACK>). The detected error is then multi plied by a programmed “gain” parameter, which is entered via the “Speed” display menu. This either speeds-up or slows-down the inverter clock (nominal 288kHz) on the Inverter Logic Board in order to make the inverter track the “Sync source” reference frequency. The “Gain” figure obviously affects the rate at which the inverter frequency is allowed to change while undertaking its tracking function, and is put into effect in the PLL Slew Rate Control Routine.

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Flow Chart 7-6: PLL Slew rate control (phase displacement calculation). Begin SUB: PLL Phase Detector

Calculate phase displacement between inverter [BACK> and [Sync Source]

Is the error greater than ±9°?

No

No

Is the "Out-of-phase" flag ON?

Yes

Yes

Calculate phase displacement between inverter [BACK> and [Sync Source]

Is the error greater than ±8°?

No

Set "Out-of-phase" flag = ON

Set "Out-of-phase" flag = OFF

Yes

Calculate phase error direction (lead/lag)

Calculate phase error direction (lead/lag)

Calculated error w.r.t. slew rate gain (set via "Speed")

Calculated error w.r.t. slew rate gain (set via "Speed")

Add calculated "error" to inverter clock. (Slew-rate control routine)

Add calculated "error" to inverter clock. (Slew-rate control routine)

Set "Out-of-phase" flag = OFF

Set "Out-of-phase" flag = ON


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7.2.5 Battery circ uit breaker cont rol This subroutine enables software control of the battery circuit breaker via the [IB_OPEN> signal applied to U23 (see paragraph 3.3.7 on page 7-29). This subroutine reacts to changes in the battery st atus flag ( ST_BAT ) which indicates whether the battery voltage is above the ‘slow overvoltage’ level, below the ‘undervoltage trip’ level, or positioned satisfactorily between the two. Changes in status affect the state of [IB_OPEN> after a suitable debounce period, which is ap plied to prevent spurious operation. The debounce period of all three status changes are factory programmed independently. The sub-routine is affected by the following inputs:

•

Battery voltage ( [VB>) – connected to X2 pin 27 via High Voltage Interface board

•

Battery maximum threshold ([Vs_sup_bat>) – programmed via the Display menu system.

•

Battery undervoltage trip threshold ([Vs_inf_bat>) – software calculated depending on discharge current (Ib) and programmed via the Display menu system.

•

Rectifier in Manual Mode status – command input from Operator Control Panel.

•

Battery Test Mode status – enabled & programmed from Operator Control Panel.

•

Battery Boost Charge Mode status – enabled & programmed via the Display menu system

•

On-Generator status – when enabled (from Operator Panel) reduces the battery charge when the UPS is running On-Generator (see paragraph 2.4.7.3 on page 2-43) – requires Alarm Interface Board input.


•

Battery status flag ([ST_BAT>) – depending on the measured battery voltage, [ST_BAT> can have one of three possible values; – [ST_BAT> = BAT_BAS (battery undervoltage alarm [53]) – [ST_BAT> = BAT_ALT (battery overvoltage alarm [55]) – [ST_BAT> = BAT_OK (battery voltage within acceptable range).

•

7-168

Battery circuit breaker control ([IB_OPEN>) – connected as an input to D88 where it affects the logic state of the ultimate Battery Trip signal [BAT_TRP> (see paragraph 3.3.7 on page 7-29) – logic high trips the battery breaker and low ‘enables’ it.

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Flow Chart 7-7: Battery Control Begin SUB: Battery circuit breaker control

Is the battery voltage (VB) below the set low volts level? (Vs_inf_bat)

(Executed every 500ms)

No

To Next Page

(See Chart 7-9)

Yes

Yes

Is ST_BAT already flagging an undervolts trip status? (BAT_BAS)

No

No

Has the Low DC condition been present for longer than 1Sec?

Yes Set ST_BAT to BAT_BAS to flag Low Voltage Trip -activate alarm [53] Set IB_OPEN high to open the battery circuit breaker

HIGH End SUB: Return to main program [IB_OPEN> M_BAT_MA RESET

D88

BAT_TRIP

M_ESD

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Flow Chart 7-7: Continued...... From Previous Page

Is the battery voltage above the set slow overvolts level? (Vs_sup_bat)

No

To Next Page

Yes

Yes

Is ST_BAT already flagging a slow overvoltage status? (BAT_ALT)

Yes

No

Is the battery in TEST; MANUAL or BOOST mode?

No

Yes

Is the ON GENERATOR block applied?

No

No

Has the Low DC condition been present for longer than 1Sec?

Yes Set ST_BAT to BAT_ALT to flag High Voltage Trip -activate alarm [55] Set IB_OPEN high to open the battery circuit breaker

HIGH End SUB: Return to main program [IB_OPEN> M_BAT_MA RESET

D88

BAT_TRIP

M_ESD

7-170

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Flow Chart 7-7: Continued...... From Previous Page

No

Is ST_BAT already flagging an OK status? (BAT_OK)

Yes

No

No

Has the DC Bus been stable for longer than 5 secs?

Yes Set ST_BAT to BAT_OK to flag Battery OK - for Alarm Interface board Set IB_OPEN low to enable the battery circuit breaker

LOW

[IB_OPEN> M_BAT_MA RESET

D88

BAT_TRIP

M_ESD End SUB: Return to main program

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7.2.6 Lo w Batt ery Pre-alarm This sub-routine controls the annunciation of the [DC BUS: UNDERVOLTAGE] warning (alarm # 56) when the battery voltage falls to a value just above the undervoltage trip voltage. A delay counter provides a 1 second delay between a change in alarm status and the alarm indication to prevent spurious operation. The sub-routine is affected by the following inputs:

•

Battery voltage ( [VB>) – connected to X2 pin 27 via the High Voltage Interface board.

•

Battery Pre-alarm operating threshold ([Vs_pre_al_bat>) – programmed via the Operator Logic board and applied via the CAN bus.


•

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Battery Pre-alarm status flag ([sta_pre_bat>) – enables/disables [ DC BUS UNDERVOLTAGE ] alarm [#56].

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Flow Chart 7-8: Low battery pre-alarm

Begin SUB: Battery Low Voltage Pre-Alarm

No

Is alarm #56 [DC BUS: UNDERVOLTAGE] active at present?

Is the battery voltage (VB) below the pre-alarm volts level?

No

Yes

Yes

Has VB been above pre-alarm level for longer than 1Sec?


Yes

Is alarm #56 [DC BUS: UNDERVOLTAGE] active at present?

No

No

No

Has VB been below pre-alarm level for longer than 1Sec?

Yes

Yes

Remove alarm #56 [DC BUS: UNDERVOLTAGE]

Display alarm #56 [DC BUS: UNDERVOLTAGE]


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7.2.7 Battery und ervoltage trip thr eshold This sub-routine calculates the battery undervoltage trip (End-of Discharge) reference level ( [Vs_inf_bat>) used in the battery circuit breaker control sub-routine (See Chart 7-7). The operating threshold value depends on the percentage battery current being drawn; basically, the undervoltage trip voltage is raised by 10% if the battery discharge current is less than 10% of its fully-rated current. This is to prevent the battery from undergoing a prolonged low-level discharge and thus enhances the overall battery performance and working life. The sub-routine is affected by the following inputs:

•

Battery current ([IB>) – from X2 pin 31 via the High Voltage Interface board.

•

Battery circuit breaker status ([SW_BAT>) – from X2 pin 53 via the High Voltage Interface board.

•

Number of battery elements – entered via Operator Control Panel and applied via the CAN bus.

•

Nominal ‘End-of-discharge’ voltage (V/Cell) – entered via Operator Control Panel and applied via the CAN bus.

•

Background task results – 2 flags are set in RAM by a background sub-routine, calculated as follows: NOMINAL = N. BATT. EL x END DIS. 110% NOMINAL = NOMINAL + 10% N. BATT. EL. = Number of battery cells connected in the string, as entered

via the “SET UP” Display menu. END DIS. = Minimum discharge voltage per battery cell, also entered via the “SET UP” Display menu. Example: if 198 cells & end of discharge = 1.67V/Cell then: NOMINAL = 330.6V and 110 NOMINAL = 363.76V The sub-routine affects the following outputs:

•

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Battery undervoltage trip reference ([Vs_inf_bat>) – (See Chart 7-7)

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Flow Chart 7-9: Battery undervoltage trip th reshold

Begin SUB: Battery undervoltage threshold selection


Is the battery circuit breaker open?

No

Yes

Is the battery current less than 10% ?

No

Yes Use the upper level

Use the lower level

Vs_inf_bat = 110% NOMINAL

Vs_inf_bat = NOMINAL


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7.2.8 Battery Boo st charge This sub-routine determines when the Rectifier Logic Board is requested to operate in the Boost Charge mode (see paragraph 2.3.2 on page 4-26). Boost charge is enabled from the Operator Control Panel and can be invoked Manually or Automatically. •

Manual selection puts the charger in an immediate Boost mode.

•

Automatic Boost mode is invoked if the charge current is greater than a programmed threshold level for 1 minute following the return of the mains supply after an outage. The system remains in the boost mode until either the battery current falls below the threshold for 5 seconds, or the boost charge timer (up to ten hours) expires (in which case an error is flagged – alarm #54 – and further Boost charge operation is locked out.

The sub-routine is affected by the following inputs:

•

Battery current ([IB>) – from X2 pin 31 via the High Voltage Interface board.

•

Automatic Boost charge enable/inhibit – selected from Operator Control Panel and applied via the CAN bus.

•

Manual Boost charge requested– selected from Operator Control Panel and applied via the CAN bus.

•

Battery in Test mode – flag set by another sub-routine (See Chart 7-11).

•

Rectifier in Manual mode – flag set by another sub-routine.

•

On-Generator mode – flag set by another sub-routine.

•

Automatic changeover threshold – programmable from Operator Control Panel (default = 10% of battery current limit threshold) and applied via the CAN bus.

•

1 minute timer – to determine when to enter Auto Boost Mode – factory default setting.

•

5 second timer – to determine when to exit Auto Boost under normal conditions (i.e. battery regains its charge) – factory default setting.

•

Boost Mode timer (to 10 hours) – to determine when to exit Boost Mode under fault conditions (i.e. battery fails to regain its charge and charge current remains high). Programmable from Operator Control Panel and applied via the CAN bus.


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•

Charge Mode selection signals ([REC_A> and [REC_B>) – selects charge mode on Rectifier Logic Board.

•

Boost charge status flag – signalling boost active/inactive/timeout

•

Alarm #54 driver [BOOST: TIME EXPIRED] signalling boost charger timer expired.

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Flow Chart 7-10: Battery Boost

Begin SUB: Boost charge

Is BATTERY TEST request active?


Is rectifier in MANUAL mode?

No

Yes

No

Is an ON GENERATOR condition active?

Yes

Yes

Is the Automatic BOOST function enabled?

No Reset "Batt-in-BOOST" flag to OFF (i.e. Stop Boost charge even if it is already in progress)

Has BOOST mode been manually selected?

No

Yes

Yes

Is the battery current > 10% of the rated Batt. current limit?

No

No

Is alarm #54 already active (latched) [BOOST: TIMER EXPIRED]?

Yes Increment 1 minute delay timer No

Has delay timer reached its terminal count (1min)?

No

Request "BOOST Charge Mode" to Rectifier Logic Bd (REC_A=0 / REC_B=1) Yes

Set the "Battery In Boost Charge" flag = ON. Start BOOST charge timer

Increment 5 second timer

No

Is the battery current > 10% of the rated current limit?

No

Yes

Has timer reached its terminal count (5 sec)?

Yes

Request "FLOAT Charge Mode" to Rectifier Logic Bd (REC_A=1 / REC_B=0)

Increment BOOST Charge timer

Request "FLOAT Charge Mode" to Rectifier Logic Bd (REC_A=1 / REC_B=0) Activate alarm #54 (latched) [BOOST: TIME EXPIRED]

Yes

Has BOOST charge timer reached its terminal count (10Hrs max)?

Reset 5 second timer

Reset 5 second timer No End SUB: Return to main program

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7.2.9 Batt ery Test A “Battery Test” routine is enabled from the Operator Control Panel and can be invoked Manually or Automatically at a set date and time (see paragraph 2.4.7.2 on page 2-42). When the TEST is invoked the rectifier is turned off and the batteries are discharged for a predefined period (nominally 5 minutes). A check is made during the TEST period to ensure that the battery voltage does not fall below a predefined minimum value (nominally 1.9V/Cell). If the battery fails this check an alarm is annunciated and the rectifier i s turned back on to take over the supply to the inverter. The battery test subroutine handles the management of the Test process. The sub-routine is affected by the following inputs:

•

Battery voltage ( [VB>) – connected to X2 pin 27 via High Voltage Interface BOard

•

Automatic Test date/time start details – programmed via the Operator Control Panel and applied via the CAN bus.

•

Final test voltage threshold (1.9V/cell) – programmed via the Operator Control Panel and applied via the CAN bus.

•

End-of-test (FAIL) debounce delay(1.5s) – factory-fixed delay time to prevent spurious detections

•

Automatic Test duration period – programmed via the Operator Control Panel and applied via the CAN bus.

•

Battery Test request (manual) – programmed via the Operator Control Panel and applied via the CAN bus.

•

Battery Test request (auto) – programmed via the Operator Control Panel and applied via the CAN bus.

•

‘Rectifier in Manual’ status flag ([st_rad_man>) – flag set by another sub-routine.

•

‘On Generator’ status flag ([st_grel_blk_car>) – flag set by another sub-routine.


•

Charge Mode selection signals ([REC_A> and [REC_B>) – selects charge mode on the Rectifier Logic Board (see paragraph 2.3.2 on page 4-26) .

•

State of test result on exit ([TST_BAT>) – OFF = OK and ON = FAIL. enables alarm #51 driver [BATTERY: TEST FAILED]

•

‘Battery in test’ mode status flag ([abil_tst_bat>) – ON = Test in progress enables alarm #50 driver [BATTERY: UNDER TEST ]

•

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Flow Chart 7-11: Battery Test Begin SUB: Battery TEST (Initialisation request)


Is rectifier in MANUAL mode?

Is an ON GENERATOR condition active?

No

No

Is a Manual OR Automatic Test request active? Yes

Yes Yes

No

Set TST_BAT to OFF (Stop the Battery Test even if it is already in progress) Is the programmed test duration >0mins?

Yes

Increment test duration counter Set [abil_tst_bat> flag=ON. Annunciate alarm #50 [BATTERY: UNDER TEST]

No

Request "TEST Mode" to Rectifier Logic Bd (REC_A=1 / REC_B=1) set [TST_BAT> = ON (enable the TEST flag)

Is [tst_bat> = ON (test enabled)?

No

Yes

Is the battery voltage below the test threshold? (1.9V/cell)

No

No

No

Has the TEST duration counter reached its final count? (5 mins)

Reset delay counter to 0 Yes Yes Increment delay counter

No

Set [TST_BAT> = OFF (Stop the battery test))

Has the delay counter reached its terminal count? (1.5s)

Yes Remove alarm #50 [BATTERY: UNDER TEST]

Reset delay counter to 0

Request "FLOAT Mode" to Rectifier Logic Bd (REC_A=1 / REC_B=0)

Activate alarm #51 [BATTERY: TEST FAILED]

Reset the test duration counter to 0


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7.2.10 Load transf er cont rol log ic 7.2.10.1 Transfer contr ol system overview

The Transfer Control Logic consists of four sub-routines, each of which is associated with a particular transfer control l ogic state. During each cycle of the main program (100µ s), only one of these four routines is executed, as determined by the state of the “Load Status Flag” ( ST_CA): namely – •

“initialisation” mode (ST_CA = 0).

•

“load-on-bypass” mode ( ST_CA = 1).

•

“load-on-inverter” mode (ST_CA = 2).

•

“out-of-sync transfer” mode (ST_CA = 3).

That is, the four routines comprising the Load Transfer Control Logic t hemselves form a closed loop which is accessed every 100µs, whereby the selected routine to be executed is determined by the condition of the “Load Status Flag” ( ST_CA) set on the previous pass. This is illustrated in Figure 7-39. Example

Assuming that ST_CA is currently set to “1” (load-on-bypass mode). The load-on-bypass sub-routine’s preferred action is to transfer the load to the i nverter, after first examining the inverter output voltage status and confirming that it’s OK. If the inverter voltage status is found acceptable, this sub-routine grants the output contactor (K1) “permission to close” and sets ST_CA =2 – which means that on the next entry to the Transfer Control Logic (100µs later) the load-on-inverter subroutine will be selected for execution. On the other hand, if the inverter voltage status indicates an error condition then the subroutine will not grant permission to close K1 and ST_CA will remain set to “1” – which means that the load-on-bypass routine will be executed again the next time the Transfer Control Logic is called (in 100µs).

Due to its complexity, the four Transfer Control Logic subroutines are described individually on the following pages.

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Figure 7-39: Transfer Control Logic sub-routines Power-up

ST_CA=0

ST_CA=0 Initialisation Mode ST_CA=0

ST_CA=0

ST_CA=1

ST_CA=3 Out-Of-Sync Transfer Mode

ST_CA=1 Load-On-Bypass Mode

ST_CA=1

ST_CA=1

ST_CA=3

ST_CA=2

ST_CA=2 Load-On-Inverter Mode

ST_CA=2

7.2.10.2 ST_CA=0 (Load status = Initi alisati on mode)(See Chart 7-12)

This is the Load Transfer Control Logic s ubroutine entered during initial powerup, or when commanded by one of the other sub-routines (See Figure 7-39). When in this routine, the software examines various flags in order to undertake any actions appropriate to the “initialisation” mode of operation. For example; i f the bypass voltage status is OK it will lead to closing the bypass SCRs, and if the inverter output voltage is OK it will lead to closing the output contactor (K1). Once the appropriate action is determined, the load status flag ( ST_CA) is reassigned (ST_CA=1 or ST_CA=2) which calls the appropriate sub-routine the next time the Transfer Control Logic subroutine is executed (in 100µs). If no appropriate flags are set, the program returns to the main program without changing ST_CA, –i.e. leaving the load disconnected and ST_CA=0. Thus the next time the Load Transfer Control Logic subroutine is called (in 100µs) this same initialisation routine will be repeated. Monitored flags

The initialisation mode sub-routine monitors the following flags: 1. Bypass voltage monitor status – ST_SVI The bypass voltage is monitored by the UPS Logic Board micro via the High Voltage Interface Board. The ripple voltage to the A/D allows the individual monitoring of each phase, and a software routine compares the actual values against the programmed limit values to set the flag status: 0 = OK (bypass voltage within the mimic-programmed limits [±10%]) 1 = LOW (bypass undervoltage [below -10%]) 2 = HIGH (bypass voltage high [above +10%]) 3 = ABSENT (bypass voltage less than 50V)

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2. Bypass Blocked Status – BL_RETE This flag is generated by a software routine which monitors the condition of: •

[BLK_MNS> signal (alarm #16) –

which is activated by emergency power off; open bypass SCRs; phase rotation error; open bypass breaker; PCB power supply failure. •

[TLC_RETE> signal (alarm #17) –

bypass inhibit selection made by operator. BL_RETE = ON – if either alarm #16 or #17 is active. BL_RETE = OFF – if alarm #16 or #17 are both inactive.

3. Inverter Voltage Monitor Status – ST_SVINV The inverter voltage is monitored by the UPS Logic Board micro via the High Voltage Interface Board. The ripple voltage to the A/D allows the individual monitoring of each phase, and a software routine compares the actual values against the programmed limit values to set the flag status: 0 = OK (inverter voltage within the mimic-programmed limits [±10%]) 1 = LOW (inverter undervoltage [below -10%]) Activates alarm #37. 2 = HIGH (inverter voltage high [above +10%]) Activates alarm #36. 3 = ABSENT (inverter voltage less than 50V) 4. Operator-selected Inverter ON/OFF – TLC_INV The Inverter ON/OFF selection from the Operator Control Panel is monitored by the UPS Logic Board micro via the CAN Bus. TLC_INV = ON (Start inverter) TLC_INV = OFF (Stop inverter) Activates alarm #31.

5. Inverter Logic Board Run Status – BL_INV The Inverter Logic Board’s Stop/Run status is monitored by the UPS Logic Board micro. When in the inverter Stop mode, alarm #32 will be active. BL_INV = ON – if Inverter Logic Board Run/Stop control is in its Stop mode. BL_INV = OFF – if Inverter Logic Board Run/Stop control is in its Run mode.

6. Overload Latch Status – BLK_INV_OVL Presented to the UPS Logic Board micro from the 150% inverter current limit detection circuit on the Inverter Logic Board. A software delay allows 5 seconds of inverter operation before alarm #61 is latched. BLK_INV_OVL = ON – if overcurrent latch is activated –contactor K1 tripped. BLK_INV_OVL = OFF – if the overcurrent latch is not activated.

7. 10 second stability timer status – BLK_INV_DP The inverter is given 10 seconds to reach nominal voltage (i.e. within the mimic-programmed limits). BLK_INV_DP = ON – block closure of the output contactor (K1). BLK_INV_DP = OFF – permit closure of the output contactor (K1).

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Flow Chart 7-12: Transfer Control - (ST_CA=0) Begin SUB: Load transfer control

Is the load status flag in its initialisation state? (ST_CA=0)

No

Yes

Is the Bypass Voltage OK? (ST_SVI = OK)

Yes

Is the "bypass block" status active? (BL_RETE = OFF)

No

1

No Yes

To Next Chart Yes

No

Is the Inverter Voltage OK? (ST_SVINV = OK)

LOAD ON BYPASS

Set ST_CA = 1 annunciate alarm #18 [LOAD ON BYPASS]

Is the inverter selected ON from the Operator Panel? TLC_INV = ON

Set [L_MAINS> = 1 Turn ON bypass SCRs Set [L_INV> = 0 Open inverter contactor (K1)

No Yes

No

Is the "Inverter Run" status OK? [INV_BLK>=OFF

Yes

Yes

Is the "Inverter Overload Block" active? [BLK_INV_OVL> =ON

No

Is the "10s Stability Timer" latch active? [BLK_INV_DP> = ON

No

LOAD ON INVERTER

Set ST_CA=2 remove alarm #18 [LOAD ON BYPASS] Set [L_MAINS> = 0 Turn OFF bypass SCRs

Yes

Set [L_INV> = 1 Close inverter contactor (K1)

End SUB: Return to Main Program

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7.2.10.3 ST_CA=1 (Load status = Load-o n-byp ass mode) (See Chart 7-13)

This is the Load Transfer Control Logic subroutine entered when the load is connected to the bypass supply; as commanded by ST_CA=0 during the initialisation routine, or ST_CA=2 while the load is “on-inverter” (See Figure 7-39). When in this routine, the software examines various flags in order to undertake any actions appropriate to the “load-on-bypass” mode of operation. For example; if the inverter voltage status is OK it will lead to the closure of the output contactor (K1), if the bypass voltage fails it will lead to the opening of the bypass SCRs. Once the appropriate action is determined the load status flag ( ST_CA) is reassigned (i.e. ST_CA=2 or ST_CA=0) which calls the appropriate sub-routine the next time the Transfer Control Logic subroutine is executed (in 100µs). If no appropriate flags are set, the program returns to the main program without changing ST_CA, – i.e. leaving the load “on-bypass” and ST_CA=1. Thus the next time the Load Transfer Control Logic subroutine is called (in 100µs) this same “load-on-bypass” routine will be repeated. Monitored flags

The “load-on-bypass” mode sub-routine monitors the following flags: 1. Bypass Blocked Status – BL_RETE This flag is generated by a software routine which monitors the condition of: •





2. Auto-retransfer Mode Selection – X26:1-2 If jumper X26 pins 1-2 are “made” it allows the examination of the “onceonly” transfer flag ( BLK_COM_DP) which is set (ON) if the load has previously been transferred to the inverter. If X2 pins 1-2 are open this flag is ignored. 3. Inverter block Latch Status – TMP Before the load is transferred to the inverter, a temporary flag is enabled which monitors the status of: •

Overload timeout flag (alarm #61)

•

Inverter run flag (alarm #32) – see BL_INV below

•

“One-transfer” flag (enabled by X26:1-2 see above)

•

10 second “Stability” flag (enabled by X26:3-4)

•

Transfer counter flag (>8 transfers)

If any of the above flags are active, the TMP flag is set to ON and prevents the inverter output contactor (K1) being closed. Note that if the TMP flag is ON it can be reset only by selecting the inverter OFF/ON at the Operator Control Panel.

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4. Inverter Voltage Monitor Status – ST_SVINV The inverter voltage is monitored by the UPS Logic Board micro via the High Voltage Interface Board. The ripple voltage to the A/D allows the individual monitoring of each phase, and a software routine compares the actual values against the programmed limit values to set the flag status: 0 = OK (inverter voltage within the mimic-programmed limits [±10%]) 1 = LOW (inverter undervoltage [below -10%]) Activates alarm #37. 2 = HIGH (inverter voltage high [above +10%]) Activates alarm #36. 3 = ABSENT (inverter voltage less than 50V)

5. Operator-selected Inverter ON/OFF – TLC_INV The Inverter ON/OFF selection from the Operator Control Panel is monitored by the UPS Logic Board micro via the CAN Bus. TLC_INV = ON (Start inverter) TLC_INV = OFF (Stop inverter) Activates alarm #31.

6. Synchronisation Status – SYNK_OK A software routine within the PLL sub-routine verifies that the inverter and bypass voltages are within ±9° of each other. The inverter output contactor (K1) is inhibited for 5 seconds after this condition is satisfied in order to validate the circuit’s stability and allow time for the PLL to bring the phase dis placement error to zero. SYNK_OK = ON (OK to transfer) SYNK_OK = OFF (not OK to transfer)

7. Transfer Counter Status – CTR_ATT_RETE The transfer counter is incremented each time the load is transferred from the inverter to bypass, and flags an error if more than eight transfers take place over a one minute period. In such an occurrence the counter locks out t he out put contactor to prevent further transfers from taking place. a) Before the load is transferred to the inverter (ST_CA=2), the transfer counter is checked to see if this is the first transfer-to-inverter event. If it is, a one minute timer started; if it is not, then the timer is already running. b) Next, the transfer counter is examined. If the counter contents is less than eight, the output contactor (K1) is permitted to close. If the counter equals 8 (or more) the one minute timer is examined to see if it has timed-out; and if so, the temporary flag TMP is enabled (see above) which prevents the output contactor (K1) closing. c) The transfer counter is reset to zero if the inverter voltage falls below its nominal range, thus it is active only as long as the inverter voltage is OK. 8. Inverter Logic Board Run Status – BL_INV The Inverter Logic Board’s Stop/Run status is monitored by the UPS Logic Board micro. When in the inverter Stop mode, alarm #32 will be active. BL_INV = ON – if Inverter Logic Board Run/Stop control is in its Stop mode. BL_INV = OFF – if Inverter Logic Board Run/Stop control is in its Run mode.

9. 10s stability counter enable status – X26:3-4 The inverter is allowed 10 seconds to reach its nominal voltage (i.e. within its selected working voltage range [±10% default]). If the i nverter fails to satisfy

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this condition it is turned OFF and alarm #32 annunciated. This feature can be enabled/disabled via jumper X26 pins 3-4 (closed = enabled); the status of which is read by this subroutine. 10.Bypass voltage monitor status – ST_SVI The bypass voltage is monitored by the UPS Logic Board micro via the High Voltage Interface Board. The ripple voltage to the A/D allows the individual monitoring of each phase, and a software routine compares the actual values against the programmed limit values to set the flag status: 0 = OK (bypass voltage within the mimic-programmed limits [±10%]) 1 = LOW (bypass undervoltage [below -10%]) Activates alarm #12. 2 = HIGH (bypass voltage high [above +10%]) Activates alarm #11. 3 = ABSENT (bypass voltage less than 50V) Activates alarm #10.

11.150% Current Limit Status – OVL_INV The 150% overload condition is detected on the Inverter Logic Board and passed to the UPS Logic Board micro. Alarm #33 annunciates the overload fault condition. The ST_CA=1 sub-routine monitors this signal to enable it to hold the load “on-bypass”, even if the bypass voltage is outside its programmed voltage limits, once the inverter is feeding a short-circuit present between the inverter power blocks and the output contactor (K1).

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Flow Chart 7-13: Transfer Control - (ST_CA=1)

From Previous Chart 1

Is the load status flag in its Load-on-bypass mode? (ST_CA=1)

Yes

Is the "bypass block" status active? (BL_RETE = ON)

Set ST_CA = 0 (return to intialise mode)

Yes

Set [L_MAINS> = 0 Turn OFF bypass SCRs

No

Set [L_INV> = 0 Open inverter contactor (K1)

No

2 Is X26:1-2 Closed? (only one transfer to inverter allowed)

To Chart 7-14

Yes

No

Reset "Once Only Transfer " flag to OFF

Enable Inverter OFF latch (TMP=ON) To monitor:

Is the "once only transfer" flag activated? (i.e. load on inverter once before)

No

Yes

1. Overload timeout flag 2. Inverter block flag 3. Transfer counter >8 4. Once only transfer flag 5. 10s Stability flag

Set Transfer counter = 0

(If any of the above is activated then TMP=ON, else TMP=OFF)

Is the inverter selected ON at the mimic panel? (TLC_INV=ON)

Yes

Is the inverter voltage OK? (ST_SVINV=OK)

Yes

Is the "inverter Off Latch" active? (TMP=ON)

Yes

No

Disable Inverter OFF latch (TMP=ON)

No

No End SUB: Return to Main Program

(Use the mimic display to rest the latch trigger source from 1 -5 in above dialog box)

A

To Next Chart

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B

To Next Chart

C

To Next Chart

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Flow Chart 7-13: Continued

From Previous Chart

From Previous Chart A

B

C

Is the inverter voltage not OK? (ST_SVINV=KO)

No

No

Is the inverter in sync with bypass? SNYK_OK=ON

Yes

Yes

Is "Inverter Run" signal present? (BL_INV=OFF)

Is the transfer counter at zero?

No

Yes

Start the 1 minute timer Yes

No

Is X26:3-4 Closed? (10s inverter stability check enabled)

No

Yes

Yes

No

Has 10s delay expired?

Is the transfer counter >8?

Has 1 minute timer expired?

No

Yes

No

Set Counter >8 flag ON (CTR_ATT_RETE = ON) (trigger Alarm #60) This will also set (TMP=ON)

Yes Turn Inverter OFF Set BLK_INV = ON (trigger Alarm #32) Activate 10Sec Stability flag (i.e. TMP = ON) Are the bypass volts OK? (ST_SVI = 0)

Reset 1 minute counter = 0

Is the 5 seconds "wait in bypass" delay expired?

No

Yes Yes

No

Set ST_CA = 2 (Load on inverter mode) Is the inverter current limit active? OVL_INV=ON

Yes

Set [L_MAINS> = 0 Turn OFF bypass SCRs Set [L_INV> = 1 Close inverter contactor (K1)

Set ST_CA = 0 (return to initialise mode)

Set "Once only transfer" flag (i.e. TMP = ON)

No

Set [L_MAINS> = 0 Turn OFF bypass SCRs Set [L_INV> = 0 Open inverter contactor (K1) End SUB: Return to Main Program

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7.2.10.4 ST_CA=2 (Load status = Load-o n-inv erter mode)

This is the Load Transfer Control Logic subroutine entered when the load is connected to the inverter supply; as commanded by ST_CA=0 during the initialisation routine, or ST_CA=1 while the load is “on-bypass” (See Figure 7-39). When in this routine, the software examines various flags in order to undertake any actions appropriate to the “load-on-inverter” mode of operation. For example; if the inverter voltage status is not OK ( KO) it will lead to the closure of the bypass SCRs and the opening of the output contactor (K1). Once the appropriate action is determined the load status flag ( ST_CA) is reassigned (i.e. ST_CA=1 or ST_CA=3) and the next time the Load Transfer Control Logic subroutine is called (in 100µs) then the appropriate sub-routine will be executed. If no appropriate flags are set, the program returns to the main program without changing ST_CA, – i.e. leaving the load “on-inverter” and ST_CA=2. Thus the next time the Load Transfer Control Logic subroutine is executed (in 100µs) this same “load-on-inverter” routine will be called. Monitored flags

The “load-on-inverter” mode sub-routine monitors the following flags: 1. Output Voltage Monitor Status – ST_SVO The output voltage is monitored by the UPS Logic Board micro via the High Voltage Interface Board. The ripple voltage to the A/D allows the individual monitoring of each phase, and a software routine compares the actual values against the programmed limit values to set the flag status: 0 = OK (output voltage within the mimic-programmed limits [±10%]) 1 = LOW (output undervoltage [below -10%]) Activates alarm #40. 2 = HIGH (output voltage high [above +10%]) Activates alarm #39. 3 = ABSENT (output voltage less than 50V) Activates alarm #41.

2. Inverter Logic Board Run Status – BL_INV The Inverter Logic Board’s Stop/Run status is monitored by the UPS Logic Board micro. When in the inverter Stop mode, alarm #32 will be active. BL_INV = ON – if Inverter Logic Board Run/Stop control is in its Stop mode. BL_INV = OFF – if Inverter Logic Board Run/Stop control is in its Run mode.

3. Operator-selected Inverter ON/OFF – TLC_INV The Inverter ON/OFF selection from the Operator Control Panel is monitored by the UPS Logic Board micro via the CAN Bus. TLC_INV = ON (Start inverter) TLC_INV = OFF (Stop inverter) Activates alarm #31.

4. Bypass voltage monitor status – ST_SVI The bypass voltage is monitored by the UPS Logic Board micro via the High Voltage Interface Board. The ripple voltage to the A/D allows the individual monitoring of each phase, and a software routine compares the actual values against the programmed limit values to set the flag status: 0 = OK (bypass voltage within the mimic-programmed limits [±10%]) 1 = LOW (bypass undervoltage [below -10%]) Activates alarm #12. 2 = HIGH (bypass voltage high [above +10%]) Activates alarm #11. 3 = ABSENT (bypass voltage less than 50V) Activates alarm #10.

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6. Synchronisation Status – SYNK_OK A software routine within the PLL sub-routine verifies that the inverter and bypass voltages are within ±9° of each other. The inverter output contactor (K1) is inhibited for 5 seconds after this condition is satisfied in order to validate the circuit’s stability and allow time for the PLL to bring the phase dis placement error to zero. SYNK_OK = ON (OK to transfer) SYNK_OK = OFF (not OK to transfer)

7. Transfer Counter Status – CTR_ATT_RETE The transfer counter is incremented each time the load is transferred from the inverter to bypass, and flags an error if more than eight transfers take place over a one minute period. In such an occurrence the counter locks out t he out put contactor to prevent further transfers from taking place. a) Before the load is transferred to the inverter (ST_CA=2), the transfer counter is checked to see if this is the first transfer-to-inverter event. If it is, a one minute timer started; if it is not, then the timer is already running. b) Next, the transfer counter is examined. If the counter contents is less than eight, the output contactor (K1) is permitted to close. If the counter equals 8 (or more) the one minute timer is examined to see if it has timed-out; and if so, the temporary flag TMP is enabled (see above) which prevents the output contactor (K1) closing. c) The transfer counter is reset to zero if the inverter voltage falls below its nominal range, thus it is active only as long as the inverter voltage is OK. 8. 150% Current Limit Status – OVL_INV The 150% overload condition is detected on the Inverter Logic Board and passed to the UPS Logic Board micro. Alarm #33 annunciates the overload fault condition. The purpose of monitoring the flag in this instance is to force the inverter to feed a short circuit for 5 seconds if the bypass is absent. 9. 10s stability counter enable status – X26:3-4 If this function is enabled, and the bypass voltage is unavailable, the inverter is allowed 10 seconds to reach its nominal voltage (i.e. within its selected working voltage range [±10% default]). If the inverter fails to satisfy this condition it is turned OFF and alarm #32 annunciated. This feature can be ena bled/disabled via jumper X26 pins 3-4 (closed = enabled); the status of which is read by this subroutine. If this function is disabled, the critical bus status has no influence on the inverter run signal.

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Flow Chart 7-14: Transfer Control - (ST_CA=2)

From Chart 7-13 2

Is the load status flag in its Load-on-inverter mode? (ST_CA=2)

Yes

Is the "critical bus volts monitor" status OK? (ST_SVO = 0)

No

Yes

No

3 No

To Chart 7-15

Is the "inverter Run" status OFF? BL-INV=OFF

Is the Inverter selected OFF at the Mimic Panel? (TLC_INV=OFF)

Yes

Is the bypass voltage OK? (ST_SVI=0)

Yes

Yes

No

Yes

Is the "inverter Run" status OFF? BL-INV=OFF

Is the bypass block active? (BL_RETE=ON)

Yes

No No Yes

No


Set ST_CA = 0 Set [L_MAINS> = 0 Turn OFF bypass SCRs Set [L_INV> = 0 Open inverter contactor (K1)

No

Is the inverter in sync with the bypass? (SNYK_OK=ON)

No

Reset Transfer Counter Yes


D

To next chart

s7-c6.f m5 - Issu e 2 Dated 21/08/97

E

To next chart

F

To next chart

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Flow Chart 7-14: Continued

From previous chart

From previous chart

From previous chart F

E

D

Is the 150% current limit flag active? (OVL_INV=ON)

Yes

Set ST_CA = 1

Set ST_CA = 3

Set [L_MAINS> = 1 Turn ON bypass SCRs

Set [L_MAINS> = 0 Turn OFF bypass SCRs Set [L_INV> = 0 Open inverter contactor (K1)

Set [L_INV> = 0 Open inverter contactor (K1) Increment transfer counter Start 5 second "wait in bypass" delay timer

Has 5 second timer expired?

No

No


Yes No Set ST_CA = 0 Set [L_MAINS> = 0 Turn OFFbypass SCRs

Yes

Set [L_INV> = 0 Open inverter contactor (K1)

Turn Inverter OFF for 1 sec.

Reset transfer counter Set Blk_INV=ON Alarm #32 Activiate Overload Alarm #61

Is X26:3-4 closed?


Yes

Has the 10s delay expired?

Yes

Set ST_CA = 0 Set [L_MAINS> = 0 Turn OFFbypass SCRs Set [L_INV> = 0 Open inverter contactor (K1) Reset transfer counter No

Set Blk_INV=ON Alarm #32 Set 10s Stability flag=ON (i.e. TMP=ON)

No End SUB: Return to Main Program

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7.2.10.5 ST_CA=3 (Load status = Out-of -Sync transfer mod e)

This is the Load Transfer Control Logic subroutine entered when commanded by ST_CA=2 while the load is “on-inverter” (See Figure 7-39). When in this routine, the software examines various flags in order to undertake any actions appropriate to the “out-of-sync” mode of operation. For example; once an out-of-sync transfer has occurred, a three second break is introduced before the bypass SCRs are closed. Once the appropriate actions are taken, the load status flag is re-assigned to either ST_CA = 1 or ST_CA = 0, which calls for one of the routines described earlier to be executed on the next pass of the main program. If no appropriate flags are set, the program returns to the main program without changing the load status flag (ST_CA still = 3). Thus the next time the Load Transfer Control Logic subroutine is executed (in 100µs) t his same “out-of-sync” subroutine will be called. Monitored flags

The “out-of-sync” transfer mode sub-routine monitors the following flags: 1. Output contactor (K1) status flag – XSTAI2 This flag is initially set (OFF) as K1 is closed while the load is “on-inverter” (ST_CA=2). When undertaking an “out-of-sync” transfer, contactor K1 should open, then after a delay of 3 seconds the bypass SCRs should be turned ON. The 3 second delay is controlled by the system software and is initiated when XSTAI2 indicates that K1 is open. Note that XSTAI2 is connected to K1 auxiliary contacts and sensed via the High Voltage Interface Board. XSTAI2 = ON (K1 contactor is closed) XSTAI2 = OFF (K1 contactor is open)



which activated by emergency power off; open bypass SCRs; phase rotation error; open bypass breaker; PCB power supply failure. •



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Sect-7

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