Schema Placa mãe Dell Inspiron 14 - 3421 (PNB040)

5

D

4

3

2

1

D

Essentials Oak 14 Schematic Chief River 2012-09-05 REV : A00

C

C

B

A

B

DY : None Installed UMA: UMA only installed OPS: DISCRTE OPTIMUS installed

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

Cover Page Size A3 Date:

5

4

A

3

2

Document Number

Rev

OAK14 Chief River DIS

W ednesday, September 05, 2012

Sheet 1

1

A00 of

105

5

4

3

2

1

CHARGER

Project code: 91.4WT01.001 91.4XP01.001 PCB P/N : 12204 Revision: A00

BQ24727 INPUTS

Oak14 Block Diagram

40

OUTPUTS

AD+

DCBATOUT

BT+

SYSTEM DC/DC TPS51225 INPUTS OUTPUTS

41

3D3V_AUX_S5 5V_AUX_S5 DCBATOUT 5V_S5 3D3V_S5

D

Intel CPU Nvidia

VRAM(DDR3) *8 128Mx16bx4(1GB) 256Mx16bx4(2GB) 128Mx16bx8(2GB)

DDR3

PCIe x 8

DDR3 1333/1600MHz Channel B

BGA1023

DDR3 SUS TPS51216 INPUTS OUTPUTS

SODIMM B 15

4,5,6,7,8,9,10

only

VCC_CORE VCC_GFXCORE 26

DCBATOUT

DDR3 1333/1600

83,84,85,86,87

Switchable Graphic

42~44 ISL95833 33 INPUTS OUTPUTS

14

17W (DC)

25W

CPU Core/NB Power

SODIMM A

Ivy Bridge

N13P - GS - OP N13M- GSR

88,89,90,91

DDR3 1333/1600

DDR3 1333/1600MHz Channel A

D

46

DCBATOUT 1D5V_S3

DDR3 VTT FDIx4x2

TPS51216 INPUTS OUTPUTS

DMIx4

46

DCBATOUT 0D75V_S0

CPU VCCP_CPU

HDMI V1.4a

C

PCIE x 1

51

Intel PCH 14.0" LCD (16:9)

LVDS (2channel)

58

B

12 USB 2.0/1.1 ports 4 USB 3.0 ports High Definition Audio 6 SATA ports 8 PCIE ports LPC I/F ACPI 4.0a

HDA CODEC

MIC_IN/GND

SYW231 INPUTS

OUTPUTS

3D3V_S5

1D8V_S0

47

Intel CPU_VCCSA TPS51463 INPUTS OUTPUTS

65

5V_S5

USB3.0 x 2

LPC BUS

0D85V_S0

ADP3211MNR2G INPUTS OUTPUTS

USB3.0 Port x 2 61,62,63

Switches

USB Board

INPUTS

USB2.0 Port x 1

CardReader Realtek RTS5170

SD/SDHC/MS/MS Pro Slot

SPI

NPCE885P

36 93

OUTPUTS

1D5V_S3

1D5V_S0

5V_S5

5V_S0

3D3V_S5

3D3V_S0

B

1D05V_VGA_S0

3D3V_S0

3D3V_VGA_S0

1D5V_S3

1D5V_VGA_S0

PCB LAYER

74

32

L1:Top L4:Signal L2:VCC L5:GND L3:Signal L6:Bottom

17,18,19,20,21,22,23,24,25

NUVOTON

92

DCBATOUT VGA_CORE

USB2.0 x 2

USB2.0 x 1

48

Nvidia VGA_CORE

Left side

KBC

Fan Control

A

Mini-Card 802.11 b/g/n BT V4.0 combo

C

Intel PCH 1D8V_S0

VCCP_CPU

SMBUS

NUVOTON NCT7718W 28

FAN 28

USB2.0 x 1

USB2.0 x 1

71

NUVOTON NCT3940S-A

59

Right side

LPC debug port

Thermal

PCIE x 1

45

DCBATOUT 1D05V_S0

29

2CH SPEAKER (2CH 2W/4ohm)

58

31

HDA

Realtek ALC3221

HP_R/L

Combo Jack

HM76

USB2.0 x 1 49

RJ45 Conn.

Realtek RTL8105E-VD

Panther Point

49

BGA989 Camera Digital MIC

TPS51219 INPUTS OUTPUTS

10/100 NIC

HDMI

SATA(Gen3) x 1

HDD 56

27

28

Int. KB

Flash ROM

PS2

8MB

SATA(Gen1) x 1

60

ODD

69

56

Touch PAD Profile/Image sensor

A

SMBUS M14 DIS

69

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size C Date:

5

4

3

2

Block Diagram Document Number


Wednesday, September 05, 2012

Sheet 1

2

of

Rev

A00 105

A

B

PCH Strapping

INIT3_3V#

4 INTVRMEN

GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51

DF_TVS

SATA1GP/ GPIO19

3

Schematics Notes

This signal is a strap for selecting DMI and FDI termination voltage. For Ivy Bridge processor only implementation: DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor. For future processor compatibility: It needs to be connected to PROC_SELECT through a 1.0 kOhms ±5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms ±5% pull-up resistor to PCH VccDFTERM. Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Panther Point require SPI flash connected directly to the Panther Point's SPI bus with a valid descriptor in order to boot. NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot BIOS Destination Bit will not affect SPI accesses initiated by Management Engine or Integrated GbE LAN. NOTE: PCI Boot BIOS destination is not supported on mobile.

SATA3GP/ GPIO37

2 GPIO15

L_DDC_DATA

SDVO_CTRLDATA

PCIe Static x16 Lane Numbering Reversal.

CFG[4]

Display Port Presence strap

PCIE Port Bifurcation Straps

1:Disabled - No Physical Display Port attached to Embedded DisplayPort No connect for disable 0:Enabled - An external Display Port device is connected to the Embedded Display Port Pull-down to GND through a 1KΩ ± 5% resistor to enable port 00 01 10 11

= = = =

1 x 8, 2 x 4 PCI Express reserved 2 x 8 PCI Express 1 x 16 PCI Express

1

1

Voltage Rails POWER PLANE

VOLTAGE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V 3.3V 1.8V 1.5V 1.05V 0.95 - 0.85V 0.75V 0.35V to 1.5V 0.4 to 1.25V 1.8V 3.3V 1V

DESCRIPTION

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

5V 1.5V 0.75V

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

6V-14.1V 6V-14.1V 5V 5V 3.3V 3.3V

3D3V_LAN_S5

3.3V

WOL_EN

Legacy WOL

3D3V_AUX_KBC

3.3V

DSW, Sx

ON for supporting Deep Sleep states

3D3V_AUX_S5

3.3V

G3, Sx

Powered by Li Coin Cell in G3 and +V3ALW in Sx

ACTIVE IN

CPU Core Rail Graphics Core Rail

S3

AC Brick Mode only All S states

3

DDR3 VREF

Configuration

Sandy Bridge + Ivy Bridge Ivy Bridge

PROC_SELECT# & DF_TVS

Ivy Bridge

VCCIO VR Implementation

Ivy Bridge

VCCSA_SEL connection to VCCSA_VID[1:0] lines

Pair

DDR3 VREF M1 and M3 Guidelines are required. Note: The M3 traces are routed to the Sandy Bridge Processor reserved pins.

LANE2

X X

LANE3

Mini Card1(WLAN)

LANE4

x

LANE5 LANE6

X Onboard LAN

LANE7

X

LANE8

X

Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor through a 1K±5% series resistor. PROC_SELECT# also needs a 2.2K±5% pull up resistor to PCH VccDFTERM rail. No change.

Sandy Bridge + Ivy Bridge

USB Table

LANE1

No change.


PCIE Routing

Schematic Notes

USB3.0 port1

1

USB3.0 port2, with Debug Port

2

USB2.0 port3

3

X

4

X

5

Touch Panel

6

HM76 NC

7

HM76 NC

8

X X

10

CARD READER

11 12

Mini Card (WLAN) X

13

CAMERA

No change.


2

SATA Table

VCCSA_SELECT[0:1] which should be connected to VID[1:0] of the System Agent (SA) VR controller.

SATA Ivy Bridge

Pair

No change.

Sandy Bridge + Ivy Bridge Layout Requirement on PCI Express Gen3 Ivy Bridge GT Core VR Implementation


Processor PCI Express Graphics Guidelines

Sandy Bridge + Ivy Bridge (PCIe Gen3):

Ivy Bridge

The total motherboard length for a pair of consecutive PCI Express Tx lanes be length matched within 100 mils (2.54 mm) No change.

Depending on the PDDG specifications, some IVB GT2 SKUs may require a new VR controller and 2 phase VCC GT core VR.

Device

0

HDD1

1

X

2

X

3

X

4

ODD1

5

X

No change.

Ivy Bridge

To support Gen 3 PCI Express Graphic, the value of the AC coupling capacitor should be 180 - 265 nF. No change.

1 M14 DIS

Wistron Corporation

GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, SLP_LAN# must be used to control the power to the PHY LAN (no other implementation is supported). If integrated Intel LAN is not supported on the platform, GPIO29 can be used as a normal GPIO. A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default, the soft strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable GPIO functionality, then SLP_LAN# functionality is no longer available, and the signal can be used as a normal GPIO (default to GPI).

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date:

B

Device

0

9

The POR for Ivy Bridge mobile parts is now 1.05 V. There is no longer a requirement for a separate VCCIO VR for Sandy Bridge + Ivy Bridge compatibility.

The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled.If not used, 8.2-kΩ to 10-kΩ pull-up to +V3.3A power-rail. GPIO28 signal also needs to be pulled up to 3.3V_SUS with 4.7K resistor to ensure proper strap setting when use as the chipset test interface.Refer to the latest platform debug design guide and platform design guide for more details. NOTE:This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# deasserts.

A

4

S0

1

Chief River Schematic Checklist Revision 1.5

Port B Detected When '1'- Port B is detected; When '0'- Port B is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

DDPD_CTRLDATA

1: Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed

Reserved configuration CFG[17:7] lands. A test point may be placed on the board for these lands.

Pin Name

LVDS Detected. When '1'- LVDS is detected; When '0'- LVDS is not detected. This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

Port D Detected. When '1'- Port D is detected; When '0'- Port D is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

Default Value

Sandy Bridge + Ivy Bridge Compatibility Requirements

Signal has a weak internal pull-down. If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect (default).If sampled high, the Flash Descriptor Security will be overridden. This strap should only be asserted high via external pull-up in manufacturing/debug environments ONLY. Note: The weak internal pull-down is disabled after PLTRST# deasserts. Asserting the HDA_SDO high on the rising edge of PWROK will also halt Intel Management Engine after chipset bring up and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manufacturing/ debug.This signal has a 20k internal pull down resistor. This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled low. Needs to be pulled High for Chief River platform. Note: HDA_SYNC signal also serves as a strap for selecting VRM voltage to the PCH. The strap is sampled on the rising edge of RSMRST# signal. Due to potential leakage on the codec (path to GND), the strap may not be able to achieve the Vihmin at PCH input.Therefore, platform may need to isolate this signal from the codec during the strap phase. Refer to the example circuits provided in the latest Chief River platform design guide. TLS Confidentiality Low (0) – Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality This signal has a weak internal pull-down. NOTE:The weak internal pull-down is disabled after RSMRST# deasserts. NOTE: A strong pull-up may be needed for GPIO functionality

Port C Detected. When '1'- Port C is detected; When '0'- Port C is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

GPIO29/ SLP_LAN#

CFG[2]

CFG[6:5]

Chief River Schematic Checklist Revision 1.5 Configuration (Default value for each bit is 1 unless specified otherwise) Connect a series 1 kOhms resistor on the critical CFG[0] trace in a manner which does not introduce any stubs to CFG[0] trace. Route as needed from the opposite side of this series isolation resistor to the debug port. ITP will drive the net to GND.

High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an active-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch electrically connects the IntelR HD Audio dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33.

DDPC_CTRLDATA

1 GPIO28

Strap Description

CFG[0]

GNT[3:0]# functionality is not available on Mobile. Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

Reserved This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

HDA_SYNC

Pin Name

Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high NOTE: This signal should always be pulled high External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low. NOTE: This signal should be pulled down to GND through 330 kOhms resistor

Reserved. This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

HDA_SDO

E Power Plane

Processor Strapping

The signal has a weak internal pull-down. Note: the internal pull-down is disabled after PLTRST# deasserts. If the signal is sampled high, this indicates that the system is strapped to the “No Reboot” mode (Panther Point will disable the TCO Timer system reboot feature). This signal has a weak internal pull-up. Note: The internal pull-up is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled low. Leave as "No Connect".

SATA2GP/ GPIO36

HDA_DOCK_EN# /GPIO33

D

Chief River Schematic Checklist Revision 1.5

Name SPKR

C

C

D

Table of Content OAK14 Chief River DIS

Document Number


E

Sheet

3

Rev

A00 of

105

5

4

SSID = CPU

3

2

1

Layout Note: Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

D

D VCCP_CPU 1 OF 9

CPU1A

Layout Note:

19 DMI_CPU_RXP_PCH_TXP[3:0]

19 DMI_CPU_TXN_PCH_RXN[3:0]

19 DMI_CPU_TXP_PCH_RXP[3:0]

19 FDI_CPU_TXN_PCH_RXN[7:0]

C Layout Note:

FDI trace length 2000~6500mil

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_CPU_RXP_PCH_TXP0 DMI_CPU_RXP_PCH_TXP1 DMI_CPU_RXP_PCH_TXP2 DMI_CPU_RXP_PCH_TXP3

N3 P7 P3 P11

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_CPU_TXN_PCH_RXN0 DMI_CPU_TXN_PCH_RXN1 DMI_CPU_TXN_PCH_RXN2 DMI_CPU_TXN_PCH_RXN3

K1 M8 N4 R2

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_CPU_TXP_PCH_RXP0 DMI_CPU_TXP_PCH_RXP1 DMI_CPU_TXP_PCH_RXP2 DMI_CPU_TXP_PCH_RXP3

K3 M7 P4 T3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI_CPU_TXN_PCH_RXN0 FDI_CPU_TXN_PCH_RXN1 FDI_CPU_TXN_PCH_RXN2 FDI_CPU_TXN_PCH_RXN3 FDI_CPU_TXN_PCH_RXN4 FDI_CPU_TXN_PCH_RXN5 FDI_CPU_TXN_PCH_RXN6 FDI_CPU_TXN_PCH_RXN7

U7 W11 W1 AA6 W6 V4 Y2 AC9

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI_CPU_TXP_PCH_RXP0 FDI_CPU_TXP_PCH_RXP1 FDI_CPU_TXP_PCH_RXP2 FDI_CPU_TXP_PCH_RXP3 FDI_CPU_TXP_PCH_RXP4 FDI_CPU_TXP_PCH_RXP5 FDI_CPU_TXP_PCH_RXP6 FDI_CPU_TXP_PCH_RXP7

U6 W10 W3 AA7 W7 T4 AA3 AC8

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI_FSYNC0 AA11 FDI_FSYNC1 AC12

19 FDI_FSYNC0 19 FDI_FSYNC1

FDI_INT

19 FDI_INT

FDI_LSYNC0 AA10 FDI_LSYNC1 AG8

19 FDI_LSYNC0 19 FDI_LSYNC1

B

VCCP_CPU

R402 1

U11

2 24D9R2F-L-GP

DP_COMP

Layout Note:

FDI_INT FDI0_LSYNC FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD#

AG4 AF4

EDP_AUX# EDP_AUX

AC3 AC4 AE11 AE7

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

AC1 AA4 AE10 AE6

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3 IVY-BRIDGE-GP-NF

71.00IVY.A0U

A

eDP

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

AF3 AD2 AG11

FDI0_FSYNC FDI1_FSYNC

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

Intel(R) FDI

19 FDI_CPU_TXP_PCH_RXP[7:0]

M2 P6 P1 P10

DMI

DMI trace length 2000~8000mil

DMI_CPU_RXN_PCH_TXN0 DMI_CPU_RXN_PCH_TXN1 DMI_CPU_RXN_PCH_TXN2 DMI_CPU_RXN_PCH_TXN3

PCI EXPRESS -- GRAPHICS

19 DMI_CPU_RXN_PCH_TXN[3:0]

G3 G1 G4

PEG_IRCOMP_R

R401

2 24D9R2F-L-GP

1

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

CPU_RXP_C_dGPU_TXP7 CPU_RXP_C_dGPU_TXP6 CPU_RXP_C_dGPU_TXP5 CPU_RXP_C_dGPU_TXP4 CPU_RXP_C_dGPU_TXP3 CPU_RXP_C_dGPU_TXP2 CPU_RXP_C_dGPU_TXP1 CPU_RXP_C_dGPU_TXP0

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

CPU_TXN_dGPU_RXN7 CPU_TXN_dGPU_RXN6 CPU_TXN_dGPU_RXN5 CPU_TXN_dGPU_RXN4 CPU_TXN_dGPU_RXN3 CPU_TXN_dGPU_RXN2 CPU_TXN_dGPU_RXN1 CPU_TXN_dGPU_RXN0

1OPS 1OPS 1OPS 1OPS 1OPS 1OPS 1OPS 1OPS

2 2 2 2 2 2 2 2

C401 C402 C403 C404 C405 C406 C407 C408

SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP

dGPU_RXN_C_CPU_TXN8 dGPU_RXN_C_CPU_TXN9 dGPU_RXN_C_CPU_TXN10 dGPU_RXN_C_CPU_TXN11 dGPU_RXN_C_CPU_TXN12 dGPU_RXN_C_CPU_TXN13 dGPU_RXN_C_CPU_TXN14 dGPU_RXN_C_CPU_TXN15

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

CPU_TXP_dGPU_RXP7 CPU_TXP_dGPU_RXP6 CPU_TXP_dGPU_RXP5 CPU_TXP_dGPU_RXP4 CPU_TXP_dGPU_RXP3 CPU_TXP_dGPU_RXP2 CPU_TXP_dGPU_RXP1 CPU_TXP_dGPU_RXP0

1OPS 1OPS 1OPS 1OPS 1OPS 1OPS 1OPS 1OPS

2 2 2 2 2 2 2 2

C409 C410 C411 C412 C413 C414 C415 C416

SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP

dGPU_RXP_C_CPU_TXP8 dGPU_RXP_C_CPU_TXP9 dGPU_RXP_C_CPU_TXP10 dGPU_RXP_C_CPU_TXP11 dGPU_RXP_C_CPU_TXP12 dGPU_RXP_C_CPU_TXP13 dGPU_RXP_C_CPU_TXP14 dGPU_RXP_C_CPU_TXP15

CPU_RXN_C_dGPU_TXN7 CPU_RXN_C_dGPU_TXN6 CPU_RXN_C_dGPU_TXN5 CPU_RXN_C_dGPU_TXN4 CPU_RXN_C_dGPU_TXN3 CPU_RXN_C_dGPU_TXN2 CPU_RXN_C_dGPU_TXN1 CPU_RXN_C_dGPU_TXN0

CPU_RXN_C_dGPU_TXN[7..0]

83

CPU_RXP_C_dGPU_TXP[7..0]

83

C dGPU_RXN_C_CPU_TXN[8..15]

83

dGPU_RXP_C_CPU_TXP[8..15]

83

B

Note: PEG with reversal type.

A

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:

CPU(PCIE/DMI/FDI) Document Number

Rev

A00

OAK14 Chief River DIS W ednesday, September 05, 2012

Sheet

4

of

105

5

4

SSID = CPU

3

D

2 OF

TP501

1

SKTOCC#_R

1

F49

PROC_SELECT#

C57

PROC_DETECT#

H_CATERR#

C49

CATERR#

H_PECI

A48

PECI

H_PROCHOT#_R

C45

PROCHOT#

H_THERMTRIP#

D45

THERMTRIP#

VCCP_CPU TPAD14-OP-GP

TP502

R501

2

H_PROCHOT#

62R2J-GP

22,27

H_PECI R513

1

27,38,40,42 H_PROCHOT#

2

56R2J-4-GP 22 H_THERMTRIP#

THERMAL

1

Layout Note: R501, R513 place near to CPU

H_PM_SYNC

H_PM_SYNC R504 0R0402-PAD 1 2

22 H_CPUPW RGD

C48

H_CPUPW RGD_R

B46

PM_SYNC

UNCOREPWRGOOD

1 R503 2 10KR2J-3-GP VDDPW RGOOD

37 VDDPW RGOOD

BUF_CPU_RST#

2

R510 1K5R2F-2-GP

D44

RESET#

1

1

C501 SC220P50V2KX-3GP

DY

D

9

BCLK BCLK#

J3 H2

CLK_EXP_P CLK_EXP_N

AG3 AG1

CLK_DP_P_R1 CLK_DP_N_R2

CLK_EXP_P 20 CLK_EXP_N 20 RN503

DPLL_REF_CLK DPLL_REF_CLK#

4 3

VCCP_CPU

Layout Note: Checking the connector pin's LAYOUT

SRN1KJ-7-GP

SM_DRAMRST#

AT30

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

BF44 BE43 BG43

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PRDY# PREQ#

N53 N55

XDP_PRDY# XDP_PREQ#

TCK TMS TRST#

L56 L55 J58

XDP_TCLK XDP_TMS XDP_TRST#

TDI TDO

M60 L59

XDP_TDI XDP_TDO

SM_DRAMRST# 37 R506 1 R508 1 R511 1

2 140R2F-GP 2 25D5R2F-GP 2 200R2F-L-GP

Layout Note: XDP_PRDY# 71 XDP_PREQ# 71

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils. Trace width = 15mil

RN501 XDP_TDI XDP_TMS XDP_TDO

DBR#

K58

XDP_DBRESET#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

G58 E55 E59 G55 G59 H60 J59 J61

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

C VCCP_CPU

XDP_DBRESET# 19

1 2 3 4

8 7 6 5

XDP

SRN51J-1-GP XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

71 71 71 71 71 71 71 71

RN502 XDP_TRST# XDP_TCLK

1 2

4 3

XDP

SRN51J-GP

2

R509 698R2F-GP

2

PLT_RST#

SM_DRAMPWROK

1

18,27,31,65,71,83

BE45

PWR MANAGEMENT

19

JTAG & BPM

C

1

R507 4K99R2F-L-GP 1 2

DDR3 MISC

H_SNB_IVB#

H_SNB_IVB#

MISC

22

CLOCKS

CPU1B

TPAD14-OP-GP

2

IVY-BRIDGE-GP-NF

71.00IVY.A0U

B

B

Layout Note: C501 place near to CPU

XDP_DBRESET#

1

1

DY

EC502 SCD1U10V2KX-5GP


DY

2

2

DY

PLT_RST#

2

1

H_CPUPW RGD EC501 SCD1U10V2KX-5GP

reserve for EMI Request

A

A

M14 DIS


CPU(THERMAL/CLOCK/PM) Document Number

Rev

A00


Sheet

5

of

105

5

4

3

2

1

SSID = CPU 4 OF 9

CPU1D 3 OF 9 15 M_B_DQ[63:0]

M_A_DQ[63:0]

14 M_A_DQ[63:0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

C

B

AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

14 14 14

M_A_BS0 M_A_BS1 M_A_BS2

BD37 BF36 BA28

SA_BS0 SA_BS1 SA_BS2

14 14 14

M_A_CAS# M_A_RAS# M_A_W E#

BE39 BD39 AT41

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

D

M_B_DQ[63:0]

SA_CK0 SA_CK#0 SA_CKE0

AU36 AV36 AY26

M_A_DIMA_CLK_DDR0 14 M_A_DIMA_CLK_DDR#0 14 M_A_DIMA_CKE0 14

SA_CK1 SA_CK#1 SA_CKE1

AT40 AU40 BB26

M_A_DIMA_CLK_DDR1 14 M_A_DIMA_CLK_DDR#1 14 M_A_DIMA_CKE1 14

SA_CS#0 SA_CS#1

BB40 BC41

M_A_DIMA_CS#0 14 M_A_DIMA_CS#1 14

SA_ODT0 SA_ODT1

AY40 BA41

M_A_DIMA_ODT0 14 M_A_DIMA_ODT1 14

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_A_DQS#[7:0] 14

M_A_DQS[7:0] 14

M_A_A[15:0] 14

AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

15 15 15

M_B_BS0 M_B_BS1 M_B_BS2

BG39 BD42 AT22

SB_BS0 SB_BS1 SB_BS2

15 15 15

M_B_CAS# M_B_RAS# M_B_W E#

AV43 BF40 BD45

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

CPU1C

SB_CK0 SB_CK#0 SB_CKE0

BA34 AY34 AR22

M_B_DIMB_CLK_DDR0 15 M_B_DIMB_CLK_DDR#0 15 M_B_DIMB_CKE0 15

SB_CK1 SB_CK#1 SB_CKE1

BA36 BB36 BF27

M_B_DIMB_CLK_DDR1 15 M_B_DIMB_CLK_DDR#1 15 M_B_DIMB_CKE1 15

SB_CS#0 SB_CS#1

BE41 BE47

M_B_DIMB_CS#0 15 M_B_DIMB_CS#1 15

SB_ODT0 SB_ODT1

AT43 BG47

M_B_DIMB_ODT0 15 M_B_DIMB_ODT1 15

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

D

C

M_B_DQS#[7:0] 15

M_B_DQS[7:0] 15

B

M_B_A[15:0] 15

IVY-BRIDGE-GP-NF IVY-BRIDGE-GP-NF

71.00IVY.A0U

71.00IVY.A0U

M14 DIS

A

A


CPU (DDR) Size A3 Date: 5

4

3

2

Document Number

Rev


Sheet 1

6

of

A00 105

5

4

3

2

1

SSID = CPU

C

TP719

1VCC_DIE_SENSE

H43 K43

VCC_VAL_SENSE VSS_VAL_SENSE

H45 K45

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

F48 G48

VCC_DIE_SENSE RSVD47

H48 K48

RSVD6 RSVD7

BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24

B

1 BCLK_ITP BCLK_ITP#

N59 N58

RSVD30 RSVD31 RSVD32 RSVD33

N42 L42 L45 L47

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

M13 M14 U14 W14 P13

RSVD39 RSVD40

AT49 K24


AH2 AG13 AM14 AM15

RSVD45

N50

BCLK_ITP BCLK_ITP#

1 1

OPS

TP721 TP722

CFG[2]

2

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

1: Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed

Display Port Presence Strap 1: Disabled; No Physical Display Port attached to Embedded Display Port

CFG[4]

0: Enabled; An external Display Port device is connected to the Embedded Display Port

CFG5

C

PCIE Port Bifurcation Straps

CFG6

1

1 1

B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53

R701

R704

CFG[6:5]

DY 1KR2J-1-GP OPS 1KR2J-1-GP DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

D

PEG Static Lane Reversal R702 1KR2J-1-GP

A4 C4 DC_TEST_C4_D3 D3 D1 A58 A59 TP_DC_TEST_A59_C59 C59 A61 TP_DC_TEST_A61_C61 C61 D61 BD61 BE61 BE59 TP_DC_TEST_BE59_BE61 BG61 BG59 DC_TEST_BG59_BG61 BG58 BG4 BG3 DC_TEST_BE3_BG3 BE3 BG1 DC_TEST_BE1_BG1 BE1 BD1

11: 1x16 PCI Express 10: 2 x8 - PCI Express

2

TP702 TP703

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6

1

1

2

CFG0 TP701

RESERVED

71

CFG2

5 OF 9

CPU1E

D

01: Reserved 00: 1x8, 2x4 PCI Express

B

IVY-BRIDGE-GP-NF

71.00IVY.A0U

M14 DIS A

A


CPU (RESERVED) Size A3 Date: 5

4

3

2

Document Number

Rev


Sheet 1

7

of

A00 105

5

4

3

2

1

SSID = CPU VCC_CORE CPU1F

POWER

6 OF 9

1 2 1 2 1 2

1 2 1

1

1 2

2 1

1 2

2

2

1 2

1 2

1 1 2

1 2

2 1 2

1 1

2

1

1 2

2 1

1 2

2

2

PEG IO AND DDR IO

1 2

1

1 2

2 1 2

1

1

1 2

2

2

1 2

1

1 2

2

1 2

1 1

2

1

1 2

2

2

SC10U6D3V3MX-GP C885

C

W16 W17

BC22

H_SNB_IVB#_PWRCTRL

1

VCCPQ Output Decoupling CAP Recommendation:

TP801

1 x 1 uF (0402) +V1.05S_VCCPQE_R AM25 AN22

SVID

VIDALERT# VIDSCLK VIDSOUT

A44 B43 C44

R812 0R0402-PAD 2 1

VCCP_CPU

VCCP_CPU

Layout Note:

C802 SC1U6D3V2KX-GP

R803, R804, R805 need close to CPU Alert# signal must be routed between the Clock and Data lines to reduce the cross talk between them

2

R804 130R2F-1-GP 2

R805 75R2F-2-GP R803 43R2J-GP 1 2

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

1

1

1

VCCPQE1 VCCPQE2

2

QUIET RAILS

1 2

1 2

1 2

1 2

1 2 1 2

1 2 1 2

1 2 1 2

1 2 1

1 2 1 2

CORE SUPPLY

1 2

1

1 2

2

1 2

1 2

1 2

1 2

1 2

1 2

2 1 2 1 2

2 1 2

SC1U6D3V2KX-GP C886

SC1U6D3V2KX-GP C883

SC1U6D3V2KX-GP C882


DY

SC1U6D3V2KX-GP C881

DY



DY

DY

SC1U6D3V2KX-GP C847

1

SC4D7U6D3V3KX-GP C884



DY

SC1U6D3V2KX-GP C848

SC1U6D3V2KX-GP C846

DY


VCCIO_SEL

DY

SC1U6D3V2KX-GP C890

VCCIO50 VCCIO51

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

SC1U6D3V2KX-GP C891

2

D

SC1U6D3V2KX-GP C842

SC1U6D3V2KX-GP C841

DY

SC1U6D3V2KX-GP C838

SC1U6D3V2KX-GP C836

SC1U6D3V2KX-GP C839



DY

SC1U6D3V2KX-GP C834

DY

SC1U6D3V2KX-GP C840

SC1U6D3V2KX-GP C837

SC1U6D3V2KX-GP C844

DY

SC1U6D3V2KX-GP C835

SC1U6D3V2KX-GP C833

DY

8.5A

VCCP_CPU

VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40 VCCIO41 VCCIO42 VCCIO43 VCCIO44 VCCIO45 VCCIO46 VCCIO47 VCCIO48 VCCIO49

SC1U6D3V2KX-GP C887

C

SC1U6D3V2KX-GP C845

SC2D2U6D3V2MX-GP C823










DY







DY

DY

SC1U6D3V2KX-GP C832



DY

DY

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76

SC1U6D3V2KX-GP C843

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

SC1U6D3V2KX-GP C831

ULV 33A

D

DY

VCCIO1 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29

SC1U6D3V2KX-GP C830





SC22U6D3V5MX-2GP C807






1

VCCP_CPU VCC_CORE

VR_SVID_ALERT# 42 H_CPU_SVIDCLK 42 H_CPU_SVIDDAT 42

Need place Pull Hi at IMVP page

VCC_CORE

2

VCCSENSE VSSSENSE

VCCSENSE 43 VSSSENSE 43 VCCP_CPU

R802 100R2F-L1-GP-U

1 AN16 AN17

R807 10R2F-L-GP VCCIO_SENSE 45 VSSIO_SENSE 45

1

IVY-BRIDGE-GP-NF

R806 10R2F-L-GP 2

71.00IVY.A0U

Voltage Rail VCC_CORE

A

Voltage(V) 0.3~1.52

VAXG

0~1.52

VCCIO

1.05

VDDQ

1.5

VCCSA

0.675~0.9

VCCPLL

1.8

2

VCCIO_SENSE VSS_SENSE_VCCIO

1. PH/PL resisors place close CPU 2. SENSE signal recommend differential routing

1

F43 G43

2

SENSE LINES

R801 100R2F-L1-GP-U

VCC_SENSE VSS_SENSE

B

Layout Note:

1

B

Iccmax(A)

Layout Note: 1. PH/PL resisors place close CPU 2. SENSE signal recommend differential routing

33 29 (GT2) 8.5 5 4 1.2 A

Refer to CPU EDS V.1.7.5 M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

CPU (VCC_CORE) Size A2 Date: 5

4

3

2

Document Number

Rev

OAK14 Chief River DIS Wednesday, September 05, 2012 1

Sheet

8

of

A00 105

5

4

3

2

1

SSID = CPU Voltage Rail

VREF

1 2 1 2

1 2 1

1 2 1 2

1 2 1 2

1 2 1 2

1 2 1 2

1 2 1

2 1 2

2

1

1 2

1 2

- 1.5V RAILS DDR3

GRAPHICS

1 2 1 2 2

1

1

1 2 1 2 2 2

1

1 2 1 2 1 2

3 1.2


1

DY


2

1 2 1 2

1.8

SC1U6D3V2KX-GP C936

1

VCCPLL

SC1U6D3V2KX-GP C935

2

5

0.675~0.9


DY

SC1U6D3V2KX-GP C934

DY


1

8.5

1.5

VCCSA

1D5V_S0

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33


2

1

C

+V1.5S_VCCD_Q

SENSE LINES

1.8V RAIL

1D5V_S0

1

2

R903 0R0402-PAD 1

BC43 BA43

TP_VDDQ_SENSE TP_VDDQ_VSS

U10

VCCSA_SENSE

TP901 TP902

1 1

TPAD14-OP-GP TPAD14-OP-GP

B

VCCSA_SENSE

VCCSA_SENSE

48

VCCSA Power Select Voltage(ULV) VCCSA_VID0 VCCSA_VID1

D48 D49

VCCSA_SEL0 VCCSA_SEL1

VCCSA_SEL0 VCCSA_SEL1

48 48

RN901 SRN1KJ-7-GP

3 4

IVY-BRIDGE-GP-NF

VDDQ_SENSE VSS_SENSE_VDDQ

VCCSA VID lines

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA9 VCCSA10 VCCSA11 VCCSA12 VCCSA13 VCCSA14 VCCSA15 VCCSA16

SA RAIL

2

VCCPLL1 VCCPLL2 VCCPLL3

1 2 1 2 1

1 2 1 2

2

1 2

1 1 2 1

1 2

2

2

1 2 1 2

SC1U6D3V2KX-GP C914

DY

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20

DY

SC10U6D3V3MX-GP C909 SC1U6D3V2KX-GP C915

DY

DY

SC10U6D3V3MX-GP C910 SC1U6D3V2KX-GP C916

DY

SC10U6D3V3MX-GP SC1U6D3V2KX-GP C911 C917

SC10U6D3V3MX-GP SC1U6D3V2KX-GP C912 C918


1

ULV 4A

B

SC10U6D3V5KX-1GP C955

SC1U6D3V2KX-GP C908

SC1U6D3V2KX-GP C907

0D85V_S0

BB3 BC1 BC4

1.2A

2

1D8V_S0

AM28 AN26

2

VAXG_SENSE VSSAXG_SENSE

QUIET RAILS

F45 G45

1

VCC_AXG_SENSE VSS_AXG_SENSE

R902 100R2F-L1-GP-U

VCCDQ1 VCCDQ2

SC1U6D3V2KX-GP C937

44 VCC_AXG_SENSE 44 VSS_AXG_SENSE

SENSE LINES

2

R901 1. PH/PL resisors place close CPU 100R2F-L1-GP-U 2. SENSE signal recommend differential routing

2 1

1 2 1 2

1.05

VDDQ

5A VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26

SC1U6D3V2KX-GP C933

1

33 29 (GT2)

D

SC1U6D3V2KX-GP C932

2

VCCIO

Iccmax(A)

Refer to CPU EDS V2.0


1

DY

SRN1KJ-7-GP


2

1 2 1 2

0~1.52

2 1

SC1U6D3V2KX-GP C931

1

3 4

SC1U6D3V2KX-GP C930

2

BE7 DDR_WR_VREFA BG7 DDR_WR_VREFB


1

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

SC1U6D3V2KX-GP C929

VCC_GFXCORE

Layout Note:

RN902

SC1U6D3V2KX-GP C928

DY

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 VAXG55 VAXG56

SM_VREF

AY43

SC1U6D3V2KX-GP C927

SC1U6D3V2KX-GP C949

DY


SC1U6D3V2KX-GP C950

SC1U6D3V2KX-GP C954

SC1U6D3V2KX-GP C952

SC1U6D3V2KX-GP C948

SC1U6D3V2KX-GP C947

SC1U6D3V2KX-GP C946

2

C906 SC22U6D3V5MX-2GP



DY




SC1U6D3V2KX-GP C951

SC1U6D3V2KX-GP C953

DY


SC1U6D3V2KX-GP C945

SC1U6D3V2KX-GP C944

C



DY



D

+V_SM_VREF_CNT

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

0.3~1.52

VAXG

+V_SM_VREF_CNT should have 10 mil trace width 7 OF 9

ULV GT2 33A

VCC_GFXCORE

Voltage(V)

VCC_CORE

2

CPU1G

POWER

Layout Note:

VID[0]

VID[1]

0.9

0

0.85

0

0 1

0.775

1

0

0.75

1

1

71.00IVY.A0U

A

A

M14 DIS


CPU (VCC_GFXCORE) Size A2 Date: 5

4

3

2

Document Number

Rev


Sheet

9

of

A00 105

5

4

3

2

1

SSID = CPU 8 OF 9

CPU1H

9 OF 9

CPU1I

C

B

VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180

VSS

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15

VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249

VSS

：

NCTF TEST PIN A5,A57,BC61,BG5 BG57,C3,E1,E61

D

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90

NCTF

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34

VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

VSS_NCTF_1#A5 VSS_NCTF_2#A57 VSS_NCTF_3#BC61 VSS_NCTF_8#BG5 VSS_NCTF_9#BG57 VSS_NCTF_10#C3 VSS_NCTF_13#E1 VSS_NCTF_14#E61

A5 A57 BC61 BG5 BG57 C3 E1 E61

VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_11 VSS_NCTF_12

BD3 BD59 BE4 BE58 C58 D59

D

C

B

IVY-BRIDGE-GP-NF

71.00IVY.A0U

M14 DIS

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

IVY-BRIDGE-GP-NF

71.00IVY.A0U Title

CPU (VSS) Size A3 Date: 5

4

3

2

Document Number

Rev


Sheet 1

10

of

A00 105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


XDP Size A3 Date: 5

4

3

2

Document Number

Rev


Sheet 1

11

of

A00 105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5

4

3

2

Reserved

Document Number

Rev


Sheet 1

12

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

(Reserved)

Document Number

Rev


Sheet 1

13

A00 of

105

5

4

3

2

1

SSID = MEMORY DM1

C1418 SC1U6D3V2KX-GP

2

1 2


1 2


DY

1

6 M_A_DQS#[7:0]

6 M_A_DQS[7:0] B

116 120

6 M_A_DIMA_ODT0 6 M_A_DIMA_ODT1

126 1

M_VREF_CA_DIMMA M_VREF_DQ_DIMMA

Layout Note: All VREF traces should have width=20mil; spacing=20 mil

15,37 DDR3_DRAMRST# 0D75V_S0

EC1401 1

DY

30 2 SCD1U10V2KX-5GP 203 204

M_A_DIMA_CLK_DDR0 6 M_A_DIMA_CLK_DDR#0 6

102 104

M_A_DIMA_CLK_DDR1 6 M_A_DIMA_CLK_DDR#1 6

1 1 2 2

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2

Close to DIMM1.199

DY

1

DY 2

DY

C1408 SC10U10V5ZY-1GP

DY

2

DY

1

1D5V_S3

C1407 SC10U6D3V5KX-1GP

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

1D5V_S3

1

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

C1401 SCD1U10V2KX-5GP

2

77 122 125

SA0_DIMA SA1_DIMA


VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

197 201

1

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

3D3V_S0

199

2

SA0 SA1 NC#1 NC#2 NC#/TEST

PCH_SMBDATA 15,20,69 PCH_SMBCLK 15,20,69

198


VDDSPD

200 202


SDA SCL EVENT#

11 28 46 63 136 153 170 187

1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

D

2

CK1 CK1#

1

CK0 CK0#

2

12 29 47 64 137 154 171 188

101 103

Note: SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

R1402 0R0402-PAD

R1401 0R0402-PAD

1

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

6 6

2

10 27 45 62 135 152 169 186

M_A_DIMA_CKE0 M_A_DIMA_CKE1

C1403 SC10U6D3V5KX-1GP 2 1

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

73 74

SA0_DIMA SA1_DIMA

C


Place these caps close to VTT1 and VTT2.

6 6


Layout Note: 0D75V_S0

M_A_DIMA_CS#0 M_A_DIMA_CS#1

1

1 2


1

DY 2


1

2

M_VREF_DQ_DIMMA

CKE0 CKE1

BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

114 121

2

1

Place these caps close to VREF_DQ

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

CS0# CS1#


1

Layout Note:

R1404 0R0402-PAD

2

2

2

DDR_VREF_S3


1 C1428 SC2D2U10V3KX-1GP

DY

C1423 SC2D2U10V3KX-1GP

2


1

2

M_VREF_CA_DIMMA

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

1

Place these caps close to VREF_CA

R1405 0R0402-PAD

C

M_A_BS0 M_A_BS1 M_A_DQ[63:0]

110 113 115

2

1

Layout Note:

109 108

NP1 NP2

TC1401 ST330U2VDM-4-GP

6 6 6

DDR_VREF_S3

M_A_BS2

NP1 NP2 RAS# WE# CAS#

1

6

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

2

D

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79


M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

1

M_A_A[15:0]

2

6

Layout Note: Place these Caps near SO-DIMMA.

1D5V_S0

1D5V_S3

1

2

DY C1421 SCD1U10V2KX-5GP 1

2

B

DY C1424 SCD1U10V2KX-5GP

Layout Note: For S3 reduction circuit's 1D5V return pass.

DDR3-204P-119-GP-U

62.10017.Z81

A

A

M14 DIS


DDR3-SODIMM1 Size A2 Date: 5

4

3

2

Document Number

Rev

A00

DNE40 14 CR DIS Wednesday, September 05, 2012 1

Sheet

14

of

105

5

4

SSID = MEMORY

6 M_B_DQS#[7:0]

6 M_B_DQS[7:0] B

116 120

6 M_B_DIMB_ODT0 6 M_B_DIMB_ODT1

126 1

M_VREF_CA_DIMMB M_VREF_DQ_DIMMB

Layout Note: All VREF traces should have width=20mil; spacing=20 mil

30

14,37 DDR3_DRAMRST#

EC1501 1 0D75V_S0

2

DY SCD1U10V2KX-5GP 203 204

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2

3D3V_S0

199 SA1_DIMB

1

SA0_DIMB

1

2 10KR2J-3-GP R1506

1D5V_S3

Close to DIMM1.199

2

0R0402-PAD

1D5V_S3

DY

1 2

1

DY


DY


DY

2

DY

C1508 SC10U6D3V5KX-1GP 2 1

C


2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

R1507

1

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124


2

77 122 125

SA0_DIMB SA1_DIMB


197 201

1

12 29 47 64 137 154 171 188

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

PCH_SMBDATA 14,20,69 PCH_SMBCLK 14,20,69 3D3V_S0

198

1

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

200 202

2

10 27 45 62 135 152 169 186

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

D


M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

NC#1 NC#2 NC#/TEST

M_B_DIMB_CLK_DDR1 6 M_B_DIMB_CLK_DDR#1 6

11 28 46 63 136 153 170 187

C1513

Place these caps close to VTT1 and VTT2.

SA0 SA1

102 104

2

1 2


1 2


1 2

DY


Layout Note:

VDDSPD

6 6

M_B_DIMB_CLK_DDR0 6 M_B_DIMB_CLK_DDR#0 6

SCD1U10V2KX-5GP 2 1

0D75V_S0

SDA SCL EVENT#

M_B_DIMB_CKE0 M_B_DIMB_CKE1

101 103

1

2

1

Place these caps close to VREF_DQ


2

DY


1

2 1 C1515 SCD1U10V2KX-5GP

2

Layout Note: M_VREF_DQ_DIMMB

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

73 74

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

2

R1503 0R0402-PAD

CK1 CK1#

BA0 BA1

6 6


1

DDR_VREF_S3

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

CK0 CK0#

M_B_DIMB_CS#0 M_B_DIMB_CS#1

1

1 2


1 2


1 2


Place these caps close to VREF_CA

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

CKE0 CKE1

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

114 121

2

2

M_VREF_CA_DIMMB

CS0# CS1#

110 113 115


109 108

Layout Note:

C

1

NP1 NP2

1

M_B_BS0 M_B_BS1 M_B_DQ[63:0]

NP1 NP2 RAS# WE# CAS#

2

M_B_BS2

6 6 6

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2


1 R1505 0R0402-PAD

6

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79

1

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

2

M_B_A[15:0]

DDR_VREF_S3

DY

2

DM2 6

D

3

Layout Note: Place these Caps near SO-DIMMA.

B

DDR3-204P-90-GP

62.10017.U81

A

A

M14 DIS


DDR3-SODIMM2 Size A2 Date: 5

4

3

2

Document Number

Rev


Sheet

15

of

A00 105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

16

A00 of

105

5

4

3

2

1

SSID = PCH

D

D

3D3V_S0

L_CTRL_CLK L_CTRL_DATA

L_BKLT_EN LVDS_VDD_EN

LVDS_IBG LVDS_VBG

LVD_VREFH LVD_VREFL

49 LVDSA_CLK# 49 LVDSA_CLK

AK39 AK40

LVDSA_CLK# LVDSA_CLK

49 LVDSA_DATA0# 49 LVDSA_DATA1# 49 LVDSA_DATA2#

AN48 AM47 AK47 AJ48

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

49 LVDSA_DATA0 49 LVDSA_DATA1 49 LVDSA_DATA2

AN47 AM49 AK49 AJ47

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

49 LVDSB_CLK# 49 LVDSB_CLK

AF40 AF39

LVDSB_CLK# LVDSB_CLK

49 LVDSB_DATA0# 49 LVDSB_DATA1# 49 LVDSB_DATA2#

AH45 AH47 AF49 AF45

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

49 LVDSB_DATA0 49 LVDSB_DATA1 49 LVDSB_DATA2

AH43 AH49 AF47 AF43

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

1 2

Layout Note: LVDS signal trace length max 4000mil

AM42 AM40

SDVO_INTN SDVO_INTP

AP39 AP40

RN1706 SRN2K2J-1-GP

N48 P49 T49

CRT_BLUE CRT_GREEN CRT_RED

T39 M40

CRT_DDC_CLK CRT_DDC_DATA

M47 M49

CRT_HSYNC CRT_VSYNC

T43 T42

DAC_IREF CRT_IRTN

Layout Note: Close HDMI port

P38 M39

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

DDPB_AUXN DDPB_AUXP DDPB_HPD

AT49 AT47 AT40

HDMI_PCH_DET

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

HDMI_DATA2_R# 51 HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51

DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

DDPD_CTRLCLK DDPD_CTRLDATA

C

Layout Note:

P46 P42 AP47 AP49 AT38

51

HDMI trace length to DC CAP. max 10000mil

M43 M36

B

CRT_DDCCLK CRT_DDCDATA

R1702 1KR2J-1-GP

DDPD_AUXN DDPD_AUXP DDPD_HPD

AT45 AT43 BH41

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

B

PANTHER-GP-NF

71.0HM76.A0U 2

Place near PCH; trace to trace spacing=30mil

1

DAC_IREF_R

Layout Note:

CRT

2 1

RN1707 SRN2K2J-1-GP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK SDVO_CTRLDATA

3 4

3D3V_S0

AP43 AP45

L_CTRL_CLK L_CTRL_DATA

AE48 AE47

1

R1701 2K37R2F-GP

C

T45 P39

LVD_IBG LVD_VBG

TP1701

Place near PCH; trace to trace spacing=20mil

L_DDC_CLK L_DDC_DATA

AF37 AF36

SRN100KJ-6-GP

Layout Note:

L_BKLTCTL

SDVO_TVCLKINN SDVO_TVCLKINP

2 1

RN1702

3 4

P45 LVDS_DDC_CLK_R T40 LVDS_DDC_DATA_R K47

49 LVDS_DDC_CLK_R 49 LVDS_DDC_DATA_R

2 1

L_BKLTEN L_VDD_EN

Digital Display Interface

49 L_BKLT_CTRL

SRN2K2J-1-GP

J47 M45

LVDS

27 L_BKLT_EN 49 LVDS_VDD_EN

3D3V_S0

4 OF 10

PCH1D L_CTRL_DATA L_CTRL_CLK

4 3

3 4

RN1701

1 2

M14 DIS

A

A


PCH (LVDS/CRT/DDI) Size A3 Date: 5

4

3

2

Document Number

Rev


Sheet 1

17

of

A00 105

5

4

3

2

1

SSID = PCH

BOARD_ID1

20

3D3V_S0

8 7 6 5

RN1804 SRN10KJ-6-GP 1 2 3 4

INT_PIRQD# KB_LED_BL_DET INT_PIRQC# PCH_GPIO04

RN1805 SRN10KJ-6-GP 1 2 3 4

PCH_GPIO52 INT_PIRQB# SATA_ODD_DA# INT_PIRQA#

3D3V_S0

8 7 6 5

Layout Note: Trace Length : PCH ~~9000mil~~Cap~~1000mil~~CONN

USB3.0/2.0 Mapping Table USB 3.0 Port

C

USB3_RX1_N USB3_RX2_N

62 USB3_RX1_N 62 USB3_RX2_N

USB 2.0 port

Port 1

Port 0

Port 2

Port 1

Port 3

Port 2

Port 4

Port 3

USB3_RX1_P USB3_RX2_P

62 USB3_RX1_P 62 USB3_RX2_P 62 USB3_TX1_N 62 USB3_TX2_N

USB3_TX1_N USB3_TX2_N

62 USB3_TX1_P 62 USB3_TX2_P

USB3_TX1_P USB3_TX2_P

SATA1GP/GPIO19

Boot BIOS Location

0

0

0

1

Reserved

1

0

Reserved

1

1

R1808

1

B

TP21 TP22 TP23 TP24

BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30

PIRQA# PIRQB# PIRQC# PIRQD#

PCH_GPIO50 PCH_GPIO52 PCH_GPIO54

C46 C44 E40

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

2 10KR2J-3-GP BBS_BIT1 TP1801 PCH_GPIO53 1 PCI_GNT3#

D47 E42 F46

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

DY

PCH_GPIO02

G42 G40 PCH_GPIO04 C42 KB_LED_BL_DET D44

56 SATA_ODD_DA#

SPI(Default) TP1802

1

PCI_PME# PCI_PLTRST#

Low = A16 swap override/Top-Block Swap Override enabled High = Default

A

AY7 AV7 AU3 BG4

RSVD5 RSVD6

AT10 BC8

RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

RSVD23 RSVD24

AV5 AV10

RSVD25

AT8

Pair

RSVD26 RSVD27

AY5 BA2

0

USB3.0 port2

AT12 BF3

1

USB3.0 port1, with Debug Port

RSVD28 RSVD29

2

USB2.0 port3

3

NC

4

NC

5

Touch Panel

6

HM76 NC

7

HM76 NC

8

NC

9

NC

10

Card reader

11

WLAN

12

NC

13

CAMERA

D

USB Table

USB2.0 Signal Group USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS#

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN4 USB_PP4

1 1

B33

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

A14 K20 B17 C16 L16 A16 D14 C14

TP1803 TP1804

USB_PN10 USB_PP10 USB_PN11 USB_PP11

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

32 32 65 65

1. USBRBIAS/# use 50ohm single-ended impedance spacing to other signal=15mil 2. Length < 500mil

USB_OC#0_1

USB_OC#0_1 61

USB_OC#4_5

USB_OC#4_5 61

OC#

1

R1812 8K2R2J-3-GP 2

3D3V_S5

RN1802 USB_OC#0_1 USB_OC#4_5

1 2

4 3

3D3V_S5

SRN10KJ-5-GP

M14 DIS

A

R1823 1 2 PCI_PLTRST# 0R0402-PAD

1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

C1801 SC220P50V2KX-3GP

Title

PCH (PCI/USB/NVRAM)

2

DY DY

Wistron Corporation

2 4

B

Layout Note:

1 2 R1811 22D6R2F-L1-GP

Size A3 Date:

5

C

1. USB Ext. port 9 (HS) External debug port use on Chief River platform. 2. 2011 July; Microsoft will support USB3.0 debug--> Port1 useable.

PME# PLTRST#

Device

USB_PN13 49 USB_PP13 49

C33 USB_RBIAS

USBRBIAS

62 62 62 62 82 82


71.PANTH.00U

PLT_RST# R1816 100KR2J-1-GP


PANTHER-GP-NF

1

5,27,31,65,71,83

DY EC1804DY EC1805 1

DY

2 22R2J-2-GP CLK_PCI_FB_R H43 2 22R2J-2-GP CLK_PCI_KBC_R J48 K42 H40

SC10P50V2JN-4GP

PCI_GNT#3

EC1802

1

Swap Override jumper

SC4D7P50V2CN-1GP

A16

C6

LPC 2 22R2J-2-GP CLK_PCI_LPC_R H49

1 1 1

2

CLK_PCI_LPC CLK_PCI_FB CLK_PCI_KBC

2

71 20 27

2

R1801 4K7R2J-2-GP

R1807 R1805 R1806

1

DY

K10

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PCI_GNT3#

1

SC4D7P50V2CN-1GP

2

USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4

K40 K38 H38 G38

3D3V_S0

LPC

B21 M20 AY16 BG46

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

Boot Bios Strap GNT1#/GPIO51

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

USB

PCH_GPIO50 PCH_GPIO54 PCH_GPIO02 BOARD_ID1

BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45

RSVD

RN1803 SRN10KJ-6-GP 1 2 3 4

PCI

8 7 6 5

D

5 OF 10

PCH1E

3D3V_S0

3

2

Document Number

Rev

A00

DNE40 14 CR DIS W ednesday, September 05, 2012

Sheet 1

18

of

105

5

4

3

2

1

SSID = PCH 3 OF 10

4 DMI_CPU_TXP_PCH_RXP[3:0]

4 DMI_CPU_RXN_PCH_TXN[3:0]

4 DMI_CPU_RXP_PCH_TXP[3:0]

Layout Note: DMI_ZCOMP keep W=4 mils and routing length less than 500 1D05V_PCH mils. DMI_IRCOMP keep W=4 mils and R1901 1 routing length less than 500 R1902 1 mils.

BC24 BE20 BG18 BG20

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI_CPU_TXP_PCH_RXP0 DMI_CPU_TXP_PCH_RXP1 DMI_CPU_TXP_PCH_RXP2 DMI_CPU_TXP_PCH_RXP3

BE24 BC20 BJ18 BJ20

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI_CPU_RXN_PCH_TXN0 DMI_CPU_RXN_PCH_TXN1 DMI_CPU_RXN_PCH_TXN2 DMI_CPU_RXN_PCH_TXN3

AW24 AW20 BB18 AV18

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI_CPU_RXP_PCH_TXP0 DMI_CPU_RXP_PCH_TXP1 DMI_CPU_RXP_PCH_TXP2 DMI_CPU_RXP_PCH_TXP3

AY24 AY20 AY18 AU18

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

BJ24 2 49D9R2F-GP DMI_COMP_R

BG25

2 750R2F-GP

BH21

RBIAS_CPY

FDI_CPU_TXN_PCH_RXN[7:0]

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

FDI_CPU_TXN_PCH_RXN0 FDI_CPU_TXN_PCH_RXN1 FDI_CPU_TXN_PCH_RXN2 FDI_CPU_TXN_PCH_RXN3 FDI_CPU_TXN_PCH_RXN4 FDI_CPU_TXN_PCH_RXN5 FDI_CPU_TXN_PCH_RXN6 FDI_CPU_TXN_PCH_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

FDI_CPU_TXP_PCH_RXP0 FDI_CPU_TXP_PCH_RXP1 FDI_CPU_TXP_PCH_RXP2 FDI_CPU_TXP_PCH_RXP3 FDI_CPU_TXP_PCH_RXP4 FDI_CPU_TXP_PCH_RXP5 FDI_CPU_TXP_PCH_RXP6 FDI_CPU_TXP_PCH_RXP7

FDI_INT

AW16

FDI_INT

FDI_INT

AV12

FDI_FSYNC0

FDI_FSYNC0

FDI_FSYNC1

BC10

FDI_FSYNC1

FDI_FSYNC1

4

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC0

4

FDI_LSYNC1

BB10

FDI_LSYNC1

FDI_LSYNC1

4

DSWVRMEN

A18

DSW ODVREN

DPWROK

E22

PCH_DPW ROK

WAKE#

B9

PCH_W AKE#

CLKRUN#/GPIO32

N3

PM_CLKRUN#

SUS_STAT#/GPIO61

G8

PM_SUS_STAT#

SUSCLK/GPIO62

N14

SUS_CLK

SLP_S5#/GPIO63

D10

PM_SLP_S5#

SLP_S4#

H4

PM_SLP_S4#

SLP_S3#

F4

PM_SLP_S3#

SLP_A#

G10

PM_SLP_A#

1

TP1903

SLP_SUS#

G16

PM_SLP_SUS#

1

TP1904

PMSYNCH

AP14

H_PM_SYNC

K14

PM_SLP_LAN#

1

TP1905

FDI

D

DMI_CPU_TXN_PCH_RXN0 DMI_CPU_TXN_PCH_RXN1 DMI_CPU_TXN_PCH_RXN2 DMI_CPU_TXN_PCH_RXN3

DMI

PCH1C 4 DMI_CPU_TXN_PCH_RXN[3:0]

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP DMI2RBIAS

4

D

FDI_CPU_TXP_PCH_RXP[7:0]

4

4

DSWODVREN - On Die DSW VR Enable 4

HIGH

Enabled (DEFAULT)

LOW

Disabled

TP1907 R1905 1

5 36

1

SUSACK#

C12

2 10KR2J-3-GP K3

XDP_DBRESET# SYS_PW ROK

1 R1921 2 0R0402-PAD

27,36 S0_PW R_GOOD 45,46,47,93 RUNPW ROK

R1907

1

DY

PW ROK 1 R1916 2 0R0402-PAD 2 0R2J-2-GP

MEPW ROK

R1924 1 2 0R0402-PAD

27 PM_PW RBTN#

B

27,86 AC_PRESENT 27

BATLOW #

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

PM_RSMRST#

C21

RSMRST#

SUS_PW R_ACK

K16

SUSWARN#/SUSPWRDNACK/GPIO30

37 PM_DRAM_PW RGD 27 RSMRST#_KBC

SUSACK#

PM_PW RBTN#

E20

AC_PRESENT

H20

BATLOW #

E10

PM_RI#

A10

PWRBTN# ACPRESENT/GPIO31 BATLOW#/GPIO72 RI#

SLP_LAN#/GPIO29

DSW ODVREN R1911 R1927

1 1

DY

2 10KR2J-3-GP 2 0R0402-PAD

R1917

1

2 330KR2J-L1-GP C

PM_RSMRST#

3D3V_S0

1 R1929 2 0R0402-PAD 1

PM_CLKRUN#

R1919

1

2 8K2R2J-3-GP

TP1901 TPAD14-OP-GP

1 R1925 2 0R0402-PAD 1

PM_CLKRUN#_EC 27

PCH_SUSCLK_KBC

27

PCH_SUSCLK_KBC

TP1902 TPAD14-OP-GP

2

3D3V_S0

EC1901 SC4D7P50V2CN-1GP

PM_SLP_S4# 27,46

DY 1

C

System Power Management

RTC_AUX_S5 RTC_AUX_S5

PM_SLP_S3# 27,36,37,47

B

H_PM_SYNC

5

PANTHER-GP-NF

Sequence: S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

71.PANTH.00U

3D3V_S5 SYS_PW ROK

S0_PW R_GOOD

RUNPW ROK

DY


DY

2

DY


1


2

1

BATLOW # PM_RI# SUS_PW R_ACK PCH_W AKE#

2

1 2 3 4

1

RN1901

8 7 6 5

SRN10KJ-6-GP

PM_DRAM_PW RGD

1

A

2

R1926 R1904

1 1

DY

2

R1908

1 10KR2J-3-GP PM_RSMRST#

DY

RSMRST#_KBC


DY


AC_PRESENT

1

2 100KR2J-1-GP AC_PRESENT 1 10KR2J-3-GP PM_SLP_LAN#

M14 DIS


Wistron Corporation

DY


2 100KR2J-1-GP SYS_PW ROK 2 100KR2J-1-GP PW ROK

Title

PCH (DM I/FDI/PM)


Size A3 Date:

5

A

2

DY

1

1 2

2

R1909 R1920

4

3

2

Document Number

Rev

A00


Sheet 1

19

of

105

5

4

SSID = PCH

3

2

S5 power rail CLKREQ#: PCIECLKRQ[0]# PCIECLKRQ[7:3]#

3D3V_S5

1

3D3V_S5 SMB_CLK SMB_DATA

4 3

1 RN2003 2 SRN2K2J-1-GP

SML0_DATA SML0_CLK SML1_CLK SML1_DATA

1 2 3 4

8 RN2004 7 SRN2K2J-2-GP 6 5

RN2001

C

PCH_RXN_C_LAN_TXN6 PCH_RXP_C_LAN_TXP6 LAN_RXN_C_PCH_TXN6 LAN_RXP_C_PCH_TXP6

C2001 1 C2002 1

2 SCD1U10V2KX-5GP PCH_TXN_LAN_RXN6 2 SCD1U10V2KX-5GP PCH_TXP_LAN_RXP6

Layout Note: Layout trace < 14000mil

3D3V_S0

S0 power rail CLKREQ#: PCIECLKRQ[2:1]# 4 3

CLK_PCIE_W LAN_REQ# CLK_PCIE_REQ1#

PERN5 PERP5 PETN5 PETP5

BJ38 BG38 AU36 AV36


BG40 BJ40 AY40 BB40


BE38 BC38 AW38 AY38


PCIE_CLK_RQ2# PCIE_CLK_RQ1# PCIE_CLK_REQ0#

NC NC WLAN NC LAN NC NC

CLKOUT_PCIE0N CLKOUT_PCIE0P

J2

65 CLK_PCIE_W LAN# 65 CLK_PCIE_W LAN

CLK_PCH_SRC2_N CLK_PCH_SRC2_P


M1


Layout Note:

PCIE_CLK_REQ3#

CLKOUT termination place close to PCH <500mil

31 CLK_PCIE_LAN# 31 CLK_PCIE_LAN

R1923 1 2 R1928 10R0402-PAD 2 0R0402-PAD


A8


PCIE_CLK_REQ4#

L12

PCIECLKRQ4#/GPIO26

CLK_PCH_SRC5_N CLK_PCH_SRC5_P

V45 V46


L14

31 PCIE_CLK_LAN_REQ#

CLK_PEG_B_REQ#

Layout Note:

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

E6

PCH_GPIO74 SML1_CLK

SML1DATA/GPIO75

M16

SML1_DATA

CLK_PCIE_REQ7#

CL_DATA1

T11

CL_RST1#

P10

3D3V_S0

2 1

Layout Note:

3 4

NC


T13

PCIECLKRQ6#/GPIO45

V38 V37


K12

PCIECLKRQ7#/GPIO46 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

SMB_DATA

SML1_DATA 27,28,86

AB37 AB38

CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_DMI_N CLKOUT_DMI_P

AV22 AU22

CLKOUT_DP_N CLKOUT_DP_P

AM12 AM13

WLAN CLK

BF18 BE18

CLKIN_DMI_N CLKIN_DMI_P

1

5

2

4

3

PCH_SMBDATA 14,15,69

PCH_SMBCLK 14,15,69 SMB_CLK C

XTAL25_IN

CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_DMI_N CLKOUT_DMI_P

1 2

4 3

OPS

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

SRN0J-6-GP R1930 1 2 R1931 10R0402-PAD 2 0R0402-PAD

2

3

C2008 SC15P50V2JN-2-GP


XTAL-25MHZ-155-GP1

2

82.30020.D41 2nd = 82.30020.G61 3D3V_S0

CLK_BUF_EXP_N CLK_BUF_EXP_P

2 RN2019 1 SRN10KJ-5-GP

3D3V_S5

3 4 3 4

CLKIN_DOT_96N CLKIN_DOT_96P

G24 E24

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

2 RN2020 1 SRN10KJ-5-GP

3 4

CLKIN_SATA_N CLKIN_SATA_P

AK7 AK5

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

2 RN2021 1 SRN10KJ-5-GP

3 4

REFCLK14IN

K45

CLK_BUF_REF14

XTAL25_IN XTAL25_OUT

NC

4

XTAL25_OUT

CLK_EXP_N 5 CLK_EXP_P 5

2 RN2008 1 SRN10KJ-5-GP

CLKIN_PCILOOPBACK

1

2

R2006 1M1R2J-GP

H45

CLK_PCI_FB

V47 V49

XTAL25_IN XTAL25_OUT

R2008 1 10KR2J-3-GP CLK_PCI_FB

R2014 10KR2J-3-GP OPS

R2004 10KR2J-3-GP

PEG_CLKREQ#

LAN CLK

1

X2001

PEG_CLKREQ# 83

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

NC

84.2N702.A3F 2nd = 84.DM601.03F 3rd = 84.2N702.E3F 4th = 84.2N702.F3F

Q2001 2N7002KDW -GP

BJ30 BG30

CLKIN_GND1_N CLKIN_GND1_P

NC

22

R2010

UMA 10KR2J-3-GP

2

Layout Note:

18

B

BOARD_ID2

BIOS UMA/DIS Strap pin

1500mil < Layout trace < 10000mil BOARD_ID2

BOARD_ID1 PX(AMD)

0

0

DIS

0

1

UMA

1

0

1

1

R2007

Y47 XCLK_RCOMP

1

2

+VCCDIFFCLKN

90D9R2F-1-GP

NC NC

6

RN2016

XCLK_RCOMP

V40 V42

SRN2K2J-1-GP

SML1_CLK 27,28,86

M10

NC

D

1KR2J-1-GP

RN2007

PEG_B_CLKRQ#/GPIO56

AK14 AK13

37

10KR2J-3-GP

Layout Note:

FLEX CLOCKS

A

DRAMRST_CNTRL_PCH

2

M7

CL_CLK1

Layout trace < 14000mil

PCIE_CLK_REQ6#

SML0_DATA

E14

PCIECLKRQ5#/GPIO44

AB42 AB40

G12

C13

PCIECLKRQ3#/GPIO25

Y43 Y45

SML0_CLK

SML1CLK/GPIO58

PCIECLKRQ2#/GPIO20

Y37 Y36 B

DRAMRST_CNTRL_PCH

C8

SML1ALERT#/PCHHOT#/GPIO74

PCIECLKRQ1#/GPIO18

AA48 AA47 V10

65 CLK_PCIE_W LAN_REQ#

SML0DATA

A12

2

CLKOUT termination place close to PCH <500mil

PCIECLKRQ0#/GPIO73

AB49 AB47

R1918 1 2 R1922 10R0402-PAD 2 0R0402-PAD

SML0CLK

R2011 1

DRAMRST_CNTRL_PCH 1 R2009

Can Place Far away PCH

SRN10KJ-5-GP

CLK_PCIE_REQ1#

SML0ALERT#/GPIO60

PEG_A_CLKRQ#/GPIO47

Y40 Y39

RN2018

1 2

BG37 BH37 AY36 BB36

PCH_GPIO74

1

31 31 31 31


SMB_DATA

27

2

BF36 BE36 AY34 BB34

C9

SMBDATA

EC_SW I#

1


SMB_CLK

2

PCIE_TXN3_C PCIE_TXP3_C

EC_SW I#

H14

2

2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP

BG36 BJ36 AV34 AU34

E12

SMBCLK

1

C2005 1 C2006 1


SMBALERT#/GPIO11

1

PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3

BE34 BF34 BB32 AY32

NC

2

SRN10KJ-6-GP 65 65 65 65


Link

PCIE_CLK_RQ5# PCIE_CLK_RQ7#

BG34 BJ34 AV32 AU32

SMBUS

8 7 6 5

2 OF 10

PCH1B

Controller

EC_SW I# PCIE_CLK_LAN_REQ# CLK_PCIE_REQ7# CLK_PEG_B_REQ#

PCIE_CLK_RQ6# PCIE_CLK_RQ3# PCIE_CLK_RQ0# PCIE_CLK_RQ4#

CLOCKS

SRN10KJ-6-GP RN2002 1 2 3 4

D

PCIE_CLK_REQ6# PCIE_CLK_REQ3# PCIE_CLK_REQ0# PCIE_CLK_REQ4#

8 7 6 5

PCI-E*

1 2 3 4

CLKOUTFLEX0/GPIO64

K43 JTAG_TCK

CLKOUTFLEX1/GPIO65

F47

CLKOUTFLEX2/GPIO66

H47 CLK_27M_VGA_R

CLKOUTFLEX3/GPIO67

K49 BOARD_ID1

CARD_READER_48M

1

TP2004

1

TP2005

1

TP2006

Optimus(NV) M14 DIS

BOARD_ID1

A

Wistron Corporation

18


PANTHER-GP-NF Title

71.PANTH.00U

PCH (PCI-E/SMBUS/CLOCK/CL) Size A3 Date:

5

4

3

2

Document Number

Rev


Sheet 1

20

of

A00 105

5

4

3

2

1

SSID = PCH RTC_AUX_S5

220KR2F-L-GP 220KR2F-L-GP

D20

RTCRST#

SRTC_RST#

G22

SRTCRST#

RTC_AUX_S5

K22

INTRUDER#

PCH_INTVRMEN

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

R2105 330KR2J-L1-GP 1 HDA_BITCLK

2

R2126 33R2J-2-GP

S

SM_INTRUDER#

HDA_SYNC

T10

SPKR

K34

HDA_RST#

29 HDA_SDIN0

E34

HDA_SDIN0

Layout Note: Place close together.

G34

HDA_SDIN1

C34

HDA_SDIN2

2

29 HDA_SPKR

2

C

R2123 33R2J-2-GP 2 1

29 HDA_CODEC_SDOUT

1

27 ME_UNLOCK

R2107 1KR2J-1-GP

3D3V_S5

Flash Descriptor Security Overide/ Intel ME Debug Mode Low = Default * HDA_SDOUT High = Enable

R2111

1

R2118

1

R2119

1

R2120

1

Place at the separated point 3D3V_S0 R2106 1

DY

2 1KR2J-1-GP

HDA_RST#

R2125 33R2J-2-GP

Layout Note: HDA_SDO and HDA_BCLK must be length matched to within 500 mils

Layout Note:

1

DY DY DY DY

2

HDA_SDOUT

A34

HDA_SDIN3

LPC

RTC_RST#

A36

HDA_SDO

TP2101

1PCH_GPIO33

C36

HDA_DOCK_EN#/GPIO33

TP2102

1PCH_GPIO13

N32

HDA_DOCK_RST#/GPIO13

27,60 SPI_CS0#_R

R2103 1

1KR2J-1-GP

2

HDA_SYNC

27,60 SPI_SO_R

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

AM3 AM1 AP7 AP5


AM10 AM8 AP11 AP10


AD7 AD5 AH5 AH4


AB8 AB10 AF3 AF1


Y7 Y5 AD3 AD1 Y3 Y1 AB3 AB1

J3

JTAG_TCK

H7

JTAG_TMS

SATAICOMPO

Y11

2 210R2F-L-GP

PCH_JTAG_TDI

K5

JTAG_TDI

SATAICOMPI

Y10

2 210R2F-L-GP

PCH_JTAG_TDO

H1

JTAG_TDO

1 R2110 1 R2115

2 PCH_SPI_SI 33R2J-2-GP 2 PCH_SPI_SO 33R2J-2-GP

PLL ODVR VOLTAGE

T3

27

PCH_RXN_C_HDD_TXN0 56 PCH_RXP_C_HDD_TXP0 56 PCH_TXN_HDD_RXN0 56 PCH_TXP_HDD_RXP0 56

C

PCH_RXN_C_ODD_TXN4 56 PCH_RXP_C_ODD_TXP4 56 PCH_TXN_ODD_RXN4 56 PCH_TXP_ODD_RXP4 56

ODD

Layout Note: HDD < 6000mil, mSATA < 6000mil, ODD < 12500mil 1D05V_PCH R2112

2 37D4R2F-GP

1

1D05V_PCH

AB12

SATA3COMPI

AB13

SATA3_COMP R2113

1

2 49D9R2F-GP

SATA3RBIAS

AH1

RBIAS_SATA3 R2114

1

2 750R2F-GP

T1

SPI_CS1# SPI_MOSI

SATALED# SATA0GP/GPIO21

SPI_MISO

SATA1GP/GPIO19

P3

SATA_LED#

V14

PCH_GPIO21

P1

BBS_BIT0

Layout Note:

SATA_LED# 68

Place close PCH(<500mil) 3D3V_S0

R2116

1

DY

2 10KR2J-3-GP

PANTHER-GP-NF

71.PANTH.00U

*

HDD1

B

SPI_CS0#

U3

27,71

LPC_FRAME# 27,71

SATA3RCOMPO

SPI_CLK

Y14

V4

LPC_AD[3..0]

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

1 R2136 2 0R0402-PAD

SATA_COMP

3D3V_S0

36,37 RUN_ENABLE

RN2103 INT_SERIRQ PCH_GPIO21

G

Low = 1.8V HDA_SYNC High = 1.5V

INT_SERIRQ

PCH_JTAG_TMS

+3VS_+1.5VS_HDA_IO 27,60 SPI_SI_R

KB_DET# 69

V5

PCH_JTAG_TCK_BUF

PCH_SPI_CLK 33R2J-2-GP 2 PCH_SPI_CS0# 33R2J-2-GP

RN2101 SRN0J-7-GP 8 7 6 5

LDRQ0# LDRQ1#/GPIO23

2 210R2F-L-GP

2

1 2 3 4

E36 K36

2 51R2J-2-GP

1 R2108 1 R2109

LPC_LAD0_PCH LPC_LAD1_PCH LPC_LAD2_PCH LPC_LAD3_PCH

D36 LPC_LFRAME#_PCH


No Reboot Strap 27,60 SPI_CLK_R

C38 A38 B37 C37

FWH4/LFRAME#

SERIRQ

HDA_SPKR

Low = Default * HDA_SPKR High = No Reboot

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

SATA 6G

RTCX2

SATA

C20

RTC

RTCX1

RTC_X2

D

LPC_AD[3..0]

1 OF 10

IHDA

1

2 1 1M1R2J-GP 1 2

29 HDA_CODEC_RST#

B

A20

R2104

29 HDA_CODEC_BITCLK

R2122 10KR2J-3-GP

RTC_X1

SPI

RTCRST_ON

Place near PCH

JTAG

SC1U6D3V2KX-GP Q2102 2N7002BK-GP

G

Layout Note: PCH1A

1

27


Low = External VRs High = Internal VRs*

INTVRMEN

2

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

D

D

1

Integrated SUS 1V VRM Enable C2104

2

R2127 1 R2128 1

SPI_CLK_R

1 2

HDA_CODEC_RST#

4 3 SRN10KJ-5-GP

D

HDA_SYNC

R2117 1M1R2J-GP

Q2101 2N7002BK-GP

EC2104

DY SC10P50V2JN-4GP DY

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

1

1

S


RTC_X1

2

33R2J-2-GP

HDA_CODEC_SYNC_R

1

1

2

2

2

R2124 29 HDA_CODEC_SYNC

R2101

1

2 10MR2J-L-GP

RTC_X2

X2101 HDA_CODEC_BITCLK

HDA_CODEC_SDOUT

1

4 M14 DIS


3 X-32D768KHZ-65-GP

Wistron Corporation


21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

PCH (SPI/RTC/LPC/SATA/IHDA)

82.30001.A41 2nd = 82.30001.841

Size A3 Date:

5

4

A

1

2

2

1

1

EC2103 DY EC2102 SC4D7P50V2CN-1GP DY SC4D7P50V2CN-1GP

C2101 SC15P50V2JN-2-GP 2 1

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

2

2

A

3

2

Document Number

Rev


Sheet 1

21

of

A00 105

5

4

3

2

1

SSID = PCH 6 OF 10

BMBUSY#/GPIO0

TACH4/GPIO68

C40

SATA_ODD_PW RGT

EC_SMI#

A42

TACH1/GPIO1

TACH5/GPIO69

B41

BOARD_ID2

PCH_GPIO6

H36

TACH2/GPIO6

TACH6/GPIO70

C41

PCH_GPIO70

1

TP2201 TPAD14-OP-GP

EC_SCI#

E38

TACH3/GPIO7

TACH7/GPIO71

A40

PCH_GPIO71

1

TP2202 TPAD14-OP-GP

PCH_GPIO08

C10

GPIO8

P4

H_A20GATE_PCH

AU16

H_PECI_R

P5

H_RCIN#

PROCPWRGD

AY11

H_CPUPW RGD

THRMTRIP#

AY10

PCH_THERMTRIP_R

INIT3_3V#

T14

INIT3_3V#

DF_TVS

AY1

DF_TVS

TS_VSS1

AH8

TS_VSS2

AK11

TS_VSS3

AH10

TS_VSS4

AK10

3D3V_S0 27

EC_SCI#

H_A20GATE_PCH H_RCIN# 60

RTC_DET#

3D3V_S0

DBC_EN

TPAD14-OP-GP TP2209

1

TPAD14-OP-GP TP2210

EC_SMI# EC_SCI# PCH_GPIO6 DGPU_PW ROK

1

E8

GPIO24

E16

GPIO27

PLL_ODVR_EN

P8

GPIO28

PCH_GPIO34

K1

STP_PCI#/GPIO34

PCH_GPIO35

K4

GPIO35

PCH_GPIO36

V8

SATA2GP/GPIO36

PCH_GPIO37

M5

SATA3GP/GPIO37

PCH_GPIO38

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

DGPU_PW R_EN# PCH_GPIO49

V3

SATA5GP/GPIO49/TEMP_ALERT#

VRAM_DET

D6

GPIO57

R2210 10KR2J-3-GP

2

VRAM_2G 2

RTC_DET# 10KR2J-3-GP

RN2207

4 3

PCH_GPIO24 PCH_GPIO08

1 2

DY

SRN10KJ-5-GP

B

R2201

2

DY

PCH_GPIO15 1 1KR2J-1-GP

A4

VSS_NCTF_1#A4

A44

VSS_NCTF_2#A44

A45

VSS_NCTF_3#A45

A46

1 2

H_RCIN#

1

R2202

5

R2209

P37

VSS_NCTF_15#BG2

BG2

PCH_NCTF_BG2

1

TP2203 TPAD14-OP-GP

VSS_NCTF_16#BG48

BG48

PCH_NCTF_BG48

1

TP2204 TPAD14-OP-GP

VSS_NCTF_17#BH3

BH3

PCH_NCTF_BH3

1

TP2205 TPAD14-OP-GP

VSS_NCTF_18#BH47

BH47

PCH_NCTF_BH47

1

TP2206 TPAD14-OP-GP

BJ5

A6

VSS_NCTF_6#A6

VSS_NCTF_24#BJ6

BJ6

VSS_NCTF_25#C2

C2

PCH_NCTF_C2

1

TP2207 TPAD14-OP-GP

VSS_NCTF_26#C48

C48

PCH_NCTF_C48

1

TP2208 TPAD14-OP-GP

VSS_NCTF_27#D1

D1

VSS_NCTF_28#D49

D49

VSS_NCTF_9#BD1 VSS_NCTF_10#BD49

BE1

VSS_NCTF_11#BE1

BE49

VSS_NCTF_12#BE49

VSS_NCTF_29#E1

E1

VSS_NCTF_30#E49

E49

BF1

VSS_NCTF_13#BF1

VSS_NCTF_31#F1

F1

BF49

VSS_NCTF_14#BF49

VSS_NCTF_32#F49

F49

2 1KR2J-1-GP

H_SNB_IVB#

5

C

Check these fuor balls are connected firstly, then to GND

NC_1

BJ46

VSS_NCTF_8#B47

1

Layout Note:

VSS_NCTF_23#BJ5

B47

H_THERMTRIP# 5

DF_TVS

VSS_NCTF_5#A5

PCH_NCTF_B47

2 2K2R2J-2-GP

DY

R2207 2K2R2J-2-GP

A5

1

1

1D8V_S0

BJ45

TPAD14-OP-GP TP2212

VCCP_CPU

TP2213 TPAD14-OP-GP

1

VSS_NCTF_22#BJ46

VSS_NCTF_7#B3

5,27

2 390R2J-1-GP

VSS_NCTF_4#A46

B3

H_PECI

27

H_CPUPW RGD R2204

H_A20GATE 27

DY

BJ44

PCH_NCTF_B3

DGPU_PW R_EN# DGPU_HOLD_RST#

4 3

1 R2205 2 0R0402-PAD 1 2 0R2J-2-GP

VSS_NCTF_21#BJ45

1

DGPU_PW R_EN# DGPU_HOLD_RST#

R2203

D

VSS_NCTF_20#BJ44

BD49 RN2208 SRN10KJ-5-GP 1 DY 2

BOARD_ID2 20

BJ4

TPAD14-OP-GP TP2211

3D3V_S0

SATA_ODD_PW RGT 56

VSS_NCTF_19#BJ4

BD1

4 3

TACH0/GPIO17

PCH_GPIO24

DGPU_HOLD_RST#

R2208 10KR2J-3-GP 2 1

D40

SCLOCK/GPIO22

93 DGPU_PW R_EN#

VRAM_1G_UMA

R2206 1

SATA4GP/GPIO16

T5

83 DGPU_HOLD_RST#

3D3V_S5 3D3V_S5

PECI

1

1 2 3 4

RN2201 SRN10KJ-6-GP 8 7 6 5

U2

A20GATE

DBC_EN

PCH_GPIO27

PCH_GPIO49 PCH_GPIO34 PCH_GPIO38 DBC_EN

3D3V_S0 C

GPIO15

DGPU_PW ROK

27,92,93 DGPU_PW ROK

3D3V_S0 RN2206 SRN10KJ-6-GP 8 7 6 5

G2

RCIN#

49

1 2 3 4

LAN_PHY_PWR_CTRL/GPIO12

PCH_GPIO15 SATA_ODD_PRSNT#

56 SATA_ODD_PRSNT# SATA_ODD_PRSNT# PCH_GPIO00

C4

CPU/MISC

RN2205 SRN10KJ-5-GP 1 4 2 3

RTC_DET#

GPIO

RN2203 SRN10KJ-5-GP 4 3

NCTF

1 2

NCTF TEST PIN: A4,A44,A45,A46,A5,A6,B3,B47, BD1,BD49,BE1,BE49,BF1,BF49, BG2,BG48,BH3,BH47,BJ4,BJ44, BJ45,BJ46,BJ5,BJ6,C2,C48,D1, D49,E1,E49,F1,F49

D

EC_SMI#

1

27

T7

2

PCH1F PCH_GPIO00

B

PANTHER-GP-NF

RN2209 SRN10KJ-5-GP

71.PANTH.00U RN2202 SRN10KJ-5-GP 1 4 2 3

R2212

2

DY

1

PCH_GPIO36 PCH_GPIO37

PLL_ODVR_EN 1KR2J-1-GP M14 DIS

A

A


PLL ON DIE VR ENABLE Title

Weakly internal pull up 20k. High - Enable LOW - Disable

GPIO28 (PLL_ODVR_EN)

PCH (GPIO/CPU) Size A3 Date:

5

4

3

2

Document Number

Rev


Sheet 1

22

of

A00 105

5

4

3

2

1

SSID = PCH

VCCIO16 VCCIO17

AN26

VCCIO18

AN27

VCCIO19

AP21

VCCIO20

AP23

VCCIO21

AP24

VCCIO22

AP26

VCCIO23

AT24

VCCIO24

AN33

VCCIO25

VCC3_3_6

VCC3_3_7

VCCVRM3

VCCDMI1

V34

BG6

VCCAFDIPLL

3D3V_S0

R2307 0R0402-PAD 1 2

1D5V_S0

R2306 0R0402-PAD 1 2

VCCP_CPU

0.047A

1D05V_PCH

0.075A

R2308 0R0402-PAD 1 2

SCD1U10V2KX-5GP

1

1

0.147A

AT20

0.002

V5REF

5

0.001

V5REF_Sus

5

0.001

Vcc3_3

3.3

0.178

VccADAC

3.3

0.063

VccADPLLA

1.05

0.075

VccADPLLB

1.05

0.075

VccCore

1.05

1.73

VccDMI

1.1

0.047

VccIO

1.05

3.799

VccASW

1.05

0.803

VccSPI

3.3

0.01

VccDSW3_3

3.3

0.001

VccDFTERM

1.8

0.002

VccRTC

3.3

6uA

VccSus3_3

3.3

0.065

VccSusHDA

3.3

0.01

VccVRM

1.5

0.147

VccClkDMI

1.05

0.075

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.05

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.04

D

C

Refer to chipset EDS V.1.8

VCCCLKDMI

AB36


VCCDFTERM1

AG16

VCCDFTERM2

AG17

VCCDFTERM3

AJ16

VCCDFTERM4

AJ17

check


1D8V_S0

0.002A

B


2

1D05V_PCH

R2301 0R0603-PAD 1 2

Iccmax(A)

AP17

VCCIO27

AU20

VCCDMI2

1D05VS_VCC_DMI

VCCSPI

V1

3D3V_S5

0.01A 1

1VCCFDIPLL

FDI

TP2302

1D8V_S0


AT16

1

VCCVRM2

DFT / SPI

AP16

2

V33

+1.05VS_VCC_DMI_CCI

VCCVRM

3D3V_S0

R2304 0R0603-PAD 1 2

0.178A

1D05VS_VCC_DMI

1

VCC3_3_3

0.04A

VCCVRM

VCCIO26

BH29

C2318 SC10U6D3V3MX-GP

AP37

0.001A

2

VCCTX_LVDS4


AP36

1

VCCTX_LVDS3

+1.8VS_VCCTX_LVDS

2

AM38

SCD01U16V2KX-3GP

1

CRT

2

VCCTX_LVDS2

1

AM37

1

VCCIO15

AN17

2


B

VCCTX_LVDS1

2

0.178A

VSSALVDS

AK37

+3VS_VCCA_LVDS

C2314

2

AN16

AN34

3D3V_S0

VCCALVDS

AK36

VCCAPLLEXP

VCCIO

1 2


1


2

1 2

DY


1


2

1


2

DY

C2313

DY


BJ22

AN21

3.799A

U47

VCCIO28

C

1D05V_PCH

VSSADAC

0.063A

1.05/1.0

1

VCCAPLLEXP

1

U48

2

TP2301

VCCADAC

2

AN19

3D3V_S0

7 OF 10

Voltage(V)

V_PROC_IO

1

1D05V_PCH

VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE17

LVDS

1 2


1


2

1 2

DY


1 2

DY


D

AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31

HVCMOS

1.73A

DMI

1D05V_PCH

POWER

VCC CORE

PCH1G

Voltage Rail

PANTHER-GP-NF

2

71.PANTH.00U


M14 DIS

A

A


PCH (POWER1) Size A3 Date: 5

4

3

2

Document Number

Rev


Sheet 1

23

of

A00 105

3

1

+VCCSUS1

VCCAPLLDMI2

AL29

VCCIO14

AL24

DCPSUS3

L2403 1 2 IND-10UH-218-GP

0.075A 1 C2410 SC1U6D3V2KX-GP

+VCCRTCEXT

1

2

SC10U6D3V3MX-GP

DY

C2409

2

1

+1.05VS_VCCA_B_DPL

68.10050.10Y 2nd = 68.1001E.10N

1D05V_PCH

R2412 0R0603-PAD 1 2

0.147A VCCVRM

T26

V5REF_SUS

M26

+5VA_PCH_VCC5REFSUS

DCPSUS4

AN23

+VCCA_USBSUS

VCCASW5

AA29

VCCASW6

VCCSUS3_3_1

AN24

AA31

VCCASW7

AC26

VCCASW8

AC27

VCCASW9

AC29

VCCASW10

AC31

VCCASW11 VCCASW12

AD31

VCCASW13

W21

VCCASW14

W23

VCCASW15

W24

VCCASW16

W26

VCCASW17

W29

VCCASW18

W31

VCCASW19

W33

VCCASW20

BF47

+VCCDIFFCLK

2

2

0.001A

3D3V_S5

C2437 SC1U10V2KX-1GP

DY

V5REF

P34

VCCSUS3_3_2

N20

VCCSUS3_3_3

N22

VCCSUS3_3_4

P20

VCCSUS3_3_5

P22

0.001A

+5VS_PCH_VCC5REF

VCC3_3_1

AA16

VCC3_3_8

W16

VCC3_3_4

T34

VCC3_3_2

3D3V_S0


VCCIO5 VCCIO12

AH13

VCCIO13

AH14

VCCIO6

AF14

DCPRTC VCCVRM4



3D3V_S0

1D05V_PCH

VCCADPLLA VCCADPLLB

AG33

VCCIO7 VCCDIFFCLKN1 VCCDIFFCLKN2 VCCDIFFCLKN3 VCCSSC

VCCAPLLSATA


DY

AK1 +V1.05S_VCCAPLL_SATA3

VCCVRM1

AF11

VCCIO2

AC16

VCCIO3

AC17

VCCIO4

AD17

1

TP2406

VCCVRM

1D05V_PCH

T17 V19

DCPSUS1 DCPSUS2

DCPSUS

4

VCCRTC PANTHER-GP-NF

HDA

A22

V_PROC_IO

CPU

BJ8

RTC

2

1


1

DY


1 C2436 SC1U6D3V2KX-GP

2

1 5

2

6uA

+V1.05S_SSCVCC C2413 SC1U6D3V2KX-GP

2

RTC_AUX_S5

1

0.095A

C2417 SC4D7U6D3V3KX-GP

2

R2404 0R0402-PAD 1 2

2

1D05V_PCH


2

2

A

1

+VCCDIFFCLK

1

0.002A


R2403 0R0402-PAD 1 2

1

1D05V_PCH


VCCP_CPU

T21

VCCASW23

V21

VCCASW21

T19

VCCSUSHDA

P32


71.PANTH.00U

+3VS_+1.5VS_HDA_IO

0.01A

C

R2402 0R0402-PAD 1 2

3D3V_S5

M14 DIS

Voltage Rail

Voltage(V)

V_PROC_IO

1.05/1.0

Iccmax(A) 0.002

V5REF

5

0.001

V5REF_Sus

5

0.001

Vcc3_3

3.3

0.178

VccADAC

3.3

0.063

VccADPLLA

1.05

0.075

VccADPLLB

1.05

0.075

VccCore

1.05

1.73

VccDMI

1.1

0.047

VccIO

1.05

3.799

VccASW

1.05

0.803

VccSPI

3.3

0.01

VccDSW3_3

3.3

0.001

VccDFTERM

1.8

0.002

VccRTC

3.3

6uA

VccSus3_3

3.3

0.065

VccSusHDA

3.3

0.01

VccVRM

1.5

0.147

VccClkDMI

1.05

0.075

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.05

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.04

B

Refer to chipset EDS V.1.8

A

Wistron Corporation

1

1

VCCASW22

MISC

2

TP2405


1D05V_PCH

2

DCPSST



2

V16

1

+VCCSST C2415 SCD1U10V2KX-5GP

2

10R2J-2-GP

3D3V_S0

AJ2 AF13

R2407

1 3D3V_S5


5V_S0

D2402 CH751H-40PT-GP

83.R0304.A8F 2nd = 83.R2004.B8F

1

+V1.05S_SSCVCC

AF17 AF33 AF34 AG34



1D05V_PCH

1 BD47

+1.05VS_VCCA_B_DPL

2

10R2J-2-GP

3D3V_S0

+VCCDIFFCLKN


VCCIO34

(0.1uFx1)

2

VCCASW4

AA27

Y49

P24

3D3V_S5

2

AA26

+1.05VS_VCCA_A_DPL

1

0.05A

VCCASW3

N16

VCCSUS3_3_6

R2408

1

2


B

AA24

AD29


VCCSUS3_3_10

V24


83.R0304.A8F 2nd = 83.R2004.B8F


1

2

DY

2


68.10050.10Y 2nd = 68.1001E.10N

1

1

+1.05VS_VCCA_A_DPL

VCCASW2

SATA

L2402 1 2 IND-10UH-218-GP

VCCSUS3_3_9

V23

1

0.075A

T24

2

1D05V_PCH

VCCASW1

AA21

PCI/GPIO/LPC

C

AA19

Clock and Miscellaneous

1 2

1 2

1 2

1 2

1 2

DY

SC1U6D3V2KX-GP C2419

DY





DY

VCCSUS3_3_8

1

1D05V_PCH

0.803A

VCCSUS3_3_7

D

0.065A

1

BH23

5V_S5

1

TP2404

+VCCAPLL_CPY_PCH

T23

3D3V_S5 3D3V_S5

2

1

T29

1

TP2403

T27

VCCIO33 VCC3_3_5

1D05V_PCH C2402 SC1U6D3V2KX-GP

VCCIO32

2

DCPSUSBYP


1

T38

P28

1

+V3.3S_VCC_CLKF33

V12

P26

VCCIO31

2

DCPSUSBYP

VCCIO30

1

2

DY

1

N26

VCCDSW3_3

USB

1


2

68.10050.10Y 2nd = 68.1001E.10N

1

+V3.3S_VCC_CLKF33

1 2 IND-10UH-218-GP

TP2402

1D05V_PCH

10 OF 10

VCCIO29

2

1 C2416 SCD1U10V2KX-5GP

L2401

2

3D3V_S0

T16

POWER

VCCACLK

1

0.001A 3D3V_S5

D

AD49

2

VCCACLK

2

1

1

TP2401

2

PCH1J 3D3V_S5

1

1

SSID = PCH

2

2

4

2

5

Title

VCCSUSHDA need to be at either 3.3V or 1.5V. All the CODEC I/O Voltages need to be at the same level either 3.3 V or 1.5 V.

PCH (POWER2) Size A3 Date:

3

2

Document Number

Rev

A00


Sheet 1

24

of

105

5

4

3

2

1

SSID = PCH PCH1I

D

PCH1H

H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3

C

B

8 OF 10

VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79

VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

PANTHER-GP-NF

71.PANTH.00U A

AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3

VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258

9 OF 10

VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS328 VSS329 VSS330 VSS331 VSS333 VSS334 VSS335 VSS337 VSS338 VSS340 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

D

C

B

M14 DIS

A


PANTHER-GP-NF

PCH (VSS)

71.PANTH.00U

Size A3 Date:

5

4

3

2

Document Number

Rev


Sheet 1

25

of

A00 105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


Reserved Size A3 Date: 5

4

3

2

Document Number

Rev



Sheet 1

26

A00 of

105

3

C2714

EC_AGND

PSID_EC

1

TP2720

R2737 100KR2J-1-GP 28 40

2

Ins

SERIES_ID

SERIES_ID VGA_THRM USBCHARGER_CB0 MODEL_ID_DET

97 98 99 100 108 96 95 94 101 105 106 107

FAN1_DAC AD_IA_HW

VREF

GPIO94/DA0 GPIO95/DA1 GPIO96/DA2 GPIO97/DA3

7 2 3 1 128 127 126 125 8 9 29 124 121 122

PLT_RST#_EC 1 R2778 2 0R0402-PAD CLK_PCI_KBC LPC_FRAME#

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

2

PLT_RST# 5,18,31,65,71,83 18 21,71 LPC_AD[3..0]

INT_SERIRQ 21 PM_CLKRUN#_EC 1 R2761 2 0R0402-PAD

PANEL_BLEN ECSCI#_KBC

100.0K

33.0K

2.48V

A00

100.0K

47.0K

2.24V

Reserved

100.0K

64.9K

2.0V

Reserved

100.0K

76.8

1.87V

Reserved

100.0K

100.0K

1.65V

Reserved

100.0K

143.0K

1.358V

Reserved

100.0K

174.0K

1.204V

Reserved

100.0K

215.0K

1.048V

MODEL_ID_DET

C2718

DY

BATLOW#_EC ECSMI#_KBC

2 0R2J-2-GP

69 CAP_LED# 36 S5_ENABLE 68 BATT_WHITE_LED# 39 BAT_IN# 70 LID_CLOSE# 19 RSMRST#_KBC 19,46 PM_SLP_S4# 22,92,93 DGPU_PWROK

Layout Note: Need very close to EC

BLUETOOTH_EN

33R2J-2-GP 33R2J-2-GP 33R2J-2-GP 33R2J-2-GP

21,60 SPI_CS0#_R 21,60 SPI_CLK_R 21,60 SPI_SO_R 21,60 SPI_SI_R 65 CARD_WPAN_OUT#

C

ECSWI#_KBC

65 WIFI_RF_EN 65 BLUETOOTH_EN 19,36 S0_PWR_GOOD 1 1 1 1

R2736 R2719 R2725 R2722

2 2 2 2

EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C EC_SPI_DO_C

79 6 109 14 15 80 17 20 21 26 123 82 83 84 90 92 86 87 91

GPIO52/PSDAT3/RDY# GPIO50/PSCLK3/TDO GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1 GPIO17/SCL1/N2TCK GPIO22/SDA1/N2TMS GPIO73/SCL2 GPIO74/SDA2 GPIO23/SCL3 GPIO31/SDA3 GPIO47/SCL4 GPIO53/SDA4

F_CS0# F_SCK F_SDI&F_SDIO1 F_SDIO&F_SDIO0 GPIO81/F_WP#

PSL_OUT_GPIO71# PSL_IN2_GPI06# PSL_IN1_GPI70#

BLON_OUT 49 AD_IA_HW2 40 PWR_CHG_AD_OFF 38 CARD_WLAN_OUT# 65 TPDATA 69 TPCLK 69

AD_IA_HW2

70 69 67 68 119 120 24 28

BAT_SCL 39,40 BAT_SDA 39,40 SML1_CLK 20,28,86 SML1_DATA 20,28,86

PROCHOT_EC

L_BKLT_EN 17

74 93 73

31 63 64

FAN_TACH1 PCIE_WAKE# PM_SLP_S3#

32 118 OVER_CURRENT_P8# 62 AC_IN_KBC# 65 22 1KB_BL_CTRL 81 66 16

68 PWRLED# 29 KBC_BEEP 86 OVER_CURRENT_P8# 38 AC_IN_KBC# 68 WLAN_LED# TP2721 49 KBC_BKLT 68 CHG_AMBER_LED#

<------ TP <------ BATTERY / CHARGER

21 ME_UNLOCK 65 E51_RxD 65 E51_TxD

23 113 111

19 PCH_SUSCLK_KBC 29 AMP_MUTE#

77 30

<------PCH / eDP

ECRST# R2721 43R2J-GP 1 2 1 R2720 2 0R0402-PAD

VCCP_CPU 5,22

H_PECI

PECI EC_VTT

KBC_VCORF

44

2

C2712 SC1U10V3KX-4GP-U

Layout Note: Need very close to EC

103

GND1 GND2 GND3 GND4 GND5 GND6

AGND

1

VCORF

13 12

GPIO56/TA1 GPIO14/TB1 GPIO1/TB2

KBSOUT0/GPOB0/JENK# KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS KBSOUT3/GPIOB3/TDI GPIO15/A_PWM KBSOUT4/GPOB4/JEN0# GPIO21/B_PWM KBSOUT5/GPIOB5/TDO GPIO13/C_PWM KBSOUT6/GPIOB6/RDY# GPIO32/D_PWM KBSOUT7/GPIOB7 GPIO45/E_PWM KBSOUT8/GPIOC0 GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS# GPIO33/H_PWM KBSOUT10&P80_CLK/GPIOC2 GPIO40/F_PWM KBSOUT11&P80_DAT/GPIOC3 KBSOUT12/GPIO64 KBSOUT13/GPIO63 GPIO46/CIRRXM/TRIST# KBSOUT14/GPIO62 GPIO87/CIRRXM/SIN_CR KBSOUT15/GPIO61/XOR_OUT GP/I/O83/SOUT_CR/TRIST# GPIO60/KBSOUT16 GPIO57/KBSOUT17 GPIO0/EXTCLK GPIO55/CLKOUT/IOX_DIN_DIO VCC_POR# PECI VTT

22

1

E

2 C

EC GPIO standard PH/PL

3D3V_AUX_KBC

3D3V_AUX_S5

RN2701 BAT_SCL BAT_SDA

C2722 SCD1U10V2KX-5GP 1 2

1

2 R2704 330KR2J-L1-GP

3 4

2 1 SRN4K7J-8-GP

1

2

KBC_ON#_GATE

Q2703 DMP2130L-7-GP

G

2

PSL_OUT#

RN2708

S

R2735

DY

G D

84.02130.031

3D3V_AUX_KBC

VGA_THRM

R2708 1

R2791 0R2J-2-GP

DY

2

3rd = 84.03413.A31

R2709 10KR2J-3-GP

3D3V_AUX_KBC

4 3

1 2 SRN100KJ-6-GP

EC_AGND

BLUETOOTH_EN R2714 1

DY

4 3

DY

R2707

1

BOOST_MODE#

R2711

1

DY

2 10KR2J-3-GP

OVER_CURRENT_P8#

R2716

1

DY

2 100KR2J-1-GP

AC_IN_KBC#

R2717

1

2 100KR2J-1-GP

R2715

1

2 10KR2J-3-GP

2 10KR2J-3-GP

X00 0608

RN2706 RSMRST#_KBC S0_PWR_GOOD

ECRST#

2 10KR2J-3-GP

4th = 84.02301.G31

S5_ENABLE 1

BAT_IN# PCIE_WAKE#

2 10KR2J-3-GP

1

1

83.00016.K11 2nd = 83.00016.F11

3D3V_AUX_S5

R2734 330KR2J-L1-GP

PSL_IN1#

B

ECSMI#_KBC

3

C502 : check list 1.5

2nd = 84.00102.031

3D3V_S0

1 2

SRN100KJ-6-GP

E51_RxD

DY

A

D

A

1

2

DY

D

R2768 0R0402-PAD 1 2

D2704 1

EC_SMI#

BAS16-6-GP

20KR2F-L-GP

AC_IN#

BAS16-6-GP

83.00016.K11 2nd = 83.00016.F11

R2723 0R0402-PAD 1 2

DY

C2720 SC47P50V2JN-3GP

3D3V_AUX_S5

PSL_IN2#

ECSCI#_KBC

3

2 C2715 SC1U6D3V2KX-GP

5,38,40,42

2

Power Switch Logic(PSL)

40

DY

1

3rd = 84.2N702.J31

R2767 0R0402-PAD 1 2

1

EC_SCI#

2

2nd = 84.2N702.W31

68 KBC_PWRBTN#

B Q2701 MMBT3906-4-GP

G

84.07002.I31

83.00016.K11 2nd = 83.00016.F11

D2703 ECRST#

22 H_PROCHOT#

ECSWI#_KBC

3

R2764 0R0402-PAD 1 2

84.T3906.A11 2nd = 84.03906.F11

R2733 0R0402-PAD 1 2

2

100KR2J-1-GP 2 1

B

H_PROCHOT#_EC

C

BAS16-6-GP

28,36,86 PURE_HW_SHUTDOWN#

69

1

EC_SWI#

3D3V_AUX_S5

PROCHOT_EC

TP2717 KROW[7..0]

D2702 20

Layout Note: Connect GND and AGND planes via either 0R resistor or connect directly.

69

R2766 0R0402-PAD 1 2

DY

EC_GPIO23 High Active

D

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL[16..0]

NPCE885PA0DX-GP

R2705 10KR2J-3-GP

S

54 55 56 57 58 59 60 61

2

EC_AGND

Q2702 2N7002BK-GP

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KBC_GPIO57 1

Need very close to EC

R2765 1 2 0R0402-PAD

R2732

KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

Layout Note:

EC_AGND

18 45 78 89 116 5

NPCE885PA0DX-GP

85

C2716

GPIO20/TA2/IOX_DIN_DIO GP/I/O84/IOX_SCLK/XORTR# GPO82/IOX_LDSH/TEST#

2 0F 2

U2701B 28 31 19,36,37,47

RTCRST_ON 21 PM_LAN_ENABLE 31 LCD_TST_EN 49 LCD_TST 49

1 R2792 2 0R0402-PAD PSL_OUT# PSL_IN2# PSL_IN1#

D

EC_AGND

19

BOOST_MODE# 40 H_A20GATE 22 H_RCIN# 22

27 25 11 10 71 72

3.0V 2.75V 2.48V 2.24V 2.0V 1.87V 1.65V 1.358V 1.204V 1.048V

21,71

SCD1U10V2KX-5GP

117 112 110

19 PM_PWRBTN# 19,86 AC_PRESENT 61 USB_PWR_EN#

GPIO02 GPIO24 GPIO30/F_WP# GPIO34/CIRRXL GPIO36 GPIO41/F_WP# GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO51/N2TCK GPIO67N2TMS GPIO75 GPIO76 GPIO77

VOLTAGE

10.0K(64.10025.6DL) 20.0K(64.20025.6DL) 33.0K(64.33025.6DL) 47.0K(64.47025.6DL) 64.9K(64.64925.6DL) 76.8K(64.76825.6DL) 100.0K(64.10035.6DL) 143.0K(64.14335.6DL) 174.0K(64.17435.6DL) 215.0K(64.21535.6DL)

1

R2793 1

BATLOW#

R2739 100KR2F-L1-GP

DY

PULL-HIGH RESISTOR

100.0K 100.0K 100.0K 100.0K 100.0K 100.0K 100.0K 100.0K 100.0K 100.0K

2

R2738 19 100KR2J-1-GP

2

Vos

1

X02

OAK14_UMA OAK14_DIS_N13P OAK14_DIS_N13M TBD TBD TBD TBD TBD TBD TBD

N13MR2713 R2710 N13PR2712 UMA 2

2.75V

2

3.0V

20.0K

1

10.0K

100.0K

1

1

100.0K

X01

PULL-LOW RESISTOR

2

1 2 1

SCD1U10V2KX-5GP

EC_AGND

DY

LRESET#/GPIOF7 LCLK/GPIOF5 LFRAME#/GPIOF6 LAD3/GPIOF4 LAD2/GPIOF3 LAD1/GPIOF2 LAD0/GPIOF1 SERIRQ/GPIOF0 GPIO11/CLKRUN# GPIO65/SMI# ECSCI#/GPIO54 GPIO10/LPCPD# GPIO85/GA20 KBRST#/GPIO86

GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO5/AD4 GPIO4/AD5 GPIO3/AD6 GPIO7/AD7

2

1

1 114

75

4

C2711 SC220P50V2KX-3GP 1 2

VBKUP

VSBY

102

VDD

2 RTC_AUX_S5 R2794

1 0F 2

DY

R2726 100KR2F-L1-GP

X00

1

36,42 IMVP_PWRGD

AVCC

VCC1 VCC2 VCC3 VCC4 VCC5 104

PCB_VER_AD

1

38

19 46 76 88 115

EC_VBKUP 1 0R0402-PAD

2 SCD1U10V2KX-5GP

AD_IA

2

3D3V_AUX_S5

U2701A

1

40

C2717

3D3V_AUX_KBC_VCC

EC_AGND

3D3V_AUX_KBC

PCB_VER_AD C2703 SC2D2U10V3KX-1GP

DY

2


1

DY 2

1 2

2


1


1 2

2


1


1 2


DY

C2709 SC2D2U10V3KX-1GP 2 1

2 1 2

1


DY


MODEL_ID_DET(GPIO07) 20KR2F-L-GP

R2771 2D2R3-1-U-GP

1

VBAT

VOLTAGE

10KR2F-2-GP

VBAT

PULL-HIGH RESISTOR

33KR2F-GP

R2724 47KR2F-GP

R2702 0R0603-PAD 1 2

PULL-LOW RESISTOR

2

3D3V_S0

3D3V_AUX_KBC

D

2

PCB VER AD(GPIO91)

2

VBAT

0905

1

VBAT A00

1

4

SCD1U10V2KX-5GP

5

SSID = KBC

M14 DIS

G

S

Q2706 2N7002BK-GP

Wistron Corporation

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date:

5

4

3

2

KBC Nuvoton NPCE885 OAK14 Chief River DIS

Document Number


1

Sheet

27

of

Rev

A00 105

5

4

3

3D3V_S0

SSID = Thermal

4

3

THM_SML1_DATA


U2802

5V_S0

20,27,86 SML1_CLK

27

U2801

DY

NCT7718W -GP

74.07718.0B9 T_CRIT#

1

2

THM_SML1_CLK THM_SML1_DATA ALERT#


8 7 6 5

DY 2

R2813 0R0402-PAD 1 2

SCL SDA ALERT# GND

1

NCT7718_DXN

2.System Sensor, Put on palm rest

VDD D+ DT_CRIT#

2

2

1 2 3 4

C2807 SC2200P50V2KX-2GP


1

DY C2806 SC470P50V2KX-3GP


FAN1_DAC

1 2 3 4

*Layout* 10 mil

FON# VIN VOUT VSET

GND GND GND GND

8 7 6 5

NCT3940S-A-GP

For linear FAN

1

1

NCT7718_DXP

THERM_SYS_SHDN#

R2802 FON# 1 DY 2 5V_S0 0R2J-2-GP FAN_VCC

2

1 2

1 2

2

THM_SML1_CLK

2

1 Q2801 PMBS3904-1-GP

1

5

Q2804 2N7002KDW -GP

1

2

C2802

2ND = 84.03904.P11 84.03904.L06 3

1 2

SCD1U10V2KX-5GP

SC10U6D3V3MX-GP

DY

6

D

3D3V_S0

R2808 NTC-100K-8-GP

3 4 SRN2K2J-1-GP

20,27,86 SML1_DATA

D

1

Fan controller NCT3940S-A

RN2801

2 1

Thermal sensor NCT7718W

C2805

2


74.03940.A71 X02 0730 change main source

Reserved for signal quality improvement.

C

C

3D3V_S0

R5

ALERT#

R2815

1

2 18K7R2F-GP

T_CRIT#

R2814

1

2 2KR2F-3-GP

R7 3D3V_S0

2

Fan Connecter

FAN_TACH1

AFTP2803

1

S

2

AFTP2802 AFTP2801

1FAN_TACH1_C 1FAN_VCC

1

FAN_VCC

DY 2

1

B

DY

1 4 ETY-CON3-8-GP

20.F1841.003

83.R5003.C8F

2nd = 83.R5003.G8H 3rd = 83.R5003.H8H 4th = 83.5R003.08F

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

2

G

C2811 SCD1U10V2KX-5GPDY

R2809 100KR2J-1-GP


2 D

27,36,86 PURE_HW _SHUTDOW N#

DY THERM_SYS_SHDN#

DY

2

1


1

3D3V_S0

5 3 2

*Layout* 15 mil

Q2802 2N7002BK-GP

1

FAN_TACH1_C


1 27

FAN1

R2807 0R0402-PAD 1 2

C2810 SC2200P50V2KX-2GP 2 1

B

R2820 10KR2J-3-GP

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing. and route has to be away from the high noise area. Put the C2807 2200pF to close the NCT7718W

3D3V_S0

M14 DIS

A

A


Thermal NCT7718W/Fan Controllor P2793 Size A3 Date: 5

4

3

2

Document Number

Rev



Sheet 1

28

A00 of

105

2

SSID = AUDIO

B


DY 2

1HDA_CODEC_BITCLK_C 1

DY 2

ER2901 47R2J-2-GP

DMIC: > 5mil and keep out the analog signal R2904 1 49 DMIC_DATA R2905 1 49 DMIC_CLK 21 HDA_CODEC_SDOUT 21 HDA_CODEC_BITCLK

close to pin 3

EC2922 SC22P50V2JN-4GP

21 HDA_SDIN0

1

2

1 2

SC4D7U6D3V3KX-GP

1

C

AUD_SENSE 58

Layout Note: Place close to Pin 13

Analog DigiTal

71.03221.A03 3D3V_S0

2SB_SPKR_R

1


C2922 DY SC100P50V2JN-3GP

2

1 R2914 1KR2J-1-GP

HDA_SPKR 21

1

AUD_PC_BEEP

R2919

DY 10KR2J-3-GP

2KBC_BEEP_R

1

C2913 SCD1U10V2KX-5GP HDA_CODEC_SDIN0

C2923 DY SC100P50V2JN-3GP

HDA_CODEC_SYNC HDA_CODEC_RST#

21 HDA_CODEC_SYNC 21 HDA_CODEC_RST#

58

2

1 R2915 1KR2J-1-GP

B

KBC_BEEP 27

R2920

DY 10KR2J-3-GP 2

C2919 SC22P50V2JN-4GP

C2908

DMIC_DATA_R 2 20R2J-2-GP DMIC_CLK_R 0R2J-2-GP

R2907 1 2 33R2J-2-GP

2

DMIC_CLK

C2909

R2917 39K2R2F-L-GP

SLEEVE

AUD_AGND

20KR2F-L-GP 2 AUD_SENSE

2

DY DY

36 35 34 33 32 31 30 29 28 27 26 25

3D3V_S0

2

1

COMBO-GPI

Azalia I/F EMI

HDA_CODEC_BITCLK 2

CPVDD CBN CPVEE HP_OUT_R HP_OUT_L LINE1/MIC1_VREFO-L LINE1/MIC1_VREFO-R MIC2_VREFO VREF LDO1_CAP AVDD1 AVSS1

ALC3221-CG-GP

ALC3221 : 71.03221.A03

2PCH_AZ_CODEC_SDOUT1 1

1

2 0R2J-2-GP 1 DY 2 R2923 10KR2J-3-GP 1 DY 2 3D3V_S0 R2918 1KR2J-1-GP

JDREF 1 R2916 AUD_SENSE_A 1

1

58

DY

C2902 R2924 SC4D7U6D3V3KX-GP 1KR2J-1-GP RING2_R RING2_C 1 1 2 2

2

Tied at point only under Codec or near the Codec

ER2902 47R2J-2-GP

AUD_AGND

1

Layout Note:

HDA_CODEC_SDOUT 1

Place close to Pin 26

2

1 R2921

24 23 22 21 20 19 18 17 16 15 14 13

SCD1U10V2KX-5GP

83.R0304.A8F 2nd = 83.R2004.B8F

1 LDO3_CAP C2911 1 C2910

AMP_MUTE#

LINE2_L LINE2_R LINE1_L LINE1_R CPVREF/MIC1_R MIC_CAP/MIC1_L SLEEVE/MIC2_R RING2/MIC2_L MONO_OUT JDREF SENSEB SENSEA

2

AUD_AGND

CH751H-40PT-GP 1

CBP AVSS2 LDO2_CAP AVDD2 PVDD1 SPK_L+ SPK_LSPK_RSPK_R+ PVDD2 PDB SPDIFO/GPIO2 GND

2

2 0R0603-PAD

D

Layout Note:

AUD_AGND

DVDD GPIO0/DMIC_DATA GPIO1/DMIC_CLK DVSS SDATA_OUT BIT_CLK LDO3_CAP SDATA_IN DVDD_IO SYNC RESET# PCBEEP

1

C

27

+5V_AVDD

1 2 3 4 5 6 7 8 9 10 11 12

R2910

58 58 58 58

37 38 39 40 41 42 43 44 45 46 47 48 49

1

1

2 0R0603-PAD

LDO2_CAP 1 C2901 +3V_1D5V_AVDD +5V_PVDD AUD_SPK_L+ AUD_SPK_L+ AUD_SPK_LAUD_SPK_LAUD_SPK_RAUD_SPK_RAUD_SPK_R+ AUD_SPK_R+ +5V_PVDD D2901 EAPD# 2 COMBO-GPI

2

SCD1U10V2KX-5GP 2

R2909

Analog DigiTal

SC10U6D3V3MX-GP

AUD_AGND

1

2 0R0603-PAD

CBP

AUD_AGND

Layout Note: Close PIN41 Close PIN46

1

C2915

2

U2901

2

2

1



2

1


Layout Note:

SCD1U10V2KX-5GP

1

C2905

2

2

SC10U6D3V3MX-GP

1

C2904

C2914

AUD_VREF LDO1_CAP

AUD_AGND

close to pin 40

R2913 0R0603-PAD 1 2

R2908

CBN CPVEE 2 C2918

+5V_PVDD R2912 0R0603-PAD 1 2

5V_S0 R2911 0R0603-PAD 1 2

SCD1U10V2KX-5GP


SC4D7U6D3V3KX-GP

5V_S0

+3V_AVDD

2

close to pin 36

60mA

2

2 0R0402-PAD 1

1

D

2 0R2J-2-GP

DY

1D5V_S0 C2920 R2903 1 SC4D7U6D3V3KX-GP

SC10U6D3V3MX-GP

2

R2902 1

+5V_AVDD

1 C2917 SC2D2U6D3V2MX-GP 1 C2916 SC10U6D3V3MX-GP

+3V_1D5V_AVDD

1 SC1U6D3V2KX-GP

2 0R0402-PAD

1

AUD_EAPD#

58 AUD_HP1_JACK_L 58 AUD_HP1_JACK_R

+3V_AVDD 3D3V_S0

R2906

58 MIC2-VREFO

HV mode : performance up , chip power consumption up LV mode : performance down , chip power consumption down

25mA

3D3V_S0

1

AUD_AGND

3

AUD_AGND

4

2

5

DY

1 10KR2J-3-GP

Depop sound

D2902

1 3D3V_S0 58 AUD_HP1_JACK_R1

1

3

POP

2

POP POP

1 AUD_PD#_C1

22KR2J-GP

B Q2901 MMBT3906-4-GP

POP

84.T3906.A11 2nd = 84.03906.F11

2

POP C2950 SC10U6D3V3MX-GP

AUD_HP1_JACK_L1

A

HP_MUTE 2

POP

1HP_MUTE_R

R2927 4K7R2J-2-GP

R2928 2

POP

1 1KR2J-1-GP

HP_MUTE_RC2

R2929 2

POP

1 1KR2J-1-GP

HP_MUTE_RC1

B

POPQ2902

BTD2040N3S-GP

C

1

AUD_PD#_C 2

AUD_HP1_JACK_R1

2

DY


84.02043.011

B

POPQ2903

BTD2040N3S-GP

M14 DIS

A

E

83.BAT54.V01

R2925

58 AUD_HP1_JACK_L1

C

BAT54A-7-F-GP

R2926 220KR2J-L2-GP

E

AUD_EAPD#

E

AMP_MUTE#

1

27

C

2 R2922

2

3D3V_S0

Wistron Corporation

84.02043.011 AUD_AGND

AUD_AGND


AUD_AGND

Title Size A3 Date: 5

4

3

2

Audio Codec ALC3221

Document Number


Sheet 1

29

Rev

A00 of

105

5

4

3

2

1

D

D

(Blanking) C

C

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

30

A00 of

105

5

4

3

2

1

3D3V_LAN_S5

1 Q3101 PMBS3904-1-GP 3

2 R3112 2 R3116

1 0R0402-PAD 1 0R0402-PAD

1

3D3V_LAN_S5 GPO

1 2

2

C3102 1 2

3 2

1

LAN_TXP_C_PCH_RXP6 LAN_TXN_C_PCH_RXN6

3D3V_LAN_S5 C3103 1 2

LANXIN R3103 1

DY

2 1KR2J-1-GP

GPO

2

SC18P50V2JN-1-GP

EEDI/SDA

DY

close to pin 21 22

C3105 LAN_TXP_C_PCH_RXP6 1 LAN_TXN_C_PCH_RXN6 1 C3104 LAN_RXP_C_PCH_TXP6 LAN_RXN_C_PCH_TXN6

SCD1U10V2KX-5GP 2 2 SCD1U10V2KX-5GP

CLK_PCIE_LAN 20 CLK_PCIE_LAN# 20

M14 DIS

A


2N7002K-2-GP

2

PCH_RXP_C_LAN_TXP6 20 PCH_RXN_C_LAN_TXN6 20 LAN_RXP_C_PCH_TXP6 20 LAN_RXN_C_PCH_TXN6 20

S

Size A3 Date: 5

B

X3102 XTAL-25MHZ-155-GP

D

R3122 100KR2J-1-GP

2

48 47 46 45 44 43 42 41 40 39 38 37

71.08105.B03

C3128

G

2

2 1

15KR2F-GP

SC18P50V2JN-1-GP

1

DY

LAN_ENABLE_R_C

Q3102

G

27 PM_LAN_ENABLE

R3118 20KR2F-L-GP 1 2 PM_LAN_ENABLE_R

R3110 1KR2J-1-GP

R3109

10KR2J-3-GP C3125 SC1U10V2KX-1GP

3D3V_S0

1

R3114

D

1

R3121 10KR2J-3-GP


main: 84.00102.031 2nd: 84.03403.031

SCD1U10V2KX-4GP

2

1

1

S

2

2

SCD1U10V2KX-5GP

2

0R3J-0-U-GP PA102FMG-GP-U Q3103

3D3V_LAN_S5 ISOLATE# PLT_RST#_LAN

4

SCD1U16V2KX-3GP 2

C3131

3D3V_S5

2 10KR2J-3-GP PCIE_W AKE# 27

EVDD10

R3120

DY

DY

C

CLK_LAN_REQ#_R LAN_RXP_C_PCH_TXP6 LAN_RXN_C_PCH_TXN6 CLK_PCIE_LAN CLK_PCIE_LAN#

2 DY 0R3J-0-U-GP

1

R3107 1 DVDD10

R3106 0R0402-PAD 1 2

LANXOUT

3D3V_LAN_S5

R3119

1

DY

DVDD10

251mA 3D3V_S0

REGOUT 1 AVDD33_REG AVDD33_REG ENSW REG EEDI/SDA

RTL8105E-VD-CGT-GP

SCD1U16V2KX-3GP

1

EC3103 EC3104

DY 2

SCD1U16V2KX-3GP

2

DY

36 35 34 33 32 31 30 29 28 27 26 25

R3105 0R2J-2-GP

1

B

1

1 0R0402-PAD

EC3102

DY 2

DY

SCD1U16V2KX-3GP

PLT_RST#_LAN

3

REGOUT VDDREG VDDREG ENSWREG EEDI EEDO/LED3 EECS DVDD10 LANWAKE# DVDD33 ISOLATE# PERST#

DY 1

LAN_MDI1P LAN_MDI1N

MDIP0 MDIN0 NC#3 MDIP1 MDIN1 NC#6 NC#7 NC#8 NC#9 NC#10 NC#11 NC#12

DVDD10 R3124 0R2J-2-GP 2

1

59 59

LAN_MDI0P_1 1 LAN_MDI0N_1 2 3 LAN_MDI1P_1 4 LAN_MDI1N_1 5 6 7 8 9 10 11 12

GND

2

1 0R0402-PAD 1 0R0402-PAD

LAN_MDI0P LAN_MDI0N LAN_MDI1P LAN_MDI1N

Q3104 PMBS3904-1-GP R3123 1 2

A

1

DY

TP3102 TPAD14-OP-GP

AVDD33 AVDD33 RSET AVDD10 CKXTAL2 CKXTAL1 NC#42 NC#41 LED0 DVDD3 GPO EESK/LED1

2 R3108 2 R3111

1Q402_13 4

DY

2

0R2J-2-GP

DVDD10 NC#14 NC#15 CLKREQ# HSIP HSIN REFCLK_P REFCLK_N EVDD10 HSOP HSON GND

LAN_MDI0P LAN_MDI0N

2 1

59 59

RN3101 SRN10KJ-5-GP

EC3101

2

PLT_RST#

CLK_LAN_REQ#_R

2

R3117

EESK 1

U3101

49

3D3V_LAN_S5

5,18,27,65,71,83

D

For Switch Regulator enable 3D3V_LAN_S5

C

DY

DVDD10 LANXOUT LANXIN

3D3V_LAN_S5 3D3V_LAN_S5 R3113 2K49R2F-GP 1 2

20 PCIE_CLK_LAN_REQ#

13 14 15 16 17 18 19 20 21 22 23 24

1 2

SCD1U10V2KX-5GP

1

C3129

2

C3119 SCD1U16V2ZY-2GP

1

C3121

2

C3118

SCD1U16V2ZY-2GP

2

close to pin 27 39 47 48

SCD1U16V2ZY-2GP

1

3D3V_LAN_S5

1

84.03904.L06 2ND = 84.03904.P11

1mS < +3D3V_LAN_S5 Rising time (10%~90%) <100mS 40 mils

R3104 10KR2J-3-GP

2

2

2

R3101 10KR2J-3-GP

1

1

1

1

C3117

2

2

C3114

CLK_LAN_REQ#_EN

2

C3109

SCD1U16V2ZY-2GP

X5R D

LAN CHIP

C3113

SCD1U16V2ZY-2GP

SC1U10V3ZY-6GP

SCD1U16V2ZY-2GP

1

C3106

DVDD10

R3115 0R0603-PAD 1 2

SCD1U16V2ZY-2GP

1

EVDD10

4

3

2

Document Number

LOM

Rev


Sheet 1

31

A00 of

105

5

4

3

2

1

SSID = SDIO

D

D

3D3V_S0

250mA C3208 SDREG

1

2 SC1U6D3V2KX-GP

V18

23 7

XD_D4/SD_D3/MS_D1 XD_D5/SD_D2/MS_D5 XD_D6/MS_BS

R3209

2

1

33R2J-2-GP

74

XD_D4/SD_D3/MS_D1 74 XD_D5/SD_D2/MS_D5 74 XD_D6/MS_BS 74

XD_D0/SD_CLK/MS_D2_R

74

2

XD_D1/SD_D5/MS_D0 XD_D2/SD_CMD 74

For EMI

DY

1

XD_D7 XD_CD#

XD_D0/SD_CLK/MS_D2 XD_D1/SD_D5/MS_D0 XD_D2/SD_CMD

EC3201 SC10P50V2JN-4GP C

GND 25

6 SDREG

4

5

GPIO0

15 16 18 19 20 21 22

SP8 SP9 SP10 SP11 SP12 SP13 SP14

71.05170.003

RREF CR_GPIO0 R3201 6K2R2F-GP

1

TP3201

1

USB_PN10_R USB_PP10_R

17

2 3

RTS5170-GR-GP

CARD_3V3

SP1 SP2 SP3 SP4 SP5 SP6 SP7

RREF

8 9 10 11 12 13 14

1

XD_RDY/SD_W P/MS_CLK_R XD_RE#/MS_INS# XD_CE#/SD_D1 XD_CLE/SD_D0/MS_D7 XD_ALE/SD_D7/MS_D3 XD_W E#/SD_CD#

2

V18

U3201

24

SC1U6D3V2KX-GP

3V3_IN

R3208 0R0402-PAD 1 2 74 XD_RDY/SD_W P/MS_CLK 74 XD_RE#/MS_INS# 74 XD_CE#/SD_D1 74 XD_CLE/SD_D0/MS_D7 74 XD_ALE/SD_D7/MS_D3 74 XD_W E#/SD_CD#

C3211 2 1

DM DP

C

3D3V_CARD_S0


C3204 SC4D7U6D3V3KX-GP 2 1

43mA

Close U3201

B

USB_PN10_R

USB_PP10_R

B

R3212 0R0603-PAD 1 2

USB_PN10

USB_PN10 18

R3211 0R0603-PAD 1 2

USB_PP10

USB_PP10 18

M14 DIS A

A


4

3

2

Card Reader-RTS5170

Document Number


Sheet 1

32

Rev

A00 of

105

A

B

C

D

E

4

4

3

3

(Blanking)

2

2

M14 DIS

1

1

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: A

B

C

D

Document Number

Reserved

Rev


Sheet E

33

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

34

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

35

A00 of

105

5

4

3

2

1

SSID = Reset.Suspend BAS16-6-GP

83.00016.K11 2nd = 83.00016.F11 83.00016.K11 2nd = 83.00016.F11

1

D

R3614 0R0402-PAD 1 2

D3602

SYS_PW ROK

SYS_PW ROK 19

41

1 C3612 DY SCD01U50V2KX-1GP

DY 2

2

D PS_S3CNTRL

Q3603 2N7002BK-GP

2

G

D

3 1

3V_5V_EN

1

27,42 IMVP_PW RGD

R3602 200KR2J-L1-GP

2 3

19,27 S0_PW R_GOOD

1 R3603

PURE_HW _SHUTDOW N#

27,28,86

D3601 BAS16-6-GP

2 1KR2J-1-GP

S5_ENABLE 27

84.07002.I31 S

2nd = 84.2N702.W31 3rd = 84.2N702.J31

AO4468 MAX 11.6A Rds(on) = 14m ohm

15V_S5

5V_S0

R3604 100KR2J-1-GP

1

8 7 6 5


PS_S3CNTRL 37

1 R3606

5V_RUN_ENABLE 2 0R2J-2-GP

S S S G

+5V_RUN Comsumption Peak current ?A Design current ?A

1 2 3 4

AO4468-GP

2

1

1

R3605

C


84.04468.037 2nd = 84.02659.037 3rd = 84.04178.037 4th = 84.04496.037 5th = 84.04800.D37

2

3D3V_AUX_S5

U3601 D D D D

1

C

5V_S0

5V_S5

2

ROSA Run Power

PS_S3CNTRL 2 100KR2J-1-GP

R3607

3.3V_RUN_ENABLE 2 100KR2J-1-GP

1

4 S1 D1


S S S G

1 2 3 4

+3.3V_RUN Comsumption Peak current ?A Design current ?A B

AO4468-GP

1

21,37 RUN_ENABLE

U3602 D D D D

1

5 G1

3

8 7 6 5

19,27,37,47 PM_SLP_S3#

3D3V_S0 3D3V_S0


2

6 D2

2

3D3V_S5

84.04468.037 2nd = 84.02659.037 3rd = 84.04178.037 4th = 84.04496.037 5th = 84.04800.D37

2

B

AO4468 MAX 11.6A Rds(on) = 14m ohm

Q3602 ME2N7002DKW -G-GP

84.2N702.F3F 2nd = 84.2N702.A3F S G D 3rd = 84.DMN66.03F

1

S2

G2

D G S

1D5V_S0

AO4468 MAX 11.6A Rds(on) = 14m ohm 1D5V_S0

8 7 6 5

U3606 D D D D

S S S G

1 2 3 4

1.5V_RUN_ENABLE 2 100KR2J-1-GP

1

C3610 SCD047U25V2KX-GP

2

1

R3630

M14 DIS


2

AO4468-GP

A

+1.5V_RUN Comsumption Peak current ?A Design current ?A

1

1D5V_S3

A

84.04468.037 2nd = 84.02659.037 3rd = 84.04178.037 4th = 84.04496.037 5th = 84.04800.D37


Power Plane Enable Size A3 Date: 5

4

3

2

Document Number

Rev

OAK14 Chief River DIS W ednesday, September 05, 2012 Sheet 1

36

A00 of

105

5

4

3

2

1

Close to DIMM S3 Power Reduction Circuit SM_DRAMPWROK

Close to CPU S3 Power Reduction Circuit Processor VREF_DQ Implementation

0D75V_S0

2

R3703 22R2J-2-GP

D

84.07002.I31

3rd = 84.2N702.J31

2nd = 84.2N702.W31 36

3rd = 84.2N702.J31

PS_S3CNTRL

D

Q3702_D2

84.07002.I31 2nd = 84.2N702.W31

R3704 220R2J-L2-GP

Q3701 2N7002BK-GP

84.07002.I31 2nd = 84.2N702.W31

PS_S3CNTRL

G

Q3702 2N7002BK-GP 3rd

= 84.2N702.J31

G

DY

1

S

45,48 1D05V_VTT_PW RGD

S

R3705 100KR2J-1-GP

D

2

S

21,36 RUN_ENABLE

DY

Q3701_D

+V_SM_VREF_CNT

D

G

M_VREF_DQ_DIMMA

1

D

2

2

Q3708 2N7002BK-GP R3708 0R0402-PAD 1 2 +V_SM_VREF

1

1

1D5V_S0

R3707 0R2J-2-GP 1 DY

2

R3710 0R0402-PAD

2 DY22R2J-2-GP

0D75V_EN 46


DY

Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK 1D5V_S3

C

1

D

2

C

0D75V_EN

1 R3716

1

19,27,36,47 PM_SLP_S3#

Q3704 2N7002BK-GP

R3706 1KR2J-1-GP

G

R3709 0R2J-2-GP 1 2

84.07002.I31

DY

S

2nd = 84.2N702.W31

2

36 PS_S3CNTRL

S3 Power Reduction Circuit SM_DRAMRST#

3rd = 84.2N702.J31 SM_DRAMRST#

2

DDR3_DRAMRST#

14,15

1KR2J-1-GP C3702 SC100P50V2JN-3GP

3rd = 84.2N702.J31

3D3V_S0

1

3D3V_S0 1D5V_S0

R3713 10KR2J-3-GP

20 DRAMRST_CNTRL_PCH

2

B

3

GND

VCC

5

Y

4

DY

R3702 200R2F-L-GP

2

A

VDDPW RGOOD_R

1R3719 910R2F-GP

1

0D75V_EN

1

B

C3703 SCD047U16V2KX-1-GP

2

2

U3701

19 PM_DRAM_PW RGD

U74LVC1G08G-AL5-R-GP-U R3721 39R2J-L-GP

DY

VDDPW RGOOD 5

R3720 750R2F-GP

Q3707_D

2

2

73.01G08.EHG 2nd = 73.7SZ08.EAH 3rd = 73.7SZ08.DAH 4th = 73.01G08.L04

2

1

B

1

DRAMRST_CNTRL_PCH

1

CEKLT V1.0: PCH to 1K,CUP to 200R

VDDPW RGOOD_R

D

R3717 1 DY 2 0R2J-2-GP

G

2nd = 84.2N702.W31

2

84.07002.I31

Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK

19 PM_DRAM_PW RGD

R3718 SM_DRAMRST#_D 1

D 1

5

Q3703 2N7002BK-GP S

SM_DRAMPWROK must have a maximum of 15ns rise or fall time over VDDQ * 0.55± 200mV and the edge must be monotonic

PS_S3CNTRL

Q3707 2N7002BK-GP

G

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

S

DY

M14 DIS

A

A


S3 Reduction Circuit Size A3 Date: 5

4

3

2

Document Number

Rev



Sheet 1

37

A00 of

105

5

4

3

2

SSID = PWR.Support

1

2

3

1

D

PR3806 2K2R2J-2-GP

83.00099.T11 2nd = 83.3X101.011

PR3807 PS_ID_R2

2

D

1

2

PSID_EC 27

33R2J-2-GP

1

84.00301.A31 2nd = 84.3K329.031 2

PSID Layout width > 25mil

PS_ID

S

0R3J-0-U-GP

Layout Note:

PSID_DISABLE#_R_C

2

3 PQ3801 FDV301N-NL-GP D

PS_ID_R

PR3819 1

3D3V_S5 PD3803 BAV99-5-GP-U

G

1

PR3811 100KR2J-1-GP

2

2 1

PMBS3904-1-GP PQ3802

PQ3802_1 1

2 D

3D3V_S5 PR3803 10KR2J-3-GP

1

84.03904.L06 2nd = 84.03904.P11

PR3802 15KR2F-GP

1

2

5V_S5

DY

PD3804 PESD24VS2UT-GP

PR3808

1

2

DY

3

33R2J-2-GP JGND

DCIN1

NP2

PQ3809_D

B

AD_OFF_L

C

R1

E R2 PDTC124EU-1-GP

G

84.00124.H1K 2nd = 84.05124.011

E

PDTA124EU-1-GP

PC3806 SC10U25V5KX-GP

1 2

1 2

1

Id=-9.6A Qg=-25nC Rdson=18~30mohm

PR3810 47KR3J-L-GP

AD_OFF_R

C

84.00124.K1K 2nd = 84.05124.A11

1

2 PR3812 1KR2J-1-GP

3D3V_S5

27

AC_IN_KBC#

AC_IN_KBC#

D

2

B

S

DY

G PQ3808D

PR3815 100KR2J-1-GP

D

B

2N7002K-2-GP

84.2N702.J31

1

PQ3810 2N7002BK-GP

PR3817 PQ3808G1 2 1KR2J-1-GP

S

PR3813 10KR2J-3-GP

1

DT MODE

PQ3808

2

84.07002.I31 2nd = 84.2N702.W31

PC3809 SCD01U50V2KX-1GP

G

27 PW R_CHG_AD_OFF

2

AC_IN#_G

1

SC1U25V3KX-1-GP PC3808 2 1

S

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

B

2

D

PQ3804

PQ3809 2N7002BK-GP

1

PQ3805 PR3814 100KR2J-1-GP

2

1

SI7121DN-T1-GE3-GP


C

8 7 6 5

2

1

D D D D


A

2

PR3809 240KR3-GP

2

PC3802 SCD1U25V3KX-GP

2

1

PC3801 SC1U25V5KX-1GP

1

K

PD3801 1SMB22AT3G-GP-U1

2

2

EC3803 SCD1U25V3KX-GP

83.22R03.03G

2

JGND

3K3R6J-GP

1

DY 2

2

JGND

SC1KP50V2KX-1GP

20.F1643.007

SC10U25V5KX-GP

ACES-CON7-3-GP-U1

PR3816

EC3802

EC3801

DY

1

1

1

1

1 NP1

AD+ PU3801 S S S G

1 2 3 4


+DC_IN +DC_IN_C

R1

C

AFTP3803

1

R2

7 6 5 4 3 2

3rd = 84.2N702.J31

AFTP3801 AFTP3802

1 1

+DC_IN PS_ID_R

PBAT_PRES1# PQ3803 PR3818

2

DY

1

100KR2J-1-GP A

5,27,40,42 H_PROCHOT#

1

2

1

6

2

5

3

4

PBAT_PRES1# 39 M14 DIS

PQ3807D

A

DMN66D0LDW -7-GP

Wistron Corporation

PC3807 SC1U6D3V2ZY-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:

5

4

3

2

DCIN

Document Number

Rev


Sheet 1

38

of

A00 105

5

4

3

2

1

SSID = PWR.Support BT+

1 EC3903 SC2200P50V2KX-2GP

DY

PD3902 SMF18AT1G-GP

A

2

1 2


4 3 2 1

BAT_SCL BAT_SDA BAT_IN#

1 1 1 1

AFTP3902 AFTP3903 AFTP3904 AFTP3905

D

BATT1 10 1

PN3901 27,40 27,40 27

PBAT_PRES1# PBAT_SMBDAT1 PBAT_SMBCLK1 BT+

Batt Connecter

K

D

2 3 4 5 6 7 8 9 11

PBAT_SMBCLK1 PBAT_SMBDAT1 PBAT_PRES1#

5 6 7 8

AFTP3901

SRN33J-7-GP

1

BAT_ALERT

38 PBAT_PRES1#

ALP-CON9-6-GP-U

C

DY

2

2

1

EC3901 DY SC10P50V2JN-4GP DY

1


1

2

C

20.81925.009


AFTP3906

1

Placement: Close to Batt Connector

BAT_SCL 2

D3901 DA3X101F0L-GP

1

2

D3903 DA3X101F0L-GP

1

2

D3902 DA3X101F0L-GP

1

B

3

3

3

BAT_SDA

BAT_IN#

B

M14 DIS 3D3V_AUX_KBC

A

83.3X101.011 2nd = 83.BAV99.H11 3rd = 83.00099.M11

83.3X101.011 2nd = 83.BAV99.H11 3rd = 83.00099.M11

83.3X101.011 2nd = 83.BAV99.H11 3rd = 83.00099.M11

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4

Document Number

BATT CONN

4

3

Rev


Date: Wednesday, September 05, 2012 5

A

2

Sheet

39

A00 of

1

105

5

4

3

2

1

SSID = Charger

AD+_TO_SYS

DCBATOUT

BT+

D

1

1

1

2

2

PWR_CHG_ILIM

11

SRP ILIM

PWR_CHG_SRP

12

PWR_CHG_SRN

EE need check pull high 2

ROSA

1

2

DY

CHG_AGND

DY 2

EC code only BQ24707 AD_IA_HW2 0

90W

1

0

130W

0

1

PC4021 SCD1U25V2KX-GP 2 1

1


2

EC4001 SC2200P50V2KX-2GP

PC4009 SCD1U50V3KX-GP 2 1

PC4026 SC10U25V5KX-GP 2 1



PWR_CHG_CSON_1

1 2

PQ4008 PWR_CHG_ACOK

3 3D3V_AUX_S5

DY

2PWR_CHG_CMPOUT 2

100KR2J-1-GP

1

PR4033 DY120KR2F-L-GP

1

PR4037

DY PR4036

120KR2F-L-GP

1

4 5 6

AC_IN#

EE need pull high and net name

H_PROCHOT#

5,27,38,42

ME2N7002DKW-G-GP

84.2N702.F3F 2nd = 84.2N702.A3F 3rd = 84.DMN66.03F

A

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom

CHARGER BQ24727

DNE40 14 CR DIS

Date: 5

1

B

PWR_CHG_CSOP_1

PWR_CHG_REGN

2

1

AC_IN#

2

2

59K 27

0

84.00412.037 2nd = 84.08884.A37

PR4019 DYPR4028 100KR2J-1-GP 100KR2J-1-GP

PR4034 100KR2J-1-GP

2

PR4025

DY 100KR2J-1-GP


130W

1

33.2K

3D3V_AUX_S5

1

90W

1

24K

3D3V_AUX_S5

1

PWR_CHG_REGN

65W

DY

CHG_AGND

PR4023

2

Adapter type

65W

27


1 PR4024 8K45R2F-2-GP

1

AD_IA

PC4022 1 SC220P50V2JN-3GP

GAP-CLOSE-PWR-3-GP

2 CHG_AGND

1 PR4022 2 0R2J-2-GP

2

BQ24727RGRR-1-GP

PWR_CHG_IOUT

7

IOUT

GND

ACOK#

14

5

DY 1

2

3D3V_AUX_S5

21

PR4023 59KR2F-GP

CHG_AGND

GND

2

1

PR4018 0R2J-2-GP

CHG_AGND

AD_IA_HW

DY

NC#11

PG4011

H_PROCHOT#

2

1

1 PR4021 2 10R2F-L-GP 1 PR4020 2 7D5R2F-GP

2

DY PR4035 10KR2F-2-GP

2

2

27 BOOST_MODE#

1PWR_CHG_IFAULT

13

S2

DY

10

SRN 2

PU4006

2

SDA


PWR_CHG_BAT_SDA 8 1 GAP-CLOSE-PWR-3-GP

PWR_CHG_LODRV

5 6 7 8

2 PG4008

15

LODRV

4 3 2 1

SCL

1

PWR_CHG_BAT_SCL 9 1 GAP-CLOSE-PWR-3-GP

SIS412DN-T1-GE3-GP

27,39 BAT_SDA

2 PG4007

PC4020 SCD1U25V2KX-GP 1

BAT_SCL

D2

27,39

CHG_AGND

A

BT+

2 BT+_R

1

PC4013 SC3300P50V3KX-1GP

PR4016 1 2 D01R3721F-GP-U

2 1 PC4018 SC10U25V5KX-GP

PWR_CHG_CMPIN

DY

PWR_CHG_PHASE

2

2 1 PC4017 SC10U25V5KX-GP

19

PHASE

DY

PL4001

1 CMPIN

5 6 7 8

PWR_CHG_BTST_R

1

4 3 2 1

DY

PWR_CHG_HIDRV

2 1 PC4015 SC10U25V5KX-GP 2 1 PC4016 SC10U25V5KX-GP

18

PR4010 PC4014 0R3J-0-U-GP SCD1U50V3KX-GP 1 2PWR_CHG_SNUB 1 2

PG4010 GAP-CLOSE-PWR-3-GP 1 2

2

2

CHG_AGND

PC4024 SC1U25V3KX-1-GP

2

1

PWR_CHG_ACN

1

2 4

120KR2F-L-GP

HIDRV

CMPOUT

3D3MR2J-GP

2

2

3

16

Charger Current=1.4~3.6A

PG4009 GAP-CLOSE-PWR-3-GP 1 2

PR4014

DY

REGN


1

2 1

1

1 1 2

1

1 2


1 2

PR4031 1

1

47KR2F-GP 2

PWR_CHG_CMPOUT

PR4017 100KR2J-1-GP

1

BTST

PWR_CHG_BTST

D1

S2

PWR_CHG_CMPIN_R 2

ACDET

17

IND-5D6UH-48-GP-U1

3D3V_AUX_S5

PWR_CHG_CMPIN

B

VCC

C

S S S G

19K6R2F-GP PR4027

6

A

DY

PU4004 1 2 PC4007 SIS412DN-T1-GE3-GP SC1U25V3KX-1-GP

D D D D

CHG_AGND

PWR_CHG_CMPIN_RR

ME2N7002DKW-G-GP

DY

27 CHG_AGND

84.2N702.F3F 2nd = 84.2N702.A3F 3rd = 84.DMN66.03F

PR4012 3K3R2F-2-GP PR4032

PR4013 3K3R2F-2-GP 49K9R2F-L-GP

20

K

84.00412.037 2nd = 84.08884.A37

G2

AD_IA_HW

6

PR4015

CHG_AGND PWR_CHG_ACDET

PWR_CHG_REGN PD4001 SD103AWS-1-GP

G1

5

PR4030 3D3V_AUX_KBC100KR2J-1-GP

PR4009 0R3J-0-U-GP 1 2

CHG_AGND

S1

CHG_AGND

D2

D1

1

G2

2

4

G1

3

S1

AD_IA_HW2

PQ4007

PR4011 19K1R2F-GP

PU4005

DCBATOUT

83.1R504.A8F 2nd = 83.1R004.H8F 3rd = 83.1R504.B8F 4th = 83.2R004.08F

S S S G

27

PWR_CHG_REGN

PWR_CHG_IOUT

2

PWR_CHG_CMPIN

PR4029 54K9R2F-L-GP

2

PG4002

2

1

10R5J-GP

C

1

2

D D D D

PWR_CHG_VCC

2

8 7 6 5


CHG_AGND PC4010 SCD47U25V3KX-3-GP

1

PR4008

1

D

D D D D

Id= -10A Qg= -22nC Rdson=15~18mohm

PR4005 470KR2J-2-GP

ACN

S2

ME2N7002DKW-G-GP

84.2N702.F3F 2nd = 84.2N702.A3F 3rd = 84.DMN66.03F

PR4007 309KR2F-GP

DY

1

ACP

6

AD+

PG4003 GAP-CLOSE-PWR-3-GP

PR4006 0R2J-2-GP 2

PWR_CHG_ACP

5

PU4003 S S S G

1 2 3 4

SI7121DN-T1-GE3-GP

2

4

D2

AD+

D1

1

G2

2

G1

3 PWR_CHG_ACOK

GAP-CLOSE-PWR-3-GP

2 1

PQ4002

AD+_G_1

DC_IN_D

Id= -10A Qg= -22nC Rdson=15~18mohm

S1

2

AD+_G_2

PC4004 SC1U25V3KX-1-GP 2 1

PR4004 3KR5J-GP

PR4002 1 2 D01R3721F-GP-U

1

SI7121DN-T1-GE3-GP

2

1

1 2 3 4

PR4001 10KR2F-2-GP PR4003 100KR2J-1-GP

D D D D

8 7 6 5

AD+

PU4002 S S S G

4

3

2


Sheet 1

Rev

A00 40

of

105

A

B

C

D

E

SSID = PWR.Plane.Regulator_5v3p3v PWR_5V_VCLK

1

3V_5V_EN 36

1

0R0402-PAD

2

GAP-CLOSE-PWR-3-GP PG4133 1 2


PD4104 BZT52C15S-GP

GAP-CLOSE-PWR-3-GP

DY

5V_PWR

1 3BST15V_1 2

BOOST_10V

PC4106 SC1U25V3KX-1-GP



A

GAP-CLOSE-PWR-3-GP

3rd = 83.BAT54.P81 1

1 15V_PWR

4

83.0R203.081 2nd = 83.00054.Y81

1

PR4127


PD4101

2

2 PWR_3D3V_EN2 2

3rd = 83.BAT54.P81 15V_S5


BAT54SPT-GP


2nd = 83.00054.Y81


PR4122 0R0402-PAD


PD4103

83.0R203.081

BAT54SPT-GP


2

0R2J-2-GP

1

DY

1

3BST15V_2 2

PWR_5V_EN1_R

2

1

2

PR4121

0R0402-PAD

1

2

K

PWR_5V_EN1

PC4103

2

2 PWR_DCBATOUT_3D3V PG4102 1 2

1

DCBATOUT

1

2

1


PR4124

PC4102

SCD1U25V3KX-GP

PR4123

DY 0R2J-2-GP

4

SC1KP50V2KX-1GP

PG4128 1 2

SCD1U25V3KX-GP

PWR_DCBATOUT_5V

2

PC4104

DCBATOUT

1

3D3V_AUX_S5

DCBATOUT PWR_DCBATOUT_3D3V

EN1

CS2

CS1

PGOOD

GND

1

1

4 3 2 1

13

5V_PWR_2

PR4114 0R2J-2-GP

DY 1 2

PWR_5V3D3V_VREG3

3

DY

1

PC4125 SC18P50V2JN-1-GP

PC4126 SC4D7U6D3V5KX-3GP

3D3V_PWR_2

3D3V_AUX_S5 PR4116

GAP-CLOSE-PWR-3-GP

X01 change PR4120 to 9.76K to solve 5V voltage fall issue while on heavy loading PR4120 9K76R2F-1-GP

2

Close to VFB Pin (pin2)

2

2

1



PR4115 15KR2F-GP PWR_5V_FB1_R

2

PR4119 100KR2J-1-GP


2

1

1

3D3V_S5



X01 0613

1

GAP-CLOSE-PWR-3-GP

2

1 2

PG4101 1 2

PWR_3D3V_FB2_R PC4124 DYSC18P50V2JN-1-GP



PC4123 SC560P50V-GP

TPS51225RUKR-GP 3D3V_PWR_2

1

1

21

84.00406.037 DY 2nd = 84.08878.A30

PT4101

1

7

VREG3

2

PWR_5V3D3V_PGOOD

PR4102 115KR2F-GP

2

PWR_5V_VCLK

1

19

DY

2

VCLK

PC4120

2

PWR_5V_CS1

S

PG4117 1

1

1

EN2

G

DY

2

PWR_5V_EN1

2

1 2

1

20

2

1

5 6 7 8

2

12

1

PWR_5V_FB1

1

5

PWR_5V_VO1

2

77.52271.09L

2

PWR_3D3V_CS2

14


2

IND-2D2UH-46-GP-U PR4111 2D2R5F-2-GP

2

6

VFB1

3

2

PWR_3D3V_EN2

VFB2

2

2

1

DPU4102

PG4119 1 2


5V_PWR

68.2R210.20B 2nd = 68.2R21B.10J

1PWR_5V_SNUB

4

PR4101 45K3R2F-L-GP

84.00406.037 2nd = 84.08878.A30

2

PR4117 10KR2F-2-GP

PWR_5V_DRVL1 5 6 7 8

PWR_3D3V_FB2

G

DY0R2J-2-GP

1

2

PWR_5V_LL1

15

S

2

D D D D

S

PR4113 PR4112 6K65R2F-GP

18

G

PL4101

1

1PWR_3D3V_SNUB 2

DRVL1 VO1

1 S 2 S 3 S 4 G

2

1 2 3V_FEEDBACK 1

PU4105 SIS406DN-T1-GE3-GP

1

1 2

1 2

SW1

DRVL2

PWR_5V_DRVH1

SE220U6D3VM-30-GP

DY

SW2

16

1

5V_S5

5V_PWR


SCD1U10V2KX-4GP

PR4110 DY 2D2R5F-2-GP

PC4121 SC330P50V3KX-GP

DRVH1

PWR_5V_VBST1

Design Current=9.15A 13.73A16.47A

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

DRVH2

17

SIS406DN-T1-GE3-GP

PG4112 1 2

VBST1

S S S G

GAP-CLOSE-PWR-3-GP


DY

PT4102 SE220U6D3VM-30-GP

PG4111 1 2

77.52271.09L

8

PWR_3D3V_DRVL211

D

SCD1U25V3KX-GP PC4118 2PWR_5V_VBST1_1 1 2 1D5R3F-GP PR4109

VBST2

D D D D


PG4110 1 2

PWR_3D3V_LL2

2

IND-2D2UH-46-GP-U

GAP-CLOSE-PWR-3-GP

PC4117 PR4108 1PWR_3D3V_VBST2_1 1 2 PWR_3D3V_VBST29 SCD1U25V3KX-GP 1D5R3F-GP PWR_3D3V_DRVH210

8 7 6 5

1

PG4109 1 2 GAP-CLOSE-PWR-3-GP

2

4 3 2 1

68.2R210.20B 2nd = 68.2R21B.10J

G

VREG5

PL4102

GAP-CLOSE-PWR-3-GP

1 2 3 4

S S S G

VIN

2

1 2

8 7 6 5 D D D D

1

1 2

2

S 3D3V_PWR

1

3D3V_PWR PG4108 1 2

PC4115 PC4116 SCD1U50V3KX-GP

3D3V_S5

D

SC10U25V5KX-GP

PU4101 SIS412DN-T1-GE3-GP

S S S G

3

PC4114

84.00412.037 2nd = 84.08884.A37

SC10U25V5KX-GP

PU4103

DY

PWR_DCBATOUT_5V

D D D D

84.00412.037 2nd = 84.08884.A37 PU4104 SIS412DN-T1-GE3-GP

TC4101 SE47U25VM-14-GP

DY

D


SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U50V3KX-GP

SC10U25V5KX-GP


PC4111

2

PC4112 PC4109 PC4110

0R0402-PAD

Close to VFB Pin (pin5)

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A O/P cap: CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuti/ 17mOhm / 77.52271.09L H/S:SIS412DN-T1-GE3 / 24mOhm/[email protected] / 84.00412.037 L/S:SIS406DN-T1-GE3 / 11.5mOhm/[email protected] / 84.00406.037

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A O/P cap: CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuti/ 17mOhm / 77.52271.09L H/S:SIS412DN-T1-GE3 / 24mOhm/[email protected] / 84.00412.037 L/S:SIS406DN-T1-GE3 / 11.5mOhm/[email protected] / 84.00406.037

1

1

M14 DIS


3V/5V TPS51225 Size A2 Date: A

B

C

D

Document Number

Rev

A00

OAK14 Chief River DIS Wednesday, September 05, 2012 E

Sheet

41

of

105

5

4

3

2

1

SSID = CPU.Regulator

2

5V_S5

2

5V_S5

1

PR4210 0R0402-PAD

1

PR4209 0R0402-PAD

PU4201

5,27,38,40

PR4205 2 PR4206 2 PR4207 2 PR4208 2

1

48 D85V_PWRGD 8 H_CPU_SVIDCLK

PR4204 499R2F-2-GP

8 VR_SVID_ALERT# 8 H_CPU_SVIDDAT

0R0402-PAD 1 0R0402-PAD 1 0R0402-PAD 1 0R0402-PAD 1

VCCP

DY

PWR_VCORE_VR_ON P

2

PWR_VCORE_SCLK

3

PWR_VCORE_ALERT#

4

PWR_VCORE_SDA

5 6

H_PROCHOT# PR4211 2

1

NTCG_RC

3K83R2F-GP

PR4212 1

2

16KR2F-GP PR4213 1 2

NTC place near high side MOSFET of AXG Phase1 1

NTC_RC

1

3K83R2F-GP

C

1

PWR_VCORE_NTC

7 9

PR4217 2

0R0402-PAD 1PWR_VCORE_ISEN2

8

2nd = 69.60013.141 PR4215

PR4214 2

PWR_VCORE_NTCG

5V_S5

NTC-470K-8-GP

21

PWR_VCORE_SDA 2 130R2F-1-GP PWR_VCORE_ALERT# 2 75R2F-2-GP PWR_VCORE_SCLK PR4203 1 2 54D9R2F-L1-GP PR4202 1

2

SC1U10V3KX-3GP 2 1

PR4201 1 PC4201

VR_ON

PWM2

ALERT# BOOT1

PWR_VCORE_ISUMN

11

16

PWR_VCORE_BOOT1

19

PWR_VCORE_LGATE1

43

18

PWR_VCORE_PHASE1

43

17

PWR_VCORE_UGATE1

43

14

PWR_VCORE_COMP

13

PWR_VCORE_FB

12

PWR_VCORE_RTN

26

PWR_VCORE_BOOTG

25

PWR_VCORE_UGATEG

44

24

PWR_VCORE_PHASEG

44

23

PWR_VCORE_LGATEG

44

43

SDA VR_HOT#

LGATE1 PHASE1

NTCG NTC UGATE1 ISEN1 ISEN2 COMP

10

20

SCLK

2

16K9R2F-GP PR4216 1 2

43 C

ISUMP FB

43

ISUMN

NTC-470K-8-GP

NTC Place near high side MOSFET of Phase1

D

PC4203

VDD

VCCP_CPU

PWR_VCORE_VDD

PC4202

22

SC1U10V3KX-3GP 2 1

PR4202 confirm with EE have 75ohm or not

SC1U10V3KX-3GP 2 1

PWR_VCORE_VCCP

D

RTN

2nd = 69.60013.141

43

PR4219

VSUM_R

PC4204

SCD1U16V2JX-1-GP 2 1

PWR_VCORE_ISUMNG PC4205

32

ISUMPG

PGOOD UGATEG

27

PGOODG

475R2F-L1-GP

PC4206 PR4222 2

DY

1

RTNG

FBG

LGATEG

44

30

ISL95833HRTZ-GP

29

GND

2

33

2

PR4221 1

COMPG

PHASEG

43 PWR_VCORE_VSUMSCD1U16V2JX-1-GP 2 1

ISUMNG

BOOTG 15

PR4220 NTC-10K-26-GP

2nd = 69.60013.131

31

28

11KR2F-L-GP 2 1

PR4218

SCD068U16V2KX-GP 2 1

1

Place near choke of Phase1

2K61R2F-1-GP 2 1

43 PWR_VCORE_VSUM+

PC4207 2 1

ISUMN_RC

DY

649R2F-GP

PWR_VCORE_RTNG

SC2200P50V2KX-2GP

PWR_VCORE_FBG

44

44

B

PWR_VCORE_COMPG

PC4209


2

1K91R2F-1-GP

1

44 PWR_VCORE_VSUMG-

PR4229 1

PR4226

2

2nd = 69.60013.131

PR4228 1


44

3D3V_S5

2

3D3V_S5

2

VSUMG_R

PC4208

1K91R2F-1-GP

PR4224


11KR2F-L-GP 2 1

PR4223

SCD068U16V2KX-GP 2 1

1

Place near choke of AXG Phase1

2K61R2F-1-GP 2 1

44 PWR_VCORE_VSUMG+ B

475R2F-L1-GP

PC4210 PR4227 2

DY

1

ISUMNG_RC

PR4230

PC4211 2 1

1

DY

649R2F-GP

DY

2

IMVP_PWRGD

27,36

For GFX

IMVP_PWRGD

27,36

For VCCCORE

0R2J-2-GP

SC2200P50V2KX-2GP

A

A

M14 DIS


ISL95833_CPU_CORE(1/3) Size C Date: 5

4

3

2

Document Number OAK14 Chief River DIS

Rev A00


Sheet 1

42

of

105

5

4

3

2

1

SSID = CPU.Regulator

PWR_VCCCORE_DCBATOUT

GAP-CLOSE-PWR-3-GP PG4302 1 2 SC10U25V5KX-GP 2 1


PC4302

PC4303

SC10U25V5KX-GP 2 1

D


SC10U25V5KX-GP 2 1

PC4304

PC4305


VCC_CORE PL4301

42 PWR_VCORE_PHASE1

1 2 COIL-D36UH-3-GP-U

1 3 2 1

1

3

2

1 2

5 6 7 8

5 6 7 8 3 2 1

PG4312

PT4303 2

PT4304 2

ST470U2VDM-7-GP-U

PG4311

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

RJK03K5DPA-00-J5A-GP

S S S

S S S

4

G

G

4

D D D D

C


D D D D

GAP-CLOSE-PWR-3-GP

PT4301 2

PU4304

ST470U2VDM-7-GP-U

PU4303

ST470U2VDM-7-GP-U


68.R3610.20S 2nd = 68.R3610.20A 1

5 6 7 8

42 PWR_VCORE_UGATE1

1

S S S 3 2 1

S S S

4

G

G

4

3

SCD22U50V3ZY-1GP

Iccmax=33A IccTDC=25A OCP>40A

PU4302

3 2 1

2

GAP-CLOSE-PWR-3-GP PG4308 1 2 GAP-CLOSE-PWR-3-GP PG4309 1 2

PU4301

5 6 7 8 PC4301 1

RJK03J6DPA-00-J5A-GP

2D2R3-1-U-GP

BOOT1_RC

D D D D

42 PWR_VCORE_BOOT1


2


PR4301 1

D D D D


3

D

PWR_VCCCORE_DCBATOUT PG4301 1 2

SC10U25V5KX-GP 2 1

DCBATOUT

C

42 PWR_VCORE_LGATE1 PR4302 2

42 PWR_VCORE_VSUM+

PWR_VCORE_VSUM+_GAP

1 3K65R2F-1-GP PR4303

2

42 PWR_VCORE_VSUM-

PWR_VCORE_VSUM-_GAP

1 1R2F-GP

PR4304 1

42 PWR_VCORE_COMP

2

42K2R2F-L-GP 42 PWR_VCORE_FB PR4305 2

1

PC4306 FB_RC 1 2

499R2F-2-GP

2

SC470P50V-2-GP

SC47P50V2JN-3GP

PR4306 1

B

PC4307 1

PR4307 2

1COMP_RC

2

1K91R2F-1-GP

PC4308 2 1

267KR2F-GP

PC4309

PR4308 2COMP_R

1

B

SC150P50V2JN-3GP

1

2KR2F-3-GP

2 SC680P50V2KX-2GP VCCSENSE

8

VSSSENSE

8

PC4310 1

DY2

SC330P50V2JC-2-GP PC4311 1 2 SCD01U50V2KX-1GP R4301 2

42 PWR_VCORE_RTN

0R0402-PAD 1

A

A

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHK 0.36UH PCMC104T-R36MH 1.05mohm/ Isat =60A rms68.R3610.20S O/P cap: CHIP CAP EL 470U 2V 7.3*4.3 ESR=0.0045 3.8Arms Panasonic/79.47719.9BL H/S: RJK03J6DPA-00#J5A / 10mohm/[email protected]/ 84.00036.037 L/S: RJK03K5DPA-00#J5A / 3mohm/[email protected]/ 84.00035.037

M14 DIS


ISL95833_CPU_CORE(2/3) Size C Date: 5

4

3

2


Rev A00


Sheet 1

43

of

105

5

4

3

2

1

SSID = CPU.Regulator PWR_GFXCORE_DCBATOUT PG4401 1 2 GAP-CLOSE-PWR-3-GP PG4402 1 2

PWR_GFXCORE_DCBATOUT


SC10U25V5KX-GP 2 1


Iccmax=33A IccTDC=22A OCP>40A 68.R3610.20S PL4401

42 PWR_VCORE_PHASEG

VCC_GFXCORE

2nd = 68.R3610.20A 2

2 1

C

2

2

3 2 1

1

5 6 7 8

5 6 7 8 3 2 1

PG4410

PT4403 SE330U2D5VM-8-GP

PG4409

PT4402 ST330U2VDM-4-GP

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

S S S


G

S S S

4

PT4401 ST330U2VDM-4-GP

PU4404 D D D D

G


D D D D 4

1

COIL-D36UH-3-GP-U PU4403

1

1

2

42 PWR_VCORE_UGATEG

C

PC4405

1

5 6 7 8

PC4404

2

3 2 1


SCD22U50V3ZY-1GP

DY 4

S S S

2D2R3-1-U-GP

2

G

1

PC4403

PU4402

D D D D

BOOTG_RC


2

S S S

42 PWR_VCORE_BOOTG

4

PC4401

PR4401 1

G

GAP-CLOSE-PWR-3-GP PG4408 1 2 GAP-CLOSE-PWR-3-GP

PU4401

D D D D


3 2 1

5 6 7 8


PC4402

SC10U25V5KX-GP 2 1

D


SC10U25V5KX-GP 2 1

D

SC10U25V5KX-GP 2 1

DCBATOUT

77.53371.18L 2nd = 77.93971.03L

42 PWR_VCORE_LGATEG

PR4402 2

42 PWR_VCORE_VSUMG+

PWR_VCORE_VSUMG+_GAP

1 3K65R2F-1-GP PR4403

2

42 PWR_VCORE_VSUMG-

PWR_VCORE_VSUMG-_GAP

1 1R2F-GP

PR4404 1

42 PWR_VCORE_COMPG

2

150KR2F-L-GP 42 PWR_VCORE_FBG B

PR4405 1FBG_RC

2

499R2F-2-GP

AXG

Loadline

PC4406 1 2

2

SC470P50V-2-GP

SC47P50V2JN-3GP

PR4406

PR4064

1

PR4407 2

4.6mohm

1COMPG_RC2

2

2K55R2F-GP

GT1

267KR2F-GP

1

3.9mohm

PC4408 1 SC150P50V2JN-3GP

237ohm PR4408

GT2

B

PC4407 1

432ohm

PC4409 2COMPG_R 1 2

2KR2F-3-GP

PC4410 1

SC330P50V2KX-3GP

VCC_AXG_SENSE

9

VSS_AXG_SENSE

9

2

DY

SC330P50V2JC-2-GP PC4411 1

42 PWR_VCORE_RTNG

2

SCD01U50V2KX-1GP R4401 2

0R0402-PAD 1

A

A

M14 DIS

Wistron Corporation

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHK 0.36UH PCMC104T-R36MH 1.05mohm/ Isat =60A rms68.R3610.20S O/P cap: CHIP CAP 330U 2V EEFSX0D331XE 3.5Arms Panasonic/79.33719.20L H/S: RJK03J6DPA-00#J5A / 10mohm/[email protected]/ 84.00036.037 L/S: RJK03K3DPA-00#J5A / 4.9mohm/[email protected]/ 84.003K3.037

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

ISL95833_CPU_CORE(3/3) Size C Date:

5

4

3

2


Rev A00


Sheet 1

44

of

105

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p05v_pch/vccp_cpu 1D05V_PCH

1D05_VTT_PW R

PG4512 1 2

TPS51219 for 1D05V_VTT

D

VCCP_CPU

PG4520 1 2

GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP PG4513 1 2

D

PG4521 1 2

GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP PW R_DCBATOUT_1D05V

PG4514 1 2 PD4501 SDMK0340L-7-F-GP

GAP-CLOSE-PW R-3-GP

1

19,46,47,93 RUNPW ROK

PC4501 3D3V_S0 SC1U6D3V2KX-L-1-GP

DY

PR4502 1KR2F-3-GP 1 2

PG4525 1 2

1

GAP-CLOSE-PW R-3-GP

PG4524 1 2 GAP-CLOSE-PW R-3-GP

PG4504 1 2

GAP-CLOSE-PW R-3-GP

PW R_DCBATOUT_1D05V

PG4526 1 2

PR4567 10KR2J-3-GP

GAP-CLOSE-PW R-3-GP

17 16 15 14 13

5 6 7 8 3 2 1

1

1 2

2

84.003K3.037 2nd = 84.00312.037

DY

PR4524

PC4505

PT4501

DY

2D2R5J-1-GP

2

2nd = 77.93971.03L

2

1 2

151219_TRIP

PC4524 SC2200P50V2KX-YK-GP


PR4510 88K7R2F-GP

2

2

1 1 1

DY

DY

2

PC4511 SC1KP50V2KX-1GP

PR4509 10R2F-L-GP

SC1KP50V2KX-1GP

2

PC4510

51219_V5FILT

B

77.53371.18L

1

PR4508 3D3R2F-GP

S

1

1

5 6 7 8

COMP TRIP GND PGND SCD1U10V2KX-4GP

3 2 1

2

G

5V_S5

1 2 COIL-D36UH-3-GP-U

DPU4503

5 6 7 8

251219_COMP

1

2

51219_VCCIO_VSNS

2 1

1

1 2

1D05_VTT_PW R PL4501

SE330U2D5VM-8-GP

4

PC4508

1

Design Current = 13A 19.5A
SCD1U10V2KX-4GP

51219_VSSP_GSNS

TPS51219RTER-GP

GAP-CLOSE-PW R-3-GP

68.R3610.20S 2nd = 68.R3610.20A

51219_SW 51219_DH 51219_DL


DY

12 11 10 9

SW DH DL V5

S

S S S

DY


VREF REFIN GSNS VSNS

G

G

SCD1U10V2KX-4GP

B

PR4507 10K5R2F-GP

1 2 3 4

51219_REFIN

4

D D D D

PC4506

PR4506 8K25R2F-1-GP

GND PGOOD MODE EN BST

1

51219_VREF

DY

2 SCD1U25V3KX-GP

10KR2J-3-GP PU4501

1

S S S

2

2 PW R_LL_1 2D2R3-1-U-GP

1 PR4504

G

1

PC4504 PW R_VBST

C

PG4527 1 2

51219_GND_VCCP 2

51219_MODE

PR4505


D D D D

3D3V_S5


PU4502

D

SC10U25V5KX-GP

84.00036.037 2nd = 84.07698.037

SC10U25V5KX-GP

37,48 1D05V_VTT_PW RGD

PC4503

2

PC4502

1

2

GAP-CLOSE-PW R-3-GP

1

PG4503 1 2

PG4523 1 2

GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP

51219_EN

2

PR4501 100KR2F-L1-GP

GAP-CLOSE-PW R-3-GP

C

PG4515 1 2

2

PG4502 1 2

DY

GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP

A

1

K

2

PG4501 1 2

PG4522 1 2

2

DCBATOUT

VCCIO_SENSE_1

2 PG4505

1 GAP-CLOSE-PW R-3-GP

VCCIO_SENSE

2 PG4506

1 GAP-CLOSE-PW R-3-GP

VSSIO_SENSE 8

8 M14 DIS

A


I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHK 0.36UH PCMC104T-R36MH 1.05mohm/ Isat =60A rms68.R3610.20S O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L H/S: RJK03J6DPA-00#J5A / 10mohm/[email protected]/ 84.00036.037 L/S: RJK03K3DPA-00#J5A / 4.9mohm/[email protected]/ 84.003K3.037

Title

TPS51219 1D05V_VTT Size A3 Date:

5

4

A

3

2

Document Number

Rev


Sheet 1

A00 45

of

105

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p5v0p75v

1D5V_PW R

PG4608 1 2

D

DCBATOUT

VTTS

1

VTTGND

4

GND TPS51216RUKR-GP

74.51216.073

DY

84.003K3.037 2nd = 84.00312.037

1 2

S5

VDDR

VTTREF

Hi

Hi

On

On

S3

Lo

Hi

On

On

Off(Hi-Z)

S4/S5

Lo

Lo

Off

Off

Off

A

GAP-CLOSE-PW R-3-GP PG4617 1 2

1 1 2

2

1


DY

PT4603

GAP-CLOSE-PW R-3-GP PG4619 1 2 GAP-CLOSE-PW R-3-GP PG4620 1 2

77.53371.18L

2nd = 77.93971.03L


PW R_1D5V_VTTREF 1 PR4611 2 0R3J-0-U-GP

PR4607 19,27 PM_SLP_S4#

1

PW R_1D5V_EN

2 0R0402-PAD

1

1 DDR_VREF_S3

B

DY

GAP-CLOSE-PW R-3-GP

S3

2

2 PC4622 SC330P50V2KX-3GP

C


2


S0


GAP-CLOSE-PW R-3-GP

2

+0D75V_DDR_P 0D75V_S0 PG4601 1 2

State

PC4614 SC4D7U25V5KX-GP

2


1

1 2


1 2

1 2

DY

1D5V_PW R

1D5V_PW R

B


7

+0D75V_DDR_P



3

1

2

VTT

PR4612 2D2R5F-2-GP

TPS51216_PHS_SET

2

VTTIN VTTREF

PC4618 SCD22U10V2KX-1GP 21 GND

SC10U6D3V5KX-1GP

PW R_1D5V_VTTREF5


1 2


5 6 7 8 4

PW R_1D5V_VDDQS

DY



9

COIL-1UH-51-GP-U

3 2 1

VDDQS

PU4603


10


68.1R01C.10Q 2nd = 68.1R01B.10J

1

11

PGND

GAP-CLOSE-PW R-3-GP

2

2

DRVL

PW R_1D5V_DRVL

PL4601

1

1

PW R_1D5V_SW


13



PWR_1D5V_VDDQS

SW

SC10U6D3V5KX-1GP PC4617 2 1

2

PW R_1D5V_DRVH

SCD1U10V2KX-5GP PC4616 2 1

PR4602 97K6R2F-GP 1

200KR2F-L-GP 1

2

1 PR4608 2

TRIP

14

PC4615 2 1

2 1 PR4601 2

PW R_1D5V_TRIP 18

DRVH


SE330U2D5VM-8-GP

240R2F-1-GP 57K6R2F-GP

REFIN

X01 0605

MODE

2

RJK03K3DPA-00-J5A-GP S S S

2 PR4606 1

8

1

2D2R3-1-U-GP

VREF

PW R_1D5V_MODE 19

2

G

PC4602 SCD01U16V2KX-3GP 2 1

PW R_1D5V_VBST1

D D D D

PR4601_1

PC4603 SCD1U10V2KX-4GP 2 1

15

EN/PSV

PR4603 10KR2F-2-GP PW R_1D5V_REFIN


12 PR4605

VBST

16

PW R_1D5V_VREF 6

1

V5IN



68.R6810.20G Id=22~39A DCR=2.4~2.7mohm Size=10X11.5X4

3 2 1

VTTEN

5 6 7 8

PGOOD

17

PR4605_2

1


2

1 2 PW R_1D5V_EN

20

4

RJK03J6DPA-00-J5A-GP S S S

C

0D75V_EN

PU4602

G

PU4601

19,45,47,93 RUNPW ROK 37

84.00172.037 BSZ115N03MSC Id=20A, Qg=9.8nC, Rdson=8.9 mohm

D D D D

PR4604 20KR2F-L-GP

84.00036.037 2nd = 84.07698.037

D



5V_S5

3D3V_S0

+PW R_SRC_1D5V PG4603 1 2


+PW R_SRC_1D5V

1D5V_S3

VTT On

MODE

M14 DIS

PR4608

Frequency

200k ohm

400kHz

100k ohm

300kHz

68k ohm

300kHz

47k ohm

400kHz

Discharge Mode Tracking Discharge Non-tracking Discharge

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHOKE 1.0UH PCMB104T-1R0M/ 3.3mohm/ Isat =28A rms /68.1R01C.10Q O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L H/S: RJK03J6DPA-00#J5A / 10mohm/[email protected]/ 84.00036.037 L/S: RJK03K3DPA-00#J5A / 4.9mohm/[email protected]/ 84.003K3.037


TPS51216_+1.5V_SUS Size A3 Date:

5

4

3

A

2

Document Number

Rev



Sheet 1

46

A00 of

105

5

4

3

2

1

D

D

SYW231 for 1D8V_S0

3D3V_S5

D.C. =0.87A 1.29A < OCP <1.52A

PG4701 1 2

PW R_1D8V_PHASE 1 2 IND-1D5UH-71-GP-U

1

PW R_1D8V_FB

1 2

PC4705

1 2

PC4707


C

GAP-CLOSE-PW R-3-GP PG4707 1 2 GAP-CLOSE-PW R-3-GP

PW R_1D8V_EN

2 0R0402-PAD

1

1

1

PC4706

2

PR4702 19,27,36,37 PM_SLP_S3#

PR4707 49K9R2F-L-GP

R2

19,45,46,93 RUNPW ROK


1 2

R1 2

SYW 231ABC-GP

PR4703 102KR2F-GP

SC22P50V2JN-4GP

68.1R510.20J 2nd = 68.1R51B.10Q

PC4702

1

3 2 1

LX GND EN

SC10U6D3V3MX-GP

2

IN PG FB

PG4704 1 2

SC10U6D3V3MX-GP

2

4 5 6

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

PC4701

1

PW R_1D8V_VIN

GAP-CLOSE-PW R-3-GP C

1D8V_S0

PL4701

1


1D8V_PW R

PU4701


PR4705 1MR2F-GP PC4704 SC22P50V2GN-GP

Vo=0.6*(1+(R1/R2))

2

2

DY

B

B

M14 DIS A

A


SYW231_1D8V_S0 Size A3 Date: 5

4

3

2

Document Number

Rev


Sheet 1

47

A00 of

105

5

4

3

2

1

SSID = PWR.Plane.Regulator_0p85v 3D3V_S0

1

5V_S5

D

2

2 2

PC4812 SCD1U10V2KX-L1-GP

DY 1

D85V_PW RGD 42

0R0402-PAD

1

PW R_VCCSA_VID0

2

1D05V_VTT_PW RGD 37,45

2

1

9

VCCSA_SEL0

9

PC4818 SCD1U10V2KX-L1-GP

DY

0R0402-PAD

2

DY

VCCSA_SEL1

1

PR4801 PW R_VCCSA_EN

1

1 PR4811

PW R_VCCSA_VOUT PW R_VCCSA_SLEW

PR4812

2VCCSA_SENSE_L

1

0R0402-PAD

0.9 V

0

0

0.85 V

0

1

0.725 V

0.775 V

1

0

0.675 V

0.750 V

1

1

VCCSA_SENSE 9

2

1

2 1

2 0R0402-PAD

1 2

1

1 2

DY

PC4809 SC560P50V-GP

PR4814 10KR2F-2-GP

2

DY B


2

2

1

0.9 V 0.8 V

1

DY

1 2 PWR_VCCSA_COMP_1

VID[1]


2 100R2F-L1-GP-U

PR4810

PR4803 2D2R5F-2-GP

2

1 0D85V_S0

2

1PWR_VCCSA_SNUB 2

1

18 17 16 15 14 13 GND VREF COMP SLEW VOUT MODE 1 2 3 4 5 6

1

68.R2010.20B 2nd = 68.R2010.10Q

DY

SCD1U25V3KX-GP

PWR_VCCSA_COMP PWR_VCCSA_VREF

VID[0]

1 2 COIL-D2UH-2-GP

PC4808

PW R_VCCSA_SW

PU4801_MODE

B

C

0D85V_S0

SC22U6D3V5MX-2GP

TPS51463RGER-GP

74.51463.043

VCCSA_SEL Voltage Selection Table ULV Only

2 PL4801

PR4813 100KR2F-L1-GP

PR4802 4K99R2F-L-GP

XE, QC, SV

1

SC22U6D3V5MX-2GP

2

1

2

SC22U6D3V5MX-2GP

SC10U10V5KX-2GP

2

12 11 10 9 8 7

PC4811 SCD1U25V3KX-GP PW R_VCCSA_BST_R

PC4806

PC4813

BST SW#11 SW#10 SW#9 SW#8 SW#7

PW R_VCCSA_BST 1

PC4804

PC4815 SC10U6D3V5KX-1GP


1

2

C

PGND PGND PGND VIN VIN VIN GND

PR4807 0R3J-0-U-GP

PC4803

19 20 21 22 23 24 25

5V_S5

D.C. =4.2A 6.6A < OCP < 7.8A

PC4810 SC1U6D3V2KX-GP

V5DRV V5FILT PGOOD VID1 VID0 EN

PU4801

1

PWR_VCCSA_V5DRV

PR4804 0R0402-PAD 2 PR4805 1 2 0R0402-PAD

PW R_VCCSA_VID1

2

1 1 2

PR4808

1

PWR_VCCSA_PGOOD

PC4816 SC2D2U10V3KX-1GP

2

2

SC1U6D3V2KX-GP

1 PR4806 1R2F-GP

D

PR4809 4K7R2J-2-GP PC4814

TPS51463 for ULV A

PR4813

700KHz

100K

0.85

1MHz

Open

0.85

1

VID0=0;VID1=1 (V)

SW frq


M14 DIS

A


TPS51463_VCCSA Size A3 Date: 5

4

3

2

Document Number

Rev



Sheet 1

48

of

A00 105

SSID = VIDEO R4910 0R2J-2-GP 2

1 3D3V_LCD_ROM LCD_TST_C LVDS_DDC_CLK LVDS_DDC_DATA LVDSA_DATA0#_C LVDSA_DATA0_C

RN4902 LVDS_DDC_DATA_R LVDS_DDC_CLK_R

4 3

1 2

3D3V_S0

C4904 SRN2K2J-1-GP

SC1U6D3V2KX-GP

2


2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

LCDVDD 22

DBC_EN

1

2

1

41

1

DBC_EN_R

LCD1

LVDSA_DATA1#_C LVDSA_DATA1_C

RN4903 SRN33J-5-GP-U 3 2 4 1

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

17 17

RN4907 DMIC_CLK_C DMIC_DATA_C

1 2

4 3

FFC

LVDSA_DATA2#_C LVDSA_DATA2_C

SRN0J-6-GP

LVDSA_CLK#_C LVDSA_CLK_C LVDSB_DATA0#_C LVDSB_DATA0_C DMIC_CLK_C LVDSB_DATA1#_C LVDSB_DATA1_C DMIC_DATA_C LVDSB_DATA2#_C LVDSB_DATA2_C

RN4908 DMIC_CLK_C DMIC_DATA_C

2 1

USB_CAMERA# USB_CAMERA

SRN33J-5-GP-U RN4904 2 3 Wire 4 1

LVDSB_CLK#_C LVDSB_CLK_C

3 4

Wire

DMIC_CLK 29 DMIC_DATA 29


SRN0J-6-GP RN4906 3 4

INVERTER POWER

3D3V_CAMERA_S0

SRN0J-6-GP

800mA

DCBATOUT DCBATOUT_LCD

42

DCBATOUT_LCD

F4901 POLYSW-1D1A24V-GP-U 1 2

R4905 100KR2J-1-GP 1 2 1 2 3 4

USB_CAMERA#

8 7 6 5

BKLT_CTRL

LCD_TST

27

BLON_OUT

27

2nd = 69.50007.D31

C4905 SCD1U50V3KX-GP

C4906

DY

SC1KP50V2KX-1GP

USB_CAMERA#_R

69.50007.A31

RN4901

LCD_TST_C LCD_BRIGHTNESS BLON_OUT_C

2

ACES-CON40-10-GP

20.K0617.040 Close to LCD connector

1

FFC

20R2J-2-GP

Wire

2

2 1 R4927 1

1

USB_CAMERA#_R USB_CAMERA_R 3D3V_CAMERA_S0_R LCD_BRIGHTNESS BLON_OUT_C

3rd = 69.50007.A41

SRN100J-4-GP

TR4901

3D3V_CAMERA_S0 20R2J-2-GP

CAM1 10

D4902

FILTER-4P-6-GP

BKLT_CTRL

L_BKLT_CTRL

17

3 1

69.10103.041

2

USB_CAMERA_R

KBC_BKLT

USB_CAMERA R4931 10KR2J-3-GP

3D3V_S0

8 7 6 5 4 3 2

27

BAT54CPT-GP

2 1

USB_CAMERA#_C_IO USB_CAMERA_C_IO

3 4

FFC

DMIC_DATA 29 DMIC_CLK 29

SRN33J-5-GP-U RN4905

2

83.R2003.E81 2ND = 83.00054.Q81

5V_S0

RN4909 DMIC_DATA_C_IO DMIC_CLK_C_IO

1

1

USB_CAMERA#_C USB_CAMERA_C

1

1 2

9

DY

TPNL1 4 3

FFC

7


1

DY

1

R4909 0R3J-0-U-GP

R4928 0R3J-0-U-GP

USB_PN5_TPNL

2

2

R4932 1

4

Wire

2

2

3

1

USB_PN5 18

R4930 0R3J-0-U-GP

TPNL_PWR

1

SRN0J-6-GP ACES-CON8-4-GP-U1

For EMI request

3D3V_S0

R4901 LVDSA_CLK

LCD_BRIGHTNESS

LVDSA_CLK#

LCD_TST_C

1

F4902

2

DY

Close to Camera connector

0R3J-0-U-GP

2 1

2 3 4 5 6

20.F0772.008

3D3V_LCD_ROM

USB_PN5_TPNL USB_PP5_TPNL

8

FUSE-2A32V-16-GP

ETY-CON6-21-GP USB_PP5_TPNL USB_CAMERA#_C_IO

2

USB_CAMERA#_C

DY

4

2

EC4903 DY SC33P50V2JN-3GP

2

0R3J-0-U-GP

1

1

2 FILTER-4P-6-GP


LVDSB_CLK#

17

LVDSB_DATA2#_C

0R0402-PAD

2

SSID = VIDEO

69.10103.041 USB_CAMERA_C_IO

R4913 1

FFC

3 2

USB_CAMERA_C

R4915 1

LVDSB_DATA2#

17

LVDSB_DATA1#_C

0R0402-PAD

2

R4917 1

LVDSB_DATA1#

17

LVDSB_DATA0#_C

0R0402-PAD

2

1

LVDSB_DATA0# 17

0R0402-PAD

D4901 17 LVDS_VDD_EN

1 LCDVDD_EN

3 2 BAT54CPT-GP

17

LVDSB_DATA2_C

0R0402-PAD

2

R4916 1

LVDSB_DATA2 17

LVDSB_DATA1_C

0R0402-PAD

2

LVDSB_DATA1 17

LVDSB_DATA0_C

0R0402-PAD

2

1 2 3 1

LVDSB_DATA0 17

0R0402-PAD

Layout Note: Trace width = 80mil

R4921 LVDSA_CLK#_C

2

R4919 1

LVDSA_CLK#

17

LVDSA_DATA2#_C

0R0402-PAD

2

R4923 1

LVDSA_DATA2#

17

LVDSA_DATA1#_C

0R0402-PAD

2

LCDVDD

R4918 1

EN GND VOUT

VIN#5 VIN#4

5 4 1

LVDSB_CLK


1

R4914 1

U4901

2

R4912 2

3D3V_S0 R4907 100KR2J-1-GP

1

83.R2003.E81 2ND = 83.00054.Q81

LVDSB_CLK_C

600mA

2

27 LCD_TST_EN

RT9724GB-GP

1

2

USB_PP5 18

TR4910 R4906 1

R4911 LVDSB_CLK#_C

1

R4929 0R3J-0-U-GP

3D3V_CAMERA_S0

DY 2

1

3D3V_S0

1

DY

EC4902

SC33P50V2JN-3GP 2

1

EC4901

SC33P50V2JN-3GP 2

1

EC4905

SC33P50V2JN-3GP 2

1 2

2


SC4D7P50V2CN-1GP

1

LCD_TST EC4907


2

Close to LVDS connector


74.09724.09F

R4925 1

LVDSA_DATA1#

17

LVDSA_DATA0#_C

0R0402-PAD

2

1

LVDSA_DATA0# 17

0R0402-PAD

M14 DIS

Wistron Corporation R4922 LVDSA_CLK_C

2

R4920 1

0R0402-PAD

LVDSA_CLK

17

LVDSA_DATA2_C

2

R4924 1

0R0402-PAD

LVDSA_DATA2 17

LVDSA_DATA1_C

2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

R4926 1

0R0402-PAD

LVDSA_DATA1 17

LVDSA_DATA0_C

2

1

LVDSA_DATA0 17

Title

LCD Connector

0R0402-PAD Size A2 Date:

Document Number

Rev



Sheet

49

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A

M14 DIS


CRT Connector Size A3 Date: 5

4

3

2

Document Number

Rev


Sheet 1

50

of

A00 105

5

4

3

2

1

SSID = VIDEO R5101 HDMI_CLK_R_C#

2

HDMI Level Shifter 1 1

2 2

SCD1U10V2KX-5GP SCD1U10V2KX-5GP

HDMI_CLK_R_C# HDMI_CLK_R_C

C5105 C5106

1 1

2 2


HDMI_DATA0_R_C# HDMI_DATA0_R_C

C5110 C5107

1 1

2 2



2 2



1

C5103 C5104

R5114 150R2F-1-GP

R5116 150R2F-1-GP D

R5102 HDMI_CLK_R_C

2

2

1

1 2 3 4 2

HDMI_DATA1_R_C#_CON

1

R5117 150R2F-1-GP

2

DY 0R2J-2-GP

C

R5106 HDMI_DATA2_R_C

2

R5108 HDMI_DATA2_R_C_CON

1

HDMI_DATA1_R_C

2

0R0402-PAD

HDMI_DATA1_R_C_CON

1

HDMI CONN

0R0402-PAD

2

S

1

HDMI_DATA1_R_C#

0R0402-PAD

R5115 150R2F-1-GP

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

G

R5107 HDMI_DATA2_R_C#_CON

1

1

D

Q5105 2N7002BK-GP

2

HDMI_DATA0_R_C_CON

1

0R0402-PAD

0R0402-PAD

R5123 5V_S0

R5113 100KR2J-1-GP

2

R5105 HDMI_DATA2_R_C# RN5107 SRN680J-GP

1 2 3 4

HDMI_PLL_GND

DY

HDMI_DATA0_R_C

0R0402-PAD

RN5106 SRN680J-GP

C

R5104 HDMI_CLK_R_C_CON

1

2

1 1

8 7 6 5

17 HDMI_DATA2_R# 17 HDMI_DATA2_R

1

C5108 C5109

8 7 6 5


HDMI_DATA0_R_C#_CON

1

0R0402-PAD

2


2

0R0402-PAD

2

D

HDMI_DATA0_R_C#

1

17 HDMI_CLK_R# 17 HDMI_CLK_R

R5103 HDMI_CLK_R_C#_CON

1

5V_S0

3

HDMI1 D5101 BAW 56-2-GP

HDMI_DATA2_R_C_CON

HDMI_DATA1_R_C#_CON HDMI_DATA0_R_C_CON HDMI_DATA0_R_C#_CON HDMI_CLK_R_C_CON HDMI_CLK_R_C#_CON

3D3V_S0 RN5101 SRN2K2J-1-GP

5V_HDMI_S0

5V_S0

17 PCH_HDMI_CLK

1 2 3

5

2

6

1

5V_HDMI_S0_R

R5109 DDC_CLK_HDMI

1

DDC_CLK_HDMI DDC_DATA_HDMI

5V_HDMI_S0_R

F5101

2 0R0603-PAD

1

2

FUSE-1D1A6V-4GP-U


69.50007.691 2nd = 69.50007.771

DDC_DATA_HDMI

3D3V_S0

3


R5125 0R0402-PAD 1 2

HDMI_HPD_E

1

17 HDMI_PCH_DET

1 HDMI_HPD_B 2 2

Q5102 PMBS3904-1-GP

R5111 150KR2F-L-GP 1

1

17 PCH_HDMI_DATA

22.10296.311

HPD_HDMI_CON

2N7002KDW -GP

B

SKT-HDMI23P-2-GP

2

B

4

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23

HDMI_DATA2_R_C#_CON HDMI_DATA1_R_C_CON

2nd = 83.00056.N11

1

4 3DDC_DATA_PH2 1

DDC_CLK_PH1

2

83.00056.G11

Q5104

22 20 1

84.03904.L06 2nd = 84.03904.P11

R5110 200KR2J-L1-GP

DY

2

2

R5112 10KR2J-3-GP M14 DIS

A

A


HDMI Level Shifter/Connector Size A3 Date: 5

4

3

2

Document Number

Rev


Sheet 1

51

of

A00 105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

52

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

LVDS_Switch

Rev


Sheet 1

53

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

54

A00 of

105

5

4

3

2

1

SSID = User.Interface

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

ITP/Fan Connector

Document Number

Rev


Sheet 1

55

A00 of

105

SSID = SATA

SATA HDD Connector HDD1

V5 V5 V5

P13 P14 P15

V12 V12 V12


2 2

1 C5602 1 C5603

HDD_RXP_C_PCH_TXP0 HDD_RXN_C_PCH_TXN0

S2 S3

A+ A-


1 1

2C5615 2C5616

HDD_TXP_PCH_RXP0 HDD_TXN_PCH_RXN0

S6 S5

B+ B-

23 24

23 24

NP1 NP2

NP1 NP2

GND GND GND GND GND GND GND GND

S1 S4 S7 P4 P5 P6 P10 P12

DAS/DSS

P11

1A 5V_S0

550mA 3D3V_S0

DY


5V_S0

P7 P8 P9

V33 V33 V33

2 1 C5601 SC10U6D3V5KX-1GP

21 PCH_RXP_C_HDD_TXP0 21 PCH_RXN_C_HDD_TXN0

P1 P2 P3

2 1 C5605 SC10U10V5ZY-1GP 2 1 C5606 SCD1U10V2KX-5GP

21 PCH_TXP_HDD_RXP0 21 PCH_TXN_HDD_RXN0

3D3V_S0

DY

SKT-SATA7P-15P-27-GP-U

Close to HDD1

22.10300.991

SATA Zero Power ODD

ODD_PW R_5V 3D3V_S0

14 NP1

U5601 SY6288CCAC-GP

R5607 SATA_ODD_PW RGT

2R5602 0R2J-2-GP

2 SCD01U16V2KX-3GP 2 SCD01U16V2KX-3GP

1


EN/EN# OCB IN#3 OUT#6 IN#2 OUT#7 GND OUT#8

5 6 7 8

ODD_PW R_5V

100 mil C5610

SC10U6D3V5KX-1GP 74.02001.079 2nd = 74.06288.079 3rd = 74.02311.079

PCH_TXN_ODD_RXN4 21 PCH_TXP_ODD_RXP4 21

Current limit Active High typ =>2.5A

R5604

DY 10KR2J-3-GP

When the drive is powered on, the FET to the MD/DA pin drive is OFF. When the drive is powered off, the FET to the MD/DA pin is ON

2

3D3V_S0

2

3D3V_S0

R5605 100KR2J-1-GP

A00-0408 Add R5606 to pull high 3.3V_S0 Change pull high to 3.3V_S0 A00-0415 Dummy R5606

4 S1

3

DY

D1

5

SATA_ODD_DA#_C

G1

ODD_PWRGT#

6

R5606 10KR2J-3-GP

1

DY

1

DY

D2

22.10300.581

PCH_RXP_C_ODD_TXP4 21 PCH_RXN_C_ODD_TXN4 21

G2

SKT-SATA7P-6P-130-GP

SUPPORT ZERO SATA ODD

S2

NP2 15

4 3 2 1

1

ODD_RXN_C_PCH_TXN4 C5611 1 ODD_RXP_C_PCH_TXP4 C5612 1

follow CKL1.5

SATA_ODD_PRSNT# 22

2SCD01U16V2KX-3GP 2SCD01U16V2KX-3GP

ODD_PW R_5V

5V_S0

2

ODD_TXP_PCH_RXP4 C5608 1 ODD_TXN_PCH_RXN4 C5607 1

1 100KR2J-1-GP

SATA_ODD_PRSNT#

1

2

SATA_ODD_DA# 18

2

1

1

SATA_ODD_DA#_C

2

6 5 4 3 2

S7 S6 S5 S4 S3 S2 S1

2.5A

22 SATA_ODD_PW RGT

1

ODD1

2

ODD Connector

Q5601 ME2N7002DKW -G-GP

M14 DIS

84.2N702.F3F 2nd = 84.2N702.A3F 3rd = 84.DMN66.03F


SATA_ODD_PW RGT

SATA_ODD_DA#

HDD/ODD Size A3 Date:

Document Number

Rev



Sheet

56

A00 of

105

5

4

3

2

1

SSID = ESATA

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

ESATA Document Number

Rev


Sheet 1

57

A00 of

105

5

4

3

2

1

SSID = AUDIO X01 0605

Layout Note:

Speaker

MIC_JACK_R

trace width=30mil

D

AUD_PORTA_L_R_B

R5801~R5804 and EC5804~EC5806 near codec as possible

SPK1

AUD_PORTA_R_R_B

1

AUD_SPK_R+_C R5804 1

2 0R0603-PAD

AUD_SPK_R+ 29

5

D5801

2

DY 1

DY 1

SC1KP50V2KX-1GP EC5806

2

DY 1

2 1

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C AUD_SPK_R+_C


1 1 1 1


SC1KP50V2KX-1GP EC5804 1 2


C

DY

DY

DY

D5804

DY

AZ2025-01H-GP-U

DY

D5803 AZ2025-01H-GP-U

20.F0772.004

D5802 AZ2025-01H-GP-U

AZ2025-01H-GP-U

ACES-CON4-7-GP-U

2

AUD_SPK_L- 29 AUD_SPK_L+ 29 AUD_SPK_R- 29

1

2 0R0603-PAD 2 0R0603-PAD 2 0R0603-PAD

2

R5801 1 R5802 1 R5803 1

1

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C

1

4 3 2

2

AUD_SENSE

6

2

D

C

AUD_AGND

Combo Jack

R5808 1

change to 22.10270.P81, but symble not change

2 2K2R2J-2-GP

MIC2-VREFO 29

HPMIC1

JACK_POWER

2 0R3J-0-U-GP 2 0R3J-0-U-GP

R5809 1

AUD_PORTA_R_R_B

2 20KR2F-L-GP

DY

R5807 1

R5813 1

20R3J-0-U-GP

AUD_HP1_JACK_R1

SLEEVE 29 AUD_HP1_JACK_L 29

R5811 1

218R2F-1-GP

AUD_HP1_JACK_R 29

SLEEVE

D

DY

2

B

COMBO-GPI 29

R5817 22KR2J-GP

1

R5816 22KR2J-GP


2

EC5807

1

2

Q5801 2N7002K-2-GP

EC5805

SC100P50V2JN-3GP 2 1

S

G

1

DY 2

1 2

AUD_AGND

R5805 47KR2F-GP

DY

C5806


29 AUD_HP1_JACK_R1

SC10U6D3V3MX-GP

AUD_AGND

218R2F-1-GP

29 AUD_HP1_JACK_L1

AUD_AGND EC5808

22.10270.P81

R5810 1

3D3V_S0

2 0R3J-0-U-GP

JACK_JD

AUDIO-JK363-GP

AUD_HP1_JACK_L1


5 6 2 4 7

B

R5814 1 R5806 1

1

MIC_JACK_R AUD_PORTA_L_R_B

3 1

AUD_AGND AUD_AGND

M14 DIS AUD_AGND R5812 1

2 0R3J-0-U-GP

AUD_AGND

AUD_SENSE 29

Wistron Corporation

A


Speaker/HPMIC CONN

Size A4

Document Number



4

3

2

Sheet

58

A00 of

1

Rev 105

A

5

4

3

2

1

SSID = LOM

D

D

LAN TransFormer X01 0605

XF5901 Rx Side

8

MDO1-

11

6

MCT1

31 LAN_MDI1P

10

7

MDO1+

31 LAN_MDI0N

15

2

MDO0-

14

3

MCT0

16

1

MDO0+

9

31 LAN_MDI1N

U5901 TVLST2304AD0-GP

MCT1

LAN_MDI1N

6

LAN_MDI1P

4

LAN_MDI0N

3

LAN_MDI0P

1

1CT:1CT MCT0

Tx Side

LOM_TCT

31 LAN_MDI0P

5

C

1CT:1CT

83.02304.0AE 2nd = 83.42236.0AE 3rd = 83.08902.0AE 4th = 83.09904.AAE

XFORM-12P-36-GP

68.HD081.30B

1 2

2

DY C


B

B

RJ45 RJ45 MDO0+ MDO0MDO1+ MCT0 MCT1

MDO1-

5 6 7 8

A

9 1

CHASSIS

2 3 4 5 6 7 8 10

MDO1+ MDO1MDO0+ MDO0-

1 1 1 1


A

Wistron Corporation

CHASSIS

RJ45-8P-123-GP

RN5901 SRN75J-1-GP


22.10019.161 Title

4 3 2 1 C5907 2

MCT 1 SC100P3KV8JN-GP

Size A3

78.1013N.14L

Date: 5

4

3

2

Document Number

XFOM&RJ45

Rev


Sheet 1

59

A00 of

105

5

4

3

2

1

SSID = Flash.ROM SPI Flash ROM(8M) for PCH 3D3V_S5

1


D

1

3D3V_S5

4 3

2

D


RN6001 SRN4K7J-8-GP

PCH

1 2

1

R6003 4K7R2J-2-GP

2

2

DY

SPI_HOLD_0#

DY 72.25Q64.B01 2nd = 72.25640.D01 EC6003 3rd = 72.25Q64.F01 4th = 72.25Q64.D01 SC4D7P50V2CN-1GP 2

DY

KBC

1

W 25Q64CVSSIG-GP

2


SPI_CLK_R 21,27 SPI_SI_R 21,27

DY 2

1

SPI_W P#

8 7 6 5

CS# VCC DO/IO1 HOLD#/IO3 WP#/IO2 CLK GND DI/IO0

1

1 2 3 4

SPI

3D3V_S5

U6001 21,27 SPI_CS0#_R 21,27 SPI_SO_R


Layout Note: KBC----10"----PCH KBC----1.5"~6.5"----SPI PCH----0.5"~6.5"----SPI

C

C

SSID = RBATT 3D3V_AUX_S5 B

B

RTC_AUX_S5

D6001

2

+RTC_VCC R6002 1KR2J-1-GP 1 2

3 2

1

RTC1

TP6001

CH715FPT-GP

1

1


RTC_PW R

83.R0304.B81 2nd = 83.00040.E81

1 2 NP1 NP2

PWR GND NP1 NP2 BAT-AAA-BAT-054-P04-GP-U1

62.70001.061 +RTC_VCC R6006 100R2J-2-GP

1

DY

1

TP6002

2

1

G

RTC_PW R

R6007 10MR2J-L-GP

A

D

M14 DIS

A

RTC_DET# 22

2

S

Wistron Corporation

Q6002 2N7002BK-GP


84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

Title

Flash/RTC Size A3 Date:

5

4

3

2

Document Number

Rev


Sheet 1

60

of

A00 105

5

4

3

2

1

USB30_VCCA

2A 1

USB_OC#0_1 18 USB30_VCCB USB30_VCCA

TC6105

AP2182SG-13-GP

74.02182.071

1

8 7 6 5

77.52271.09L

USB3.0 Port1

C6111

2

1

USB_PWR_EN#

2

27

FLG1 OUT1 OUT2 FLG2

SC1U10V3KX-3GP


GND IN EN1# EN2#

SE220U6D3VM-30-GP

D

U6102 1 2 3 4

2

5V_S5

D

USB30_VCCB

1 2

1 2

1 2

2

TC6104 SC100U6D3V6MX-GP

SCD1U10V2KX-4GP C6109

SC1U10V3KX-3GP C6108

C

SCD1U10V2KX-4GP C6107

1

2A USB3.0 Port2

78.10710.52L C

Right USB Power x1 5V_S5

Support 2A +5V_USB1

2A

U6101

TPS2000CDGNR-GP

74.02000.B71

78.10710.52L

1

DY 2

SC1U10V3KX-3GP

1 2

1 2

DY

SCD1U10V2KX-5GP

FLT#

1 9

100KR2J-1-GP

2

SCD1U10V2KX-5GP

5

18 USB_OC#4_5

GND GND

1

EN/EN#

2

4

TC6102 SC100U6D3V6MX-GP

27 USB_PWR_EN#

6 7 8

C6122

C6101 B

OUT#6 OUT#7 OUT#8

C6121

IN#2 IN#3

at least 40 mil R6101

2 3

1

at least 80 mil

B

M14 DIS

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size

Document Number

USB Power SW

Rev

OAK14 Chief River DIS Date: Wednesday, September 05, 2012 5

4

3

2

Sheet

61

A00 of

1

105

A

5

4

3

2

SSID = USB 18

1

USB3.0 Port1

USB20_DN1_C

USB_PN1

U6204 USB20_DN1_C USB20_DP1_C USB30_RXDP2_C USB30_RXDN2_C

TR6204 D

1

2

4

3

1 2 3 4

FILTER-4P-6-GP

I/O_1 I/O_2 I/O_3 I/O_4

USB20_DN1_C USB30_VCCA USB20_DP1_C

USB30_VCCA

DY

VDD GND I/O_6 I/O_5

8 7 6 5

D

USB30_VCCA

TVW MSOP06AD0-GP USB1

83.00060.0AJ 1

VBUS

USB30_RXDN2_C USB30_RXDP2_C

5 6

STDA_SSRXSTDA_SSRX+

USB30_TXDN2_C USB30_TXDP2_C

8 9

STDA_SSTXSTDA_SSTX+

12 13

CHASSIS#12 CHASSIS#13

USB20_DP1_C

USB_PP1

C6222

1

18 USB3_TX2_P

2

R6281 USB30_TXDP2_R

2

R6283

1

USB30_TXDP2_C

18

2

USB3_RX2_P

0R0402-PAD

SCD1U10V2KX-5GP

AFTP6204 AFTP6205 AFTP6209

USB30_TXDP2_C USB30_TXDN2_C

69.10103.041

18

1 1 1

USB30_RXDP2_C

1

0R0402-PAD

DD+

2 3

GND_DRAIN

7

GND GND GND

USB20_DN1_C USB20_DP1_C

10 11 4

SKT-USB13-18-GP-U

22.10339.331 AFTP6218

1

C

C

C6223

1

18 USB3_TX2_N

2

R6282 USB30_TXDN2_R

2

R6284

1

USB30_TXDN2_C

18

2

USB3_RX2_N

0R0402-PAD

SCD1U10V2KX-5GP

USB30_RXDN2_C

1

0R0402-PAD

USB3.0 Port2 18

USB20_DN0_C

USB_PN0

USB30_VCCB USB20_DN0_C USB20_DP0_C

USB30_VCCB U6205 USB20_DN0_C USB20_DP0_C USB30_RXDP1_C USB30_RXDN1_C

TR6207

1

2

4

3

1 2 3 4

I/O_1 I/O_2 I/O_3 I/O_4

DY

VDD GND I/O_6 I/O_5

8 7 6 5

USB30_TXDP1_C USB30_TXDN1_C USB30_VCCB

TVW MSOP06AD0-GP

FILTER-4P-6-GP

USB2

69.10103.041

83.00060.0AJ

1

VBUS

USB30_RXDN1_C USB30_RXDP1_C

5 6

STDA_SSRXSTDA_SSRX+

USB30_TXDN1_C USB30_TXDP1_C

8 9

STDA_SSTXSTDA_SSTX+

12 13

CHASSIS#12 CHASSIS#13

B

18

DD+

2 3

GND_DRAIN

7

USB20_DP0_C

USB_PP0

C6225

1

18 USB3_TX1_P

2

R6287 USB30_TXDP1_R

SCD1U10V2KX-5GP

2

R6289

1

AFTP6210 AFTP6211 AFTP6212

1 1 1

USB30_TXDP1_C

18

USB3_RX1_P

0R0402-PAD

2

GND GND GND

USB20_DN0_C USB20_DP0_C

B

10 11 4

SKT-USB13-18-GP-U

1

USB30_RXDP1_C

22.10339.331

0R0402-PAD AFTP6217

1

M14 DIS

A

C6224

1

18 USB3_TX1_N

2

R6288 USB30_TXDN1_R

SCD1U10V2KX-5GP

2

A

R6290

1

USB30_TXDN1_C

0R0402-PAD

18

USB3_RX1_N

2

1

USB30_RXDN1_C


0R0402-PAD Title Size A3 Date:

5

4

3

2

Document Number

USB 3.0

Rev


Sheet 1

62

A00 of

105

5

4

3

2

1

SSID = USB

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

USB3.0 PORT

Rev


Sheet 1

63

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A

M14 DIS


4

3

2

RESERVED

Document Number

Rev



Sheet 1

64

A00 of

105

5

4

3

WLAN1 6

1.5V

3D3V_S0

2

3.3V

1D5V_S0

28 48

+1.5V +1.5V

3D3V_S0

52

+3.3V

24

+3.3VAUX

3 5 8 10 12 14 16 17 19 20 37 39 41 43 45 47 49 51

RESERVED#3 RESERVED#5 RESERVED#8 RESERVED#10 RESERVED#12 RESERVED#14 RESERVED#16 RESERVED#17 RESERVED#19 RESERVED#20 RESERVED#37 RESERVED#39 RESERVED#41 RESERVED#43 RESERVED#45 RESERVED#47 RESERVED#49 RESERVED#51

42 44 46

LED_WWAN# LED_WLAN# LED_WPAN#

1

TP6506

20R2J-2-GP E51_RX 20R2J-2-GP E51_TX

R6513 1 R6512 1

E51_RXD E51_TXD

WLAN_ACT BT_ACT

27 WIFI_RF_EN 2

C

3D3V_S0

27 BLUETOOTH_EN

R6514 5V_S0

R6504

1

2 0R2J-2-GP

DY

1

2+5V_MINI_DEBUG 0R2J-2-GP

R6516 0R2J-2-GP 1 2

27 CARD_WLAN_OUT# 27 CARD_WPAN_OUT#

DEBUG

SKT-MINI52P-81-GP

1.1A 1D5V_S0

B

DY

A

SCD1U25V2KX-GP 2 1

SCD1U25V2KX-GP 2 1

WLAN_ACT C6508

PERN0 PERP0

23 25

PCIE_RXN3 PCIE_RXP3

20 20

PETN0 PETP0

31 33

PCIE_TXN3 PCIE_TXP3

20 20

USB_DUSB_D+

36 38

SMB_CLK SMB_DATA

30 32

WAKE# CLKREQ# PERST#

1 7 22

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

4 9 15 18 21 26 27 29 34 35 40 50 53 54

USB_PN11_R USB_PP11_R

CLK_PCIE_WLAN_REQ# 20 PLT_RST# 5,18,27,31,71,83

C

R6506 0R0603-PAD 1 2

USB_PN11 18

R6505 0R0603-PAD 1 2

USB_PP11 18

B

USB_PP11_R

M14 DIS

DY


MINICARD(WLAN)/ITP CONN

Size A4

Document Number



D

C6506

5V_S5

C6501

CLK_PCIE_WLAN 20 CLK_PCIE_WLAN# 20

SCD1U10V2KX-5GP

1

DY 2


1

DY 2


1 2

SC10U6D3V5KX-1GP

1

C6503

2

SCD1U10V2KX-5GP

2

1

USB_PN11_R C6502

13 11

62.10043.C81

375mA

3D3V_S0

REFCLK+ REFCLK-

NP1 NP2

1D5V_S0

NP1 NP2

D

27 27

1

Mini Card Connector(802.11a/b/g)

SSID = Wireless

R6515 0R2J-2-GP BT_ACT 1

2

4

3

2

Sheet

65

A00 of

1

Rev 105

A

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

66

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

67

A00 of

105

5

4

3

2

1


Wireless LED FRONT POWER LED Low actived from KBC GPIO

Low actived from KBC GPIO 5V_S0

5V_S5 Q6805

2

1

FPOW ER_LED_A 1 A

330R2J-3-GP

DY EC6801 SC220P50V2KX-3GP

W LAN_LED_R

C

1

W LAN_LED_A

DY

1A

D

K2

LED-W -27-GP

330R2J-3-GP

84.00144.P11 2nd = 84.DT144.A11

2nd = 83.00110.R70 3rd = 83.01105.070

2

2

PDTA144VT-GP

LED-W -27-GP

83.01221.R70

1

84.00144.P11 2nd = 84.DT144.A11

K2

R6808

83.01221.R70

1

LED_PW R

C

PDTA144VT-GP

W LED1

E

2

R1

27 PW RLED#

R6806

3

R2

B

B

27 W LAN_LED#

3

PLED1

E

R1

Q6801

R2

D


2nd = 83.00110.R70 3rd = 83.01105.070

Place EC6806 near WLED1

C

Power button

SATA HDD LED(White) Low actived from PCH GPIO

C

PW RBT1 5V_S0

6 HDLED1

E 2

1A

HDD_LED_A

K2

AFTP6801

1

83.01221.R70 2nd = 83.00110.R70 3rd = 83.01105.070

R1

2


1

DY

LED-W -27-GP


84.00144.P11 2nd = 84.DT144.A11

1

330R2J-3-GP

KBC_PW RBTN#_C

1 2 R6802 100R2J-2-GP

2

SATA_LED_R

PDTA144VT-GP

27 KBC_PW RBTN#

3

R2

C

R6812

1

Q6802

B

21 SATA_LED#

4 3 2 1 5 ETY-CON4-34-GP

20.K0465.004

1

AFTP6802

Battery LED1 (AMBER_LED) Low actived from KBC GPIO B

B

5V_S5 Q6804 R2 R1

B

27 CHG_AMBER_LED#

E C

R6803 AMBER_LED_BAT

BAT_AMBER

AMBER


CHLED1

2

84.00144.P11 2nd = 84.DT144.A11

1

499R2F-2-GP

1

PDTA144VT-GP

2

1

ORANGE

+

2

-

3

+ WHITE

5V_S5 LED-OW -8-GP Q6803 R2 R1

B

27 BATT_W HITE_LED#

83.01222.X80

E C

R6801 W HITE_LED_BAT

84.00144.P11 2nd = 84.DT144.A11

1

330R2J-3-GP M14 DIS


A

2

A

2

WHITE

1

PDTA144VT-GP

BAT_W HITE


Battery LED2 (WHITE_LED) Low actived from KBC GPIO

LED Bard/Power Button Size A3 Date:

5

4

3

2

Document Number

Rev


68

A00 of

105

5

4

3

SSID = KBC

2

1

SSID = Touch.Pad

Internal Keyboard Connector

TP_VDD TPCLK_C TPDATA_C PCH_SMBCLK PCH_SMBDATA

Touch Pad Connector

D

KB1

1

TP_VDD

AFTP6901

AFTP6902

1

1

RN6901 SRN10KJ-5-GP

3D3V_S0


2

AFTP6909 AFTP6910 AFTP6911 AFTP6913 AFTP6912 AFTP6914 AFTP6916 AFTP6915 AFTP6917 AFTP6919 AFTP6918 AFTP6920 AFTP6922 AFTP6921 AFTP6923 AFTP6925 AFTP6924 AFTP6926 AFTP6928 AFTP6927 AFTP6929 AFTP6931 AFTP6930 AFTP6932 AFTP6934

1 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

R6909 0R0402-PAD 1 2

TPAD1 7

4 3

KROW7 KROW6 KROW4 KROW2 KROW5 KROW1 KROW3 KROW0 KCOL5 KCOL4 KCOL7 KCOL6 KCOL8 KCOL3 KCOL1 KCOL2 KCOL0 KCOL12 KCOL16 KCOL15 KCOL13 KCOL14 KCOL9 KCOL11 KCOL10 CAP_LED

1 27 27

R6911 R6910

TPCLK TPDATA

KROW[7..0] 27

1 1

C

KB_DET# 21

EC6917 DY SC33P50V2JN-3GP

KCOL[16..0] 27

DY

2 2

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32

D

TP_VDD TP_VDD

31 1

AFTP6906 AFTP6907 AFTP6908 AFTP6933 AFTP6937

1 1 1 1 1

2 0R2J-2-GP TPCLK_C 2 0R2J-2-GP TPDATA_C

1 1

2 3 4 5 6

14,15,20 PCH_SMBCLK 14,15,20 PCH_SMBDATA EC6918 SC33P50V2JN-3GP

C

8 AFTP6935

PTWO-CON6-12-GP

1

20.K0382.006

CAP LED Control LOW actived from KBC GPIO

ACES-CON30-10-GP B

B

20.K0592.030

5V_S0 Q6902 R2 B

CAP_LED#

R1

E C

PDTA144VT-GP

1

27

R6906 CAP_LED_Q

1

2

CAP_LED

1KR2J-1-GP

2

SCD1U25V2KX-GP

EC690284.00144.P11

DY

2nd = 84.DT144.A11

M14 DIS

Wistron Corporation

A


Key Board/Touch Pad

Size A4

Document Number



4

3

2

Sheet

69

of 1

Rev

A00 105

A

5

4

3

2

1

SSID = User.Interface D

D

3D3V_S5


LIDSW1

2

R7001 100KR2J-1-GP

1

2

3D3V_S5

1

1 2 3

LID_CLOSE#

27 LID_CLOSE#

VSS VDD OUT

C

C

1

S-5712ACDL1-M3T1U-GP

2

DY

C7002 SCD047U16V2KX-1-GP

74.05712.0BB

B

B

M14 DIS

Wistron Corporation

A


Hall Sensor

Size A4

Document Number


4

3

Rev

OAK14 Chief River DIS 2

Sheet

70

of 1

A00 105

A

5

4

3

2

1

SSID = DEBUG PORT Debug Connector

Layout Note:

Place near trace separated point 3D3V_S0 DB1 21,27 LPC_AD[3..0]

LPC_AD[3..0] LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

D

21,27 LPC_FRAME# 5,18,27,31,65,83 PLT_RST#

R7101 R7102

1 2 3 4

11 1

RN7101 SRN0J-7-GP 8 7 6 5

LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R LPC_FRAME#_DEBUG PLT_RST#_DEBUG

DY

1 1

DY DY

2 2 0R2J-2-GP 0R2J-2-GP

2 3 4 5 6 7 8 9 10 12

18 CLK_PCI_LPC

D

PAD-10P-177042-GP

ZZ.00PAD.Y41

SSID = CPU

C

C

CPU XDP

5

B

5

XDP_PREQ# XDP_PRDY#

XDP_PREQ# XDP_PRDY#

1 1

TP7101 TP7102

1 1

TP7103 TP7104

5 5

XDP_BPM0 XDP_BPM1

XDP_BPM0 XDP_BPM1

5 5

XDP_BPM2 XDP_BPM3

XDP_BPM2 XDP_BPM3

1 1

TP7105 TP7106

5 5

XDP_BPM4 XDP_BPM5

XDP_BPM4 XDP_BPM5

1 1

TP7107 TP7108

5 5

XDP_BPM6 XDP_BPM7

XDP_BPM6 XDP_BPM7

1 1

TP7109 TP7110

CFG0

1

TP7111

7

CFG0

B

M14 DIS A

A


4

3

2

Document Number

Dubug connector


Sheet 1

71

Rev

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

72

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

73

A00 of

105

5

4

3

2

1

SSID = SDIO 3D3V_CARD_S0 CARD1

11

1


2

1 2


1

DY 2

DY


1


2

DY


12 13 10 7

MS_INS MS_BS MS_SCLK

8 15 5

23 24

23 24

SD_GND

21

MS_VSS MS_VSS

16 2

SD_VSS/MMC_VSS1 SD_VSS/MMC_VSS2

9 17

MS_VCC

20 3

32 XD_W E#/SD_CD# 32 XD_D4/SD_D3/MS_D1

2

1

3D3V_CARD_S0


D

MS_DATA0 MS_DATA1 MS_DATA2 MS_DATA3

SD_VDD/MMC_VDD

4

SD_CD SD_CD/DAT3/MMC_RSV

14 6

SD_CLK/MMC_CLK SD_CMD/MMC_CMD

32 XD_CLE/SD_D0/MS_D7 32 XD_CE#/SD_D1 32 XD_D5/SD_D2/MS_D5

18 19 1

SD_DAT0/MMC_DAT SD_DAT1 SD_DAT2

32 XD_RDY/SD_W P/MS_CLK

22

SD_WP/SW

32 XD_D0/SD_CLK/MS_D2_R 32 XD_D2/SD_CMD

NP1 NP2

NP1 NP2

XD_D1/SD_D5/MS_D0 32 XD_D4/SD_D3/MS_D1 32 XD_D0/SD_CLK/MS_D2_R 32 XD_ALE/SD_D7/MS_D3 32


XD_RE#/MS_INS# 32 XD_D6/MS_BS 32 XD_RDY/SD_W P/MS_CLK

D

32

SKT-CARDREADER26-GP

62.10051.C21

Close to Socket 3D3V_CARD_S0

Vendor recommand

EC7410

1 2

EC7409

1 2

EC7408

1 2

EC7407

1 2

EC7406

1 2

EC7405

1 2

EC7404

1 2

EC7403

1 2

EC7402

1 2

2

1

C7407 SC4D7U6D3V3KX-GP 2 1

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

SC6D8P50V2DN-GP

For EMI

SC6D8P50V2DN-GP

XD_ALE/SD_D7/MS_D3 XD_D1/SD_D5/MS_D0 XD_CLE/SD_D0/MS_D7 XD_CE#/SD_D1 XD_D5/SD_D2/MS_D5 XD_D4/SD_D3/MS_D1 XD_D2/SD_CMD XD_D0/SD_CLK/MS_D2_R XD_W E#/SD_CD# XD_RDY/SD_W P/MS_CLK

EC7401

C

SC6D8P50V2DN-GP


C

B

B

M14 DIS

A

A


4

3

2

SD/XD/MS/MMC Card CONN

Document Number


Sheet 1

74

Rev

A00 of

105

5

4

3

2

1

D

D

(Blanking)

C

C

B

B

M14 DIS A

A


4

3

2

Document Number

Express Card

Rev


Sheet 1

75

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

76

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

77

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

78

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A

M14 DIS


4

3

2

Document Number

Free Fall Sensor


Sheet 1

79

Rev

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

80

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


4

3

2

Document Number

Reserved

Rev


Sheet 1

81

A00 of

105

5

4

3

2

1


D

D

C

C

18

USB_PN2_R

USB_PN2

TR8201

4 IOBD1

3

1

+5V_USB1

2 FILTER-4P-6-GP

7 1 2 3 4 5 6

AFTP8201

1

18

USB_PN2_R USB_PP2_R

USB_PP2_R

USB_PP2

8 PTW O-CON6-13-GP

B

20.K0397.006

B

AFTP8204

1

U8202 USB_PP2_R USB_PN2_R USB_PP2_R

1 1

AFTP8203 AFTP8202

1 2 3

VIO#6

6

GROUND

VBUS

5

VIO#3

VIO#4

4

VI/O#1

DY

USB_PN2_R +5V_USB1

IP4223CZ6-GP

M14 DIS

A

A


4

3

2

IO Board Connector

Document Number

Rev



Sheet 1

82

A00 of

105

5

4

3

2

1

dGPU Reset 3D3V_VGA_S0 U8301 1

22 DGPU_HOLD_RST# 5,18,27,31,65,71

2

PLT_RST#

3

A B

5

VCC

OPS

GND

4

Y

1D05V_VGA_S0

U74LVC1G08G-AL5-R-GP-U

D

2ND = 73.7SZ08.EAH 3RD = 73.01G08.L04 1 DY 2 0R2J-2-GP

OPS

R8309 100KR2F-L1-GP

D


dGPU_RXP_C_CPU_TXP9 dGPU_RXN_C_CPU_TXN9

AN18 AM18

dGPU_TXP_CPU_RXP8 dGPU_TXN_CPU_RXN8

AL19 AK19


AN20 AM20 AK20 AJ20 AP20 AP21 AH20 AG20 AN21 AM21

B

AK21 AJ21 AN23 AM23 AL22 AK22 AP23 AP24 AK23 AJ23 AN24 AM24 AH23 AG23 AN26 AM26

1

1 2

2

2

1

1 2

2

1

1

2

2

2

2

2

1

1

1

1 OPS

PEX_TX7 PEX_TX7#

X7R, Under GPU.

PEX_RX7 PEX_RX7#

VDD_SENSE PEX_RX8 PEX_RX8# GND_SENSE

C8324

C8333

OPS

OPS

L4

VGA_SENSE 92

L5

GND_SENSE

POWER IC

92

PEX_TX9 PEX_TX9# PEX_RX9 PEX_RX9# B

PEX_TX10 PEX_TX10# NC_3V3AUX

P8

PEX_RX10 PEX_RX10# PEX_TX11 PEX_TX11# PEX_RX11 PEX_RX11# PEX_TX12 PEX_TX12#

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

AJ26 PEXTSTCLK_OUT AK26 PEXTSTCLK_OUT#

R8304 100R2J-2-GP 1 DY

1.05V +/- 3% 130mA

2

PEX_RX12 PEX_RX12# PEX_TX13 PEX_TX13#

PEX_PLLVDD

AG26

68.00335.151

PEX_RX13 PEX_RX13# PEX_TX14 PEX_TX14#

C8327 TESTMODE

R8303 AK11 TESTMODE 1 OPS 10KR2J-3-GP

2

PEX_TERMP

R8301 AP29 PEX_TERMP 1 OPS 2K49R2F-GP

2

OPS

PEX_RX14 PEX_RX14# PEX_TX15 PEX_TX15# PEX_RX15 PEX_RX15#

1D05V_VGA_S0 L8301 MHC1608S121PBP-GP 1 OPS 2

VCC1R05VIDEO_PEX_PLLVDD

C8326

OPS


AL25 AK25 AN27 AM27

C8325

PEX_RX6 PEX_RX6#

PEX_TX8 PEX_TX8#

3.3V +/- 5% 22mA

AG12

PEX_TX6 PEX_TX6#

SC4D7U6D3V3KX-GP

AP26 AP27

PEX_SVDD_3V3

3D3V_VGA_S0

SCD1U10V2KX-5GP

AK24 AJ24

PEX_RX5 PEX_RX5#

AH12

1

C8315 1OPS C8316 1OPS

AK18 AJ18

PEX_PLL_HVDD

OPS 2

CPU_RXP_C_dGPU_TXP7 CPU_RXN_C_dGPU_TXN7


PEX_TX5 PEX_TX5#

SC4D7U6D3V3KX-GP


AP17 AP18

SC4D7U6D3V3KX-GP

C8313 1OPS C8314 1OPS

AH17 AG17

C

GPU

SCD1U10V2KX-5GP


dGPU_TXP_CPU_RXP10 dGPU_TXN_CPU_RXN10 dGPU_RXP_C_CPU_TXP10 dGPU_RXN_C_CPU_TXN10

OPS

C8337

PEX_RX4 PEX_RX4#

1


PEX_TX4 PEX_TX4#

2

C8311 1OPS C8312 1OPS

AK17 AJ17 AN17 AM17

PEX_RX3 PEX_RX3#

OPS

C8336

1



PEX_TX3 PEX_TX3#

OPS

C8323

2


AN15 AM15

OPS

C8320

1

C8309 1OPS C8310 1OPS


PEX_RX2 PEX_RX2#

OPS

C8318

2


4 CPU_RXN_C_dGPU_TXN[7..0]

AL16 AK16

DY

C8330

1

4 CPU_RXP_C_dGPU_TXP[7..0]

AP14 AP15


OPS

C8329

2

4 dGPU_RXN_C_CPU_TXN[8..15]


PEX_TX2 PEX_TX2#

SC10U6D3V5KX-1GP


PEX_RX1 PEX_RX1#

SC10U6D3V5KX-1GP

C8307 1OPS C8308 1OPS

AK15 AJ15

PEX_TX1 PEX_TX1#

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28

SCD1U10V2KX-4GP



PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14

SC1U10V2KX-1GP


AH14 AG14 AN14 AM14

1D05V_VGA_S0

PEX_RX0 PEX_RX0#

SC4D7U6D3V3KX-GP

C8305 1OPS C8306 1OPS


PEX_TX0 PEX_TX0#

SC10U6D3V5KX-1GP


AN12 AM12

1.05V +/- 5% 1.97A

2



PEX_REFCLK PEX_REFCLK#

1

C8303 1OPS C8304 1OPS

AK14 AJ14

SC10U6D3V5KX-1GP

4 dGPU_RXP_C_CPU_TXP[8..15]



AG19 AG21 AG22 AG24 AH21 AH25

2


2

R8307 0R2J-2-GP

C

C8301 1OPS C8302 1OPS

PEX_CLKREQ#

1

DY

AL13 AK13

20 CLK_PCIE_VGA 20 CLK_PCIE_VGA# CPU_RXP_C_dGPU_TXP0 CPU_RXN_C_dGPU_TXN0

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

PEX_RST#

2

2 1

G 1

AK12

OPS


OPS

AJ12

PEX_CLKREQ#

OPS


Q8301 2N7002BK-GP

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

VGA_RST#

OPS


S

OPS


D

OPS


20 PEG_CLKREQ#

PEX_WAKE#

SC10U6D3V5KX-1GP

AJ11

SC10U6D3V5KX-1GP

1/17 PCI_EXPRESS R8310

OPS 10KR2J-3-GP

1

OPS

C8331

2

OPS

C8332 1 OF 17

GPU1A

2

3D3V_VGA_S0

1

1

2

R8306

1

73.01G08.EHG

N13P-GS-A1-GP

71.0N13P.00U A

A

M14 DIS


GPU_PCIE/STRAPPING(1/5) Size A2 Date: 5

4

3

2

Document Number

Rev



1

Sheet

83

of

A00 105

5

4

3

2

1

LVDS Interface 10 OF 17

GPU1J 5/17 IFPAB

D

D

AJ8

IFPA_TXC# IFPA_TXC

AH8

IFPA_TXD2# IFPA_TXD2 IFPA_TXD3# IFPA_TXD3 IFPB_TXC# IFPB_TXC

IFPA_IOVDD IFPB_TXD4# IFPB_TXD4

IFPB_IOVDD

RN8402 SRN10KJ-5-GP

IFPC_PLLVDD

AK6 AL6

DVI/HDMI

DP

I2CW_SDA I2CW_SCL

IFPC_AUX_I2CW_SDA# IFPC_AUX_I2CW_SCL

GPU

TXC TXC

IFPC_L3# IFPC_L3

IFPC

TXD0 TXD0

IFPC_L2# IFPC_L2

TXD1 TXD1

IFPC_L1# IFPC_L1

TXD2 TXD2

IFPC_L0# IFPC_L0

AH6 AJ6 AH9 AJ9 AP5 AP6

IFPC_IOVDD

AL7 AM7

AF6

IFPC_IOVDD

AG2 AG3 AG4 AG5 AH4 AH3 AJ2 AJ3 AJ1 AK1

P2

GPIO15

N13P-GS-A1-GP RN8401 SRN10KJ-5-GP

71.0N13P.00U

OPS

AM8 AN8

1 2

IFPB_TXD6# IFPB_TXD6

IFPC_RSET

1 2

4 3

OPS


AF7

AM5 AN5

4 3

AG9

AN3 AP3 IFPC_PLLVDD

IFPAB_PLLVDD

GPU AG8

ALL PINS NC FOR GF117 AF8

IFPA_TXD1# IFPA_TXD1

IFPAB_IOVDD

AN6 AM6

IFPAB_RSET IFPA_TXD0# IFPA_TXD0

IFPAB_PLLVDD

11 OF 17

GPU1K 6/17 IFPC

ALL PINS NC FOR GF117

C

C


GPIO14

IFPAB

AL8 AK8

N4

N13P-GS-A1-GP

71.0N13P.00U

13 OF 17

GPU1M 8/17 IFPEF

ALL PINS NC FOR GF117 DVI-DL

IFPEF_PLLVDD

HDMI Interface

AB8 AD6

IFPEF_RSET

ALL PINS NC FOR GF117

IFPE

B

AN2

IFPD_PLLVDD

AG7

IFPD_RSET

IFPD_PLLVDD

GPU

4 3

IFPD_IOVDD

I2CX_SDA I2CX_SCL

IFPD_AUX_I2CX_SDA# IFPD_AUX_I2CX_SCL

TXC TXC

IFPD_L3# IFPD_L3

TXD0 TXD0

IFPD_L2# IFPD_L2

TXD1 TXD1

IFPD_L1# IFPD_L1

TXD2 TXD2

IFPD_L0# IFPD_L0

IFPE_L3# IFPE_L3

TXD0 TXD0

IFPE_L2# IFPE_L2

TXD1 TXD1

TXD1 TXD1

IFPE_L1# IFPE_L1

TXD2 TXD2

TXD2 TXD2

IFPE_L0# IFPE_L0

HPD_E

HPD_E

AG6

IFPD_IOVDD

GPIO17

GPIO18

AK5 AK4

AB4 AB3 AC5 AC4 AC3 AC2 AC1 AD1 B

AD3 AD2

R1

AL4 AL3 AM4 AM3

IFPEF_IOVDD

AC7

IFPE_IOVDD

GPU I2CZ_SDA I2CZ_SCL

AM2 AM1

AC8

IFPF_AUX_I2CZ_SDA# IFPF_AUX_I2CZ_SCL

OPS 1 2

71.0N13P.00U

AF2 AF3

IFPF_IOVDD TXC TXC

IFPF_L3# IFPF_L3

TXD3 TXD3

TXD0 TXD0

IFPF_L2# IFPF_L2

TXD4 TXD4

TXD1 TXD1

IFPF_L1# IFPF_L1

TXD5 TXD5

TXD2 TXD2

IFPF_L0# IFPF_L0

M6

N13P-GS-A1-GP RN8404 SRN10KJ-5-GP

TXC TXC

TXD0 TXD0

IFPE_AUX_I2CY_SDA# IFPE_AUX_I2CY_SCL

AK2 AK3

RN8403 SRN10KJ-5-GP

IFPF

1 2

OPS

DP

TXC TXC

4 3

IFPD

DVI/HDMI

DP

I2CY_SDA I2CY_SCL

IFPEF_PLLVDD

12 OF 17

GPU1L 7/17 IFPD

DVI-SL/HDMI

I2CY_SDA I2CY_SCL

HPD_F

GPIO19

AF1 AG1 AD5 AD4 AF5 AF4 AE4 AE3

P3

N13P-GS-A1-GP

71.0N13P.00U

A

A

M14 DIS


GPU Memory(2/5) Size A2 Date: 5

4

3

2

Document Number

Rev


Wednesday, September 05, 2012 1

Sheet

84

of

A00 105

5

4

3

DA-05691-001_V05 P7 Pull Down 10K : N13P-GS

2

2

1

1

2

2

1.5V +/- 5% 4.88A

1

FBA_PLL_AVDD

H17

GPU FBVDDQ Decoupling

N13P-GS-A1-GP

OPS

4 OF 17

Colay: N13P - GS connected to power

1D5V_VGA_S0

PLACE CLOSE TO GPU BALLS

GPU1D 14/17 FBVDDQ

TP8501

1

FBVDDQ_SENSE

F1

FB_GND_SENSE

F2

DY

DY

2

2

C8531

C8532

DY 1

C8523

DY

SC10U10V5KX-2GP

1

2

C8519

OPS

SC10U6D3V3MX-GP

1

C8514

1

DY

SC10U10V5KX-2GP

1

C8513

DY

2

1

C8525

SC4D7U6D3V3KX-GP

DY

2

1

C8527

SC4D7U6D3V3KX-GP

DY

2

C8508

OPS

SC4D7U6D3V3KX-GP

C8507

OPS

1

C8528

OPS

2

C8502

OPS

SC1U16V3KX-5GP

C8501

B

1D5V_VGA_S0

DY

SC10U10V5KX-2GP

C8533

DY

2

2

DY

C8521 C8524

OPS

C8534

DY 1

1

C8516

2

DY

SC10U6D3V3MX-GP

C8515

DY

1

C8526

2

C8530

OPS DY

SC4D7U6D3V3KX-GP

C8512

OPS

1

C8511

2

DY

SC4D7U6D3V3KX-GP

C8529

OPS

1

C8504

OPS

2

C8503

1

PLACE CLOSE TO GPU BALLS

SC4D7U6D3V3KX-GP

GPU

AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27 B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24 H8 H9 L27 M27 N27 P27 R27 T27 T30 T33 V27 W27 W30 W33 Y27

2

B

FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43 FBVDDQ_44

1

Place under GPU near

SC1U16V3KX-5GP

Place under GPU near

X7R DA-05691-001_V05 P14

2

C8510

71.0N13P.00U

SC10U10V5KX-2GP

FBB_PLL_AVDD

D6 D7 C6 B6 F26 E26 A26 A27

1

30ohm@100MHz ESR=0.2

F8 E8 A5 A6 D24 D25 B27 C27

SC10U10V5KX-2GP

2

90 90 91 91

2

FBB_WCKB1 FBB_WCKB1# FBB_WCKB23 FBB_WCKB23# FBB_WCKB45 FBB_WCKB45# FBB_WCKB67 FBB_WCKB67#

THE FBB_WCKBxx PINS ARE USED ONLY ON GK107 THEY ARE NC FOR GF108 AND FOR GF117

FBB_CLK0 FBB_CLK0# FBB_CLK1 FBB_CLK1#

1

FBB_WCK1 FBB_WCK1# FBB_WCK23 FBB_WCK23# FBB_WCK45 FBB_WCK45# FBB_WCK67 FBB_WCK67#

D12 E12 E20 F20

2 60D4R2F-GP 2 10KR2J-3-GP

SC10U10V5KX-2GP

FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7

OPS OPS

2

FBB_CLK0 FBB_CLK0# FBB_CLK1 FBB_CLK1#

R8509 1 R8510 1

1

FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7

G14 G20

C8506

OPS

10KR2J-3-GP

1

10KR2J-3-GP

2 1

10KR2J-3-GP

2 1

10KR2J-3-GP

1

10KR2J-3-GP

10KR2J-3-GP

1

10KR2J-3-GP

1

2

2

2

2

1D5V_VGA_S0

FBB_DEBUG0 FBB_DEBUG1

SC1U16V3KX-5GP

OPS

C

TP8512

C12 C20

1

OPS

R8516

OPS

2

1

SC1U16V3KX-5GP

OPS

C8505

R8515

OPS

SC1U16V3KX-5GP

1

68.00335.051 C8520

R8514

OPS

1

FBA_PLL_AVDD

U27

N13P-GS-A1-GP

D9 E4 B2 A9 D22 D28 A30 B23

R8513

OPS

2

1D05V_VGA_S0 L8501 MHC1608S300QBP-GP

FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7

R8512

OPS

2

X02 0730 change source

DA-05691-001_V05 P7 NC : N13P-GL

90 90 90 90 91 91 91 91

D10 D5 C3 B9 E23 E28 B30 A23

R8511

OPS

SC1U6D3V2KX-GP

J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33

FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7

R8508

OPS

1

K31 L30 H34 J34 AG30 AG31 AJ34 AK34

90 90 90 90 91 91 91 91

R8507

OPS

1

88 88 89 89

1

FBB_CMD2 FBB_CMD3 FBB_CMD5 FBB_CMD18

FBA_CMD2 FBA_CMD3 FBA_CMD5 FBA_CMD18

2

FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1#

FBB_CMD31

91 91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91

R8518

OPS 10KR2J-3-GP

2

R30 R31 AB31 AC31

FBB_CMD_RFU0 FBB_CMD_RFU1

TP8513 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30

FBB_CMD19

R8517

OPS 10KR2J-3-GP

SCD1U10V2KX-5GP

FBA_PLL_AVDD

2 60D4R2F-GP 2 10KR2J-3-GP

OPS OPS

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

90 90 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 91

1

FBA_WCKB1 FBA_WCKB1# FBA_WCKB23 FBA_WCKB23# FBA_WCKB45 FBA_WCKB45# FBA_WCKB67 FBA_WCKB67#

R8503 1 R8506 1

E11 E3 A3 C9 F23 F27 C30 A24

1

90

TP8515 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16

1

FBA_WCK1 FBA_WCK1# FBA_WCK23 FBA_WCK23# FBA_WCK45 FBA_WCK45# FBA_WCK67 FBA_WCK67#

R28 AC28

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

FBB_CMD17

FBB_CMD0

SC1U6D3V2KX-GP

90 90 90 90 91 91 91 91

1

SCD1U10V2KX-5GP

TP8509

R32 AC32

FBB_CMD1

1

2

91 FBB_D[56..63]

D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17

2

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FB_VREF

91 FBB_D[48..55]

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

10KR2J-3-GP

1

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1#

71.0N13P.00U

89 89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89

91 FBB_D[40..47]

FBA_CMD19

GPU

2

H26

TP8508 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

91 FBB_D[32..39]

SCD1U10V2KX-5GP

FB_VREF

1

88 88 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 89

1

1

FBA_CMD31

1

88

TP8505 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16

1

TP8503

FBA_CMD17

FBA_CMD0

1D5V_VGA_S0

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

THE FBA_WCKBxx PINS ARE USED ONLY ON GK107 THEY ARE NC FOR GF108 AND FOR GF117

1

2

M30 H30 E34 M34 AF30 AK31 AM34 AF32

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3

2

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_CMD_RFU0 FBA_CMD_RFU1

U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31

SCD1U10V2KX-5GP

88 88 88 88 89 89 89 89

M31 G31 E33 M33 AE31 AK30 AN33 AF33

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

SC1U6D3V2KX-GP

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

GPU

SC1U6D3V2KX-GP

88 88 88 88 89 89 89 89

90 FBB_D[24..31]

1

P30 F31 F34 M32 AD31 AL29 AM32 AF34

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

90 FBB_D[16..23]

D

2

88 88 88 88 89 89 89 89

Place close to Ball

FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63

SCD1U10V2KX-5GP

C

90 FBB_D[8..15]

DA-05691-001_V05 P7 Colay: N13P - GS connected to power

G9 E9 G8 F9 F11 G11 F12 G12 G6 F5 E6 F6 F4 G4 E2 F3 C2 D4 D3 C1 B3 C4 B5 C5 A11 C11 D11 B11 D8 A8 C8 B8 F24 G23 E24 G24 D21 E21 G21 F21 G27 D27 G26 E27 E29 F29 E30 D30 A32 C31 C32 B32 D29 A29 C29 B29 B21 C23 A21 C21 B24 C24 B26 C26

1

89 FBA_D[56..63]

X7R

OPS

1

89 FBA_D[48..55]

C8509

2

89 FBA_D[40..47]

Layout note:FBA_PLL_AVDD=16mil

2

89 FBA_D[32..39]

FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63

FBA_PLL_AVDD

K27

3 OF 17

GPU1C 3/17 FBB 90 FBB_D[0..7]

2 10KR2J-3-GP

OPS

SCD1U10V2KX-5GP

88 FBA_D[24..31]

FB_DLL_AVDD

R8519 1

E1

SC10U6D3V5KX-1GP

88 FBA_D[16..23]

FB_CLAMP

SCD1U10V2KX-5GP

88 FBA_D[8..15]

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

2

D

L28 M29 L29 M28 N31 P29 R29 P28 J28 H29 J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32 L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28 AM29 AM31 AN29 AM30 AN31 AN32 AP30 AP32 AM33 AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33

1

2 OF 17

GPU1B 2/17 FBA 88 FBA_D[0..7] FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

2

FB_VDDQ_SENSE

1D5V_VGA_S0 TP8502

1

FB_GND_SENSE

R8501

2

OPS

FB_CAL_PD_VDDQ

J27

FB_CAL_PU_GND

H27

FB_CAL_TERM_GND

H25

1

FB_CAL_PD_VDDQ

40D2R2F-GP

FB_CAL_PU_GND FB_CAL_TERM_GND N13P-GS-A1-GP

2 R8502

OPS 1

1

42D2R2F-GP

R8504

OPS A

51R2J-2-GP

2

71.0N13P.00U

A

M14 DIS


GPU_DP/LVDS/CRT/GPIO(3/5) Size A1 Date: 5

4

3

2

Document Number

Rev



Sheet

85

of

A00 105

5

4

3

2

1

1D05V_VGA_S0 3D3V_VGA_S0

OPS

L8602 MCB1608S181FBP-GP

OPS

1

2

PLLVDD SP_PLLVDD

AD7

71.0N13P.00U

C8604

GF117

VIDEO_CLK_XTAL_SS

OPS OPS OPS OPS

H1

XTAL_SSIN

H3

XTAL_IN

XTAL_OUT

27MHZ_IN

1

DY

1 4

2

3

R8610 1K5R2F-2-GP

4 3

1

OPS 2

RN8601 OPS SRN4K7J-8-GP

2

1

1

XTAL-27MHZ-85-GP

82.30034.641 2

2ND = 82.30034.651 3RD = 82.30034.681

2

1 2 20,27,28 SML1_DATA

SMBD_THERM_NV

4

27MHZ_OUT_R

OPS C8607 SC18P50V2JN-1-GP

Q8601

3

R8608

OPS10KR2J-3-GP 27MHZ_OUT

2

X8601

0R2J-2-GP

H2

R8609 1MR2J-1-GP

R8630

2

J4

71.0N13P.00U 20PF 5% 50V +/-0.25PF 0402

3D3V_VGA_S0

OPS

D

XTAL_OUTBUFF

N12P_XTAL_OUTBUFF

N13P-GS-A1-GP

R8607 10KR2J-3-GP

2

OPS 3D3V_VGA_S0

1

N13P-GS1

C8602

1

N13P-GS-A1-GP

C8603

GPU

NC

VID_PLLVDD GF108/GKx

C8601

AL9

1

DACA_BLUE

108mA

AD8 AE8

68.00909.261

AL10

15 OF 17

GPU1O 11/17 XTAL_PLL GPU_PLL_VDD SP_PLLVDD

2

NC

AK9

1

DACA_GREEN

1

DACA_RED

NC

2

NC

SCD1U10V2KX-5GP

2

GPU

NV request to need to be keeped

C8606 SC2D2U6D3V2MX-GP

1

AM9 AN9

2

NC

DACA_RSET

SC4D7U6D3V3KX-GP

1

AP8

OPS R8612 10KR2J-3-GP D

52mA

2

C8605 OPS SCD1U10V2KX-5GP

TSEN_VREF

DACA_VREF

OPS

68.00335.081

SCD1U10V2KX-5GP

DACA_HSYNC DACA_VSYNC

1 RN8603 2 SRN2K2J-1-GP

OPS

4 3

1

NC NC

R4 R5

1

I2CA_SCL I2CA_SDA

2

NC NC

2

AP9

L8601 MHC1608S181NBP-GP

1

NC

DACA_VDD

GF108/GKx

SC4D7U6D3V3KX-GP

AG10

GF117

1

DACA_VDD

GF117

2

GF108/GKx

2

14 OF 17

GPU1N 4/17 DACA

OPS


OPS

5

OPS

1

6

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F 3RD = 84.2N702.F3F SMBC_THERM_NV 20,27,28 SML1_CLK

I2CS_SCL I2CS_SDA I2CC_SCL I2CC_SDA

TP8604

1 1 1

AM10 AP11 AM11 AP12 AN11

OPS

R7 R6

4 3

OPS

1 RN8605 2 SRN2K2J-1-GP

C

THERMDP 3D3V_VGA_S0

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST#

GPU

4 3

TP8602 TP8606 TP8601

N12P_JTAG_TCK N12P_JTAG_TMS N12P_JTAG_TDI N12P_JTAG_TDO N12P_JTAG_TRST

I2CB_SCL I2CB_SDA

THERMDN

RN8602 SRN10KJ-5-GP

1 2

OPS

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO16 GPIO20 GPIO21

P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 R8 P4 P1

NV_VID4 NV_VID3

92 92

R8617 10KR2J-3-GP

3D3V_VGA_S0 NV_VID1 NV_VID2

92 92 3D3V_VGA_S0

GPIO8_OVERT# GPIO9_ALERT

R8635 1

210KR2J-3-GP

OPS

NV_VID0 NV_VID5

92

OPS

G

K3

1 RN8604 2 SRN2K2J-1-GP

1

K4

P2800_VGA_DXP

4 3

2

P2800_VGA_DXN

1

SMBC_THERM_NV SMBD_THERM_NV

R2 R3

1

1 TP8603

T4 T3

PWR_LEVEL

OPS

GPIO8_OVERT#

S

R8611 10KR2J-3-GP

D

OPS

A

92

DY

K

AC_PRESENT

PURE_HW_SHUTDOWN#

27,28,36

Q8604 2N7002BK-GP

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

D8601

2

C

3D3V_VGA_S0

17 OF 17

GPU1Q 10/19 MISC1

19,27

1SS400GPT-GP

83.00400.C1F 2ND = 83.27101.01F 3RD = 83.01426.01F

DA-05691-001_V05 P15 GPIO20/21 NC : for ALL

D8602

A

OPS

K

OVER_CURRENT_P8#

27

1SS400GPT-GP

83.00400.C1F 2ND = 83.27101.01F 3RD = 83.01426.01F

N13P-GS-A1-GP

71.0N13P.00U

N13M-GSR

3D3V_VGA_S0 16 OF 17

2

GPU1P 12/17 MISC2

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

B

J2 J7 J6 J5 J3

GPU


ROM_SI ROM_SO ROM_SCLK

H6

ROM_CS#

H5 H7 H4

ROM_SI_D3 ROM_SO_C4 ROM_SLK_D4

R8632 10KR2J-3-GP

1

DY ROM_CS#

B

R8634

BUFRST#

L2

2

OPS

1

10KR2J-3-GP STRAP_REF0_GND_N9

J1

MULTI_STRAP_REF0_GND

CEC

L3

N13M-GSR

1 R8618 10KR2F-2-GP

R8624 10KR2F-2-GP

R8626 10KR2F-2-GP

R8633 10KR2F-2-GP

2

N13M_128M

R8636 10KR2F-2-GP

R8623 10KR2F-2-GP

R8637 10KR2F-2-GP

N13M-GS / N13P-GS

R8620 4K99R2F-L-GP

2

2

3D3V_VGA_S0

1

1

N13P-GS1

3D3V_VGA_S0

N13P_STRAP0 STRAP0 STRAP1 STRAP2

A

R8616 45K3R2F-L-GP

R8625 4K99R2F-L-GP

R8627 15KR2F-GP

2

N13P_STRAP1 N13P_STRAP2 2

2

N13P_STRAP4 N13P_STRAP3

2

2

2

R8631 4K99R2F-L-GP

N13M_ROM_CLK

2

N13P_Samsung

1

1 R8615 10KR2J-3-GP

N13M_ROM_SO 2

2

2

1

R8614 10KR2J-3-GP

N13P_Hynix N13M_ROM_SI

1

1

1

1 R8621 24K9R2F-L-GP

1

DY

STRAP3 STRAP4

1

2

R8629 4K99R2F-L-GP

ROM_SI_D3 ROM_SO_C4 ROM_SLK_D4

R8639 30KR2F-GP

R8622 45K3R2F-L-GP

2

2

1

1

N13P_ROM_SCLK N13P_ROM_SO

R8640 10KR2J-3-GP

R8638 10KR2F-2-GP

N13M_256M N13M_STRAP4

N13M_Samsung

3D3V_VGA_S0

R8619 10KR2F-2-GP

A

2

2

N13M_STRAP1_D N13M_STRAP0_D

1

N13M_Other

1

1

N13M_STRAP0_U

1

2

2

N13M_STRAP1_U


2

1 R8628 10KR2F-2-GP

1

3D3V_VGA_S0

71.0N13P.00U

1

2

N13P-GS-A1-GP

2

N13P_MULTI_STRAP R8613 40K2R2F-GP

1

1

DA-05691-001_V05 P6 NC : N13P-GS

M14 DIS

4/9 update GPU strappin


GPU_POWER(4/5) Size A1 Date: 5

4

3

2

Document Number

Rev



Sheet

86

of

A00 105

5

4

3

2

N13P-GS : 27A

6 OF 17 GPU1F 13/17 NVVDD

Under GPU

OPS

1

1

SC4D7U6D3V3KX-GP 2

SC4D7U6D3V3KX-GP 2

C8725

1

C8726

OPS

OPS

C8718

SC4D7U6D3V3KX-GP 2

SC4D7U6D3V3KX-GP 2

OPS

OPS

C8717

OPS

SC1U6D3V2KX-GP 2 1

OPS

C8719

OPS

1

1

SC10U6D3V3MX-GP 1 2

SC4D7U6D3V3KX-GP 2

C8720

OPS

AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23 M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15 V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22

C8701

SC4D7U6D3V3KX-GP 2

SC10U6D3V3MX-GP 2 1

SC4D7U6D3V3KX-GP 2

SC10U6D3V3MX-GP 1

1

C8727

OPS

C8702

SC1U6D3V2KX-GP 2 1

OPS

C8730

OPS

C8723

OPS

SC1U6D3V2KX-GP 2 1

OPS

C8729

C8711

OPS

SCD1U10V2KX-4GP 2 1

C8724

SC1U6D3V2KX-GP 2 1

OPS

C8721

SC1U6D3V2KX-GP 2 1

SC1U6D3V2KX-GP 2 1

C8722

OPS

SC4D7U6D3V3KX-GP 2

OPS

SC1U6D3V2KX-GP 2 1

1

C8728

SC10U6D3V3MX-GP 1 2

C8731

C

OPS

SC4D7U6D3V3KX-GP 2

OPS

D

C8713

1

2

C8712

1

C8714

OPS

C8715

OPS

R8701

UMA 2

OPS

SC10U6D3V3MX-GP 1 2

SC10U6D3V3MX-GP 1 2

SC10U6D3V3MX-GP 1 2

C8710

0R3J-0-U-GP

OPS

1

NEAR TO GPU

C8707

A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19 AB2 AB21 A33 AB23 AB28 AB30 AB32 AB5 AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22 AE2 AE28 AE30 AE32 AE33 AE5 AE7 AH10 AA15 AH13 AH16 AH19 AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33 AH5 AH7 AJ7 AK10 AK7 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33 AL5 AM13 AM16 AM19 AM22

VGA_CORE

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72

GPU

15/17 GND_1/2 GND_1 GND_71 GND_5 GND_72 GND_6 GND_73 GND_7 GND_74 GND_8 GND_75 GND_9 GND_76 GND_10 GND_77 GND_11 GND_78 GND_12 GND_79 GND_13 GND_80 GND_14 GND_81 GND_2 GND_82 GND_15 GND_83 GND_16 GND_84 GND_17 GND_85 GND_18 GND_86 GND_19 GND_87 GND_20 GND_88 GND_21 GND_89 GND_22 GND_90 GND_23 GND_91 GND_24 GND_92 GND_3 GND_93 GND_25 GND_94 GND_26 GND_95 GND_27 GND_96 GND_28 GND_97 GND_29 GND_98 GND_30 GND_99 GND_31 GND_100 GND_32 GND_101 GND_33 GND_102 GND_34 GND_103 GND_4 GND_104 GND_35 GND_105 GND_36 GND_106 GND_37 GND_107 GND_38 GND_108 GND_39 GND_109 GND_40 GND_110 GND_41 GND_111 GND_42 GND_112 GND_43 GND_113 GND_44 GND_114 GND_45 GND_115 GND_46 GND_116 GND_47 GND_117 GND_48 GND_118 GND_49 GND_119 GND_50 GND_120 GND_51 GND_121 GND_52 GND_122 GND_53 GND_123 GND_54 GND_124 GND_55 GND_125 GND_56 GND_126 GND_57 GND_127 GND_58 GND_128 GND_59 GND_129 GND_60 GND_130 GND_61 GND_131 GND_62 GND_132 GND_63 GND_133 GND_64 GND_134 GND_65 GND_135 GND_66 GND_136 GND_67 GND_137 GND_68 GND_138 GND_69 GND_139 GND_70 GND_140

GPU

3.3V +/- 5% 85mA

DA-05691-001_V05 P20 3V3MISC : N13P-GS

N13P-GS-A1-GP

71.0N13P.00U A

GPU 3D3V_VGA_S0

C8734

X7R

OPS

C8732

X7R

OPS

XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16 XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22

SC1U6D3V2KX-GP 2 1

OPS

SCD1U10V2KX-5GP 2 1

C8709

SCD1U10V2KX-5GP 2 1

SC1U6D3V2KX-GP 2 1

J8 K8 L8 M8

GPU

GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169

GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198

T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23

D

GPU AG11

GND_F

GND_H

GND_OPT_1 GND_OPT_2

AH11

C16 W32

Optional CMD GNDs (2) NC for 4-Lyr cards

N13P-GS-A1-GP

71.0N13P.00U

C

CONFIGURABLE POWER CHANNELS

XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8

VDD33_1 VDD33_2 VDD33_3 VDD33_4

N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22

5 OF 17

GPU1E 9/17 XVDD

B

NC#AC6 NC#AJ28 NC#AJ4 NC#AJ5 NC#AL11 NC#C15 NC#D19 NC#D20 NC#D23 NC#D26 NC#H31 NC#T8 NC#V32

16/17 GND_2/2

AM25 AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34 AN4 AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28 C7 D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16

71.0N13P.00U

71.0N13P.00U

AC6 AJ28 AJ4 AJ5 AL11 C15 D19 D20 D23 D26 H31 T8 V32

8 OF 17

GPU1H

N13P-GS-A1-GP

N13P-GS-A1-GP

7 OF 17 GPU1G 17/17 NC/VDD33

1

9 OF 17

GPU1I

C8733

OPS


0.1U Under GPU 4.7U NEAR TO GPU 1U NEAR TO GPU


U1 U2 U3 U4 U5 U6 U7 U8

B

XVDD_1~38 NC : N13P-GL

V1 V2 V3 V4 V5 V6 V7 V8 W2 W3 W4 W5 W7 W8

Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A

AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

N13P-GS-A1-GP

71.0N13P.00U

Title

GPU_DPPWR/GND(5/5) Size Custom Date: 5

4

3

2

Document Number

Rev



Sheet 1

87

of

A00 105

5

4

3

2

1

Frame Buffer Patition A-Lower Half

D

D

1D5V_VGA_S0

1D5V_VGA_S0

85,89 FBA_CMD12 85,89 FBA_CMD27 85,89 FBA_CMD26

M2 N8 M3

BA0 BA1 BA2

FBA_CLK0 FBA_CLK0#

J7 K7

CK CK#

85

FBA_CMD3

K9

85 85

FBA_DQM1 FBA_DQM3

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#


F3 G3

FBA_DQS_W P3 85 FBA_DQS_RN3 85

ODT

K1

FBA_CMD2 85

CS# RESET#

L2 T2

FBA_CMD0 85 FBA_CMD5 85,89

NC#M7 NC#L9 NC#L1 NC#J9 NC#J1

M7 L9 L1 J9 J1

FBA_CMD14 85,89

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

OPS

C8829

OPS

C8827

1

OPS 2

2

2

2

2 1

C8811

OPS

OPS

1

1

1 2 1

1 2 1


DQSL DQSL#

CKE

C8832

OPS

OPS

C8806

K8 K2 N1 R9 B2 D9 G7 R1 N9

VDD VDD VDD VDD VDD VDD VDD VDD VDD

A8 A1 C1 C9 D2 E9 F1 H9 H2

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VRAM1_VREF H1 VRAM2_VREF M8 VRAM_ZQ1 L8

VREFDQ VREFCA ZQ

FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14


M2 N8 M3

BA0 BA1 BA2

FBA_CLK0 FBA_CLK0#

J7 K7

CK CK#

85

FBA_CMD3

K9

CKE

85 85

FBA_DQM0 FBA_DQM2

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#

1 R8801 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89

85 85

OPS

2

243R2F-2-GP


FBA_D17 FBA_D21 FBA_D19 FBA_D20 FBA_D18 FBA_D22 FBA_D16 FBA_D23

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3


DQSU DQSU#

C7 B7


DQSL DQSL#

F3 G3


ODT

K1

FBA_CMD2 85

CS# RESET#

L2 T2



M7 L9 L1 J9 J1

FBA_CMD14 85,89


J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1


G1 F9 E8 E2 D8 D1 B9 B1 G9

OPS

72.41646.00U

72.41646.00U

1

2

2

A

VRAM2_VREF

Wistron Corporation

1


R8807 OPS 1K33R2F-GP


OPS C8805 SCD1U10V2KX-5GP Title

2

OPS 2


B

M14 DIS

VRAM1_VREF

2

FBA_CLK0#

C


1

2

OPS

R8809 162R2F-GP

85

1D5V_VGA_S0


1 A

FBA_D[0..7]

1

1D5V_VGA_S0

85

E3 F7 F2 F8 H3 H8 G2 H7

K4W 4G1646B-HC11-GP

FBA_CLK0

FBA_D[16..23]

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

K4W 4G1646B-HC11-GP

2

85 85

C7 B7

85

2

1 2 1

2 1 2

2

2

1

1 2

2 1 2


DQSU DQSU#

FBA_D[8..15]

OPS

C8807

SCD1U10V2KX-5GP



OPS

C8809

SC1U6D3V2KX-GP

VREFDQ VREFCA ZQ

D7 C3 C8 C2 A7 A2 B8 A3

C8808

SC1U6D3V2KX-GP

H1 M8 L8


85

SC1U6D3V2KX-GP


FBA_D[24..31]

SC1U6D3V2KX-GP

A8 A1 C1 C9 D2 E9 F1 H9 H2



SC1U6D3V2KX-GP


VRAM2

E3 F7 F2 F8 H3 H8 G2 H7

SCD1U10V2KX-5GP

243R2F-2-GP

VRAM1_VREF VRAM2_VREF VRAM_ZQ2

K8 K2 N1 R9 B2 D9 G7 R1 N9

SC1U6D3V2KX-GP

C8820

OPS

SC1U6D3V2KX-GP

2

OPS

SC1U6D3V2KX-GP

OPS

C8814


85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89

B

C8830

OPS

SCD1U10V2KX-5GP

1 R8802

SC1U6D3V2KX-GP

C8833

C8815

OPS

OPS

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C

SC1U6D3V2KX-GP

C8834

OPS

C8821

OPS

SC1U6D3V2KX-GP

OPS

1

1

VRAM1 C8816

GPU-VRAM1,2 (1/4) Size A3 Date: 5

4

3

2

Document Number

Rev



Sheet 1

88

of

A00 105

5

4

3

2

1

Frame Buffer Patition A-Upper Half

D

D


J7 K7

85

FBA_CMD19

K9

85 85

FBA_DQM4 FBA_DQM7

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#


CS# RESET#

L2 T2



M7 L9 L1 J9 J1

FBA_CMD14 85,88


J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1


G1 F9 E8 E2 D8 D1 B9 B1 G9

CKE

OPS

1

1

1





M2 N8 M3

BA0 BA1 BA2

1 R8901 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88

OPS

2

2 1

C8923

OPS

C8918

OPS 2

2 1

2

C8922

OPS

2

FBA_CMD18 85

VREFDQ VREFCA ZQ


1

K1

1

ODT

H1 M8 L8

C8921

OPS

2

2 1 2

2 1 2

2

2 2

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

2

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

FBA_CLK1 FBA_CLK1#



2

CK CK#

85 85

DQSL DQSL#

F3 G3

1

BA0 BA1 BA2

C7 B7

A8 A1 C1 C9 D2 E9 F1 H9 H2

85

OPS

SC1U6D3V2KX-GP

M2 N8 M3

243R2F-2-GP

DQSU DQSU#

FBA_D[32..39]

OPS

SC1U6D3V2KX-GP


2



OPS

SC1U6D3V2KX-GP


OPS

C8908

OPS

D7 C3 C8 C2 A7 A2 B8 A3

C8907


OPS

SC1U6D3V2KX-GP


OPS


C8915

K8 K2 N1 R9 B2 D9 G7 R1 N9

SCD1U10V2KX-5GP


1 R8902 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88

C8925



VREFDQ VREFCA ZQ

C

C8926

OPS

OPS

C8917

SCD1U10V2KX-5GP

H1 M8 L8

C8927

OPS

85


SC1U6D3V2KX-GP


OPS

VRAM4 FBA_D[56..63]

E3 F7 F2 F8 H3 H8 G2 H7

2

1

1

1

C8913

A8 A1 C1 C9 D2 E9 F1 H9 H2

OPS

B

C8928


OPS

1

C8929

K8 K2 N1 R9 B2 D9 G7 R1 N9

1

1

VRAM3 C8920


243R2F-2-GP

85 85

FBA_CLK1 FBA_CLK1#

J7 K7

CK CK#

85

FBA_CMD19

K9

CKE

85 85

FBA_DQM5 FBA_DQM6

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#


K4W 4G1646B-HC11-GP

85

E3 F7 F2 F8 H3 H8 G2 H7



D7 C3 C8 C2 A7 A2 B8 A3


DQSU DQSU#

C7 B7


DQSL DQSL#

F3 G3


ODT

K1

FBA_CMD18 85

CS# RESET#

L2 T2



M7 L9 L1 J9 J1

FBA_CMD14 85,88


J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1


G1 F9 E8 E2 D8 D1 B9 B1 G9

OPS

FBA_D[40..47]

85

C

B

K4W 4G1646B-HC11-GP

72.41646.00U

72.41646.00U


1

2


2

FBA_CLK1

1

1D5V_VGA_S0

1

1D5V_VGA_S0

VRAM4_VREF

1

A

OPS C8914 SCD1U10V2KX-5GP

Wistron Corporation

2



2

FBA_CLK1#

M14 DIS

1 1

OPS C8911 SCD1U10V2KX-5GP

2

2


2

OPS 162R2F-GP

1

VRAM3_VREF R8909

A

FBA_D[48..55]


Title


4

3

2

Document Number

Rev



Sheet 1

89

of

A00 105

5

4

3

2

1

Frame Buffer Patition B-Lower Half

D

D


2

2

2

F3 G3

FBB_DQS_W P0 85 FBB_DQS_RN0 85

ODT

K1

FBB_CMD2 85

CS# RESET#

L2 T2

FBB_CMD0 85 FBB_CMD5 85,91


M7 L9 L1 J9 J1

FBB_CMD14 85,91


J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

85,91 FBB_CMD12 85,91 FBB_CMD27 85,91 FBB_CMD26

M2 N8 M3

BA0 BA1 BA2

85 85

FBB_CLK0 FBB_CLK0#

J7 K7

CK CK#

85

FBB_CMD3

K9

CKE VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

85 85

FBB_DQM1 FBB_DQM0

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#

8VRAM

1

VREFDQ VREFCA ZQ

FBB_CMD9 FBB_CMD11 FBB_CMD8 FBB_CMD25 FBB_CMD10 FBB_CMD24 FBB_CMD22 FBB_CMD7 FBB_CMD21 FBB_CMD6 FBB_CMD29 FBB_CMD23 FBB_CMD28 FBB_CMD20 FBB_CMD4




M2 N8 M3

BA0 BA1 BA2

2 1

2 1

1

H1 M8 L8

C9023

C9024

2

DQSL DQSL#


C9008

1

C7 B7

A8 A1 C1 C9 D2 E9 F1 H9 H2

85

2

DQSU DQSU#

FBB_D[8..15]

8VRAM 8VRAM

1

1



FBB_D12 FBB_D9 FBB_D14 FBB_D8 FBB_D13 FBB_D10 FBB_D15 FBB_D11

C9009


1 R9004 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91

2 8VRAM

2

2

2

8VRAM 8VRAM 8VRAM 8VRAM 2

1 2

2 1

2 1

1

1

1

1 2 1 2


243R2F-2-GP

D7 C3 C8 C2 A7 A2 B8 A3


8VRAM DY

SC1U6D3V2KX-GP


85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91



VREFDQ VREFCA ZQ

2 8VRAM


SC1U6D3V2KX-GP

SCD1U10V2KX-5GP


E3 F7 F2 F8 H3 H8 G2 H7


H1 M8 L8

1 R9001

B

SCD1U10V2KX-5GP

C

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

8VRAM 8VRAM 8VRAM 8VRAM

A8 A1 C1 C9 D2 E9 F1 H9 H2



SCD1U10V2KX-5GP

C9022

K8 K2 N1 R9 B2 D9 G7 R1 N9

C9002

K8 K2 N1 R9 B2 D9 G7 R1 N9

SCD1U10V2KX-5GP

C9012

SC1U6D3V2KX-GP

C9004

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C9026

C9015

8VRAM

C9003

SC1U6D3V2KX-GP

C9021

C9007

SC1U6D3V2KX-GP

C9018

85

SC1U6D3V2KX-GP

C9016

8VRAM 8VRAM DY

FBB_D[0..7]

1

VRAM6 VRAM5


243R2F-2-GP

85 85

FBB_CLK0 FBB_CLK0#

J7 K7

CK CK#

85

FBB_CMD3

K9

CKE

85 85

FBB_DQM3 FBB_DQM2


D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#

FBB_D[16..23]

85

FBB_D[24..31]

85


E3 F7 F2 F8 H3 H8 G2 H7



D7 C3 C8 C2 A7 A2 B8 A3


DQSU DQSU#

C7 B7


DQSL DQSL#

F3 G3


ODT

K1

FBB_CMD2 85

CS# RESET#

L2 T2



M7 L9 L1 J9 J1

FBB_CMD14 85,91


J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1


G1 F9 E8 E2 D8 D1 B9 B1 G9

8VRAM

C

B

K4W 4G1646B-HC11-GP K4W 4G1646B-HC11-GP

72.41646.00U

72.41646.00U

1

1D5V_VGA_S0

1

1D5V_VGA_S0

FBB_CLK0

R9006 1K33R2F-GP8VRAM

2 VRAM5_VREF

A

1


C9014 SCD1U10V2KX-5GP 8VRAM


2

2


2

FBB_CLK0#

M14 DIS

1 1


2

VRAM6_VREF

1

R9009

8VRAM162R2F-GP

A

2

1

2

R9003 8VRAM 1K33R2F-GP

Title


4

3

2

Document Number

Rev



Sheet 1

90

of

A00 105

5

4

3

2

1

Frame Buffer Patition B-Upper Half

D

D

1D5V_VGA_S0

1D5V_VGA_S0

85

FBB_CMD19

K9

85 85

FBB_DQM5 FBB_DQM7

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#


1





M2 N8 M3

BA0 BA1 BA2


CS# RESET#

L2 T2



M7 L9 L1 J9 J1

FBB_CMD14 85,90


J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 8VRAMVSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

CKE

1

FBB_CMD18 85

1

K1

2 1

2 1

C9124

C9122

C9117


1 R9102 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90

2 8VRAM

2

2

2

2

2

2

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

J7 K7

ODT

VREFDQ VREFCA ZQ

2

2 1

2 1

2 1

2 1

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

FBB_CLK1 FBB_CLK1#


H1 M8 L8

C9123

1

CK CK#

85 85

DQSL DQSL#

F3 G3


85

2

BA0 BA1 BA2

243R2F-2-GP

C7 B7

1

M2 N8 M3

85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90

2 8VRAM

DQSU DQSU#

A8 A1 C1 C9 D2 E9 F1 H9 H2

2


1 R9104


FBB_D[40..47]

SC1U6D3V2KX-GP


C


8VRAM 8VRAM 8VRAM DY

SC1U6D3V2KX-GP


C9130


C9106

K8 K2 N1 R9 B2 D9 G7 R1 N9

SCD1U10V2KX-5GP


C9120

D7 C3 C8 C2 A7 A2 B8 A3


VREFDQ VREFCA ZQ

C9126


C9104

SC1U6D3V2KX-GP

H1 M8 L8

C9127



C9105

SC1U6D3V2KX-GP


85


SCD1U10V2KX-5GP

A8 A1 C1 C9 D2 E9 F1 H9 H2

FBB_D[56..63]

E3 F7 F2 F8 H3 H8 G2 H7

SC1U6D3V2KX-GP



B

VRAM8

K8 K2 N1 R9 B2 D9 G7 R1 N9

1

C9119

2

C9128

1

C9107

1

C9109

1

1

VRAM7


243R2F-2-GP

85 85

FBB_CLK1 FBB_CLK1#

J7 K7

CK CK#

85

FBB_CMD19

K9

CKE

85 85

FBB_DQM6 FBB_DQM4

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#


K4W 4G1646B-HC11-GP

FBB_D[32..39]

85


E3 F7 F2 F8 H3 H8 G2 H7



D7 C3 C8 C2 A7 A2 B8 A3


DQSU DQSU#

C7 B7


DQSL DQSL#

F3 G3


ODT

K1

FBB_CMD18 85

CS# RESET#

L2 T2



M7 L9 L1 J9 J1

FBB_CMD14 85,90


J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 8VRAMVSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

FBB_D[48..55]

85

C

B

K4W 4G1646B-HC11-GP

72.41646.00U

72.41646.00U

1

1D5V_VGA_S0

1

1D5V_VGA_S0

FBB_CLK1

VRAM7_VREF

VRAM8_VREF

M14 DIS

1

1

A

2




2


FBB_CLK1#


2

2

1

1

R9109 162R2F-GP 8VRAM

A

2

1

2


2


Title


4

3

2

Document Number

Rev

OAK14 Chief River DIS W ednesday, September 05, 2012 Sheet

1

91

of

A00 105

5

4

3

V-BOOT

VID0

VID1

VID2

VID3

VID4

VID5

VID6

0.9000V

0

0

0

0

1

1

0

2

1

D

D

1

1

DY

2

2

10KR2J-3-GP

PR9207

DY

10KR2J-3-GP

1

PR9206

DY

2

10KR2J-3-GP

1

1

PR9205

DY

2

2

2

2

PR9204

OPS

PWR_VGA_CORE_VID6 PWR_VGA_CORE_VID5 PWR_VGA_CORE_VID4 PWR_VGA_CORE_VID3 PWR_VGA_CORE_VID2 PWR_VGA_CORE_VID1 PWR_VGA_CORE_VID0

PR9214

OPS

OPS

2

2

10KR2J-3-GP

2

1

1 PR9213

OPS

10KR2J-3-GP

PR9212

OPS

2

2

1

1 PR9211

DY

10KR2J-3-GP

PR9210

DY

10KR2J-3-GP

PR9209

OPS

2

10KR2J-3-GP

PR9208

10KR2J-3-GP

0R0402-PAD

1

2 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 1

OPS OPS OPS OPS OPS OPS

2

1 PR92151 PR92161 PR92171 PR92181 PR92411 PR9242

1

NV_VID5 NV_VID4 NV_VID3 NV_VID2 NV_VID1 NV_VID0

NV_VID5 NV_VID4 NV_VID3 NV_VID2 NV_VID1 NV_VID0

10KR2J-3-GP

86 86 86 86 86 86

PR9203

OPS

10KR2J-3-GP

1 PR9202

DY

10KR2J-3-GP

10KR2J-3-GP

PR9201

10KR2J-3-GP

1

3D3V_S0

5V_S0

83.R5003.C8F

Please confirm with H/W for resistor pull high and pull GND PD9201

OPS

1

DY

CH551H-30PT-GP

DCBATOUT PWR_VGA_CORE_VR_ON

2 0R0402-PAD

OPS 2

2

OPS

OPS

2

1

1

1 2

2

1 2

5 6 7 8

1

OPS 2

1 2

OPS 79.47719.2BL 2ND = 77.24771.13L 2

PG9207

1

PG9206

GAP-CLOSE-PWR-3-GP

84.00035.037

1

OPS

2

5 6 7 8 4

GAP-CLOSE-PWR-3-GP

OPS 3 2 1

OPS

3 2 1

5 6 7 8 3 2 1 5 6 7 8

2 1 1

1

1

PC9210

2

79.47719.2BL 2ND = 77.24771.13L

PWR_VGA_CORE_CSCOMP_R PWR_VGA_CORE_LG

69.60029.001 2nd = 69.60028.001

1

OPS

PR9238

2

174KR2F-GP

1

2

PWR_VGA_CORE_L_L

240KR3-GP

OPS

B

1

2

OPS


2


PWR_VGA_CORE_CSCOMP

1 2

VGA_SENSE

PC9209

2 PR9234 20KR2F-L-GP

2

PR9236 76K8R2F-GP

OPS

2

2

PC9212 SC2D2U10V3KX-1GP

PR9237

1

2

OPS

OPS

PU9204

3 2 1

32 31 30 29 28 27 26 25 EN VID0 VID1 VID2 VID3 VID4 VID5 VID6 IREF RPM RT RAMP LLINE CSREF CSFB CSCOMP PWR_VGA_CORE_LLINE PWR_VGA_CORE_CSREF PWR_VGA_CORE_CSFB PWR_VGA_CORE_CSCOMP

2 1 PWR_VGA_CORE_RAMP_1

PR9233 20KR2F-L-GP

GND_3211

83

1


1

OPS GND_SENSE

1

2

1

1 2

OPS

422KR2F-1-GP

PU9203

84.00035.037

SC1200P50V2KX-1GP

1

OPS PR9231

PR9232 1KR2F-3-GP

VGA_SENSE

OPS

4

SC330P50V2KX-3GP

GND_3211

OPS 2

PR9230

OPS

300KR2F-L-GP

300KR2F-L-GP

1 2

80K6R2F-GP

PR9229

OPS

PL9201

1

IND-D22UH-31-GP

9 10 11 12 13 14 15 16

1 2

2

SC22P50V2JN-4GP

1

SC100P50V2JN-3GP

PWR_VGA_CORE_FB_L

1

OPS 2

PR9227 0R0402-PAD

1

OPS 2

PR9226 0R0402-PAD

PR9228

DCBATOUT

GND_SENSE

PWR_VGA_CORE_UG

PT9202 SE470UF2VDM-GP

PWR_VGA_CORE_RAMP

C

Design Current = 27A OCP>40A VGA_CORE

PWR_VGA_CORE_SW

PWR_VGA_CORE_LG

GND_3211 PWR_VGA_CORE_IREF PWR_VGA_CORE_RPM PWR_VGA_CORE_RT

PWR_VGA_CORE_FB_R

B

83


PC9215

OPS

PT9201 SE470UF2VDM-GP

74.03211.033

PR9224 20KR2F-L-GP

OPS 2

OPS

5V_S0

S S S

ADP3211MNR2G-GP

1

OPS

SCD01U50V2KX-1GP

08/01 PWR_VGA_CORE_CSCOMP


1K65R2F-GP

PWR_VGA_CORE_BOOT_R

OPS


OPS

PC9206

OPS

OPS 2

G

PR9223 1KR2F-3-GP

2

1

4

D D D D

1

PWR_VGA_CORE_BOOT PWR_VGA_CORE_UG PWR_VGA_CORE_SW

S S S

OPS

2

2

24 23 22 21 20 19 18 17 33


1

OPS

VCC BST DRVH SW PVCC DRVL PGND GND GND

OPS

G

OPS

2

1

5V_S0 PWR_VGA_CORE_ILIM

PWRGD IMON CLKEN# FBRTN FB COMP GPU ILIM

D D D D


1

PR9225

1 2 3 4 5 6 7 8

OPS


PWR_VGA_CORE_FBRTN PWR_VGA_CORE_FB PWR_VGA_CORE_COMP

OPS

4 PR9240 0R2J-2-GP

S S S

22,27,93 DGPU_PWROK

2

PC9204

GND_3211

G

DY

66K5R2F-GP

PC9214

OPS

PU9205

D D D D

PR9222

1


SC1KP50V2KX-1GP

PU9202

S S S

OPS 2


G

1

GND_3211

OPS

D D D D

PU9201 PC9203

PC9213

SC10U25V5KX-GP

C

SC10U25V5KX-GP

DY


PWR_VGA_CORE_VCC

PR9219

1

OPS

1

3D3V_VGA_S0

PR9220 10R2J-2-GP

2

2

93 DGPU_PWR_EN

1

2nd = 83.R5003.G8H 3rd = 83.R5003.H8H 4th = 83.5R003.08F

GND_3211

PR9239

1

OPS

2

0R0402-PAD

Please confirm on H/W side whether have resistor pull high and pull GND by 100 ohm GND_3211

A

A

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHK 0.36UH PCMC104T-R36MH 1.05mohm/ Isat =60A rms68.R3610.20S O/P cap: CHIP CAP 470UF 2V EEFSX0D471X/ 3.5Arms Panasonic/79.47719.2BL H/S: RJK03J6DPA-00#J5A / 10mohm/[email protected]/ 84.00036.037 L/S: RJK03K5DPA-00#J5A / 3mohm/[email protected]/ 84.00035.037

M14 DIS


ADP3211_+VGA_CORE Size Document Number Custom

Rev

DNE40 14 CR DIS

Date: 5

4

3

2


Sheet

A00 92

of

105

5

4

3

1

1D05V_VGA_S0 3D3V_VGA_S0 should ramp-up before

VGA_Core

ramp-up before 1D5V_VGA_S0

1D5V_VGA_S0 should

ramp-up before 1D05V_VGA_S0

2 0R2J-2-GP

DY

1.05V +/- 5% 2.872A

VCCP_CPU

DMP2130L-7-GP

2

D

1

1 OPS

PC9305 SC10U6D3V3MX-GP

2nd = 84.00102.031

1 2 3 4

Decap

AO4468-GP

84.04468.037 2nd = 84.02659.037 3rd = 84.04178.037 4th = 84.04496.037 5th = 84.04800.D37

4th = 84.02301.G31

PR9304 10KR2F-2-GP

1D05V_VGA_S0 D

S S S G

OPS

OPS

3D3V_VGA discharge

3rd = 84.03413.A31

PQ9302_G

2

84.02130.031

8 7 6 5

1

OPS

G

2

G

PC9301 OPS SCD1U10V2KX-5GP

AO4468, SO-8 Id=?A, Qg=9~12nC Rdson=17.4~22m ohm

D

2

1

S PQ9301 D

OPS

PR9303 10KR2F-2-GP

PU9303 D D D D

1

PR9301 1

3D3V_S0

VGA_Core should

3D3V_VGA_S0

DY PC9308 SC10U6D3V3MX-GP 2

3.3V +/- 5% 274mA

1D05V_ENABLE_RC

3D3V_VGA_S0

2

1D05V_VGA_S0

PR9319_1

1

DGPU_PWR_EN

H

PQ9303 2N7002BK-GP

IGPU with BACO

L

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

1D5V_VGA_S0


92

3.3V +/- 5% 4.88A

1D5V_PWR

DIS_1D05V_VGA_S0 2

4

D

D1

2

5 G1

S1

6 D2

1D05V_VGA_EN

S S S G

1 2 3 4

OPS

OPS

AO4468-GP

84.04468.037 2nd = 84.02659.037 3rd = 84.04178.037 4th = 84.04496.037 5th = 84.04800.D37

C

1D05V_VGA_EN#

G

OPS

PQ9307 2N7002BK-GP

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

OPS

NV do not need 1.8V 1D5V_VGA_S0

1

PU9302 D D D D

1D5V_ENABLE_RC

1

8 7 6 5

2

B

2 1KR2J-1-GP

2

L

IGPU


OPS

PR9313

OPS 100KR2J-1-GP

1D05V_ENABLE

dGPU mode

AO4468, SO-8 Id=?A, Qg=9~12nC Rdson=17.4~22m ohm

PR9307 1

15V_S5

S

22,27,92 DGPU_PWROK

D

OPS

S G D

1

CH551H-30PT-GP

OPS

OPS


2

DGPU_PWR_EN#

DY

PR9316 470R2J-2-GP

1

DGPU_PWR_EN

G

22 DGPU_PWR_EN#

2

OPS

3

PD9302 92 DGPU_PWR_EN

84.2N702.F3F 2nd = 84.2N702.A3F 3rd = 84.DMN66.03F

0R0402-PAD

OPS

D G S

G2

2nd = 83.R5003.G8H 3rd = 83.R5003.H8H 4th = 83.5R003.08F

C

S

PQ9305 ME2N7002DKW-G-GP

83.R5003.C8F

S2

3.3V_RUN_VGA_1

2

3

1 OPS 2 PR9311 100KR2J-1-GP

PR9305 10KR2J-3-GP 1 DY 2

3D3V_S0

PC9304 SCD01U50V2KX-1GP 1D05V_VGA_EN#

1

2

3D3V_AUX_S5

Discharge Circuit

2

4

5

S1

PR9315 100KR2J-1-GP 1 OPS 2

D1

G1

D2

1

PR9302

OPS 220R2J-L2-GP

2

1

RUNPWROK

OPS

G2

6

1 19,45,46,47

S2

84.2N702.F3F 2nd = 84.2N702.A3F 3rd = 84.DMN66.03F

2


OPS

1

PR9312

1

B

PR9308

1D5V_VGA_EN#

0R0402-PAD

OPS

DIS_1D5V_VGA_S0 2

D1

3

2

5

4

OPS

PR9309 100KR2J-1-GP

D

1D5V_VGA_EN

S G D

15V_S5

1

1

OPS

S1

6

DY

CH551H-30PT-GP PR9306 1 OPS 2

PR9314 470R2J-2-GP

1D5V_ENABLE 1D5V_VGA_EN#

A

G

OPS

A

PQ9306 2N7002BK-GP

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

M14 DIS

S

22,27,92 DGPU_PWROK

2

84.2N702.F3F 2nd = 84.2N702.A3F 3rd = 84.DMN66.03F

1

PD9301

S2


2nd = 83.R5003.G8H 3rd = 83.R5003.H8H 4th = 83.5R003.08F 92 DGPU_PWR_EN

D2

83.R5003.C8F

1D5V_VGA_S0

Discharge Circuit

OPS

D G S G1

2

G2

OPS

PR9310 100KR2J-1-GP

2

1

2

1

3D3V_AUX_S5

OPS

0R0402-PAD

2


1

1


DISCRETE VGA POWER

Size Document Number Custom

Rev


Date: 5

4

3

2


Sheet 1

93

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS A

A


LVDS_Switch Size A3 Date: 5

4

3

2

Document Number

Rev


94

A00 of

105

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

M14 DIS A

A


CRT_Switch Size A3 Date: 5

4

3

2

Document Number

Rev


95

A00 of

105

5

4

3

2

1

SSID = SDIO

D

D

C

C

(Blanking)

B

B

M14 DIS

A

A


TOUCH PANEL Size A3 Date: 5

4

3

2

Document Number

Rev



Sheet 1

96

A00 of

105

5

4

3

2

1

SSID = Mechanical S2 STF237R117H83-1-GP

34.4CK01.001

1

S3 STF237R113H111-GP

1

1

S1 STF237R117H83-1-GP

34.4CK01.001

34.4V802.001

D

D

H4 H3 HOLE335R115-GP

HOLE256R115-GP

H5 HT85BE85R29-U-5-GP

ZZ.00PAD.D41

ZZ.00PAD.D01

ZZ.00PAD.D11

ZZ.00PAD.D41

H9 HOLE237R95-GP

H8 HOLE237R95-GP


ZZ.00PAD.D41 1

1

1

1

1

1

1

ZZ.00PAD.D01


1

H1 HOLE335R115-GP

ZZ.00PAD.921 ZZ.00PAD.921

C3 HOLE197R166-1-GP

1

1

ZZ.00PAD.V71

C

C2 HOLE197R166-1-GP

1

C1 HOLE197R166-1-GP

SPR3 SPRING-102-GP

1

1

SPR2 SPRING-102-GP

ZZ.00PAD.V71

ZZ.00PAD.V71

34.41V01.001 34.41V01.001

C

CPU BRACKET

SSID = EMI

1 2

1

1 2

2

2

2

1

1

1 2

1 2

1 2

1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

1

EC9732

DY

DY 2

2

1 2

1 2

1 2

1 2

2

1

1 2

1 2

1 2

2

1

EC9734

DY

EC9733 SC1U6D3V2KX-GP

EC9736

DY

SC1U6D3V2KX-GP

EC9738

DY

SC1U6D3V2KX-GP

EC9735

DY

SC1U6D3V2KX-GP

EC9737

DY

SC1U6D3V2KX-GP

1 2

2

1 2

1 2

1 2

1 2

1 2

1 2 1 2

1 2 1 2

1 2 2

1

1 1 2

2 2

2

1 1

2 2

1

EC9750

DY

EC9745


UNUSED PARTS/EMI Capacitors Date:

4

3

A

M14 DIS

Size A3 5

EC9744

5V_S5

SC1U6D3V2KX-GP

1

SCD1U25V2ZY-1GP

EC9749

DY

EC9748 SCD1U25V2ZY-1GP

EC9747

DY

EC9746

SCD1U25V2ZY-1GP


2

EC9743

SCD1U25V2ZY-1GP

2

EC9739

SCD1U25V2ZY-1GP

AUD_AGND

SCD1U25V2ZY-1GP


1

EC9731

DY

SCD1U25V2ZY-1GP

2

EC9729

DY

SCD1U25V2ZY-1GP

EC9740

3D3V_S0

SC1U6D3V2KX-GP

1

EC9728

SCD1U25V2ZY-1GP

DY


2

EC9730

SC1U6D3V2KX-GP

DY

B

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP


EC9721

DY

SC1U6D3V2KX-GP

A

EC9723

DY

SC1U6D3V2KX-GP

EC9718

DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

EC9719

DY

SC1U6D3V2KX-GP

EC9720

EC9726

DCBATOUT

5V_S0

DY

DY

SC1U6D3V2KX-GP

EC9725

DY

SC1U6D3V2KX-GP

EC9727

SC1U6D3V2KX-GP

DY

SC1U6D3V2KX-GP

EC9710

SC1U6D3V2KX-GP


EC9717

DY


SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

EC9715

DY

EC9716

EC9707

SC1U6D3V2KX-GP


SCD1U25V2ZY-1GP

EC9714

DY

EC9705

SCD1U25V2ZY-1GP


EC9712

DY

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

EC9713

DY


SCD1U25V2ZY-1GP EC9711

DY

B

EC9703

DY

SCD1U25V2ZY-1GP

EC9701

1

1D5V_VGA_S0

SCD1U25V2ZY-1GP

1

DCBATOUT

2

Document Number

Rev



Sheet 1

97

A00 of

105

5

4

3

2

1

Chief River Platform Power Sequence (AC mode) +RTC_VCC

(DC mode)

Red Words: Controlled by EC GPIO

RTC_RST# DCBATOUT

DCBATOUT Within logic high level and disable if it is less than the logic low level.

3D3V_AUX_S5

3D3V_AUX_S5

D

KBC GPIO34 control power on by 3V_5V_EN

S5_ENABLE Ta V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within 0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

Press Power button

Sense the power button status

Platform to KBC PSL_IN2

KBC_PWRBTN#

5V_S5

PSL_OUT#(GPIO71) keep low

3D3V_S5

Ta

3D3V_AUX_KBC

+5VA_PCH_VCC5REFSUS

5V_S5

PCH to KBC GPIO00

PCH_SUSCLK_KBC

t07 >5ms

AC_PRESENT

0ms
KBC GPIO34 control power on by 3V_5V_EN

S5_ENABLE

KBC GPIO43 to PCH t05 >10ms

PM_RSMRST#(EC Delay 40ms)

Not floating.

t01 >9ms

+RTC_VCC t01 >9ms

RTC_RST#

D

Red Words: Controlled by EC GPIO

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within 0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

KBC GPO84 to PCH

5V_S5 & 3D3V_S5 need meet 0.7V difference

3D3V_S5


+5VA_PCH_VCC5REFSUS

Ta

KBC GPIO43 to PCH t05 >10ms

PM_RSMRST#(RSMRST#_RST) 3D3V_AUX_KBC Sense the power button status

This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input.

In case of a non-Deep S4/S5 Platform timing t42 should be added to t07 which will make it 100mS minimum.

Press Power Button

t07 >100ms

PCH to KBC GPIO00

PCH_SUSCLK_KBC

Platform to KBC PSL_IN2

KBC GPIO20 to PCH

AC KBC_PWRBTN#

PM_PWRBTN#

KBC GPIO20 to PCH AC PM_PWRBTN# DC PM_PWRBTN#

After Power Button

After Power Button

PCH to KBC GPIO44 PM_SLP_S4#

t10

PCH to KBC GPIO44

PCH to KBC GPIO01

>30us

PM_SLP_S3#

PM_SLP_S4#

Enable by PM_SLP_S4#

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

Enable by PM_SLP_S4#

1D5V_S3

DDR_VREF_S3(0.75V) Tb

KBC GPIO47 to LAN

PM_LAN_ENABLE

1D5V_S3 C

PCH to KBC GPIO01

>30us

PM_SLP_S3#

KBC GPIO47 to LAN

PM_LAN_ENABLE

t10

C

DDR_VREF_S3(0.75V)


5V_S0


5V_S0 V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

3D3V_S0 +5VS_PCH_VCC5REF

Tb

1D5V_S0

3D3V_S0 +5VS_PCH_VCC5REF

Tb

1D5V_S0

1D8V_S0

1D8V_S0

0D75V_S0

0D75V_S0

1D8V_S0 & 1D5V_S3 power ready

RUNPWROK

RUNPWROK

VCCP_CPU

1D05V_PCH

1D05_VTT_PWRGD

VCCP_CPU

0D85V_S0

1D05_VTT_PWRGD

1D8V_S0 & 1D5V_S3 power ready

0D85V_S0

0D85V_S0

0D85V_S0

D85V_PWRGD

D85V_PWRGD SetVID

CPU SVID BUS

ACK

50us< t36 <2000us

SetVID

CPU SVID BUS

VCC_CORE

ACK

50us< t36 <2000us

VCC_CORE

VCC_GFXCORE

VCC_GFXCORE

t37

t37

<5ms

IMVP_PWRGD

<5ms

IMVP_PWRGD

B

B

PCH_CLOCK_OUT This signal represents the Power Good for all the non-CORE and non-graphics power rails.

PCH_CLOCK_OUT

ALL_SYS_PWRGD=D85V_PWRGD

t14 >99ms

PWROK(S0_PWR_GOOD)

KBC GPIO77 to PCH t18 >0us

D85V_PWRGD

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

t14 >99ms

KBC GPIO77 to PCH t18 >0us

D85V_PWRGD

2ms
DRAMPWROK(VDDPWRGOOD)

ALL_SYS_PWRGD=D85V_PWRGD PWROK(S0_PWR_GOOD)

PCH to CPU

PCH to CPU

2ms
DRAMPWROK(VDDPWRGOOD)

t19 >1ms

t19 >1ms

t20 >2ms

1D8V_S0

5ms
1D8V_S0

PCH to CPU

UNCOREPWRGOOD(H_CPUPWRGD)

t20 >2ms 5ms
PCH to CPU

UNCOREPWRGOOD(H_CPUPWRGD)

t21+t22 >1ms+60us

SYS_PWROK 1ms<

t25 <100ms

PLT_RST#

t21+t22 >1ms+60us

SYS_PWROK 1ms<

PCH to all system PLT_RST#

t39 <200us

DMI

t25 <100ms

PCH to all system t39 <200us

DMI

N13M-GS Power-Up/Down Sequence 3D3V_S0

PCH GPIO54 output

DGPU_PWR_EN#(Discrete only) 3D3V_VGA_S0(VDD33) A

8209A_EN/DEM_VGA(Discrete only)

A

tNVVDD >0ms

VGA_CORE(NVVDD)

RT8208 PGOOD

DGPU_PWROK(Discrete only) 1D5V_VGA_S0(FBVDDQ)

tNV-FBVDDQ

>0ms tNV-PEX_VDD >0ms

1D05V_VGA_S0(PEX_VDD)

VGA_CORE,1D05V_VGA_S0 1D5V_VGA_S0,3D3V_VGA_S0

First rail to power down

M14 DIS

Wistron Corporation

Last rail to power down tPOWER-OFF

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

<10ms Title

Power Sequence Size A1

For power-down, reversing the ramp-up sequence is recommended.

Date: 5

4

3

2

Document Number

Rev


Sheet

98

A00 of

105

5

4

3

2

1

OAK14 Chief River POWER UP SEQUENCE DIAGRAM 5V_S5

-6 AC Adapter in

DCBATOUT

AD+

-3.1

Page38

-3.1

-3.1 VDDP

PWR_5V3D3V_ENC

D

3V_5V_EN

VIN

S5_ENABLE

VOUT

1D5V_S3 D

3 PM_SLP_S4#

-3.2 PWR_CHG_ACOK

-3.3

EN

DDR_VREF_S3

REF

SWITCH

ENC

LL1

Page40

LL2 VREG5

TPS51125 DC/DC (3V/5V)

-6.1 DCBATOUT

VREG3

VIN

PGOOD

5V_S5

PUMP

3D3V_S5 5V_AUX_S5

15V_S5

TPS51216RUK 0D75V_S0

VTT

3D3V_AUX_S5

-5

3V_5V_POK

-2

3

RUNPWROK

PGD

PM_SLP_S4#

Page46

5

Page41

DC Battery

5V_S5

4

BQ24707 Charger

BT+

-3

Page39

SWITCH Page37

BJT

3D3V_AUX_KBC

VDD

-3.1

Page40 ACOK

-4

1D8V_S0

EN

RUNPWROK PGD

1D5V_S0

Page47

SWITCH

C

C

5

Page37

1 -1

VOUT

SYW231ABC

PM_SLP_S3#

Page37

GPIO34

GPIO70

VIN

4

3D3V_S0 SWITCH

S5_ENABLE

AC_IN#

3D3V_S5

5V_S0

PM_SLP_S3#

KBC_PWRBTN#

SLP_S4#

KBC NPCE885P

GPIO6

-2.1

Power Button

PM_SLP_S4#

GPIO43

GPIO44

PM_SLP_S3#

GPIO20

GPIO01

SLP_S3#

PM_RSMRST# PM_PWRBTN#

11 RSMRST# PWRBTN#

Pather Point PCH

Y

VDDPWRGOOD

SM_DRAMPWROK

A

H_CPUPWRGD

PROCPWRGD

GPIO77

B

DRAMPWRGD

2 Page27

AND GATE

0D75V_EN PM_DRAM_PWRGD

H_CPUPWRGD_R

UNCOREPWRGOOD

12

Ivy Bridge CPU

13

S0_PWR_GOOD APWROK PWROK

PLT_RST#

BUF_CPU_RST#

PLTRST#

SYS_PWROK

RSTIN#

SVID

SYS_PWROK SVID

10 5V_S5

B

V5IN

VIN VOUT

5 RUNPWROK

EN

Page45

PGOOD

S0_PWR_GOOD

VIN VOUT

5a

1.05VTT_PWRGD

IMVP_PWRGD

10

AND GATE

SYS_PWROK

A Y B

5a

5V_S5 DCBATOUT

1.05VTT_PWRGD

B

1D05_VTT

TPS51219RTER

VDDP

-5

0D85_S0

-7

TPS51463 Page48

-8

PGOOD

+RTC_VCC

6 DCBATOUT

8 A

6

7

D85V_PWRGD

IMVP_VR_ON

3D3V_AUX_S5

RTC_AUX_S5 D85V_PWRGD

EN

RTC battery

VIN

OUTPUT

SVID

8

DCBATOUT

VCC_CORE

SVID

VCC_GFXCORE

VR_ON

IMVP_PWRGD

VR OUTPUT VT1318+1323

A

9 Page42 & 43 & 44 PGOOD

M14 DIS

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Power Up Sequence: -8 ~ 13

Title Size A2 Date:

5

4

3

2

Power Sequence Diagram

Document Number

Rev


Sheet

99

of

A00 105

5

4

3

2

1

DCBATOUT

Adapter

TPS51219DSCR

TPS51216RUKR

ADP3211

AO4407A

D

D

Charger 1D05V_VTT

BQ24707

1D5V_S3

+PBATT

Battery

0D75V_S0

VGA_CORE

AO4468 TPCA8062

AO4468

1D05V_VGA_S0 1D5V_S0

1D5V_VGA_S0

C

C

TPS51225ARGER

15V_S5

3D3V_AUX_S5

5V_AUX_S5

5V_S5

TPS51463

G547F2P81

3D3V_S5

AO4468

ISL95833

ADP3211

AO4468 SYW231

0D85V_S0

5V_USB2_S0

5V_S0

3D3V_S0 VCC_CORE

1D8V_S0

VCC_GFXCORE

AO3403

3D3V_LAN_S5

B

B

SY6288

ODD_PWR_5V

G5285T11

LCDVDD

RT9724

3D3V_CARD_S0

DMP2130L

3D3V_VGA_S0

Power Shape M14 DIS

A

Regulator

LDO

A

Wistron Corporation

Switch

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:

5

4

3

2

Power Block Diagram

Document Number


Sheet 1

100

Rev

A00 of

105

A

B

C

3D3V_S5

3D3V_S0

‧

‧

KBC SMBus Block Diagram

PCH SMBus Block Diagram

D

3D3V_S0

‧

3D3V_S0

‧

SRN2K2J-1-GP

1

SMBCLK

SMB_CLK

SMBDATA

SMB_DATA

3D3V_S5

‧ ‧

SML1DATA

‧‧

DIMM 1

‧ ‧

SRN10KJ-5-GP

SCL

PCH_SMBDATA

SDA

SMBus Address:A0

PSDAT1

TPDATA

PSCLK1

TPCLK

TouchPad Conn.

‧ ‧

2N7002SPT

TPDATA

TPDATA

TPCLK

TPCLK

1

3D3V_AUX_KBC 3D3V_S5

SRN2K2J-8-GP

SML1CLK

SRN2K2J-1-GP

PCH_SMBCLK

‧

E

‧ ‧

‧

SML1_CLK

To KBC

SML1_DATA

SML0CLK

SML0_CLK

SML0DATA

SML0_DATA

‧

DIMM 2 PCH_SMBCLK

SCL

PCH_SMBDATA

SDA SRN4K7J-8-GP

SRN2K2J-1-GP

SMBus Address:A4 GPIO17/SCL1

TPAD

GPIO22/SDA1

‧‧ ‧ ‧

Battery Conn.

SRN33J-7-GP

BAT_SCL

PBAT_SMBCLK1

CLK_SMB

BAT_SDA

PBAT_SMBDAT1

DAT_SMB

SMBus address:16

SMB_CLK

PCH_SMBCLK

BQ24707

SMB_DATA

PCH_SMBDATA

KBC NPCE885P

SCL SDA

SMBus address:12

2

2

3D3V_AUX_KBC

PCH 3D3V_S5

3D3V_S0

SML1DATA

‧ ‧

‧

‧

SCL SDA

NCT7718W

SRN2K2J-8-GP

3D3V_S0

‧

SRN2K2J-8-GP

SML1CLK

‧

‧

SML1_CLK SML1_DATA

SRN4K7J-8-GP

‧ ‧

THM_SML1_CLK

SCL

Thermal

GPIO73/SCL2

SML1_CLK

SCL

GPIO74/SDA2

SML1_DATA

SDA

PCH

THM_SML1_DATA SDL

SMBus Address:98 2N7002SPT

3D3V_VGA_S0

‧

SRN4K7J-8-GP

3D3V_VGA_S0

VGA

‧

3

THM_SML1_CLK

SMBC_Therm_NV

THM_SML1_DATA

SMBD_Therm_NV

3D3V_S0

‧ ‧ SMBus Address:9E

3

I2CS_SCL I2CS_SDA

5V_HDMI_S0_R

‧

‧ 3D3V_S0

‧

SRN2K2J-1-GP

SDVO_CTRLCLK SDVO_CTRLDATA

‧ ‧

‧‧

PCH_HDMI_CLK PCH_HDMI_DATA

SRN1K5J-GP

‧ ‧

DDC_CLK_HDMI DDC_DATA_HDMI

HDMI CONN

2N7002DW-1-GP

3D3V_S0

‧

4

4

SRN2K2J-1-GP

L_DDC_CLK L_DDC_DATA

‧ ‧

M14 DIS

LVDS_DDC_CLK_R

LVDS_DDC_CLK

CLK

LVDS_DDC_DATA_R

LVDS_DDC_DATA

DATA

LCD CONN

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date:

A

B

C

D

SMBUS Block Diagram

Document Number


Wednesday, September 05, 2012 E

Sheet

101

Rev

A00 of

105

5

4

3

2

1

OAK14 DIS CLK Block Diagram D

CK0 CK0#

DDR3 DIMM1

CK1 CK1#

CPU Ivy & Sandy

M_A_DIMA_CLK_DDR0

PCH Panther Point CLKOUTFLEX1/GPIO65

SA_CK0

M_A_DIMA_CLK_DDR#0

CLK_PCH_48M

SA_CLK#0

M_A_DIMA_CLK_DDR1 M_A_DIMA_CLK_DDR#1

SA_CK1

BCLK

SA_CLK#1

BCLK#

CLK_EXP_P CLK_EXP_N

CK0#

DDR3 DIMM2

CK1 CK1#

M_B_DIMB_CLK_DDR0

CLK_PCIE_WLAN#

CLKOUT_PCIE2P

C

VRAM1

CK0#

LAN RTL8105E-VD

SB_CLK#1

CLK_PCIE_LAN

FBA_CLK0

VRAM2

CK0

FBA_CLK0#

CK0#

PEX_REFCLK#

FBA_CLK0 FBA_CLK0#

PEX_REFCLK

PIN 19

CLK_PCIE_LAN#

CLKOUT_PCIE5N

VGA N13M-GSR N13P-GS-OP

FBA_CLK0#

PIN 20

LANXIN CLK_PCIE_VGA#

CLK_PCIE_VGA

VRAM3

CK0#

FBA_CLK1 XTAL_IN

FBA_CLK1#

C

CKXTAL1

CLKOUT_PEG_A_N X3101 25MHz

CLKOUT_PEG_A_P LANXOUT

CK0

WLAN

PIN 13

SB_CK1

M_B_DIMB_CLK_DDR#1

CLKOUT_PCIE5P CK0

PIN 11

CLK_PCIE_WLAN

SB_CLK#0

M_B_DIMB_CLK_DDR1

FBA_CLK0

D

CLKOUT_DMI_N

SB_CK0

M_B_DIMB_CLK_DDR#0

Card Reader RTS5170

CLKOUT_DMI_P

CLKOUT_PCIE2N CK0

CLK_IN

CKXTAL2

27MHZ_IN

X8601 27MHz

VRAM4

CK0 CK0#

FBA_CLK1 FBA_CLK1#

FBA_CLK1 FBA_CLK1#

XTAL_OUT

Audio ALC3221

27MHZ_OUT

HDA_BCLK

HDA_BITCLK

RN2102

HDA_CODEC_BITCLK

BITCLK

SRN33J-5-GP-U

B

RTC_X1

B

RTCX1

KBC NPCE885P

X2101 32.768KHz

RTC_X2

Regulatory Model: P22G Regulatory Type: P22G004

RTCX2

PCH_SUSCLK_KBC

SUSCLK/GPIO62

R1806

CLKOUT_PCI2 XTAL25_IN

GPIO0/EXTCLK CLK_PCI_KBC

LCLK/GPIOF5

XTAL25_IN

X2001 25MHz

CLKOUT_PCI1

XTAL25_OUT

22R2J-2-GP

CLKIN_PCILOOPBACK

XTAL25_OUT

CLK_PCI_FB_R

R1805 22R2J-2-GP

CLK_PCI_FB

A

A M14 DIS


CLK Block Diagram Size A2 Date:

5

4

3

2

Document Number

Rev

A00

OAK14 Chief River DIS Wednesday, September 05, 2012

1

Sheet

102

of

105

A

B

C

D

Thermal Block Diagram

E

Audio Block Diagram

1

1

3D3V_S5

PCH Pather Point

3D3V_S0

D+

PAGE28

NCT7718_DXP SPKR_L+ SPKR_LSPKR_RSPKR_R+

MMBT3904-3-GP SC2200P50V2KX-2GP

‧‧ ‧‧

SML1_DATA

GPIO75

2N7002

SML1_CLK

GPIO58

‧ ‧

THM_SML1_DATA

SDA

THM_SML1_CLK

SCL

DIS Thermal NCT7718

D-

Place near CPU PWM CORE

Codec ALC3221

MMBT3904-3-GP

HP MIC COMBO (IPhone Only)

AUD_HP1_JACK_L

T8 SML1_DATA

AUD_HP1_JACK_R

3D3V_VGA_S0 SML1_CLK

PAGE20

SPEAKER

NCT7718_DXN

2

THM_SML1_DATA

‧

T_CRIT#

THERM_SYS_SHDN#

2N7002

PURE_HW_SHUTDOWN#

EN

D

S

3V/5V

SLEEVE

3D3V_S0

RING2

G

Put under CPU(T8 HW shutdown)

THM_SML1_CLK

PAGE27

GPIO74

KBC NPCE885P

GPIO73

GPIO4 GPIO56

FAN1_DAC

3

SMBC_Therm_NV

I2CS_SCL

SMBD_Therm_NV

I2CS_SDA

2N7002

VGA

N13M-GSR N13P-GS-OP

TACH 3

FAN VIN

5V

VIN

PAGE86

FAN_TACH1

GPIO94

‧‧

2

VSET

Digital MIC

DMIC_CLK

VOUT

DMIC_DATA

FAN CONTROL

NCT3940S-A PAGE28

4

4

M14 DIS


Thermal/Audio Block Diagram

Size Document Number Custom Date: A

B

C

D


Sheet E

103

Rev

A00

OAK14 Chief River DIS of

105

5

D

C

B

4

Version

Date

PAGE

X01

5/10

P38

Dummy R3818 R3813 for DT Mode

X01

5/10

P20

Change CLK_PCIE_WLAN_REQ#

X01

5/10

P86

Dummy R8613 (for N13M-GS1 strappin)

X01

5/28

X01

5/30

P49

Add TPNL1 (USB20 port#3)

X01

5/30

P29

Add delay circuit for Audio Jack JD pin

X01

5/30

P59

Change RJ45 Conn

X01

6/1

P38

Stuff PQ3801 PR3814 PR3815 for DT mode

X01

6/1

P37

Change R3713 to 10k for sequence timming

X01

6/1

P31

Change R3118 to 20k for sequence timming

X01

6/1

P69

Add KBL1 and keyboard backlight function

X01

6/1

P27

Change PCB version from X00 to X01

X01

6/5

P46

Fine tune the level of 1d5v_vga_s0: PR4601 (47K -> 57.6K)

X01

6/5

P58

Add TVS at combo JACK & RJ45 for EMI request

X01

6/5

P18

Move the KB_LED_BL_DET from GPIO5 to GPIO4

X01

6/11

X01

6/11

P27

Delete RN2702 , DY R2716, Stuff R2717 For DT Mode

X01

6/11

P21

Add VRAM detect circuit at PCH_GPIO57

X01

6/11

P51

Change D5101 to 83.00056.G11 for lower internal cap

X01

6/12

P18

Move USB2.0 from port4# to port2#

X01

6/12

P49

Modify CAMERA1 to CAM1

X01

6/13

P61

Separate the USB3.0 PWR to USB30_VCCA & USB30_VCCB

X01

6/14

P49

Add LCD Back Light control circuit from KBC GPIO33

3

2

1

Description of Required Change

PU from 3D3V_S5 to 3D3V_S0 & change port 3 to port 2(non AOAC)

D

Update connector list(5/28) for X01

C

Implement EMI change request 6/11

X01

6/14

P40

implement Power team request item

X01

6/15

P31

Change C3102=C3103=18pf for Xtal vendor request

X01

6/15

P62

Modify cap value for USB30_VCCA & USB30_VCCB

X01

6/18

P69

DY the Keyboard back light parts, add R6916 for PU

X01

6/18

P61

Change TC6102 & TC6104 to 78.10710.52L; TC6103 to 79.10710.60L

X01

6/18

P20

Move WLAN from PCIE 4# to PCIE 3#

X01

6/18

P51

implement EMI team request item (6/15)

X01

6/18

P69

Remove R6916 Stuff R6912

X01

6/18

P69

Change Q6801~Q6805 & Q6902 to 84.00144.P11

B

M14 DIS

A

A


4

3

2

Change History

Document Number

Rev


Sheet 1

104

A00 of

105

5

D

4

Version

Date

PAGE

X02

7/30

P58

X02

7/30

X02

7/30

X02

7/31

X02

7/31

P71

Dummy DB1 circuit

X02

8/1

P58

Change HPMIC1 source and related circuit

X02

8/1

X02

8/6

3

2

1

Description of Required Change Add delay circuit at Audio Combo Jack update the connector symble, base on ME connector list 7/16

P69

Remove the Key board back ligh circuit

D

Modify 0 ohm to short PAD

update power team request change 8/1 P27

Move SERIES_ID to GPIO5

C

C

B

B

M14 DIS

A


Change History

Document Number

Rev


Sheet

105

A00 of

105

A

5

D

4

Version

Date

PAGE

A00

9/4

change 0 ohm to short pad

A00

9/4

combine CM choke & 0 ohm

A00

9/4

change close gap & DB1 to symble with solder mask

A00

9/4

27

change PCB version from SC to -1

A00

9/4

74

Replace EC7401 ~ EC7410 from 10p to 6.8p

A00

9/4

61

Remove CM Choke at USB3.0 side, dummy U6204 U6205

3

2

1

Description of Required Change

D

C

C

B

B

M14 DIS A

A


4

3

2

Change History

Document Number

Rev


Sheet 1

106

A00 of

106

Schema Placa mãe Dell Inspiron 14 - 3421 (PNB040)

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