RS – 485 1. Differential Comm. D+
RXD TXD
D-
In above diagram Left side is a d river, river, right side is a receiver. receiver. Interface will provide 2 signals from driver. D+ is primitive signal, reverse signal is D-. (If TXD
＝
0V, D+
＝
0V, D-
＝
5V. If TXD
＝
5V, D+
＝
5V, D-
＝
0V.) D+
－
D- > 0.2V, RXD
D+
－
D- <- 0.2V, RXD
0.2V > D+
－
＝
＝
5V 0V
D- > -0.2V, accept wrong coder.
In UART communication type, waiting mode always keep on “high” potential. So in d ifferential communication, RXS must keep on “high” potential, even there are not any connections and signals. So D+ TXD
D+
D-
RXD
－
D- > 0.2V.
5V
150K~ K~200K Ohm
RXD RXD
150K~ K~200K Ohm
GND
IC design house add 150K~200K pull high and pull low resistances in Differential receiver IC D+ and D- to avoid above problems. Refer Figure 5, D+ keep in 5V, D- keep in 0V, so D+
－
D- > 0.2V,
RXD do not accept low signals. But it will cause another problems after perform this design.
2. Signal and Noise Below is signal representation, S(t) = Σan(t)sin(2πnft + θn) + Φ This is Fourier transfer equation, all signals that are associated much Harmonics. We can make an assumption that Harmonic’s characters are same as noise. We can distribute S’(t) = a(t)sin(2πft + θ), one is amplitude - a(t) in equation, the other one is sin wave - sin(2πft + θ). According this rule, amplitude noise effect a(t), phase noise effect the equation that is sin(2πft + θ) add θn.
Amplitude Noise S’(t) = a(t)sin(2πft + θ) + an(t) represent Amplitude Noise equation, an(t) is amplitude noise in this equation. In ideal differential communication, the amplitude noises that connected i n two wires are equal. We can assume S1(t) = a1(t)sin(2πft1 + θ1), D- signa l is S2(t) = a2(t)sin(2πft2 + θ2), after add an amplitude noise, then equation will become S1’(t) = a1(t)sin(2πft1 + θ1) + n(t) and S2’(t) = a2(t)sin(2πft2 + θ2) + n(t), S1’(t) – S2’(t). It’s same as S1(t) – S2(t). So differential can avoid amplitude noise effect.
Phase Noise Phase noise equation is S’(t) = a(t)sin(2πft + θ +θnt), θnt is a phase noise. Phase noise are usually occurred in reflection. As below diagrams, in signal transmission, every node compare with (Zt) and (Zo) impedances.
1. Zt = Zo, no reflect. 2.
Zt > Zo, there is a reflection into the transmission line, noise adding to signal now. It’s dispersal reflection.
3. Zt < Zo,a portion is reflected back into the transmission line , the signal is lower than primitive. But noise and reflective effect are less than primitive. It’s disappear reflection.
In ideal, Zt = Zo , that’s mean no phase noise, there are no reflections. But that’s impossible, so we choice Zt < Zo to decrease phase noise effect. According differential communication model, we add a termination to decrease phase noise effect. But signal become weak in this change, so you must refer different situation to decide how to add a termination resister.
RXD
D-
In above diagram, we suggest add a termination that from 100Ω~150Ω(MOXA use 120Ω) as we know. But it will cause another questions. In below diagram, there are 150KΩ~200KΩ pull h igh/low resister inside IC. if you add a 120Ω termination resister, and signal damp out in the data line, D+ - D- = 5V * 120 / (150K + 150K + 120) = 0.002V. This result different D+ - D- > 0.2. We add a 1KΩ pull high/low resisters to fix this problem. In this time, final result will become D+ - D- = 5V * 120 / (1K + 1K + 120) = 0.28V.
5V
150K~200K Ohm
RXD
150K~200K Ohm
GND
5V
150K~200K Ohm
RXD
150K~200K Ohm
GND
Is this a good solution? In above diagram, we add impedance in this circuit, and it will cause a distributive current. This current can increase D+ and D- signals. In below diagram, pink is D+, blue is D-. We can make an assumption that impedance is small. D+
－
D- always under 0.2V, and no signals
in data line.
No pull high/low
1KΩ pull high/low
500Ω pull high/low
What situation cause above effects? One is pull high/low impedance too small, the other o ne is so many device have pull high/low resister in this network topology. All pull high/low resister are parallel connections in this situation. TI and Linear supply a fail safe method to fix above pull high/low problem. It is use a current sense to correct receiver structure. If there are not any current cross D+ and D- (this mean no signal) in receiver, it will accept high signal. If current cross the data line, we can refer the result that is D+
－
D- to
determine high/low potential. This method can fix above problems. If some of devices don’t use this IC that design in fail safe ba se, maybe cause above problems.
According above data, there are not any sol ution can fix all p roblems. You must understand system’s characters then according above solutions to fix your problems.
3. 2 wire RS-485 standard Differential Communication’s almost be used in RS-485. We may describe RS -485 structure as below diagram. There are six RS-485 devices connected in this diagram. Every RS-485 interface function diagram in n ext one. LTXD/LRXD pair UART LTXD/LRXD, D+/D- represent differential +/-. When TEN = ‘1’, it will enable transmission, LTXD transfer differential signals to D+/D-. REN = ’0’, it enable receiver, LRXD transfer signals that convert from D+/D- to UART. In RS-485 applications, TEN and REN always connected. V C C LRXD0 TEN0 L TX D 0
1 2 3 4
R E N R E N T T
V C C D D + GN D
V C C
8 7 6 5
8 7 6 5
V C C LRXD1 TEN1 L TX D 1
1 2 3 4
R E N R E N T T
V C C D D + GN D
L TX D 2
1 2 3 4
R E N R E N T T
V C C D D + GN D
8 7 6 5
8 7 6 5
R E N R E N T T
V D D G
C C + N D
R E N R E N T T
V D D G
C C + N D
R E N R E N T T
1 2 3 4
LRXD3 TE N 5
1 2 3 4
LRXD4 TE N 4
1 2 3 4
LRXD5 TE N 3
L TX D 3
L TX D 4
V C C
8 7 6 5
8 7 6 5
REN
D+
LRXD
D-
LTXD
TEN
C C + N D
V C C
V C C LRXD2 TEN2
V D D G
L TX D 5
In RS-485 applications, because D+/D- are connected in all devices and RS-485 can’t detect data collision. If there are over 2 devices send data to data line, it will cause a problem that is data crash . The network topology that used in RS-485, default setting is “ receiver mode”. It is changed when data transfer, and back to receiver mode a fter finish data transmit. There are kinds of transmission/receiver as follows.
SW Use SW to control Transmission/Receiver, enable transmission before data transfer. After data transfer, it will enable receiver. Because no hardware effort happened, we have a benefic that is easy to design. Disadvantage is SW will polling data until data transfer finish, so system has heavy loading. Enable time longer than data, so data collision happen frequency. This application can’t used in converter. (1. D+, 2. D-. 3. TEN, 4. LTXD, above no termination register, below has 120Ω register)
HW 1. We just only send low signal, then get below wave form. (1. D+, 2. D-. 3. TEN, 4. LTXD, above no termination register, below has 120Ω termination register)
There is a problem in this wave form. When status change from transmit to receive, D+/D- are in low/high status. After transmission enable, D+
－
D- less than -0.2V are happened in portion of data
transfer. Because it is receiver status, so you will accept a few low signals. Maybe you accept wrong data in receiver. (1. D+, 2. D-. 3. TEN, 4. LTXD, above no termination register, below has 120Ω register)
(1. D+, 2. D-. 3. TEN, 4. LTXD, above no termination register, below has 120Ω register)
1. HW enable, packet all data Because enable signal will packet all data, so spend less time to enable transmission and integrate signals. The defect is not easy to implement. Because data transfer from UART influence parameters that include baud rate, data bit, parity and stop bit, hardware must detect software setting then make sure these parameters. But it’s complex to detect and modify start bit. If there are any design that support ADDC inside the UART, it can provide a correct enable signal to fix this problem. But this application still can’t be used on converter. (1. D+, 2. D-. 3. TEN, 4. LTXD, above no terminator, below has 120Ω terminator)
4. Topology
Star B Z D
Z A
Z
C
Device A send a signal to C. we can make an assumption to ignore impedance. The input impedance that on device A /B are Z. When device A export a signal, Zt is Z/2, Zo is Z. B ut after signal cross the node D, Zt change to Z, Zo change to Z/2, this is reflecting status. Phase noise bigger than old. If we add a 1 20 ohm register (Z>>120) on C, device A send a signal to B , before signal cross node D, Zt <= 120, Zo = Z, it’s reverse reflection. But after the signal cross node D, Zt <= 120, Zo = Z, it’s reflection. Start topology is bad for phase noise .
Daisy Chain
A
B
C L
Above is Daisy chain structure. We make an assumption to ignore distance L in ideal, and no impedance on the line. Device A send a signal to device C, result the same as Star . There is a reflection occur after pass device B, but we can add a termination register on device C to fix this problem. Zt always < Zo, so it decrease phase noise effect in Star topology. Below diagram is the Star Topology and Star signal.
Because it’s hard to build Daisy chain, so there are many variations in RS-485. We suggest use Star to build a network, then connect all Star networks by single connection. In below diagram, we just add a termination register in left/right zone, it can decrease phase noise. H
A
I
B
C
D
E
F
G
J
5. 4 wire RS-485 and RS-422(Full duplex) Biasing an RS-485 In idle state, all nodes a re in listen mode at RS -485 network, there are not any active drivers on network. All drivers are tristated. In below diagram, Each RS-485 nodes have pull high/low impedance of 150K~ 200K ohm to make sure all drivers are tristated.
5V
150K~200K Ohm
RXD
150K~200K Ohm
GND
+5V
REN
Bias Resistor D+
LRXD
D-
LTXD
Bias Resistor
TEN
In proper idle voltage status, bias resistors must be applied to force the data lines to idle condition. Bias resistors are a pullup resistor on the D+ line ( typically to 5 voltages) and a pulldown (to ground) on the D-. In above diagram, we place bias resistors on a transceiver in a two wires configuration. If apply in an RS-485 four wires configuration, the bias resistors should be placed on the receiver line. The bi as resistors are dependent on termination and number of nodes in the system. The purpose is keep different voltage that under net work alw ays over 0.2V.
Example. 10 nodes without termination resistors T Master
R T
R
T
Slave
R Slave
T
R Slave
Each RS-485 node has 100K ohm impedance. 10 nodes in parallel give a load of 10K ohm. There are least 200mV between data line, so we need 20 μA bias current to flow through the load. To create this bias from a DC 5V supply, this network need 250K ohm resistance or less is require. Subtract 10K ohm that is already a part of the load, we are left with 240K ohm. Placing half of this value as a pull high to 5V, half as pull low to ground gives a maximum bias resistor 120K ohm for each of the two biasing resistors.
One node has 100K ohm 10 nodes in parallel impedance -> 10K ohm 200mV / 10K = 20 μA 5V / 20μA = 250K ohm -> total impedance of the load 250K – 10K = 240K ohm 240K ohm / 2 = 120K ohm -> biasing resistor
Example. 10 nodes with two 120 ohm termination resistors One node has 100K ohm 10 nodes in parallel impedance -> 10K ohm 10K parallel two 120 ohm = 59 ohm 200mV / 59 = 3.4mA 5V / 3.4mA = 1470 ohm -> total impedance of the load 1470 – 59 = 1411 ohm 1411 ohm / 2 = 705.5 ohm -> biasing resistor
6. 5. 5 wire RS-485 and RS-422(Full duplex)
4W RS-485 In below diagram, there aren’t any p roblems that what time to export data on master, but all transmissions are connected in Slave. If two S laves export data in the same time, it will cause data collision. Transmission enable is like 2 wires RS-485, and need ADDC, too. When master transfer data to slave, all slave device will accept data in the same time. So Receiver always enable in this type.
T Master
R
T
R Slave
T
R
T
Slave
R Slave
V C C
1 2 3 4
TE N LTXD
R E N R E N T T
V C C D D + G ND
8 7 6 5
10£[ 10£[
TXDTXD+
10£[ 10£[
R X D R X D +
V CC
R 24
V C C
10 K LRXD
1 2 3 4
R E N R E N T T
V C C D D + G ND
8 7 6 5
RS-422 In another exception, we assume this application just only use single master and slave on 4 wires RS-485, refer below diagram. It’s a pair in this type, so you can ignore collision problem when you enable transmission. So you can always enable Transmission.
Master
T R
T
R Slave
V C C V C C
1 2 3 4
LTXD
R E N R E N T T
V C C D D + G N D
8 7 6 5
10£[ 10£[
TXDTXD+
10£[ 10£[
R X D R X D +
V CC
R 24
V C C
10 K LRXD
1 2 3 4
R E N R E N T T
V C C D D + G N D
8 7 6 5
It’s different to determine RS-422 or 4 wires RS-485 by every corporation. Some determine 4 wires RS-485 is RS-422. Actually, the applications that are used in 4 wires RS-485 almost used on RS-422, too. But there is an exception, if the environment is abominable, 4 wires RS-485 TXD+/- will keep the status in floating mode, if there are not any data accepted. In this situation, it wi ll interfere with data transfer. We almost suggest customer modify influence in a critical environment. Because in this environment, even device shutdown or unconnected, device still accept wrong data possibly. Specifying compliance to RS-422 only establishes that the signal between the specified devices will be compatible. The RS-422 standard o nly defines the characteristic requirements for the balanced line drivers and receivers. RS-422 interfaces are typically used when the data rate o r distance criteria cannot be met with RS-232. The RS-422 standard allows for operation of up to 1 0 receivers from a single transmitter. The standard does not define operations of multiple tristated transmitters on a link. The RS-422 interfaces between the Data Terminal Equipment and Data Communication Equipment or in any point-to-point interconnection of signals between digital equipment. It employs the electrical characteristics of balanced-voltage digital interface circuits. The balanced voltage digital interface circuit will normally be utilized on data, timing, or control circuits where the data bound rate is up to 10 Mbit/s. While the balanced interface is intended for use at the higher data bound rate, it may ( in preference to the unbalanced interface circuit ) generally be required if any of the following conditions prevail: The interconnecting cable is too long for effective unbalanced operation.
The interconnecting cable is exposed to an extraneous noise source that may cause an unwanted voltage in excess of +1 vol t measured differentially between the signal conductor and circuit common at the load end of the cable with a 50 ohm resistor substituted for the generator. It is necessary to minimize interference with other si gnals. Inversion of signals may be required, i.e. plus to minus MARK may be obtained by inverting the cable pair. Applications of the balanced voltage digital interface circuit are shown in Figure 1.
1. Electrical Characteristics: The balanced voltage digital i nterface circuit consists of three parts: the generator (G), the balanced interconnecting cable, and the load. The lo ad is comprised of one or more receivers (R) and an optional cable termination resistance (RT). The balanced voltage interface circuit is shown in Fi gure 2.
2. Environmental Constraints: Balanced voltage digital interface conforming to this standard will perform satisfactorily at data bound rates up to 10 Mbit/s providing that the following operational constraints are satisfied: The common mode voltage at the receiver is less than 7 volts (peak). The common mode voltage is defined to be any uncompensated combination of generator-receiver ground potential difference, the generator offset voltage (Vos), and longitudinally coupled peak noise voltage measured between the received circuit ground and cable wi thin the generator ends of the cable short-circuited to ground.
