Most asked INterview Questions for Physical Design

PD Assignment [7 Questions] Submitted by: Nandan Roy A.S.

1.Why should we have extra margin for clock enable? 2.What are early clock latency and late clock latency? -Early Clock Latency: -Specifies additional delay (latency) in a clock network. -This delay represents the external delay from a virtual (ideal) clock through the shortest path. -The Classic Timing Analyzer uses the more conservative latency value. -For setup analysis, the Timing Analyzer Analyzer uses the early latency value for each destination register. -For hold analysis, the Classic Timing Analyzer uses the early latency value for each source register. -The Early Clock Latency timing assignment can be done to a clock signal in the design. -The Classic Timing Analyzer ignores early and late clock latency on a clock when analyzing paths between registers within the same clock domain.

-Late Clock Latency: -Specifies additional delay (latency) in a clock network. -This delay represents the external delay from a virtual (or ideal) clock through the longest path. -The Timing Analyzer uses the more conservative latency value. -For setup analysis, analysis , the Timing Analyzer uses the late clock latency value for each source register. -For hold analysis, the Timing Analyzer uses the late clock latency value for each destination register. -The Timing Analyzer Analyzer ignores early and late clock latency on a clock when analyzing paths between registers within the same clock domain.

3.Why load or slew fixing should be done? Violation is the max output load i.e; capacitance -Load Violation -Slew Violation Violation is the max transition of the signal -Delay is a function of both slew and load -So they have to be fixed in order to be having less delay of cells.

4.What are voltage domains? 5.What are power domains?

6.What is temperature inversion? -When CMOS devices are scaled down, voltage level and oxide thickness must also be reduced. The electrical barriers within the device begin to lose their insulation properties because of thermal injection and quantum mechanical tunneling, which results in higher leakage and reduced speed -Traditionally, cell delay increases with rising temperature. But in the 90-nm node, measurement has shown that cell delays decreases with rising temperature. This behavior is called temperature inversion. -Temperature inversion varies per timing arc. Each timing arc is dependent on input slope (input transition) and output load.

7.What are virtual clocks? -By definition, virtual clock is a clock which doesn't have any design object associated with it. -Virtual Clocks are generally used to constraint the IOs (Inputs & Outputs) of a block. -A virtual Clock is not required for the tool in top level. Example: -In a big design with two sub-blocks, block 'A' and block 'B'. Suppose there is a timing path going from a register x_reg (clocked by 'clk1') (in block A) to register y_reg (clocked by 'clk2') (in block B). -Since you are analyzing this design at the top-level, the tool can associate both the clocks with some design objects and hence there is no need for virtual clocks. -Virtual Clock is required mostly if there are two or more clocks and the path to be analyzed is a path between two blocks, with different clocks, some of which m ay not be present in this block. Example: -Now if you are doing analysis at block-level (say Block 'B'), and you have to tell the tool that timing path ending at y_reg register is launched by a clock "clk1". -The only way to do this is to create a virtual clock. -For creating clk2 you have some design object (port/pin) available, since it exist in block 'B ' itself. But block 'A' is out of the scope of the current environment, and you have to define "clk1" as virtual clock.