Modeling R-2R Segmented-Ladder DACs

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010

Modeling

31

Segmented-Ladder DACs David Marche and Yvon Savaria , Fellow, IEEE

Abstract—Although ladder ladderss are are common commonly ly used used as digital-todigital-to-analog analog convert converter er (DAC) (DAC) cores, cores, complete complete equivalen equivalentt circuits are still missing from the literature for most of the configurations figurations used in practice practice.. In this paper, paper, expressi expressions ons for the input and output impedances of ladders are derived for currentcurrent- and voltage-m voltage-mode ode operations operations.. In addition, addition, since many DACs DACs use segmentation to reach higher resolutions, the impedance expressions are also obtained for different segmentation schemes. Using these expressions, the existing current-mode model is extended to segmented architectures, and a new equivalent circuit is proposed for voltage-mode designs. This allows modeling the most common DAC designs. Simulation results produced with the proposed models are compared to measurements on two 14-bit DAC DAC prototypes. These results demonstrate how impedance variation with code can limit the static performances of high-resolution converters. Index Terms— DAC,

Fig. 1. Current-m Current-mode ode

DAC.

, model, impedance.

I. INTRODUCTION HE ladd ladder er is a comp compac actt resi resist stiive netw networ orkk whic whichh cangen can genera erate te binary binary weight weighted ed curren currentt or volta voltage ge level levelss and is mostly used in digital-to-analog converters (DAC) [1]. Based on a reduced set of identical components, they are well suited to layout optimization for reaching low mismatch levels critical in high-resolution flash converters. Furthermore, resistive networks are naturally suited to laser trimming matching enhancement, allowing even higher resolution products. References [2] and [3] are examples of such products that are commercially available. Even though such converters are widely available, little information can be found on the challenges faced when desig designi ning ng such such high high-re -reso solu luti tion on con converte verters. rs. Resis Resisto torr devi deviat atio ionn is the the mo most st obvi obviou ouss line linear arit ityy paparameter: The relation between mismatch level and maximum differ different ential ial nonlin nonlinear earity ity (DNL) (DNL) is well well known known and highli highlight ghtss the need for calibration or trimming solutions [4], [5]. For voltagemode ladders, an expression of the output voltage in terms of resistance ratio is derived in [6] along with test and trimming strategies. In [7], a similar analysis is conducted for the current-mode ladder, and other major sources of errors are listed: switches and wire resistance. Indeed, switching circuitry is critical for settling time, but switch resistance itself can have significant impact on linearity. An overview of explored switch sizing sizing andcom and compen pensat sation ion soluti solutions ons canbe can be found found in [8].The [8]. Theinp input ut and output impedance expressions for the current-mode DAC are derived in [9] and can be used to compute the impact of wire resistance on linearity for this configuration.

T

Manuscript received October 02, 2008; revised January 20, 2009. First published March 27, 2009; current version published January 20, 2010. This paper was recommended by Associate Editor M. Delgado-Restituto. The authors are with the Departmen Departmentt of Electrical Electrical Engineering Engineering,, École Polyte Polytechn chniqu iquee de Montr Montréal éal,, Montr Montréal éal,, QC H3T 1J4, 1J4, Canada Canada (e-mail (e-mail:: [email protected]). Digital Object Identifier 10.1109/TCSI.2009.2019396 10.1109/TCSI.2009.2019396

Fig. 2. Zurada and and Goodman’s Goodman’s current-mode current-mode

DAC equivalent circuit.

For hand analysis or fast simulation in larger systems, it is often desirable to use high-level models which are accurate simple equivalent circuits. This is particularly true for DACs since the number of input codes to be verified grows exponentially with the input word bit count, making exhaustive code scan simulation difficult for high-resolution designs. In these cases, if no high-level model is available, available, partial simulations are often used, and the designer’s knowledge and understanding of significant factors involved become critical. Although current and voltage analog output expressions are available, complete DAC models including input and output impedances are still limited to current-mode ladders with no segmentation [9]–[11]. This is a significant drawback since most recent networks use segmentation to meet the ever-increasing resolution demand. Furthermore, many converters are based on the volta voltagege-mod modee operat operation ion of the netwo network rk for which which no impedance expressions have been published yet. Thus, actual models have limited value for today’s DAC simulation and optimization. The objective of this paper is to present new models derived for for all the the mo most st comm common on DAC stru struct ctur ures es:: volta oltage ge-and and curr curren entt-mo mode de , with with or with withou outt segm segmen enta tati tion on.. In Section II, the existing current-mode model is extended to segmented designs. In Section III, an equivalent circuit is propose posedd for for volt voltag agee-mo mode de con convert verter er and and is also also vali validd for for segmented architectures. An analysis of the model limits and circuit implications follows in Section IV with some simulation results. Before concluding, a practical high-resolution

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32


Fig. 3. Current-mode DAC DAC segmentation. segmentation. (a) Addition of digital inputs, respectively. respectively.

stages. (b) Addition of stages.

and

subscripts denote the thermoencoded and binary-encoded

DAC design case is studied in Section VI: Simulation results based on the simplified models are compared with chip measurements to show the significant impact of code-dependent impedance on linearity. II. CURRENT-MODE A. A. All Bina Binary ry Curr Curren entt-Mo Mode de

s (No (No Segm Segmen enta tati tion on))

Fig. 1 shows a current-mode ladder with -bit resolu resolutio tion. n. The equiv equivale alent nt circui circuitt propose proposedd by Zurada Zurada and Goodman [10] is shown in Fig. 2. In this configuration, the inpu inputt imp imped edan ance ce is simp simply ly equa equall to to , and and mo most st of the the model’s complexity lies in the expression of the output resistanc tancee , whic whichh is code code depe depend nden entt

Fig. 4. Setup for output output impedance impedance analysis of of the current-mode current-mode segmentation A.

with

(1) This expression was derived by Erb and Wierzba, and complete derivation details can be found in [9]. Note that the output current source is proportional to the digital input (2) B. Current-Mode Segmentation

Fig. 3 shows two possible segmentation solutions commonly used used to exte extend nd the the ladd ladder er with with unar unaryy weig weight hted ed bits bits.. In these configurati configurations, ons, binary weighted weighted stages are controlled controlled bybina bybinary ry-e -enncode codedd bits bits , and and unar unaryy weig weight htedst edstag agesar esaree cont contro roll lled ed by ther thermo moen enco code dedd bits bits . Both Both opti option onss will will allow segmentation but lead to different areas and impedance of the network. 1) Segmentation A: Additi Additiona onall unary unary weight weighted ed stages stages are controlled by thermoencoded bits [cf. Fig. 3(a)]. This solution requires a larger area and results in a higher input impedance. 2) Segmenta Addit itio iona nall unar unaryy wei weigh ghte tedd sta stage gess Segmentation tion B: Add are contro controlle lledd by thermo thermoenc encode odedd bits bits [cf. [cf. Fig. Fig. 3(b)]. 3(b)]. This solution requires less area and results in a lower input impedance. In this case, the current drawn from the volt voltag agee refe refere renc ncee inpu inputt is high higher er.. Zurada’s model (cf. Fig. 2) is also valid for the segmented versio versions ns of the DAC, DAC, but but the input input impeda impedance nce and output output

Fig. Fig. 5. Binary Binary-bi -bitt contribu contribution tion to the test source source current current with type-A type-A segmensegmentation (current mode).

impeda impedance nce express expression ionss must must be adapte adapted. d. The deriv derived ed expressions for these cases are given in Sections II-C and D. C. Curr Curren entt-Mo Mode de

With ith Typeype-A A Segm Segmen enta tati tion on

When When segmen segmentat tation ion A is used used [Fig. [Fig. 3(a)], 3(a)], theinp the input ut impeda impedance nce can be expressed as a function of thermobit count (3) Fig. 4 shows the setup for output impedance analysis: A test test volt voltag agee sour source ce is conn connec ecte tedd at the the outp output ut,, and and the the inpu inputt vol volta tage ge refe refere renc ncee sourc sourcee is grou ground nded ed.. The The outp output ut impedance can be derived if the expression of the current sourced by the test voltage is obtained: . Fig. Fig. 5 shows shows the contri contribu butio tionn of one activ activee binary binary bit to the test source current. In this configuration, all thermoresistors are shorted, and the binary segment currents are not affected

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MARCHE AND SAVARIA: MODELING

SEGMENTED-LADDER DACs

33

Fig. 6. Unary bit contribution contribution to the test source current with type-A segmentation (current mode).

by the segmentation. In this case, the expression of binary-bit contributi contribution on to derived derived by Erb Erb and and Wierzba Wierzba [9] is still still valid valid

Fig. 7. Setup for output output impedance impedance analysis of the current-mode current-mode segmentation segmentation B.

with

(4) Fig. 6 shows a circuit that reflects the contribution of one active tive thermo thermobit bit to the test test source source curren current. t. Since Since all thermo thermoss except except one one are shorted shorted to ground, ground, the current current contrib contribution ution is simp simply ly and and inde indepe pend nden entt of othe otherr bits bits stat states es.. Note Note that that the binary most significant bit (MSB) can be either considered as a ther thermo mobi bitt or a bina binary ry bit bit , but but its its curr curren entt cont contri ri-bution must be counted only once. By superposition, the current contribution of all thermos and bina binary ry bits bits can can be adde addedd to get get the the expr expres essio sionn of the the tota totall curr curren entt flowing out of the test source

(5)

Fig. 8. Unary bit contribution to the test source current with type-B segmentation (current mode).

Fig. 7 shows shows the setup for output impedance impedance analysis in the case case of type-B type-B segmen segmentat tation ion.. The test test source source curren currentt in this this conconfiguration must be derived to obtain the output impedance expression. Fig. 5 shows the contribution of one active binary bit, and the binary segment contribution is given by (5). Fig. Fig. 8 shows shows the contri contribu butio tionn of one activ activee thermo thermobit bit . Since all thermos are shorted to ground, their current contribution is simply . By superposition, the current contribution of all thermos and bina binary ry bits bits can can be adde addedd to get get the the expr expres essio sionn of the the tota totall curre current nt flowing out of the test source

The The corr corres espo pond ndin ingg outp output ut impe impeda danc ncee is give givenn by (6), shown at the bottom of the page. Note that these expression sionss are are valid alid for for both both segm segmen ente tedd and and unse unsegm gmen ente tedd architectures : Setting into (6) gives back (1). D. D. Curr Curren ent-M t-Mod odee

With ith Typeype-B B Segm Segmen enta tati tion on

Segm Segmen enta tati tion on B (Sect (Sectio ionn III-B III-B)) offe offers rs half half the the inpu inputt impedance of segmentation A (7)

(8) The corresponding output impedance is given by (9), shown at the bottom of the next page. This expression is also valid for unsegm unsegment ented ed archit architect ecture uress since since settin settingg gives gives back back (1).

(6)


34


Fig. 9. Voltage-mode

DAC.

Fig.10. Voltage-mod oltage-modee DAC DAC segmentat segmentation.(a) ion.(a) Additionof Additionof stages.(b)Addition of stages. and subscripts denote the thermoencoded and binary-encoded digital inputs, r espectively. espectively.

Fig. 11. Setup for the input input impedance analysis analysis of the voltage-mode voltage-mode (no segmentation). segmentation).

III. VOLTAGE-MODE Voltage-mode operation is another common use of ladd ladder ers. s. Fig. Fig. 9 sho shows a volta oltage ge-m -mod odee ladd ladder er with with reso resolu lu-tion . In this this case, case, input input impedanc impedancee becomes becomes code code depende dependent, nt, and output impedance is constant. A. Voltage-Mode Segmentation

As for the current-mode operation, there are two commonly used segmentation options to extend the resistor binary ladder with unary weighted bits. Fig. 10 shows these two solutions. Binary weighted stages are controlled by binary-encoded bits , and unary weighted stages are controlled by thermoencoded bits . B. B. All Bina Binary ry Volta oltage ge-M -Mod odee

Fig. 12. Bit contribution contribution to the test current (voltage mode; no segmentation). segmentation).

s (No (No Segm Segmen enta tatio tion) n)

Output impedance, when no segmentation is used, is not affected by the resolution of the converter (10) Fig. 11 shows the setup for the input impedance analysis: A test test volta oltage ge sour source ce is conn connec ecte tedd atthe inpu input, t, and and the the outp output ut

is left open. The input impedance is derived by finding the expression expression of the current current sourced sourced by the test voltage. voltage. Fig. 12 shows the current contribution drawn from each bit when one bit is active. Superposition theorem can then be used to add these current contributions and compute the total test source current.

(9)




With ith idea ideall resi resist stor ors, s, it is easy easy to see see tha that ever ever,, the expre expressio ssionn for is not so obviou obviouss

35

. How How-

(11) Thus, (12) Fig. 13. Setup for the input input impedance analysis analysis of the voltage-mode voltage-mode with segmentation A.

(13)

(14) Moreover Moreover,, the the current current contributi contribution on of bit is (15) The expressions of all other branch currents caused by the acti active ve bit bit are are

Fig. 14. Binary-bi Binary-bitt contribution contribution to the test current with type-A segmentation (voltage mode).

With the appropriate change of variable, (16) and (17) can be inserted into (18) to get the total test source current expression (13). Thus, the input impedance of the unsegmented voltagemode ladder is (14). C. Volta oltage ge-M -Mod odee

With ith Typeype-A A Segm Segmen enta tati tion on

When When segm segmen enta tati tion on A is used used [Fig [Fig.. 10(a 10(a)] )],, the the outp output ut impedance can be expressed as a function of thermoencoded bit count (19) (16)

(17) By superposition, the total current drawn from the test source can be expressed as

Fig. 13 shows the setup for the input impedance analysis: A test test volt voltag agee sour source ce is conn connec ecte tedd at the the inpu input, t, and and the the outp output ut is left open. The input impedance can be derived if the expression of the current sourced by the test voltage is obtained: . Fig. Fig. 14 shows shows the the cont contri ribu buti tion on of a bina binary ry bit bit to the the test test sour source ce current. Fig. 15 shows the equivalent simplified ladder used for binary-bit contribution analysis. Thermoresistors have been grouped together in a single equivalent resistor (20) With ith ide ideal resi resist stor ors, s, it is easy easy to see see tha that . However ever,, the the expr expres essi sion on for for is not not so so obv obvio ious us,, and and it can can be be shown to be

(18)

(21)


36


Fig. 16. Unary part of of the segmented segmented DAC. DAC. Fig. 15. Simplified ladder ladder for the analysis of binary-bit test current (voltage mode).

contribution to the

Moreover Moreover,, the the curren currentt contrib contribution ution of bit bit is

Thus,

(29) Other thermobran thermobranch ch current currentss caused caused by by a unary unary bit are (22)

In addition addition,, the current current contrib contribution ution of binary binary bit is

(30) (23)

This This is the the expr expres essio sionn of the the test test sour source ce curr curren entt when when all all inpu inputt bits are set to zero except one of the binary bits. The general solution valid for any number of active binary bit requires the expression of all branch currents caused by an active binary bit. Solving for the network of Fig. 15, we find that

The intera interacti ction on betwee betweenn unary unary and binary binary segmen segments ts must also also be taken into account. Currents in the binary ladder due to the unar unaryy bit bit are are (31) and current currentss in the the unary unary ladder ladder due due to the the binary binary bit bit are (32) By superpositio superposition, n, the total test source current current

is

(24)

(33) (25) Equations Equations (23)–(25) are the current contribution contributionss of the binary weighted section only. To analyze thermobit contributions, the ladder can be simplified as shown in Fig. 16, where the binary nary part part is repl replac aced ed by an equi quivale alent resi resist stan ancce: . In this case,

With the appropriate change of variables, (23), (24), (25), (29), (30), (31), and (32) can be inserted into (33) to get the test source current expression (35) and the input impedance expression (36), shown at the bottom of the page. Note that this expression is valid for both segmented and unsegmented architect tectur ures es:: Sett Settin ingg give givess back back (14) (14).. D. D. Volta oltage ge-M -Mod odee

(26)

With ith Typeype-B B Segm Segmen enta tati tion on

(27)

When When segm segmen enta tati tion on B is used used [Fig [Fig.. 10(b 10(b)], )], the the outp output ut impedance can be expressed as a function of thermoencoded bit count

(28)

(34)




37

Fig. 17 shows shows the setup for the input impedance impedance analysis. analysis. The input impedance can be derived if the expression of the current , shown at the bottom of the page, sourced by the test voltage is obtained: . Fig. Fig. 15 shows shows the equiv equivale alent nt simplifie simplifiedd ladder ladder used used for binary-bit binary-bit contribut contribution ion analysis. analysis. Thermoresist Thermoresistors ors have have been grouped together in a single equivalent resistor

Equations (40)–(42) are the current contributions of the binary weighted section only. To To analyze thermobit contributions, contributions, the ladder can be simplified as shown in Fig. 16, where the binary nary part part is repl replaaced ced by an equi equivvalent lent resi resist stan ance ce:: . In this case

(37)

(44)

. It can can

(45)

With ith ide ideal resi resist stor ors, s, it is easy easy to see see that that also also be shown shown that that the the expr expres essio sionn for for is

(43)

In additio addition, n, the the current current contributi contribution on of of bit bit

is (46)

(38) Other thermobranc thermobranchh currents currents caused caused by a unary unary bit bit are

Thus,

(47) (39)

The curren currents ts in the the binary binary ladder ladder due to the unary bit are

Moreover Moreover,, the current current contribu contribution tion of binary bit is (48) (40) This This is the expres expressio sionn of the test test source source curren currentt when when all input input bits are set to zero except one of the binary bits. The general solution valid for any number of active binary bit requires the expression of all branch currents caused by an active binary bit. Solving for the network of Fig. 15, we find that

(41)

(42)

and the the currents currents in in the unary ladder ladder due to the binary binary bit are given by (49)–(51), shown at the bottom of the next page. By superpositio superposition, n, the total test source current current is

(52) With the approp appropria riate te change change of varia variable bles, s, (40)–( (40)–(42) 42) and (46)–(49) can be inserted into (52) to get the test source current expression (50) and the input impedance expression (51). Note

(35)

(36)


38


Fig. 17. Setup for the input input impedance analysis analysis of the voltage-mode voltage-mode with segmentation B.

Fig. 18. Equivalent Equivalent circuit for voltage-mode voltage-mode

DAC.

that this expression is valid for both segmented and unsegment mented ed arch archit itec ectu ture res: s: Setti Setting ng give givess back back (14) (14).. E. Voltage-Mode Equivalent Equivalent Circuit Circuit

The proposed equivalent circuit for voltage-mode operation is shown in Fig. 18. This same model can be used for both segmented and unsegmented ladders, given that the input and output impedance expressions are adapted to the ladder type. These expressions were derived in the previous sections according to the segmentation type [cf. (10), (19), (34), (14), (36), and (51)]. If voltage output deviations due to resistance mismatch must be simu simula late ted, d, the the idea ideall volt voltag agee sourc sourcee can can be repl replac aced ed by the output expression in terms of resistor ratios derived in [6]. [6]. This This would would allow allow a Monte Monte Carlo Carlo simulat simulation ion includ including ing errors errors coming from ladder mismatch.

IV. IV. VOLTAGE-MODE MODEL CONSIDERATION The following is a list of considerations related to the use of the the simp simpli lifie fiedd volta oltage ge-m -mod odee DAC mo mode dell sho shown in Fig. 18. 1) Input Node: Although grounded in our analysis, the negative input node of the equivalent circuit can be tied to another potential. This can be used on purpose to set the output voltage range lower limit. DACs 2) Output Output Impedance: Impedance: Since voltage-mode have a constant output impedance, the stabilization of any output amplifier is simplified. The stable nature of the output impedance also allows loading the DAC without linearity loss. In this case, the load resistor can be used to adjust the converter full-scale output (i.e., gain). -mode DACs have a 3) Input Input Impeda Impedance nce:: Voltage-mo code-dependent input impedance. The input impedance of the DAC sets the input voltage reference loading. To validate our mode mo del, l, a segm segmen ente tedd volt voltag agee-mo mode de DAC was was netl netlist isted ed and simulated with the Hspice simulator to measure the input reference current for all possible digital input codes. The test netlis netlistt is a 16-bit 16-bit segmen segmented ted volta voltagege-mod modee ladder ladder based based on 50-k resistors resistors and using segment segmentation ation A with three three therthermoenco moencoded ded bits. bits. The same same circui circuitt simulat simulation ion was was perfor performed med analytically using our proposed model: (36) was used with , , an a nd k . F ig ig. 19 1 9 sh s hows t he he r ef eference cu c urrent as computed with our model and as simulated with Hspice. The analytical solution is very accurate with a maximum error of 30 ppm, arising from the single-pole double-throw (SPDT) switch value values, s, which which are not consid considere eredd in our mod model. el. Consid Consideri ering ng the complexity of the derived equations, the observed accuracy of the results constitutes a useful validation of our models. Appropriate reference circuit design or selection must take into account the DAC input current curve in order to get accurate converters. was found found in practi practice ce that, that, in high-r high-reso esolut lution ion 4) Reference: It was designs, the varying input impedance puts some constraints on the reference distribution network. Indeed, since the reference curren currentt varie variess with with the digita digitall input input code, code, the volta voltage ge drop drop across across the reference distribution path modulates the reference voltage level seen by the converter. For high-resolution converter, this

(49)

(50)

(51)




39

Fig. 19. 16-bit segmented segmented voltage-mode voltage-mode reference current computation (type-A segmentation, , , V, and k ). (a) Simulated solution with Hspice and a complete netlist and (b) analytical solution with the proposed model. Results differ by less than 30 ppm. The difference is mainly due to switch value, which is not taken into account in the simplified model.

should either be minimized or well compensated. Note that, in the voltage-mode configuration, the switches are placed at the DAC inpu inputs ts and and sepa separa rate tedd from from the the outp output ut by the the reresistors, thus providing some shielding of the output from the switching glitches. Appendix II lists the bit values creating situations of maximum/minimum input impedances and current values. Fig. 20. Reference bus impedance impedance analysis with the simplified simplified voltage-mode voltage-mode model.

phenomenon can significantly affect linearity. Using the equivalent circuit in Fig. 18, it is possible to rapidly evaluate the impact of reference connection impedances on the output of the DAC. DAC. Fig. 20 shows the DAC DAC equivalent circuit, including parasit asitic ic impe impeda danc nces es and and mode mo deli ling ng typi typica call posi positi tive ve and and negat negativ ivee refere reference nce distrib distributi ution on buses buses.. Since Since the curren currentt is code code depend dependent ent,, the appare apparent nt refere reference nce voltag voltagee as can be seen by the DAC is also code dependent. This creates linearity errors. Fig. 21 shows the simulated impact of reference connections on integral nonlinearity (INL) and DNL, as obtained with the the simu simula lati tion on of a deta detail iled ed netl netlist ist simu simula lati tion on,, as well well as with with the the simple equivalent model analysis result. Both results are very similar. similar. They show that that only only 1- parasitic parasitic resistanc resistancee between between the reference source and the DAC would be responsible for almost 2 LSB INL and 1.5 LSB DNL errors in the modeled 16-bit DAC. DAC. Note that the parasitic parasitic resistance on reference reference inputs is also responsible for gain errors, not plotted here, but which can also be obtained with the proposed model. model, el, the simplifie simplifiedd impeda impedance nce expres expres-5) Resistors: In our mod sions and output voltage expression are based on ideal equal resistors. In reality, however, resistors are subject to variations inherent to fluctuations of any fabrication processes, and their value value canbe can be mod modula ulated ted by temper temperatu ature re and volta voltage ge state. state. Taking aking all these these effec effects ts into into consid considera eratio tionn still still requir requires es simula simulatio tions ns with with a complete detailed netlist of the DAC. The swit switch chees of volta oltagge-mo e-mode de DACsare Csare 6) Switches: The SPDT SPDT devic devices es connec connectin tingg input input branch branches es to either either the positi positive ve or negative reference potential. This wide operating voltage range sets constraints on the switch design. Our proposed model does not not take take into into acco accoun untt swit switch ch para parasi siti ticc resi resista stanc ncee whic whichh

V. CURRENT-MODE MODEL CONSIDERATION As for the voltage mode, the current-mode model (cf. Fig. 2) can be very useful for fast simulation. Although it is a highlevel model that depicts accurately the DAC behavior in many situations, it also shows some limitations due to the fact that it ignores significant circuit details. Note that the expression of output current in terms of resistance ratio derived in [7] can be used in place of the ideal current source to consider resistance mismatches. The following are some considerations to be aware of when using the current-mode model shown in Fig. 2. The curr curren entt-mo mode de ladd ladder er feat featur ures es 1) Output Nodes: Nodes: The two current outputs, between which the input current is divided in a proportion dictated by the digital input code: It is a current steering circuit. However, Zurada’s current-mode equivalent circuit only models one output and assumes the other is grounded. grounded. Although grounding grounding one of the outputs outputs is probably probably the most common situation, the converter converter is really a two-output block, and some simulations require the DAC to be considered as such. In these cases, the model is not valid. For example, the model cannot be used to analyze accurately a current-mode DAC with the complementary output tied to the ground through a resistor nor can it take into consideration any varying voltage found on that same output. 2) Input Impedanc Impedance: e: Contrary to voltage mode, the input impe impeda dannceof curr curreent-m nt-mod odee DACsis not not mo moddifiedby ifiedby the the digital input code. In this situation, the current drawn from the reference input is constant, and the input voltage drop through the input connection parasitic resistances will only impact the gain error but not linearity. This relaxes the constraint on reference distribution path design and also allows gain adjustment with the addition of an input resistor, as shown in Fig. 22. When the DAC output is not grounded or virtually grounded with an


40


Fig. 21. Voltage-mode reference connection impedance impact on INL and DNL (type-A segmentation, segmentation, ). (a) Detailed netlist simulation results. (b) Simplified model analytical results.

,

,

V,

, and

As for voltage mode, resistors were were all consid considere eredd ideal, ideal, and switche switchess are ignore ignoredd to obtain simple impedance expressions. Adequate switch sizing and compensation options needed to make this valid can be found f ound in [8] and [12]–[15]. 4) Resistors Resistors and Switches: Switches:

VI. HIGH-RESOLUTION

DAC CASE STUDY

A. Chip Implementa Implementation tion and First First Results Fig. 22. Gain adjustme adjustment nt resistor resistor addition addition

Fig. 23. Fourteen-bit current-mode

in current-mode

DAC.

DAC.

Fig. Fig. 23 shows shows a 14-b 14-bit it curr curren entt-mo mode de DAC chip chip fabfabricated ricated in 0.25- m TSMC CMOS process and previously previously described scribedin in [5]. [5]. The three three MSBs MSBs are thermo thermoenc encode oded, d, andseg and segmen men-tation is of type A [cf. Fig. 3(a)]. The remaining 11 bits control the binary binary weight weighted ed curren currents ts genera generated ted with with stages stages.. The unit resistance resistance value value is 50 k , and all resistors resistors can be individindividually and precisely adjusted by laser trimming: This trimming is done with laser-diffused resistors [16], allowing the cancellation of any significant mismatches found after fabrication. This allows trimming away significant DNLs, which, in turn, is expected to result in a very low INL performance. Fig. 24(a) shows the typical linearity curves as measured on the first prototype version of the chip and before any trimming operation. Fig. 24(b) shows the corresponding linearity curves obtain obtained ed if the most most signific significant antmism mismatc atches hes affec affectin tingg the resist resistor or ladder are removed: The INL is not improved by mismatch cancellation.

op amp, the controlled controlled current current source present at the input side Analysis and Design Design Correctio Correction n of the model allows taking into consideration the output voltage B. Analysis effect on the input current. Note again that the model assumes The analysis of the prototype showed that parasitic resistors a grounded complementary output and does not have the ability of output output buses buses combin combined ed with with the code-d code-depe epende ndent nt output output to adjust the input current with the output voltage found on a impedance impedance were responsible for the limited INL capability capability of complementary output. the chip. Indeed, these buses, made very long to collect all output ut curr curren ents ts comi coming ng out out of all all bran branch ches es,, had had 3) Output Output Impedance: Impedance: Contrary to voltage mode, the output DAC outp impe impeda danc ncee of curre current nt-m -mod odee DACs is code code depe depend nden ent. t. a parasitic parasitic resistance resistance reaching reaching almost almost 8 from one end end to the This impacts the stabilization of the operational amplifier gen- other. The effect of these buses can be obtained with a complete erally found at the output of such a converter [10] and also puts simulation when including parasitic elements, but extracting constraints on the output path design as any resistance present all parasitic resistors for simulations is usually not possible on that that path will degrade degrade linearity. linearity. An observation observation of this this degradegra- because of the excessive number of nodes added to the original dation is reported in [7], where the authors have noted that the netlist. A more practical solution (which also requires some output wire resistance is a source of INL error. Controlling this human expertise) is to include only the sensitive parasitic elefactor becomes important when target resolution increases, and ments: in this this case, the output output bus bus resistor resistors. s. Fig. 25(a) shows shows the an illu illust stra rati tion on of this this will will be give givenn in Sect Sectio ionn VI with with actu actual al chip chip linearity curves of the DAC, as simulated using the equivalent measurements. model proposed, with a reference bus resistors added, as shown Authorized licensed use limited to: Amal Jyothi College of Engineering. Engineering. Downloaded on July 07,2010 at 12:36:02 UTC from IEEE Xplore. Restrictions apply.



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Fig. 24. Linearity curves as measured on the first DAC DAC prototype, (a) before any trimming and (b) after most significant mismatch mismatch correction.

Fig. 25. Linearity curves of the (a) first prototype and (b) improved improved DAC circuit as obtained obtained with a fast simulation using the simplified DAC DAC model.

Fig. 26. Linearity curves as measured on on the improved DAC DAC prototype, prototype, (a) before any trimming and (b) after trimming.

in Fig. 20. Note that this simulation gives a good approximation of the chip result (cf. Fig. 24), although the bus resistors are probably a bad model of the bus layout solution and neither switch resistance nor resistor mismatch is considered. The The layo layout ut of this this chip chip was was late laterr mo modi difie fiedd to redu reduce ce the the outp output ut path resistan resistance ce down down to approxi approximatel matelyy 1 . Again, Again, using using the equivalent model, the expected typical linearity curves can be computed and are shown in Fig. 25(b). Fig. 26 shows the linearity curves measured on the improved prototype chip [5]. Although the output impedance effect can still be observed in trimmed curves, nonlinearities are now dominated by mismatch errors which can be trimmed out to reduce the INL down to 0.6 LSB.

VII. CONCLUSION Express Expression ionss of output output and input input impeda impedance ncess have have been been derived to extend Zurada and Goodman’s current-mode equivalent equivalent circuit to segmented architectures. A new model has also been proposed for the voltage-mode designs. Expressions have again been derived to fit segmented architectures as well. Simula Simulatio tionn and chip chip measur measureme ements nts have have shown shown that that these these models can offer an accurate representation for fast simulation or higher level analysis. This is certainly a benefit for accurate system simulation in the trend for higher integration. These models were used to demonstrate the importance of considering the network impedance when designing high-res-


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Tables I–IV list some of these codes 1 for the different configurations modeled. Using the provided code values, limits to models and equations can be generated generated with a symbolic symbolic computing computing software. software. For example, example, the the maximum maximum input current current of an an -bit voltage voltage-mode -mode binary ladder is

TABLE I BINARY VOLTAGE-MODE SPECIAL CODES

TABLE II SEGMENTED (A OR B) VOLTAGE-MODE SPECIAL CODES

(55) Although it is interesting to note that the expression is closed for any any value value of , the formula formula is not simple simple and becomes becomes even even more complex for segmented cases. For this reason, we have only provided the list of special codes. With these tables and the equations that compose the model, the interested reader can generate any needed result.

TABLE III BINARY CURRENT-MODE SPECIAL CODES

REFERENCES TABLE IV SEGMENTED (A OR B) CURRENT-MODE SPECIAL CODES

olution DACs. The measurements of a trimmable 14-bit DAC chip were compared to the model simulation results to show how the code-dependent output impedance prevents reaching the targeted resolution. APPENDIX I USEFUL PROPERTIES Several Several expressions expressions were simplified using the following following geometric series property: (53) In particular, (11), (21), and (38) were obtained with and . Anothe Anotherr useful useful versio versionn of this this proper property ty is obtain obtained ed when and (54)

APPENDIX II SPECIAL CASES Seve Severa rall inpu inputt code codess are are of spec specia iall inte intere rest st sinc sincee they they create configurations of extreme impedance and/or current.

[1] “Analog–Digital Conversion Handbook,” Eng. Staff , Analog Devices Inc., Prentice-Hall, Englewood Cliffs, NJ, 1986. [2] “LTC “LTC1591 1591—14 —14-Bit -Bit Parallel arallel Low Glitch Glitch Multiplyi Multiplying ng DAC DAC With With 4-Quadrant Resis tors,” tors,” Linear Technol. Corporation, Milpitas, CA, 1998. [Online]. Available: Available: http://www.linear.com [3] “AD5554 Analog De“AD5554 Precisi Precision on QUAD QUAD 14-Bit 14-Bit D/A Converte Converterr,” Analog vices Inc., Norwood, MA, 2004. [Online]. Available: http://www. analog.com [4] D. S. Karadimas, D. Mavridis, and K. A. Efstathiou, “A digitally calibrated ladder ladder architectu architecture re for high performance performance digital-to-analog converters,” converters,” in Proc. ISCAS, 2006, pp. 4779–4782. 4779–4782. [5] D. Marche, Y. Savaria, Savaria, and Y. Gagnon, “Laser fine-tuneable fine-tuneable deep submicron CMOS 14 bit DAC,” IEEE Trans. Circuits Syst. I, Reg. Papers , vol. 55, no. 8, pp. 2157–2165, Sep. 2008. [6] M. Kennedy Kennedy,, “On the robustnes robustnesss of ladder DACs,” DACs,” IEEE Trans. Trans. Circuit Circuitss Syst.I, Fundam.Theory Fundam.Theory Appl. Appl.,vol.47,no.2,pp.109–116,Feb. 2000. [7] L. Wang, Y. Fukatsu, and K. Watanabe, “Characterization of CMOS ladder digital-to-analog converters,” converters,” IEEE Trans. Instrum. Meas., vol. 50, no. 6, pp. 1781–1786, Dec. 2001. [8] D. Marche, Marche, Y. Savaria, Savaria, and Y. Gagnon, Gagnon, “Compensated “Compensated inverted inverted ladder ladder and compensa compensation tion technique technique therefor therefor,” ,” U.S. Patent Patent Pending 11/411,110, 11/411,110, May 19, 2006. [9] E. Erb and G. Wierzba, “Expression for the output resistance of a switched ladder network,” IEEE Trans. Circuits Syst. , vol. CAS-30, no. 3, pp. 167–169, Mar. 1983. [10] J. Zurada and K. Goodman, “Equivalent circuit of multiplying DAC using ladder networks,” networks,” Electron. Lett., vol. 16, no. 24, pp. 925–927, Nov. 1980. [11] V. V. B. Rao and K. S. Rao, “Equivalent circuit for a multiplying D/A converter,” IEEE Trans. Circuits Syst. , vol. CAS-32, no. 11, pp. 1199–1200, 1199–1200, Nov. 1985. [12] D. Marche and Y. Savaria, “An improved switch compensation technique for inverted ladder DACs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 6, pp. 1115–1124, Jun. 2009. [13] J. B. Cecil, “Digital to analog conversion circuit including compensation FET’s,” U.S. Patent 4 267 550, May 12, 1981. [14] P. P. Morlon, “Digital to analog converters,” International Patent WO 90/16114, Dec. 27, 1990. [15] H. Asazawa, “D/A converter for minimizing nonlinear error,” U.S. Patent 5 119 095, Jun. 2, 1992. [16] M. Meunier, Y. Gagnon, Gagnon, Y. Savaria, A. Lacourse, and M. M. Cadotte, “A novel laser trimming technique for microelectronics,” Appl. Surf. Sci., vol. 186, no. 1–4, pp. 52–56, Jan. 2002. 1Separation between thermometer and binary bits is shown, but all bits are given binary encoded.



Canada.


David Marche received the B.Ing., M.Sc.A., and Ph.D. degrees in electrical electrical engineering engineering from the École Polytechniqu Polytechniquee de Montréal, Montréal, Montréal Montréal,, QC, Canada, in 1993, 1996, and 2009, respectively. respectively. As a Software Engineer and an Analog Designer with with OPMAXX OPMAXX,, Portla Portland,OR, nd,OR, andlaterwith LTRIM TRIM Techno Technologi logies, es, Laval, Laval, QC, Canada, Canada, he has participat participated ed in the design of several analog and mixed-signal integrated circuits and in the development development of optimization and test software. Since 2007, he has been with the École Polytechnique de Montréal, Montréal, QC,

(S’77–M’86–SM’97–F’08) (S’77–M’86–SM’97–F’08) received the B.Ing. and M.Sc.A. degrees in electrical engineering from the École Polytechnique de Montréal, Montréal, QC, Canada, in 1980 and 1982, respectively, tively, and the Ph.D. degree in electrical engineering from McGill University, Montreal, QC, Canada, in 1985. Since 1985, he has been with the École Polytechnique de Montréal, where he is currently a Professor and the Chairman of the Department of Electrical Engineering. He has been working as a Consultant or was sponsored for carrying out research by CNRC, Design Workshop, Dolphin, Yvon Savaria

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DREO, Genesis, Gennum, Hyperchip, LTRIM, Miranda, MiroTech, Nortel, Octasic, PMC-Sierra, Technocap, Tundra, and VXP. He has carried out work in several areas related to microelectronic circuits and microsystems, such as testing, verification, validation, clocking methods, defect and fault tolerance, high-speed interconnects and circuit design techniques, computer-aided design (CAD) methods, methods, reconfigura reconfigurable ble computin computingg and applicatio applications ns of microelecmicroelectronics tronics to telecomm telecommunica unications tions,, image image processin processing, g, video processing processing,, radar signal processing, and digital signal processing acceleration. He has authored or coauthored 80 journal papers and 322 conference papers. He holds 15 patents. He was the thesis advisor of 122 graduate students who completed their studies. Dr. Savaria is a member of the Regroupement Stratégique Stratégique en Microélectronique du Québec of the Ordre des Ingénieurs du Québec. He is the chairman of the Board of CMC Microsystems. He was the program cochairman of the 1992 edition and the chairman of the 1993 edition of the IEEE Workshop on Defect and Fault Tolerance Tolerance in VLSI Systems. He was the program cochairman of Application-Specific Systems, Architecture and Processors (ASAP) 2006 and the general cochairman of ASAP 2007. He was awarded with a Canada Research Chair on the design and architectures of advanced microelectronic systems in 2001. He wasalso the recipient of a Synergy Award of the Natural Sciences and Engineering Research Council of Canada in 2006.


Modeling R-2R Segmented-Ladder DACs

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