ejercicios unidad #5 michael parkinFull description
Descripción completa
Descripción: ejercicios unidad #5 michael parkin
tutorialDescripción completa
Full description
Consumer Electronics Servicing NCII CBC
Investigación sobre Micro mouseDescripción completa
Descripción completa
microeconomiaFull description
MICROELECTRONICS MICROELE CTRONICS CIRCUITS (10EC63) MODEL QUESTIONS 1. MOS Field-Effect Transistors (MOSFETs) – Unit Unit 1 1. Explain with the neat layered diagram, construction and working of NMOS transistor.
2. Explain the derivation of i D – v vDS characteristic of the NMOS transistor with a neat diagram. 3. Explain the operation of biasing in MOSFET using a constant – constant – current current source. 4. Draw the small signal equivalent model of Source Follower amplifier. Using this model obtain the expressions for A v and r out out. 5. Explain with the neat layered diagram, working of NMOS transistor when – when – (a) operation with no gate voltage. (b) creating a channel for current flow. (c) applying a small
.
vDS
(d) operation as vDS is increased. 6. Draw the small signal equivalent model of Common gate amplifier. Using this model
obtain an expression for A v and r out out. 7. Explain the operation of biasing in MOS MOS amplifier circuits by fixing VG and connecting a Resistance in the Source. 8. Write short notes on: (i) Complementary MOS and (ii) P-Channel MOS. 9. Explain the role of Substrate with respect to Body effect, Temperature effect and Break Down & input protection. 10. Derive the finite output resistance of an N-channel MOSFET in saturation region. 11. Write short note on: i) Single stage MOS amplifier. ii) Common – Common – Source Source amplifier. iii) Common – Common – Drain Drain amplifier. iv) Common – Common – Gate Gate amplifier. 12. Explain the biasing in MOS amplifier circuits by – by – (i) (i) fixing VGS, (ii) connecting a resistance to the source (R s), (iii) Drain to Gate Feedback resistor (R G), (iv) a constant current source.
2. Single-Stage Integrated-Circuit Amplifiers – Unit 2 1. Compare BJT and MOSFET technologies. Explain in terms of characteristics.
2. Describe the IC Design Philosophy. 3. Explain the concept of MOSFET scaling with a neat diagram. 4. Distinguish between Full scaling and Partial scaling in terms of device dimensions. 5. Define MOSFET Scaling. Explain and derive the small geometry effects in terms of Constant field scaling (Full scaling) and Constant Voltage Scaling (Parti al scaling) with a neat diagram. 6. List and explain the short channel effects of MOSFETs in detail. 7. Explain the operation of N-channel current mirror circuit and hence derive a relationship between IO and IREF. 8. What is meant by current steering in an IC biasing of MOSFET? Explain the operation of MOS Current Steering circuits with a neat diagram. 9. Explain the operation of BJT current mirror circuit and hence derive a relationship between IO & IREF. 10. With a suitable mathematical analysis, explain Millers theorem in detail with neat diagram. 11. Explain the dynamic operation of CMOS implementat ion of the Common Source amplifier with a neat diagram.
3. Single-Stage Integrated-Circuit Amplifiers – Unit 3
1. Explain the CS amplifier with a Source Resistance (R s) and its frequency response. 2. Derive the Voltage gain (A vo) and also explain the frequency response of the Source Follower. 3. List all the Current Mirror circuits with improved performance and Explain any in two in brief. 4. Write short notes on: MOS cascade, BJT Cascode, Cascode current source, Double cascoding source, Folded Cascode, BiCMOS Cascode.
5. Draw the small signal equivalent model of Common gate (Common Base) amplifier with the active loads. Using this model obtain an expression for A v and r out. 6. Derive the high frequency response of the CS amplifier. 7. Explain Darlington configuration briefly with a neat diagram. 8. List out all the useful transistor pairings. Explain any two of them.
4. Feedback – Unit 5
1. Explain the negative feedback effects with some properties in detail. 2. Explain the four feedback topologies with neat diagram. (With table also). 3. Explain the effects of feedback on the amplifier poles in terms of stability and pole location, poles of the feedback amplifier. 4. Write short note on: (i) Stability problems and (ii) Gain and Phase Margins. 5. Explain the effects of phase margin on closed loop response. 6. Explain Frequency Compensation in terms of Miller Compensation and Pole splitting. 7. List out all feedback network topologies with neat diagram. Explain any two in brief. 8. Explain the general structure of feedback amplifier with a neat signal flow diagram. 9. Explain an alternative approach to determine the loopgain (Aβ). 10. List out the properties of Negative feedback and explain in detail. 11. Explain the theory and implementation of Frequency compensation along with Miller compensation and Pole splitting.
5. Digital CMOS Logic Circuits – Unit 7
1. Write short notes on: i. CMOS Logic gate circuits, ii. Dynamic Logic circuits, iii. Pass Transistor logic circuits, iv. Transistor sizing, v. Effects of Fan-in and Fan-out. 2. Explain the design and performance analysis of the CMOS inverter. 3. Describe briefly Logic circuit characterization. 4. Explain the non-ideal effects of Dynamic logic circuits.
5. Describe the operation of Transmission gates as Switches with neat diagram. 6. Write short notes on: Domino CMOS logic (or) Dynamic logic circuits. 7. Explain in detail the Digital IC technologies and Logic circuit families. 8. Explain the dynamic operation of CMOS inverter and also derive an expression for t PLH and tPHL. 9. Draw the CMOS logic circuit for (i) Y = A(B+CD) and (ii) Y = A+BC.
