Medipix3RX manual v1.4
10/31/2012 CERN R. Ballabriga and X. Llopart
Medipix3RX manual
Contents 1
List of Figures ......................................................... .......................................................................................................................... ................................................................. 4
2
List of Tables .......................................................... ........................................................................................................................... ................................................................. 6
3
Medipix3RX Physical Description ............................................................ ............................................................................................ ................................ 7 3.1
Wire Bond Extension (WB) .................................................................. .................................................................................................. ................................ 8
3.2
Through Silicon Via (TSV) ......................................................... .................................................................................................... ........................................... 9
4
Medipix3RX Active Area............................................................... ........................................................................................................ ......................................... 10 4.1
Configuration of the pixel ........................................................ ................................................................................................. ......................................... 17
4.1.1 4.2 5
Modes of operation .......................................................... .................................................................................................. ........................................ 18
Biasing the analog circuitry .................................................................. ............................................................................................... ............................. 18 Medipix3RX Bottom Periphery ................................................................ ............................................................................................. ............................. 20
5.1
Medipix3RX IO IO and Power Pads ........................................................... ........................................................................................ ............................. 20
5.1.1
Medipix3RX LVDS receiver and driver...................................................... driver....................................................................... ................. 24
5.1.2
Medipix3RX IO Analog pads ........................................................... ...................................................................................... ........................... 25
5.2
Medipix3RX IO Logic ........................................................ ......................................................................................................... ................................................. 25
5.3
Medipix3RX Analog Periphery ............................................................... .......................................................................................... ........................... 25
5.3.1
Band-Gap circuitry .............................................................. .................................................................................................... ...................................... 25
5.3.2
Medipix3RX DACs ................................................................. ...................................................................................................... ..................................... 26
5.3.3
Selection and monitoring logic ........................................................ ................................................................................. ......................... 27
5.4 6
Test Pulse ................................................................ .......................................................................................................................... .......................................................... 27 Medipix3RX power consumption (To be updated) ............................................................ ............................................................... ... 29
6.1
Analog power consumption (VDDA/GNDA and VDDA33) ................................................ 29
6.1.1
Analog Periphery power consumption ........................................................ ..................................................................... ............. 29
6.1.2
Active Area analog power consumption .................................................................. .................................................................... 30
6.2
Digital power consumption (VDD/GND DVDD/DGND) ..................................................... 30
6.2.1
Digital periphery power consumption ........................................................... ...................................................................... ........... 30
6.2.2
Active area digital power consumption .......................................................... .................................................................... .......... 31
7
Medipix3RX Operation ............................................................... .......................................................................................................... ........................................... 32 7.1
Main guidelines for the chip operation .................................................................. ............................................................................ .......... 32
7.2
Chip Reset ......................................................... ......................................................................................................................... ................................................................ 32
7.3
Chip Control Modes ................................................................ .......................................................................................................... .......................................... 32
7.4
Operation Mode Register (OMR) .................................................................. ...................................................................................... .................... 32
7.5
Periphery operations .............................................................. ........................................................................................................ .......................................... 35
7.5.1
Load DACs (M012=100) ............................................................................................... 36
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Medipix3RX manual 7.5.2
Load CTPR (M012=101) ............................................................................................... 36
7.5.3
Read DACs (M012=110) ............................................................... .............................................................................................. ............................... 37
7.5.4
Read OMR and ChipID (M012=111) ........................................................ ............................................................................ .................... 37
7.5.5
E-fuse burning .................................................................. ........................................................................................................... ......................................... 38
7.6
Pixel Matrix operations ............................................................ ..................................................................................................... ......................................... 39
7.6.1
Load Pixel Matrix Configuration (M012=01x) ............................................................. 39
7.6.2
Read Pixel Matrix (M012=x00) .................................................................................... 40
7.6.3
Fast Pixel Matrix Reset ................................................................. .............................................................................................. ............................. 46
7.7
Acquisition modes:......................................................... ............................................................................................................ ................................................... 47
7.7.1
Sequential Acquisition Mode ........................................................ .................................................................................... ............................ 48
7.7.2
Continuous Read Write Acquisition Mode .......................................................... ............................................................... ..... 49
8
Appendix ........................................................ .......................................................................................................................... ....................................................................... ..... 50 8.1
Detailed Operation Mode Register table .......................................................... .......................................................................... ................ 50
8.2
Multi-chip Medipix3RX connection options ................................................................ ..................................................................... ..... 51
8.3
Recommended PCB layout power distribution for a single Medipix3 .............................. 54
8.4
Medipix3RX wafer step plan .................................................................. ............................................................................................. ........................... 56
8.5
Chip Identification ............................................................ ............................................................................................................. ................................................. 57
9
Threshold Equalization......................................................... .......................................................................................................... ................................................. 58
10
Review on the Chip Operation ........................................................ .............................................................................................. ...................................... 59
10.1
Load Pixel Matrix Configuration (M012=01x) ......................................................... ................................................................. ........ 59
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Medipix3RX manual
1 List of Figures Figure 1. The Medipix3RX chip. The dash line shows the in-chip dicing lane to remove the wire-bond extenders. The layers displayed are top metal me tal (MA) and passivation openings (DV). ________________ ________________________ _______________ _______ 7 Figure 2. Bottom left corner detail showing: the chip origin, the WB extension, a “dicing streets” and “fingers”. 8 Figure 3. Detail of the TSV pads at the bottom left corner of the chip. ________________ ________________________ _________________ __________ _9 Figure 4. The position of the regular structure in the matrix and the assignation of the test pulses (indicated in blue) to the pixels in the matrix is shown. The regular structure that repeats in the matrix is a 2x2 pixel structure. In red, the type of pixel is indicated. ________________ _________________________ _________________ ________________ ________________ __________ __ 10 Figure 5. Distances between the center of the passivation openings to the left and right of the chip edge. The position of the regular structure in the full matrix is shown. For Colour Mode operation only P1 is bump-bonded. _________________________________________________________________________________________ 10 Figure 6. Scheme with the modes of operation of the Medipix3RX chip. _________________ _________________________ ______________ ______ 11 Figure 7. Block diagram of the pixel circuitry when programmed in Fine Pitch Mode with Single Pixel Mode of operation. operat ion. ______________________________________________ ________________________ ____________________________________________ __________________________________ ____________ 12 Figure 8. Block diagram of the pixel circuitry when programmed in Fine Pitch Mode with Charge Summing Mode of operation. _________________________________________________________________________ 13 Figure 9. Block diagram of the pixel circuitry when programmed in Spectroscopic Mode with Single Cluster Mode of operation. _________________________________________________________________________ 14 Figure 10. Block diagram of the pixel circuitry when programmed in Spectroscopic Mode with Charge Summing Mode of operation. _________________________________________________________________________ 15 Figure 11. RX, PC and M1 layout of the regular structure is shown. The regular structure is composed by 4 pixels with different layouts. 1 to 4 indicate the analog circuitry of pixels 1, 2, 3 and 4 respectively. 5 shows the digital part for pixels 1 and 2. 6 shows the di gital part for pixels 3 and 4. The merge of digital parts allows sharing common circuitry and reducing the circuit area. The orientation assumes the periphery is on the bottom. ___ 16 Figure 12. RX, PC and M1-M4 layout of the regular structure is shown. It is composed by 4 pixels with different layouts. The orientation assumes the periphery is on the bottom. M4 lines for biasing the pixel analog circuits are shown in purple. ________________________________________________________________________ 16 Figure 13. Sche matic of the analog part. The biasing signals are shown in blue.__________________ blue._________________________ _______ 19 Figure 14. Sche matic of the Medipix3RX bottom periphery ________________ ________________________ ________________ _________________ _________ 20 Figure 15. Multidrop LVDS bus configuration. D: LVDS Driver; R: LVDS Receiver. _________________ ________________________ _______ 24 Figure 16. Point-to-point LVDS bus configuration. D: LVDS Driver; R: LVDS Receiver. _________________ _____________________ ____ 24 Figure 17. Measure of the Medipix3RX on-chip temperature sensor in a climatic chamber. The measurement is linear in the range of temperatures. ________________ ________________________ _________________ _________________ ________________ ________________ __________ __ 26 Figure 18. Pixel column test pulse schematic. sche matic. ________________ ________________________ ________________ _________________ _________________ ___________ ___ 28 Figure 19. Load Operation Mode Register time diagram. _____________________ _____________________________ ________________ ______________ ______ 35 Figure 20. Fuse programming time diagram. The FusePulse int shows the internal programming pulse width. _ 38 Figure 21. Time diagram of the load pixel matrix command. Only the load of one counter is shown. The pixel column construction is shown in Figure 21. _________________ _________________________ ________________ ________________ _________________ _____________ ____ 39 Figure 22. The pixel column is built by connecting together the 256 pixels shift registers. CA stands for CounterL and CB stands for CounterH. __________________________________________________________________ 40 Figure 23. Data readout of the chip when programmed in serial mode (PS=00), counter length of 12 bits (CountL[0:1]=01) and without information header (InfoHeader=0). _________________ _________________________ ________________ __________ __ 41 Figure 24. Data readout of the chip when programmed in serial mode (PS=00), counter length of 12 bits (CountL[0:1]=01) and with information header (InfoHeader=1). ________________ ________________________ _________________ _____________ ____ 41 Figure 25. Data readout of the chip when programmed in 2-bit parallel mode (PS=01), counter length of 12 bits (CountL[0:1]=10) and without information header (InfoHeader=0). Notice that the synchronization header is only present prese nt in DataOut[0]. DataOut [0]. _____________________ ___________________________________________ ____________________________________________ _______________________ _ 42 Figure 26. Data readout of the chip when programmed in 2-bit parallel mode (PS=01), counter length of 12 bits (CountL[0:1]=10) and with information header (InfoHeader=1). Notice that the synchronization header and the information header are only present in DataOut[0]. ___________________ ___________________________ _________________ _________________ ___________ ___ 43
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Medipix3RX manual Figure 27. Schematic of the different pixel matrix regions of interest which can be readout independently. On the left the columns have a minimum width of 32 pixel columns and can be selected individually; on the right, the rows, are always readout from the bottom. b ottom. _________________ _________________________ ________________ ________________ _________________ _________ 45 Figure 28. Readout of a region of interest of 32 x 64 pixels programmed in 12-bit mode. The OMR settings are: CountL[0:1]=01, PS[0:1]=11, ColumnBlockSel=1, ColumnBlock[0:2]=010, RowBlockSel=1 and RowBlock[0:2]=011 and InfoHeader=0.__________________________________________________________________________ 45 Figure 29. Example of a Fast Pixel Matrix Reset done by asserting the MatrixFastClear input signal twice. EnableIn is not needed for this high priority command. ________________ ________________________ _________________ _________________ ___________ ___ 46 Figure 30. Example of a Fast Pixel Matrix Reset done by asserting the MatrixFastClear input signal once. EnableIn is not needed for this high priority command. ________________ ________________________ _________________ _________________ ___________ ___ 47 Figure 31. Full sequential readout _________________ _________________________ ________________ ________________ _________________ _________________ ___________ ___ 48 Figure 32. Full sequential readout of two consecutive frames. Notice that the OMR has to be loaded only once at the beginning of the sequence. _________________ _________________________ ________________ ________________ _________________ _________________ ___________ ___ 48 Figure 33. Continuous Read Re ad Write time diagram. ________________ ________________________ ________________ ________________ _________________ _________ 49 Figure 34. Sche me of connection of 1 single Medipix3RX chip _________________ _________________________ ________________ ______________ ______ 51 Figure 35. Scheme of a daisy-chain connection with 2 Medipix3RX chips ________________ ________________________ ______________ ______ 51 Figure 36. Sche me of a connection with 2 Medipix3RX chips working in full parallel IO readout . ____________ ____________ 52 Figure 37. Scheme of a connection with 2 Medipix3RX chips working in serial input and parallel output readout. _________________________________________________________________________________________ 52 Figure 38. Scheme of a connection of 2 Medipix3RX chips connected in serial input and parallel output readout mode with one common output clock. _____________________ _____________________________ ________________ ________________ _________________ _____________ ____ 53 Figure 39. Proposed pin distribution in the VHDCI connector ________________ _________________________ _________________ _______________ _______ 55 Figure 40. Medipix3RX wafer step plan _________________ _________________________ ________________ _________________ _________________ _______________ _______ 56 Figure 41. Medipix3RX wafer map _________________ _________________________ ________________ ________________ _________________ _________________ ___________ ___ 57 Figure 42. Chip decoding algorythm ______________ _______________________ _________________ ________________ ________________ _________________ _____________ ____ 57 Figure 43. Pixel Configuration matrix quick fix diagram ________________ ________________________ _________________ _________________ ___________ ___ 59 Figure 44. Load Pixel matrix configuration in 2x128 rows data blocks _______________ _______________________ ________________ __________ __ 59
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Medipix3RX manual
2 List of Tables Table 1. Active area depending on dicing cuts _____________________________________________________ 8 Table 2. Position of the HV TSV pads with respect the chip origin. _____________________________________ 9 Table 3. Configuration bits for the Medipix3RX full imaging chip. The total number of configuration bits is 12. 17 Table 4. Configuration lines for the Medipix3RX chip. ______________________________________________ 17 Table 5. Position of the 12 configuration bits on the CounterH. In the Medipix3RX all the configuration bits are shifted through CounterH. ___________________________________________________________________ 18 Table 6. Modes of operation of the digital circuitry of the pixel. (SPM stands for Single Pixel Mode, CSM Charge Summing Mode, FP Fine Pitch (55um), SPECT (110um), SRW Sequential Read-Write and CRW Continuous ReadWrite). ___________________________________________________________________________________ 18 Table 7. Biasing signals for the preamplifier circuit. _______________________________________________ 19 Table 8. Biasing signals for the shaper circuit. The bias voltage for the pole-zero cancellation circuit depends on the gain mode of operation and on I_Ikrum. The values of the bias voltage are shown for the different gain modes of operation, assuming an I_Ikrum current of 2nA. __________________________________________ 19 Table 9. Biasing signals for the discriminator and equalization DAC. __________________________________ 19 Table 10. List and description of the IO pads. ____________________________________________________ 20 Table 11. Medipix3RX bottom periphery power/ground pads. _______________________________________ 21 Table 12. IO pad and power/ground pads locations from the chip origin (bottom left corner) to the center of the Wire Bonding (WB) pads and centre of the Through Silicon Via (TSV) pads at the bottom of the chip. There are 110 WB connections and 108 TSV connections at the bottom of the chip. ______________________________ 21 Table 13. LVDS receiver summary ______________________________________________________________ 24 Table 14. LVDS driver summary _______________________________________________________________ 24 Table 15. Medipix3RX DACs. __________________________________________________________________ 26 Table 16. Internal monitoring signals selection code and simulated value. _____________________________ 27 Table 17. Pixel column test pulse circuit summary ________________________________________________ 28 Table 18. Summary of the overall Medipix3RX chip power consumption. ______________________________ 29 Table 19. Detailed current consumption of the different blocks contained in the Medipix3RX analog periphery. _________________________________________________________________________________________ 29 Table 20. Minimum and maximum analog power consumption of the Medipix3RX active area. ____________ 30 Table 21. Digital power consumption in the Medipix3RX periphery. The values are obtained with the Encounter® Power Analysis tool in statistical mode with a 50% net toggle probability. _____________________________ 30 Table 22. Bit position in the 48-bit OMR. ________________________________________________________ 33 Table 23. OMR bits description. Default column shows the bit value after chip Reset. ____________________ 33 Table 24. Example of FusePulseWidth range depending on the system readout clock. ____________________ 38 Table 25. Data output stream length for different s ettings of the PS[0:1] and CountL[0:1] OMR bi ts. ________ 40 Table 26. Readout column selection to DataOut[0:7] versus the PS[0:1], ColumnBlockSel and ColumnBlock[0:2] OMR bits. _________________________________________________________________________________ 44 Table 27. CounterL and CounterH configuration in the different acquisition modes ______________________ 47 Table 28. Full Operation Mode Register (OMR) description table. This table is only valid for full pixel matrix (256 x 256) readout. ____________________________________________________________________________ 50 Table 29. Summary of the Medipix3RX connectivity. “Parallel Oc_clk” stands for: Parallel output common readout clock. _____________________________________________________________________________ 53 Table 30.Summary of the threshold equalization depending on different settings _______________________ 58
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Medipix3RX manual
3 Medipix3RX Physical Description Figure 1 shows the Medipix3RX chip dimensions and the different dicing option cuts. The active area contains a 256 x 256 matrix of 55 µm square pixels. The chip IO can be connected either through standard wire bonding (WB) or through silicon via (TSV). The bottom periphery which contains the IO-logic, DACs, e-fuses, IO pads and power pads is placed at the bottom of the active area (14100 µm x 800 µm). At bottom there are the wire bond extenders which measure 14100 µm x 1000 µm.
14.1 mm
m m 8 8 . 5 1
Figure 1. The Medipix3RX chip. The dash line shows the in-chip dicing lane to remove the wire-bond extenders. The layers displayed are top metal (MA) and passivation openings (DV).
The Medipix3RX can have the wire bond extenders diced off as shown in Figure 1. Table 1 summarizes the percentage of active area with and without the in-chip dicing option.
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Medipix3RX manual Table 1. Active area depending on dicing cuts
In-chip Dicing
X [µm]
Y [µm]
Active Area
1
14100 14100
15880 ~14900
88.4% 94.3%
Medipix3RX bottom WB Medipix3RX bottom TSV
3.1 Wire Bond Extension (WB) The wire bond extension pads allows the electrical connection from the IO pads to the readout system using standard wedge wire bonding once a sensor is bump bonded to the active area. With such extension the active guard-ring (distance from the first active pixel to the sensor edge) of the sensor material can measure up to ~1.2 mm without compromising the connectivity. There are 110 IO WB pads (see Table 11)
m µ 0 0 8
TSV test structures
“dicing street” m µ 0 0 1
“fingers”
m µ 0 0 0 1
62 µm
m µ 7 9 2
(0,0) Chip Origin
Figure 2. Bottom left corner detail showing: the chip origin, the WB extension, a “dicing streets” and “fingers”.
The opening in the passivation at the wire bond extension measures 62 µm x 297 µm. There are no active components in these blocks to allow a possible dicing off if the TSV connection (see 3.2) is used. The “dicing street” is 100 µm wide with 10 µm thick “fingers” laid out in the 2 top metals MA (4 µm Al) and E1 (3 µm Cu). There are test TSV test structures in the 1mm fingers allowing a snake connection between the chip front (TSV side) and back (Top metal side).
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Medipix3RX manual
3.2 Through Silicon Via (TSV) Through Silicon Via (TSV) technology is a vertical electrical connection passing completely through a silicon wafer or die. This technology gives an alternative connection between the Medipix3RX chip IO and the readout system which significantly improves the percentage of active area as shown in Table 1. Medipix3RX includes M1 (first metal) landing pads which allow such connections. There are 2 kinds of TSV pads: •
•
The TSV for IO and power/ground : These pads are square with a side length of 76.5 µm and a regular pitch of 120 µm. Their position in the chip is shown in Table 11. The TSV for the sensor High Voltage bias : These pads are rectangular (78 µm x 135 µm). There are 4 HV TSV pads which position with respect the chip origin is shown in Table 2. Table 2. Position of the HV TSV pads with respect the chip origin.
X [µm] 114 13990
HV_TSV0 HV_TSV1
Y [µm] 1110 1110
Figure 3 shows the TSV landing pads in the bottom left corner of the chip.
IO TSVs
76.5 µm
HV TSVs
IO TSVs H V T S V s
Figure 3. Detail of the TSV pads at the bottom left corner of the chip.
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Medipix3RX manual
4 Medipix3RX Active Area The Medipix3RX active area is formed by a square matrix of 256 x 256 pixels. Each pixel measures 55 µm x 55 µm. The regular structure in the matrix is implemented as a cluster composed of 2x2 pixels with different circuitry. This allows the implementation of the Spectroscopic Mode of operation in which only one pixel in the cluster is bump-bonded (Pixel 1). The position of Pixel 1 with respect to the matrix edges is shown in Figure 4. The distances of the passivation openings to the chip edge for the top-right and top-left pixels are shown in Figure 5.
TP2
…
TP1
TP1
TP2
…
TP2
TP1
P1 TP2
P4
P2
P4
TP1
P3
P1
P3
P2
… … Regular Structure The bump-bonded pixel in Spectroscopic Mode is Pixel1
… TP2
…
TP1
P3
TP1
P2
TP1
P3
…
TP2
P4
TP2
P1
Matrix edge
TP1
P1 TP2
P4
P2
Row of pads for sensor guard ring connection
Figure 4. The position of the regular structure in the matrix and the assignation of the test pulses (indicated in blue) to the pixels in the matrix is shown. The regular structure that repeats in the matrix is a 2x2 pixel structure. In red, the type of pixel is indicated.
m µ 6 7 . 7 3
25.67 µm
m µ 6 7 . 7 3
49.33 µm
Figure 5. Distances between the center of the passivation openings to the left and right of the chip edge. The position of the regular structure in the full matrix is shown. For Colour Mode operation only P1 is bump-bonded.
The pixel front-end can be configured in four modes of operation that are combinations of 1. FinePitch/Spectroscopic mode and 2. SinglePixel/ChargeSumming mode. The front-end operation modes are:
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Medipix3RX manual
1. FinePitch and Single Pixel Mode: The pixel pitch is 55µm. Every pixel works independently of its neighbouring pixels. The block diagram for this mode of operation is shown in Figure 7. 2. FinePitch and Charge Summing Mode: The charge in every cluster of 4 pixels is reconstructed in every corner between pixels and is assigned to the pixel with the largest charge deposition. This is a way of maintaining the 55 µm spatial resolution while eliminating the spectral distortion due to charge diffusion in the sensor. The block diagram for this mode of operation is shown in Figure 8. 3. Spectroscopic Mode and Single “Cluster” Mode: The pixels are grouped in clusters of 4 becoming a single detection unit. Only one of the pixels in the cluster is bump-bonded. The detector pitch is 110 µm. In this mode of operation 8 thresholds per cluster are available. The block diagram for this mode of operation is shown in Figure 9. 4. Spectroscopic Mode and Charge Summing Mode where the readout pixels are grouped in clusters of 4 pixels and become a single detection unit. The charge summing algorithm in which the charge is reconstructed and assigned to a single pixel is applied. This means that all the charge deposited in an area of 220 µm x 220 µm is reconstructed at the summing nodes and assigned to only one single cluster, the cluster with the highest charge deposition. The spatial resolution becomes 110 µm x 110 µm. In this mode of operation we have 4 thresholds with the local charge information and 4 with the reconstructed charge information. The block diagram for this mode of operation is shown in Figure 10. Figure 6 shows a diagram with the different modes of operation. The 4 pixels in the regular cluster are shown. The red octagon shows the bump-bonded pixel in the cluster. The arrows represent the activation of the communication circuits for charge reconstruction and hit allocation. P3
P1
P3
P1
P4
P2
P4
P2
Singl e Pixel Mode, Fine pitch
Charge Summing Mode, Fine pit ch
P3
P1
P3
P1
P4
P2
P4
P2
Singl e Pixel Mode, Spectroscopi c
Charge Summing Mod e, Spectroscopi c
Figure 6. Scheme with the modes of operation of the Medipix3RX chip.
Every pixel contains an analog and a digital part. The block diagram of the pixel schematic in the different modes of operation are shown in Figure 7 to Figure 10. The charge collected on a pixel is integrated by a Charge Sensitive Amplifier (CSA) with a feedback capacitance of programmable value (7fF, 14fF, 21fF and 28fF). The CSA is based on the Krummenacher architecture and can handle both positive and negative input charges. A test injection capacitance of ~5fF is provided in each pixel in order to permit full testing of the chip functionality. Two different test pulses are available to allow the injection of different charges in adjacent pixels (the distribution of the test pulses in the matrix is shown in Figure 4). This allows the testing of the all the modes of operation of the system. The output of the CSA is filtered by a first order semi-gaussian shaper with a time constant of ~120 ns,
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Medipix3RX manual which acts both as a transconductance and as a noise filter. The shaper also AC couples the output of the preamplifier to the rest of the circuit (eliminating the offset produced by the mismatch of the transistors in the preamplifier feedback loop and thus relaxing the dimensions of those transistors) and makes the system less sensitive to the variations of the preamplifier characteristics. Furthermore the shaper generates five currents with amplitudes proportional to the charge collected on the input electrode. The currents generated in the shaper are sent to the local discriminator and to the corresponding summing circuits. The summing nodes are located effectively at each pixel corner. There are two discriminators in each pixel, and one summing node per pixel corner. Each discriminator has a 5-bit Digital-to-Analog Converter (DAC) to reduce the threshold dispersion caused by mismatch in the transistors that provide the threshold and the summing currents. When configured in Charge Summing Mode of operation, the applied algorithm is as follows: 1. The lower threshold in every pixel (or cluster) is compared to the locally deposited signal. 2. The arbitration circuitry suppresses the pixels with lower signal, identifying the pixel (or cluster) with the largest energy deposit. The information of the hit pixel after the allocation algorithm is stored in the lower counter (this information is referred to as “Single Pix el Mode Arbitrated” because the information is based on the local charge deposited in the pixel). 3. In parallel, the charge has been reconstructed and compared with the highest threshold in the 4 adjacent summing nodes with respect to the pixel. 4. The pixel with the highest charge checks the adjacent summing circuits to see if at least one of them exceeds the highest threshold. Because the pixel contains two counters (one associated with each threshold) the pixel readout can be configured for Continuous Read-Write. This makes simultaneous counting and readout possible, providing dead-time-free operation. In this case the output of one of the discriminators is ignored. The readout discriminator is selectable. The block diagram for the configuration of the pixel is shown in the pictures below. Shutter ConfigDiscL[0:4]
DataInL
1 5
DataInH
1
1
CF
1
DISCL TH[0]
-Av
ConfigDiscH[0:4]
gm
5
CTEST
PULSE PROCESSING LOGIC
Polarity CSM_SPM ColourMode
TestBit
TH[1]
1 1
1 GainMode[0:1]
COUNTERL
COUNTERH
DISCH 1 DataOutL
TestPulse Disc_CSM_SPM CRW_SRW CSM_SPM ColourMode Equalization
1 DataOutH
MaskBit
Figure 7. Block diagram of the pixel circuitry when programmed in Fine Pitch Mode with Single Pixel Mode of operation.
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Medipix3RX manual
To adjacent summing nodes
ConfigDiscL[0:4]
DataInH
1
5
3
DataInL
Shutter
1
1
-Av
4
gm
ConfigDiscH[0:4]
GainMode[0:1]
5
PULSE PROCESSING LOGIC AND ARB ITRATION CIRCUITRY
TH[1]
DISCH
1
COUNTERH
1
3 TestPulse
1
1
Polarity CSM_SPM ColourMode
TestBit
COUNTERL
TH[0]
1
CTEST
1
DISCL
CF
From adjacent pixels
DataOutL Disc_CSM_SPM CRW_SRW CSM_SPM ColourMode Equalization MaskBit
1 DataOutH
Communication with adjacent pixels for hit allocation
Figure 8. Block diagram of the pixel circuitry when programmed in Fine Pitch Mode with Charge Summing Mode of operation.
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Medipix3RX manual
CF
PIXEL1
ConfigDiscL_P1[0:4]
Control Signals
1
-Av
gm
DataInP1
TH[0] DiscL
2
PULSE PROCESSING LOGIC
1 TH[1] DiscH
TestBit
COUNTERL COUNTERH 2
GainMode[0:1]
DataOutP1 ConfigDiscH_P1[0:4]
TestPulse
PIXEL2
gm
ConfigDiscL_P2[0:4]
Control Signals
1
DataInP2
TH[2] DiscL
2
PULSE PROCESSING LOGIC
1 TH[3] DiscH
COUNTERL COUNTERH 2 DataOutP2
ConfigDiscH_P2[0:4]
PIXEL3
gm
ConfigDiscL_P3[0:4]
Control Signals
1
DataInP3
TH[4] DiscL
2
PULSE PROCESSING LOGIC
1 TH[5] DiscH
COUNTERL COUNTERH 2 DataOutP3
ConfigDiscH_P3[0:4]
PIXEL4 gm
ConfigDiscL_P4[0:4]
Control Signals
1
DataInP4
TH[6] DiscL
2
PULSE PROCESSING LOGIC
1 TH[7] DiscH
COUNTERL COUNTERH 2 DataOutP4
ConfigDiscH_P4[0:4]
Figure 9. Block diagram of the pixel circuitry when programmed in Spectroscopic Mode with Single Cluster Mode of operation.
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Medipix3RX manual
PIXEL1
CF
To adjacent clusters
ConfigDiscL_P1[0:4]
Control Signals DataInP1
1
-Av
TestBit
GainMode[0:1]
TH[0] DiscL
gm From adjacent clusters
PULSE PROCESSING LOGIC
1
3
2 COUNTERL COUNTERH
TH[1] DiscH
2 DataOutP1
ConfigDiscH_P1[0:4]
PIXEL2 TestPulse
To adjacent clusters
ConfigDiscL_P2[0:4]
Control Signals DataInP2
1
TH[2] DiscL
gm From adjacent clusters
1
3
2
PULSE PROCESSING LOGIC
COUNTERL COUNTERH
TH[3] DiscH
2 DataOutP2
ConfigDiscH_P2[0:4]
PIXEL3
To adjacent clusters
ConfigDiscL_P3[0:4]
Control Signals DataInP3
1
TH[4] DiscL
gm From adjacent clusters
PULSE PROCESSING LOGIC
1
3
2 COUNTERL COUNTERH
TH[5] DiscH
2 DataOutP3
ConfigDiscH_P3[0:4]
PIXEL4 To adjacent clusters
ConfigDiscL_P4[0:4]
Control Signals DataInP4
1
TH[6] DiscL
gm From adjacent clusters
PULSE PROCESSING LOGIC
1
3
2 COUNTERL COUNTERH
TH[7] DiscH
2 DataOutP4
ConfigDiscH_P4[0:4]
Communication with adjacent clusters for hit allocation
Figure 10. Block diagram of the pixel circuitry when progr ammed in Spectroscopic Mode with Charge Summing Mode of operation.
The layout of one of the Medipix3RX regular cells is shown in Figure 11 and Figure 12.
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Medipix3RX manual
3
6
4
1
5
2
Figure 11. RX, PC and M1 layout of the reg ular structure is shown. The regular structure is composed by 4 pixels with different layouts. 1 to 4 indicate the analog circuitry of pixels 1, 2, 3 and 4 respectively. 5 shows the digital part for pixels 1 and 2. 6 shows the digital part for pixels 3 and 4. The merge of digital parts allows sharing common circuitry and reducing the circuit area. The orientation assumes the periphery is on the bottom.
3
4
6
1
5
2
Figure 12. RX, PC and M1-M4 layout of the regular structure is shown. It is composed by 4 pixels with different layouts. The orientation assumes the periphery is on the bottom. M4 lines for biasing the pixel analog circuits are shown in purple.
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Medipix3RX manual
4.1 Configuration of the pixel The pixel mode of operation is configured using local configuration bits and global metal lines. Figure 5 shows the circuits that are programmed by the different configuration bits and global metal lines. The configuration bit data is stored in a level sensitive latch. The list of the configuration bits is shown in Table 3. The position of the configuration bits is shown in Table 5. All configuration bits are placed in CounterH. Table 3. Configuration bits for the Medipix3RX full imaging chip. The total number of configuration bits is 12.
Configuration Bit Name
Power domain
Bits position
TestBit
Analog
11
MaskBit
Digital
0
ConfigDiscL[0:4]
Analog
1,2,3,4,5
ConfigDiscH[0:4]
Analog
6,7,8,9,10
Description When active (logic 1), a pulse can be injected through a test capacitance. Configured to logic 0 for normal operation with a sensor material. Set to 1 to mask the pixel. Set to 0 for normal operation. Threshold adjustment bits for the 5-bit DAC associated with the lower threshold (SPM) or the channel configured in Single Pixel Mode (CSM). Threshold adjustment bits for the 5-bit DAC associated with the higher threshold (SPM) or the channel configured in Charge Summing Mode (CSM).
Table 4. Configuration lines for the Medipix3RX chip.
Global configuration signal
Power domain
ColourMode
Analog/Digital
CSM_SPM
Analog/Digital
GainMode[0:1]
Analog
Polarity
Analog
October 31, 2012
Description
When active (logic 1) the pixel is programmed in Spectroscopic Mode (Colour Mode). This is the mode in which one in every four pixels is bump-bonded (110um pitch). When low, the pixel is configured in Fine Pitch Mode (55um pitch). When active the pixel or cluster are applying the charge summing mode algorithm. When low, the pixel or cluster are working independently from their neighbours. 00: configures the pixel in Super High Gain mode (CFB=7fF). 10: configures the pixel in High Gain mode (CFB=14fF). 01: configures the pixel in Low Gain mode (CFB=21fF). 11: configures the pixel in Super Low Gain mode (CFB=28fF). PolarityBit=1 for hole collection (=0 for electron collection).
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Medipix3RX manual
Table 5. Position of the 12 configuration bits on the CounterH. In the Medipix3RX all the configuration bits are shifted through CounterH.
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
t i B k s a M
] 0 [ L c s i D g i f n o C
] 1 [ L c s i D g i f n o C
] 2 [ L c s i D g i f n o C
] 3 [ L c s i D g i f n o C
] 4 [ L c s i D g i f n o C
] 0 [ H c s i D g i f n o C
] 1 [ H c s i D g i f n o C
] 2 [ H c s i D g i f n o C
] 3 [ H c s i D g i f n o C
] 4 [ H c s i D g i f n o C
t i B t s e T
4.1.1 Modes of operation Table 6. Modes of operation of the digital circuitry of the pixel. (SPM stands for Single Pixel Mode, CSM C harge Summing Mode, FP Fine Pitch (55um), SPECT (110um), SRW Sequential Read-Write and CRW Continuous Read-Write).
ColourMode
CSM_SPM
Continuous RW
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Operation Mode SPM, FP SPM, FP CSM, FP CSM, FP SPM, SPECT SPM, SPECT CSM, SPECT CSM, SPECT
Readout mode SRW CRW SRW CRW SRW CRW SRW CRW
Each pixel contains two configurable-depth registers (Counter0 & Counter1) which can function either as LFSR counters or as serial shift registers. During counting, the register bits are connected in a LFSR architecture. During reading, the register bits are daisy-chained for serial shifting. The registers can be configured as two 1-bit, 6-bit, or 12-bit registers, or a single 24-bit register through the CountL[0:1] OMR bits (see Table 24).
4.2 Biasing the analog circuitry To properly set the analog circuit reference currents and voltages, some DACs have been implemented on chip. A schematic of the analog part with the biasing signals for every sub-circuit is shown in Figure 10. The list of reference currents and voltages needed to bias the preamplifier are shown in Table 7, Table 8 and Table 9.
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Medipix3RX manual
CF
To adjacen t pixels THSPM
TH ADJ_SPM
3
-Av
Iout_TH_SPM
gm
ZX
VOUT_DISCL
ZX
VOUT_DISCH
1
THCSM
TH ADJ_CSM
3
From adjacent pixels I_Preamp I_Ikrum V_Fbk V_Gnd V_Cas
I_Shaper V_Rpz V_Cas
Threshold[0:7] I_DAC_DiscL I_DAC_DiscH
I_Disc I_Disc_LS
Figure 13. Schematic of the analog part. The biasing signals are shown in blue. Table 7. Biasing signals for the preamplifier circuit.
Signal name
Nominal Value
I_Preamp
1.5µA 1nA 800mV (600mV
I_Ikrum V_Fbk V_Cas V_Gnd
Table 8. Biasing signals for the shaper circuit. The bias voltage for the pole-zero cancellation circuit depends on the gain mode of operation and on I_Ikrum. The values of the bias voltage are shown for the different gain modes of operation, assuming an I_Ikrum current of 2nA.
Signal name
Nominal Value
I_Shaper V_Rpz V_RPZ (GM=00LSB) V_RPZ (GM=01LSB) V_RPZ (GM=10LSB) V_RPZ (GM=11LSB)
0.55µA 1.5V (OFF) 0.3V 0.55V 0.6V 0.7V
Table 9. Biasing signals for the discriminator and equalization DAC.
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Signal name
Nominal Value
I_Disc
1µA
I_Disc _LS I_DAC_DiscL I_DAC_DiscH
0.35µA 10nA 10nA
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Medipix3RX manual
5 Medipix3RX Bottom Periphery The bottom periphery is the interface between the active area and the Medipix3RX readout system. Figure 11 shows a schematic description of the bottom periphery. It measures 14100 µm x 1800 µm including the WB extensions. The bottom periphery contains the following circuitry: IO pads and power pads Medipx3 IO Logic 32 e-fuse bits Analog periphery block: band-gap, 27 DACs and monitoring circuitry End Of Column and 2 Test Pulse circuits for each pixel column WB extensions (14100 µm x 1000 µm)
• • • • • •
0 C o E
0 C p T
1 C o E
1 C p T
2 C o E
IO Logic
n I n I n e I l a t l k b a C a n D E
3 5 2 C o E
2 C p T
8 LVDS in
e e r e r s O o I u V C V o C l f V V l 5 a g 5 E 5 t - 3 . a . . . o i l 1 i t 1 g 2 D 3 a i g D i n D V D A
A A D D D N V G
D D D N V G
D S D S V V D D
4 5 2 C o E
4 5 2 C p T
5 5 2 C o E
5 5 2 C p T
BandGap Biasing 27 DACs (226 bits)
E-Fuses (32 bits)
r W a e R l C C h r l c t e t e t i t e S s s t a w r e u e F x S t i R h _ S n r P T u t a o M C
3 5 2 C p T
3 3 A D D V
n I G B _ T X E
n I C A D _ T X E
n I G B _ T X E
n I C A D _ T X E
T U O _ C A D
] ] ] ] ] ] ] ] t 0 [ 1 2 [ 3 4 [ 5 6 [ 7 u [ t t [ t t [ t t [ t t O t u u u u u u u u l e u O O O O O O O O O b k a a a a a a a a l t t t t t t t t a C a a a a a a a a n D D D D D D D D E
T U O _ C A D
10 LVDS out
Figure 14. Schematic of the Medipix3RX bottom periphery
5.1 Medipix3RX IO and Power Pads All the data communication to/from the chip is done at the bottom periphery using LVDS (Low Voltage Differential Signaling) technology (see 5.1.1). There are also 3 analog IO pads in the chip. Table 9 summarizes the list of digital and analog IOs. The position of the IO pads is found in Table 11. The chip is connected to the readout system either by using standard wire bond pads (see 3.1) or through silicon via (see 3.2 ). Table 10. List and description of the IO pads.
Name
Signal I/O Type
#
EnableIn
LVDS
I
2
ClkIn
LVDS
I
2
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Description Clocked with rising edge of ClkIn 0: Data transfer operations are allowed 1: No Data transfer operations are allowed Input clock. Maximum frequency ~350 MHz (simulated)
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Medipix3RX manual
DataIn
LVDS
I
2
EnableOut
LVDS
O
2
ClkOut
LVDS
O
2
DataOut[0..7]
LVDS
O
16
Reset
LVDS
I
2
Shutter
LVDS
I
2
CounterSelCRW
LVDS
I
2
MatrixFastClear
LVDS
I
2
TP_Switch
LVDS
I
2
DAC_OUT EXTDAC_IN EXT_BG_IN
Analog Analog Analog
O I I
1 1 1
Input Data. Clocked with rising edge of ClkIn. Clocked with the falling edge of ClkOut At falling edge: Indicated end of data transfer operation or Matrix Fast Reset Output clock. Inverted from ClkIn with an internal delay of ~4ns (simulated) Output data port. The number of data port is configurable through the PS[0:1] OMR bits (see Table 24) Clocked with rising edge of ClkIn. Top priority command. 0: DACs and internal logic are reset; 1: Idle state. Clocked with rising edge of ClkIn. Controls the acquisition time in Sequential and Continuous Read Write modes (see 7.7). 0: Acquisition ON 1: Acquisition OFF Clocked with the rising edge of ClkIn. Used to select CounterL and CounterH alternately in Continuous Read Write mode. Clocked with the rising edge of ClkIn. 0: Reset of the pixel matrix command is started (see 7.6.3) 1: idle state. Asynchronous Signal Test pulse switching signal Analog buffered output. Output Range= 0..1.5V External DAC input. Input Range=0 ... 1V External Band-Gap input. Input Range=0 ... 1V
The Medipix3RX chip has 4 different power domains. The power pads used are from the “ShortIO IBM library”. ESD clamps are present in every power/ground cell. Table 10 summarizes the 4 power domains with number of pads in both connectivity modes (WB or TSV). The position of the WB and TSV of the power and ground pads is found in Table 11. Table 11. Medipix3RX bottom periphery power/ground pads.
Power Domain Analog 1.5V Analog 3.3V Digital 1.5V Digital 2.5V
Pads name
V
# of ARTISAN cells
# WB pads bottom
# TSV pads bottom
VDDA
1.5 V
31
16
16
GNDA VDDA_33
0V 3.3 V
36 4
19 2
22 2
VDD
1.5 V
19
10
10
GND
0V
24
12
13
DVDD
2.5 V
12
6
6
DGND
0V
12
6
6
Usage Active area Periphery (DACs) Periphery (e-fuses) Active area Periphery (core logic) Periphery (IO drivers)
Table 12. IO pad and power/ground pads locations from the chip origin (bottom left corner) to the center of the Wire Bonding (WB) pads and centre of the Through Silicon Via (TSV) pads at the bottom of the chip. There are 110 WB connections and 108 TSV connections at the bottom of the chip.
WB PADS GND EnableIn_PLUS EnableIn_MINUS DVDD DataIn_PLUS DataIn_MINUS
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X [µm] Y[µm] 263.5 373 446 555.5 665 738
164.5 164.5 164.5 164.5 164.5 164.5
TSV PADS GND EnableIn_PLUS EnableIn_MINUS DVDD DataIn_PLUS DataIn_MINUS
X[µm] Y[µm] 261.8 381.8 501.8 621.8 741.8 861.8
1256.8 1256.8 1256.8 1256.8 1256.8 1256.8
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Medipix3RX manual
VDD ClockIn_PLUS ClockIn_MINUS DGND GNDA GNDA VDDA VDDA GND Reset_PLUS Reset_MINUS DVDD Shutter_PLUS Shutter_MINUS VDD CounterSelCRW_PLUS CounterSelCRW_MINUS DGND MatrixFastClear_PLUS MatrixFastClear_MINUS GND VDDA_33 VDDA_33 GNDA GNDA GNDA GNDA VDDA VDDA GNDA GNDA GNDA VDDA VDDA GND VDD GND VDD VDD DVDD DGND GND GND VDD VDD GNDA GNDA VDDA VDDA DAC_OUT GNDA GNDA EXT_BGIN VDDA VDDA EXT_DACIn GNDA GNDA
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847.5 957 1030 1139.5 1358.5 1504.5 1650.5 1796.5 2015.5 2125 2198 2307.5 2417 2490 2599.5 2709 2782 2891.5 3001 3074 3183.5 3402.5 3548.5 3694.5 3840.5 4059.5 4205.5 4351.5 4497.5 4607 4716.5 4862.5 5008.5 5154.5 5373.5 5519.5 5665.5 5811.5 5957.5 6103.5 6249.5 6395.5 6541.5 6687.5 6797 6979.5 7125.5 7271.5 7381 7454 7563.5 7673 7746 7855.5 8001.5 8111 8220.5 8366.5
164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5
VDD ClockIn_PLUS ClockIn_MINUS DGND GNDA GNDA VDDA VDDA GND Reset_PLUS Reset_MINUS DVDD Shutter_PLUS Shutter_MINUS VDD CounterSelCRW_PLUS CounterSelCRW_MINUS DGND MatrixFastClear_PLUS MatrixFastClear_MINUS GND VDDA_33 VDDA_33 GNDA GNDA GNDA GNDA GNDA VDDA VDDA VDDA GNDA GNDA GNDA VDDA VDDA GND GND GND GND VDD VDD VDD DVDD DGND GND GND GND VDD VDD GNDA GNDA VDDA VDDA DAC_OUT EXT_BGIN EXT_DACIn VDDA
981.8 1101.8 1221.8 1341.8 1461.8 1581.8 1701.8 1821.8 1941.8 2061.8 2181.8 2301.8 2421.8 2541.8 2661.8 2781.8 2901.8 3021.8 3141.8 3261.8 3381.8 3501.8 3621.8 3741.8 3861.8 3981.8 4101.8 4221.8 4341.8 4461.8 4581.8 4701.8 4821.8 4941.8 5061.8 5181.8 5301.8 5421.8 5541.8 5661.8 5781.8 5901.8 6021.8 6141.8 6261.8 6381.8 6501.8 6621.8 6741.8 6861.8 6981.8 7101.8 7221.8 7341.8 7461.8 7581.8 7701.8 7821.8
1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1257.8 1258.8 1259.8 1260.8 1261.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8
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Medipix3RX manual
VDDA VDDA GND TP_Switch_PLUS TP_Switch_MINUS DGND DataOut7_PLUS DataOut7_MINUS VDD DataOut6_PLUS DataOut6_MINUS DVDD DataOut5_PLUS DataOut5_MINUS GND GNDA GNDA VDDA VDDA GND DataOut4_PLUS DataOut4_MINUS DGND DataOut3_PLUS DataOut3_MINUS VDD DataOut2_PLUS DataOut2_MINUS DVDD DataOut1_PLUS DataOut1_MINUS GND GNDA GNDA VDDA VDDA DGND EnableOut_PLUS EnableOut_MINUS VDD DataOut0_PLUS DataOut0_MINUS DVDD ClockOut_PLUS ClockOut_MINUS GND
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8512.5 8658.5 8877.5 8987 9060 9169.5 9279 9352 9461.5 9571 9644 9753.5 9863 9936 10045.5 10264.5 10410.5 10556.5 10702.5 10921.5 11031 11104 11213.5 11323 11396 11505.5 11615 11688 11797.5 11907 11980 12089.5 12308.5 12454.5 12600.5 12746.5 12965.5 13075 13148 13257.5 13367 13440 13549.5 13659 13732 13841.5
164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5 164.5
VDDA VDDA GNDA GNDA GNDA GNDA GNDA TP_Switch_PLUS TP_Switch_MINUS DGND DataOut7_PLUS DataOut7_MINUS VDD DataOut6_PLUS DataOut6_MINUS DVDD DataOut5_PLUS DataOut5_MINUS GND GNDA GNDA GNDA VDDA VDDA DataOut4_PLUS DataOut4_MINUS DGND DataOut3_PLUS DataOut3_MINUS VDD DataOut2_PLUS DataOut2_MINUS DVDD DataOut1_PLUS DataOut1_MINUS GND GNDA GNDA VDDA VDDA DGND EnableOut_PLUS EnableOut_MINUS VDD DataOut0_PLUS DataOut0_MINUS DVDD ClockOut_PLUS ClockOut_MINUS GND
7941.8 8061.8 8181.8 8301.8 8421.8 8541.8 8661.8 8781.8 8901.8 9021.8 9141.8 9261.8 9381.8 9501.8 9621.8 9741.8 9861.8 9981.8 10101.8 10221.8 10341.8 10461.8 10581.8 10701.8 10821.8 10941.8 11061.8 11181.8 11301.8 11421.8 11541.8 11661.8 11781.8 11901.8 12021.8 12141.8 12261.8 12381.8 12501.8 12621.8 12741.8 12861.8 12981.8 13101.8 13221.8 13341.8 13461.8 13581.8 13701.8 13821.8
1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8 1256.8
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Medipix3RX manual
5.1.1 Medipix3RX LVDS receiver and driver All the digital IO pads use the Low Voltage Differential Signaling technology. The chip includes 8 LVDS receivers and 10 LVDS drivers which are self-bias and are always on after the chip is powered on. The receivers do not include de 100 Ω termination resistors on -chip. This permits the multidrop topology which can connects one driver to several receivers by adding, outside chip, a 100 Ω termination resistor only at the farthest receiver from the driver as shown in Figure 12. In a typical multichip daisy-chain configuration Reset, Shutter, Shutter1_CounterSel, MatrixFastClear and TP_Switch can use a multidrop topology while EnableIn, DataIn and ClockIn should use a point-topoint topology (see Figure 13).
1 0 0
D
Ω
R
R
R
R
Figure 15. Multidrop LVDS bus configuration. D: LVDS Driver; R: LVDS Receiver.
1 0 0
D
Ω
R
Figure 16. Point-to-point LVDS bus configuration. D: LVDS Driver; R: LVDS Receiver.
Table 12 and Table 13 summarize the main characteristics of both LVDS receivers and LVDS drivers respectively. Table 13. LVDS receiver summary
Parameter
Value
Number of receivers Maximum operating frequency Power supplies Power consumption per channel Total power consumption (8 channels)
8 500 MHz DVDD = 2.5V // VDD = 1.5 V ~2 mW (800 µA) ~16 mW (6.40 mA)
Table 14. LVDS driver summary
Parameter VOUT Low VOUT High VOUT Common Number of drivers Maximum operating frequency
October 31, 2012
Value 1V 1.4 V 1.2 V 10 500 MHz
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Medipix3RX manual
Power supplies Power consumption per channel Maximum power consumption (8 DataOut ports used) Minimum power consumption (1 DataOut port used)
DVDD = 2.5V // VDD = 1.5 V Output connected: ~11.25 mW (4.5 mA) Output pins floating: ~1.25 mW (500µA) ~112.5 mW (45 mA) ~42.5 mW (17 mA)
5.1.2 Medipix3RX IO Analog pads There are two input and one output analog pads as shown in Table 9: • The input pads ExtDAC_IN and ExtBG_IN inputs are ESD protected by a series resistance of 250 Ω. The output analog pad is based in the same cell as one the test pulse circuit (see Table • 16) since the driving capabilities needed in both circuits are similar. The DAC_OUT pad output voltage shows then a ±1% linear range between ~325 and 1250 mV.
5.2 Medipix3RX IO Logic The Medipix3RX IO Logic has been synthesized using the IBM CMOS8RF CERN Digital Library. The IO Logic includes one on-chip a ~1 nF decoupling capacitance between VDD/GND.
5.3 Medipix3RX Analog Periphery The analog periphery contains and it is powered through VDDA and GNDA. Band-Gap circuitry • 10 9-bit and 17 8-bit DACs: • • Selection and monitoring logic
5.3.1 Band-Gap circuitry The Band-Gap circuitry is used to generate a stable voltage reference for the DACs. The forward voltage of one of its diodes is used to monitor the temperature variation on-chip. A simulation of this circuit is shown in Figure 14 which shows a ~1.6 mV/ºC temperature dependent slope. The on-chip Medipix3RX temperature is calculated by measuring the Band_Gap Temperature (DAC Code 27) and the Band_Gap Output (DAC Code 26) internal monitoring voltages (see Table 16). From simulations the slope and offset has been extracted as:
3 = 88.75 − 607.3 ∗ ( − )
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Medipix3RX manual
100
y = 1.0555x + 24.173 R² = 0.9999
80 ] C º [ 3 x i p i d e M p m e T
60 40 20 0 -20
-60
-40
-20
0
20
40
60
-40 -60
Temp In Climate Chamber [ºC]
Figure 17. Measure of the Medipix3RX on-chip temperature sensor in a climatic chamber. The measurement is linear in the range of temperatures.
The Band-gap can be overdriven using the external reference voltage EXTBG_IN if the ExtBGSel OMR bit is set to 1 (see Table 24).
5.3.2 Medipix3RX DACs These digital-to-analog converters are used to set the different bias conditions and references used in the chip. Table 14 summarizes the 27 on-chip DACs. The voltage DACs are linear between 0 and 1.275 V. All the DAC output stages are buffered with a unitary gain buffer. The Medipix3RX chip includes two special DACs (I_Shaper_test and I_DAC_test) for test use. The I_Shaper_test DAC is identical as the I_Shaper DAC and I_DAC_test is identical as I_DAC_DiscL and I_DAC_DiscH DACs. Unlike the regular ones these special DACs have their output not connected to the pixel matrix. Table 15. Medipix3RX DACs.
e m a N C A D
Threshold[0] Threshold[1] Threshold[2] Threshold[3] Threshold[4] Threshold[5] Threshold[6] Threshold[7] I_Preamp I_Ikrum I_Shaper I_Disc I_Disc_LS
e d o C C A D
r e > t B s i S g M e : R B C S A L D <
00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101
<30:38> <39:47> <48:56> <57:65> <66:74> <75:83> <84:92> <93:101> <102:109> <110:117> <118:125> <126:133> <134:141>
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] s t i b [ h t g n e L
e g n a R C A D
) e t g e s n e e a u R R l a r e d i V f t M A (
p e t S C A D
e g n ] a V R 1 C o A t D 0 t [ x E
9
0 to 2.04 µA SHGM: 0..10.4 KeHGM: 0..19.6 KeLGM: 0..28.6 KeSLGM: 0..37.8 Ke-
1.024 µA (1.05 V) SHGM: 5.2 KeHGM: 9.8 KeLGM: 14.3 KeSLGM: 18.9 Ke-
4 nA SHGM: 20 eHGM: 38 eLGM: 56 eSLGM: 74 e-
2 µA/V SHGM: 10 Ke-/V HGM: 19 Ke-/V LGM: 28 Ke-/V SLGM: 38 Ke-/V
8 8 8 8 8
0 to 5.1 µA 0 to 60 nA 0 to 1.02 µA 0 to 2.04 µA 0 to 1.02 µA
2.56 µA (355 mV) 30 nA (970 mV) 512 nA (1.03 V) 1.024 µA (0.84 V) 512 nA (270 mV)
20 nA 234 pA 4 nA 8 nA 4 nA
1 V/V 1 V/V 1 V/V 1 V/V 1 V/V
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Medipix3RX manual
I_Shaper_test I_DAC_DiscL I_DAC_test I_DAC_DiscH I_Delay I_TP_BufferIn I_TP_BufferOut V_Rpz V_Gnd V_Tp_ref V_Fbk V_Cas V_Tp_refA V_Tp_refB
01110 01111 11110 11111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001
<142:149> <150:157> <158:165> <166:173> <174:181> <182:189> <190:197> <198:205> <206:213> <214:221> <222:229> <230:237> <238:246> <247:255>
8 8 8 8 8 8 8 8 8 8 8 8 9 9
0 to 1.02 µA 0 to 48 nA 0 to 48 nA 0 to 48 nA 0 to 204 nA 0 to 10.2 µA 0 to 255 µA 0 to 1.5 V 0 to 1.275 V 0 to 1.275 V 0 to 1.275 V 0 to 1.275 V 0 to 1.275 V 0 to 1.275 V
512 nA (1.03 V) 24 nA (1.25 V) 24 nA (1.25 V) 24 nA (1.25 V) 102.4nA (1.02 V) 5.12 µA (1.12 V) 128 µA (1.04 V) 640 mV 640 mV 640 mV 640 mV 640 mV 640 mV 640 mV
4 nA 187 pA 187 pA 187 pA 800 pA 40 nA 1 µA 5 mV 5 mV 5 mV 5 mV 5 mV 2.5 mV 2.5 mV
1 V/V 48 nA/V 48 nA/V 48 nA/V 1 V/V 1 V/V 1 V/V 1 V/V 1 V/V 1 V/V 1 V/V 1 V/V 1 V/V 1 V/V
5.3.3 Selection and monitoring logic Each DAC can be monitored (through DAC_Out ) by selecting the DAC code (see Table 14) in the SenseDAC[0:4] OMR bits (see Table 24). Four other internal signals can be observed (see Table 15) through the DAC_OUT pad by using the appropriate selection code in the SenseDAC[0:4] OMR bits. Table 16. Internal monitoring signals selection code and simulated value.
Monitoring signal Name
Selection Code
Simulated value
Band_Gap Output
11010
637 mV
Band_Gap Temperature
11011
See Figure
DAC Bias DAC cascode bias
11100 11101
1.16 V 950 mV
14
An external input voltage through EXTDAC_IN can be used to by-pass any of the internal DACs. The selection of the DAC is done by putting in the ExtDAC[0:4] OMR bits the code of the DAC to be by-passed. The range in current and in voltage for each DAC is also available in Table 14.
5.4 Test Pulse For each pixel column test pulse circuitry there are generated 2 independent outputs in order to electrically test and calibrate the charge summing circuit correctly. A schematic of a pixel column test pulse with two outputs (TP_1 and TP_2) is shown in Figure 18. The test pulse amplitude is generated by multiplexing the V_Tp_refA and V_Tp_ref analog voltages to produce the test pulse TP_1 with a switching frequency controlled by the IO input TP_SWITCH. TP_2 is generated in the same way by mixing V_Tp_refB and V_Tp_ref. V_Tp_refA, V_Tp_refB and V_Tp_ref are on-chip DACs described in Table 14. A unitary gain buffer, which bias settings are controlled by TP_BufferIn and TP_BufferOut on-chip DACs, sends the signal to the pixel column.
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V_Tp_refA 1
TP_1
1
TP_2
V_Tp_ref V_Tp_refB
TP_SWITCH Figure 18. Pixel column test pulse schematic.
At default DAC settings each pixel column test pulse circuit consumes ~500 µA. When all test pulse circuits are active simultaneously the total power consumption is then 128 mA. To minimize the power consumption each of the 256 test pulse circuits can be enabled/disabled independently using the set CTPR command (see 8.4.2). When a circuit is disabled the unitary gain buffer is switched off and the power consumption is then negligible. Table 16 summarizes the main characteristics of the pixel column test pulse circuit. After chip Reset all the Pixel column test pulse circuits are disabled (CTPR[0:255]=0). Table 17. Pixel column test pulse circuit summary
Parameter Channels per column Minimum step Linear dynamic range [± 1%] TP_REF min TP_REF max TP_REFA and TP_REFB min TP_REFA and TP_REFB max Typical Rise/Fall time Current consumption
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Value 2 2.5 mV → 86.2 e 925 mV → ~ 32 Ke 8’b0100_0001 → ~325 mV 8’b1111_1010 → ~1250 mV 9’b0_1000_0010 → ~312.5 mV 9’b1_1111_0100 → ~1250 mV < 50 ns CTPR bit enabled: ~500 µA @ default DAC values CTPR bit disabled: neglegible
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6 Medipix3RX power consumption (To be updated) The overall power consumption of the chip for each of the four different power domains is summarized in Table 19. Table 18. Summary of the overall Medipix3RX chip power consumption.
Max Current [mA]
Max Current @200MHz
Max Power @200MHz
V
Block name
Min Current [mA]
VDDA/GNDA
1.5
Periphery Active Area
0.583 400
1.338 662
664 mA
~1 W
VDDA33
3.3
E-fuse
10
13.5
13.5 mA
44.5 mW
VDD/GND
1.5
170 mA
255 mW
DVDD/DGND
2.5
51.4 mA
128.5 mW
Periphery (core)
~0.25 mA/MHz (average)
Active Area
~0.6 mA/MHz (average)
Periphery (IO)
23.4
51.4
6.1 Analog power consumption (VDDA/GNDA and VDDA33) The analog power consumption can be split into the analog periphery (see 5.3) and the active area (see 4) static power consumption. The recommended analog voltage supply (VDDA) is 1.5 V. The VDDA33 power supply (3.3 V) is only required during e-fuse burning process (see 8.4.5). During that process the power consumption at the burning time (see FusePulseint in Figure 17) will be between 33 and 44.5 mW.
6.1.1 Analog Periphery power consumption The analog power consumption in the periphery is detailed in Table 20. The minimum power consumption is 874 µW. This is reached when the ExtDACIN is set to 0V and all the DACs are set to their minimum digital value. The maximum power consumption is ~2 mW. This is achieved when the ExtDACIN is set to 1 V and all the DACs are set to their maximum digital value. Table 19. Detailed current consumption of the different blocks contained in the Medipix3RX analog periphery.
Min [µA] Band-Gap DAC-Bias ExtDACIN Threshold[0:7] Preamp Ikrum Shaper Disc Disc_LS ThresholdN DAC_pixel Delay TP_BufferIn TP_BufferOut RPZ
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150 50 25 164 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2
Max [µA] 150 50 350 180 10.2 11.2 11.2 12.2 10.2 10.2 11.2 11.2 20.4 265.2 30.6
Min [µW] 225 75 37.5 246 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3
Max [µW] 225 75 525 270 15.3 16.8 16.8 18.3 15.3 15.3 16.8 16.8 30.6 397.8 45.9
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GND TP_REF FBK Cas TP_REFA TP_REFB
10.2 10.2 10.2 10.2 20.5 20.5
30.6 30.6 30.6 30.6 41 41
15.3 15.3 15.3 15.3 30.75 30.75
45.9 45.9 45.9 45.9 61.5 61.5
TOTAL
583
1338.2
874.5
2007.3
6.1.2 Active Area analog power consumption The analog power consumption in the active area depends on the operation mode selected. At nominal conditions (see Table 6, Table 7 and Table 8) the pixel analog current consumption can vary from 6.1 µA in Single Pixel Mode (SPM see Table 5) to 10.1 µA in Colour Mode in Charge Summing Mode (Colour Mode in CSM see Table 5). Table 21 shows the total analog power consumption of the full pixel matrix in the SPM and the Colour Mode in CSM modes. Table 20. Minimum and maximum analog power consumption of the Medipix3RX active area.
SPM (1 pixel) Colour Mode in CSM (1 pixel)
Current Consumption 6.1 µA 10.1 µA
Power Consumption 9.1 µW 15.1 µW
400 mA 662 mA
600 mW 1W
Single pixel Mode (256 x 256 pixels) Colour Mode in CSM (256 x 256 pixels)
6.2 Digital power consumption (VDD/GND DVDD/DGND) Two digital power domains exist in the chip: • The VDD/GND is used for the IO core logic and the pixel matrix digital part. The recommended operation supply voltage is 1.5 V. • The DVDD/DGND is used for the IO LVDS drivers and receivers. The recommended operation supply voltage is 2.5V. The power consumption of this block has already been discussed in 5.1.1.
6.2.1 Digital periphery power consumption The digital power consumption in the periphery is dominated by the IO core logic and the 256 end of column blocks which are powered with VDD/GND, and the LVDS receivers/drivers which are powered with DVDD/DGND. Table 22 gives a worst case estimation of the VDD/GND periphery power consumption at different clock frequencies. Since the average power consumption is proportional to the frequency it can be expressed as ~0.25 mA/MHz. Table 21. Digital power consumption in the Medipix3RX periphery. The values are obtained with the E ncounter® Power Analysis tool in statistical mode with a 50% net toggle probability.
Readout clock frequency 350 MHz 200 MHz 100 MHz
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Average power 120 mW 70 mW 35 mW
Worst IR drop 9.1 mV 5.2 mV 2.6 mV
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6.2.2 Active area digital power consumption Extensive analog simulations of the complete digital part of one pixel have been carried out in order to estimate the average digital power consumption during the readout at different clock frequencies. The simulated average digital current consumption in one pixel is ~9nA/MHz. The full pixel matrix current consumption is then ~0.6 mA/MHz as shown in Table 19.
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7 Medipix3RX Operation 7.1 Main guidelines for the chip operation •
• •
Reset, DataIn, EnableIn, MatrixFastReset, Shutter and CounterSelCRW, are sampled at the rising edge of ClkIn. DataOut[0:7] and EnableOut are set at the falling edge of ClkOut . Signal priority is: 1) Reset : Chip Reset (see 7.2). 2) MatrixFastReset : Reset of the pixel counters (see 7.6.3). 3) EnableIn: Enables chip communication.
7.2 Chip Reset When the Reset IO input is set low the chip will be reset on the rising edge of ClkIn. At this moment all the internal state machines are initialized, the DACs are set to the default value (see Table 14), all the CTPR bits are disabled (see 5.4) and the OMR bits are set to 0 except the polarity bit which is set to 1. This operation has priority over all other operations/commands.
7.3 Chip Control Modes The chip has three main operation modes: 1) Load OMR: Loads the 32-bit Operation Mode Register (OMR) which configures the following operation type into the chip. 2) Start Operation: With this command the previously loaded operation (Load OMR) is executed for example: Load DACs, Read DACs, Load Matrix, Read matrix, etc. 3) E-fuse burning: Stand-alone operation used to burn the E-fuses used for chip identification. The three control modes are distinguished by a 4-bit header word which must be included in all communication to the chip once EnableIn is low: 1100LSB: Load Operation Mode Register (OMR) 0101LSB: Operation execution 0010LSB: E-fuse burning The Medipix3RX IO logic includes a state machine which continuously looks for any of these sequences at the input if the chip is requested to start a command ( EnableIn goes Low and EnableOut is High).
7.4 Operation Mode Register (OMR) A 48-bit register controls the chip operation mode. This register must be loaded serially before executing a new operation. The OMR bit position is shown in Table 23. The description of the OMR bits is explained in Table 24. After Reset (see 8.1) all the OMR bits are set to zero but Polarity bit is set to 1. The OMR register can only be changed after a chip Reset or after loading a new OMR. The contents of the OMR register can be readout using the Read OMR and e-fuseID operation (see 8.4.4).
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Table 22. Bit position in the 48-bit OMR.
B0
B1
B2
B3
B4
0 M
1 M
2 M
W y t R i S r _ l a W o P R C
B16
B17
B18
B19
B20
] 1 [ k c o l B w o R
] 2 [ k c o l B w o R
l e S k c o l B w o R
n o i t a z i l a u q E
e d o M r u o l o C
B32 ] 4 [ h t d i W e s l u P e s u F
B33 ] 5 [ h t d i W e s l u P e s u F
B34 ] 6 [ h t d i W e s l u P e s u F
B35
B36
B5
B6
B7
B8
B9
B10
M P P S T _ _ e M l S b C a _ n c E s i D
] 0 [ L t n u o C
] 1 [ L t n u o C
B11
B14 l ] ] ] e 0 [ 1 [ 2 [ S k k k c c c k c o l o l o l o l B B B B n n n n m m m m u l u l u l u l o o o o C C C C
B15
] 0 [ S P
] 1 [ S P
B21
B22
B23
B24
B25
B26
B27
r e M d P a S e _ H M f o S n C I
] 0 [ l e S e s u F
] 1 [ l e S e s u F
] 2 [ l e S e s u F
] 3 [ l e S e s u F
] 4 [ l e S e s u F
B41
B42
B43
B37
B38
B39
B40
] ] 0 [ 1 ] 0 [ [ e e C d d A o o D M M e s n n n i i e a a G G S
] 1 [ C A D e s n e S
] 2 [ C A D e s n e S
] 3 [ C A D e s n e S
] 4 [ C A D e s n e S
] 0 [ C A D t x E
] 1 [ C A D t x E
B12
B13
B28
] 0 [ k c o l B w o R
B29 ] ] 1 0 [ [ h h t t d d i i W W e e s l s l u u P P e e s s u u F F
B30 ] 2 [ h t d i W e s l u P e s u F
B31 ] 3 [ h t d i W e s l u P e s u F
B44
B46
B47
] 2 [ C A D t x E
B45 ] 3 [ C A D t x E
] 4 [ C A D t x E
l e S G B t x E
Table 23. OMR bits description. Default column shows the bit value after chip Reset.
Name
Bits
Default
0:2
000
CRW_SRW
3
0
Polarity
4
1
PS[0:1]
5:6
00
M[0:2]
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Description Operation mode selection: 000: Read CounterL 001: Read CounterH 010: Load CounterL 011: Load CounterH 100: Load DACs 101: Load CTPR 110: Read DACs 111: Read OMR and ChipID 0:Sequential Read Write 1:Continuous Read Write 0: Electron collection mode 1: Holes collection mode 00: DataOut[0] 10: DataOut[0..1] 01: DataOut[0..3]
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Disc_CSM_SPM
7
0
Enable_TP
8
0
CountL[0:1]
9:10
00
ColumnBlock[0:2]
11:13
000
14
0
15:17
000
RowBlockSel
18
0
Equalization
19
0
ColourMode
20
0
CSM_SPM
21
0
InfoHeader
22
0
FuseSel[0:4]
23:27
000000
ColumnBlockSel
RowBlock[0:2]
FusePulseWidth[0:6]
28:34
0000000
GainMode[0:1]
35:36
00
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11: DataOut[0..7] Selects which Discriminator output is used during the 24-bit mode, CRW or Equalization operation modes 0: Selects DiscL 1: Selects DiscH 1: Enable internal Test pulse 0: Disable external Test pulse Selects the counter depth: 00: 2x 1-bit 10: 2x 6-bit 01: 2x 12-bit 11: 1x24 bit Selects the matrix columns to be readout if ColumnBlockSel is high 000 100 010 110 See 7.6.2.1 001 101 011 111 0: All columns are read out 1: Matrix columns selected by ColumnBlock[0:2] are read out Selects the matrix rows to be readout if RowBlockSel is high. See 7.6.2.1. 000: Row [0] 100: Row [0:1] 010: Row [0:3] 110: Row [0:7] 001: Row [0:15] 101: Row [0:31] 011: Row [0:63] 111: Row [0:127] 0: All rows are read out 1: Matrix rows selected by RowBlock[0:2] are read out Selects if the chip is in Threshold Equalization Mode (see chapter 8.4) 0: Equalization OFF 1: Equalization ON 0: Fine Pitch Mode (55μm x 55μm) 1: Spectroscopic Mode (110μm x 110μm) 0: Single Pixel Mode 1: Charge Summing Mode 0: No Info header added 1: Info header (OMR bits + chip ID) added before the DataOut stream in Data_Out[0] Selects Fuse to be burned Set the programming pulse width t o burn the selected e-fuse 0000_000: No pulse 1000_000: 1024 clocks width 1111_111: 523264 clocks width 00: Super-High Gain Mode (SHGM) 10: High Gain Mode (HGM)
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SenseDAC[0:4] ExtDAC[0:4] ExtBGSel
37:41 42:46
0_0000 0_0000
47
0
01: Low Gain Mode (LGM) 11: Super-Low Gain Mode (SLGM) Selects DAC to be sensed through DACOUT pin Selects DAC to be externally imposed through EXTDAC pin 0: Internal Band-Gap is used 1: External Band-Gap used through EXTBG pin
Figure 16 shows how the OMR is loaded for a single chip. This operation can be also daisy chained with multiple chips. For a single chip this operation need 80 data bits: 16 pre-sync, 48-bit OMR and 16 post-sync.
Reset EnableIn 80 bits
0011 12’bX
DataIn
OMR[0:47]
PreSync
16’bX PostSync
ClkIn ClkOut 0011
DataOut[0] EnableOut
Figure 19. Load Operation Mode Register time diagram.
7.5 Periphery operations There are 4 commands that only affect the Medipix3RX periphery. All these commands have the same length of 288 Tclk (16 PreSync, 256 data input or output bits and 16 PostSync). The first 3 bits of the OMR (M0, M1 and M2) selects each command: • • • •
Load DACs (M012=001) Load CTPR (M012=101) Read DACs (M012=110) Read OMR and E-fuseID (M012=111)
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7.5.1 Load DACs (M 012=100) The chip includes 25 DACs used to set different bias conditions. All These DACs can be set using this command. The position of each DAC inside this 256-bit register is shown in Table 14.
Reset EnableIn DataIn
OMR: M012 =b100
1010 12’bX
256-bits
PreSync
DataOut[0]
0011
16’bX PostSync
1010
226-bits: DAC Register[255:30] (see Table 14)
30’bX
ClkIn ClkOut EnableOut
7.5.2 Load CTPR (M 012=101) This command loads a 256 bit register which is used to enable/disable the test pulse individually for each column (see 5.4). 0: Test pulse circuitry is disabled. 1: Enabled.
Reset EnableIn DataIn
OMR: M 012 =b101
1010 12’bX
256-bits
PreSync
DataOut[0]
0011
16’bX PostSync
1010
256-bits: CTPR Register[255:0]
ClkIn ClkOut EnableOut
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Medipix3RX manual
7.5.3 Read DACs (M 012=110) The digital value of each DAC can be read out using this command. A 256-bit register is readout. The data output channel is always DataOut[0]. The position of each DAC inside this 25 6-bit register is shown in Table 14.
Reset EnableIn DataIn DataOut[0]
1010 12’bX
OMR: M012 =b110
0011
1010 12’bX
256-bits
16’bX PostSync
PreSync
30’bX
226-bits: DAC Register[255:30] (see Table 14)
ClkIn ClkOut EnableOut 7.5.4 Read OMR and ChipID (M 012=111) The 48 OMR bits and the 32 e-fuseID bits are readout using this command. The data output channel is always DataOut[0].
Reset EnableIn DataIn DataOut[0]
OMR: M012 =b111
0011
1010 12’bX 1010 12’bX
256-bits
PostSync
PreSync
160’bX
E-fuse [0:31]
16’bX
16’bX
OMR[47:0]
ClkIn ClkOut EnableOut
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Medipix3RX manual
7.5.5 E-fuse burning The Medipx3 includes 32-bit e-fuse used to set a unique ID for each chip. E-fuses are made by electronically “burning” a salicided polysilicon strip. Before and after burning the resistance is changed from ~100 Ω to >5 KΩ. To program an e-fuse a high current of value 10 mA < Ion < 13.5 mA during > 0.18 ms and < 1.0 ms has to be set through a programming transistor powered at 3.3 V. The programming and reading of the e-fuses is embedded in the Medipix3RX IO logic. Only one e-fuse can be burned at a time. First an e-fuse is selected (FuseSel[0:4]) and the programming pulse width (FusePulseWidth[0:6]) is set by loading the OMR register (see Figure 19). The programming pulse width has to be selected appropriately depending on the clock period (Tclk):
0.00018/Tclk (low limit)< (FusePulseWidth[0:6]<<12) < 0.001/Tclk (top limit) Table 25 shows and example of the FusePulseWidth[0:6] OMR bits range depending on the clock period. Table 24. Example of FusePulseWidth range depending on the system readout clock.
Fclk 5 MHz 50 MHz 100 MHz 200 MHz 500 MHz
Tclk 200 ns 20 ns 10 ns 5 ns 2 ns
Low limit (FusePulseWidth[0:6]) 1000_000 0100_000 0010_000 0001_000 1010_100
Top limit (FusePulseWidth[0:6]) 1000_000 0011_000 0001_100 0000_110 0101_111
The fuse programming time diagram is shown in Figure 20.
Reset EnableIn DataIn
DataOut[0]
Load OMR
0011
0100 12’bX
16’bX
PreSync
PostSync
0100
EnableOut FuseSel FusePulseWidth
FuseSel[0:4] FusePulseWidth[0:6]
FusePulse (chip’s internal signal) Figure 20. Fuse programming time diagram. The
FusePulseint shows the internal programming pulse width.
Reading the e-fuses is done for all the 32 e-fuses simultaneously using the Read OMR and chipID (see 8.4.4). If an e-fuse is blown a 1 is read out otherwise the e-fuse gives a 0. A non-blown chip gives 32-bits at 0.
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7.6 Pixel Matrix operations There are basically 3 main pixel matrix operations: 1) Load Pixel Matrix configuration. 2) Read Pixel Matrix. 3) Fast pixel matrix reset.
7.6.1 Load Pixel Matrix Configuration (M 012=01x) This command loads the configuration bits in the pixel matrix. There are 13 configuration bits per pixel to be set (see Table 4) which are set by shifting data in both counters/registers. To load completely the 13 configuration bits this operation has to be repeated twice with M 2 = 0 to load counterL and M2 = 1 to load counterH.
Reset EnableIn DataIn
OMR: M012=3’b01X
0 : Set bits CounterL 1 : Set bits CounterH
1010 12’bX
786432-bits
256’bX
16’bX PostSync
PreSync
EnableOut
] ] ] 0 , 0 , 0 , 5 4 3 5 5 5 2 [ 2 [ 2 [ n n n m m m u l u l u l o o o C C C l l l e e e x i x i x i P P P
] ] ] ] 1 , 1 , 0 , 0 , 5 4 1 0 5 5 [ [ 2 2 n n [ [ m m n n u l u m m l u l u o o l C C o o l l C C e e l l x i x e e i P P x i x i P P
] ] 1 1 7 7 0 0 3 , 3 , 1 [ 0 [ n n m m u l u l o o C C l l e e x i x i P P
First row sent Figure 21. Time diagram of the load pixel matrix command. Only the load of one counter is shown. The pixel column construction is shown in Figure 21.
The pixel columns are built by joining the 256 pixel shift registers (CounterL and CounterH). For example the B11 or B23 of pixel row 0 and column 255 corresponds to PixelColumn[255,0].
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Row 255→
→ CA:B0/CB:B12
Row 0 →
→ Row 3071
t i b 2 : 1 f o * 6 d 5 e 2 = m r r e o f t n e r u a o c s / n n m m u u l o l C o c l / s e t x i i P b 2 7 0 3
] ] 4 5 5 5 2 2 [ [ n n m m u u l l o o C C l l e e x i x i P P
] ] ] ] 0 1 2 3 [ [ [ [ n n n n m m m m u u u u l l l l o o o o C C C C l l l l e e e e x i x i x i x i P P P P
→ CA:B11/CB:B23
→ Row0
Figure 22. The pixel column is built by connecting together the 256 pixels shift registers. CA stands for CounterL and CB stands for CounterH.
7.6.2 Read Pixel Matrix (M 012=x00) The pixel matrix can be read in serial mode through DataOut[0] or in a configurable length LVDS parallel output port DataOut[0:7] controlled by the PS[0:1] bits in the OMR (see Table 24). In serial readout mode the chip can be daisy-chained by connecting the DataOut[0] to the DataIn of the following chip. The total data output stream length also depends on the setting of the pixel counter length which is set by the CountL[0:1] bits in the OMR. Table 26 summarizes the data output stream length for this mixture of settings. The pixel matrix counters are always reset at the end of a full matrix readout command. All Data readout commands can include a 256-bit information header if the InfoHeader OMR bit is set High(see Table 23). The Information header includes the 48-bit OMR and the ChipID as explained in the ReadOMR and ChipID operation command (see 7.5.4).
Table 25. Data output stream length for different settings of the PS[0:1] and CountL[0:1] O MR bits.
PS[0:1]
Mode
Daisy Chain
DataOut ports
00
Serial
Yes
DataOut[0]
10
Parallel 2 lines
No
DataOut[0:1]
01
Parallel 4 lines
No
DataOut[0:3]
11
Parallel 8 lines
No
DataOut[0:7]
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CountL[0:1]
00: 2x1-bit 10: 2x6-bits 01 : 2x12-bits 11: 1x24-bits 00: 2x1-bit 10: 2x6-bits 01 : 2x12-bits 11: 1x24-bits 00: 2x1-bit 10: 2x6-bits 01 : 2x12-bits 11: 1x24-bits 00: 2x1-bit 10: 2x6-bits 01 : 2x12-bits 11: 1x24-bits
DataOut stream length
[65536 bits] x 1 [393216 bits x 1 [786432 bits] x 1 [1572864 bits] x 1 [32768 bits] x 2 [196608 bits] x 2 [393216 bits] x 2 [786432 bits] x 2 [16384 bits] x 4 [98304 bits] x 4 [196608 bits] x 4 [393216 bits] x 4 [8192 bits] x 8 [49152 bits] x 8 [98304 bits] x 8 [196608 bits] x 8
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Medipix3RX manual
Reset
0 : Set bits CounterL 1 : Set bits CounterH
EnableIn DataIn
OMR: M 012=3’b00X
1010 12’bX
EnableOut
DataOut[0]
0011
PreSync
Data
PostSync
1010 12’bX
786432-bits
16’bX
] ] ] 0 , 0 , 0 , 5 4 3 5 5 5 2 [ 2 [ 2 [ n n n m m m u l u l u l o o o C C C l l l e e e x i x i x i P P P
] ] ] ] 1 , 1 , 0 0 , , 5 4 1 0 5 5 [ [ 2 2 n n [ [ m m n n u l u m m l u l u o o l C C o o l l C C e e l l x e i x i e x i x P P i P P
] ] 1 1 7 7 0 0 3 , 3 , 1 [ 0 [ n n m m u l u l o o C C l l e e x i x i P P
First row Recieved Figure 23. Data readout of the chip when programmed in serial mode (PS=00), counter length of 12 bits (CountL[0:1]=01) and without information header (InfoHeader=0).
Reset 0 : Set bits CounterL 1 : Set bits CounterH
EnableIn DataIn
OMR: M012=3’b00X
1010 12’bX
EnableOut
DataOut[0]
0011
160’bX
PreSync
InfoHeader
Data
PostSync
1010 12’bX
256-bits
786432-bits
16’bX
E-fuse [31:0]
16’bX
OMR[0:47]
] ] ] 0 , 0 , 0 , 5 4 3 5 5 5 2 [ 2 [ 2 [ n n n m m m u l u l u l o o o C C C l l l e e e x i x i x i P P P
] ] ] ] 1 , 1 , 0 , 0 , 5 4 1 [ 0 5 5 [ 2 2 n n [ [ m m n n u l u m m l u l u o o l C C o o l l C C e e l l x i x e e i x i x P P i P P
] ] 1 1 7 7 0 0 3 , 3 , 1 [ 0 [ n n m m u l u l o o C C l l e e x i x i P P
First row Recieved Figure 24. Data readout of the chip when programmed in serial mode (PS=00), counter length of 12 bits (CountL[0:1]=01) and with information header (InfoHeader=1).
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Reset
0 : Set bits CounterL 1 : Set bits CounterH
EnableIn DataIn
OMR: M012=3’b00X
1010 12’bX
EnableOut
DataOut[0]
0011
PreSync
Data
PostSync
1010 12’bX
393216-bits
16’bX
] ] ] 0 , 0 , 0 , 5 4 3 5 5 5 2 [ 2 [ 2 [ n n n m m m u l u l u l o o o C C C l l l e e e x i x i x i P P P
DataOut[1] ] ] ] 0 , 0 , 0 , 7 6 5 2 2 2 1 [ 1 [ 1 [ n n n m m m u l u l u l o o o C C C l l l e e e x i x i x i P P P
] ] ] ] 0 , 0 , 1 , 1 , 9 8 5 4 2 2 5 5 1 [ 1 [ 2 [ 2 [ n n n n m m m m u l u l u l u l o o o o C C C C l l l l e e e e x i x i x i x i P P P P
] ] 1 1 7 7 0 0 3 , 3 , 9 8 2 2 1 [ 1 [ n n m m u l u l o o C C l l e e x i x i P P
Data
PostSync
393216-bits
16’bX
] ] ] ] 1 , 1 , 0 , 0 , 7 6 1 0 2 2 [ [ 1 1 n n [ [ m m n n u l u m m l u l u o o l C C o o l l C C e e l l x i x i e e P P x i x i P P
] ] 1 1 7 7 0 0 3 , 3 , 1 0 [ [ n n m m u l u l o o C C l l e e x i x i P P
Figure 25. Data readout of the chip when programmed in 2-bit parallel mode (PS=01), counter length of 12 bits (CountL[0:1]=10) and without information header (InfoHeader=0). Notice that the synchronization header is only present in DataOut[0].
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Reset
0 : Set bits CounterL 1 : Set bits CounterH
EnableIn DataIn
OMR: M012=3’b00X
1010 12’bX
EnableOut
DataOut[0]
0011
PreSync
InfoHeader
Data
PostSync
1010 12’bX
256-bits
393216-bits
16’bX
] ] ] 0 , 0 , 0 , 5 4 3 5 5 5 2 [ 2 [ 2 [ n n n m m m u l u l u l o o o C C C l l l e e e x i x i x i P P P
DataOut[1] ] ] ] 0 , 0 , 0 , 7 6 5 2 2 2 1 [ 1 [ 1 [ n n n m m m u l u l u l o o o C C C l l l e e e x i x i x i P P P
] ] ] ] 0 , 0 , 1 , 1 , 9 8 5 4 2 2 5 5 1 [ 1 [ 2 [ 2 [ n n n n m m m m u l u l u l u l o o o o C C C C l l l l e e e e x i x i x i x i P P P P
] ] 1 1 7 7 0 0 3 , 3 , 9 8 2 2 1 [ 1 [ n n m m u l u l o o C C l l e e x i x i P P
Data
PostSync
393216-bits
16’bX
] ] ] ] 1 , 1 , 0 0 , , 7 6 1 0 2 2 [ [ 1 1 n n [ [ m m n n u l u m m l u l u o o l C C o o l l C C e e l l x e i x i e x i x P P i P P
] ] 1 1 7 7 0 0 3 , 3 , 1 [ 0 [ n n m m u l u l o o C C l l e e x i x i P P
Figure 26. Data readout of the chip when programmed in 2-bit parallel mode (PS=01), counter length of 12 bits (CountL[0:1]=10) and with information header (InfoHeader=1). Notice that the synchronization header and the information header are only present in DataOut[0].
7.6.2.1 Region of interest readout The pixel matrix can be also readout by region of interest. This is achieved by selecting a column block and/or a row block through the OMR bits before a readout command is started (see Figure 19). Figure 27 shows how the pixel matrix is split by column blocks, on the left, or by row blocks, on the right. The column blocks have a minimum width of 32 pixel columns and can be selected individually while the rows are always readout from the bottom and have a variable row block width. Each column block can be selected with a width of pixel columns of 32, 64, 128 or 256 columns. This selection is done through the PS[0:1], ColumnBlockSel and ColumnBlock[0:2] OMR bits. Table 27 summarizes the readout column block output width. When ColumnBlockSel is active all the output data goes through DataOut[0]. The number of readout rows can be selected through the RowBlockSel and RowBlock[0:2] OMR bits as shown in Table 24. Region readout is non-destructive: • The columns that haven’t been readout keep their value in all acquisition modes. The columns which have been readout shift the contents for the amount of rows • readout
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Table 26. Readout column selection to DataOut[0:7] versus the P S[0:1], ColumnBlockSel and ColumnBlock[0:2] OMR bits.
PS[0:1]
ColumnBlockSel
ColumnBlock[0:2]
Columns
DataOut[0:7]
00
X
XXX
0
XXX
1
XX1 XX0
0
XXX
1
X11 X01 X10 X00
0
XXX
1
111 011 101 001 110 010 100 000
Col[255:0] Col[255:128] Col[127:0] Col[255:128] Col[127:0] Col[255:192] Col[191:128] Col[127:64] Col[63:0] Col[255:192] Col[191:128] Col[127:64] Col[63:0] Col[255:224] Col[223:192] Col[191:160] Col[159:128] Col[127:96] Col[95:64] Col[63:32] Col[31:0] Col[255:224] Col[223:192] Col[191:160] Col[159:128] Col[127:96] Col[95:64] Col[63:32] Col[31:0]
DataOut[0] DataOut[0] DataOut[1] DataOut[0] DataOut[0] DataOut[0] DataOut[1] DataOut[2] DataOut[3] DataOut[0] DataOut[0] DataOut[0] DataOut[0] DataOut[0] DataOut[1] DataOut[2] DataOut[3] DataOut[4] DataOut[5] DataOut[6] DataOut[7] DataOut[0] DataOut[0] DataOut[0] DataOut[0] DataOut[0] DataOut[0] DataOut[0] DataOut[0]
10
01
11
Pixel Matrix size [X,Y] 256x256 256x256 128x256
256x256
64x256
256x256
32x256
Both selection modes can be combined together. Figure 28 shows an example of ROI readout. In this case one 32 pixel column block is selected (PS[0:1]=11 and ColumnBlockSel=1 and ColumnBlock[0:2]=010) and the first 64 rows (RowBlockSel=1 and RowBlock[0:2]=110). Only 2048 pixels will be readout following the same time protocol as in 7.6.2).
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] ] ] ] ] 9 1 3 5 ] ] 7 5 9 2 5 ] 3 5 2 1 : 1 : 2 : 2 : 1 6 9 1 : : : 8 0 2 4 3 : 2 4 6 2 6 9 2 0 3 [ 6 [ 9 [ 1 [ 1 [ 1 [ 2 [ [ n n n n n n n n m m m m m m m m u l u l u l u l u l u l u l u l o o o o o o o o C C C C C C C C = = = = = = = = 0 1 2 3 4 5 6 7 k k k k k k k k c c c c c c c c o l o l o l o l o l o l o l o l B l B l B l B l B l B l B l B l o o o o o o o o C C C C C C C C
Full Matrix = Row [0:255 ]
RowBlock7 = Row [0:127] RowBlock6= Row [0:63] RowBlock5 = Row [0:31] RowBlock4 = Row [0:15] RowBlock3 = Row [0:7] RowBlock2 = Row [0:3] RowBlock1 = Row [0:1] RowBlock0 = Row [0]
Bottom Periphery
Bottom Periphery
Figure 27. Schematic of the different pixel matrix regions of interest which can be readout independently. On the left the columns have a minimum width of 32 pixel columns and can be selected individually; on the right, the r ows, are always readout from the bottom.
Reset
0 : Set bits CounterL 1 : Set bits CounterH
EnableIn DataIn
OMR: M012=3’b00X
1010 12’bX
EnableOut
0011
DataOut[0]
] ] ] ] ] ] ] ] 1 3 5 7 9 1 3 5 5 9 2 5 3 : 6 : 9 : 2 1 1 : : 1 : 2 : 2 : 0 2 4 [ 3 6 6 8 2 4 n [ [ 9 2 0 6 9 2 1 [ 1 [ 1 [ 2 m n n [ u m m n [ l n n n n u l u m o l u m m m m C o o l u l u l u l u C C o l C o o o o C C C C a t a D
PreSync
Data
PostSync
1010 12’bX
24576-bits
16’bX
] ] ] 0 , 0 , 0 , 5 4 3 9 9 9 [ [ [ n n n m m m u l u l u l o o o C C C l l l e e e x i x i x i P P P
] ] ] ] 0 , 0 , 1 , 1 , 5 4 5 4 6 6 9 9 [ [ [ [ n n n n m m m m u l u l u l u l o o o o C C C C l l l l e e e e x i x i x i x i P P P P
] ] 7 7 6 6 7 , 7 , 5 4 6 6 [ [ n n m m u l u l o o C C l l e e x i x i P P
Bottom Periphery
Figure 28. Readout of a region of interest of 32 x 64 pixels progr ammed in 12-bit mode. The OMR settings are: CountL[0:1]=01, PS[0:1]=11, ColumnBlockSel=1, ColumnBlock[0:2]=010, RowBlockSel=1 and RowBlock[0:2]=011 and InfoHeader=0.
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7.6.3 Fast Pixel Matrix Reset The pixel matrix counter can be quickly reset (both pixel counters set at 12’b0000_0000_0000) using the IO input MatrixFastClear . The MatrixFastClear is synchronous to ClkIn. An internal state machine resets 6 bits of the pixel counter every time this operation is performed. To reset the full pixel counter this command has to be performed twice. After the MatrixFastClear pin is asserted low the first 6 bits of all pixel counters will be reset in 140 ClkIn cycles (Tclk). Once the operation is finished the EnableOut pin will acknowledge the end of operation by going low for 1 Tclk. A second command can be immediately started to reset the high 6-bits of the pixel counter. There are 2 ways to generate such command: 1) Generate two independent Fast Pixel Matrix Reset commands by asserting twice the MatrixFastClear pin as shown in Figure 29. 2) Generate one Fast Pixel Matrix Reset command by asserting once the MatrixFastClear pin and keeping it low until the first 6-bits are reset as shown in Figure 30Figure 29.
Reset Start of a Ma trix Reset (1): previous command (of any) is aborted Asserted >= 1 Tclk Low 6 bits of CounterL and CounterH are reset
Start of a Matrix Reset (2) Asserted >= 1 Tclk High 6 bits of CounterL and CounterH are reset
MatrixFastClear 140 Tclk
N Tclk
140 Tclk
ClkIn ClkOut EnableOut 1 Tclk
1 Tclk
Fast Matrix Reset Operation 2x141 Tclk + N Tclk =282 Tclk + N Tclk Figure 29. Example of a Fast Pixel Matrix Reset done by asserting the MatrixFastClear input signal twice. EnableIn is not needed for this high priority command.
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Reset Start of a Matrix Res et (1): previous command (of any) is aborted Asserted >= 1 Tclk Low 6 bits of CounterL and CounterH are reset
Start of a Matrix Reset (2) Asserted >= 1 Tclk High 6 bits of CounterL and CounterH are reset
MatrixFastClear 140 Tclk
140 Tclk
ClkIn ClkOut EnableOut 1 Tclk
1 Tclk
Fast Matrix Reset Operation 2x141 TClk =282 TClk Figure 30. Example of a Fast Pixel Matrix Reset done by asserting the MatrixFastClear input signal once. EnableIn is not needed for this high pr iority command.
7.7 Acquisition modes: Two different acquisition modes are implemented in the Medipix3RX. The control of these modes is done through the CRW_SRW OMR bit and the input pins Shutter and CounterSelCRW as shown in Table 27. •
Sequential Acquisition Mode (CRW_SRW=0): Shutter (see Table 9) controls the 2 pixel counters acquisition time simultaneously. When Shutter is active (low) the chip is in counting mode and when Shutter is not-active (high) both counters can be read out.
•
Continuous Read Write Acquisition Mode (CRW_SRW=1): Shutter sets the total acquisition time while CounterSelCRW controls which counter is read out. Table 27. CounterL and CounterH configuration in the different acquisition modes
Shutter
CRW_SRW
Not-Active (high) Active (low) Not-Active (high)
0 Sequential
Active (low)
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1 Continuous Read Write
CounterSelCRW CounterL X Readout X Counting X Readout 0 Counting 1 Readout
CounterH Readout Counting Readout Readout Counting
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Medipix3RX manual
7.7.1 Sequential Acquisition Mode Figure 31 shows a time diagram of one frame readout in full sequential mode. Figure 32 shows to consecutive acquisitions (counting and readout). In such a case if we only read from one counter the OMR has to be set only once.
Figure 31. Full sequential readout
Reset Shutter
Counting
Counting
EnableIn DataIn DataOut[0:7]
OMR: M012=3’b00X CRW=0
0011
1010 12’bX Data readout
1010 12’bX Data readout
EnableOut
Figure 32. Full sequential readout of two consecutive frames. Notice that the OMR has to be loaded only once at the beginning of the sequence.
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7.7.2 Continuous Read Write Acquisition Mode In CRW mode Shutter sets the total acquisition time while CounterSelCRW sets which of the pixel counters is counting or read out as shown in Table 27. Figure 33 shows a time diagram of the CRW mode acquisition and readout. The frequency of the CounterSelCRW has to be set appropriately to ensure that data is readout before toggling the counter selection to avoid data corruption. The last counting frame has to be readout separately doing a pixel matrix readout command (see 8.5.2). Reset Shutter
Acquisition time
Shutter1_CounterSel
Counting C1
Counting C0
Counting C1
Counting C0
EnableIn DataIn
OMR: M012=3’b00x CRW=1
DataOut[0:7]
0011
1010 12’bX
1010 12’bX
C1 readout
C0 readout
1010 12’bX C1 readout
OMR: M012=3’b000 CRW=0
0011
1010 12’bX C0 readout
EnableOut C1 Readout
Prohibited
Figure 33. Continuous Read Write time diagram.
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8 Appendix 8.1 Detailed Operation Mode Register table Table 28. Full Operation Mode Register (OMR) description table. This table is only valid for full pixel matrix (256 x 256) readout.
t e s e R
r a e l r C t e s t t a F u x h i S r t a M
W R C l e S r e t n u o C
W R C
0 M
1 M
] 1 : 0 2 [ L M t n u o C
1
] 1 : 0 [ S _ P
s e l c y c k c o l C
] s m [ e 1 z m H i t M t u 0 o 0 d 2 a e R
1 z
H M 0 0 2 @ s p f
h t p e D r e t n u o C
Function
0
X
X
X
X
X
X
X
X
X
Chip Reset
X
0
X
X
X
X
X
X
X
X
Pixel matrix Counter Reset
00 1
1
0
X
0
X
X
X
10 01 11
0 00 1 0 1
1
1
1
0
0
0
10 1 0 X1 1
1
1
0
e m a r F
1
0
0
X
00
X
10
X
01
1 bit 6 bit
X
00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11 00 10 01 11
Chip counting Sequential Mode
12 bit 24 bit 65536 32768 16384 8192 393216 196608 98304 49152 786432 393216 196608 98304 65536 32768 16384 8192 393216 196608 98304 49152 786432 393216 196608 98304 786432 786432
0.327 0.163 0.082 0.041 1.966 0.983 0.491 0.245 3.938 1.966 0.983 0.491 0.327 0.163 0.082 0.041 1.966 0.983 0.491 0.245 3.938 1.966 0.983 0.491 3.938 3.938
1
1
1
1
X
0
1
0 1
XX
XX
1
1
X
X
X
1
0
0 1
XX XX
XX XX
256 256
0.001
1
1
X
X
X
1
1
0 1
XX XX
XX XX
256 256
0.001
3051 6103 12207 24414 508 1017 2034 4069 254 508 1017 2034 3051 6103 12207 24414 508 1017 2034 4069 254 508 1017 2034
1bit
Read Out Sequential Mode
6 bit
12 bit
1x1 bit
1x6 bit
Continuous Read Write Mode (Clocks per Shutter)
1x12 bit 12 bit
Load Matrix Configuration Register Load DACs Registers Load CTPR Register Read DACs Read OMR and chipID
1
Without the pre and post synchronization bits and no information Header.
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8.2 Multi-chip Medipix3RX connection options A scheme of the Medipix3RX IO is shown in Figure 34. The chip when uses the full parallel port requires 18 LVDS pairs, 2 analog inputs (generated from DACs) and 1 analog output (to be connected to an ADC). 1 0 0
EnableIn
Ω
1 0 0
ClockIn
Ω
1 0 0
1 0 0
To Readout System
ClockOut
Datan
Ω
From Readout System
EnableOut
VDD/VSS DVDD/DVSS
DataOut[0:7]
Shutter
Ω
1 0 0
Shutter1_CounterSel
Ω
1 0 0
Reset
Ω
1 0 0
MatrixFastClear
Ω
1 0 0
TP_Switch
Ω
From DAC
ExtBG_In
From DAC
ExtDAC_In
DAC_Out
AVDD/AVSS
To ADC
Figure 34. Scheme of connection of 1 single Medipix3RX chip
In daisy-chain connection only DataOut[0] is connected to DataIn of the following chip. Only serial readout allowed. This configuration requires only 11 LVDS pairs for a multi-chip structure with N chips. Figure 35 shows a daisy-chain structure with 2 Medipix3RX chips. VDD/VSS DVDD/DVSS
n I e n I l b k a c o n l E C
l e S r e t n u o C _ r 1 r n e I e t t t t a t u u a h h D S S
AVDD/AVSS
r a e l C t s h a c F t x i t i r w S e s t _ e a P R M T
n I _ G B t x E
n I _ C A D t x E
VDD/VSS DVDD/DVSS
] 0 t t u t [ u t u O u e O O O l _ k b C a t c o a A a l n D D C E
VDD/VSS DVDD/DVSS
n I e n I l b k a c o n l E C 100 Ω
100 Ω 100 Ω
100 Ω
t u m o e m d t o s r F a e y R S
100 Ω
r n I e t t a t u a h D S
t e s e R
r h a c e t i l C w t s S _ a P F x T i r t a M
C C A A D D m m o o r F r F
C D A o T
AVDD/AVSS
r a e l C t s h a c F t x i t i r w S e s t _ e a P R M T
n I _ G B t x E
n I _ C A D t x E
VDD/VSS DVDD/DVSS
] 0 t t u t [ u t u O u e O O O l _ k b C a t c o a A a l n D D C E
100 Ω 100 Ω
r l e e t t S u r e t h S n u o C _ 1 r e t t u h S
l e S r e t n u o C _ 1 r e t t u h S
100 Ω
100 Ω
100 Ω
100 Ω
C C A A D D m m o o r F r F
t C u m D o e A o d T a t s o T e y R S
Figure 35. Scheme of a daisy-chain connection with 2 Medipix3RX chips
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51
Medipix3RX manual If a parallel readout with a multi-chip structure is desired there are 3 possible options. First a full parallel IO scheme (Figure 36) is shown where the 5 common (TP_Switch, Shutter, Shutter1_counterSel, Reset and MatrixFastClear ) are connected to all chips by means of a multi-drop connection. With this scheme the chips can be loaded and readout independently while Shutter and Reset are common to all chips. VDD/VSS DVDD/DVSS
n I e n I l b k a c o n l E C
100 Ω 100 Ω
l e S r e t n u o C _ r 1 r n e e I t t a t t t u u a h h D S S
AVDD/AVSS
r a e l C t s h a c F t x i t i r w S e s t _ e a P R M T
n I _ G B t x E
n I _ C A D t x E
VDD/VSS DVDD/DVSS
] 0 t t u t [ u t u u O e O O O l _ a k b c a C t o n A a l D D C E
100 Ω
t u m m o e t o d s r F a e y R S
r e t t u h S
l e S r e t n u o C _ 1 r e t t u h S
t e s e R
r h a c t e l i C w t s S_ a P F T x i r t a M
C C A A D D m m o o r F r F
t C u m D e A o o d t T o a s T e y R S
VDD/VSS DVDD/DVSS
n I e n I l b k a c o n l E C
r n e I t a t t u a h D S
l e S r e t n u o C _ 1 r e t t u h S
100 Ω 100 Ω
100 Ω 100 Ω
100 Ω
AVDD/AVSS
r a e l C t s h a c F t x i t i r w S e s t _ e a P R M T
100 Ω
100 Ω
n I _ G B t x E
n I _ C A D t x E
VDD/VSS DVDD/DVSS
] 0 t t u t [ u t u u O e O O O l _ a k b c a C t o n A a l D D C E
100 Ω
t u m m o e t o d s r F a e y R S
C C A A D D m m o o r F r F
t C u m D e A o o d t T o a s T e y R S
Figure 36. Scheme of a connection with 2 Medipix3RX chips working in full parallel IO readout.
The second option (Figure 37) is to set clock and data input in a multi-drop connection scheme. This configuration requires that the data loading to the different chips must be controlled by addressing only one chip at a time with the EnableIn signal. The data readout can be done in parallel for all the chips at the same time. VDD/VSS DVDD/DVSS
n I n e I l b k a c o n l E C
l e S r e t n u o C _ r 1 r n e e I t t t t a t u u a h h D S S
AVDD/AVSS
r a e l C t s h c a t F i i w t x r e t S s a _ e P R M T
n I _ G B t x E
n I _ C A D t x E
VDD/VSS DVDD/DVSS
] 0 t t u t [ u t u O e O u O l _ O k b C a t c a o A a l n D D C E
100 Ω
0 p i h c _ n I e l b a n E
n I k c o l C
n I a t a D
r e t t u h S
l e S r e t n u o C _ 1 r e t t u h S
t e s e R
r h a c t e l i C w t s S_ a P F T x i r t a M
C C A A D D m m o o r F r F
C D t A u m o o e T o T d s a t e y R S
VDD/VSS DVDD/DVSS
n I n e I l b k a c o n l E C
r n I e t t a t u a h D S
l e S r e t n u o C _ 1 r e t t u h S
100 Ω 100 Ω
100 Ω 100 Ω
100 Ω
1 p i h c _ n I e l b a n E
AVDD/AVSS
r a e l C t s h c a t F i i w t x r e t S s a _ e P R M T
100 Ω
100 Ω
n I _ G B t x E
n I _ C A D t x E
VDD/VSS DVDD/DVSS
] 0 t t u t [ u t u O e O u O l _ O k b C a t c a o A a l n D D C E
100 Ω
C C A A D D m m o o r F r F
C D t A u m o o e T o T d s a t e y R S
Figure 37. Scheme of a connection with 2 Medipix3RX chips working in serial input and parallel output readout.
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Medipix3RX manual
A third option is shown in Figure 38 which is similar to the previous option but with only 1 output clock common to all the chips. This option can be problematic if there is a significant skew between the data output and the common readout output clock. VDD/VSS DVDD/DVSS
n I n e I l b k a c o n l E C
l e S r e t n u o C _ r 1 r n e e I t t t t a t u u a h h D S S
AVDD/AVSS
r a e l C t s h a c t F i i w t x r S e t s a _ e P R M T
n I _ G B t x E
n I _ C A D t x E
VDD/VSS DVDD/DVSS
] 0 t t u t [ u t u O e O u O _ O k l b C a t c o a A a l n D D C E
100 Ω
0 p i h c _ n I e l b a n E
n I k c o l C
n I a t a D
r e t t u h S
l e S r e t n u o C _ 1 r e t t u h S
t e s e R
r h a c t e l i C w t s S_ a P F T x i r t a M
C C A A D D m m o o r F r F
C D t A u m o o e T o T d s a t e y R S
VDD/VSS DVDD/DVSS
n I n e I l b k a c o n l E C
r n I e t t a t u a h D S
l e S r e t n u o C _ 1 r e t t u h S
100 Ω 100 Ω
100 Ω 100 Ω
100 Ω
AVDD/AVSS
r a e l C t s h a c t F i i w t x r S e t s a _ e P R M T
100 Ω
1 p i h c _ n I e l b a n E
100 Ω
n I _ G B t x E
n I _ C A D t x E
VDD/VSS DVDD/DVSS
] 0 t t u t [ u t u O e O u O _ O k l b C a t c o a A a l n D D C E
100 Ω
C C A A D D m m o o r F r F
C D t A u m o o e T o T d s a t e y R S
Figure 38. Scheme of a connection of 2 Medipix3RX chips connected in serial input and parallel output readout mode with one common output clock.
Table 29 shows a summary of the different connection possibilities of the Medipix3RX as single chip or as a multi-chip structure. The number of LVDS pairs and time to readout a full frame are shown. Table 29. Summary of the Medipix3RX connectivity. “Parallel Oc_clk” stands for: Parallel output common readout clock.
1 1 to N
DataOut port 1 to 8 1
N
1
N
2
N
4
N
8
#of Chips
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Connection Type Single chip full parallel IO Daisy chain Full parallel IO Parallel O Serial I Parallel Oc_clk Serial I Full parallel IO Parallel O Serial I Parallel Oc_clk Serial I Full parallel IO Parallel O Serial I Parallel Oc_clk Serial I Full parallel IO Parallel O Serial I Parallel Oc_clk Serial I
LVDS pairs 11 to 18 11 5+6*N 7+4*N 8+3*N 5+7*N 7+5*N 8+4*N 5+9*N 7+7*N 8+6*N 5+13*N 7+11*N 8+10*N
Readout time @ 200 MHz and full matrix 3.93 ms to 491 µs 3.93 ms * N 3.93 ms
1.96 ms
983 µs
491 µs
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Medipix3RX manual
8.3 Recommended PCB layout power distribution for a single Medipix3 1.5V
DVDD
AVDD = 1.5 V
VDD
2k Ω
AVDD
1.5V
m m 1
AVSS/VSS/DVSS
m m 1
AVSS/VSS/DVSS
VDD = 1.5 V
2k Ω
2.5V
DVDD = 2.5 V
4kΩ
AVDD VDD DVDD
IO’s
Component List VHDCI Connector LDO Regulator LFD Capacitors HFD Capacitors HFD Capacitors Resistance Resistance Resistance Resistance Resistance
Value
#
Part number
Package
1
0714300006
3
MAX8556
Through Hole THIN QFN
10 µF ± 10%
12
JMK212BJ106KD-T
0805
10 nF ± 10%
9
04023C103KAT2A
0402
100 nF ± 10%
12
C0402C104K4RAC
0402
1 kΩ ± 0.1%
3 2 1 3 8
PCF0402-R-1K-B-T1 PCF0402-R-2K-B-T1 CRCW04024K02FKED 0402WGF1003TCE 0402WGF1000TCE
0402 0402 0402 0402 0402
2 kΩ ± 0.1% 4 kΩ ± 1% 100 kΩ ± 1% 100 Ω ± 1%
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Cost
Cost
10 €
10 €
2€ 0.078 €
6€ 1€
0.084 €
0.8 €
0.021 €
0.3 €
1.02 € 0.74 € 0.012 € 0.04 € 0.04 €
3€ 1.5 € 0.012 € 0.12 € 0.32 €
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Medipix3RX manual
Resistance HV Capacitor HV
100KΩ [150V] 10nF [500V]
1 1
CRCW0805100KFKEA 222297015636
0805 0805
0.034 € 0.2 €
0.034 € 0.2 €
<25 €
TOTAL
The proposed scheme uses 2 external power supplies: VL = 1.8 V and VH = 3.3 V which can be generated from a switch power supply. This scheme is targeted to supply efficiently up to 4 Medipix3RX chips. There are 3 ultra-low-input voltage LDO regulators (MAX8556) which efficiently convert VL into VDDA (1.5 V) and VDD (1.5 V) and VH into DVDD (2.5 V). The VDDA and VDD LDO regulators achieve an efficiency of 83% with a maximum power dissipation of 1.2 W @4 A. The DVDD LDO regulator achieves an efficiency of 75% with a power dissipation of 1.2 W @1.5 A. VDDA33, if needed, can be directly supplied from V H. The VHDCI connector has 68 pins with a maximum current per pin of 500 mA. The proposed pin distribution in the connector is shown in
Figure 39. With such distribution the maximum current per pin in a 4 chip module is 420 mA .
Detector_bias(100 Vmax) NC GND EnableIn_PLUS DataIn_PLUS ClockIn_PLUS Reset_PLUS Shutter_PLUS Shutter1_CounterSelCRW_PLUS MatrixFastClear_PLUS TP_Switch_PLUS VL_1.8 VL_1.8 VL_1.8 VL_1.8 VL_1.8 V L_1.8 GND GND GND GND GND GND GND DataOut7_PLUS DataOut6_PLUS DataOut5_PLUS DataOut4_PLUS DataOut3_PLUS DataOut2_PLUS DataOut1_PLUS EnableOut_PLUS DataOut0_PLUS ClockOut_PLUS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
NC NC GND EnableIn_MINUS DataIn_MINUS ClockIn_MINUS Reset_MINUS Shutter_MINUS Shutter1_CounterSelCRW_MINUS MatrixFastClear_MINUS TP_Switch_MINUS VL_1.8 VL_1.8 VL_1.8 VL_1.8 VL_1.8 VH_3.3 VH_3.3 EXT_BGIn EXT_DACIn DAC_OUT_0 DAC_OUT_1 DAC_OUT_2 DAC_OUT_3 DataOut7_MINUS DataOut6_MINUS DataOut5_MINUS DataOut4_MINUS DataOut3_MINUS DataOut2_MINUS DataOut1_MINUS EnableOut_MINUS DataOut0_MINUS ClockOut_MINUS
Figure 39. Proposed pin distribution in the VHDCI connector
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Medipix3RX manual
8.4 Medipix3RX wafer step plan One Medipix3RX wafer contains 109 chips. The arrangement of the chips in the wafer can be seen in Figure 40. Note than when the notch is down and the chip origin is placed at the bottom left of the reticle. 200 mm
14.2 mm
m µ 5 6 4
14.1 mm
Medipix3
m m 8 8 . 5 1
m m 6 3 . 6 1
Chip origin
m µ 5 1
85 µm
15 µm
Figure 40. Medipix3RX wafer step plan
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Medipix3RX manual
8.5 Chip Identification The Medipix3RX chip name identification in a wafer is shown in Figure 41. As described in 7.5.5 there are 32 e-fuse bits which are used to identify uniquely each Medipix3 chip. In order to read the chipID the fuses are read using the command described in 7.5.4. Once the 32 bits are read out the chipID is decoded as shown in Figure 42. A correction algorithm has been implemented in order to correct badly burned Efuse bits as shown in . This algorithm corrects only one of the fields (Y, X or Wafer#).
(Y) 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
I
J
K
L
M (X)
Figure 41. Medipix3RX wafer map
Efuse [0:31] Y [0:3]
X [0:3]
Wafer# [0:11]
Y=1000 → A Y=0100 → B Y=1100 → C Y=0010 → D . . . Y=1011 → M
X=1000 → 1 X=0100 → 2 X=1100 → 3 X=0010 → 4 . . . X=1101 → 11
W=10000000_0000 → 1 W=01000000_0000 → 2 W=11000000_0000 → 3 W=00100000_0000 → 4 . . . W=11111111_1111 → 4095
MOD[0:1]
00 → No Correction 10 → Y Correction 01 → X Correction 11 → W Correction
MOD_VAL[0:7]
00 → 8’bXXXX_XXXX 10 → Y [0:3] 01 → X [0:3] 11 → W [0:7]
Figure 42. Chip decoding algorythm
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Medipix3RX manual
9 Threshold Equalization The Threshold equalization of the Medipix3RX chip is achieved by adjusting the 5-bit on-pixel current DACs ConfigDiscL[0:4] and ConfigDiscH[0:4]. The dynamic range of each current DAC can be adjusted independently. The I_DAC_DiscL periphery DAC adjusts the range for the ConfigDiscL pixel DAC and the I_DAC_DiscH periphery DAC adjusts the range for the ConfigDiscH pixel DAC. During threshold equalization the OMR bit Equalization must be set High as shown in Table 23. In this mode only CounterL is used to record the events and only one discriminator is equalized at a time by properly selecting the Disc_CSM_SPM OMR bit. The chip requires 4 threshold equalization 5-bit 256x256 masks: SPM_DiscL: Mask to be used in all modes for DiscL. • • SPM_DiscH: Mask to be used when chip is set in SPM (CSM_SPM=0) for DiscH. CSM_FP_DiscH: Mask to be used when chip is set in CSM (CSM_SPM=1) and fine pitch • mode (ColourMode=0) for DiscH. CSM_SM_DiscH: Mask to be used when chip is set in CSM (CSM_SPM=1) and • spectroscopic mode (ColourMode=1) for DiscH. In Table 30 is shown the different ways to generate the 3 equalization mask in different modes. Table 30.Summary of the threshold equalization depending on different settings
n o i t a z i l a u q E
e d o M r u o l o C
0
M P M S _ P S M _ S M C _ S C c s i D
X
X 0
0
SPM
Fine Pitch Mode
1 CSM
e r d o t o a m n n i o m i i r t c a s r e i D p o
d n e c o u i t d a o z r i l p a s u k q s E a M
X 0 1 0 1
SPM SPM SPMa CSM
SPM_DiscL SPM_DiscH SPM_DiscL CSM_FP_DiscH
0
SPM
SPM_DiscL
1
SPM
SPM_DiscH
0
SPMa
SPM_DiscL
1
CSM
CSM_SM_DiscH
0 SPM
1 1 Colour Mode
1 CSM
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d l d o e z h i s l e a r u h q T E
Threshold[0] Threshold[1] Threshold[0] Threshold[1] Threshold[0] Threshold[2] Threshold[4] Threshold[6] Threshold[1] Threshold[3] Threshold[5] Threshold[7] Threshold[0] Threshold[2] Threshold[4] Threshold[6] Threshold[1] Threshold[3] Threshold[5] Threshold[7]
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