Quiz #1P Name: Section: 1. An IC containing up to 100 gates or more than 100 transistor. a. Small-Scale Integration b. Medium-Scale Integration c. Large-Scale Integration d. Very Large-Scale Integration 2. It has attractive features of lowest power dissipation and highest integration density. a. CMOS b. BJT c. GaAS d. MOSFET 3.
What is VSLI? a. Very Large Scene Integration Circuit b. Very Large Scale Integration Circuit c. Very Large Scene Integral Circuit d. Very Large Scene Interpolation Circuit 4. It is the first semiconductor material that they used in first point contact transistor. a. Silicon b. Germanium c. GalliumArsenide d. Tellurium
Date: Instructor: c. 1947 d. 1948 7. It explored the potential of miniaturization of building multiple transistors on a single piece of silicon. a. The first microprocessor b. The first integrated circuit c. The first integrated program d. The first CMOS 8. Meaning of CMOS. a. Complementary Metal-Oxide Semiconductor b. Complementary Complementary Metal-Oxide Silicon c. Complementary Metal-Oxygen Semiconductor d. Complimentary Metal-Osmium Silicon 9. The fabrication of semiconductor devices with p-n junctions that terminate in the same plane surface of a semiconductor wafer and are located beneath a layer of a protective dielectric coating. a. Germanium Plane Process b. Germanium Planar Process c. Silicon Plane Process d. Silicon Planar Process
5. To estimate that the simulation should take between one to two time that is schedule to design or to enter system design. a. Rule of Right Hand b. Rule of the Finger c. Rule of Thumb Factor d. Rule of the Hand
10. In this device, one gate is approximately equivalent to 7 to 10 transistor depending on type. a. Field Program Gate Array b. Field Programmable Gate Array c. Field Program Gate Arrangement d. Field Programmable Gate Arrangement
6. In what year did John Bardeen, William Shockley and Walter Brattain discovered the first point contact transistor? a. 1945 b. 1946
11. Which of the following is not benefit of using a VLSI Circuit? a. May reduce manufacturing cost b. Reducing parasitic c. Generates less heat d. High Current Output
12. Also termed optical lithography or UV lithography a. Photolithography b. Photolithograph c. Photography d. Photobiography 13. It is also referred to nonrecurring engineering cost and mainly the start cost until the first prototype is obtain a. Fixed Cost b. Total Cost c. Variable Cost d. Actual Cost 14. Namely the cost of manufacturing wafers that range between 1200 to 1600 USD for a 300mm wafer. a. Fixed Cost b. Total Cost c. Variable Cost d. Actual Cost 15. The typical value for the measure of manufacturing complexity. a. 3.0 b. 4.0 c. 5.0 d. 6.0
16. It is popular because they can integrate a complicated system into a single chip or also known as System-On-a-Chip. a. DSM b. SM c. VLSI d. CMOS
17. What is the effect of the reduction of thickness of the DSM. a. Short Channel b. DIBL c. Charge Sharing d. Thin Oxide and Breakdown 18. It affects a large area of circuits in a unpredictable way it is formed in a closed loop and there may exist many possible return paths with different path lengths for a single signal path. a. Capacitive Coupling b. Inductive Coupling c. IR Drop d. Electromigration 19. Refers to the influence of drain voltage on the threshold voltage a. Subsurface Punchthrough b. Charge Sharing c. DIBL d. Short Channel Effect 20. An electron in a conductor migrates and dislodges the lattice of the conductor, what is this phenomenon. a. DIBL b. Electromigration c. Charge Sharing d. Subsurface Punchthrough
Quiz #2P Name: Section:
1. What do you call the combining effects of both nMOS and pMOS transistors as a combined switch? a. Field Effect transistor (FET) b. junction gate field-effect transistor (JFET)
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c. Complementary Metal –oxide – Semiconductor (CMOS) d. Metal –oxide –semiconductor field-effect transistor (MOSFET) What is the other term of CMOS switch? a. Transmission Gate b. Transistor Gate c. Transferring Gate d. Teaching Gate What minimum voltage required to operate CMOS? a. 3v-5v b. 0.7v-1.4v c. 1.4-2.1v d. 0.3v-0.7v The minimum voltage VGS including the channel is defined as the _________, denoted VTn, of the nMOS transistor. a. Barrier potential b. Threshold voltage c. Input voltage d. Logic input PMOS transistors will operate when it supplies? a. Positive input voltage b. Negative input Voltage c. Positive or Negative input voltage NMOS transistors will operate when it supplies? a. Positive input voltage b. Negative input voltage c. Positive or Negative input Voltage
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7. The junctions of an nMOS and pMOS transistors are? a. Collector, Emitter, Base b. Drain, Source, Gate c. Anode, Cathode, Out d. Positive, Negative,Neutral 8. The “GATE” junction of an CMOS is made up of ? a. Germanium b. Polysilicon c. Lead d. Copper 9. Most semiconductor components is made up of? a. Di-electric material b. Copper c. Silicon d. Lead 10. In most applications, pMOS and cMOS transistors are used as? a. Amplifier b. Switch c. Rectifier d. Inductor 11. NMOS transistors are ideal switches for transferring? a. Logic-0 Signals b. Logic-1 Signals c. Logic-0 or 1 Signals 12. PMOS transistors are ideal switches for transferring? a. Logic-0 Signals b. Logic-1 Signals c. Logic-0 or1 Signals 13. It is a simple logic pattern utilizing the aforementioned features of both NMOS and PMOS switches to implement a switching function?
a. Block Diagram b. Truth Table c. Ladder Diagram d. f/f’ Paradigm 14. What are the two Fundamental Rules should be followed to correctly and completely realize a switching function using CMOS switches? a. Positive-value rule, Negative-value rule b. Node-conflict-free rule, Negative-value rule c. Node-value rule, Positive-value rule d. Nod-value rule, Node-conflict-free rule 15. MOS is the abbreviation of _____________________. a. manganese-oxide silicon b. metal-oxide silicon c. metal-oxide semiconductor d. mega-over semiconductor 16. The NMOS transistor has a. 2 p regions and n substrate b. 1 n region and p substrate c. 1 p region and n substrate d. 2 n regions and p substrate 17. The PMOS transistor has a. 2 p regions and n substrate b. 1 n region and p substrate c. 1 p region and n substrate d. 2 n regions and p substrate 18. The threshold voltage of NMOS transistor ranges a. from 3V to 7V b. from -3V to -7V c. from 0.3V to 0.7V d. from -0.3V to -0.7V 19. The threshold voltage of PMOS transistor ranges a. from 3V to 7V b. from -3V to -7V c. from 0.3V to 0.7V d. from -0.3V to -0.7V
20. Is a transistor used for amplifying or switching electronic signals. a. MESFET b. MOSFET c. BJT d. JFET
SW #1P Name: Section:
Date: Instructor:
1.) An iterative process that refines an idea to a 7.) What is the symbol for PMOS? manufacturable device through at least five levels of design abstraction a.) a. Design Abstraction b. Design Process c. Hierarchy Design d. Project Design 2. )A Design domain that specifies what a particular system does a. Behavioral b. Structural b. ) c. Sociological d. Physical 3. )It is also known as “Divide and Conquer” wherein complexity is reduced via recursively breaking it down into manageable parts a. Structural b. Hierarchical Design c. Design Abstraction c.) d. VLSI Design 4.) It tells what is the capability of the design like, what does the chip do? How big will it be? Or How much power will it consume? a. Design constraints b. Electronic design c. Specification d. Design Process 5.) Complexity is reduced by successively replacing details d) with simplified levels of process a. Design abstraction b. Physical domain c. Hierarchy design d. Behavioral design 6.)At this level, the design is implemented with transistors. a. Gate level 8.) It is a simplified layout which only represents the re lative b. Layout level relationship among wires and components without being c. Circuit level confined to layout rules. d. Functional level a.) Stick diagram b.) Logic diagram c.) Logic circuit d.) None of the Above
9.)It is the symbol for AND gate.
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d) 10.) In the state diagram color scheme, what is the red wire/part in called? a. metal1 b. passive c. active d. poly
b. NOT gate, two input NAND gate and two output NOR gate c. Inverter, two input AND gate and two output NOR gate d. NOT gate, two input NAND gate and two output OR gate 15.) What are the three most basic types of cells? a. Hierarchical cells, Sequential cells and Subsystem cells b. Combinational cells, Sequential cells and Subsystem cells c. Hierarchical cells, Combinational cells and Sequential cells d. Hierarchical cells, Combinational cells and Subsystem cells
16.) Another view of a circuit, it has all the information required for fabricating the circuit in an IC foundry. a. LOCOS b. CMOS circuit c. CMOS layout d. STI 17.) Also Known as BOX ISOLATION TECHNIQUE is an integrated circuit feature which prevents electrical 11.) What cells whose outputs are only determined by the current leakage . present inputs. That only functions of present inputs? a. CMOS circuit a. Sequential cells b. Shallow trench isolation b. Subsystem cells c. Local oxidation of silicon c. Combinational cells d. Layout d. Hierarchical cells 18.) Usual range of masks required for CMOS circuit. 12.)What cells included the basic memory devices such as a. 7 to more than 20 b. 14 to more than 40 latches and flipflops? c. 3 to more than 18 a. Sequential cells d. 8 to more than 16 b. Subsystem cells 19.) The range of masks required is dependent to its ___. c. Combinational cells a. substrate d. Hierarchical cells b. epitaxial layer 13.)What cells whose outputs are not only determined by the c. metal layers current inputs but also dependent on their previous output d. active regions values? 20.) Is a set of predefined rules to specify geometrical a. Hierarchical cells objects (polygons). Either it touches or overlaps the masking b. Combinational cells layer. c. Subsystem cells a. silicon oxidation rule b. Euler’s theorem d. Sequential cells c. Layout design rules 14.)Combinational cells typically include basic gates. What d. CMOS process are the three basic CMOS gates? a. Inverter, two input AND gate and two output OR gate
SW #2P Name: Section: 1. It is significantly increased with the decreasing feature sizes of manufacture processes due to exponentially increased cost related equipment, photolithography masks, CAD tools and R&D. a. NRE COST c. CAD tools b. Field-Programmable Devices d. Full-custom 2. Combines features from both platforms and field programmers into one or more CPUs in a hard, soft or hardwired IP worm, some periphery modules, and field programmable logic modules. a. ASICs c. Platforms FPGA b. Time to market d. µP/DSP- based system 3. It is a predesigned component that can be reused for larger designs. a. IR drop c. Hard IP b. Intellectual Property (IP) d. Gate-Array 4. Combines varieties of IPs and builds the resulting design on a gate array (which is a wafer with fabricated transistors). a. Intellectual Property (IP) c. Hardwired IP b. Gate-Array d. Cell-based 5. It starts from scratch and needs to design layouts of every transistor and wire. a. Full-custom c. L di/dt effect b. Hardwired IP d. Complex Programmable Logic Devices 6. It is often reserved to identify an integrated circuit (IC) that needs to be processed in an IC foundry. a. ASICs b. Field Programmable Gate Arrays c. Platforms FPGA d. Field-Programmable Devices 7. Contains an 8-bit or 32-bit Center Processor Unit (CPU). a. Microprocessor c. FPGAs b. Field-programmable devices d. µP/DSPbased system 8. It is the one that designs many uncommitted logic modules that can be committed to the desired functions on-demand laboratories. a. Field-programmable devices c. FPGAs
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Computer-Aided Design d. ComplexProgrammable Logic Devices It is a circuit module already fabricated along with FPGA fabrics. a. Hard IP c. Intellectual Property (IP) b. Hardwired IP d. Soft IP Combines various full-custom cells, blocks, and IPs into a chip. a. Cell-based c. Gate-array b. Full-custom d. Platforms FPGAs These are used to model and analyze the three issues in designing a VLSI system with DSM processes. a. Field-programmable devices b. µP/DSP- based system c. Complex-Programmable Logic Devices d. Computer-Aided Design (CAD) tools The following are the important issues in designing a VLSI system with DSM Processes except? a. Hot-spot problems c. µP/DSP- based system b. L di/dt effect d. IR drop The Future trends of VLSI (digital) system designs can be designed into these three classes except? a. ASICs c. Field-programmable devices b. Computer-Aided Design d. Platforms It is also called as a microcontroller chip. a. µP/DSP- based system c. Gate-Array b. Cell-based d. IR drop It is often referred as a virtual component. a. Intellectual Property (IP) c. Gate-Array b. Full-custom d. IR drop It can accurately measure by block size, performance and power dissipation of a hard IP a. Soft IP c. Hard IP b. Hardwired IP d. Intellectual Property (IP)
17. It is a synthesizable module in HDL, Verilog HDL or VHDL. a. Soft IP c. Hard IP b. Hardwired IP d. Intellectual Property (IP) 18. It is more flexible to new technologies but is harder to characterize, occupy more area, and perform more poorly that hard IPs. a. Hardwired IP c. Soft IP b. Intellectual Property (IP) d. Hard IP 19. It has the essential feature that its final logic function needs to be committed through par tial or full set of mask layers in an IC foundry. a. Platforms FPGAs c. Field-programmable devices b. µP/DSP- based system d. ASICs 20. It is suitable for a product that has a successful market and needs a short time to market. a. Gate-Array c. Cell-based b. Full-custom d. IR drop
Answers Q1 1. B 2. A 3. B 4. B 5. C 6. C 7. B 8. A 9. D 10. B 11. D 12. A 13. A 14. C 15. B 16. A 17. D 18. B 19. C 20. B
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1.C 2. A 3.D 4. B 5. B 6. A 7. B 8.B 9. C 10. B 11.A 12. B 13. D 14. D 15. C 16. D 17. A 18. C 19. D 20. B
1) B 2) A 3) B 4) C 5)A 6) C 7) B 8) A 9) C 10) D 11) C 12) A 13) D 14) B 15) 16) C 17) B 18) A 19) C 20) C
1. NRE COST (a) 2. Platforms FPGA (c) 3. Intellectual Property (IP) (b) 4. Gate-Array (b) 5. Full-custom (a) 6. ASICs (a) 7. µP/DSP- based system (d) 8. Field-Programmable Devices (a) 9. Hardwired IP (b) 10. Cell-based (a) 11. Computer-Aided Design (CAD) tools (d) 12. µP/DSP- based system (c) 13. Computer-Aided Design (b) 14. µP/DSP- based system (a) 15. Intellectual Property (IP) (a) 16. Hard IP (c) 17. Soft IP (a) 18. Soft IP (c) 19. ASICs (d) 20. Gate-Array (a)
