VISVESVARAYA TECHNOLOGICAL UNIVERSITY Jnana Sangama, Belgaum, Karnataka - 590014
A Dissertation Report on
Design and Verification of I2C Master/Slave Controller with APB Interface Submitted in partial fulfillment for the award of degree of
MASTER of TECHNOLOGY in
VLSI Design & Embedded systems Submitted By
M.R. Manjunatha USN: 1RV08LVS12
Carried out at R.V VLSI Design Center, Bangalore
Under the guidance of: Internal Guide:
V. Kiran Asst Professor, R.V.C.E, Bangalore
R V COLLEGE OF ENGINEERING Department of Electronics and Communication Engineering BANGALORE – 560 059 2010-2011
R.V. College of Engineering Bangalore – 560059 Department of Electronics and Communication Engineering
CERTIFICATE This is to certify that the project work entitled “ Design and Verification I2C Master/Slave Controller with APB Interface ” is a bonafide work carried out at R.V.
VLSI Design Design Centre , Bangalore Bangalore.. by Mr. M.R. Manjunatha , USN: 1RV08LVS12, 1RV08LVS12, a student of fourth Semester M.Tech, at the Department of Electronics and Communication Engineering, R.V.C.E R.V.C.E,, in the partial fulfillment of the requirements for the award of degree in Master of Technology in VLSI Design & Embedded Systems, affiliated to Visvesvaraya Technological University, Belgaum during the academic year 2010-2011.
It is certified that all corrections/suggestions indicated for Internal Assessment have been incorporated in the report deposited in the department library. The project has been approved as it satisfies the academic requirements in respect of project work described for the M.Tech degree.
V.Ki V. Kira ran n Internal Guide
Dep Dept. of E.C. .C.E, R.V. R.V.C. C.E E Bangalore -560059
Prof.. S. Prof S.Ja Jaga gann nnat atha han n Head of the Department Dep Dept. of E.C.E .C.E,, R.V. R.V.C. C.E E Bangalore -560059
Prof. Pro f. B. B.S. S.Sa Saty tyan anar aray ayan ana a Principal R.V R.V.C.E .C.E Bangalore -560059
External Viva Name of the Examiners
Signature with Date
1.___________________
_________________
2.___________________
_________________
R.V. College of Engineering Bangalore – 560059 Department of Electronics and Communication Engineering
CERTIFICATE This is to certify that the project work entitled “ Design and Verification I2C Master/Slave Controller with APB Interface ” is a bonafide work carried out at R.V.
VLSI Design Design Centre , Bangalore Bangalore.. by Mr. M.R. Manjunatha , USN: 1RV08LVS12, 1RV08LVS12, a student of fourth Semester M.Tech, at the Department of Electronics and Communication Engineering, R.V.C.E R.V.C.E,, in the partial fulfillment of the requirements for the award of degree in Master of Technology in VLSI Design & Embedded Systems, affiliated to Visvesvaraya Technological University, Belgaum during the academic year 2010-2011.
It is certified that all corrections/suggestions indicated for Internal Assessment have been incorporated in the report deposited in the department library. The project has been approved as it satisfies the academic requirements in respect of project work described for the M.Tech degree.
V.Ki V. Kira ran n Internal Guide
Dep Dept. of E.C. .C.E, R.V. R.V.C. C.E E Bangalore -560059
Prof.. S. Prof S.Ja Jaga gann nnat atha han n Head of the Department Dep Dept. of E.C.E .C.E,, R.V. R.V.C. C.E E Bangalore -560059
Prof. Pro f. B. B.S. S.Sa Saty tyan anar aray ayan ana a Principal R.V R.V.C.E .C.E Bangalore -560059
External Viva Name of the Examiners
Signature with Date
1.___________________
_________________
2.___________________
_________________
R.V. College of Engineering Bangalore – 560059 Department of Electronics and Communication Engineering
DECLARATION I, M.R. Manjunatha, student of fourth semester M.Tech, VLSI Design & Embedded Systems, Department of Electronics and Communication Engineering, R.V. College of Engine Engineerin ering, g, Bangal Bangalore ore,, hereby hereby declar declaree that that the disser dissertat tation ion entitl entitled ed “Des Design ign and Verification of I2C Master/Slave Controller with APB Interface” Interface ” has been carried out
by me and submitted in partial fulfillment of the course requirements for the award of degr degree ee in Mast Master er of Tech Techno nolo logy gy in Comm Commun unic icat atio ion n Syst System emss Engi Engine neer erin ing g of Visvesvaraya Technological University, Belgaum during the academic year 2010-2011.
Further, the matter embodied in the dissertation has not been submitted previously by anybody for the award of any degree or diploma to any other university.
Place: Bangalore
M.R.Manjunatha
Date :
USN: 1RV08LVS12 R.V.C.E, Bangalore- 59.
ABSTRACT I2C master/slave controller is an interface that interconnects an advanced peripheral bus (APB) with Inter Integrated circuit (I2C) bus. The APB - I2C Bridge interfaces to the APB bus on the system side and the I2C bus. The APB interface is used to easily integrate the Bridge Controller for any SOC implementation. The controller performs the following functions. Parallel-to-serial conversion on data written to an internal 8bit wide,1024 deep FIFO. Serial-to-parallel conversion on received data, buffering it in a similar 8-bit wide,1024 deep
FIFO. Device states are read by the APB using status registers that
reflect the completion of I2C transfers.
The APB bus is part of the Advanced Microcontroller Bus Architecture (AMBA) hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The APB bus is used to interface to any peripheral device which are low bandwidth and do not require the high performance of a pipelined bus interface. The APB slave interface acts as a bridge between the APB bus and the peripheral device to which the bus is connected. It receives the APB bus signals and converts them to a form in which is understood by the connected peripheral device. Most common applications of the APB interface is to read and write registers of the connected device. The Peripheral devices connected to the APB bus could be UART, Timer, Keypad, etc.
I2C bus contains two lines. Serial clock line(SCL) and Serial Data Line (SDA).Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a currentsource or pull-up resistor . When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the I2C-bus can be transferred at rates of up to 100 Kbit/s in the Standard-mode, up to 400 Kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the Highspeed mode.I2C interface supports a Clock generation circuitry to derive I2C clock from APB clock. I2C interface supports various operational frequencies from 100 KHZ to 400 KHZ. It supports a simple bi-directional 2-wire bus for efficient inter-IC control.
ACKNOWLEDGEMENT Any accomplishment requires the effort of many people and this work is no different. I gratefully acknowledge all the people who contributed to the successful completion of this project. I would specially like to thank I am thankful to my external Guide Mr. Ramrao, Faculty, RV-VLSI Design Centre, Bangalore, for his creative ideas, high standards of discipline, constant inspiration and guidance. I also would like to thank Malathi, R.V. VLSI Design Centre, Bangalore, for his support, guidance , suggestions and constant assistance throughout my project. I express my gratitude to my internal guide V.Kiran , Assistant Professor, Department of Electronics and Communication RVCE, Bangalore for the valuable guidance and support offered to me throughout the course of this project. Prof. B.S.Satyanarayana, Principal,R. V. College of Engineering, Bangalore, for giving
me an opportunity to carry out my project at RV-VLSI Design Centre, Bangalore. Prof. S.Jagannathan , Head of the Department, Department of Electronics and
Communication Engineering, R.V. College of Engineering, Bangalore, for his constant encouragement and support. Dr.M.Uttara Kumari , P.G. Coordinator, Department of Electronics and Communication
Engineering, R.V. College of Engineering, Bangalore, for her constant guidance in all the phases of my project. I am thankful to all the Faculty Members in the Department of Electronics and Communication, R.V. College of Engineering, Bangalore, for their constant support. I would like to thank my Parents and Friends for their moral support. Last but not least, I would like to thank those, whose name may not have been appeared here but their efforts have not gone unnoticed. -Manjunatha M.R.
TABLE OF CONTENTS LIST OF TABLES................................................................................. IX LIST OF ABBREVIATIONS........................................................................................... X CHAPTER 1 .................................................................................................................... 11 INTRODUCTION............................................................................................................ 11 1.7 Organization of the Report........................................................................................ 16 LITERATURE SURVEY................................................................................................18 Chapter 3........................................................................................................................... 28 Table 1 Definition of I2C-bus terminology.................................................................... 30 TERM................................................................................................................................ 30 DESCRIPTION................................................................................................................ 30 Transmitter....................................................................................................................... 30 Receiver............................................................................................................................. 30 Master................................................................................................................................ 30 Slave................................................................................................................................... 30 The device addressed by a master..................................................................................30 Multi-master..................................................................................................................... 30 Arbitration........................................................................................................................ 30 Synchronization................................................................................................................ 30 ................................................................................................................................... 31 Fig.2 Example of an I2C-bus configuration using
two microcontrollers........31
3.4) GENERAL CHARACTERISTICS......................................................................... 32 3.4.1) BIT TRANSFER.............................................................................................. 32 3.4.2) Data validity.......................................................................................................... 33 CHAPTER 4 ..................................................................................................................... 37 CHAPTER 7 ..................................................................................................................... 64 CONCLUSIONS AND FUTURE SCOPE....................................................................64
LIST OF FIGURES ............................................................................................................................................58 Figure 5.3: Simulation result of Baud rate generator using VCS (Synopsys). .......................................................................................................................58 6.2.3 Master read operation...........................................................................................59 Slave address =000111,
Data length =2.....................................................................59
APB address = 000 1001 (address of device on APB bus which has to red data from I2C bus).............................................................................................................................59 Data bytes received serially from I2C bus ....................................................................59 0011 1110....................................................................................................59 1100 0111....................................................................................................59 Data bus outputs 3e and c7..............................................................................................59 000 Address bus
Pselect1 is selected
....................................................................59
9..........................................................................................................59
....................................................................................................................................60 Figure 5.6: Simulation result shows RAM with different data loaded at different instant of time. .................................................................................................................60 ............................................................................................................................................61 Figure 5.7: Shows Schematic view of Synchronous FIFO . .................61 5.2.4 ) Slave read operation.............................................................................................62 During the slave read mode , slave controller detects the start bit from I2C bus, then it receives the 7 bit of data , it stores the data into the APB address register. Then checks for R/W. If R/W is 1, then it receives 8 bit of data from I2C bus. It stores the data in to the FIFO. It updates the I2C status register. APB controller always keeps checking the I2C status register. After the operation of slave controller is over, it reads the APB ADDR register , to that particular address it sends the data from FIFO in APB protocol format.........................................................................................62 ............................................................................................................................................62 Figure 5.8: Simulation result of THRE interrupt using Questasim 6.4b. ............................................................................................................................................63 .....................................................................................................................................63 ...................................63
Figure 5.8: Simulation result of THRE interrupt using QuestaSim 6.4b … Figure 5.9: Simulation result of Receiver data available Interrupt……………… Figure 5.10: Simulation result of Character Time Out Interrupt … Figure 5.11: Simulation result of Receiver line status Interrupt………………………….. Figure 5.12: Quad UART clocks with random skew.……………………………………… Figure 5.13: Showing simulation report of random number generation................................ Figure 6.1: Shows the process of converting HDL into Standard cells................................. Figure 6.2 : Showing Synthesis flow for the design............................................................. Figure 6.3: Showing translation from HDL to Generic Boolean (Generic technology)........ Figure 6.4: Schematic view of GTECH form........................................................................ Figure 6.5: Process of converting GTECH form into Standard cells by mapping................ Figure 6.6: Schematic view of Standard cells.......................................................................
LIST OF TABLES
LIST OF ABBREVIATIONS APB:
Advanced Peripheral Bus.
AMBA:
Advanced Microcontroller Bus Architecture
IIC:
Inter Integrated Circuit
FCR:
FIFO Control Register.
IIR:
Interrupt Identification Register.
IER:
Interrupt Enable Register.
DRAB:
Divisor Register Address Bit.
DRMSB:
Divisor Register Most Significant Bit.
DRLSB:
Divisor Register Least Significant Bit .
DL:
Divisor Latch Register.
SOUT:
Serial Out.
SIN:
Serial In.
FIFO:
First In First Out.
TX:
Transmitter.
RX:
Receiver.
BRG:
Baud Rate Generator.
UART:
Universal Asynchronous Receiver And Transmitter .
LSR :
Line Status Register.
RLS:
Receiver Line Status Interrupt.
RDA:
Received Data Available Interrupt.
THRE:
Transmitter Holding Register Empty Interrupt.
CTO:
Character Time Out Indication.
FE:
Framing Error.
BE:
Break Error.
VCS:
Verilog Code Simulator
GTECH:
Generic Technology.
CHAPTER 1
INTRODUCTION 1.1 Introduction to I2C Master/Slave Controller The I2C Controller provides access to devices with I2C interface. It accepts the Read / Write commands from APB and converts it to the serial I2C access. The controller supports High speed mode with maximum 3.4 Mbps throughput and it is down compatible with fast mode (400kbps) and standard mode (100kbps). I2C controller supports both master and slave m ode. In master mode data transfer is initiated by I2C master interface. In slave mode data transfer is initiated by I2C bus
The synchronous 2 bit I2C bus is a serial bus which supports the bit transfer rate up to 3.4mbps. The I2C controller interfaces to the host through AMBA-APB bus. The host programs all the control and configuration register using APB bus. Depending on the data transfer direction the controller initiates the transaction. The controller is responsible for converting the 8 bit data from host to serial data or serial data from I2C bus to 8 bit data for the host. The APB–I2C is a master/slave interface that enables synchronous serial communication with the other master or slave I2C peripherals having I2C compatible interface. Device states are read by the APB using status registers that reflect the completion of I2C transfers. Controller also supports the interrupt pin for indicating the transaction completion or any error in the controller.
1.2 Overview of the AMBA The Advanced Microcontroller Bus Architecture (AMBA) specification defines an on chip
communications
standard
for
designing
microcontrollers.
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high-performance
embedded
Three distinct buses are defined within the AMBA specification: 1 The Advanced High-performance Bus (AHB) 2 The Advanced System Bus (ASB) 3 The Advanced Peripheral Bus (APB).
The Advanced High-performance Bus (AHB)
The AMBA AHB is for high-performance, high clock frequency system modules. The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macro cell functions. AHB is also specified to ensure ease of use in an efficient design flow using synthesis and automated test techniques.
Advanced System Bus (ASB)
The AMBA ASB is for high-performance system modules. AMBA ASB is an alternative system bus suitable for use where the high-performance features of AHB are not required. ASB also supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macro cell functions.
Advanced Peripheral Bus (APB)
The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The AMBA APB should be used to interface to any peripherals which are low bandwidth and do not require the high performance of a pipelined bus interface.
1.3 Introducing the AMBA APB The APB is part of the AMBA hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The AMBA APB appears as a local secondary bus that is encapsulated as a single AHB or ASB slave device. APB provides a -12-
low-power extension to the system bus which builds on AHB or ASB signals directly. The APB bridge appears as a slave module which handles the bus handshake and control signal retiming on behalf of the local peripheral bus. By defining the APB interface from the starting point of the system bus, the benefits of the system diagnostics and test methodology can be exploited. The AMBA APB should be used to interface to any peripherals which are low bandwidth and do not require the high performance of a pipelined bus interface.
The latest revision of the APB is specified so that all signal transitions are only related to the rising edge of the clock. This improvement ensures the APB peripherals can be integrated easily into any design flow, with the following adv antages: 1) High-frequency operation easier to achieve 2) Performance is independent of the mark-space ratio of the clock 3) Static timing analysis is simplified by the use of a single clock edge 4) No special considerations are required for automatic test insertion 5)
Many Application Specific Integrated Circuit (ASIC) libraries have a better selection of rising edge registers
6) Easy integration with cycle-based simulators. These changes to the APB also make it simpler to interface it to the new AHB. An AMBA APB implementation typically contains a single APB bridge which is required to convert AHB or ASB transfers into a suitable format for the slave devices on the APB. The bridge provides latching of all address, data and control signals, as well as providing a second level of decoding to generate slave select signals for the APB peripherals.
1.4 THE I2C-BUS CONCEPT The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether it’s a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In -13-
addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers . A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave
1.5
PROJECT FLOW •
The specification of the APB (Advanced peripheral bus) and I2C bus are understood.
•
The architecture and design of the functional specification for the APB-I2C bridge are developed.
•
The design is coded in RTL using Verilog HDL.
•
A verification plan is prepared for verifying the feature of the I2C Master/Slave Controller with APB bus interface.
•
A verilog based test bench are developed and simulated using Mentor Graphics Questasim 6.4b.
•
RTL is verified for various test cases like manually giving the inputs and getting the output in I2C protocol format.
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Fig shows a flow diagram of the stages explained above.
SPECIFICATIONANALYSIS
DESIGNSPECIFICATIONPREPARATION
RTL CODING
VERIFICATIONPLANCREATION
TESTBENCHANDTEST CASE CREATION
RUNNING TEST CASE / DEBUG
Figure 1.1: A Schematic Representation of the Project Flow
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1.6
Objectives of the project
The aims and objectives of this project are as follows: 1. To design an I2C Master/Slave Controller with APB bus interface in verilog HDL and to do its verification. 2. 3. 4. 5. 6.
To design and verify I2C master/slave controller with APB interface. To develop FSM design for the given design. To develop a verilog code based on the FSM , for the given design. To develop a test bench for the verification of given design. Compilation and simulation by using VCS.( Verilog Code Simulator).
1.7 Organization of the Report The report is organized into 6 chapters as given below. Chapter 1 provides a brief introduction about the I2C Master/slave controller. This
chapter provides a brief description AMBA bus, I2C bus different classification of AMBA bus. Chapter 2 deals with the detailed literature survey, which provides ,previous method of
I2C - APB bridge, method of operation of previous method, limitations of I2C – APB bridge in the previous method Chapter 3 provides an overview about the I2C bus. Specifications of I2C bus. Different
modes of operations of I2C bus, devices connected to I2C bus. Chapter 4 provides an overview of APB bus. Specifications of APB bus. How the data
flows during read/write operation. Chapter 5 discusses about I2C master/slave controller, functional block description of
the I2C master/slave controller. Chapter 6 provides the details about test results of electronic rudder actuation hardware
system, error angle plot, conclusions and future enhancement.
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CHAPTER 2 LITERATURE SURVEY 2.1) A review on APB-I2C bridge The I2C core is built around four primary blocks; the Clock Generator, the Byte Command Controller, the Bit Command Controller and the DataIO Shift Register. All other blocks are used for interfacing or for storing temporary values.
Registers list Name Clock Prescale register
Width 8 bit
Access RW
Control register Transmit register Receive register Command register
8 bit 8 bit 8 bit 8 bit
RW W R W
Status register
8 bit
R
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2.2) Register description Prescale Register
This register is used to prescale the SCL clock line. Due to the structure of the I2C interface, the core uses a 5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change the value of the prescale register only when the ‘EN’ bit is cleared.
Example: wb_clk_i = 32MHz, desired SCL = 100KHz
Pre scale = 32 MHz/(5*100KHz)-1= 63(decimal) = 3F(hex)
Transmit register Bit # 7:1 0
Access w w
Description Next byte to transmit via I2C In case of a data transfer this bit represent the
data’s LSB. In case of a slave address transfer this bit represents the RW bit. ‘1’ = reading from slave ‘0’ = writing to slave
Receive register Bit # 7:0
Access R
Description Last byte received via I2C
Command register Bit #
Access
Description -19-
7 6 5 4 3 2:1 0
w w w w w
STA, generate start condition STO, generate stop condition RD, read from slave WR, write to slave ACK, when a receiver, sent ACK
w w
(ACK = ‘0’) or NACK (ACK = ‘1’) Reserved IACK, Interrupt acknowledge. When set, clears a pending interrupt
The STA, STO, RD, WR, and IACK bits are cleared automatically. These bits are always read as zeros.
Status register Bit # 7
Access R
Description Received acknowledge from slave.
This flag represents acknowledge from the addressed slave. ‘1’ = No acknowledge received 6
‘0’ = Acknowledge received Busy, I2C bus busy
R
‘1’ after START signal detected 4:2 1
R R
‘0’ after STOP signal detected Reserved TIP, Transfer in progress. ‘1’ when transferring data ‘0’ when transfer complete
Control register
Bit # 7
Access RW
Description EN, I2C core enable bit.
When set to ‘1’, the core is enabled. 6
RW
When set to ‘0’, the core is disabled. IEN, I2C core interrupt enable bit. -20-
When set to ‘1’, interrupt is enabled. 5:0
RW
When set to ‘0’, interrupt is disabled. Reserved
The core responds to new commands only when the ‘EN’ bit is set. Pending commands are finished. Clear the ‘EN’ bit only when no transfer is in progress, i.e. after a STOP command, or when the command register has the STO bit set. When halted during a transfer, the core can hang the I2C bus.
2.3) Operation System Configuration The I2C system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers. All devices connected to these two signals must have open drain or open collector outputs. The logic AND function is exercised on both lines with external pull-up resistors. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (see START and STOP signals).
2.4) I2C Protocol Normally, a standard communication consists of four parts: 1) START signal generation 2) Slave address transfer 3) Data transfer 4) STOP signal generation
START signal
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When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a high-to-low transition of SDA while SCL is high. The START signal d enotes the beginning of a new data transfer. A Repeated START is a START signal without first generating a STOP signal. The master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading from a device) without releasing the bus.The core generates a START signal when the STA-bit in the Command Register is set and the RD or WR bits are set. Depending on the current status of the SCL line, a START or Repeated START is generated.
Slave Address Transfer
The first byte of data transferred by the master immediately after the START signal is the slave address. This is a seven-bits calling address followed by a RW bit. The RW bit signals the slave the data transfer direction. No two slaves in the system can have the same address. Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle. Note: The core supports 10bit slave addresses by generating two address transfers. See the Philips I2C specifications for more details. The core treats a Slave Address Transfer as any other write action. Store the slave device’s address in the Transmit Register and set the WR bit. The core will then transfer the slave address on the bus. Data Transfer
Once successful slave addressing has been achieved, the data transfer can proceed on a byte-by-byte basis in the direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a No Acknowledge, the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle. If the master, as the receiving device, does not acknowledge the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal. To write data to a slave, store the data to be transmitted in the Transmit Register and set the WR bit. To -22-
read data from a slave, set the RD bit. During a transfer the core set the TIP flag, indicating that a Transfer is In Progress. When the transfer is done the TIP flag is reset, the IF flag set and, when enabled, an interrupt generated. The Receive Register contains valid data after the IF flag has been set. The user may issue a new write or read command when the TIP flag is reset.
STOP signal
The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-bit, is defined as a low-to-high transition of SDA while SCL is at logical ‘1’.
Clock Generator
The Clock Generator generates an internal 4*Fscl clock enable signal that triggers all synchronous elements in the Bit Command Controller. It also handles clock stretching needed by some slaves.
2.5) Byte Command Controller The Byte Command Controller handles I2C traffic at the byte level. It takes data from the Command Register and translates it into sequences based on the transmission of a single byte. By setting the START, STOP, and READ bit in the Command Register, for example, the Byte Command Controller generates a sequence that results in the generation of a START signal, the reading of a byte from the slave device, and the generation of a STOP signal. It does this by dividing each byte operation into separate bit-operations, which are then sent to the Bit Command Controller.
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Working flow chart
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2.6) Bit Command Controller The Bit Command Controller handles the actual transmission of data and the generation of the specific levels for START, Repeated START, and STOP signals by controlling the SCL and SDA lines. The Byte Command Controller tells the Bit Command Controller which operation has to be performed. For a single byte read, the Bit Command Controller receives 8 separate read commands. Each bit-operation is divided into 5 pieces (idle and A, B, C, and D), except for a STOP operation which is divided into 4 pieces (idle and A, B and C).
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2.7) Data IO Shift Register The Data IO Shift Register contains the data associated with the current transfer. During a read action, data is shifted in from the SDA line. After a byte has been read the contents are copied into the Receive Register. During a write action, the Transmit Register’s contents are copied into the Data IO Shift Register and are then transmitted onto the SDA line.
2.8) Limitations 1) In the above method we have only master mode. There is no slave mode. 2) In the above method we can send/receive only one byte of data. We cannot able to send more then one byte of data during each start signal.
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Chapter 3 Introduction to I2C bus 3.1) Introduction
Figure 3.1: I2C bus applications
I2C is a serial bus interface developed by Philips, originally conceived as a way for parts inside a TV to communicate with a minimum of wires, it has spread and become an industry standard. I2C is an extremely simple protocol for communicating with other chips using just two signal wires. This is interesting to embedded systems engineers, because it is relatively simple to implement I2C in software. The above graphic shows some examples of what can be added to an embedded CPU with just two wires and a few lines of code.
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The I2C bus is a serial bus consisting of two wires, the SCL (clock) line, and the SDA (data) line. Obviously, the data bits are shifted in and out on the SDA line while the SCL line provides the clock so all devices know when to sample the bits in the SDA line. Unlike RS232, there are no fixed baud rates, so the clock does not have to be regular. In the simplest situation, one part is a master, and it can send data to (or receive data from) any slave on the two-wire bus. Each part on the bus has a unique address, so when the master requests a transaction, only one device responds. It is very easy to write a simple software implementation which will allow a CPU to communicate with I2C slave parts, if you don't bother implementing multiple-master arbitration etc. The protocol has more advanced features also. There is a system for having multiple masters on the bus, and advanced addressing to allow more than 127 devices. However, for the simple project, most of the benefit of I2C can be realized by only using the dirtsimple baseline implementation. 3.2) Features of I2C •
Only requires two open collector I/O lines.
•
Software is very simple for baseline implementation - no problem to write your own.
•
Can easily talk to up to 127 devices with those two I/O lines, more if you want to implement more detail.
•
•
•
•
A major industry standard. Parts available from a huge variety of manufacturers. No tight specs on the signal wires, usually just PCB traces or w ires etc. 100 kbps, 400kbps, and 3.4 Meg/sec transfer rates possible. (100kbps is easy) No worries about CPU keeping up - Master controls clock for each bit.
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3.3) I2C bus specification Table 1 Definition of I2C-bus terminology TERM
DESCRIPTION
The device which sends data to the bus Transmitter Receiver Master
The device which receives data from the bus. The device which initiates a transfer, generates clock signals and terminates a transfer.
Slave Multi-master
Arbitration
Synchronization
The device addressed by a master. More than one master can attempt to control the bus at the same time without corrupting the message. Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted Procedure to synchronize the clock signals of two or more devices.
The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually micro-controllers, let’s consider the case of a data transfer between two microcontrollers connected to the I2C bus (see Fig). This highlights the master-slave and receiver-transmitter relationships to be found on the I2C-bus. It should be noted that these relationships are not permanent, but only depend on the direction of data transfer at that time. The transfer of data would proceed as follows:
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Fig.2 Example of an I2C-bus configuration using
two microcontrollers.
1) Suppose microcontroller A wants to send information to microcontroller B: a) Microcontroller A (master), addresses microcontroller B (slave) b) Microcontroller A (master-transmitter), sends data to microcontroller B (slave receiver). c) Microcontroller A terminates the transfer.
2) If microcontroller A wants to receive information from microcontroller B:
a) Microcontroller A (master) addresses microcontroller B (slave) b) Microcontroller A (master- receiver) receives data from microcontroller B (slavetransmitter) c) Microcontroller A terminates the transfer.
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The possibility of connecting more than one microcontroller to the I2C-bus means that more than one master could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event -an arbitration procedure has been developed. This procedure relies on the wired-AND connection of all I2C interfaces to the I2C-bus. If two or more masters try to put information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ will lose the arbitration.
3.4) GENERAL CHARACTERISTICS
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a current-source or pull-up resistor (see Fig.3). When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or opencollector to perform the wired-AND function. Data on the I2C-bus can be transferred at rates of up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. The number of interfaces connected to the bus is solely dependent on the bus capacitance limit of 400 pF. For information on High-speed mode master devices
3.4.1) BIT TRANSFER
Due to the variety of different technology devices (CMOS, NMOS, bipolar) which can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of VDD (see Section 15 for electrical specifications). One clock pulse is generated for ea ch data bit transferred.
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3.4.2) Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.4.3) START and STOP conditions
Within the procedure of the I2C-bus, unique situations arise which are defined as START (S) and STOP (P) conditions . A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition.
START and STOP conditions.
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3.5) Possible data transfer formats 1. Master-transmitter transmits to slave-receiver. The transfer direction is not changed
2. Master reads slave immediately after first byte . At the moment of the first acknowledge, the master- transmitter becomes a master- receiver and the slavereceiver becomes a slave-transmitter. This first acknowledge is still generated by the slave. The STOP condition is generated by the master, which has previously sent a not-acknowledge (A).
3.
Combined format. During a change of direction within a transfer, the START condition and the slave address are both repeated, but with the R/W bit reversed. If a master receiver sends a repeated START condition, it has previously sent a not-acknowledge (A).
Fig A master-transmitter addressing a slave receiver with a 7-bit address. The transfer direction is not changed.
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Fig
A master reads a slave immediately after the first byte.
Fig Combined format
3.6) 7-BIT ADDRESSING
The addressing procedure for the I2C-bus is such that the first byte after the START condition usually determines which slave will be selected by the master. The exception is the ‘general call’ address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. However, devices can be
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made to ignore this address. The second byte of the general call address then defines the action to be taken.
Fig The first byte after the START procedure
3.7) Definition of bits in the first byte
The first seven bits of the first byte make up the slave address (see Fig.14). The eighth bit is the LSB (least significant bit). It determines the direction of the message. A ‘zero’ in the least significant position of the first byte means that the master will write information to a selected slave. A ‘one’ in this position means that the master will read information from the slave. When an address is sent, each device in a system compares the first seven bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slave-receiver or slave-transmitter, depending on the R/W bit.
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CHAPTER 4
APB (ADVANCED PERIPHERAL BUS) 4.1) FUNCTIONAL DESCRIPTION
The APB bus is part of the Advanced Microcontroller Bus Architecture (AMBA) hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The APB bus is used to interface to any peripheral device which are low bandwidth and do not require the high performance of a pipelined bus interface. The APB slave interface acts as a bridge between the APB bus and the peripheral device to which the bus is connected. It receives the APB bus signals and converts them to a form in which is understood by the connected peripheral device.
4.2) APPLICATION OF THE APB INTERFACE
Most common applications of the APB interface are to read and write registers of the connected device. The Peripheral devices connected to the APB bus could be UART, Timer, Keypad, etc.
4.3) FEATURES •
Compliant with AMBA [Rev 2.0] for easy Integration with SOC implementations
•
Supports APB bus for a wide range of frequencies (approximately 100 MHz)
•
Programmable Address and data widths
•
Easy integration to any SOC implementation
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4.4) APB SIGNALS
APB Interface performs the interface functions between UART and APB bus. Allows easy connection of the core to existing APB systems.
Figure 3.1: Input or output signals of APB interface
PCLK (System clock): Internal state machines and the baudrate generator all operate at
this frequency. PRESET_N (Master reset ): When this signal is low, it initializes all registers and
control logic. PSELECT: The UART module is selected if select is equal to one. PENABLE: The UART module is enabled if enable is equal to one.
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4.5) OPERATING STATES The state diagram, shown in Figure can be used to represent the activity of the Peripheral Bus.
Figure 3.2: Operating States of APB interface
The state machine operates through the following states:
IDLE : This is the default state of the APB.
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SETUP : When a transfer is required the bus moves into the SETUP state, where the
appropriate select signal, PSELx, is asserted. The bus only remains in the SETUP state for one clock cycle and always moves to the ACCESS state on the next rising edge of the clock.
ACCESS : The enable signal, PENABLE, is asserted in the ACCESS state. The address,
write, select, and write data signals must remain stable during the transition from the SETUP to ACCESS state. Exit from the ACCESS state is controlled by the PREADY signal from the slave:
If PREADY is held HIGH by the slave then the peripheral bus remains in the ACCESS state.
If PREADY is driven LOW by the slave then the ACCESS state is exited and the bus returns to the IDLE state if no more transfers are required. Alternatively, the bus moves directly to the SETUP state if another transfer follows.
4.6) TIMING DIAGRAMS:
The following diagrams illustrate the timing relationships between various signals during different operations.
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Figure 3.3: Write transfer
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The write transfer starts with the address, write data, write signal and select signal all changing after the rising edge of the clock. The first clock cycle of the transfer is called the SETUP cycle. After the following clock edge the enable signal PENABLE is asserted, and this indicates that the ENABLE cycle is taking place. The address, data and control signals all remain valid throughout the ENABLE cycle. The transfer completes at the end of this cycle. The write transfer starts with the address, write data, write signal and select signal all changing after the rising edge of the clock. The first clock cycle of the transfer is called the SETUP cycle. After the following clock edge the enable signal PENABLE is asserted, and this indicates that the ENABLE cycle is taking place. The address, data and control signals all remain valid throughout the ENABLE cycle. The transfer completes at the end of this cycle.
The enable signal, PENABLE , will be deasserted at the end of the transfer. The select signal will also go LOW, unless the transfer is to be immediately followed by another transfer to the same peripheral.
In order to reduce power consumption the address signal and the write signal will not change after a transfer until the next access occurs.
The protocol only requires a clean transition on the enable signal. It is possible that in the case of back to back transfers the select and write signals may glitch.
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Figure 3.4: Read transfer
The timing of the address, write, select and strobe signals are all the same as for the write transfer. In the case of a read, the slave must provide the data during the ENABLE cycle. The data is sampled on the rising edge of clock at the end of the ENABLE cycle.
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CHAPTER 5 I2C Master/Slave controller with APB interface 5.1) I2C MASTER/SLAVE CONTROLLER BLOCK DIAGRAMME
In our method we have introduced First in First out (FIFO), so that we can send or receive any number of bytes of data to I2C bus, during master mode. The length of data to be sent is stored in the data length register. I2C master interface checks the data length register, according it will number of bytes of data which is equal to data length register. In our method we have used both master mode and slave mode. During master mode the data transfer is initiated by i2c master controller block. I2c master controller block generates the start bit, then it generates address of device on i2c bus, then it generates read/write bit to indicate whether it is read operation or write operation. Then waits for an acknowledge signal. During slave mode the data transfer is initiated by i2c device. Slave block detects the start bit then it detects the address, then it checks whether it is read/write bit to check whether it is read or write operation.
Block diagram representation
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5.2) Functional
Blocks Description:
APB Bridge
The APB interface block is primarily used for programming the registers on the I2C controller and to transmit and receive data from the I2C master/slave devices.
Registers
The operational registers are used to program the controller and also to give the status of the design. The registers are programmed using the APB interface and are used by the I2C controller to control the I2C interface.
Clock Generator
The clock generator contains a counter. The counter is used to generated a divide signal and generate the I2C clock as required by the user by programming the divisor registers.
I2C Transceiver
The transmit and receive logic contains the state machines to receive and send data in the I2C protocol format. It contains shift register which converts parallel data in to serial form during transmit operation. It also serial data parallel form during receive operation.
FIFO
This FIFO is 8 bit wide and 1024 bit deep. It is filled by the APB controller and sent to the external I2C device by the I2C controller during a transmit operation. The same FIFO is filled by the I2C controller and read by the APB controller during a receive operation.
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I2C Master Interface
When APB - I2C IP is programmed as the I2C master interface, the APB controller initiates read and write transfers through command registers and watches the completion of the task by polling the status registers. The amount of data to be transferred or read is predetermined by the APB controller and is programmed in the data length registers. Data to be read or written in the external I2C device is addressed using data port registers. This block throttles the data flow between the I2C interface and the APB controller in master mode.
I2C slave Interface
When the APB - I2C IP is programmed as the I2C slave interface, the APB controller polls the status register to know whether a read or write is happening in the I2C interface. When a read or write is completed the APB controller takes away the data from the FIFO by reading the data length registers and address registers to map the register locations. This block throttles the data flow between the I2C interface and the APB controller in slave mode.
5.3)
Principle of operation
APB-I2C Bridge Controller can be operated in two modes 1) I2C interface as master mode 2) I2C interface as slave mode
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5.3.1) I2C interface as master mode
During I2C master interface mode command registers are programmed by external device on APB bus. I2C device address is written on address register. The data to be send is written on FIFO. Information about data length in written on data length register. APB controller watches the completion of task by polling the status register. I2C interface reads the command register. It acts as master on I2C bus. It initiates the data transfer on I2C bus by sending start bit. It sends the I2C device address and control bit to inform whether it is read or write operation. I2C master interface waits for the acknowledge signal. After receiving acknowledge signal it performs read or write operation. After the data transfer is over it g enerates stop signal.
Register Details
APB register address 000 001 010 011 100 101 110 111
Register name Command register Data port register Divisor register Mode register APB ADDR Data length register I2C status register APB status register
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Register type R/W R/W R/W R/W R/W RO R/W R/W
Command register Bit
description
no 7
Generate start condition
6
Generate stop condition
5
Read from slave
4
Write to slave
3
Acknowledge, when receiver sent ACK
2:
Reserved
1 0
Interrupt acknowledge when set, clears a pending interrupt
Data port register
Data port register is used to store the slave address. I2C master controller reads the DATAPORT register. It places the slave address in I2C protocol format. I2C master controller first generates the start bit, then it generates the slave address in serially, then -48-
it generates R/W bit. If this is bit is 1 then write operation from master to slave takes place. If this bit is 0 read operation takes place.
Divisor register
Divisor register is used to convert the clock signal from 10 MHz to 100 KHz. Clock generator reads the divisor register according it will will divide the clock signal. We switch the different modes of I2C bus ( 100 1 00 KHz or 400 KHz) using this Divisor register.
MODE register
Mode register is used to select Master/Slave mode. The I2C-APB bridge can be operated in one of the two mode. Master or Slave mode is selected depending up on the data present in MODE register.
APB ADDR register
APB ADDR register is used to stored the address of the device on APB bus. During slave mode start bit is detected. After start bit slave address (address of device on APB bus) is detected. Then slave address is stored in APB ADDR register. Later this APB ADDR register is read by APB controller , then APB controller place this address in APB protocol format.
Data length register
Data length register is to store the length of data (in terms of bytes). Master controller reads this data length register. Suppose if data length is 5 then master controller sends 5 bytes of data to I2C bus, after sending send ing 5 bytes of data, it will terminates the data transfer.
I2C status register
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This register is used to check the status of I2C master/slave master/slave block. I2C controller after data transfer it will update the I2C status register. I2c status register is read by APB controller to know the status of I2C Master/slave controller block.
APB status register
APB controller is used to check the status of APB controller. APB controller always updates the APB status register after the completion of data transfer. This register is read by I2C Master/slave controller block to know the status of APB controller.
I2C Master state machine. (Multiple read/write transfer)
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5.3.2) 5.3.2) I2C interface interface as slave slave mode During I2C interface as slave mode, I2C waits for start bit on SDA line. If start bit is recognized it receives the slave address from I2C master device on I2C bus. -51-
It converts the received slave address from serial to parallel from through shift register. It reads control bit to know whether it is read operation or write operation. It stores the slave address in to APB address register. It sends acknowledge signal to I2C master device, and waits for data on SDA line. After receiving data on SDA line it stores it in to FIFO. It stores the length of the data received to data length register.
I2C slave state machine (read or write transfer):
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5.4 ) F EATURES
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I2C Interface
•Compliant with I2C specification Version 2.1 •Supports a simple bi-directional 2-wire bus for efficient for inter-IC control •Programmable as I2C Master mode •Programmable as I2C slave mode •Supports a Clock generation circuitry to derive I2C clock from APB clock •Supports various operational frequencies from 100 KHZ to 400 KHZ APB Interface
•Compliant with AMBA [Rev2.0] for easy integration with SOC implementations •Supports APB bus for varying frequency range from 1 to 95MHZ. •Supports Bus mastering DMA modes. •Device states are read by periodic polling mechanism. •Has 512X 8 FIFO to accelerate the data transfers from and to I2C and APB.
5.5)
Signal Interfaces
I2C Interface PINS PIN NAME SDA_IN SCL_IN SDA_OUT SCL_OUT
Direction Input Input Output Output
5.6)
Pin name PRDATA[7:0] PWDATA [7:0]
Pin Description Serial data line input signal Serial clock line input signal Serial data line output signal Serial clock line output signal
APB INTERFACE PINS:
Direction Output Input
Pin Description Output 8 bit data bus Input 8 bit data bus
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PADDR [7:0] PENABLE PSEL PWRITE P_CLK
Input Input Input
Input 8 bit address bus Input Processor Enable data lines Input Processor select same as chip
Input Input
select Input write enable Input APB processor clock This is also used as a reference clock
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CHAPTER 6 VERIFICATION AND RESULTS 6.1 INTRODUCTION Verification is a very important phase in VLSI. It is achieved by building test benches (or BFMs). The test benches are written as Verilog codes and are used to force the data to the different RTL modules while simulating. Simulation is done by using the software Mentor Graphics QuestaSim. The simulated waveforms are then observed b y forcing different values. The following test benches are written for different modes of o peration. •
Master write operation.
•
Master read operation.
•
Slave write operation.
•
Slave read operation.
For verification to be exhaustive, many cases are to be checked. The different cases are listed and explained in the following section.
6.2 RESULT WAVEFORMS 6.2.1 APB Interface:
APB interface operates through three states first one is idle state during this state select (apb_psel_x_i) and penable (apb_penable_i) is active low. Idle state will go to the next state called setup state ,when select line is active high which selects the UART. Setup state will go to the next state called access state when penable is active high . In access state slave (apb_pready_o) is ready to access data for read and write operations. When write signal is active high then write operation can be performed otherwise read operation can be performed.
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Figure 5.1: Simulation result of APB Interface using VCS (Synopsys).
Figure 5.2: Showing Schematic view of APB Interaface (I / O ports of APB interface) .
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6.2.2 Master write operation
In this mode we are going to write 3 bytes of data to I2C bus. I2C master controller sends start bit followed by slave address (7 bits ), then R/W equal to 1. Then master controller waits for an acknowledge signal from I2C bus, then it reads the byte of data from FIFO , send it to I2C bus bit by bit serially, after 8 bit of data it waits for an acknowledge signal then it sends next byte of data, finally it will send any number bytes of data which is equal to data length register.
Data port register = 000 111 (I2C slave address) Data length register = 3 (Length of data to be sent) Data bytes stored in FIFO = 1001 0011 0011 0011 1100 1100
Figure 5.3: Simulation result of Baud rate generator using VCS (Synopsys).
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6.2.3 Master read operation
This mode is also similar to master mode, but the direction of flow of data is in opposite direction. I2C master controller sends start bit followed by slave address (7 bit) ,followed by R/W bit which is equal to 0. It waits for an acknowledge signal then , it reads a byte of data from I2C bus stores it in FIFO. It reads any number of bytes of data which is equal to Data length register . In the example given below the Master controller reads 3 bytes of data from I2C bus at rate of 100 KHz, and stores all 3 bytes of data in to the FIFO. After completion of data transfer it updates the I2C status register , APB controller always keeps checking the I2C status register. APB controller reads all 3 bytes of data which is stored in FIFO , and send it to the APB bus in in APB protocol format. Slave address =000111,
Data length =2
APB address = 000 1001 (address of device on APB bus which has to red data from I2C bus) Data bytes received serially from I2C bus 0011 1110 1100 0111 Data bus outputs 3e and c7 000 Address bus
Pselect1 is selected 9
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Figure 5.6: Simulation result shows RAM with different data loaded at different instant of time.
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Figure 5.7: Shows Schematic view of Synchronous FIFO .
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5.2.4 ) Slave read operation
During the slave read mode , slave controller detects the start bit from I2C bus, then it receives the 7 bit of data , it stores the data into the APB address register. Then checks for R/W. If R/W is 1, then it receives 8 bit of data from I2C bus. It stores the data in to the FIFO. It updates the I2C status register. APB controller always keeps checking the I2C status register. After the operation of slave controller is over, it reads the APB ADDR register , to that particular address it sends the data from FIFO in APB protocol format.
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Figure 5.8: Simulation result of THRE interrupt using Questasim 6.4b.
5.2.5) Slave write operation Slave write operation is similar to slave read operation. The difference is the direction of flow of
data is in opposite direction. Slave controller detect start bit ,then it receives 7 bit address, then it receives R/W bit 0. It stores the 7 bit address in to APB address register, updates the I2C status register. APB controller always keeps checking for I2C status register. It reads the APB ADDR register, it request for the data in APB protocol format in APB bus. After the data received from the derived address it stores the data in to FIFO. The it updates the APB STATUS register. I2C slave controller always keeps checking for APB status register. I2C slave controller reads the data which is stored in FIFO. Send the data to 2C bus in serially in I2C protocol format.
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Figure 5.9: Simulation result of (RDA) Receiver Data Available Interrupt using Questasim 6.4b.
CHAPTER 7
CONCLUSIONS AND FUTURE SCOPE 7.1 CONCLUSION The I2C master/slave controller with APB bus interface was successfully designed in RTL using verilog is suitable for use in embedded systems and System on Chip (SoC). The verification is considered as the main bottoleneck in the ASIC design flow. The design verification consumes up to 70% of the effort of design cycle. A verilog based tesbenche are developed and simulated using Mentor Graphics Questasim . -64-
I2C master/slave controller can send any number of bytes of data to I2C bus in I2C protocol format. I2C master controller reads the Data length register accordingly it will send many number of bytes of data. By this method efficiency of the processor is increased. If the processor wants to send many number of bytes of data to the same address on I2C bus, by this method we have reduced the time to transfer data to I2C bus. In our method we have used slave mode also. During slave mode slave controller block detects the start bit, performs either read or write operation depending up on the R/W bit. The design is implemented in RTL using Verilog HDL.
7.2 FUTURE SCOPE A few improvements which can be implemented in the current design in the future are listed below. 1. In our method only 7 bit addressing format is used. We can make it to operate in 10 bit addressing format.
2. The FIFO depth can be increased to 1024-byte so that we can send maximum of 1024 bytes of data to the device on I2C bus.
3. We can make clock generator to work in different modes such as standard mode, Fast mode, and high- speed mode.
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REFERENCES 1. “Implementation of an On-Chip Bus Bridge between Heterogeneous Buses with Different Clock Frequencies” by Sangik Choi and Shinwook Kang, Digital Media R&D center, Samsung Electronics Co., Ltd, IEEE-2005. 2. “AMBA™ Specification” (Rev 2.0),ARM Limited 1999, http://www.arm.com. 3. “AMBA Based Multiprocessor System”, Youngwoo Kim, Kyoung Park, and Myungioon Kim, Electronics and Telecommunications Research Institute,IEEE-2003 . 4. “Design of AMBA TM Wrappers for Multiple-Clock Operations” by Nam-Joon Kim, HyukJae Lee Seoul National University, School of Electrical Engineering & Computer Science , IEEE- 2004. -66-
5.
“Configurable UART with APB interface”, DCD-Digital Core design, 2009.
6.
“AMBA: Enabling reusable on-chip Designs” by David Flynn, IEEE-1997.
7.
“SC16C554/554D Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder”, Philips Electronics N.V. 2003.
8.
“The High-Performance UART Product Family” , Texas Instruments, 2008.
9.
“SC28L194 Quad UART for 3.3 V and 5 V supply voltage”, Product data sheet, Philips semiconductor,Aug-2006.
10. “Quad universal asynchronous receiver/transmitter (QUART)”, Product data sheet, Philips semiconductors, Aug 09-2006. 11. “The Design of High Speed UART” By J. Norhuzaimin and H.H Maimun Department Of Electronic, Faculty Of Engineering, University Malaysia Sarawak, IEEE-2005. 12. “Introduction to UART Design “ by Sakir Sezer School of Electrical and Electronic Engineering Q ueen’s University of Belfast. 13. “IPC- UART-APB-APB 16450/16550 Compatible UART Core” CAST, Inc. www.castinc.com
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APPENDIX-A
SDC(Synopsys design constraints) FILE for Quad UART: design_vision> gui_start set search_path "/tools/library/jazz130/A13_d03/synopsys/db/ss/" set target_library "cscd_ss.db" set link_library "* cscd_ss.db" read_verilog ~/synthesis/rtl/verilog_APB/quad_channel_uart.v link compile current_design quad_uart current_design set_max_fanout 80 [current_design] set_driving_cell -lib_cell cdfd0 -library cscd_ss [all_inputs] set_load -pin_load 0.05 [all_outputs ] create_clock [get_ports apb_pclk_i] -name apb_pclk_i -period 2.2 {0 1} set_clock_latency 0.7 [get_clocks apb_pclk_i] set_clock_latency -source 0.3 [get_clocks apb_pclk_i]
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-waveform
set_clock_uncertainty -setup 0.05 [get_clocks apb_pclk_i] set_clock_transition -rise 1.5 [get_clocks apb_pclk_i] set_clock_transition -fall 1.5 [get_clocks apb_pclk_i] set_input_delay -clock apb_pclk_i 0.3 -network_latency_included -source_latency_included [all_inputs] set_output_delay -clock apb_pclk_i 0.3 -network_latency_included -source_latency_included [all_outputs] link compile report_area set_max_area 0 set_max_capacitance 2 quad_uart set_max_transition 2 quad_uart set_drive 2 [all_inputs ] link compile report_area check_design report_design report_constraints **************************************** Report : design Design : quad_uart Version: C-2009.06-SP2 Date : Tue Jun 22 17:49:38 2010 **************************************** Design allows ideal nets on clock nets. Library(s) Used: cscd_ss (File: /tools/library/jazz130/A13_d03/synopsys/db/ss/cscd_ss.db) Local Link Library: {cscd_ss.db} Operating Conditions: Operating Condition Name : WORST Library : cscd_ss Process : 1.00 Temperature : 125.00 Voltage : 1.08 Interconnect Model : worst_case_tree Wire Loading Model: Selected automatically from the total cell area. Name : c13_small Location : cscd_ss Resistance : 0 Capacitance : 0.82 Area : 0 Slope : 0.105 Fanout Length Points Average Cap Std Deviation -------------------------------------------------------------1 0.00
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2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 40 50 60 70 80 90 100 400 1000 2000 3000 5000
0.01 0.01 0.02 0.03 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.12 0.14 0.16 0.17 0.19 0.22 0.25 0.40 0.55 0.70 0.87 1.05 1.25 1.50 1.75 6.50 15.00 27.00 40.00 60.00
**************************************** Report : area Design : quad_uart Version: C-2009.06-SP2 Date : Tue Jun 22 17:48:40 2010 **************************************** Library(s) Used: cscd_ss (File: /tools/library/jazz130/A13_d03/synopsys/db/ss/cscd_ss.db) Number Number Number Number
of of of of
ports: nets: cells: references:
41 125 62 23
Combinational area: Noncombinational area: Net Interconnect area:
50132.736323 36048.385098 undefined (Wire load has zero net area)
Total cell area: Total area:
86181.121420 undefined
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