lp_trend08_godwin

Low Power Trends and Methodology Godwin Maben

Predictable Success

Agenda • Introduction • Summary of Low Power Techniques  Designer’s Arsenal

• Details on each Technique  Technology Highlights  Advantages/Trade-Offs  Challenges

• Synopsys Low Power Flow Summary

© 2008 Synopsys, Inc. (2)

Predictable Success

Reasons for Low Power Demand

Source: Intel

It’s all about battery life Leakage Power Dynamic Power

250nm180nm130nm 90nm 65nm 45nm © 2008 Synopsys, Inc. (3)

Predictable Success

Reasons for Low Power Demand 60%

Technology Driven

Application Driven

75%

40% 48%

50%

30%

41%

26% 21% 20%

22%

25%

10%

13%

1%

10%

1%

1%

0%

0% Consumer

Communications 2004

2006

Computer/ Peripherals 2007

Other

>250nm 250nm

180nm Last

130nm

90nm Current

65nm

45nm

32nm

Next

Source: SNUG 2007 © 2008 Synopsys, Inc. (4)

Predictable Success

Summary of Low Power Techniques (Designer’s Arsenal)


Predictable Success

Factors Governing Power t



E  ( VDD I leak  CV 2 DD fc)dt 0

Total Power Total Power Dissipation Dissipation

t

 VDD I leak dt 0

Static Power Static Power Dissipation Dissipation

Minimize Ileak by:

DynamicPower Power Dynamic Dissipation Dissipation

Ileak

t

 CV

2

DD

f c dt

0

Minimize Iswitch by:

Iswitch

 Reducing operating voltage

 Reducing operating voltage

 Less switching cap

 Fewer leaking transistors

 Less switching activity


Predictable Success

Basic Low Power Techniques Summary Clock Gating

Q

D

FF

16 bit

64 bit

Ripple

90

366

CLA

100

405

Carry Skip

108

437

Carry Select

161

711

Carry Save

218

1323

EN LT

a b c b d

ICG

a c f

b c d

Leakage Current

CLK

Multi-Threshold Low VTH Nominal VTH High VTH Delay


Predictable Success

Advanced Low Power Techniques Summary SLEEP Virtual VDD

1.0V 0.7V 0.8V

Virtual VSS nSLEEP

Power Gating

Multi-Voltage (MV)

VDDB

A A

Z

Z

VSSB

Non minimum size gate lengths

VTCMOS

Stack Effect


Predictable Success

Details on each Technique • Clock Gating  Basic Understanding  Advantages  Concerns in the flow


Predictable Success

Understanding Clock Gating

D

EN

FF

FF

Q

D

Q

FF EN LT

CLK

CLK

ICG


Predictable Success

Clock Gating Flow Challenges • Enable Timing • Insertion delay increase  Impact on OCV

• Peak Power during ON/OFF of clock  IR drop as well

• Verification Impact


Predictable Success

Managing Enable Timing


Predictable Success

Clock Gating Impact on Verification • RTL functional Simulation  None

• Gate level Simulation

Reset “0/1”

Q

D

D

FF

FF

EN “X” LT

CLK “0/1”

ICG


Predictable Success

Details on each Technique • Multi-Threshold Leakage Optimization  Basic Understanding  Advantages  Concerns in the flow


Predictable Success

Understanding Multi Threshold

• Multiple Threshold Cells Vdd 0.9v

Vdd 0.9v

Vth 0.22v

Vth 0.3v

16ps

10ps


Predictable Success

Multi-Threshold Flow Challenges

-ve slack

+ve slack

•

Looking at a different view of the problem, optimizations push towards zero-slack

•

High-Vt cells tend to be weaker and can be more susceptible to variability

Slack

Power critical range


Predictable Success

Multi-Threshold Flow Challenges • Implant Spacing Violations

• Min Width Violations • Chip Finishing requires Proper filler Cell Insertion


Predictable Success

Details on each Technique • Power Gating  Basic Understanding  Advantages  Concerns in the flow


Predictable Success

Understanding Power Gating VDDG

Switch Fabric

Switch Fabric

Gating Control

ISO Power Gated Block

Always On Block

Switch Fabric

VSS © 2008 Synopsys, Inc. (19)

Predictable Success

Architectural Tradeoffs

• Amount of leakage power savings that is possible

• Entry and exit time penalties incurred • Energy dissipated entering and leaving such leakage saving modes


Predictable Success

Activity Profile for Power Gating

SLEEP

WAKE

Power

Dynamic Power Activity “X”

SLEEP

Dynamic Power Activity “Y”

Leakage Power Activity “X” Leakage Power Power Gated

Leakage Power Activity “Y”

WAKE

SLEEP

Dynamic Power Activity “Z”

Leakage Power Activity “Z” Leakage Power Power Gated

TIME


Predictable Success

Realistic Profile for Power Gating SLEEP

WAKE

Power

Dynamic Power Activity “X”

Leakage Power Activity “X” Leakage Power Power Gated

SLEEP

WAKE

SLEEP

Dynamic Power Activity “Y”

Dynamic Power Activity “Z”

Leakage Power Activity “Y”

Leakage Power Activity “Z” Leakage Power Power Gated

TIME


Predictable Success

Architectural Tradeoffs

• Gate VDD or VSS?

• Retention Mechanism


Predictable Success

Power Gating Flow Challenges

• Functional Verification

Clock wiggling while power-gated Rail with Standby value (0.6 volts)

Rail ramp-down

Rail ramp-up Restore RETENTION Rail

Island Power-gated (Z) © 2008 Synopsys, Inc. (24)

Save

Registers RESTORED Predictable Success

Power Gating Sequence/Coverage

Voltage States: 8/8 Logical States: 2/3

Is the wakeup/shutdown sequence correct ?


Predictable Success

Power Gating Flow Challenges

• Logic Synthesis VDD OFF GATE

VDD

X

EN

ISO

on/off

VDD_BACKUP

Active Logic CP D

VSS save

Active Logic

Insert Isolation Cell

restore

SI SE LD RS

RR

Q

Shut Down Insert Retention Register Hookup Retention Register


Predictable Success

Power Planning the Switches Resistance

# PWR SWITCHE S

X_INC R

Y_INC R

LIB_CEL_NAME

0.4

650.0

328.0

26.3

3.6

SXXZZYX8L

42.7

0.3

1300.0

328.0

26.3

3.6

SXXZZYX4L

43.6

0.2

650.0

164.0

26.3

7.2

SXXZZYX8L

53.2

0.2

2600.0

328.0

26.3

3.6

SXXZZYX2L

55.3

0.2

1300.0

164.0

26.3

7.2

SXXZZYX4L

72.5

0.2

650.0

164.0

52.6

3.6

SXXZZYX8L

MAXIR (mV)

Area (%)

37.2

53.2

39.9


Predictable Success

IR-Drop Management Limit the voltage drop across the switch

Turn On All Switches at Once NSLEEP

VDD

VDD

VVDD

NSLEEP

IN

NOT_IN

VSS

Sequentially Turn On Switches NSLEEP

Volts

VVDD Normal - Power-on

Power-up

t0

t1

t2 VDD

Time

T

T-

Power-up

Normal - Power-on VVDD

T+


Predictable Success

Details on each Technique • Multi-Voltage  Basic Understanding  Advantages  Concerns in the flow


Predictable Success

Multi-Voltage Design Style • Static Voltage • Multi-Level Voltage Scaling • Dynamic Voltage and Frequency Scaling • Adaptive Voltage Scaling Voltage Island

Voltage Island

A

Voltage Island

B 1.0 V, 250 MHz

Voltage Island

C 1.5 V, 500 MHz

B

A Programmable

1.2 V, 350 MHz

Voltage Island

Voltage Regulators

Mode Control

Voltage Island Monitor

A

Mode Control

Voltage Island Monitor

B

Voltage Regulators

Voltage Island

Voltage Island

C

Monitor

C


Predictable Success

Understanding Multi-Voltage/Scaling • Avoid completing tasks early – energy is wasted • Use only enough energy required to complete task in time

Reduce Voltage

Voltage

Reduce Voltage

Reduce Voltage

Energy Energy Saved Energy Run Task in Available Time

Run Task Slow as Possible Time

Task 1

Idle

Task 2

Task 3


Predictable Success

Voltage Scaling Facts • Voltage/Frequency are not changed at runtime

direction based on

 Wait till Voltage/Frequency are locked

0.76V

CU when Target Control  Voltage/Frequency changed in aReached specific Voltage Unit(CU) requests VCU to “amount of change” the ramp up Voltage

1.08V

0V

VCU Interrupts  Change of V/F is defined either through s/w or h/w

CU requests VCU to ramp down voltage and reprograms clock generator to lower Frequency

CU programs clock

 Designs at run time will operate on locked Frequency/Voltage generator to maximum Frequency

• Identify the various operating voltages under which •

blocks will be operating at any point of time Do we have libraries characterized at these V points?


Predictable Success

Voltage Scaling Flow Challenges • Accurately represent effects of dynamic change in voltage values during simulation

Vｄｓｔ 1.0V Logic1

Vｓｒｃ

VIH

0.6V X

VIL Logic0

0.0V

Vsrc

1.0v 0.6v 0.0v

When Vsrc is between VIH And VIL propagate “X”

SIM Output

Hi

X

Z


Predictable Success

Voltage Scaling Flow Challenges

• Synthesis

 Multi-Mode Optimization  Optimal Voltage for Timing/Area/Power Optimization  Level Shifter Optimization based on Mode

• Power Planning  Optimal Power Grid

• Choose the appropriate Power Numbers


Predictable Success

Voltage Scaling Flow Challenges • Placement, CTS and Route  Minimize Skew  MCMM

 Placement of Level Shifters  Temperature Inversion

3000 2000 1000 0

VDDMax VDDMin VDDMax 3.5 3.9 4.1 4.4 4.7

Large Skew Across Domains # Flops

# Flops

Reduced Skew Across Domains

3000 2000 1000 0 3.5 3.8 3.9 4 4.2 4.4 4.5


Predictable Success

Voltage Scaling Timing Challenges • Functional or Performance Failures VDD=1.0

VDD=1.0

Set-up Time Met

VDD=1.0

VDD=1.0

D CLK Q

D

CLK

VDD=1.0

Q

D

CLK

DFF

DFF CLK Q

D

Combinatorial

CLK

DFF

D

VDD=1.0

VDD=1.0

Q DFF


Predictable Success

Voltage Scaling Timing Challenges • Functional or Performance Failures VDD0.95

VDD=1.2

VDD=0.91

VDD=0.99

Set-up Time Failure D CLK Q

D

CLK

Q

D

VDD=1.0

CLK

DFF

DFF CLK Q

D

Combinatorial

CLK

DFF

D VDD=0.99

VDD=0.98

Q DFF


Predictable Success

Details on each Technique • Back Biasing  Basic Understanding  Advantages  Concerns in the flow


Predictable Success

Understanding Biasing

Shut-Down

Wake-Up

Short Stop

Long Stop

Body Bias (VTCMOS)

MTCMOS

Reduced Leakage

Zero Leakage


Predictable Success

Reducing Leakage using Well Bias Gate

FILLBIAS Connect N-Well to VDD

Source

Drain

n+

n+

VDD

VNW

ID p-well

VPW

Connect P-Well to VSS – 0.3V

VPW

VSS

• When VPW < Source  Vth increases

 ID decreases

 Leakage

decreases

Drain

VPW

Gate

I D

Source


Predictable Success

Well Biasing Flow Challenges • Impact on Area due to extra Pick-Up cells • Multi-Corner Analysis required for Sign-Off  VBB = 1V, VBB = 2V…etc

• Sleep to Transition Power Overhead • LVS complexity • Well RC extraction


Predictable Success

Power Savings Data Technique Used

Technology

% Leakage Savings

% Total Power Savings

Clock gating

90nm

NA

57%

Multi-Vt

90nm

31%

NA

Power Gating

130nm

25X

13x

Power Gating

65nm

2x

NA

DVFS

45nm

98% during Standby

NA


Predictable Success

Thoughts on Efficient Leakage Power Management

Predictable Success

Efficient Leakage Power Management VDD

VDD

VDD

VSS

VSS

VVSS

VIRTUAL_VSS Source:IBM

Gate Voltage Gate Voltage

Source:IBM


Predictable Success

Multiple Power Mode Implementation

VDD

VDD

VDD

VSS

VSS

VVSS

S0

S1

S2

1

0

0

Snore

0

1

0

Dream

0

0

1

Sleep

0

1

1

Active

VIRTUAL_VSS

Gate Voltage

S0

S1

S2

Voltage Generator

Source:I BM


Predictable Success

Activity Profile of Multiple Sleep Modes

Shut-Down

Sleep

Wake-Up

Dream Dream

Snore

Active


Predictable Success

Recycle Energy - Hybrid Car

Motor Generator

Battery


Predictable Success


Motor Generator

Battery


Predictable Success


Motor Generator

Battery


Predictable Success


Motor Generator

Battery


Predictable Success

Recycle Leakage VDD

Full Chip Standard Cell Area

GND © 2008 Synopsys, Inc. (51)

Predictable Success

Recycle Leakage VDD


TEMP_GND

Charge Collector


Predictable Success

Recycle Leakage VDD


VDD_SPARE

TEMP_GND

Charge Collector


Predictable Success

Where Best to Manage Power and How? Architectural Changes Re-architect vectors

RTL

Simulation

TB

Synthesis VCD

Vector Vector Analysis

Re-architect Design

No

Good?

Yes

Power Analysis No

Power Good

Yes

Place and Route

Parasitic Extraction

Sign-Off Analysis


Predictable Success

Synopsys Low Power Flow Summary


Predictable Success

Predictable Success


Predictable Success

lp_trend08_godwin

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