LOGIC DESIGNING AND SWITCHING THEORY BOOK

Digital Fundamentals


DIGITAL U

FUNDAMENTALS U

COPYRIGHT © No part of this book may be reproduced or transmitted in any form or by any means, electronic or mechanical, without permission in writing from the authors and publishers.

(FIRST EDITION) Edition

For B-TECH &Engineering Students By Engr. Waqas Naeem

EDITION … 2008 PRICE … Rs. 175/-

BS Computer Engg. (SSUET) ME C&SP (UIT)

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PREFACE U

TABLE OF CONTENTS U

U

FIRST EDITION The book has been designed for B-Tech & Engineering students of the Universities & Institutes of Pakistan. It covers the specific material required to have a basic knowledge of Logic Designing & Theory. The author has made an attempt to present the material in a simple, clear and straightforward manner. Exercises are given at the end of each section. Students are urged to grapple with these exercises for acquiring solid understanding and insight of the subject. I wish to express my infinite gratitude to my family members who encourages me to achieve this valuable target. I am responsible for the mistakes and misprints that might have been left unnoticed. Thanks are also due to Mr. Riaz Ahmed (HOD Tech. IIHE) who took pains for the publication of this book. Suggestions for further improvements will be gratefully acknowledged. KARACHI

AUTHOR

JUNE, 2008

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TOPIC

PAGE#

S# 1

Number Systems

7 –17

1.1 1.2 1.2.1 1.2.2 1.2.3 1.2.4

Types Conversion between numeral systems Decimal Hexa-Decimal Octal Practice

7 7 7 11 13 16

2

Binary Arithmetic

18—30

2.1 2.2 2.3 2.4 2.5 2.6

Addition Subtraction Multiplication Division Boolean Algebra Practice

18 20 20 21 23 30

3

Logic Gates

31—37

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

AND Gate OR Gate NOT Gate NAND Gate NOR Gate XOR Gate XNOR Gate Summary Truth Table

32 32 33 34 34 35 36 37

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4

Combinations of Logic Gates

38—44

4.1 4.2 4.3 4.3.1 4.4 4.5

Function of Combination of Logic Gates Substitution of Alternate Gates Alternate Gate Building NOR/NAND Gates NAND Gate Equivalent Examples Practice

38 39 40 41 42 44

5

Circuit, Expression, Truth Table & Conditions

45—52

5.1 5.2 5.3 5.4 5.5

Gates Boolean Expression Representations Boolean Expression Truth Table Circuit Building with Conditions Practice

45 45 48 49 52

6

Adder

53—54

6.1 6.2

Half Adder Full Adder

53 54

7

Karnaugh Map

55—63

7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8

Introduction K-Map Representation Minimization Using K-Map Grouping Minterms Folding Groups Incompletely Specified Function Populating Maps Using 0’s versus 1’s Practice

55 55 57 59 60 65 67 69

8

Latches

70—78

8.1

RS NOR

70

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8.2 8.3 8.4 8.5

RS NAND JK Flip Flop Data Latch Toggle Latch

72 74 76 77

9

MUX & DE-MUX

79—81

9.1 9.2

MUX DE-MUX

79 80

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For example, 11810, in binary, are: B

1. NUMBER SYSTEMS U

B

U

Operation Remainder

1.1 Types

118 ÷ 2 = 59

0

There are four (4) types of number systems used in computer systems to interpret data in different modes, listed below:

59 ÷ 2 = 29

1

29 ÷ 2 = 14

1

14 ÷ 2 = 7

0

1.2 Conversion to and from other numeral systems

7÷2=3

1

1.2.1 Decimal

3÷2=1

1

1÷2=0

1

T

1. 2. 3. 4.

Binary Octal Decimal Hexadecimal

Æ Æ Æ Æ

0&1 0,1,2,3,4,5,6 & 7 0,1,2,3,4,5,6,7,8 & 9 0,1,2,3,4,5,6,7,8,9,A,B,C, D, E & F

To convert from a base-10 integer numeral to its base-2 (binary) equivalent, the number is divided by two, and the remainder is the least-significant bit. The (integer) result is again divided by two; its remainder is the next most significant bit. This process repeats until the result of further division becomes zero.

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Reading the sequence of remainders from the bottom up gives the binary numeral 11101102. T

B

TB

This method works for conversion from any base, but there are better methods for bases which are powers of two, such as octal and hexadecimal given below. To convert from base-2 to base-10 is the reverse algorithm. Starting from the left, double the result and add the next digit until there are no more. For example to convert 1100101011012 to decimal: B

Result

B

Remaining digits 110010101101

0 0×2+1=1

10010101101

1×2+1=3

0010101101

3×2+0=6

010101101

12 × 2 + 1 = 25

0101101

25 × 2 + 0 = 50

101101

50 × 2 + 1 = 101

01101

101 × 2 + 0 = 202

1101

202 × 2 + 1 = 405

101

405 × 2 + 1 = 811

01

811 × 2 + 0 = 1622

1

1622 × 2 + 1 = 3245 The result is 324510. B

6 × 2 + 0 = 12

B

10101101

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1.2.2 Hexadecimal Binary may be converted to and from hexadecimal somewhat more easily. This is due to the fact that the radix of the hexadecimal system (16) is a power of the radix of the binary system (2). More specifically, 16 = 24, so it takes four digits of binary to represent one digit of hexadecimal. P

The following table shows each hexadecimal digit along with the equivalent decimal value and four-digit binary sequence:

Hexa-Decimal 0 1 2 3 4 5 6 7 8 9 A B C

Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12

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Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100

D E F

13 14 15

1101 1110 1111

P

To convert a hexadecimal number into its binary equivalent, simply substitute the corresponding binary digits: 3A16 = 0011 10102 E716 = 1110 01112 B

B

B

B

B

B

B

B

To convert a binary number into its hexadecimal equivalent, divide it into groups of four bits. If the number of bits isn't a multiple of four, simply insert extra 0 bits at the left (called padding). For example: 10100102 = 0101 0010 grouped with padding = 5216 110111012 = 1101 1101 grouped = DD16 B

B

B

B

B

B

B

B

To convert a hexadecimal number into its decimal equivalent, multiply the decimal equivalent of each hexadecimal digit by the corresponding power of 16 and add the resulting values:

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C0E716 = (12 × 163) + (0 × 162) + (14 × 161) + (7 × 160) = (12 × 4096) + (0 × 256) + (14 × 16) + (7 × 1) = 49,38310 B

P

B

P

P

P

P

P

P

P

B

3

011

4

100

5

101

6

110

7

111

B

1.2.3 Octal Binary is also easily converted to the octal numeral system, since octal uses a radix of 8, which is a power of two (namely, 23, so it takes exactly three binary digits to represent an octal digit). The correspondence between octal and binary numerals is the same as for the first eight digits of hexadecimal in the table above. Binary 000 is equivalent to the octal digit 0, binary 111 is equivalent to octal 7, and so on. P

P

Converting from octal to binary proceeds in the same fashion as it does for hexadecimal:

Octal Binary

658 = 110 1012 B

0

000

1

001

B

B

178 = 001 1112 B

B

B

B

B

And from binary to octal: 1011002 = 101 1002 (grouped) = 548 B

2

010

B

B

B

B

B

100112 = 010 0112 (grouped with padding) = 238 B

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B

B

B

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B

B



And from octal to decimal:

Practice U

1

658 = (6 × 8 ) + (5 × 8 ) = (6 × 8) + (5 × 1) = 5310 B

B

P

P

P

P

B

2

1

0

1278 = (1 × 8 ) + (2 × 8 ) + (7 × 8 ) = (1 × 64) + B

B

U

0

P

P

P

(2 × 8) + (7 × 1) = 8710 B

B

P

P

P

B

1. Conversion between Base-2 & Base-8: • (1001010100001111010101)2 = ( )8 • (101001010100101110101000111)2= ( )8 • (7361421)8 = ( )2 • (276314)8 = ( )2 B

B

2. Conversion between Base-2 & Basae-10: • (111000101010)2 = ( )10 • (1010000111101)2 = ( )10 • (293)10 = ( )2 • (352)10 = ( )2 3. Conversion between Base-2 & Base-16: • (101000010101010101111010101110100 0)2 = ( )16 • (101010010101010000011110101000010 11)2 = ( )16 • (9AE5F)16 = ( )2 • (ACD106E)16 = ( )2 4. Conversion between Base-8 & Base-10: • (4723)8 = ( )10 • (71062)8 = ( )10 • (397)10 = ( )8 • (219)10 = ( )8

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5. Conversion between Base-8 & Base-16: • (2374)8 = ( )16 • (17260)8 = ( )16 • (A912F)16 = ( )8 • (19EDF)16 = ( )8 6. Conversion between Base-10 and Base-16: • (317)10 = ( )16 • (2319)10 = ( )16 • (AFC1)16 = ( )10 • (10DCB)16 = ( )10

2. BINARY ARITHMETIC T

T

Arithmetic in binary is much like arithmetic in other numeral systems. Addition, subtraction, multiplication, and division can be performed on binary numerals.

2.1 Addition

The circuit diagram for a binary half adder, which adds two bits together, producing sum and carry bits. The simplest arithmetic operation in binary is addition. Adding two single-digit binary numbers is relatively simple: 0+0=0 0+1=1 1+0=1 1 + 1 = 10 (carry: 1)

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Adding two "1" values produces the value "10" (spoken as "one-zero"), equivalent to the decimal value 2. This is similar to what happens in decimal when certain singledigit numbers are added together; if the result equals or exceeds the value of the radix (10), the digit to the left is incremented:

and a 1 is written in the bottom row. Proceeding like this gives the final answer 1001002 (36 decimal).

5 + 5 = 10 7 + 9 = 16 This is known as carrying in most numeral systems. When the result of an addition exceeds the value of the radix, the procedure is to "carry the one" to the left, adding it to the next positional value. Carrying works the same way in binary:

B

2.2 Subtraction Subtraction works in much the same way: HTU

UTH

0−0=0 0 − 1 = 1 (with borrow) 1−0=1 1−1=0 One binary numeral can be subtracted from another as follows: * * * * (starred columns are borrowed from) 1101110 − 10111 ---------------=1010111

1 1 1 1 1 (carry) 01101 + 10111 ------------=100100

In this example, two numerals are being added together: 011012 (13 decimal) and 101112 (23 decimal). The top row shows the carry bits used. Starting in the rightmost column, 1 + 1 = 102. The 1 is carried to the left, and the 0 is written at the bottom of the rightmost column. The second column from the right is added: 1 + 0 + 1 = 102 again; the 1 is carried, and 0 is written at the bottom. The third column: 1 + 1 + 1 = 112. This time, a 1 is carried, B

B

B

B

B

B

B

B

B

B

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B

2.3 Multiplication Multiplication in binary is similar to its decimal counterpart. Two numbers A and B can be multiplied by partial products: for each digit in B, the product of that digit in A is calculated and written on a new line, shifted leftward so that its rightmost digit lines up with the digit in B that was used. The sum of all these partial products gives the final result.

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Since there are only two digits in binary, there are only two possible outcomes of each partial multiplication:

1012 goes into the first three digits 1102 of the dividend one time, so a "1" is written on the top line. This result is multiplied by the divisor, and subtracted from the first three digits of the dividend; the next digit (a "1") is included to obtain a new three-digit sequence:

• •

If the digit in B is 0, the partial product is also 0 If the digit in B is 1, the partial product is equal to A

For example, the binary numbers 1011 and 1010 are multiplied as follows:

B

B

B

1 __________ 101 |11011 − 101 011 U

1 0 1 1 (A) × 1 0 1 0 (B) --------0 0 0 0 ← Corresponds to a zero in B + 1 0 1 1 ← Corresponds to a one in B + 0000 +1011 --------------=1101110

U

The procedure is then repeated with the new sequence, continuing until the digits in the dividend have been exhausted: 101 __________ 101 |11011 − 101 011 − 000 111 − 101 10 U

2.4 Division

U

U

Binary division is again similar to its decimal counterpart: __________ 101 |11011

U

U

U

Thus, the quotient of 110112 divided by 1012 is 1012, as shown on the top line, while the remainder, shown on the bottom line, is 102. In decimal, 27 divided by 5 is 5, with a remainder of 2. B

Here, the divisor is 1012, or 5 decimal, while the dividend is 110112, or 27 decimal. The procedure is the same as that of decimal long division; here, the divisor B

B

B

B

B

B

B

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B

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B

B

B

B



2.5 Boolean Algebra • • • • •

Digital computers contain circuits that implement Boolean functions. The simpler we can make a Boolean function, the smaller the circuit that will result. Simpler circuits are cheaper to build, consume less power, and run faster than complex circuits. With this in mind, we always want to reduce our Boolean functions to their simplest form. There are a number of Boolean identities that help us to do this.

3. Our last group of Boolean identities is perhaps the most useful. If you have studied set theory or formal logic, these laws are also familiar to you.

1. Most Boolean identities have an AND (product) form as well as an OR (sum) form. We give our identities using both forms. Our first group is rather intuitive:

Example: We can use Boolean identities to simplify the function: as follows:

2. Our second group of Boolean identities should be familiar to you from your study of algebra:

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2. Simplify: ¬(AB)(¬A + B)(¬B + B) Expression U

Rule(s) Used

U

U

U

¬(AB)(¬A + B)(¬B + B) Original Expression Compliment law, Identity law.

(¬A + ¬B)(¬A + B)

DeMorgan's Law

¬A + (¬B)B

Distributive law. This step uses the fact that or distributes over and. It can look a bit strange since addition does not distribute over multiplication.

¬A

Compliment, Identity.

Here are some examples of Boolean algebra simplifications. Each line gives a form of the expression, and the rule or rules used to derive it from the previous one. Generally, there are several ways to reach the result. As before, I use ¬A to denote not A.

¬(AB)(¬A + B)

1. Simplify: C + ¬(BC) Expression U

U

C + ¬(BC)

Rule(s) Used U

U

Original Expression

C + (¬B + ¬C) DeMorgan's Law. (C + ¬C) + ¬B Commutative, Associative Laws. T + ¬B

Compliment Law.

T

Identity Law.

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3. Simplify: (A + C)(AD + A(¬D)) + AC + C Expression U

Rule(s) Used

U

U

(A + C)(AD + A(¬D)) + AC + C Original Expression

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U



(A + C)A(D + ¬D) + AC + C

Distributive.

(A + C)A + AC + C


A((A + C) + C) + C

Commutative, Distributive.

A(A + C) + C

Associative, Idempotent.

AA + AC + C

Distributive.

A + (A + T)C

Idempotent, Identity, Distributive.

A+C

Identity, twice.

used twice. (¬A)B + (B + A)A + (B + A)(¬B) Compliment, then Identity. (Strictly speaking, we also used the Commutative Law for each of these applications.) (¬A)B + BA + AA + B(¬B) + A(¬B)

Distributive, two places.

(¬A)B + BA + A + A(¬B)

Idempotent (for the A's), then Compliment and Identity to remove B(¬B).

(¬A)B + AB + AT + A(¬B)

Commutative , Identity; setting up for the next step.

(¬A)B + A(B + T + ¬B)

Distributive.

(¬A)B + A

Identity, twice

4. You can also use distribution of or over and starting from A(A+C)+C to reach the same result by another route. 5. Simplify: (¬A)(A + B) + (B + AA)(A + ¬B) Expression U

Rule(s) Used

U

U

U

(¬A)(A + B) + (B + AA)(A + ¬B) Original Expression (¬A)A + (¬A)B + (B + A)A + (B + A)(¬B)

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Idempotent (AA to A), then Distributive,

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(depending how you count it). A + (¬A)B

Commutative .

(A + ¬A)(A + B)

Distributive.

A+B


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Practice U

U

1. Addition • 1011101 + 1110101 = • 1111010101 + 1010000101 = • 00010101 + 1001010100 = • 1011001111 + 10001010100 = 2. Subtraction • 11100111 – 1101 = • 10011101010 – 100011 = • 11010101 – 100110 = • 1011001100 – 1110001 = 3. Multiplication • 10100001 x 11011 = • 11101010 x 1010 = • 11010001 x 100110 = • 111001110 x 11010 = 4. Division • 1110001100 divide by 110 = • 10011110010 divide by 100 = • 110101000111 divide by 101 = • 100011110100 divide by 1001 = 5. Solve the Boolean expression by using different laws: • {A(¬A+C)&(B+¬B)} • [{C(A&¬A) & 0} + {C(A+¬C) & B(¬C)}

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3. LOGIC GATES U

U

Keep in mind that computers work on an electrical flow where a high voltage is considered a 1 and a low voltage is considered a 0. Using these highs and lows, data are represented. Electronic circuits must be designed to manipulate these positive and negative pulses into meaningful logic. Logic gates are the building blocks of digital circuits. Combinations of logic gates form circuits designed with specific tasks in mind. For example, logic gates are combined to form circuits to add binary numbers (adders), set and reset bits of memory (flip flops), multiplex multiple inputs, etc. A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two binary conditions low (0) or high (1), represented by different voltage levels. The logic state of a terminal can, and generally does, change often, as the circuit processes data. In most logic gates, the low state is approximately zero volts (0 V), while the high state is approximately five volts positive (+5 V). There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.

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3.1 AND gate The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in the same way as the logical "and" operator. The following illustration and table show the circuit symbol and logic combinations for an AND gate. (In the symbol, the input terminals are at left and the output terminal is at right.) The output is "true" when both inputs are "true." Otherwise, the output is "false."

Input 1 Input 2 Output 0

0

0

0

1

0

1

0

0

1

1

1

3.2 OR gate The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive "or." The output is "true" if either or both of the inputs are "true." If both inputs are "false," then the output is "false."

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3.4 NAND gate


0

0

0

1

1

1

0

1

1

1

1

The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner of the logical operation "and" followed by negation. The output is "false" if both inputs are "true." Otherwise, the output is "true."

Input 1 Input 2 Output

3.3 Inverter or NOT gate

0

0

1

A logical inverter, sometimes called a NOT gate to differentiate it from other types of electronic inverter devices, has only one input. It reverses the logic state.

0

1

1

1

0

1

1

1

0

3.5 NOR gate Input Output 1

0

0

1

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The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both inputs are "false." Otherwise, the output is "false."

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0

1

0

1

0

1

0

0

1

1

0

3.7 XNOR gate The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. Its output is "true" if the inputs are the same and "false" if the inputs are different.

3.6 XOR gate The XOR (exclusive-OR) gate acts in the same way as the logical "either/or." The output is "true" if either, but not both, of the inputs are "true." The output is "false" if both inputs are "false" or if both inputs are "true." Another way of looking at this circuit is to observe that the output is 1 if the inputs are different, but 0 if the inputs are the same.


0

0

0

1

1

1

0

1

1

1

0

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0

1

0

1

0

1

0

0

1

1

1

Using combinations of logic gates, complex operations can be performed. In theory, there is no limit to the number of gates that can be arrayed together in a single device. But in practice, there is a limit to the number of gates that can be packed into a given physical space. Arrays of logic gates are found in digital integrated circuits (ICs). As IC technology advances, the required physical volume for each individual logic gate decreases and digital devices of the same or smaller size become capable of performing ever-more-complicated operations at ever-increasing speeds.

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4. COMBINATIONS OF LOGIC GATES U

3.8 Summary truth tables The summary truth tables below show the output states for all types of 2-input and 3-input gates. Summary for all 2-input gates Inputs A

B

Output of each gate AND

NAND

OR

NOR

EX-OR

EX-NOR

0

0

0

1

0

1

0

1

0

1

0

1

1

0

1

0

1

0

0

1

1

0

1

0

1

1

1

0

1

0

0

1

Logic gates can be combined to produce more complex functions. They can also be combined to substitute one type of gate for another. For example to produce an Input A Input B Output Q output Q which is true only 0 0 0 when input A is true and 0 1 0 input B is false, as shown in the truth table on the right, 1 0 1 we can combine a NOT gate 1 1 0 and an AND gate like this:

Summary for all 3-input gates Inputs A

B

Output of each gate C

AND

NAND

OR

NOR

0

0

0

0

1

0

1

0

0

1

0

1

1

0

0

1

0

0

1

1

0

0

1

1

0

1

1

0

1

0

0

0

1

1

0

1

0

1

0

1

1

0

1

1

0

0

1

1

0

1

1

1

1

0

1

0

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Q = A AND NOT B

4.1 Working out the function of a combination of gates Truth tables can be used to work out the function of a combination of gates.

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For example the truth table on the right show the intermediate outputs D and E as well as the final output Q for the system shown below.

Inputs

Outputs

A B C D E Q 0

0

0

1

0

1

0

0

1

1

0

1

0

1

0

0

0

0

0

1

1

0

1

1

1

0

0

0

0

0

1

0

1

0

0

0

1

1

0

0

0

0

1

1

1

0

1

1

reduce the number of gate inputs or substitute one type of gate for another.

Reducing the number of inputs The number of inputs to a gate can be reduced by connecting two (or more) inputs together. The diagram shows a 3-input AND gate operating as a 2input AND gate.

Making a NOT gate from a NAND or NOR gate Reducing a NAND or NOR gate to just one input creates a NOT gate. The diagram shows this for a 2-input NAND gate.

D = NOT (A OR B) E = B AND C Q = D OR E = (NOT (A OR B)) OR (B AND C)

4.2 Substituting one type of gate for another Logic gates are available on ICs which usually contain several gates of the same type, for example four 2-input NAND gates or three 3-input NAND gates. This can be wasteful if only a few gates are required unless they are all the same type. To avoid using too many ICs you can

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4.3 Any gate can be built from NAND or NOR gates As well as making a NOT gate, NAND or NOR gates can be combined to create any type of gate! This enables a circuit to be built from just one type of gate, either NAND or NOR. For example an AND gate is a NAND gate then a NOT gate (to undo the inverting function). Note that AND and OR gates cannot be used to create other gates because they lack the inverting (NOT) function.

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To change the type of gate, such as changing OR to AND, you must do three things: • • •

Invert (NOT) each input. Change the gate type (OR to AND, or AND to OR) Invert (NOT) the output.

For example an OR gate can be built from NOTed inputs fed into a NAND (AND + NOT) gate.

OR

NOR

4.3.1 NAND gate equivalents The table below shows the NAND gate equivalents of NOT, AND, OR and NOR gates:

Gate

Equivalent in NAND gates

NOT

4.4 Substituting gates in an example logic system The original system has 3 different gates: NOR, AND and OR. This requires three ICs (one for each type of gate). To re-design this system using NAND gates only begin by replacing each gate with its NAND gate equivalent, as shown in the diagram below.

AND

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Practice U

U

1. What is the NAND equivalent of NOR gate? 2. Construct an equivalent circuit of XOR gate by using NAND gate. 3. Construct an equivalent circuit of Half Adder by using NAND gate. Then simplify the system by deleting adjacent pairs of NOT gates (marked X above). This can be done because the second NOT gate cancels the action of the first. The final system is shown below. It has five NAND gates and requires two ICs (with four gates on each IC). This is better than the original system which required three ICs (one for each type of gate). Substituting NAND (or NOR) gates does not always increase the number of gates, but when it does (as in this example) the increase is usually only one or two gates. The real benefit is reducing the number of ICs required by using just one type of gate.

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5. CIRCUIT, EQUATION, TRUTH TABLE & CONDITIONS U

5.1 GATES REPRESENTATIONS In this topic we will discuss how to represent any circuit in a Boolean expression or vice versa. For this concern, primarily we should know the symbolic representation of each operation i.e. OR, AND etc. Following are the different symbols to represent different gates or operations: 1. AND 2. OR 3. N OT

Æ Æ Æ

“&” “|” “¬”

“x” “+” “’”

“.”

The above mentioned symbols are for the basic gates and we can use it for the derived gates as well by the combination of different symbols.

5.2 BOOLEAN EXPRESSION Now proceeding to the Boolean expression, in the first step we are expressing a simple logic circuit into its Boolean expression.

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Considering the above circuitry, break it into the gate level circuits. What I mean to say that firstly write the expression for the NOR gate, secondly for the AND gate and then finally for an OR gate with results the final output. See below for the specific expression of all gates: NOR AND OR -- (i)

Æ Æ Æ

(A + B)’ (B & C) (D + E) Æ

Æ D Æ E (A+B)’ + (B&C) -

Now we succeeded to achieve the final Boolean equation for the given circuit in Eq. (i). Let’s see even more complex logic circuit to achieve its Boolean expression:

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Here we achieve the final and complex expression of the given logic circuit in Eq. (ii). The point should be reviewed in this expression is [(A+B)’&C’] which should be NOTed two times as per circuit. As we can remind that inverting the original signal two times will give you the original signal again which reflects that two times inversion will not effect the Boolean expression, so it can be eliminated.

5.3 TRUTH TABLE The core motive to design any circuit is to achieve the required pattern of output for any productive use. Output pattern of any circuit is the major concern for any designer.

Boolean expression for each gate is given below: NOR Æ (A + B)’ Æ G AND Æ (C & D) Æ H NAND Æ (E & F)’ Æ I NAND Æ (G & C’)’ Æ J NOR Æ (C’ + H)’ Æ K OR Æ (E’ + I) Æ M NAND Æ (J & K & M & E’)’ Æ {[(A+B)’&C’] & [C’+(C&D)] & [E’+ (E & F)’] & E’}---- (ii)

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Again the same simple circuit (It might be a traditional one …Cheers). Number of possible combination for the given circuit can be calculated by the formula:

(0 or 1). For example we have the following condition to construct a circuit for a specified output:

Number of possible combinations

n

=

2 P

P

Where “n” is the total number of inputs in the circuit which is “3” in this case (A, B & C). Now the total possible combinations for the input are 8 (23) and they are stated below with their respective output: P

S# 1 2 3 4 5 6 7 8

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

P

Q 1 1 0 1 0 0 0 1

5.4 CONDITIONS As stated earlier that the major concern to design any logical circuit is to achieve the specific pattern of output. Here we will discuss how to create a circuit when the conditions of inputs are given to get any particular output

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A=B=1; C=0 O/p = 1 Now we have to precisely examine the input and the logical gates we have to satisfy the condition of input. It is known that the functionality of AND gate is that it provides logical output HIGH when all the inputs are HIGH. Leading with this statement we can satisfy the conditions for input A and B by using AND gate. Now proceeding to the third and last input condition which is LOW, we already knows that out of the previous AND gate will be HIGH in only condition when A and B will be HIGH. Then we should have any gate which checks the output of AND and input C. look into the below circuit:

By verifying the above circuit, we come to know that it also satisfies our remaining condition. Now the final circuit we achieve is:

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Practice U

U

1. Find the circuit on behalf of the following Boolean expressions: a. {(¬A+B) & (B&¬C)} b. [{(A+B+¬C) & (¬B &A)} + (A&¬D)]

And the required truth table is: S# 1 2 3 4 5 6 7 8

A 0 0 0 0 1 1 1 1

c. {(¬C&A) + ¬(¬B&C)} B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

o/p 0 0 0 0 0 0 1 0

You can verify the above truth table by applying all the inputs to the constructed circuit. I suppose that you will the same output.

2. Find the Truth Tables of the circuits constructed in the above part (1). 3. Construct circuits which fulfills the following condition with required output pattern: a. Circuit#1 i. A=B=0 ii. C=1 iii. DE= 00,01 & 11 iv. Output should be high on these conditions. b. Circuit#2 i. A=1 ii. BC=00 & 01 iii. Any one condition a) D= Unspecified b) EF=10 & 11

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6. ADDERS U

6.2 FULL ADDER U

6.1 HALF ADDER The half adder is an example of a simple, functional digital circuit built from two logic gates. The half adder adds to one-bit binary numbers (AB). The output is the sum of the two bits (S) and the carry (C). Note how the same two inputs are directed to two different gates. The inputs to the XOR gate are also the inputs to the AND gate. The input "wires" to the XOR gate are tied to the input wires of the AND gate; thus, when voltage is applied to the A input of the XOR gate, the A input to the AND gate receives the same voltage.

The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is from the carry output from the circuit "above" itself in the cascade. The carry output from the full adder is fed to another full adder "below" itself in the cascade. If you look closely, you'll see the full adder is simply two half adders joined by an OR. Full Adder Circuit

TT Input Output

Half Adder

ABC S C

Truth Table Input Output A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

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0 0 0 0

0

0 0 1 1

0

0 1 0 1

0

0 1 1 0

1

1 0 0 1

0

1 0 1 0

1

1 1 0 0

1

1 1 1 1

1



7. KARNAUGH MAPS U

7.1 Introduction Karnaugh maps provide an alternative technique for representing Boolean functions. For example, consider the Karnaugh map for a 2-input AND gate.

The y column in the truth table shows all the 0 and 1 values associated with the gate's output. Similarly, all of the output values could be entered into the Karnaugh map. However, for reasons of clarity, it is common for only a single set of values to be used, typically the 1s. Similar maps can be constructed for 3-input and 4-input functions. In the case of a 4-input map, the values associated with the c and d inputs must also be ordered as a gray code; that is, ordered in such a way that the values for adjacent rows vary by only a single bit.

Karnaugh map for a 2-input AND gate.

7.2 Representation The Karnaugh map comprises a box for every line in the truth table; the binary values above the boxes are those associated with the a and b inputs. Unlike a truth table, in which the input values typically follow a standard binary sequence (00, 01, 10, 11), the Karnaugh map's input values must be ordered such that the values for adjacent columns vary by only a single bit, for example, 00, 01, 11, and 10. This ordering is known as a gray code, and it is a key factor in the way in which Karnaugh maps work.

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Karnaugh maps for 3-input and 4-input functions.

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7.3 Minimization Using Karnaugh Maps

the map differ by only one bit, any pair of horizontally or vertically adjacent boxes corresponds to minterms that differ by only a single variable. Such pairs of minterms can be grouped together and the variable that differs can be discarded (Figure 4).

Karnaugh maps often prove useful in the simplification and minimization of Boolean functions. Consider an example 3-input function represented as a black box with an associated truth table (Figure 3). (Note that the values assigned to the y output in the truth table were selected randomly, and have no significance beyond the purposes of this example.)

Karnaugh map minimization of example 3-input function.

Example 3-input function.

The equation extracted from the truth table in sum-ofproducts form contains four minterms, one for each of the 1s assigned to the output. Algebraic simplification techniques could be employed to minimize this equation, but this would necessitate every minterm being compared to each of the others which can be somewhat time-consuming.

In the case of the horizontal group, input a is 0 for both boxes, input c is 1 for both boxes, and input b is 0 for one box and 1 for the other. Thus, for this group, changing the value on b does not affect the value of the output. This means that b is redundant and can be discarded from the equation representing this group. Similarly, in the case of the vertical group, input a is 1 for both boxes, input b is 0 for both boxes, and input c is 0 for one box and 1 for the other. Thus, for this group, input c is redundant and can be discarded.

This is where Karnaugh maps enter the game. The 1s assigned to the map's boxes represent the same minterms as the 1s in the truth table's output column; however, as the input values associated with each row and column in

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7.4 Grouping Minterms

7.5 Folding Groups

In the case of a 3-input Karnaugh map, any two horizontally or vertically adjacent minterms, each composed of three variables, can be combined to form a new product term composed of only two variables. Similarly, in the case of a 4-input map, any two adjacent minterms, each composed of four variables, can be combined to form a new product term composed of only three variables. Additionally, the 1s associated with the minterms can be used to form multiple groups. For example, consider a new 3-input function.

In addition to the above methods of groups, we can also make groups by folding the Karnaugh map from horizontal and vertical center lines. In the results of folding, the elements overlaps each others can make relatively larger groups. Now either fold up the corners or center lines (RED) of the map below like it is a napkin to make the four cells physically adjacent.

Karnaugh map minterms can be used to form multiple groups.

The four cells above are a group of four because they all have the Boolean variables B' and D' in common. In other words, B=0 for the four cells, and D=0 for the four

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cells. The other variables (A, B) are 0 in some cases, 1 in other cases with respect to the four corner cells. Thus, these variables (A, B) are not involved with this group of four. This single group comes out of the map as one product term for the simplified result: Out=B'C'

The Boolean expression below has nine p-terms, three of which have three Booleans instead of four. The difference is that while four Boolean variable product terms cover one cell, the three Boolean p-terms cover a pair of cells each.

For the K-map below, roll the top and bottom edges into a cylinder (Horizontal Fold) forming eight adjacent cells.

The above group of eight has one Boolean variable in common: B=0. Therefore, the one group of eight is covered by one p-term: B'. The original eight term Boolean expression simplifies to Out=B'

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The six product terms of four Boolean variables map in the usual manner above as single cells. The three Boolean variable terms (three each) map as cell pairs, which is shown above. Note that we are mapping p-terms into the K-map, not pulling them out at this point. For the simplification, we form two groups of eight. Cells in the corners are shared with both groups. This is fine. In fact, this leads to a better solution than forming a

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group of eight and a group of four without sharing any cells. Final Solution is Out=B'+D'

Often times there are more than one minimum cost solution to a simplification problem. Such is the case illustrated below.

Below we map the unsimplified Boolean expression to the Karnaugh map.

Above, three of the cells form into groups of two cells. A fourth cell cannot be combined with anything, which often happens in "real world" problems. In this case, the Boolean p-term ABCD is unchanged in the simplification process. Result: Out= B'C'D'+A'B'D'+ABCD

Both results above have four product terms of three Boolean variables each. Both are equally valid minimal cost solutions. The difference in the final solution is due to how the cells are grouped as shown above. A minimal cost solution is a valid logic design with the minimum number of gates with the minimum number of inputs. Below we map the unsimplified Boolean equation as usual and form a group of four as a first simplification

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step. It may not be obvious how to pick up the remaining cells.

certain input combinations will never occur, then the value assigned to the output for these combinations is irrelevant. Alternatively, for some input combinations the designer may simply not care about the value on the output. In both cases, the designer can represent the output values associated with the relevant input combinations as question marks in the map.

Pick up three more cells in a group of four, center above. There are still two cells remaining. The minimal cost method to pick up those is to group them with neighboring cells as groups of four as at above right. On a cautionary note, do not attempt to form groups of three. Groupings must be powers of 2 that is, 1, 2, 4, 8...

7.6 Incompletely Specified Functions In certain cases a function may be incompletely specified; that is, the output may be undefined for some of the input combinations. If the designer knows that

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Karnaugh map for an incompletely specified function.

The ? characters indicate don't care states which can be considered to represent either 0 or 1 values at the designer's discretion. It should be noted that many electronics references use X characters to represent don't care states. Unfortunately, this may lead to confusion as design tools such as logic simulators use X characters to represent don't know states. Unless otherwise indicated, this book uses? And X to represent doesn’t care and don't know states respectively.

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7.7 Populating Maps Using 0s Versus 1s

Karnaugh maps are most often used to represent 3-input and 4-input functions. It is possible to create similar maps for 5-input and 6-input functions, but these maps can become unwieldy and difficult to use. The Karnaugh technique is generally not considered to have any application for functions with more than six inputs.

When a Karnaugh map is populated using the 1s assigned to the truth table's output, the resulting Boolean expression is extracted from the map in sum-of-products form. As an alternative, the Karnaugh map can be populated using the 0s assigned to the truth table's output. In this case, groupings of 0's are used to generate expressions in product-of-sums format. Although the sum-of-products and product-of-sums expressions appear to be somewhat different, they do produce identical results. The expressions can be shown to be equivalent using algebraic means, or by constructing truth tables for each expression and comparing the outputs.

Karnaugh maps populated using 0s versus 1s.

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Practice

8. LATCHES U

Find the simplified SOP and POS equations by using the different condition given below: 1. When the outputs are high on the following inputs: 0, 2, 3, 4, 6, 8, A, B & C 2. With the given un-simplified POS equation: O/p= (¬A+¬B+¬C) & (¬A+¬B+C) & (¬A+B+C) & (A+B+C) 3. Truth Table given: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

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D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

O/P 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1

8.1 RS NOR LATCH While most of our demonstration circuits use NAND gates, the same functions can also be performed using NOR gates. A few adjustments must be made to allow for the difference in the logic function, but the logic involved is quite similar. The circuit shown below is a basic NOR latch. The inputs are generally designated "S" and "R" for "Set" and "Reset" respectively. Because the NOR inputs must normally be logic 0 to avoid overriding the latching action, the inputs are not inverted in this circuit. The NOR-based latch circuit is:

For the NOR latch circuit, both inputs should normally be at a logic 0 level. Changing an input to logic 1 level will force that output to logic 0. The same logic 0 will

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also be applied to the second input of the other NOR gate, allowing that output to rise to logic 1 level. This in turn feeds back to the second input of the original gate, forcing its output to remain at logic 0 even after the external input is removed.

confusing when you first try to deal with NORbased circuits.

Applying another logic 1 input to the same gate will have no further effect on this circuit. However, applying logic 1 to the other gate will cause the same reaction in the other direction, thus changing the state of the latch circuit the other way.

S 0 0 1 1

One problem with the basic RS NOR latch is that the input signals actively drive their respective outputs to a logic 0, rather than to a logic 1. Thus, the S input signal is applied to the gate that produces the Q' output, while the R input signal is applied to the gate that produces the Q output. The circuit works fine, but this reversal of inputs can be

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Q n+1 Qn Reset Set Undefined B

B

B

B

8.2 RS NAND Latch T

Note that it is forbidden to have both inputs at logic 1 level at the same time. That state will force both outputs to logic 0, overriding the feedback latching action. In this condition, whichever input goes to logic 0 first will lose control, while the other input (still at logic 1) controls the resulting state of the latch. If both inputs go to logic 0 simultaneously, the result is a "race" condition, and the final state of the latch cannot be determined ahead of time.

R 0 1 0 1

T

In order for a logical circuit to "remember" and retain its logical state even after the controlling input signal(s) have been removed, it is necessary for the circuit to include some form of feedback. We might start with a pair of inverters, each having its input connected to the other's output. The two outputs will always have opposite logic levels. The problem with this is that we don't have any additional inputs that we can use to change the logic states if we want. We can solve this problem by replacing the inverters with NAND or NOR gates, and using the extra input lines to control the circuit. The circuit shown below is a basic NAND latch. The inputs are generally designated "S" and "R" for "Set" and "Reset" respectively. Because the NAND

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inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit.

reaction in the other direction, thus changing the state of the latch circuit the other way.

The outputs of any single-bit latch or memory are traditionally designated Q and Q'. In a commercial latch circuit, either or both of these may be available for use by other circuits. In any case, the circuit itself is:

Note that it is forbidden to have both inputs at a logic 0 level at the same time. That state will force both outputs to logic 1, overriding the feedback latching action. In this condition, whichever input goes to logic 1 first will lose control, while the other input (still at logic 0) controls the resulting state of the latch. If both inputs go to logic 1 simultaneously, the result is a "race" condition, and the final state of the latch cannot be determined ahead of time.

For the NAND latch circuit, both inputs should normally be at logic 1 level. Changing an input to a logic 0 level will force that output to logic 1. The same logic 1 will also be applied to the second input of the other NAND gate, allowing that output to fall to a logic 0 level. This in turn feeds back to the second input of the original gate, forcing its output to remain at logic 1. Applying another logic 0 input to the same gate will have no further effect on this circuit. However, applying logic 0 to the other gate will cause the same

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S 0 0 1 1

Q n+1 Undefined Set Reset Qn

R 0 1 0 1

B

B

B

B

8.3 J-K Flip Flop T

T

To prevent any possibility of a "race" condition occurring when both the S and R inputs are at logic 1 we construct JK Flip Flop. The basic J-K Flip-flop is shown

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J 0 0 1 1

K 0 1 0 1

Q Q’ No change 0 1 1 0 Toggle

8.4 D Latch T

Like the R-S flip-flop the outputs follow the inputs when the Clk is logic, but there are two inputs, traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge. If J and K are both low then no change occurs. If J and K are both high at the clock edge then the output will toggle from one state to the other. It can perform the functions of the R-S Flip-flop and has the advantage that there are no ambiguous states. Due to the extra logic that ensures only one of the R and S inputs is enabled at any time. This prevents possible oscillation, which can occur when both inputs of an RS flip-flop are active at the same time. The truth table of this J-K flip-flop is shown below:

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T

One very useful variation on the RS latch circuit is the Data latch, or D latch as it is generally called. As shown in the logic diagram below, the D latch is constructed by using the inverted S input & the R input signal. The single remaining input is designated "D" to distinguish its operation from other types of latches. It makes no difference that the R input signal is effectively clocked twice, since the CLK signal will either allow the signals to pass both gates or it will not.

In the D latch, when the CLK input is logic 1, the Q output will always reflect the logic level present at the

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D input, no matter how that changes. When the CLK input falls to logic 0, the last state of the D input is trapped and held in the latch, for use by whatever other circuits may need this signal.

Converting a D flip-flop to T operation is quite similar; the Q' output is connected back to the D input.

Because the single D input is also inverted to provide the signal to reset the latch, this latch circuit cannot experience a "race" condition caused by all inputs being at logic 1 simultaneously. Therefore the D latch circuit can be safely used in any circuit. Although the D latch does not have to be made edge triggered for safe operation, there are some applications where an edge-triggered D flip-flop is desirable. This can be accomplished by using a D latch circuit as the master section of an RS flip-flop. Both types are useful, so both are made commercially available.

8.5 T Flip-Flop We've already seen that a JK flip-flop with its J and K inputs connected to a logic 1 will operate as a T flip-flop. Converting an RS flip-flop involves a bit more, as shown below. However, the simple feedback connections shown will ensure that the S and R inputs will always tell the flip-flop to change state at each clock pulse.

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9. MUX & DEMUX U

This circuit can be scaled upward to 3 by 8 MUX (three NOT gates, eight 4-input AND gates, one 8-input OR gate) etc. Multiplexors can be used to control the flow of "data" through the circuits of a computer. U

9.1 Multiplexor (MUX): A multiplexor circuit has N selector lines, 2N input lines and 1 output line. The N selector lines determine which of the 2N input lines is connected to the output. A simple 2 by 4 MUX can be constructed out of two NOT gates, four 3-input AND gate and one 4-input OR gate. Here the configuration of the two control lines c0 and c1 determines which of the four input data lines (data in 0 thru data in 3) is connected to the data out line. For example of c0 = 1 and c1 = 0 then Data In 1 is connected to Data Out through the second And gate. P

P

P

C0

C1

Output

0

0

D0

0

1

D1

1

0

D2

1

1

D3

P

9.2 Decoder: A Decoder is the opposite of a multiplexor (also called a Demultiplexor). Here N control inputs are decoded to connect the single input to one of 2N outputs. If the single data in is set to 1, all other data outs except the one selected are 0. A simple 2 to 4 Decoder can be constructed out of two NOT and four 3-input AND gates. Observe that if c1 equals 1 and c0 equals 0 (10 forms a binary 2), Data In is connected to Data Out 2. Data Out 0, 1, and 3 are all 0. Like multiplexors, decoders can be scaled upward. P

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P


C1

C0

Output

0

0

D0

0

1

D1

1

0

D2

1

1

D3

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LOGIC DESIGNING AND SWITCHING THEORY BOOK

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