Risers, offshore, riser clamps design and analysis
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Descripción: La puerta es el terminal equivalente a la base del BJT (Bipolar Junction Transistor), de cuyo funcionamiento se diferencia, ya que en el FET, el voltaje aplicado entre la puerta y la fuente control...
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Lenormand - Combination
Lenormand - Combination
permutation and combination
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2/1/2012
JFET DC Biasing Topics Topics
JFET DC Biasing EE 21 – Fundamentals of Electronics
) S M A A ( s e d i l S 1 2 E E
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Important relationships… •
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Fixed Bias
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Self-bias
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Voltage-divider bias
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Q-pt (VGS, ID) input graph
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Q-pt (VDS, ID) output graph
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For the FET: gate current I G ≈ 0.
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ID may be assumed equal to I S.
Simplest FET bias circuit. Presence of DC bias in VGG directly manipulates control voltage VGS value.
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DC Analysis of Fixed Bias
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DC Analysis of Fixed Bias
INPUT SIDE: •
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Fixed Bias Circuit
Shockley’s Equation:
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GOAL: To locate the Q-point and plot it in the characteristic curves (input and output) of the FET.
OUTPUT SIDE
Since IG = 0, resistor RG is effectively shorted.
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By KVL, -VGG – VGS = 0, and VGS = -VGG.
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ID is determined by Shockley’s eq’n By KVL: VDS = VDD – IDRD
Note that the value of VGS is fixed, is fixed, hence the name ‘fixed bias’.
* VS = 0 (grounded) Therefore, VDS = VD 5
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Plotting the loadline / output characteristics curve •
Example: Fixed Bias Circuit
From the loadline equation
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VDS = VDD – IDRD
Intercepts of line: •
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When ID = 0, VDS = VDD
Determine the Q-point of the fixed bias circuit and plot in on the Shockley and characteristic curves. Use both mathematical and graphical approach.
When VDS =0, •
ID = VDD/RD.
Take IDSS = 10mA and VP = - 8 Volts.
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Self-bias circuit •
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DC Analysis of Self-bias circuit
Term “self -bias” comes from its independence from a VGG source.
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Again, RG is shorted by the absence of IG. Since ID = IS, KVL on the input ckt yields the ff: V GS
Also known as “common-gate “common-gate configuration”.
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I D RS
Note now that VGS is a function of the drain current ID, which is what we are looking for.
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Mathematical Solution for ID •
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Graphical Solution for ID
Substituting VGS = -IDRS to Shockley’s eqn… eqn…
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Manipulate this to get a quadratic equation in terms of ID. Note that this will yield two possible answers. (How will you know which one to accept?)
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Provides an accurate enough solution for the current ID (as long as the graphs are constructed neatly and properly scaled). This doesn’t mean the graphical solution is ALWAYS better than the mathematical. There are cases that the mathematical solution (though not necessarily the quadratic) is needed to find the answer. 12
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Graphical Solution •
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Completing the solution
Shockley curve is plotted (through 4 points)
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The line VGS = –IDRS is also plotted on the same set of axes.
After solving for ID (using either method) KVL on output circuit: VDS = VDD – ID(RD+RS)
Also, Vs = I DRS VG = 0
The Q-point is the intersection of the two graphs.
VD = VDS + VS = VDD - VRd 13
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Example: Self-bias circuit •
Voltage Divider Bias Circuit
For the self-bias circuit, determine:
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a. VGSQ
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b. IDQ (2 methods) c. VDS
Similar to the BJT voltage divider Since IG = 0, then R1 and R2 are in series, and
d. VS e. VG f.
VD
IDSS = 8mA, VP = -6 V.
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Graphical Solution
DC Analysis of voltage divider bias •
KVL (lower loop) gives us
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VG – VGS – VRs = 0 VGS = VG – VRS since IS = ID, •
VRs = IDRS And
Mathematical solution for ID is too tedious due to the line’s equation Therefore we use graphical solution (similar to self bias)
VGS = VG – IDRS
(variable as well!)
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Example: Voltage Divider Bias For the voltage divider circuit, solve for a. IDQ and VGSQ b. VD c. VS d. VDS e. VDG FET Cha racteristics: racteristics: IDSS = 8mA VP = - 4 V
Combination Networks •
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First approach the device that will provide a terminal voltage or current level BJT and FET analysis are carried over (“creeping” solution)
